Boot log: qemu_arm64-virt-gicv3
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 4
- Errors: 0
1 10:05:07.986438 lava-dispatcher, installed at version: 2023.01
2 10:05:07.986665 start: 0 validate
3 10:05:07.986791 Start time: 2023-06-10 10:05:07.986784+00:00 (UTC)
4 10:05:07.987978 Validating that http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image exists
5 10:05:08.331247 Validating that http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz exists
6 10:05:08.502326 cmd: ['docker', 'pull', 'kernelci/qemu']
7 10:05:08.502584 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
8 10:05:08.670193 >> Using default tag: latest
9 10:05:09.760970 >> latest: Pulling from kernelci/qemu
10 10:05:09.792749 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
11 10:05:09.793075 >> Status: Image is up to date for kernelci/qemu:latest
12 10:05:09.826272 >> docker.io/kernelci/qemu:latest
13 10:05:09.829592 Returned 0 in 1 seconds
14 10:05:09.967372 cmd: ['docker', 'run', '--rm', '--init', 'kernelci/qemu', 'qemu-system-aarch64', '--version']
15 10:05:09.967746 Calling: 'nice' 'docker' 'run' '--rm' '--init' 'kernelci/qemu' 'qemu-system-aarch64' '--version'
16 10:05:13.428638 >> QEMU emulator version 7.2.2 (Debian 1:7.2+dfsg-7~bpo11+1)
17 10:05:13.429006 >> Copyright (c) 2003-2022 Fabrice Bellard and the QEMU Project developers
18 10:05:14.616590 Returned 0 in 4 seconds
19 10:05:14.717948 validate duration: 6.73
21 10:05:14.718639 start: 1 deployimages (timeout 00:03:00) [common]
22 10:05:14.718856 start: 1.1 lava-overlay (timeout 00:03:00) [common]
23 10:05:14.719368 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2
24 10:05:14.719660 makedir: /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin
25 10:05:14.719899 makedir: /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/tests
26 10:05:14.720135 makedir: /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/results
27 10:05:14.720366 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-add-keys
28 10:05:14.720667 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-add-sources
29 10:05:14.720946 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-background-process-start
30 10:05:14.721295 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-background-process-stop
31 10:05:14.721558 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-common-functions
32 10:05:14.721814 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-echo-ipv4
33 10:05:14.722060 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-install-packages
34 10:05:14.722307 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-installed-packages
35 10:05:14.722546 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-os-build
36 10:05:14.722813 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-probe-channel
37 10:05:14.723067 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-probe-ip
38 10:05:14.723334 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-target-ip
39 10:05:14.723607 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-target-mac
40 10:05:14.723854 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-target-storage
41 10:05:14.724124 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-test-case
42 10:05:14.724377 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-test-event
43 10:05:14.724619 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-test-feedback
44 10:05:14.724858 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-test-raise
45 10:05:14.725136 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-test-reference
46 10:05:14.725387 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-test-runner
47 10:05:14.725625 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-test-set
48 10:05:14.725878 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-test-shell
49 10:05:14.726124 Updating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-install-packages (oe)
50 10:05:14.726431 Updating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/bin/lava-installed-packages (oe)
51 10:05:14.726696 Creating /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/environment
52 10:05:14.726897 LAVA metadata
53 10:05:14.727039 - LAVA_JOB_ID=592431
54 10:05:14.727187 - LAVA_DISPATCHER_IP=172.27.0.2
55 10:05:14.727384 start: 1.1.1 lava-vland-overlay (timeout 00:03:00) [common]
56 10:05:14.727524 skipped lava-vland-overlay
57 10:05:14.727713 end: 1.1.1 lava-vland-overlay (duration 00:00:00) [common]
58 10:05:14.727877 start: 1.1.2 lava-multinode-overlay (timeout 00:03:00) [common]
59 10:05:14.728015 skipped lava-multinode-overlay
60 10:05:14.728161 end: 1.1.2 lava-multinode-overlay (duration 00:00:00) [common]
61 10:05:14.728322 start: 1.1.3 test-definition (timeout 00:03:00) [common]
62 10:05:14.728474 Loading test definitions
63 10:05:14.728656 start: 1.1.3.1 inline-repo-action (timeout 00:03:00) [common]
64 10:05:14.728805 Using /lava-592431 at stage 0
65 10:05:14.729481 uuid=592431_1.1.3.1 testdef=None
66 10:05:14.729699 end: 1.1.3.1 inline-repo-action (duration 00:00:00) [common]
67 10:05:14.729881 start: 1.1.3.2 test-overlay (timeout 00:03:00) [common]
68 10:05:14.730924 end: 1.1.3.2 test-overlay (duration 00:00:00) [common]
70 10:05:14.731481 start: 1.1.3.3 test-install-overlay (timeout 00:03:00) [common]
71 10:05:14.732779 end: 1.1.3.3 test-install-overlay (duration 00:00:00) [common]
73 10:05:14.733356 start: 1.1.3.4 test-runscript-overlay (timeout 00:03:00) [common]
74 10:05:14.734604 runner path: /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/0/tests/0_timesync-off test_uuid 592431_1.1.3.1
75 10:05:14.734947 end: 1.1.3.4 test-runscript-overlay (duration 00:00:00) [common]
77 10:05:14.735486 start: 1.1.3.5 git-repo-action (timeout 00:03:00) [common]
78 10:05:14.735652 Using /lava-592431 at stage 0
79 10:05:14.735877 Fetching tests from https://github.com/kernelci/test-definitions.git
80 10:05:14.736053 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/0/tests/1_kselftest-arm64_qemu'
81 10:05:17.524777 Running '/usr/bin/git checkout kernelci.org
82 10:05:17.667491 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/0/tests/1_kselftest-arm64_qemu/automated/linux/kselftest/kselftest.yaml
83 10:05:17.668596 uuid=592431_1.1.3.5 testdef=None
84 10:05:17.668838 end: 1.1.3.5 git-repo-action (duration 00:00:03) [common]
86 10:05:17.669326 start: 1.1.3.6 test-overlay (timeout 00:02:57) [common]
87 10:05:17.670924 end: 1.1.3.6 test-overlay (duration 00:00:00) [common]
89 10:05:17.671413 start: 1.1.3.7 test-install-overlay (timeout 00:02:57) [common]
90 10:05:17.673585 end: 1.1.3.7 test-install-overlay (duration 00:00:00) [common]
92 10:05:17.674113 start: 1.1.3.8 test-runscript-overlay (timeout 00:02:57) [common]
93 10:05:17.679779 runner path: /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/0/tests/1_kselftest-arm64_qemu test_uuid 592431_1.1.3.5
94 10:05:17.679956 BOARD='qemu_arm64-virt-gicv3'
95 10:05:17.680085 BRANCH='cip'
96 10:05:17.680206 SKIPFILE='/dev/null'
97 10:05:17.680326 SKIP_INSTALL='True'
98 10:05:17.680444 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
99 10:05:17.680566 TST_CASENAME=''
100 10:05:17.680684 TST_CMDFILES='arm64'
101 10:05:17.680959 end: 1.1.3.8 test-runscript-overlay (duration 00:00:00) [common]
103 10:05:17.681424 Creating lava-test-runner.conf files
104 10:05:17.681553 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/592431/lava-overlay-eelpymj2/lava-592431/0 for stage 0
105 10:05:17.681744 - 0_timesync-off
106 10:05:17.681889 - 1_kselftest-arm64_qemu
107 10:05:17.682077 end: 1.1.3 test-definition (duration 00:00:03) [common]
108 10:05:17.682247 start: 1.1.4 compress-overlay (timeout 00:02:57) [common]
109 10:05:26.437583 end: 1.1.4 compress-overlay (duration 00:00:09) [common]
110 10:05:26.437783 start: 1.1.5 persistent-nfs-overlay (timeout 00:02:48) [common]
111 10:05:26.437873 end: 1.1.5 persistent-nfs-overlay (duration 00:00:00) [common]
112 10:05:26.437978 end: 1.1 lava-overlay (duration 00:00:12) [common]
113 10:05:26.438067 start: 1.2 apply-overlay-guest (timeout 00:02:48) [common]
114 10:05:26.438143 Overlay: /var/lib/lava/dispatcher/tmp/592431/compress-overlay-cjwrkn00/overlay-1.1.4.tar.gz
115 10:05:41.464815 end: 1.2 apply-overlay-guest (duration 00:00:15) [common]
117 10:05:41.465603 start: 1.3 deploy-device-env (timeout 00:02:33) [common]
118 10:05:41.465840 end: 1.3 deploy-device-env (duration 00:00:00) [common]
119 10:05:41.466013 start: 1.4 download-retry (timeout 00:02:33) [common]
120 10:05:41.466186 start: 1.4.1 http-download (timeout 00:02:33) [common]
121 10:05:41.466484 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
122 10:05:41.466623 saving as /var/lib/lava/dispatcher/tmp/592431/deployimages-1es6uzg4/kernel/Image
123 10:05:41.466746 total size: 45746688 (43MB)
124 10:05:41.466865 No compression specified
125 10:05:41.809101 progress 0% (0MB)
126 10:05:42.830901 progress 5% (2MB)
127 10:05:43.171425 progress 10% (4MB)
128 10:05:43.350325 progress 15% (6MB)
129 10:05:43.698755 progress 20% (8MB)
130 10:05:43.867454 progress 25% (10MB)
131 10:05:44.043474 progress 30% (13MB)
132 10:05:44.372198 progress 35% (15MB)
133 10:05:44.616316 progress 40% (17MB)
134 10:05:44.883060 progress 45% (19MB)
135 10:05:45.222394 progress 50% (21MB)
136 10:05:45.454877 progress 55% (24MB)
137 10:05:45.791228 progress 60% (26MB)
138 10:05:46.073858 progress 65% (28MB)
139 10:05:46.409043 progress 70% (30MB)
140 10:05:46.641058 progress 75% (32MB)
141 10:05:46.974432 progress 80% (34MB)
142 10:05:47.256399 progress 85% (37MB)
143 10:05:47.487398 progress 90% (39MB)
144 10:05:47.888824 progress 95% (41MB)
145 10:05:48.161403 progress 100% (43MB)
146 10:05:48.161771 43MB downloaded in 6.70s (6.52MB/s)
147 10:05:48.162100 end: 1.4.1 http-download (duration 00:00:07) [common]
149 10:05:48.162659 end: 1.4 download-retry (duration 00:00:07) [common]
150 10:05:48.162853 start: 1.5 download-retry (timeout 00:02:27) [common]
151 10:05:48.163043 start: 1.5.1 http-download (timeout 00:02:27) [common]
152 10:05:48.163302 Not decompressing ramdisk as can be used compressed.
153 10:05:48.163495 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz
154 10:05:48.163637 saving as /var/lib/lava/dispatcher/tmp/592431/deployimages-1es6uzg4/ramdisk/rootfs.cpio.gz
155 10:05:48.163788 total size: 88976554 (84MB)
156 10:05:48.163937 No compression specified
157 10:05:48.335199 progress 0% (0MB)
158 10:05:49.017275 progress 5% (4MB)
159 10:05:49.698714 progress 10% (8MB)
160 10:05:50.377529 progress 15% (12MB)
161 10:05:51.054365 progress 20% (17MB)
162 10:05:51.728665 progress 25% (21MB)
163 10:05:52.379921 progress 30% (25MB)
164 10:05:52.927678 progress 35% (29MB)
165 10:05:53.600933 progress 40% (33MB)
166 10:05:54.271899 progress 45% (38MB)
167 10:05:54.798767 progress 50% (42MB)
168 10:05:55.467838 progress 55% (46MB)
169 10:05:56.139403 progress 60% (50MB)
170 10:05:56.804282 progress 65% (55MB)
171 10:05:57.331987 progress 70% (59MB)
172 10:05:58.005503 progress 75% (63MB)
173 10:05:58.673601 progress 80% (67MB)
174 10:05:59.195220 progress 85% (72MB)
175 10:05:59.866965 progress 90% (76MB)
176 10:06:00.403849 progress 95% (80MB)
177 10:06:01.051239 progress 100% (84MB)
178 10:06:01.051660 84MB downloaded in 12.89s (6.58MB/s)
179 10:06:01.051973 end: 1.5.1 http-download (duration 00:00:13) [common]
181 10:06:01.052532 end: 1.5 download-retry (duration 00:00:13) [common]
182 10:06:01.052724 end: 1 deployimages (duration 00:00:46) [common]
183 10:06:01.052923 start: 2 boot-image-retry (timeout 00:05:00) [common]
184 10:06:01.053118 start: 2.1 boot-qemu-image (timeout 00:05:00) [common]
185 10:06:01.053312 start: 2.1.1 execute-qemu (timeout 00:05:00) [common]
186 10:06:01.053739 Extending command line for qcow2 test overlay
187 10:06:01.054406 Pulling docker image
188 10:06:01.054586 cmd: ['docker', 'pull', 'kernelci/qemu']
189 10:06:01.054748 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
190 10:06:01.221973 >> Using default tag: latest
191 10:06:02.306235 >> latest: Pulling from kernelci/qemu
192 10:06:02.338524 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
193 10:06:02.338753 >> Status: Image is up to date for kernelci/qemu:latest
194 10:06:02.371930 >> docker.io/kernelci/qemu:latest
195 10:06:02.374461 Returned 0 in 1 seconds
196 10:06:02.503137 Boot command: docker run --network=host --cap-add=NET_ADMIN --interactive --tty --rm --init --name=lava-docker-qemu-592431-2.1.1-tl53m9t735 --mount=type=bind,source=/var/lib/lava/dispatcher/tmp,destination=/var/lib/lava/dispatcher/tmp kernelci/qemu qemu-system-aarch64 -cpu max,pauth-impdef=on -machine virt,gic-version=3,mte=on,accel=tcg -nographic -net nic,model=virtio,macaddr=52:54:00:12:34:58 -net user -m 1g -monitor none -kernel /var/lib/lava/dispatcher/tmp/592431/deployimages-1es6uzg4/kernel/Image -append "console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon" -initrd /var/lib/lava/dispatcher/tmp/592431/deployimages-1es6uzg4/ramdisk/rootfs.cpio.gz -drive format=qcow2,file=/var/lib/lava/dispatcher/tmp/592431/apply-overlay-guest-a7lbo6o9/lava-guest.qcow2,media=disk,if=virtio,id=lavatest
197 10:06:02.657922 started a shell command
198 10:06:02.658467 end: 2.1.1 execute-qemu (duration 00:00:02) [common]
199 10:06:02.658619 end: 2.1 boot-qemu-image (duration 00:00:02) [common]
200 10:06:02.658754 start: 2.2 auto-login-action (timeout 00:04:58) [common]
201 10:06:02.658886 Setting prompt string to ['Linux version [0-9]']
202 10:06:02.658994 auto-login-action: Wait for prompt ['Linux version [0-9]'] (timeout 00:05:00)
203 10:06:05.198276 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510]
204 10:06:05.199001 start: 2.2.1 login-action (timeout 00:04:56) [common]
205 10:06:05.199134 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
206 10:06:05.199271 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
207 10:06:05.199393 Using line separator: #'\n'#
208 10:06:05.199490 No login prompt set.
209 10:06:05.199592 Parsing kernel messages
210 10:06:05.199682 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
211 10:06:05.199860 [login-action] Waiting for messages, (timeout 00:04:56)
212 10:06:05.200776 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j19381-arm64-gcc-10-defconfig-arm64-chromebook-d6qsg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023
213 10:06:05.200887 [ 0.000000] random: crng init done
214 10:06:05.200971 [ 0.000000] Machine model: linux,dummy-virt
215 10:06:05.201054 [ 0.000000] efi: UEFI not found.
216 10:06:05.201134 [ 0.000000] earlycon: pl11 at MMIO 0x0000000009000000 (options '')
217 10:06:05.201213 [ 0.000000] printk: bootconsole [pl11] enabled
218 10:06:05.204936 [ 0.000000] NUMA: No NUMA configuration found
219 10:06:05.205360 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000007fffffff]
220 10:06:05.206066 [ 0.000000] NUMA: NODE_DATA [mem 0x7fdf3a00-0x7fdf5fff]
221 10:06:05.208951 [ 0.000000] Zone ranges:
222 10:06:05.209880 [ 0.000000] DMA [mem 0x0000000040000000-0x000000007fffffff]
223 10:06:05.209993 [ 0.000000] DMA32 empty
224 10:06:05.210100 [ 0.000000] Normal empty
225 10:06:05.210186 [ 0.000000] Movable zone start for each node
226 10:06:05.210289 [ 0.000000] Early memory node ranges
227 10:06:05.210590 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000007fffffff]
228 10:06:05.211067 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000007fffffff]
229 10:06:05.228360 [ 0.000000] cma: Reserved 32 MiB at 0x000000007cc00000
230 10:06:05.229726 [ 0.000000] psci: probing for conduit method from DT.
231 10:06:05.230155 [ 0.000000] psci: PSCIv1.1 detected in firmware.
232 10:06:05.230267 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
233 10:06:05.230387 [ 0.000000] psci: Trusted OS migration not required
234 10:06:05.230700 [ 0.000000] psci: SMC Calling Convention v1.0
235 10:06:05.233792 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
236 10:06:05.234542 [ 0.000000] pcpu-alloc: s45224 r8192 d32600 u86016 alloc=21*4096
237 10:06:05.234866 [ 0.000000] pcpu-alloc: [0] 0
238 10:06:05.236657 [ 0.000000] Detected PIPT I-cache on CPU0
239 10:06:05.244220 [ 0.000000] CPU features: detected: Address authentication (IMP DEF algorithm)
240 10:06:05.245095 [ 0.000000] CPU features: detected: GIC system register CPU interface
241 10:06:05.245391 [ 0.000000] CPU features: detected: Hardware dirty bit management
242 10:06:05.245687 [ 0.000000] CPU features: detected: Memory Tagging Extension
243 10:06:05.245996 [ 0.000000] CPU features: detected: Asymmetric MTE Tag Check Fault
244 10:06:05.246292 [ 0.000000] CPU features: detected: Spectre-v4
245 10:06:05.251496 [ 0.000000] alternatives: applying boot alternatives
246 10:06:05.255590 [ 0.000000] Fallback order for Node 0: 0
247 10:06:05.255903 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258048
248 10:06:05.255987 [ 0.000000] Policy zone: DMA
249 10:06:05.256674 [ 0.000000] Kernel command line: console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon
250 10:06:05.260075 <5>[ 0.000000] Unknown kernel command line parameters \"verbose\", will be passed to user space.
251 10:06:05.264241 <6>[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
252 10:06:05.264775 <6>[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
253 10:06:05.265524 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
254 10:06:05.277333 <6>[ 0.000000] Memory: 862480K/1048576K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 153328K reserved, 32768K cma-reserved)
255 10:06:05.284445 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
256 10:06:05.291688 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
257 10:06:05.291902 <6>[ 0.000000] rcu: RCU event tracing is enabled.
258 10:06:05.292021 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=1.
259 10:06:05.292164 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
260 10:06:05.292530 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
261 10:06:05.292653 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
262 10:06:05.292763 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
263 10:06:05.293929 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
264 10:06:05.301731 <6>[ 0.000000] GICv3: 224 SPIs implemented
265 10:06:05.302125 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
266 10:06:05.303534 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
267 10:06:05.303933 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
268 10:06:05.304666 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000080a0000
269 10:06:05.309777 <6>[ 0.000000] ITS [mem 0x08080000-0x0809ffff]
270 10:06:05.310835 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Devices @43030000 (indirect, esz 8, psz 64K, shr 1)
271 10:06:05.310974 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Interrupt Collections @43040000 (flat, esz 8, psz 64K, shr 1)
272 10:06:05.311596 <6>[ 0.000000] GICv3: using LPI property table @0x0000000043050000
273 10:06:05.312403 <6>[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000043060000
274 10:06:05.314127 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
275 10:06:05.325512 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 62.50MHz (virt).
276 10:06:05.325935 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x1cd42e208c, max_idle_ns: 881590405314 ns
277 10:06:05.326493 <6>[ 0.000089] sched_clock: 57 bits at 63MHz, resolution 16ns, wraps every 4398046511096ns
278 10:06:05.348354 <6>[ 0.018949] Console: colour dummy device 80x25
279 10:06:05.352944 <6>[ 0.026153] Calibrating delay loop (skipped), value calculated using timer frequency.. 125.00 BogoMIPS (lpj=250000)
280 10:06:05.353243 <6>[ 0.027171] pid_max: default: 32768 minimum: 301
281 10:06:05.354666 <6>[ 0.028504] LSM: Security Framework initializing
282 10:06:05.359008 <6>[ 0.032887] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
283 10:06:05.359501 <6>[ 0.033186] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
284 10:06:05.393976 <4>[ 0.067862] cacheinfo: Unable to detect cache hierarchy for CPU 0
285 10:06:05.400924 <6>[ 0.074568] cblist_init_generic: Setting adjustable number of callback queues.
286 10:06:05.401182 <6>[ 0.074929] cblist_init_generic: Setting shift to 0 and lim to 1.
287 10:06:05.401737 <6>[ 0.075610] cblist_init_generic: Setting shift to 0 and lim to 1.
288 10:06:05.403824 <6>[ 0.077614] rcu: Hierarchical SRCU implementation.
289 10:06:05.403983 <6>[ 0.077794] rcu: Max phase no-delay instances is 1000.
290 10:06:05.409278 <6>[ 0.082996] Platform MSI: its@8080000 domain created
291 10:06:05.410006 <6>[ 0.083750] PCI/MSI: /intc@8000000/its@8080000 domain created
292 10:06:05.410568 <6>[ 0.084375] fsl-mc MSI: its@8080000 domain created
293 10:06:05.414047 <6>[ 0.087977] EFI services will not be available.
294 10:06:05.415632 <6>[ 0.089569] smp: Bringing up secondary CPUs ...
295 10:06:05.415999 <6>[ 0.089777] smp: Brought up 1 node, 1 CPU
296 10:06:05.416103 <6>[ 0.089943] SMP: Total of 1 processors activated.
297 10:06:05.416668 <6>[ 0.090309] CPU features: detected: Branch Target Identification
298 10:06:05.416777 <6>[ 0.090527] CPU features: detected: 32-bit EL0 Support
299 10:06:05.416886 <6>[ 0.090687] CPU features: detected: 32-bit EL1 Support
300 10:06:05.416993 <6>[ 0.090805] CPU features: detected: ARMv8.4 Translation Table Level
301 10:06:05.417321 <6>[ 0.091045] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
302 10:06:05.417669 <6>[ 0.091346] CPU features: detected: Common not Private translations
303 10:06:05.417768 <6>[ 0.091503] CPU features: detected: CRC32 instructions
304 10:06:05.418100 <6>[ 0.091649] CPU features: detected: E0PD
305 10:06:05.418204 <6>[ 0.091809] CPU features: detected: Generic authentication (IMP DEF algorithm)
306 10:06:05.418292 <6>[ 0.092033] CPU features: detected: RCpc load-acquire (LDAPR)
307 10:06:05.418395 <6>[ 0.092166] CPU features: detected: LSE atomic instructions
308 10:06:05.418727 <6>[ 0.092339] CPU features: detected: Privileged Access Never
309 10:06:05.418840 <6>[ 0.092524] CPU features: detected: RAS Extension Support
310 10:06:05.419168 <6>[ 0.092684] CPU features: detected: Random Number Generator
311 10:06:05.419279 <6>[ 0.092805] CPU features: detected: Speculation barrier (SB)
312 10:06:05.419382 <6>[ 0.093209] CPU features: detected: Stage-2 Force Write-Back
313 10:06:05.419489 <6>[ 0.093368] CPU features: detected: TLB range maintenance instructions
314 10:06:05.419911 <6>[ 0.093634] CPU features: detected: Scalable Matrix Extension
315 10:06:05.420525 <6>[ 0.093857] CPU features: detected: FA64
316 10:06:05.420633 <6>[ 0.094012] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
317 10:06:05.420722 <6>[ 0.094410] CPU features: detected: Scalable Vector Extension
318 10:06:05.432986 <6>[ 0.103666] SVE: maximum available vector length 256 bytes per vector
319 10:06:05.433601 <6>[ 0.107294] SVE: default vector length 64 bytes per vector
320 10:06:05.435642 <6>[ 0.109374] SME: minimum available vector length 16 bytes per vector
321 10:06:05.436197 <6>[ 0.109968] SME: maximum available vector length 256 bytes per vector
322 10:06:05.436319 <6>[ 0.110200] SME: default vector length 32 bytes per vector
323 10:06:05.437002 <6>[ 0.110787] CPU: All CPU(s) started at EL1
324 10:06:05.437485 <6>[ 0.111249] alternatives: applying system-wide alternatives
325 10:06:05.515000 <6>[ 0.188706] devtmpfs: initialized
326 10:06:05.543573 <6>[ 0.217028] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
327 10:06:05.544322 <6>[ 0.218064] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
328 10:06:05.552647 <6>[ 0.226262] pinctrl core: initialized pinctrl subsystem
329 10:06:05.568207 <6>[ 0.242011] DMI not present or invalid.
330 10:06:05.580952 <6>[ 0.254563] NET: Registered PF_NETLINK/PF_ROUTE protocol family
331 10:06:05.597578 <6>[ 0.270923] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
332 10:06:05.598350 <6>[ 0.272105] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
333 10:06:05.598948 <6>[ 0.272740] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
334 10:06:05.600431 <6>[ 0.274167] audit: initializing netlink subsys (disabled)
335 10:06:05.608712 <5>[ 0.282304] audit: type=2000 audit(0.220:1): state=initialized audit_enabled=0 res=1
336 10:06:05.611094 <6>[ 0.284912] thermal_sys: Registered thermal governor 'step_wise'
337 10:06:05.612111 <6>[ 0.285018] thermal_sys: Registered thermal governor 'power_allocator'
338 10:06:05.612285 <6>[ 0.285936] cpuidle: using governor menu
339 10:06:05.613277 <6>[ 0.287198] NET: Registered PF_QIPCRTR protocol family
340 10:06:05.617459 <6>[ 0.291145] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
341 10:06:05.618222 <6>[ 0.292018] ASID allocator initialised with 65536 entries
342 10:06:05.627464 <6>[ 0.301099] Serial: AMBA PL011 UART driver
343 10:06:05.701757 <6>[ 0.375440] 9000000.pl011: ttyAMA0 at MMIO 0x9000000 (irq = 13, base_baud = 0) is a PL011 rev1
344 10:06:05.704103 <6>[ 0.377708] printk: console [ttyAMA0] enabled
345 10:06:05.704292 <6>[ 0.377708] printk: console [ttyAMA0] enabled
346 10:06:05.704403 <6>[ 0.378330] printk: bootconsole [pl11] disabled
347 10:06:05.704734 <6>[ 0.378330] printk: bootconsole [pl11] disabled
348 10:06:05.720007 <6>[ 0.393858] KASLR enabled
349 10:06:05.775218 <6>[ 0.448781] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
350 10:06:05.775582 <6>[ 0.449036] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
351 10:06:05.776122 <6>[ 0.449253] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
352 10:06:05.776336 <6>[ 0.449454] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
353 10:06:05.776511 <6>[ 0.449649] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
354 10:06:05.776678 <6>[ 0.449855] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
355 10:06:05.776876 <6>[ 0.450038] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
356 10:06:05.777048 <6>[ 0.450243] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
357 10:06:05.790274 <6>[ 0.464028] ACPI: Interpreter disabled.
358 10:06:05.802834 <6>[ 0.476616] iommu: Default domain type: Translated
359 10:06:05.803503 <6>[ 0.476861] iommu: DMA domain TLB invalidation policy: strict mode
360 10:06:05.805510 <5>[ 0.479221] SCSI subsystem initialized
361 10:06:05.806865 <7>[ 0.480641] libata version 3.00 loaded.
362 10:06:05.808745 <6>[ 0.482509] usbcore: registered new interface driver usbfs
363 10:06:05.809134 <6>[ 0.483019] usbcore: registered new interface driver hub
364 10:06:05.809501 <6>[ 0.483423] usbcore: registered new device driver usb
365 10:06:05.814825 <6>[ 0.488694] pps_core: LinuxPPS API ver. 1 registered
366 10:06:05.815362 <6>[ 0.488893] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
367 10:06:05.815488 <6>[ 0.489306] PTP clock support registered
368 10:06:05.816179 <6>[ 0.490155] EDAC MC: Ver: 3.0.0
369 10:06:05.826214 <6>[ 0.499876] FPGA manager framework
370 10:06:05.827518 <6>[ 0.501274] Advanced Linux Sound Architecture Driver Initialized.
371 10:06:05.839500 <6>[ 0.513361] vgaarb: loaded
372 10:06:05.843484 <6>[ 0.517363] clocksource: Switched to clocksource arch_sys_counter
373 10:06:05.844758 <5>[ 0.518748] VFS: Disk quotas dquot_6.6.0
374 10:06:05.845219 <6>[ 0.519049] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
375 10:06:05.846946 <6>[ 0.520661] pnp: PnP ACPI: disabled
376 10:06:05.868022 <6>[ 0.541831] NET: Registered PF_INET protocol family
377 10:06:05.871073 <6>[ 0.544744] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
378 10:06:05.878997 <6>[ 0.551860] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
379 10:06:05.879430 <6>[ 0.553194] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
380 10:06:05.879639 <6>[ 0.553540] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
381 10:06:05.880115 <6>[ 0.553961] TCP bind hash table entries: 8192 (order: 6, 262144 bytes, linear)
382 10:06:05.880736 <6>[ 0.554598] TCP: Hash tables configured (established 8192 bind 8192)
383 10:06:05.882025 <6>[ 0.555844] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
384 10:06:05.882371 <6>[ 0.556263] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
385 10:06:05.884059 <6>[ 0.557949] NET: Registered PF_UNIX/PF_LOCAL protocol family
386 10:06:05.886584 <6>[ 0.560348] RPC: Registered named UNIX socket transport module.
387 10:06:05.886743 <6>[ 0.560620] RPC: Registered udp transport module.
388 10:06:05.887083 <6>[ 0.560827] RPC: Registered tcp transport module.
389 10:06:05.887679 <6>[ 0.561473] RPC: Registered tcp NFSv4.1 backchannel transport module.
390 10:06:05.888025 <6>[ 0.561831] PCI: CLS 0 bytes, default 64
391 10:06:05.892398 <6>[ 0.566362] Unpacking initramfs...
392 10:06:05.901382 <6>[ 0.574959] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
393 10:06:05.902285 <6>[ 0.576019] kvm [1]: HYP mode not available
394 10:06:05.909740 <5>[ 0.583581] Initialise system trusted keyrings
395 10:06:05.916336 <6>[ 0.589962] workingset: timestamp_bits=42 max_order=18 bucket_order=0
396 10:06:05.957141 <6>[ 0.630719] squashfs: version 4.0 (2009/01/31) Phillip Lougher
397 10:06:05.964771 <5>[ 0.638415] NFS: Registering the id_resolver key type
398 10:06:05.965010 <5>[ 0.638948] Key type id_resolver registered
399 10:06:05.965357 <5>[ 0.639142] Key type id_legacy registered
400 10:06:05.966119 <6>[ 0.639842] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
401 10:06:05.966475 <6>[ 0.640185] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
402 10:06:05.971709 <6>[ 0.645463] 9p: Installing v9fs 9p2000 file system support
403 10:06:06.044147 <5>[ 0.717960] Key type asymmetric registered
404 10:06:06.044657 <5>[ 0.718249] Asymmetric key parser 'x509' registered
405 10:06:06.045013 <6>[ 0.718823] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
406 10:06:06.045416 <6>[ 0.719213] io scheduler mq-deadline registered
407 10:06:06.045541 <6>[ 0.719458] io scheduler kyber registered
408 10:06:06.134017 <6>[ 0.807467] pl061_gpio 9030000.pl061: PL061 GPIO chip registered
409 10:06:06.145767 <6>[ 0.819430] pci-host-generic 4010000000.pcie: host bridge /pcie@10000000 ranges:
410 10:06:06.147002 <6>[ 0.820557] pci-host-generic 4010000000.pcie: IO 0x003eff0000..0x003effffff -> 0x0000000000
411 10:06:06.155947 <6>[ 0.829627] pci-host-generic 4010000000.pcie: MEM 0x0010000000..0x003efeffff -> 0x0010000000
412 10:06:06.156441 <6>[ 0.830115] pci-host-generic 4010000000.pcie: MEM 0x8000000000..0xffffffffff -> 0x8000000000
413 10:06:06.157161 <4>[ 0.830891] pci-host-generic 4010000000.pcie: Memory resource size exceeds max for 32 bits
414 10:06:06.158395 <6>[ 0.831691] pci-host-generic 4010000000.pcie: ECAM at [mem 0x4010000000-0x401fffffff] for [bus 00-ff]
415 10:06:06.164267 <6>[ 0.837923] pci-host-generic 4010000000.pcie: PCI host bridge to bus 0000:00
416 10:06:06.164977 <6>[ 0.838598] pci_bus 0000:00: root bus resource [bus 00-ff]
417 10:06:06.165473 <6>[ 0.838924] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
418 10:06:06.165582 <6>[ 0.839252] pci_bus 0000:00: root bus resource [mem 0x10000000-0x3efeffff]
419 10:06:06.165918 <6>[ 0.839537] pci_bus 0000:00: root bus resource [mem 0x8000000000-0xffffffffff]
420 10:06:06.171789 <6>[ 0.845484] pci 0000:00:00.0: [1b36:0008] type 00 class 0x060000
421 10:06:06.179676 <6>[ 0.853315] pci 0000:00:01.0: [1af4:1000] type 00 class 0x020000
422 10:06:06.179931 <6>[ 0.853823] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x001f]
423 10:06:06.180266 <6>[ 0.854073] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x00000fff]
424 10:06:06.180633 <6>[ 0.854364] pci 0000:00:01.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
425 10:06:06.180992 <6>[ 0.854770] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x0003ffff pref]
426 10:06:06.181853 <6>[ 0.855583] pci 0000:00:02.0: [1af4:1001] type 00 class 0x010000
427 10:06:06.182217 <6>[ 0.855825] pci 0000:00:02.0: reg 0x10: [io 0x0000-0x007f]
428 10:06:06.182324 <6>[ 0.856059] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x00000fff]
429 10:06:06.182426 <6>[ 0.856315] pci 0000:00:02.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
430 10:06:06.189878 <6>[ 0.863696] pci 0000:00:01.0: BAR 6: assigned [mem 0x10000000-0x1003ffff pref]
431 10:06:06.190618 <6>[ 0.864278] pci 0000:00:01.0: BAR 4: assigned [mem 0x8000000000-0x8000003fff 64bit pref]
432 10:06:06.190750 <6>[ 0.864626] pci 0000:00:02.0: BAR 4: assigned [mem 0x8000004000-0x8000007fff 64bit pref]
433 10:06:06.195478 <6>[ 0.864932] pci 0000:00:01.0: BAR 1: assigned [mem 0x10040000-0x10040fff]
434 10:06:06.195636 <6>[ 0.869414] pci 0000:00:02.0: BAR 1: assigned [mem 0x10041000-0x10041fff]
435 10:06:06.195739 <6>[ 0.869661] pci 0000:00:02.0: BAR 0: assigned [io 0x1000-0x107f]
436 10:06:06.195955 <6>[ 0.869884] pci 0000:00:01.0: BAR 0: assigned [io 0x1080-0x109f]
437 10:06:06.212366 <6>[ 0.886214] EINJ: ACPI disabled.
438 10:06:06.306817 <6>[ 0.980410] virtio-pci 0000:00:01.0: enabling device (0000 -> 0003)
439 10:06:06.314133 <6>[ 0.987677] virtio-pci 0000:00:02.0: enabling device (0000 -> 0003)
440 10:06:06.348660 <6>[ 1.022494] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
441 10:06:06.363904 <6>[ 1.037758] SuperH (H)SCI(F) driver initialized
442 10:06:06.365455 <6>[ 1.039269] msm_serial: driver initialized
443 10:06:06.399347 <4>[ 1.073165] cacheinfo: Unable to detect cache hierarchy for CPU 0
444 10:06:06.435699 <6>[ 1.109523] loop: module loaded
445 10:06:06.436985 <6>[ 1.110674] virtio_blk virtio1: 1/0/0 default/read/poll queues
446 10:06:06.461768 <5>[ 1.135390] virtio_blk virtio1: [vda] 1048576 512-byte logical blocks (537 MB/512 MiB)
447 10:06:06.493742 <6>[ 1.167561] megasas: 07.719.03.00-rc1
448 10:06:06.517085 <5>[ 1.190689] physmap-flash 0.flash: physmap platform flash device: [mem 0x00000000-0x03ffffff]
449 10:06:06.518754 <6>[ 1.192503] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
450 10:06:06.523698 <6>[ 1.197405] Intel/Sharp Extended Query Table at 0x0031
451 10:06:06.524492 <6>[ 1.198310] Using buffer write method
452 10:06:06.524997 <7>[ 1.198788] erase region 0: offset=0x0,size=0x40000,blocks=256
453 10:06:06.525309 <5>[ 1.199199] physmap-flash 0.flash: physmap platform flash device: [mem 0x04000000-0x07ffffff]
454 10:06:06.526042 <6>[ 1.199916] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
455 10:06:06.526383 <6>[ 1.200210] Intel/Sharp Extended Query Table at 0x0031
456 10:06:06.526999 <6>[ 1.200812] Using buffer write method
457 10:06:06.531341 <7>[ 1.205096] erase region 0: offset=0x0,size=0x40000,blocks=256
458 10:06:06.531499 <5>[ 1.205404] Concatenating MTD devices:
459 10:06:06.531624 <5>[ 1.205569] (0): \"0.flash\"
460 10:06:06.531743 <5>[ 1.205679] (1): \"0.flash\"
461 10:06:06.531820 <5>[ 1.205768] into device \"0.flash\"
462 10:06:11.472809 <6>[ 6.146602] Freeing initrd memory: 86888K
463 10:06:11.598354 <6>[ 6.272242] tun: Universal TUN/TAP device driver, 1.6
464 10:06:11.608654 <6>[ 6.282539] thunder_xcv, ver 1.0
465 10:06:11.609159 <6>[ 6.282814] thunder_bgx, ver 1.0
466 10:06:11.609270 <6>[ 6.283024] nicpf, ver 1.0
467 10:06:11.612606 <6>[ 6.286393] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
468 10:06:11.612752 <6>[ 6.286616] hns3: Copyright (c) 2017 Huawei Corporation.
469 10:06:11.613081 <6>[ 6.287060] hclge is initializing
470 10:06:11.613411 <6>[ 6.287288] e1000: Intel(R) PRO/1000 Network Driver
471 10:06:11.613733 <6>[ 6.287481] e1000: Copyright (c) 1999-2006 Intel Corporation.
472 10:06:11.614080 <6>[ 6.287827] e1000e: Intel(R) PRO/1000 Network Driver
473 10:06:11.614179 <6>[ 6.287999] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
474 10:06:11.614498 <6>[ 6.288367] igb: Intel(R) Gigabit Ethernet Network Driver
475 10:06:11.614611 <6>[ 6.288538] igb: Copyright (c) 2007-2014 Intel Corporation.
476 10:06:11.614932 <6>[ 6.288831] igbvf: Intel(R) Gigabit Virtual Function Network Driver
477 10:06:11.615262 <6>[ 6.289106] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
478 10:06:11.616302 <6>[ 6.290126] sky2: driver version 1.30
479 10:06:11.619809 <6>[ 6.293697] VFIO - User Level meta-driver version: 0.3
480 10:06:11.629206 <6>[ 6.302853] usbcore: registered new interface driver usb-storage
481 10:06:11.629841 <6>[ 6.303673] usbcore: registered new device driver onboard-usb-hub
482 10:06:11.639408 <6>[ 6.313102] rtc-pl031 9010000.pl031: registered as rtc0
483 10:06:11.640450 <6>[ 6.313972] rtc-pl031 9010000.pl031: setting system clock to 2023-06-10T10:06:11 UTC (1686391571)
484 10:06:11.642657 <6>[ 6.316454] i2c_dev: i2c /dev entries driver
485 10:06:11.662505 <6>[ 6.336232] sdhci: Secure Digital Host Controller Interface driver
486 10:06:11.662714 <6>[ 6.336457] sdhci: Copyright(c) Pierre Ossman
487 10:06:11.664556 <6>[ 6.338392] Synopsys Designware Multimedia Card Interface Driver
488 10:06:11.667032 <6>[ 6.340861] sdhci-pltfm: SDHCI platform and OF driver helper
489 10:06:11.672859 <6>[ 6.346630] ledtrig-cpu: registered to indicate activity on CPUs
490 10:06:11.680670 <6>[ 6.354312] usbcore: registered new interface driver usbhid
491 10:06:11.680888 <6>[ 6.354535] usbhid: USB HID core driver
492 10:06:11.708770 <6>[ 6.382433] NET: Registered PF_PACKET protocol family
493 10:06:11.709808 <6>[ 6.383647] 9pnet: Installing 9P2000 support
494 10:06:11.710137 <5>[ 6.384074] Key type dns_resolver registered
495 10:06:11.711790 <6>[ 6.385612] registered taskstats version 1
496 10:06:11.712105 <5>[ 6.386028] Loading compiled-in X.509 certificates
497 10:06:11.734012 <6>[ 6.407636] input: gpio-keys as /devices/platform/gpio-keys/input/input0
498 10:06:11.740838 <6>[ 6.414810] ALSA device list:
499 10:06:11.741252 <6>[ 6.415002] No soundcards found.
500 10:06:11.743902 <6>[ 6.417739] uart-pl011 9000000.pl011: no DMA platform data
501 10:06:11.801027 <6>[ 6.474848] Freeing unused kernel memory: 8384K
502 10:06:11.802052 <6>[ 6.475838] Run /init as init process
503 10:06:11.802167 <7>[ 6.475985] with arguments:
504 10:06:11.802275 <7>[ 6.476100] /init
505 10:06:11.802365 <7>[ 6.476213] verbose
506 10:06:11.802465 <7>[ 6.476326] with environment:
507 10:06:11.802551 <7>[ 6.476461] HOME=/
508 10:06:11.802649 <7>[ 6.476578] TERM=linux
509 10:06:11.938009 <30>[ 6.611346] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
510 10:06:11.938911 <31>[ 6.612689] systemd[1]: No virtualization found in DMI
511 10:06:11.940152 <31>[ 6.613943] systemd[1]: UML virtualization not found in /proc/cpuinfo.
512 10:06:11.940531 <31>[ 6.614277] systemd[1]: No virtualization found in CPUID
513 10:06:11.940896 <31>[ 6.614612] systemd[1]: Virtualization XEN not found, /proc/xen does not exist
514 10:06:11.941938 <31>[ 6.615738] systemd[1]: Virtualization QEMU: \"fw-cfg\" present in /proc/device-tree/fw-cfg@9020000
515 10:06:11.942289 <31>[ 6.616156] systemd[1]: Found VM virtualization qemu
516 10:06:11.942421 <30>[ 6.616391] systemd[1]: Detected virtualization qemu.
517 10:06:11.942758 <30>[ 6.616735] systemd[1]: Detected architecture arm64.
518 10:06:11.943566 <31>[ 6.617392] systemd[1]: Detected initialized system, this is not the first boot.
519 10:06:11.947610
520 10:06:11.947995 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
521 10:06:11.948097
522 10:06:11.950005 <30>[ 6.623748] systemd[1]: Set hostname to <debian-bullseye-arm64>.
523 10:06:11.969243 <31>[ 6.642854] systemd[1]: Successfully added address 127.0.0.1 to loopback interface
524 10:06:11.970306 <31>[ 6.644121] systemd[1]: Failed to add address ::1 to loopback interface: Operation not supported
525 10:06:11.970845 <31>[ 6.644598] systemd[1]: Successfully brought loopback interface up
526 10:06:11.975983 <31>[ 6.649777] systemd[1]: Setting 'fs/file-max' to '9223372036854775807'.
527 10:06:11.988467 <31>[ 6.662139] systemd[1]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
528 10:06:11.988664 <31>[ 6.662509] systemd[1]: Unified cgroup hierarchy is located at /sys/fs/cgroup.
529 10:06:12.031684 <31>[ 6.705239] systemd[1]: Got EBADF when using BPF_F_ALLOW_MULTI, which indicates it is supported. Yay!
530 10:06:12.032908 <31>[ 6.706654] systemd[1]: Controller 'cpu' supported: yes
531 10:06:12.033030 <31>[ 6.706848] systemd[1]: Controller 'cpuacct' supported: no
532 10:06:12.033168 <31>[ 6.707032] systemd[1]: Controller 'cpuset' supported: yes
533 10:06:12.033295 <31>[ 6.707237] systemd[1]: Controller 'io' supported: yes
534 10:06:12.033440 <31>[ 6.707414] systemd[1]: Controller 'blkio' supported: no
535 10:06:12.033789 <31>[ 6.707577] systemd[1]: Controller 'memory' supported: yes
536 10:06:12.033907 <31>[ 6.707791] systemd[1]: Controller 'devices' supported: no
537 10:06:12.034267 <31>[ 6.708042] systemd[1]: Controller 'pids' supported: yes
538 10:06:12.034374 <31>[ 6.708240] systemd[1]: Controller 'bpf-firewall' supported: yes
539 10:06:12.034694 <31>[ 6.708467] systemd[1]: Controller 'bpf-devices' supported: yes
540 10:06:12.036167 <31>[ 6.709894] systemd[1]: Set up TFD_TIMER_CANCEL_ON_SET timerfd.
541 10:06:12.036648 <31>[ 6.710301] systemd[1]: Failed to stat /etc/localtime, ignoring: No such file or directory
542 10:06:12.036871 <31>[ 6.710834] systemd[1]: /etc/localtime doesn't exist yet, watching /etc instead.
543 10:06:12.044309 <31>[ 6.718171] systemd[1]: Enabling (yes) showing of status (commandline).
544 10:06:12.052539 <31>[ 6.726207] systemd[1]: Successfully forked off '(sd-executor)' as PID 98.
545 10:06:12.064789 <31>[ 6.738427] systemd[98]: Successfully forked off '(direxec)' as PID 99.
546 10:06:12.072027 <31>[ 6.745684] systemd[98]: Successfully forked off '(direxec)' as PID 100.
547 10:06:12.074036 <31>[ 6.747809] systemd[98]: Successfully forked off '(direxec)' as PID 101.
548 10:06:12.088743 <31>[ 6.762506] systemd[98]: Successfully forked off '(direxec)' as PID 102.
549 10:06:12.090985 <31>[ 6.764700] systemd[98]: Successfully forked off '(direxec)' as PID 103.
550 10:06:12.252948 <31>[ 6.926422] systemd-bless-boot-generator[99]: Skipping generator, not an EFI boot.
551 10:06:12.256715 <31>[ 6.930381] systemd-fstab-generator[100]: Parsing /etc/fstab...
552 10:06:12.258956 <31>[ 6.932573] systemd-fstab-generator[100]: Found entry what=/dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76 where=/ type=ext4 makefs=no growfs=no noauto=no nofail=no
553 10:06:12.267808 <31>[ 6.941504] systemd-getty-generator[101]: Automatically adding serial getty for /dev/ttyAMA0.
554 10:06:12.269192 <31>[ 6.942914] systemd-getty-generator[101]: SELinux enabled state cached to: disabled
555 10:06:12.281331 <31>[ 6.954864] systemd-fstab-generator[100]: Checking was requested for /dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76, but fsck.ext4 does not exist.
556 10:06:12.288566 <31>[ 6.962458] systemd-fstab-generator[100]: SELinux enabled state cached to: disabled
557 10:06:12.295107 <31>[ 6.968742] systemd[98]: /usr/lib/systemd/system-generators/systemd-fstab-generator succeeded.
558 10:06:12.296321 <31>[ 6.970044] systemd[98]: /usr/lib/systemd/system-generators/systemd-bless-boot-generator succeeded.
559 10:06:12.296569 <31>[ 6.970401] systemd[98]: /usr/lib/systemd/system-generators/systemd-getty-generator succeeded.
560 10:06:12.297037 <31>[ 6.970788] systemd[98]: /usr/lib/systemd/system-generators/systemd-run-generator succeeded.
561 10:06:12.297532 <31>[ 6.971151] systemd[98]: /usr/lib/systemd/system-generators/systemd-veritysetup-generator succeeded.
562 10:06:12.300403 <31>[ 6.974382] systemd[1]: (sd-executor) succeeded.
563 10:06:12.302325 <31>[ 6.976049] systemd[1]: Looking for unit files in (higher priority first):
564 10:06:12.302794 <31>[ 6.976300] systemd[1]: /etc/systemd/system.control
565 10:06:12.302971 <31>[ 6.976440] systemd[1]: /run/systemd/system.control
566 10:06:12.303103 <31>[ 6.976558] systemd[1]: /run/systemd/transient
567 10:06:12.303225 <31>[ 6.976671] systemd[1]: /run/systemd/generator.early
568 10:06:12.303370 <31>[ 6.976861] systemd[1]: /etc/systemd/system
569 10:06:12.303856 <31>[ 6.977550] systemd[1]: /etc/systemd/system.attached
570 10:06:12.304052 <31>[ 6.977740] systemd[1]: /run/systemd/system
571 10:06:12.304277 <31>[ 6.977884] systemd[1]: /run/systemd/system.attached
572 10:06:12.304451 <31>[ 6.978084] systemd[1]: /run/systemd/generator
573 10:06:12.304606 <31>[ 6.978231] systemd[1]: /usr/local/lib/systemd/system
574 10:06:12.304763 <31>[ 6.978356] systemd[1]: /lib/systemd/system
575 10:06:12.304890 <31>[ 6.978500] systemd[1]: /usr/lib/systemd/system
576 10:06:12.305008 <31>[ 6.978659] systemd[1]: /run/systemd/generator.late
577 10:06:12.342539 <31>[ 7.016370] systemd[1]: Modification times have changed, need to update cache.
578 10:06:12.344987 <31>[ 7.018496] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.network1.service → systemd-networkd.service
579 10:06:12.345952 <31>[ 7.019635] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.timesync1.service → systemd-timesyncd.service
580 10:06:12.346756 <31>[ 7.020339] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.resolve1.service → systemd-resolved.service
581 10:06:12.347826 <31>[ 7.021545] systemd[1]: unit_file_build_name_map: normal unit file: /run/systemd/generator/-.mount
582 10:06:12.348690 <31>[ 7.022412] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald@.service
583 10:06:12.348910 <31>[ 7.022743] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/console-getty.service
584 10:06:12.349104 <31>[ 7.023025] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/fstrim.timer
585 10:06:12.349688 <31>[ 7.023292] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-wall.path
586 10:06:12.349901 <31>[ 7.023574] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.service
587 10:06:12.350106 <31>[ 7.023915] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/poweroff.target
588 10:06:12.350658 <31>[ 7.024272] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-pre.target
589 10:06:12.351555 <31>[ 7.025269] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel4.target → multi-user.target
590 10:06:12.352111 <31>[ 7.025667] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend-then-hibernate.target
591 10:06:12.352274 <31>[ 7.026030] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network.target
592 10:06:12.352768 <31>[ 7.026642] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel5.target → graphical.target
593 10:06:12.353010 <31>[ 7.026914] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.service
594 10:06:12.353573 <31>[ 7.027195] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp-runlevel.service
595 10:06:12.353829 <31>[ 7.027489] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-fs.target
596 10:06:12.354024 <31>[ 7.027762] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/slices.target
597 10:06:12.354659 <31>[ 7.028333] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/kmod.service → systemd-modules-load.service
598 10:06:12.355127 <31>[ 7.028627] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp.service
599 10:06:12.356183 <31>[ 7.029681] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel1.target → rescue.target
600 10:06:12.356407 <31>[ 7.030010] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup-pre.target
601 10:06:12.356646 <31>[ 7.030328] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-pre.target
602 10:06:12.356865 <31>[ 7.030598] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/machine.slice
603 10:06:12.357073 <31>[ 7.030895] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-fs-pre.target
604 10:06:12.357340 <31>[ 7.031127] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.service
605 10:06:12.357854 <31>[ 7.031689] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel3.target → multi-user.target
606 10:06:12.358463 <31>[ 7.032269] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.timedate1.service → systemd-timedated.service
607 10:06:12.359095 <31>[ 7.032603] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.service
608 10:06:12.359267 <31>[ 7.032895] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/reboot.target
609 10:06:12.359797 <31>[ 7.033624] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-audit.socket
610 10:06:12.360063 <31>[ 7.033897] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty@.service
611 10:06:12.360394 <31>[ 7.034123] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kexec.target
612 10:06:12.360592 <31>[ 7.034335] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-systemd\x2dcryptsetup.slice
613 10:06:12.360812 <31>[ 7.034590] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timedated.service
614 10:06:12.361003 <31>[ 7.034818] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-device.target
615 10:06:12.361254 <31>[ 7.035054] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-parse-etc.service
616 10:06:12.361468 <31>[ 7.035276] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd.target
617 10:06:12.361644 <31>[ 7.035509] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.timer
618 10:06:12.361862 <31>[ 7.035767] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-binfmt.service
619 10:06:12.362426 <31>[ 7.036057] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/local-fs-pre.target
620 10:06:12.362622 <31>[ 7.036379] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.service
621 10:06:12.362850 <31>[ 7.036692] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/paths.target
622 10:06:12.363158 <31>[ 7.037090] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/modprobe@.service
623 10:06:12.364053 <31>[ 7.037663] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rc.service → /dev/null
624 10:06:12.364260 <31>[ 7.038029] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-static.service
625 10:06:12.365013 <31>[ 7.038657] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel2.target → multi-user.target
626 10:06:12.365401 <31>[ 7.039015] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-modules-load.service
627 10:06:12.365521 <31>[ 7.039429] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend.target
628 10:06:12.365970 <31>[ 7.039695] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-debug.mount
629 10:06:12.366353 <31>[ 7.040048] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysusers.service
630 10:06:12.366993 <31>[ 7.040690] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/default.target → graphical.target
631 10:06:12.367358 <31>[ 7.041191] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-poweroff.service
632 10:06:12.368004 <31>[ 7.041564] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.target
633 10:06:12.368134 <31>[ 7.041952] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysctl.service
634 10:06:12.368923 <31>[ 7.042686] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/procps.service → systemd-sysctl.service
635 10:06:12.369621 <31>[ 7.043121] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-time-wait-sync.service
636 10:06:12.369850 <31>[ 7.043505] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user@.service
637 10:06:12.370376 <31>[ 7.044188] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/udev.service → systemd-udevd.service
638 10:06:12.370856 <31>[ 7.044554] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-cleanup.service
639 10:06:12.371424 <31>[ 7.044888] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/nss-lookup.target
640 10:06:12.372031 <31>[ 7.045561] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/umount.target
641 10:06:12.372269 <31>[ 7.045935] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-udevadm-cleanup-db.service
642 10:06:12.372629 <31>[ 7.046326] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-tracing.mount
643 10:06:12.372868 <31>[ 7.046661] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.socket
644 10:06:12.373073 <31>[ 7.046915] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timesyncd.service
645 10:06:12.373666 <31>[ 7.047218] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.socket
646 10:06:12.373875 <31>[ 7.047507] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/printer.target
647 10:06:12.374086 <31>[ 7.047787] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-online.target
648 10:06:12.374293 <31>[ 7.048117] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/usb-gadget.target
649 10:06:12.374769 <31>[ 7.048457] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hybrid-sleep.service
650 10:06:12.375029 <31>[ 7.048802] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-reboot.service
651 10:06:12.375807 <31>[ 7.049467] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/quotaon.service
652 10:06:12.376265 <31>[ 7.050054] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/bluetooth.target
653 10:06:12.376734 <31>[ 7.050394] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rescue.service
654 10:06:12.376855 <31>[ 7.050696] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-backlight@.service
655 10:06:12.377475 <31>[ 7.051283] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks-early.service → /dev/null
656 10:06:12.377853 <31>[ 7.051624] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dev-hugepages.mount
657 10:06:12.378195 <31>[ 7.051949] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-cryptsetup.target
658 10:06:12.378563 <31>[ 7.052290] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-pstore.service
659 10:06:12.378963 <31>[ 7.052727] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/x11-common.service → /dev/null
660 10:06:12.380138 <31>[ 7.053653] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.locale1.service → systemd-localed.service
661 10:06:12.380267 <31>[ 7.054080] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/timers.target
662 10:06:12.380652 <31>[ 7.054405] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/proc-sys-fs-binfmt_misc.automount
663 10:06:12.381035 <31>[ 7.054770] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-console.service
664 10:06:12.381404 <31>[ 7.055121] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.socket
665 10:06:12.381551 <31>[ 7.055431] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user.slice
666 10:06:12.381922 <31>[ 7.055706] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup.service
667 10:06:12.382286 <31>[ 7.056030] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-fsck-root.service
668 10:06:12.382648 <31>[ 7.056354] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-quotacheck.service
669 10:06:12.382771 <31>[ 7.056651] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-kexec.service
670 10:06:12.383260 <31>[ 7.057170] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/graphical.target
671 10:06:12.383617 <31>[ 7.057471] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.timer
672 10:06:12.383993 <31>[ 7.057760] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/exit.target
673 10:06:12.384172 <31>[ 7.058015] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-fs.target
674 10:06:12.384621 <31>[ 7.058358] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-boot-system-token.service
675 10:06:12.385276 <31>[ 7.058862] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-varlink@.socket
676 10:06:12.385399 <31>[ 7.059189] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd.service
677 10:06:12.385762 <31>[ 7.059483] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rpcbind.target
678 10:06:12.386447 <31>[ 7.060199] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.hostname1.service → systemd-hostnamed.service
679 10:06:12.386842 <31>[ 7.060616] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/syslog.socket
680 10:06:12.387477 <31>[ 7.061193] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-user-sessions.service
681 10:06:12.387854 <31>[ 7.061582] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-volatile-root.service
682 10:06:12.388229 <31>[ 7.061911] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user-runtime-dir@.service
683 10:06:12.388347 <31>[ 7.062216] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kmod-static-nodes.service
684 10:06:12.388745 <31>[ 7.062501] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-logind.service
685 10:06:12.389113 <31>[ 7.062790] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-control.socket
686 10:06:12.389236 <31>[ 7.063101] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-bless-boot.service
687 10:06:12.389593 <31>[ 7.063421] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd.service
688 10:06:12.389959 <31>[ 7.063752] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journal-flush.service
689 10:06:12.390341 <31>[ 7.064141] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-pre.target
690 10:06:12.390716 <31>[ 7.064520] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty.target
691 10:06:12.391093 <31>[ 7.064899] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-network-generator.service
692 10:06:12.391821 <31>[ 7.065567] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update.target
693 10:06:12.392200 <31>[ 7.065904] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/multi-user.target
694 10:06:12.392589 <31>[ 7.066192] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend.service
695 10:06:12.392706 <31>[ 7.066524] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.service
696 10:06:12.393220 <31>[ 7.066819] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-cleanup.service
697 10:06:12.393345 <31>[ 7.067168] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/basic.target
698 10:06:12.393727 <31>[ 7.067493] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/emergency.target
699 10:06:12.394119 <31>[ 7.067822] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend-then-hibernate.service
700 10:06:12.394508 <31>[ 7.068210] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate-resume@.service
701 10:06:12.394905 <31>[ 7.068545] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-kernel.socket
702 10:06:12.397891 <31>[ 7.068842] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-dev-log.socket
703 10:06:12.398061 <31>[ 7.069290] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-machine-id-commit.service
704 10:06:12.398198 <31>[ 7.069551] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/serial-getty@.service
705 10:06:12.398322 <31>[ 7.069779] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.service
706 10:06:12.398472 <31>[ 7.070027] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_reap.service
707 10:06:12.398624 <31>[ 7.070253] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sockets.target
708 10:06:12.398752 <31>[ 7.070656] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks.service → /dev/null
709 10:06:12.398865 <31>[ 7.070932] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hybrid-sleep.target
710 10:06:12.398956 <31>[ 7.071525] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.login1.service → systemd-logind.service
711 10:06:12.399354 <31>[ 7.071839] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sleep.target
712 10:06:12.399491 <31>[ 7.072165] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate.service
713 10:06:12.399641 <31>[ 7.072404] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-halt.service
714 10:06:12.399785 <31>[ 7.072625] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/halt.target
715 10:06:12.399932 <31>[ 7.073367] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sigpwr.target
716 10:06:12.400105 <31>[ 7.073815] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup-dev.service
717 10:06:12.400295 <31>[ 7.074181] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sound.target
718 10:06:12.402127 <31>[ 7.074473] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/time-set.target
719 10:06:12.402257 <31>[ 7.074813] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udev-settle.service
720 10:06:12.402355 <31>[ 7.075185] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.socket
721 10:06:12.402453 <31>[ 7.075713] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/hwclock.service → /dev/null
722 10:06:12.402811 <31>[ 7.076254] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rcS.service → /dev/null
723 10:06:12.402933 <31>[ 7.076668] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hibernate.target
724 10:06:12.403641 <31>[ 7.077284] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-random-seed.service
725 10:06:12.404110 <31>[ 7.077709] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup.target
726 10:06:12.404275 <31>[ 7.078080] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/boot-complete.target
727 10:06:12.404707 <31>[ 7.078446] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/blockdev@.target
728 10:06:12.405163 <31>[ 7.078769] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd-wait-online.service
729 10:06:12.808524 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
730 10:06:12.812920 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
731 10:06:12.816606 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
732 10:06:12.820181 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
733 10:06:12.823933 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
734 10:06:12.825351 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
735 10:06:12.827669 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
736 10:06:12.828926 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
737 10:06:12.829467 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
738 10:06:12.830402 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
739 10:06:12.831390 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
740 10:06:12.834667 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
741 10:06:12.838679 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
742 10:06:12.841427 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
743 10:06:12.843732 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
744 10:06:12.845974 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
745 10:06:12.848978 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
746 10:06:12.850721 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
747 10:06:12.877252 Mounting [0;1;39mHuge Pages File System[0m...
748 10:06:12.912346 Mounting [0;1;39mPOSIX Message Queue File System[0m...
749 10:06:12.954383 Mounting [0;1;39mKernel Debug File System[0m...
750 10:06:12.993819 Starting [0;1;39mLoad Kernel Module configfs[0m...
751 10:06:13.040719 Starting [0;1;39mLoad Kernel Module drm[0m...
752 10:06:13.096780 Starting [0;1;39mJournal Service[0m...
753 10:06:13.128867 Starting [0;1;39mLoad Kernel Modules[0m...
754 10:06:13.168581 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
755 10:06:13.220591 Starting [0;1;39mColdplug All udev Devices[0m...
756 10:06:13.331497 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
757 10:06:13.338766 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
758 10:06:13.353014 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
759 10:06:13.400499 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
760 10:06:13.452290 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
761 10:06:13.478440 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
762 10:06:13.552805 Mounting [0;1;39mKernel Configuration File System[0m...
763 10:06:13.681225 Starting [0;1;39mApply Kernel Variables[0m...
764 10:06:13.754115 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
765 10:06:13.804609 <47>[ 8.478157] systemd-journald[109]: SELinux enabled state cached to: disabled
766 10:06:13.805743 <47>[ 8.479505] systemd-journald[109]: Auditing in kernel turned off.
767 10:06:13.826671 <47>[ 8.500488] systemd-journald[109]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
768 10:06:13.888369 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
769 10:06:13.892089 See 'systemctl status systemd-remount-fs.service' for details.
770 10:06:13.893506 <47>[ 8.567244] systemd-journald[109]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
771 10:06:13.909148 <47>[ 8.582636] systemd-journald[109]: Fixed min_use=3.8M max_use=19.3M max_size=2.4M min_size=512.0K keep_free=9.6M n_max_files=100
772 10:06:13.910577 <47>[ 8.584308] systemd-journald[109]: Reserving 333 entries in field hash table.
773 10:06:13.941304 Starting [0;1;39mLoad/Save Random Seed[0m...
774 10:06:13.948594 <47>[ 8.622194] systemd-journald[109]: Reserving 4408 entries in data hash table.
775 10:06:13.950273 <47>[ 8.624037] systemd-journald[109]: Vacuuming...
776 10:06:13.950925 <47>[ 8.624642] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
777 10:06:13.964413 <47>[ 8.638247] systemd-journald[109]: Flushing /dev/kmsg...
778 10:06:14.001084 Starting [0;1;39mCreate System Users[0m...
779 10:06:14.040079 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
780 10:06:14.148639 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
781 10:06:14.349660 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
782 10:06:14.377494 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
783 10:06:14.521730 <47>[ 9.195259] systemd-journald[109]: systemd-journald running as PID 109 for the system.
784 10:06:14.540128 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
785 10:06:14.547753 <47>[ 9.221396] systemd-journald[109]: Sent READY=1 notification.
786 10:06:14.548189 <47>[ 9.221974] systemd-journald[109]: Sent WATCHDOG=1 notification.
787 10:06:14.579289 <47>[ 9.252829] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
788 10:06:14.595288 <47>[ 9.268793] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
789 10:06:14.601250 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
790 10:06:14.622019 <47>[ 9.295810] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
791 10:06:14.647927 <47>[ 9.321463] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
792 10:06:14.661066 <47>[ 9.334629] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
793 10:06:14.666567 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
794 10:06:14.680493 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
795 10:06:14.682397 <47>[ 9.356081] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
796 10:06:14.688953 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
797 10:06:14.700601 <47>[ 9.374156] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
798 10:06:14.732716 <47>[ 9.406552] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
799 10:06:14.734990 <47>[ 9.408667] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
800 10:06:14.749774 <47>[ 9.423372] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
801 10:06:14.751175 <47>[ 9.424862] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
802 10:06:14.763793 <47>[ 9.437676] systemd-journald[109]: n/a: New incoming connection.
803 10:06:14.764356 <47>[ 9.438244] systemd-journald[109]: varlink-18: varlink: setting state idle-server
804 10:06:14.780786 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
805 10:06:14.784888 <47>[ 9.458620] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
806 10:06:14.787199 <47>[ 9.460739] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
807 10:06:14.802606 <47>[ 9.476142] systemd-journald[109]: varlink-18: New incoming message: {\"method\":\"io.systemd.Journal.FlushToVar\",\"parameters\":{}}
808 10:06:14.814937 <47>[ 9.488668] systemd-journald[109]: varlink-18: varlink: changing state idle-server → processing-method
809 10:06:14.816749 <46>[ 9.490495] systemd-journald[109]: Received client request to flush runtime journal.
810 10:06:14.817187 <47>[ 9.491005] systemd-journald[109]: Journal effective settings seal=yes keyed_hash=no compress=yes compress_threshold_bytes=512B
811 10:06:14.818215 <47>[ 9.491902] systemd-journald[109]: Vacuuming...
812 10:06:14.818708 <47>[ 9.492497] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
813 10:06:14.828532 <47>[ 9.502159] systemd-journald[109]: varlink-18: Sending message: {\"parameters\":{}}
814 10:06:14.828711 <47>[ 9.502464] systemd-journald[109]: varlink-18: varlink: changing state processing-method → processed-method
815 10:06:14.829070 <47>[ 9.502806] systemd-journald[109]: varlink-18: varlink: changing state processed-method → idle-server
816 10:06:14.844190 <47>[ 9.517605] systemd-journald[109]: varlink-18: varlink: changing state idle-server → pending-disconnect
817 10:06:14.844534 <47>[ 9.518007] systemd-journald[109]: varlink-18: varlink: changing state pending-disconnect → processing-disconnect
818 10:06:14.844768 <47>[ 9.518283] systemd-journald[109]: varlink-18: varlink: changing state processing-disconnect → disconnected
819 10:06:14.861758 <47>[ 9.534443] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
820 10:06:14.864075 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
821 10:06:14.873502 <47>[ 9.547075] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
822 10:06:14.928995 Starting [0;1;39mCreate Volatile Files and Directories[0m...
823 10:06:14.933605 <47>[ 9.607283] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
824 10:06:15.386906 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
825 10:06:15.477042 Starting [0;1;39mNetwork Service[0m...
826 10:06:15.509727 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
827 10:06:15.526448 <47>[ 10.200243] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
828 10:06:15.617470 Starting [0;1;39mNetwork Time Synchronization[0m...
829 10:06:15.638132 <47>[ 10.311895] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
830 10:06:15.689316 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
831 10:06:15.730766 <47>[ 10.404577] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
832 10:06:16.193447 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
833 10:06:17.178699 <47>[ 11.852199] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3307 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
834 10:06:17.179225 <47>[ 11.852730] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
835 10:06:17.195417 <47>[ 11.869246] systemd-journald[109]: Rotating...
836 10:06:17.196466 <47>[ 11.870226] systemd-journald[109]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
837 10:06:17.197901 <47>[ 11.871653] systemd-journald[109]: Reserving 333 entries in field hash table.
838 10:06:17.223606 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
839 10:06:17.246496 <47>[ 11.920301] systemd-journald[109]: Reserving 4408 entries in data hash table.
840 10:06:17.273431 <47>[ 11.947321] systemd-journald[109]: Vacuuming...
841 10:06:17.295900 <47>[ 11.969458] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
842 10:06:17.355985 Starting [0;1;39mNetwork Name Resolution[0m...
843 10:06:17.391681 <47>[ 12.065471] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
844 10:06:17.733456 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
845 10:06:17.735935 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
846 10:06:17.741503 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
847 10:06:18.238002 <47>[ 12.911766] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
848 10:06:19.547774 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
849 10:06:19.557773 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
850 10:06:19.577508 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
851 10:06:19.590792 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
852 10:06:19.602418 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
853 10:06:19.609517 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
854 10:06:19.637591 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
855 10:06:19.638322 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
856 10:06:19.639052 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
857 10:06:19.729298 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
858 10:06:19.737659 <47>[ 14.411314] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
859 10:06:19.852613 <47>[ 14.526204] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
860 10:06:19.859970 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
861 10:06:20.037936 Starting [0;1;39mUser Login Management[0m...
862 10:06:20.053800 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
863 10:06:20.061784 <47>[ 14.735482] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
864 10:06:20.070666 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
865 10:06:20.090331 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
866 10:06:20.169735 Starting [0;1;39mPermit User Sessions[0m...
867 10:06:20.194136 <47>[ 14.867760] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
868 10:06:20.464469 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
869 10:06:20.545538 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
870 10:06:20.753203 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
871 10:06:21.163289 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
872 10:06:23.313749 [[0m[0;31m* [0m] A start job is running for /dev/ttyAMA0 (10s / 1min 30s)
873 10:06:23.636972 M[K[[0;32m OK [0m] Found device [0;1;39m/dev/ttyAMA0[0m.
874 10:06:23.702061 [K[[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyAMA0[0m.
875 10:06:23.724294 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
876 10:06:23.736994 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
877 10:06:23.754062 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
878 10:06:23.804139 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
879 10:06:23.813462 <47>[ 18.487107] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
880 10:06:24.026174 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
881 10:06:24.058047 <47>[ 18.731633] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
882 10:06:24.077984 <47>[ 18.751548] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
883 10:06:24.153671
884 10:06:24.154292 Debian GNU/Linux 11 debian-bullseye-arm64 ttyAMA0
885 10:06:24.154463
886 10:06:24.154617 debian-bullseye-arm64 login: root (automatic login)
887 10:06:24.154744
888 10:06:24.354040 <6>[ 19.027731] virtio_net virtio0 enp0s1: renamed from eth0
889 10:06:24.379706 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023 aarch64
890 10:06:24.380005
891 10:06:24.380223 The programs included with the Debian GNU/Linux system are free software;
892 10:06:24.380396 the exact distribution terms for each program are described in the
893 10:06:24.380571 individual files in /usr/share/doc/*/copyright.
894 10:06:24.380706
895 10:06:24.380831 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
896 10:06:24.380961 permitted by applicable law.
897 10:06:24.986832 <47>[ 19.660385] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
898 10:06:25.021087 <47>[ 19.694600] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.1 (3310 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
899 10:06:25.021589 <47>[ 19.695248] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
900 10:06:25.021969 <47>[ 19.695717] systemd-journald[109]: Rotating...
901 10:06:25.031945 <47>[ 19.705658] systemd-journald[109]: Reserving 333 entries in field hash table.
902 10:06:25.056203 <47>[ 19.729809] systemd-journald[109]: Reserving 4408 entries in data hash table.
903 10:06:25.067487 <47>[ 19.741449] systemd-journald[109]: Vacuuming...
904 10:06:25.068960 <47>[ 19.742710] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
905 10:06:25.252977 <47>[ 19.926531] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
906 10:06:26.937726 <47>[ 21.611494] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
907 10:06:27.492245 Matched prompt #10: / #
909 10:06:27.492813 Setting prompt string to ['/ #']
910 10:06:27.492995 end: 2.2.1 login-action (duration 00:00:22) [common]
912 10:06:27.493403 end: 2.2 auto-login-action (duration 00:00:25) [common]
913 10:06:27.493573 start: 2.3 expect-shell-connection (timeout 00:04:34) [common]
914 10:06:27.493722 Setting prompt string to ['/ #']
915 10:06:27.493844 Forcing a shell prompt, looking for ['/ #']
917 10:06:27.544367 / #
918 10:06:27.544539 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
919 10:06:27.544690 Waiting using forced prompt support (timeout 00:02:30)
920 10:06:27.546251
921 10:06:27.550901 end: 2.3 expect-shell-connection (duration 00:00:00) [common]
922 10:06:27.551107 start: 2.4 export-device-env (timeout 00:04:34) [common]
923 10:06:27.551278 end: 2.4 export-device-env (duration 00:00:00) [common]
924 10:06:27.551438 end: 2 boot-image-retry (duration 00:00:26) [common]
925 10:06:27.551597 start: 3 lava-test-retry (timeout 00:08:47) [common]
926 10:06:27.551755 start: 3.1 lava-test-shell (timeout 00:08:47) [common]
927 10:06:27.551893 Using namespace: common
929 10:06:27.652747 / # #
930 10:06:27.653044 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
931 10:06:27.653715 #
933 10:06:27.762714 / # mkdir /lava-592431
934 10:06:27.763715 mkdir /lava-592431
936 10:06:27.894466 / # mount /dev/disk/by-uuid/1a11af02-87d3-48ca-a4ee-61a19168a20c -t ext2 /lava-592431
937 10:06:27.895410 mount /dev/disk/by-uuid/1a11af02-87d3-48ca-a4ee-61a19168a20c -t ext2 /lava-592431
938 10:06:27.926286 <4>[ 22.599512] ext2 filesystem being mounted at /lava-592431 supports timestamps until 2038 (0x7fffffff)
940 10:06:28.068564 / # ls -la /lava-592431/bin/lava-test-runner
941 10:06:28.069676 ls -la /lava-592431/bin/lava-test-runner
942 10:06:28.110671 -rwxr-xr-x 1 root root 1039 Jun 10 10:05 /lava-592431/bin/lava-test-runner
943 10:06:28.122937 Using /lava-592431
945 10:06:28.224045 / # export SHELL=/bin/sh
946 10:06:28.225314 export SHELL=/bin/sh
948 10:06:28.335899 / # . /lava-592431/environment
949 10:06:28.336973 . /lava-592431/environment
951 10:06:28.449637 / # /lava-592431/bin/lava-test-runner /lava-592431/0
952 10:06:28.449905 Test shell timeout: 10s (minimum of the action and connection timeout)
953 10:06:28.450591 /lava-592431/bin/lava-test-runner /lava-592431/0
954 10:06:28.607113 + export TESTRUN_ID=0_timesync-off
955 10:06:28.607440 + cd /lava-592431/0/tests/0_timesync-off
956 10:06:28.609790 + cat uuid
957 10:06:28.618598 + UUID=592431_1.1.3.1
958 10:06:28.618730 + set +x
959 10:06:28.619132 <LAVA_SIGNAL_STARTRUN 0_timesync-off 592431_1.1.3.1>
960 10:06:28.619528 Received signal: <STARTRUN> 0_timesync-off 592431_1.1.3.1
961 10:06:28.619741 Starting test lava.0_timesync-off (592431_1.1.3.1)
962 10:06:28.619947 Skipping test definition patterns.
963 10:06:28.620192 + systemctl stop systemd-timesyncd
964 10:06:28.880253 + set +x
965 10:06:28.880764 <LAVA_SIGNAL_ENDRUN 0_timesync-off 592431_1.1.3.1>
966 10:06:28.881139 Received signal: <ENDRUN> 0_timesync-off 592431_1.1.3.1
967 10:06:28.881320 Ending use of test pattern.
968 10:06:28.881466 Ending test lava.0_timesync-off (592431_1.1.3.1), duration 0.26
970 10:06:28.925412 + export TESTRUN_ID=1_kselftest-arm64_qemu
971 10:06:28.925897 + cd /lava-592431/0/tests/1_kselftest-arm64_qemu
972 10:06:28.929013 + cat uuid
973 10:06:28.937484 + UUID=592431_1.1.3.5
974 10:06:28.937742 + set +x
975 10:06:28.938117 Received signal: <STARTRUN> 1_kselftest-arm64_qemu 592431_1.1.3.5
976 10:06:28.938229 Starting test lava.1_kselftest-arm64_qemu (592431_1.1.3.5)
977 10:06:28.938338 Skipping test definition patterns.
978 10:06:28.938471 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64_qemu 592431_1.1.3.5>
979 10:06:28.938563 + cd ./automated/linux/kselftest/
980 10:06:28.942977 + ./kselftest.sh -c arm64 -T -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L -S /dev/null -b qemu_arm64-virt-gicv3 -g cip -e -p /opt/kselftests/mainline/ -n 1 -i 1
981 10:06:29.041327 INFO: install_deps skipped
982 10:06:29.074884 --2023-06-10 10:06:28-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
983 10:06:29.227640 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
984 10:06:29.429659 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
985 10:06:29.617469 HTTP request sent, awaiting response... 200 OK
986 10:06:29.620390 Length: 2883260 (2.7M) [application/octet-stream]
987 10:06:29.621763 Saving to: 'kselftest.tar.xz'
988 10:06:29.623093
989 10:06:30.871870 kselftest.tar.xz 0%[ ] 0 --.-KB/s kselftest.tar.xz 1%[ ] 50.15K 152KB/s kselftest.tar.xz 7%[> ] 219.84K 324KB/s kselftest.tar.xz 31%[=====> ] 894.35K 874KB/s kselftest.tar.xz 72%[=============> ] 1.99M 1.62MB/s kselftest.tar.xz 100%[===================>] 2.75M 2.18MB/s in 1.3s
990 10:06:30.872193
991 10:06:30.881800 2023-06-10 10:06:30 (2.18 MB/s) - 'kselftest.tar.xz' saved [2883260/2883260]
992 10:06:30.881933
993 10:06:34.069992 skiplist:
994 10:06:34.070495 ========================================
995 10:06:34.070706 ========================================
996 10:06:34.126435 arm64:tags_test
997 10:06:34.126737 arm64:run_tags_test.sh
998 10:06:34.126962 arm64:fake_sigreturn_bad_magic
999 10:06:34.127131 arm64:fake_sigreturn_bad_size
1000 10:06:34.127499 arm64:fake_sigreturn_bad_size_for_magic0
1001 10:06:34.127704 arm64:fake_sigreturn_duplicated_fpsimd
1002 10:06:34.127865 arm64:fake_sigreturn_misaligned_sp
1003 10:06:34.128008 arm64:fake_sigreturn_missing_fpsimd
1004 10:06:34.128225 arm64:fake_sigreturn_sme_change_vl
1005 10:06:34.128437 arm64:fake_sigreturn_sve_change_vl
1006 10:06:34.128649 arm64:mangle_pstate_invalid_compat_toggle
1007 10:06:34.128886 arm64:mangle_pstate_invalid_daif_bits
1008 10:06:34.129153 arm64:mangle_pstate_invalid_mode_el1h
1009 10:06:34.129369 arm64:mangle_pstate_invalid_mode_el1t
1010 10:06:34.129608 arm64:mangle_pstate_invalid_mode_el2h
1011 10:06:34.129837 arm64:mangle_pstate_invalid_mode_el2t
1012 10:06:34.130053 arm64:mangle_pstate_invalid_mode_el3h
1013 10:06:34.130201 arm64:mangle_pstate_invalid_mode_el3t
1014 10:06:34.130323 arm64:sme_trap_no_sm
1015 10:06:34.130439 arm64:sme_trap_non_streaming
1016 10:06:34.130554 arm64:sme_trap_za
1017 10:06:34.130667 arm64:sme_vl
1018 10:06:34.130782 arm64:ssve_regs
1019 10:06:34.130896 arm64:sve_regs
1020 10:06:34.131010 arm64:sve_vl
1021 10:06:34.131123 arm64:za_no_regs
1022 10:06:34.131235 arm64:za_regs
1023 10:06:34.131349 arm64:pac
1024 10:06:34.131465 arm64:fp-stress
1025 10:06:34.131591 arm64:sve-ptrace
1026 10:06:34.131711 arm64:sve-probe-vls
1027 10:06:34.131827 arm64:vec-syscfg
1028 10:06:34.131979 arm64:za-fork
1029 10:06:34.132102 arm64:za-ptrace
1030 10:06:34.132217 arm64:check_buffer_fill
1031 10:06:34.132331 arm64:check_child_memory
1032 10:06:34.132444 arm64:check_gcr_el1_cswitch
1033 10:06:34.132556 arm64:check_ksm_options
1034 10:06:34.132673 arm64:check_mmap_options
1035 10:06:34.132786 arm64:check_prctl
1036 10:06:34.132899 arm64:check_tags_inclusion
1037 10:06:34.133011 arm64:check_user_mem
1038 10:06:34.133124 arm64:btitest
1039 10:06:34.133236 arm64:nobtitest
1040 10:06:34.133348 arm64:hwcap
1041 10:06:34.133460 arm64:ptrace
1042 10:06:34.133573 arm64:syscall-abi
1043 10:06:34.133706 arm64:tpidr2
1044 10:06:34.143841 ============== Tests to run ===============
1045 10:06:34.149496 arm64:tags_test
1046 10:06:34.149823 arm64:run_tags_test.sh
1047 10:06:34.150004 arm64:fake_sigreturn_bad_magic
1048 10:06:34.150183 arm64:fake_sigreturn_bad_size
1049 10:06:34.150688 arm64:fake_sigreturn_bad_size_for_magic0
1050 10:06:34.150887 arm64:fake_sigreturn_duplicated_fpsimd
1051 10:06:34.151060 arm64:fake_sigreturn_misaligned_sp
1052 10:06:34.151207 arm64:fake_sigreturn_missing_fpsimd
1053 10:06:34.151366 arm64:fake_sigreturn_sme_change_vl
1054 10:06:34.151537 arm64:fake_sigreturn_sve_change_vl
1055 10:06:34.151723 arm64:mangle_pstate_invalid_compat_toggle
1056 10:06:34.151880 arm64:mangle_pstate_invalid_daif_bits
1057 10:06:34.152033 arm64:mangle_pstate_invalid_mode_el1h
1058 10:06:34.152185 arm64:mangle_pstate_invalid_mode_el1t
1059 10:06:34.152387 arm64:mangle_pstate_invalid_mode_el2h
1060 10:06:34.152558 arm64:mangle_pstate_invalid_mode_el2t
1061 10:06:34.152725 arm64:mangle_pstate_invalid_mode_el3h
1062 10:06:34.152888 arm64:mangle_pstate_invalid_mode_el3t
1063 10:06:34.153032 arm64:sme_trap_no_sm
1064 10:06:34.153148 arm64:sme_trap_non_streaming
1065 10:06:34.153260 arm64:sme_trap_za
1066 10:06:34.153373 arm64:sme_vl
1067 10:06:34.153485 arm64:ssve_regs
1068 10:06:34.153595 arm64:sve_regs
1069 10:06:34.153787 arm64:sve_vl
1070 10:06:34.153981 arm64:za_no_regs
1071 10:06:34.154164 arm64:za_regs
1072 10:06:34.154330 arm64:pac
1073 10:06:34.154470 arm64:fp-stress
1074 10:06:34.154610 arm64:sve-ptrace
1075 10:06:34.154785 arm64:sve-probe-vls
1076 10:06:34.154955 arm64:vec-syscfg
1077 10:06:34.155134 arm64:za-fork
1078 10:06:34.155305 arm64:za-ptrace
1079 10:06:34.155448 arm64:check_buffer_fill
1080 10:06:34.155589 arm64:check_child_memory
1081 10:06:34.155778 arm64:check_gcr_el1_cswitch
1082 10:06:34.155913 arm64:check_ksm_options
1083 10:06:34.156054 arm64:check_mmap_options
1084 10:06:34.156196 arm64:check_prctl
1085 10:06:34.156337 arm64:check_tags_inclusion
1086 10:06:34.156477 arm64:check_user_mem
1087 10:06:34.156618 arm64:btitest
1088 10:06:34.156758 arm64:nobtitest
1089 10:06:34.156899 arm64:hwcap
1090 10:06:34.157039 arm64:ptrace
1091 10:06:34.157178 arm64:syscall-abi
1092 10:06:34.157318 arm64:tpidr2
1093 10:06:34.157458 ===========End Tests to run ===============
1094 10:06:35.046730 <12>[ 29.720516] kselftest: Running tests in arm64
1095 10:06:35.074327 TAP version 13
1096 10:06:35.092002 1..48
1097 10:06:35.137900 # selftests: arm64: tags_test
1098 10:06:35.190086 ok 1 selftests: arm64: tags_test
1099 10:06:35.236369 # selftests: arm64: run_tags_test.sh
1100 10:06:35.285337 # --------------------
1101 10:06:35.285854 # running tags test
1102 10:06:35.286014 # --------------------
1103 10:06:35.286166 # [PASS]
1104 10:06:35.290953 ok 2 selftests: arm64: run_tags_test.sh
1105 10:06:35.337183 # selftests: arm64: fake_sigreturn_bad_magic
1106 10:06:35.388323 # Registered handlers for all signals.
1107 10:06:35.388659 # Detected MINSTKSIGSZ:10000
1108 10:06:35.389138 # Testcase initialized.
1109 10:06:35.389328 # uc context validated.
1110 10:06:35.389517 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1111 10:06:35.389675 # Handled SIG_COPYCTX
1112 10:06:35.389803 # Available space:3536
1113 10:06:35.389926 # Using badly built context - ERR: BAD MAGIC !
1114 10:06:35.390055 # SIG_OK -- SP:0xFFFFF6048910 si_addr@:0xfffff6048910 si_code:2 token@:0xfffff60476b0 offset:-4704
1115 10:06:35.390180 # ==>> completed. PASS(1)
1116 10:06:35.390330 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
1117 10:06:35.390462 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF60476B0
1118 10:06:35.397389 ok 3 selftests: arm64: fake_sigreturn_bad_magic
1119 10:06:35.464551 # selftests: arm64: fake_sigreturn_bad_size
1120 10:06:35.513262 # Registered handlers for all signals.
1121 10:06:35.513911 # Detected MINSTKSIGSZ:10000
1122 10:06:35.514155 # Testcase initialized.
1123 10:06:35.514370 # uc context validated.
1124 10:06:35.514585 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1125 10:06:35.514722 # Handled SIG_COPYCTX
1126 10:06:35.514839 # Available space:3536
1127 10:06:35.514953 # uc context validated.
1128 10:06:35.515092 # Using badly built context - ERR: Bad size for esr_context
1129 10:06:35.515211 # SIG_OK -- SP:0xFFFFFC63B890 si_addr@:0xfffffc63b890 si_code:2 token@:0xfffffc63a630 offset:-4704
1130 10:06:35.515326 # ==>> completed. PASS(1)
1131 10:06:35.515437 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
1132 10:06:35.515549 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFC63A630
1133 10:06:35.522154 ok 4 selftests: arm64: fake_sigreturn_bad_size
1134 10:06:35.567521 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
1135 10:06:35.616770 # Registered handlers for all signals.
1136 10:06:35.617052 # Detected MINSTKSIGSZ:10000
1137 10:06:35.617190 # Testcase initialized.
1138 10:06:35.617549 # uc context validated.
1139 10:06:35.617701 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1140 10:06:35.617829 # Handled SIG_COPYCTX
1141 10:06:35.617953 # Available space:3536
1142 10:06:35.618077 # Using badly built context - ERR: Bad size for terminator
1143 10:06:35.618201 # SIG_OK -- SP:0xFFFFEB6F50A0 si_addr@:0xffffeb6f50a0 si_code:2 token@:0xffffeb6f3e40 offset:-4704
1144 10:06:35.618328 # ==>> completed. PASS(1)
1145 10:06:35.618451 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
1146 10:06:35.618576 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEB6F3E40
1147 10:06:35.625269 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
1148 10:06:35.670626 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
1149 10:06:35.719603 # Registered handlers for all signals.
1150 10:06:35.719889 # Detected MINSTKSIGSZ:10000
1151 10:06:35.720013 # Testcase initialized.
1152 10:06:35.720427 # uc context validated.
1153 10:06:35.720604 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1154 10:06:35.720736 # Handled SIG_COPYCTX
1155 10:06:35.720858 # Available space:3536
1156 10:06:35.720980 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
1157 10:06:35.721104 # SIG_OK -- SP:0xFFFFE8B5F050 si_addr@:0xffffe8b5f050 si_code:2 token@:0xffffe8b5ddf0 offset:-4704
1158 10:06:35.721229 # ==>> completed. PASS(1)
1159 10:06:35.721378 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
1160 10:06:35.721509 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE8B5DDF0
1161 10:06:35.729285 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
1162 10:06:35.773249 # selftests: arm64: fake_sigreturn_misaligned_sp
1163 10:06:35.821513 # Registered handlers for all signals.
1164 10:06:35.822155 # Detected MINSTKSIGSZ:10000
1165 10:06:35.822381 # Testcase initialized.
1166 10:06:35.822589 # uc context validated.
1167 10:06:35.822731 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1168 10:06:35.822850 # Handled SIG_COPYCTX
1169 10:06:35.822963 # SIG_OK -- SP:0xFFFFF763D973 si_addr@:0xfffff763d973 si_code:2 token@:0xfffff763d973 offset:0
1170 10:06:35.823101 # ==>> completed. PASS(1)
1171 10:06:35.823219 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
1172 10:06:35.823333 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF763D973
1173 10:06:35.830438 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
1174 10:06:35.874790 # selftests: arm64: fake_sigreturn_missing_fpsimd
1175 10:06:35.925394 # Registered handlers for all signals.
1176 10:06:35.925656 # Detected MINSTKSIGSZ:10000
1177 10:06:35.925749 # Testcase initialized.
1178 10:06:35.925838 # uc context validated.
1179 10:06:35.926138 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1180 10:06:35.926241 # Handled SIG_COPYCTX
1181 10:06:35.926333 # Mangling template header. Spare space:4096
1182 10:06:35.926424 # Using badly built context - ERR: Missing FPSIMD
1183 10:06:35.928343 # SIG_OK -- SP:0xFFFFE589A290 si_addr@:0xffffe589a290 si_code:2 token@:0xffffe5899030 offset:-4704
1184 10:06:35.928454 # ==>> completed. PASS(1)
1185 10:06:35.928558 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
1186 10:06:35.928661 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE5899030
1187 10:06:35.935801 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
1188 10:06:35.980372 # selftests: arm64: fake_sigreturn_sme_change_vl
1189 10:06:36.029417 # Registered handlers for all signals.
1190 10:06:36.029897 # Detected MINSTKSIGSZ:10000
1191 10:06:36.030003 # Required Features: [ SME ] supported
1192 10:06:36.030092 # Incompatible Features: [] absent
1193 10:06:36.030175 # Testcase initialized.
1194 10:06:36.030257 # uc context validated.
1195 10:06:36.030350 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1196 10:06:36.030452 # Handled SIG_COPYCTX
1197 10:06:36.030534 # Attempting to change VL from 16 to 256
1198 10:06:36.030618 # SIG_OK -- SP:0xFFFFE7EECCA0 si_addr@:0xffffe7eecca0 si_code:2 token@:0xffffe7eeba40 offset:-4704
1199 10:06:36.030717 # ==>> completed. PASS(1)
1200 10:06:36.030802 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
1201 10:06:36.030901 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE7EEBA40
1202 10:06:36.039323 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl
1203 10:06:36.083032 # selftests: arm64: fake_sigreturn_sve_change_vl
1204 10:06:36.130942 # Registered handlers for all signals.
1205 10:06:36.131452 # Detected MINSTKSIGSZ:10000
1206 10:06:36.131661 # Required Features: [ SVE ] supported
1207 10:06:36.131836 # Incompatible Features: [] absent
1208 10:06:36.132048 # Testcase initialized.
1209 10:06:36.132202 # uc context validated.
1210 10:06:36.132322 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1211 10:06:36.132466 # Handled SIG_COPYCTX
1212 10:06:36.132584 # Attempting to change VL from 16 to 256
1213 10:06:36.132696 # SIG_OK -- SP:0xFFFFC48E0BB0 si_addr@:0xffffc48e0bb0 si_code:2 token@:0xffffc48df950 offset:-4704
1214 10:06:36.132810 # ==>> completed. PASS(1)
1215 10:06:36.132920 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
1216 10:06:36.133032 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC48DF950
1217 10:06:36.139654 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl
1218 10:06:36.184060 # selftests: arm64: mangle_pstate_invalid_compat_toggle
1219 10:06:36.231817 # Registered handlers for all signals.
1220 10:06:36.232078 # Detected MINSTKSIGSZ:10000
1221 10:06:36.232203 # Testcase initialized.
1222 10:06:36.232318 # uc context validated.
1223 10:06:36.233746 # Handled SIG_TRIG
1224 10:06:36.234187 # SIG_OK -- SP:0xFFFFEBCED780 si_addr@:0xffffebced780 si_code:2 token@:(nil) offset:-281474637944704
1225 10:06:36.234375 # ==>> completed. PASS(1)
1226 10:06:36.234579 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
1227 10:06:36.240694 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
1228 10:06:36.284071 # selftests: arm64: mangle_pstate_invalid_daif_bits
1229 10:06:36.331724 # Registered handlers for all signals.
1230 10:06:36.332047 # Detected MINSTKSIGSZ:10000
1231 10:06:36.332237 # Testcase initialized.
1232 10:06:36.332645 # uc context validated.
1233 10:06:36.332780 # Handled SIG_TRIG
1234 10:06:36.332901 # SIG_OK -- SP:0xFFFFDAEE1540 si_addr@:0xffffdaee1540 si_code:2 token@:(nil) offset:-281474354779456
1235 10:06:36.333018 # ==>> completed. PASS(1)
1236 10:06:36.333132 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
1237 10:06:36.340472 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
1238 10:06:36.387701 # selftests: arm64: mangle_pstate_invalid_mode_el1h
1239 10:06:36.437222 # Registered handlers for all signals.
1240 10:06:36.437567 # Detected MINSTKSIGSZ:10000
1241 10:06:36.437767 # Testcase initialized.
1242 10:06:36.437903 # uc context validated.
1243 10:06:36.438246 # Handled SIG_TRIG
1244 10:06:36.438377 # SIG_OK -- SP:0xFFFFCFE8D000 si_addr@:0xffffcfe8d000 si_code:2 token@:(nil) offset:-281474169884672
1245 10:06:36.438499 # ==>> completed. PASS(1)
1246 10:06:36.438617 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
1247 10:06:36.445184 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
1248 10:06:36.488607 # selftests: arm64: mangle_pstate_invalid_mode_el1t
1249 10:06:36.534525 # Registered handlers for all signals.
1250 10:06:36.534768 # Detected MINSTKSIGSZ:10000
1251 10:06:36.535073 # Testcase initialized.
1252 10:06:36.535178 # uc context validated.
1253 10:06:36.535272 # Handled SIG_TRIG
1254 10:06:36.535359 # SIG_OK -- SP:0xFFFFC7A599E0 si_addr@:0xffffc7a599e0 si_code:2 token@:(nil) offset:-281474031262176
1255 10:06:36.535441 # ==>> completed. PASS(1)
1256 10:06:36.535536 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
1257 10:06:36.543876 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
1258 10:06:36.587623 # selftests: arm64: mangle_pstate_invalid_mode_el2h
1259 10:06:36.633930 # Registered handlers for all signals.
1260 10:06:36.634267 # Detected MINSTKSIGSZ:10000
1261 10:06:36.634511 # Testcase initialized.
1262 10:06:36.634676 # uc context validated.
1263 10:06:36.635027 # Handled SIG_TRIG
1264 10:06:36.635155 # SIG_OK -- SP:0xFFFFC1CB8440 si_addr@:0xffffc1cb8440 si_code:2 token@:(nil) offset:-281473933083712
1265 10:06:36.635274 # ==>> completed. PASS(1)
1266 10:06:36.635391 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
1267 10:06:36.642974 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
1268 10:06:36.687741 # selftests: arm64: mangle_pstate_invalid_mode_el2t
1269 10:06:36.733399 # Registered handlers for all signals.
1270 10:06:36.733781 # Detected MINSTKSIGSZ:10000
1271 10:06:36.734205 # Testcase initialized.
1272 10:06:36.734366 # uc context validated.
1273 10:06:36.734494 # Handled SIG_TRIG
1274 10:06:36.734616 # SIG_OK -- SP:0xFFFFD3FEFE50 si_addr@:0xffffd3fefe50 si_code:2 token@:(nil) offset:-281474238447184
1275 10:06:36.734737 # ==>> completed. PASS(1)
1276 10:06:36.734853 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
1277 10:06:36.742630 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
1278 10:06:36.786504 # selftests: arm64: mangle_pstate_invalid_mode_el3h
1279 10:06:36.832679 # Registered handlers for all signals.
1280 10:06:36.833035 # Detected MINSTKSIGSZ:10000
1281 10:06:36.833463 # Testcase initialized.
1282 10:06:36.833613 # uc context validated.
1283 10:06:36.833753 # Handled SIG_TRIG
1284 10:06:36.833873 # SIG_OK -- SP:0xFFFFF5975780 si_addr@:0xfffff5975780 si_code:2 token@:(nil) offset:-281474802079616
1285 10:06:36.833995 # ==>> completed. PASS(1)
1286 10:06:36.834111 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
1287 10:06:36.841315 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
1288 10:06:36.885918 # selftests: arm64: mangle_pstate_invalid_mode_el3t
1289 10:06:36.932238 # Registered handlers for all signals.
1290 10:06:36.932591 # Detected MINSTKSIGSZ:10000
1291 10:06:36.932773 # Testcase initialized.
1292 10:06:36.933131 # uc context validated.
1293 10:06:36.933262 # Handled SIG_TRIG
1294 10:06:36.933380 # SIG_OK -- SP:0xFFFFC05D2290 si_addr@:0xffffc05d2290 si_code:2 token@:(nil) offset:-281473909072528
1295 10:06:36.933499 # ==>> completed. PASS(1)
1296 10:06:36.933615 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
1297 10:06:36.940311 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
1298 10:06:36.983976 # selftests: arm64: sme_trap_no_sm
1299 10:06:37.092695 # Registered handlers for all signals.
1300 10:06:37.092995 # Detected MINSTKSIGSZ:10000
1301 10:06:37.093398 # Required Features: [ SME ] supported
1302 10:06:37.093508 # Incompatible Features: [] absent
1303 10:06:37.093603 # Testcase initialized.
1304 10:06:37.093702 # SIG_OK -- SP:0xFFFFC5BA45B0 si_addr@:0xaaaac8ec2514 si_code:1 token@:(nil) offset:-187650492081428
1305 10:06:37.093792 # ==>> completed. PASS(1)
1306 10:06:37.093896 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
1307 10:06:37.111302 ok 19 selftests: arm64: sme_trap_no_sm
1308 10:06:37.200554 # selftests: arm64: sme_trap_non_streaming
1309 10:06:37.258594 # Registered handlers for all signals.
1310 10:06:37.258826 # Detected MINSTKSIGSZ:10000
1311 10:06:37.258916 # Required Features: [] NOT supported
1312 10:06:37.259208 # Incompatible Features: [] supported
1313 10:06:37.259302 # ==>> completed. SKIP.
1314 10:06:37.259388 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
1315 10:06:37.267262 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
1316 10:06:37.315522 # selftests: arm64: sme_trap_za
1317 10:06:37.364108 # Registered handlers for all signals.
1318 10:06:37.364537 # Detected MINSTKSIGSZ:10000
1319 10:06:37.364653 # Testcase initialized.
1320 10:06:37.364751 # SIG_OK -- SP:0xFFFFD4533660 si_addr@:0xaaaae5702510 si_code:1 token@:(nil) offset:-187650970494224
1321 10:06:37.364848 # ==>> completed. PASS(1)
1322 10:06:37.364952 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
1323 10:06:37.372401 ok 21 selftests: arm64: sme_trap_za
1324 10:06:37.417468 # selftests: arm64: sme_vl
1325 10:06:37.467145 # Registered handlers for all signals.
1326 10:06:37.467469 # Detected MINSTKSIGSZ:10000
1327 10:06:37.467677 # Required Features: [ SME ] supported
1328 10:06:37.467819 # Incompatible Features: [] absent
1329 10:06:37.468164 # Testcase initialized.
1330 10:06:37.468292 # uc context validated.
1331 10:06:37.468406 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1332 10:06:37.468519 # Handled SIG_COPYCTX
1333 10:06:37.468630 # got expected VL 32
1334 10:06:37.468742 # ==>> completed. PASS(1)
1335 10:06:37.468853 # # SME VL :: Check that we get the right SME VL reported
1336 10:06:37.475250 ok 22 selftests: arm64: sme_vl
1337 10:06:37.520195 # selftests: arm64: ssve_regs
1338 10:06:37.699475 # Registered handlers for all signals.
1339 10:06:37.699744 # Detected MINSTKSIGSZ:10000
1340 10:06:37.701135 # Required Features: [ SME FA64 ] supported
1341 10:06:37.701512 # Incompatible Features: [] absent
1342 10:06:37.701773 # Testcase initialized.
1343 10:06:37.701956 # Testing VL 256
1344 10:06:37.702101 # Validating EXTRA...
1345 10:06:37.702261 # uc context validated.
1346 10:06:37.702429 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1347 10:06:37.702565 # Handled SIG_COPYCTX
1348 10:06:37.702708 # Got expected size 8752 and VL 256
1349 10:06:37.702840 # Testing VL 128
1350 10:06:37.702961 # Validating EXTRA...
1351 10:06:37.703109 # uc context validated.
1352 10:06:37.703256 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1353 10:06:37.703411 # Handled SIG_COPYCTX
1354 10:06:37.703537 # Got expected size 4384 and VL 128
1355 10:06:37.703683 # Testing VL 64
1356 10:06:37.703801 # uc context validated.
1357 10:06:37.703915 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1358 10:06:37.704028 # Handled SIG_COPYCTX
1359 10:06:37.704142 # Got expected size 2208 and VL 64
1360 10:06:37.704255 # Testing VL 32
1361 10:06:37.704367 # uc context validated.
1362 10:06:37.704480 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1363 10:06:37.704594 # Handled SIG_COPYCTX
1364 10:06:37.704706 # Got expected size 1120 and VL 32
1365 10:06:37.704820 # Testing VL 16
1366 10:06:37.704934 # uc context validated.
1367 10:06:37.709977 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1368 10:06:37.710280 # Handled SIG_COPYCTX
1369 10:06:37.710703 # Got expected size 576 and VL 16
1370 10:06:37.710861 # ==>> completed. PASS(1)
1371 10:06:37.710984 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
1372 10:06:37.711103 ok 23 selftests: arm64: ssve_regs
1373 10:06:37.755846 # selftests: arm64: sve_regs
1374 10:06:38.180909 # Registered handlers for all signals.
1375 10:06:38.181132 # Detected MINSTKSIGSZ:10000
1376 10:06:38.181230 # Required Features: [ SVE ] supported
1377 10:06:38.182676 # Incompatible Features: [] absent
1378 10:06:38.182974 # Testcase initialized.
1379 10:06:38.183157 # Testing VL 256
1380 10:06:38.183335 # Validating EXTRA...
1381 10:06:38.183505 # uc context validated.
1382 10:06:38.183671 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1383 10:06:38.183861 # Handled SIG_COPYCTX
1384 10:06:38.184017 # Got expected size 8752 and VL 256
1385 10:06:38.184173 # Testing VL 240
1386 10:06:38.184348 # Validating EXTRA...
1387 10:06:38.184519 # uc context validated.
1388 10:06:38.184698 # 8816 byte GOOD CONTEXT grabbed from sig_copyctx handler
1389 10:06:38.184891 # Handled SIG_COPYCTX
1390 10:06:38.185065 # Got expected size 8208 and VL 240
1391 10:06:38.185209 # Testing VL 224
1392 10:06:38.185352 # Validating EXTRA...
1393 10:06:38.185490 # uc context validated.
1394 10:06:38.185630 # 8272 byte GOOD CONTEXT grabbed from sig_copyctx handler
1395 10:06:38.185786 # Handled SIG_COPYCTX
1396 10:06:38.185968 # Got expected size 7664 and VL 224
1397 10:06:38.186102 # Testing VL 208
1398 10:06:38.186241 # Validating EXTRA...
1399 10:06:38.186384 # uc context validated.
1400 10:06:38.186522 # 7728 byte GOOD CONTEXT grabbed from sig_copyctx handler
1401 10:06:38.186662 # Handled SIG_COPYCTX
1402 10:06:38.186801 # Got expected size 7120 and VL 208
1403 10:06:38.186939 # Testing VL 192
1404 10:06:38.187078 # Validating EXTRA...
1405 10:06:38.187217 # uc context validated.
1406 10:06:38.187356 # 7184 byte GOOD CONTEXT grabbed from sig_copyctx handler
1407 10:06:38.187495 # Handled SIG_COPYCTX
1408 10:06:38.187634 # Got expected size 6576 and VL 192
1409 10:06:38.187773 # Testing VL 176
1410 10:06:38.191724 # Validating EXTRA...
1411 10:06:38.191992 # uc context validated.
1412 10:06:38.192373 # 6640 byte GOOD CONTEXT grabbed from sig_copyctx handler
1413 10:06:38.192504 # Handled SIG_COPYCTX
1414 10:06:38.192670 # Got expected size 6032 and VL 176
1415 10:06:38.192802 # Testing VL 160
1416 10:06:38.192918 # Validating EXTRA...
1417 10:06:38.193031 # uc context validated.
1418 10:06:38.193143 # 6096 byte GOOD CONTEXT grabbed from sig_copyctx handler
1419 10:06:38.193256 # Handled SIG_COPYCTX
1420 10:06:38.193370 # Got expected size 5488 and VL 160
1421 10:06:38.193484 # Testing VL 144
1422 10:06:38.193597 # Validating EXTRA...
1423 10:06:38.193731 # uc context validated.
1424 10:06:38.193878 # 5552 byte GOOD CONTEXT grabbed from sig_copyctx handler
1425 10:06:38.194004 # Handled SIG_COPYCTX
1426 10:06:38.194121 # Got expected size 4944 and VL 144
1427 10:06:38.194237 # Testing VL 128
1428 10:06:38.194355 # Validating EXTRA...
1429 10:06:38.194471 # uc context validated.
1430 10:06:38.194584 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1431 10:06:38.194698 # Handled SIG_COPYCTX
1432 10:06:38.194812 # Got expected size 4384 and VL 128
1433 10:06:38.194924 # Testing VL 112
1434 10:06:38.195038 # Validating EXTRA...
1435 10:06:38.195151 # uc context validated.
1436 10:06:38.195264 # 4448 byte GOOD CONTEXT grabbed from sig_copyctx handler
1437 10:06:38.195378 # Handled SIG_COPYCTX
1438 10:06:38.195491 # Got expected size 3840 and VL 112
1439 10:06:38.195604 # Testing VL 96
1440 10:06:38.195716 # uc context validated.
1441 10:06:38.195870 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1442 10:06:38.195990 # Handled SIG_COPYCTX
1443 10:06:38.196106 # Got expected size 3296 and VL 96
1444 10:06:38.196219 # Testing VL 80
1445 10:06:38.196333 # uc context validated.
1446 10:06:38.196446 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1447 10:06:38.196570 # Handled SIG_COPYCTX
1448 10:06:38.196697 # Got expected size 2752 and VL 80
1449 10:06:38.196812 # Testing VL 64
1450 10:06:38.196924 # uc context validated.
1451 10:06:38.197038 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1452 10:06:38.197151 # Handled SIG_COPYCTX
1453 10:06:38.197265 # Got expected size 2208 and VL 64
1454 10:06:38.197380 # Testing VL 48
1455 10:06:38.197494 # uc context validated.
1456 10:06:38.197607 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1457 10:06:38.197734 # Handled SIG_COPYCTX
1458 10:06:38.197851 # Got expected size 1664 and VL 48
1459 10:06:38.197964 # Testing VL 32
1460 10:06:38.198076 # uc context validated.
1461 10:06:38.198190 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1462 10:06:38.198303 # Handled SIG_COPYCTX
1463 10:06:38.198417 # Got expected size 1120 and VL 32
1464 10:06:38.198530 # Testing VL 16
1465 10:06:38.198642 # uc context validated.
1466 10:06:38.198754 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1467 10:06:38.198867 # Handled SIG_COPYCTX
1468 10:06:38.198980 # Got expected size 576 and VL 16
1469 10:06:38.199093 # ==>> completed. PASS(1)
1470 10:06:38.199231 # # SVE registers :: Check that we get the right SVE registers reported
1471 10:06:38.199556 ok 24 selftests: arm64: sve_regs
1472 10:06:38.244715 # selftests: arm64: sve_vl
1473 10:06:38.335880 # Registered handlers for all signals.
1474 10:06:38.336219 # Detected MINSTKSIGSZ:10000
1475 10:06:38.336417 # Required Features: [ SVE ] supported
1476 10:06:38.336825 # Incompatible Features: [] absent
1477 10:06:38.336991 # Testcase initialized.
1478 10:06:38.337121 # uc context validated.
1479 10:06:38.337241 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1480 10:06:38.337357 # Handled SIG_COPYCTX
1481 10:06:38.337473 # got expected VL 64
1482 10:06:38.337592 # ==>> completed. PASS(1)
1483 10:06:38.338372 # # SVE VL :: Check that we get the right SVE VL reported
1484 10:06:38.343865 ok 25 selftests: arm64: sve_vl
1485 10:06:38.390697 # selftests: arm64: za_no_regs
1486 10:06:38.451227 # Registered handlers for all signals.
1487 10:06:38.451478 # Detected MINSTKSIGSZ:10000
1488 10:06:38.451785 # Required Features: [ SME ] supported
1489 10:06:38.451893 # Incompatible Features: [] absent
1490 10:06:38.451986 # Testcase initialized.
1491 10:06:38.452076 # Testing VL 256
1492 10:06:38.452163 # uc context validated.
1493 10:06:38.452251 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1494 10:06:38.453623 # Handled SIG_COPYCTX
1495 10:06:38.454110 # Got expected size 16 and VL 256
1496 10:06:38.454317 # Testing VL 128
1497 10:06:38.454490 # uc context validated.
1498 10:06:38.454653 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1499 10:06:38.454810 # Handled SIG_COPYCTX
1500 10:06:38.454962 # Got expected size 16 and VL 128
1501 10:06:38.455152 # Testing VL 64
1502 10:06:38.455313 # uc context validated.
1503 10:06:38.455449 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1504 10:06:38.455564 # Handled SIG_COPYCTX
1505 10:06:38.455683 # Got expected size 16 and VL 64
1506 10:06:38.455795 # Testing VL 32
1507 10:06:38.455906 # uc context validated.
1508 10:06:38.456015 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1509 10:06:38.456125 # Handled SIG_COPYCTX
1510 10:06:38.456235 # Got expected size 16 and VL 32
1511 10:06:38.456345 # Testing VL 16
1512 10:06:38.456454 # uc context validated.
1513 10:06:38.456568 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1514 10:06:38.456680 # Handled SIG_COPYCTX
1515 10:06:38.456817 # Got expected size 16 and VL 16
1516 10:06:38.456935 # ==>> completed. PASS(1)
1517 10:06:38.457046 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
1518 10:06:38.462264 ok 26 selftests: arm64: za_no_regs
1519 10:06:38.506035 # selftests: arm64: za_regs
1520 10:06:38.658865 # Registered handlers for all signals.
1521 10:06:38.659143 # Detected MINSTKSIGSZ:10000
1522 10:06:38.659491 # Required Features: [ SME ] supported
1523 10:06:38.660533 # Incompatible Features: [] absent
1524 10:06:38.660745 # Testcase initialized.
1525 10:06:38.661235 # Testing VL 256
1526 10:06:38.661423 # Validating EXTRA...
1527 10:06:38.661593 # uc context validated.
1528 10:06:38.661840 # 66160 byte GOOD CONTEXT grabbed from sig_copyctx handler
1529 10:06:38.662012 # Handled SIG_COPYCTX
1530 10:06:38.662159 # Got expected size 65552 and VL 256
1531 10:06:38.662308 # Testing VL 128
1532 10:06:38.662449 # Validating EXTRA...
1533 10:06:38.662627 # uc context validated.
1534 10:06:38.662808 # 17008 byte GOOD CONTEXT grabbed from sig_copyctx handler
1535 10:06:38.662981 # Handled SIG_COPYCTX
1536 10:06:38.663123 # Got expected size 16400 and VL 128
1537 10:06:38.663266 # Testing VL 64
1538 10:06:38.663405 # Validating EXTRA...
1539 10:06:38.663545 # uc context validated.
1540 10:06:38.663686 # 4720 byte GOOD CONTEXT grabbed from sig_copyctx handler
1541 10:06:38.663826 # Handled SIG_COPYCTX
1542 10:06:38.663969 # Got expected size 4112 and VL 64
1543 10:06:38.664147 # Testing VL 32
1544 10:06:38.664283 # uc context validated.
1545 10:06:38.664423 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1546 10:06:38.664566 # Handled SIG_COPYCTX
1547 10:06:38.664707 # Got expected size 1040 and VL 32
1548 10:06:38.664847 # Testing VL 16
1549 10:06:38.664988 # uc context validated.
1550 10:06:38.665128 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1551 10:06:38.669193 # Handled SIG_COPYCTX
1552 10:06:38.669360 # Got expected size 272 and VL 16
1553 10:06:38.669532 # ==>> completed. PASS(1)
1554 10:06:38.669688 # # ZA register :: Check that we get the right ZA registers reported
1555 10:06:38.670047 ok 27 selftests: arm64: za_regs
1556 10:06:38.712953 # selftests: arm64: pac
1557 10:06:38.872060 # TAP version 13
1558 10:06:38.872384 # 1..7
1559 10:06:38.872569 # # Starting 7 tests from 1 test cases.
1560 10:06:38.872986 # # RUN global.corrupt_pac ...
1561 10:06:38.873096 # # OK global.corrupt_pac
1562 10:06:38.873188 # ok 1 global.corrupt_pac
1563 10:06:38.873275 # # RUN global.pac_instructions_not_nop ...
1564 10:06:38.873363 # # OK global.pac_instructions_not_nop
1565 10:06:38.873451 # ok 2 global.pac_instructions_not_nop
1566 10:06:38.873538 # # RUN global.pac_instructions_not_nop_generic ...
1567 10:06:38.873824 # # OK global.pac_instructions_not_nop_generic
1568 10:06:38.873908 # ok 3 global.pac_instructions_not_nop_generic
1569 10:06:38.873970 # # RUN global.single_thread_different_keys ...
1570 10:06:38.874031 # # OK global.single_thread_different_keys
1571 10:06:38.874091 # ok 4 global.single_thread_different_keys
1572 10:06:38.874151 # # RUN global.exec_changed_keys ...
1573 10:06:38.874210 # # OK global.exec_changed_keys
1574 10:06:38.882328 # ok 5 global.exec_changed_keys
1575 10:06:38.882876 # # RUN global.context_switch_keep_keys ...
1576 10:06:38.883051 # # OK global.context_switch_keep_keys
1577 10:06:38.883226 # ok 6 global.context_switch_keep_keys
1578 10:06:38.883375 # # RUN global.context_switch_keep_keys_generic ...
1579 10:06:38.883555 # # OK global.context_switch_keep_keys_generic
1580 10:06:38.883732 # ok 7 global.context_switch_keep_keys_generic
1581 10:06:38.883905 # # PASSED: 7 / 7 tests passed.
1582 10:06:38.884051 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
1583 10:06:38.884194 ok 28 selftests: arm64: pac
1584 10:06:38.933156 # selftests: arm64: fp-stress
1585 10:06:56.718943 # TAP version 13
1586 10:06:56.719183 # 1..27
1587 10:06:56.719294 # # 1 CPUs, 16 SVE VLs, 5 SME VLs
1588 10:06:56.719384 # # Will run for 10s
1589 10:06:56.719475 # # Started FPSIMD-0-0
1590 10:06:56.719559 # # Started SVE-VL-256-0
1591 10:06:56.719658 # # Started SVE-VL-240-0
1592 10:06:56.719743 # # Started SVE-VL-224-0
1593 10:06:56.719827 # # Started SVE-VL-208-0
1594 10:06:56.719909 # # Started SVE-VL-192-0
1595 10:06:56.720005 # # Started SVE-VL-176-0
1596 10:06:56.720083 # # Started SVE-VL-160-0
1597 10:06:56.720157 # # Started SVE-VL-144-0
1598 10:06:56.720229 # # Started SVE-VL-128-0
1599 10:06:56.725394 # # Started SVE-VL-112-0
1600 10:06:56.725808 # # Started SVE-VL-96-0
1601 10:06:56.725908 # # Started SVE-VL-80-0
1602 10:06:56.725994 # # Started SVE-VL-64-0
1603 10:06:56.726079 # # Started SVE-VL-48-0
1604 10:06:56.726161 # # Started SVE-VL-32-0
1605 10:06:56.726242 # # Started SVE-VL-16-0
1606 10:06:56.726324 # # Started SSVE-VL-256-0
1607 10:06:56.726423 # # Started ZA-VL-256-0
1608 10:06:56.726518 # # Started SSVE-VL-128-0
1609 10:06:56.726601 # # Started ZA-VL-128-0
1610 10:06:56.726685 # # Started SSVE-VL-64-0
1611 10:06:56.726770 # # Started ZA-VL-64-0
1612 10:06:56.726855 # # Started SSVE-VL-32-0
1613 10:06:56.726939 # # Started ZA-VL-32-0
1614 10:06:56.727020 # # Started SSVE-VL-16-0
1615 10:06:56.727121 # # Started ZA-VL-16-0
1616 10:06:56.727206 # # SVE-VL-256-0: Vector length: 2048 bits
1617 10:06:56.727289 # # SVE-VL-256-0: PID: 912
1618 10:06:56.727373 # # FPSIMD-0-0: Vector length: 128 bits
1619 10:06:56.727472 # # FPSIMD-0-0: PID: 911
1620 10:06:56.727558 # # SVE-VL-208-0: Vector length: 1664 bits
1621 10:06:56.727656 # # SVE-VL-208-0: PID: 915
1622 10:06:56.727740 # # SVE-VL-144-0: Vector length: 1152 bits
1623 10:06:56.727839 # # SVE-VL-144-0: PID: 919
1624 10:06:56.727938 # # SVE-VL-224-0: Vector length: 1792 bits
1625 10:06:56.728037 # # SVE-VL-224-0: PID: 914
1626 10:06:56.733878 # # SVE-VL-160-0: Vector length: 1280 bits
1627 10:06:56.734468 # # SVE-VL-160-0: PID: 918
1628 10:06:56.734665 # # SVE-VL-192-0: Vector length: 1536 bits
1629 10:06:56.734865 # # SVE-VL-192-0: PID: 916
1630 10:06:56.735042 # # SVE-VL-176-0: Vector length: 1408 bits
1631 10:06:56.735256 # # SVE-VL-176-0: PID: 917
1632 10:06:56.735466 # # SVE-VL-240-0: Vector length: 1920 bits
1633 10:06:56.735670 # # SVE-VL-240-0: PID: 913
1634 10:06:56.735855 # # SVE-VL-128-0: Vector length: 1024 bits
1635 10:06:56.736060 # # SVE-VL-128-0: PID: 920
1636 10:06:56.736229 # # SVE-VL-112-0: Vector length: 896 bits
1637 10:06:56.736379 # # SVE-VL-112-0: PID: 921
1638 10:06:56.736525 # # SVE-VL-96-0: Vector length: 768 bits
1639 10:06:56.736687 # # SVE-VL-96-0: PID: 922
1640 10:06:56.736833 # # SVE-VL-80-0: Vector length: 640 bits
1641 10:06:56.736974 # # SVE-VL-80-0: PID: 923
1642 10:06:56.737094 # # ZA-VL-256-0: Streaming mode vector length: 2048 bits
1643 10:06:56.737223 # # ZA-VL-256-0: PID: 929
1644 10:06:56.737357 # # SSVE-VL-128-0: Streaming mode Vector length: 1024 bits
1645 10:06:56.737599 # # SSVE-VL-128-0: PID: 930
1646 10:06:56.737812 # # SSVE-VL-32-0: Streaming mode Vector length: 256 bits
1647 10:06:56.737986 # # SSVE-VL-16-0: Streaming mode Vector length: 128 bits
1648 10:06:56.738136 # # SSVE-VL-16-0: PID: 936
1649 10:06:56.738267 # # SVE-VL-32-0: Vector length: 256 bits
1650 10:06:56.738398 # # SVE-VL-32-0: PID: 926
1651 10:06:56.738526 # # SSVE-VL-64-0: Streaming mode Vector length: 512 bits
1652 10:06:56.738729 # # SVE-VL-16-0: Vector length: 128 bits
1653 10:06:56.738933 # # SVE-VL-16-0: PID: 927
1654 10:06:56.739164 # # ZA-VL-128-0: Streaming mode vector length: 1024 bits
1655 10:06:56.739343 # # ZA-VL-128-0: PID: 931
1656 10:06:56.739467 # # SVE-VL-48-0: Vector length: 384 bits
1657 10:06:56.739591 # # SVE-VL-48-0: PID: 925
1658 10:06:56.739728 # # SSVE-VL-32-0: PID: 934
1659 10:06:56.739876 # # SVE-VL-64-0: Vector length: 512 bits
1660 10:06:56.740019 # # SVE-VL-64-0: PID: 924
1661 10:06:56.740137 # # SSVE-VL-256-0: Streaming mode Vector length: 2048 bits
1662 10:06:56.740252 # # SSVE-VL-256-0: PID: 928
1663 10:06:56.740366 # # SSVE-VL-64-0: PID: 932
1664 10:06:56.740481 # # ZA-VL-16-0: Streaming mode vector length: 128 bits
1665 10:06:56.740595 # # ZA-VL-32-0: Streaming mode vector length: 256 bits
1666 10:06:56.740709 # # ZA-VL-16-0: PID: 937
1667 10:06:56.740854 # # ZA-VL-32-0: PID: 935
1668 10:06:56.740974 # # ZA-VL-64-0: Streaming mode vector length: 512 bits
1669 10:06:56.741090 # # ZA-VL-64-0: PID: 933
1670 10:06:56.741202 # # Finishing up...
1671 10:06:56.741316 # ok 1 FPSIMD-0-0
1672 10:06:56.741446 # ok 2 SVE-VL-256-0
1673 10:06:56.741598 # ok 3 SVE-VL-240-0
1674 10:06:56.742602 # ok 4 SVE-VL-224-0
1675 10:06:56.742803 # ok 5 SVE-VL-208-0
1676 10:06:56.742975 # ok 6 SVE-VL-192-0
1677 10:06:56.743168 # ok 7 SVE-VL-176-0
1678 10:06:56.743340 # ok 8 SVE-VL-160-0
1679 10:06:56.743509 # ok 9 SVE-VL-144-0
1680 10:06:56.743670 # ok 10 SVE-VL-128-0
1681 10:06:56.743819 # ok 11 SVE-VL-112-0
1682 10:06:56.743949 # ok 12 SVE-VL-96-0
1683 10:06:56.744064 # ok 13 SVE-VL-80-0
1684 10:06:56.744427 # ok 14 SVE-VL-64-0
1685 10:06:56.744612 # ok 15 SVE-VL-48-0
1686 10:06:56.744749 # ok 16 SVE-VL-32-0
1687 10:06:56.744869 # ok 17 SVE-VL-16-0
1688 10:06:56.744984 # ok 18 SSVE-VL-256-0
1689 10:06:56.745100 # ok 19 ZA-VL-256-0
1690 10:06:56.745214 # ok 20 SSVE-VL-128-0
1691 10:06:56.745328 # ok 21 ZA-VL-128-0
1692 10:06:56.745442 # ok 22 SSVE-VL-64-0
1693 10:06:56.745556 # ok 23 ZA-VL-64-0
1694 10:06:56.745685 # ok 24 SSVE-VL-32-0
1695 10:06:56.745803 # ok 25 ZA-VL-32-0
1696 10:06:56.745918 # ok 26 SSVE-VL-16-0
1697 10:06:56.746031 # ok 27 ZA-VL-16-0
1698 10:06:56.746145 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=3464, signals=9
1699 10:06:56.746260 # # ZA-VL-128-0: Terminated by signal 15, no error, iterations=712, signals=9
1700 10:06:56.746375 # # SSVE-VL-128-0: Terminated by signal 15, no error, iterations=4683, signals=9
1701 10:06:56.746492 # # SVE-VL-192-0: Terminated by signal 15, no error, iterations=3547, signals=9
1702 10:06:56.746607 # # SVE-VL-224-0: Terminated by signal 15, no error, iterations=3118, signals=9
1703 10:06:56.746720 # # SVE-VL-144-0: Terminated by signal 15, no error, iterations=4362, signals=9
1704 10:06:56.746833 # # SVE-VL-128-0: Terminated by signal 15, no error, iterations=4888, signals=9
1705 10:06:56.746948 # # ZA-VL-16-0: Terminated by signal 15, no error, iterations=1498, signals=9
1706 10:06:56.765287 # # SVE-VL-176-0: Terminated by signal 15, no error, iterations=3654, signals=9
1707 10:06:56.897354 # # SSVE-VL-32-0: Terminated by signal 15, no error, iterations=10432, signals=9
1708 10:06:56.897913 # # SVE-VL-160-0: Terminated by signal 15, no error, iterations=4045, signals=9
1709 10:06:56.898120 # # SVE-VL-240-0: Terminated by signal 15, no error, iterations=2945, signals=9
1710 10:06:56.898288 # # SSVE-VL-16-0: Terminated by signal 15, no error, iterations=13217, signals=9
1711 10:06:56.898487 # # SVE-VL-112-0: Terminated by signal 15, no error, iterations=5021, signals=9
1712 10:06:56.898661 # # SVE-VL-208-0: Terminated by signal 15, no error, iterations=3365, signals=9
1713 10:06:56.898834 # # SVE-VL-256-0: Terminated by signal 15, no error, iterations=2751, signals=9
1714 10:06:56.898989 # # SVE-VL-80-0: Terminated by signal 15, no error, iterations=6526, signals=9
1715 10:06:56.899160 # # SVE-VL-16-0: Terminated by signal 15, no error, iterations=13382, signals=9
1716 10:06:56.899339 # # ZA-VL-64-0: Terminated by signal 15, no error, iterations=948, signals=9
1717 10:06:56.899480 # # ZA-VL-256-0: Terminated by signal 15, no error, iterations=304, signals=9
1718 10:06:56.899607 # # SVE-VL-64-0: Terminated by signal 15, no error, iterations=6308, signals=9
1719 10:06:56.899733 # # SSVE-VL-256-0: Terminated by signal 15, no error, iterations=2671, signals=9
1720 10:06:56.899890 # # SVE-VL-32-0: Terminated by signal 15, no error, iterations=9740, signals=9
1721 10:06:56.900022 # # SVE-VL-48-0: Terminated by signal 15, no error, iterations=7841, signals=9
1722 10:06:56.900141 # # SVE-VL-96-0: Terminated by signal 15, no error, iterations=5998, signals=9
1723 10:06:56.900299 # # ZA-VL-32-0: Terminated by signal 15, no error, iterations=1377, signals=9
1724 10:06:56.900428 # # SSVE-VL-64-0: Terminated by signal 15, no error, iterations=7115, signals=9
1725 10:06:56.900544 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:0 error:0
1726 10:06:56.909905 ok 29 selftests: arm64: fp-stress
1727 10:06:57.083081 # selftests: arm64: sve-ptrace
1728 10:06:57.234378 # TAP version 13
1729 10:06:57.234711 # 1..4104
1730 10:06:57.234890 # # Parent is 954, child is 955
1731 10:06:57.235342 # ok 1 SVE FPSIMD set via SVE: 0
1732 10:06:57.235510 # ok 2 SVE get_fpsimd() gave same state
1733 10:06:57.235663 # ok 3 SVE SVE_PT_VL_INHERIT set
1734 10:06:57.235843 # ok 4 SVE SVE_PT_VL_INHERIT cleared
1735 10:06:57.235973 # ok 5 Set SVE VL 16
1736 10:06:57.236090 # ok 6 Set and get SVE data for VL 16
1737 10:06:57.236207 # ok 7 Set and get FPSIMD data for SVE VL 16
1738 10:06:57.236331 # ok 8 Set FPSIMD, read via SVE for SVE VL 16
1739 10:06:57.236451 # ok 9 Set SVE VL 32
1740 10:06:57.236563 # ok 10 Set and get SVE data for VL 32
1741 10:06:57.236673 # ok 11 Set and get FPSIMD data for SVE VL 32
1742 10:06:57.236785 # ok 12 Set FPSIMD, read via SVE for SVE VL 32
1743 10:06:57.236896 # ok 13 Set SVE VL 48
1744 10:06:57.237038 # ok 14 Set and get SVE data for VL 48
1745 10:06:57.237158 # ok 15 Set and get FPSIMD data for SVE VL 48
1746 10:06:57.237272 # ok 16 Set FPSIMD, read via SVE for SVE VL 48
1747 10:06:57.237385 # ok 17 Set SVE VL 64
1748 10:06:57.237500 # ok 18 Set and get SVE data for VL 64
1749 10:06:57.237668 # ok 19 Set and get FPSIMD data for SVE VL 64
1750 10:06:57.237838 # ok 20 Set FPSIMD, read via SVE for SVE VL 64
1751 10:06:57.238014 # ok 21 Set SVE VL 80
1752 10:06:57.238215 # ok 22 Set and get SVE data for VL 80
1753 10:06:57.238359 # ok 23 Set and get FPSIMD data for SVE VL 80
1754 10:06:57.238513 # ok 24 Set FPSIMD, read via SVE for SVE VL 80
1755 10:06:57.238688 # ok 25 Set SVE VL 96
1756 10:06:57.238862 # ok 26 Set and get SVE data for VL 96
1757 10:06:57.239019 # ok 27 Set and get FPSIMD data for SVE VL 96
1758 10:06:57.239184 # ok 28 Set FPSIMD, read via SVE for SVE VL 96
1759 10:06:57.239336 # ok 29 Set SVE VL 112
1760 10:06:57.239463 # ok 30 Set and get SVE data for VL 112
1761 10:06:57.239604 # ok 31 Set and get FPSIMD data for SVE VL 112
1762 10:06:57.239757 # ok 32 Set FPSIMD, read via SVE for SVE VL 112
1763 10:06:57.239884 # ok 33 Set SVE VL 128
1764 10:06:57.239998 # ok 34 Set and get SVE data for VL 128
1765 10:06:57.240109 # ok 35 Set and get FPSIMD data for SVE VL 128
1766 10:06:57.240253 # ok 36 Set FPSIMD, read via SVE for SVE VL 128
1767 10:06:57.240372 # ok 37 Set SVE VL 144
1768 10:06:57.240488 # ok 38 Set and get SVE data for VL 144
1769 10:06:57.240599 # ok 39 Set and get FPSIMD data for SVE VL 144
1770 10:06:57.240711 # ok 40 Set FPSIMD, read via SVE for SVE VL 144
1771 10:06:57.240821 # ok 41 Set SVE VL 160
1772 10:06:57.240931 # ok 42 Set and get SVE data for VL 160
1773 10:06:57.241041 # ok 43 Set and get FPSIMD data for SVE VL 160
1774 10:06:57.241151 # ok 44 Set FPSIMD, read via SVE for SVE VL 160
1775 10:06:57.241262 # ok 45 Set SVE VL 176
1776 10:06:57.241373 # ok 46 Set and get SVE data for VL 176
1777 10:06:57.241486 # ok 47 Set and get FPSIMD data for SVE VL 176
1778 10:06:57.241596 # ok 48 Set FPSIMD, read via SVE for SVE VL 176
1779 10:06:57.241821 # ok 49 Set SVE VL 192
1780 10:06:57.242016 # ok 50 Set and get SVE data for VL 192
1781 10:06:57.242443 # ok 51 Set and get FPSIMD data for SVE VL 192
1782 10:06:57.242609 # ok 52 Set FPSIMD, read via SVE for SVE VL 192
1783 10:06:57.242753 # ok 53 Set SVE VL 208
1784 10:06:57.245070 # ok 54 Set and get SVE data for VL 208
1785 10:06:57.245470 # ok 55 Set and get FPSIMD data for SVE VL 208
1786 10:06:57.245636 # ok 56 Set FPSIMD, read via SVE for SVE VL 208
1787 10:06:57.245843 # ok 57 Set SVE VL 224
1788 10:06:57.246012 # ok 58 Set and get SVE data for VL 224
1789 10:06:57.246174 # ok 59 Set and get FPSIMD data for SVE VL 224
1790 10:06:57.246305 # ok 60 Set FPSIMD, read via SVE for SVE VL 224
1791 10:06:57.246456 # ok 61 Set SVE VL 240
1792 10:06:57.246588 # ok 62 Set and get SVE data for VL 240
1793 10:06:57.246723 # ok 63 Set and get FPSIMD data for SVE VL 240
1794 10:06:57.246912 # ok 64 Set FPSIMD, read via SVE for SVE VL 240
1795 10:06:57.247052 # ok 65 Set SVE VL 256
1796 10:06:57.247199 # ok 66 Set and get SVE data for VL 256
1797 10:06:57.247353 # ok 67 Set and get FPSIMD data for SVE VL 256
1798 10:06:57.247507 # ok 68 Set FPSIMD, read via SVE for SVE VL 256
1799 10:06:57.247659 # ok 69 Set SVE VL 272
1800 10:06:57.247806 # ok 70 # SKIP SVE set SVE get SVE for VL 272
1801 10:06:57.247937 # ok 71 # SKIP SVE set SVE get FPSIMD for VL 272
1802 10:06:57.248051 # ok 72 # SKIP SVE set FPSIMD get SVE for VL 272
1803 10:06:57.248163 # ok 73 Set SVE VL 288
1804 10:06:57.248275 # ok 74 # SKIP SVE set SVE get SVE for VL 288
1805 10:06:57.248385 # ok 75 # SKIP SVE set SVE get FPSIMD for VL 288
1806 10:06:57.248527 # ok 76 # SKIP SVE set FPSIMD get SVE for VL 288
1807 10:06:57.248643 # ok 77 Set SVE VL 304
1808 10:06:57.248754 # ok 78 # SKIP SVE set SVE get SVE for VL 304
1809 10:06:57.248863 # ok 79 # SKIP SVE set SVE get FPSIMD for VL 304
1810 10:06:57.248973 # ok 80 # SKIP SVE set FPSIMD get SVE for VL 304
1811 10:06:57.249082 # ok 81 Set SVE VL 320
1812 10:06:57.249190 # ok 82 # SKIP SVE set SVE get SVE for VL 320
1813 10:06:57.249300 # ok 83 # SKIP SVE set SVE get FPSIMD for VL 320
1814 10:06:57.249410 # ok 84 # SKIP SVE set FPSIMD get SVE for VL 320
1815 10:06:57.249521 # ok 85 Set SVE VL 336
1816 10:06:57.249630 # ok 86 # SKIP SVE set SVE get SVE for VL 336
1817 10:06:57.253072 # ok 87 # SKIP SVE set SVE get FPSIMD for VL 336
1818 10:06:57.253274 # ok 88 # SKIP SVE set FPSIMD get SVE for VL 336
1819 10:06:57.253672 # ok 89 Set SVE VL 352
1820 10:06:57.253812 # ok 90 # SKIP SVE set SVE get SVE for VL 352
1821 10:06:57.253978 # ok 91 # SKIP SVE set SVE get FPSIMD for VL 352
1822 10:06:57.254177 # ok 92 # SKIP SVE set FPSIMD get SVE for VL 352
1823 10:06:57.254327 # ok 93 Set SVE VL 368
1824 10:06:57.254468 # ok 94 # SKIP SVE set SVE get SVE for VL 368
1825 10:06:57.254609 # ok 95 # SKIP SVE set SVE get FPSIMD for VL 368
1826 10:06:57.254751 # ok 96 # SKIP SVE set FPSIMD get SVE for VL 368
1827 10:06:57.254930 # ok 97 Set SVE VL 384
1828 10:06:57.255110 # ok 98 # SKIP SVE set SVE get SVE for VL 384
1829 10:06:57.255262 # ok 99 # SKIP SVE set SVE get FPSIMD for VL 384
1830 10:06:57.255384 # ok 100 # SKIP SVE set FPSIMD get SVE for VL 384
1831 10:06:57.255507 # ok 101 Set SVE VL 400
1832 10:06:57.255625 # ok 102 # SKIP SVE set SVE get SVE for VL 400
1833 10:06:57.255738 # ok 103 # SKIP SVE set SVE get FPSIMD for VL 400
1834 10:06:57.255882 # ok 104 # SKIP SVE set FPSIMD get SVE for VL 400
1835 10:06:57.256006 # ok 105 Set SVE VL 416
1836 10:06:57.256120 # ok 106 # SKIP SVE set SVE get SVE for VL 416
1837 10:06:57.256235 # ok 107 # SKIP SVE set SVE get FPSIMD for VL 416
1838 10:06:57.256349 # ok 108 # SKIP SVE set FPSIMD get SVE for VL 416
1839 10:06:57.256462 # ok 109 Set SVE VL 432
1840 10:06:57.256579 # ok 110 # SKIP SVE set SVE get SVE for VL 432
1841 10:06:57.256692 # ok 111 # SKIP SVE set SVE get FPSIMD for VL 432
1842 10:06:57.256805 # ok 112 # SKIP SVE set FPSIMD get SVE for VL 432
1843 10:06:57.256917 # ok 113 Set SVE VL 448
1844 10:06:57.257032 # ok 114 # SKIP SVE set SVE get SVE for VL 448
1845 10:06:57.262978 # ok 115 # SKIP SVE set SVE get FPSIMD for VL 448
1846 10:06:57.263377 # ok 116 # SKIP SVE set FPSIMD get SVE for VL 448
1847 10:06:57.263550 # ok 117 Set SVE VL 464
1848 10:06:57.263714 # ok 118 # SKIP SVE set SVE get SVE for VL 464
1849 10:06:57.263855 # ok 119 # SKIP SVE set SVE get FPSIMD for VL 464
1850 10:06:57.263972 # ok 120 # SKIP SVE set FPSIMD get SVE for VL 464
1851 10:06:57.264087 # ok 121 Set SVE VL 480
1852 10:06:57.264225 # ok 122 # SKIP SVE set SVE get SVE for VL 480
1853 10:06:57.264366 # ok 123 # SKIP SVE set SVE get FPSIMD for VL 480
1854 10:06:57.264487 # ok 124 # SKIP SVE set FPSIMD get SVE for VL 480
1855 10:06:57.264612 # ok 125 Set SVE VL 496
1856 10:06:57.264799 # ok 126 # SKIP SVE set SVE get SVE for VL 496
1857 10:06:57.264961 # ok 127 # SKIP SVE set SVE get FPSIMD for VL 496
1858 10:06:57.265100 # ok 128 # SKIP SVE set FPSIMD get SVE for VL 496
1859 10:06:57.265254 # ok 129 Set SVE VL 512
1860 10:06:57.265461 # ok 130 # SKIP SVE set SVE get SVE for VL 512
1861 10:06:57.265667 # ok 131 # SKIP SVE set SVE get FPSIMD for VL 512
1862 10:06:57.265829 # ok 132 # SKIP SVE set FPSIMD get SVE for VL 512
1863 10:06:57.266010 # ok 133 Set SVE VL 528
1864 10:06:57.266149 # ok 134 # SKIP SVE set SVE get SVE for VL 528
1865 10:06:57.266359 # ok 135 # SKIP SVE set SVE get FPSIMD for VL 528
1866 10:06:57.266532 # ok 136 # SKIP SVE set FPSIMD get SVE for VL 528
1867 10:06:57.266696 # ok 137 Set SVE VL 544
1868 10:06:57.266850 # ok 138 # SKIP SVE set SVE get SVE for VL 544
1869 10:06:57.267015 # ok 139 # SKIP SVE set SVE get FPSIMD for VL 544
1870 10:06:57.267199 # ok 140 # SKIP SVE set FPSIMD get SVE for VL 544
1871 10:06:57.267445 # ok 141 Set SVE VL 560
1872 10:06:57.267605 # ok 142 # SKIP SVE set SVE get SVE for VL 560
1873 10:06:57.267769 # ok 143 # SKIP SVE set SVE get FPSIMD for VL 560
1874 10:06:57.267945 # ok 144 # SKIP SVE set FPSIMD get SVE for VL 560
1875 10:06:57.268090 # ok 145 Set SVE VL 576
1876 10:06:57.268229 # ok 146 # SKIP SVE set SVE get SVE for VL 576
1877 10:06:57.268369 # ok 147 # SKIP SVE set SVE get FPSIMD for VL 576
1878 10:06:57.268509 # ok 148 # SKIP SVE set FPSIMD get SVE for VL 576
1879 10:06:57.268649 # ok 149 Set SVE VL 592
1880 10:06:57.268787 # ok 150 # SKIP SVE set SVE get SVE for VL 592
1881 10:06:57.268927 # ok 151 # SKIP SVE set SVE get FPSIMD for VL 592
1882 10:06:57.269067 # ok 152 # SKIP SVE set FPSIMD get SVE for VL 592
1883 10:06:57.269206 # ok 153 Set SVE VL 608
1884 10:06:57.269345 # ok 154 # SKIP SVE set SVE get SVE for VL 608
1885 10:06:57.269483 # ok 155 # SKIP SVE set SVE get FPSIMD for VL 608
1886 10:06:57.269622 # ok 156 # SKIP SVE set FPSIMD get SVE for VL 608
1887 10:06:57.269774 # ok 157 Set SVE VL 624
1888 10:06:57.269949 # ok 158 # SKIP SVE set SVE get SVE for VL 624
1889 10:06:57.270084 # ok 159 # SKIP SVE set SVE get FPSIMD for VL 624
1890 10:06:57.270226 # ok 160 # SKIP SVE set FPSIMD get SVE for VL 624
1891 10:06:57.277540 # ok 161 Set SVE VL 640
1892 10:06:57.277827 # ok 162 # SKIP SVE set SVE get SVE for VL 640
1893 10:06:57.278225 # ok 163 # SKIP SVE set SVE get FPSIMD for VL 640
1894 10:06:57.278427 # ok 164 # SKIP SVE set FPSIMD get SVE for VL 640
1895 10:06:57.278623 # ok 165 Set SVE VL 656
1896 10:06:57.278869 # ok 166 # SKIP SVE set SVE get SVE for VL 656
1897 10:06:57.279133 # ok 167 # SKIP SVE set SVE get FPSIMD for VL 656
1898 10:06:57.279343 # ok 168 # SKIP SVE set FPSIMD get SVE for VL 656
1899 10:06:57.279562 # ok 169 Set SVE VL 672
1900 10:06:57.279777 # ok 170 # SKIP SVE set SVE get SVE for VL 672
1901 10:06:57.279917 # ok 171 # SKIP SVE set SVE get FPSIMD for VL 672
1902 10:06:57.280035 # ok 172 # SKIP SVE set FPSIMD get SVE for VL 672
1903 10:06:57.280149 # ok 173 Set SVE VL 688
1904 10:06:57.280263 # ok 174 # SKIP SVE set SVE get SVE for VL 688
1905 10:06:57.280394 # ok 175 # SKIP SVE set SVE get FPSIMD for VL 688
1906 10:06:57.280550 # ok 176 # SKIP SVE set FPSIMD get SVE for VL 688
1907 10:06:57.280699 # ok 177 Set SVE VL 704
1908 10:06:57.280830 # ok 178 # SKIP SVE set SVE get SVE for VL 704
1909 10:06:57.280974 # ok 179 # SKIP SVE set SVE get FPSIMD for VL 704
1910 10:06:57.281140 # ok 180 # SKIP SVE set FPSIMD get SVE for VL 704
1911 10:06:57.281342 # ok 181 Set SVE VL 720
1912 10:06:57.281541 # ok 182 # SKIP SVE set SVE get SVE for VL 720
1913 10:06:57.281735 # ok 183 # SKIP SVE set SVE get FPSIMD for VL 720
1914 10:06:57.281929 # ok 184 # SKIP SVE set FPSIMD get SVE for VL 720
1915 10:06:57.282074 # ok 185 Set SVE VL 736
1916 10:06:57.282224 # ok 186 # SKIP SVE set SVE get SVE for VL 736
1917 10:06:57.282375 # ok 187 # SKIP SVE set SVE get FPSIMD for VL 736
1918 10:06:57.282533 # ok 188 # SKIP SVE set FPSIMD get SVE for VL 736
1919 10:06:57.282693 # ok 189 Set SVE VL 752
1920 10:06:57.282850 # ok 190 # SKIP SVE set SVE get SVE for VL 752
1921 10:06:57.282985 # ok 191 # SKIP SVE set SVE get FPSIMD for VL 752
1922 10:06:57.283118 # ok 192 # SKIP SVE set FPSIMD get SVE for VL 752
1923 10:06:57.283261 # ok 193 Set SVE VL 768
1924 10:06:57.283396 # ok 194 # SKIP SVE set SVE get SVE for VL 768
1925 10:06:57.283543 # ok 195 # SKIP SVE set SVE get FPSIMD for VL 768
1926 10:06:57.283674 # ok 196 # SKIP SVE set FPSIMD get SVE for VL 768
1927 10:06:57.283807 # ok 197 Set SVE VL 784
1928 10:06:57.283920 # ok 198 # SKIP SVE set SVE get SVE for VL 784
1929 10:06:57.284031 # ok 199 # SKIP SVE set SVE get FPSIMD for VL 784
1930 10:06:57.284143 # ok 200 # SKIP SVE set FPSIMD get SVE for VL 784
1931 10:06:57.284282 # ok 201 Set SVE VL 800
1932 10:06:57.284400 # ok 202 # SKIP SVE set SVE get SVE for VL 800
1933 10:06:57.284516 # ok 203 # SKIP SVE set SVE get FPSIMD for VL 800
1934 10:06:57.284630 # ok 204 # SKIP SVE set FPSIMD get SVE for VL 800
1935 10:06:57.284742 # ok 205 Set SVE VL 816
1936 10:06:57.284854 # ok 206 # SKIP SVE set SVE get SVE for VL 816
1937 10:06:57.285200 # ok 207 # SKIP SVE set SVE get FPSIMD for VL 816
1938 10:06:57.285351 # ok 208 # SKIP SVE set FPSIMD get SVE for VL 816
1939 10:06:57.285471 # ok 209 Set SVE VL 832
1940 10:06:57.285587 # ok 210 # SKIP SVE set SVE get SVE for VL 832
1941 10:06:57.285718 # ok 211 # SKIP SVE set SVE get FPSIMD for VL 832
1942 10:06:57.285833 # ok 212 # SKIP SVE set FPSIMD get SVE for VL 832
1943 10:06:57.285945 # ok 213 Set SVE VL 848
1944 10:06:57.286059 # ok 214 # SKIP SVE set SVE get SVE for VL 848
1945 10:06:57.286173 # ok 215 # SKIP SVE set SVE get FPSIMD for VL 848
1946 10:06:57.286287 # ok 216 # SKIP SVE set FPSIMD get SVE for VL 848
1947 10:06:57.286400 # ok 217 Set SVE VL 864
1948 10:06:57.286511 # ok 218 # SKIP SVE set SVE get SVE for VL 864
1949 10:06:57.286629 # ok 219 # SKIP SVE set SVE get FPSIMD for VL 864
1950 10:06:57.286742 # ok 220 # SKIP SVE set FPSIMD get SVE for VL 864
1951 10:06:57.292679 # ok 221 Set SVE VL 880
1952 10:06:57.292905 # ok 222 # SKIP SVE set SVE get SVE for VL 880
1953 10:06:57.293328 # ok 223 # SKIP SVE set SVE get FPSIMD for VL 880
1954 10:06:57.293519 # ok 224 # SKIP SVE set FPSIMD get SVE for VL 880
1955 10:06:57.293697 # ok 225 Set SVE VL 896
1956 10:06:57.293859 # ok 226 # SKIP SVE set SVE get SVE for VL 896
1957 10:06:57.294021 # ok 227 # SKIP SVE set SVE get FPSIMD for VL 896
1958 10:06:57.294185 # ok 228 # SKIP SVE set FPSIMD get SVE for VL 896
1959 10:06:57.294428 # ok 229 Set SVE VL 912
1960 10:06:57.294601 # ok 230 # SKIP SVE set SVE get SVE for VL 912
1961 10:06:57.294801 # ok 231 # SKIP SVE set SVE get FPSIMD for VL 912
1962 10:06:57.294956 # ok 232 # SKIP SVE set FPSIMD get SVE for VL 912
1963 10:06:57.295139 # ok 233 Set SVE VL 928
1964 10:06:57.295295 # ok 234 # SKIP SVE set SVE get SVE for VL 928
1965 10:06:57.295412 # ok 235 # SKIP SVE set SVE get FPSIMD for VL 928
1966 10:06:57.295532 # ok 236 # SKIP SVE set FPSIMD get SVE for VL 928
1967 10:06:57.295648 # ok 237 Set SVE VL 944
1968 10:06:57.295790 # ok 238 # SKIP SVE set SVE get SVE for VL 944
1969 10:06:57.295908 # ok 239 # SKIP SVE set SVE get FPSIMD for VL 944
1970 10:06:57.296052 # ok 240 # SKIP SVE set FPSIMD get SVE for VL 944
1971 10:06:57.296172 # ok 241 Set SVE VL 960
1972 10:06:57.296286 # ok 242 # SKIP SVE set SVE get SVE for VL 960
1973 10:06:57.296401 # ok 243 # SKIP SVE set SVE get FPSIMD for VL 960
1974 10:06:57.296514 # ok 244 # SKIP SVE set FPSIMD get SVE for VL 960
1975 10:06:57.296626 # ok 245 Set SVE VL 976
1976 10:06:57.296736 # ok 246 # SKIP SVE set SVE get SVE for VL 976
1977 10:06:57.296847 # ok 247 # SKIP SVE set SVE get FPSIMD for VL 976
1978 10:06:57.296958 # ok 248 # SKIP SVE set FPSIMD get SVE for VL 976
1979 10:06:57.297070 # ok 249 Set SVE VL 992
1980 10:06:57.297180 # ok 250 # SKIP SVE set SVE get SVE for VL 992
1981 10:06:57.297291 # ok 251 # SKIP SVE set SVE get FPSIMD for VL 992
1982 10:06:57.297401 # ok 252 # SKIP SVE set FPSIMD get SVE for VL 992
1983 10:06:57.297513 # ok 253 Set SVE VL 1008
1984 10:06:57.302831 # ok 254 # SKIP SVE set SVE get SVE for VL 1008
1985 10:06:57.303296 # ok 255 # SKIP SVE set SVE get FPSIMD for VL 1008
1986 10:06:57.303485 # ok 256 # SKIP SVE set FPSIMD get SVE for VL 1008
1987 10:06:57.303655 # ok 257 Set SVE VL 1024
1988 10:06:57.303796 # ok 258 # SKIP SVE set SVE get SVE for VL 1024
1989 10:06:57.303917 # ok 259 # SKIP SVE set SVE get FPSIMD for VL 1024
1990 10:06:57.304056 # ok 260 # SKIP SVE set FPSIMD get SVE for VL 1024
1991 10:06:57.304175 # ok 261 Set SVE VL 1040
1992 10:06:57.304292 # ok 262 # SKIP SVE set SVE get SVE for VL 1040
1993 10:06:57.304476 # ok 263 # SKIP SVE set SVE get FPSIMD for VL 1040
1994 10:06:57.304678 # ok 264 # SKIP SVE set FPSIMD get SVE for VL 1040
1995 10:06:57.304878 # ok 265 Set SVE VL 1056
1996 10:06:57.305091 # ok 266 # SKIP SVE set SVE get SVE for VL 1056
1997 10:06:57.305314 # ok 267 # SKIP SVE set SVE get FPSIMD for VL 1056
1998 10:06:57.305528 # ok 268 # SKIP SVE set FPSIMD get SVE for VL 1056
1999 10:06:57.305719 # ok 269 Set SVE VL 1072
2000 10:06:57.305920 # ok 270 # SKIP SVE set SVE get SVE for VL 1072
2001 10:06:57.306103 # ok 271 # SKIP SVE set SVE get FPSIMD for VL 1072
2002 10:06:57.306291 # ok 272 # SKIP SVE set FPSIMD get SVE for VL 1072
2003 10:06:57.306473 # ok 273 Set SVE VL 1088
2004 10:06:57.306650 # ok 274 # SKIP SVE set SVE get SVE for VL 1088
2005 10:06:57.306867 # ok 275 # SKIP SVE set SVE get FPSIMD for VL 1088
2006 10:06:57.307099 # ok 276 # SKIP SVE set FPSIMD get SVE for VL 1088
2007 10:06:57.307271 # ok 277 Set SVE VL 1104
2008 10:06:57.307420 # ok 278 # SKIP SVE set SVE get SVE for VL 1104
2009 10:06:57.307537 # ok 279 # SKIP SVE set SVE get FPSIMD for VL 1104
2010 10:06:57.307653 # ok 280 # SKIP SVE set FPSIMD get SVE for VL 1104
2011 10:06:57.307764 # ok 281 Set SVE VL 1120
2012 10:06:57.307875 # ok 282 # SKIP SVE set SVE get SVE for VL 1120
2013 10:06:57.307984 # ok 283 # SKIP SVE set SVE get FPSIMD for VL 1120
2014 10:06:57.308093 # ok 284 # SKIP SVE set FPSIMD get SVE for VL 1120
2015 10:06:57.308201 # ok 285 Set SVE VL 1136
2016 10:06:57.308310 # ok 286 # SKIP SVE set SVE get SVE for VL 1136
2017 10:06:57.308418 # ok 287 # SKIP SVE set SVE get FPSIMD for VL 1136
2018 10:06:57.308526 # ok 288 # SKIP SVE set FPSIMD get SVE for VL 1136
2019 10:06:57.308637 # ok 289 Set SVE VL 1152
2020 10:06:57.308770 # ok 290 # SKIP SVE set SVE get SVE for VL 1152
2021 10:06:57.308884 # ok 291 # SKIP SVE set SVE get FPSIMD for VL 1152
2022 10:06:57.308995 # ok 292 # SKIP SVE set FPSIMD get SVE for VL 1152
2023 10:06:57.324528 # ok 293 Set SVE VL 1168
2024 10:06:57.325091 # ok 294 # SKIP SVE set SVE get SVE for VL 1168
2025 10:06:57.325279 # ok 295 # SKIP SVE set SVE get FPSIMD for VL 1168
2026 10:06:57.325464 # ok 296 # SKIP SVE set FPSIMD get SVE for VL 1168
2027 10:06:57.325620 # ok 297 Set SVE VL 1184
2028 10:06:57.325777 # ok 298 # SKIP SVE set SVE get SVE for VL 1184
2029 10:06:57.325941 # ok 299 # SKIP SVE set SVE get FPSIMD for VL 1184
2030 10:06:57.326205 # ok 300 # SKIP SVE set FPSIMD get SVE for VL 1184
2031 10:06:57.326387 # ok 301 Set SVE VL 1200
2032 10:06:57.326561 # ok 302 # SKIP SVE set SVE get SVE for VL 1200
2033 10:06:57.326727 # ok 303 # SKIP SVE set SVE get FPSIMD for VL 1200
2034 10:06:57.326878 # ok 304 # SKIP SVE set FPSIMD get SVE for VL 1200
2035 10:06:57.327029 # ok 305 Set SVE VL 1216
2036 10:06:57.327182 # ok 306 # SKIP SVE set SVE get SVE for VL 1216
2037 10:06:57.327346 # ok 307 # SKIP SVE set SVE get FPSIMD for VL 1216
2038 10:06:57.327507 # ok 308 # SKIP SVE set FPSIMD get SVE for VL 1216
2039 10:06:57.327673 # ok 309 Set SVE VL 1232
2040 10:06:57.327824 # ok 310 # SKIP SVE set SVE get SVE for VL 1232
2041 10:06:57.327973 # ok 311 # SKIP SVE set SVE get FPSIMD for VL 1232
2042 10:06:57.328092 # ok 312 # SKIP SVE set FPSIMD get SVE for VL 1232
2043 10:06:57.328204 # ok 313 Set SVE VL 1248
2044 10:06:57.328314 # ok 314 # SKIP SVE set SVE get SVE for VL 1248
2045 10:06:57.328424 # ok 315 # SKIP SVE set SVE get FPSIMD for VL 1248
2046 10:06:57.328534 # ok 316 # SKIP SVE set FPSIMD get SVE for VL 1248
2047 10:06:57.328647 # ok 317 Set SVE VL 1264
2048 10:06:57.328756 # ok 318 # SKIP SVE set SVE get SVE for VL 1264
2049 10:06:57.328866 # ok 319 # SKIP SVE set SVE get FPSIMD for VL 1264
2050 10:06:57.328975 # ok 320 # SKIP SVE set FPSIMD get SVE for VL 1264
2051 10:06:57.329085 # ok 321 Set SVE VL 1280
2052 10:06:57.329194 # ok 322 # SKIP SVE set SVE get SVE for VL 1280
2053 10:06:57.329304 # ok 323 # SKIP SVE set SVE get FPSIMD for VL 1280
2054 10:06:57.329414 # ok 324 # SKIP SVE set FPSIMD get SVE for VL 1280
2055 10:06:57.329524 # ok 325 Set SVE VL 1296
2056 10:06:57.330594 # ok 326 # SKIP SVE set SVE get SVE for VL 1296
2057 10:06:57.331007 # ok 327 # SKIP SVE set SVE get FPSIMD for VL 1296
2058 10:06:57.331166 # ok 328 # SKIP SVE set FPSIMD get SVE for VL 1296
2059 10:06:57.331294 # ok 329 Set SVE VL 1312
2060 10:06:57.331431 # ok 330 # SKIP SVE set SVE get SVE for VL 1312
2061 10:06:57.331578 # ok 331 # SKIP SVE set SVE get FPSIMD for VL 1312
2062 10:06:57.331787 # ok 332 # SKIP SVE set FPSIMD get SVE for VL 1312
2063 10:06:57.331951 # ok 333 Set SVE VL 1328
2064 10:06:57.332091 # ok 334 # SKIP SVE set SVE get SVE for VL 1328
2065 10:06:57.332273 # ok 335 # SKIP SVE set SVE get FPSIMD for VL 1328
2066 10:06:57.332454 # ok 336 # SKIP SVE set FPSIMD get SVE for VL 1328
2067 10:06:57.332618 # ok 337 Set SVE VL 1344
2068 10:06:57.332768 # ok 338 # SKIP SVE set SVE get SVE for VL 1344
2069 10:06:57.332889 # ok 339 # SKIP SVE set SVE get FPSIMD for VL 1344
2070 10:06:57.333038 # ok 340 # SKIP SVE set FPSIMD get SVE for VL 1344
2071 10:06:57.333173 # ok 341 Set SVE VL 1360
2072 10:06:57.333332 # ok 342 # SKIP SVE set SVE get SVE for VL 1360
2073 10:06:57.333525 # ok 343 # SKIP SVE set SVE get FPSIMD for VL 1360
2074 10:06:57.333700 # ok 344 # SKIP SVE set FPSIMD get SVE for VL 1360
2075 10:06:57.333888 # ok 345 Set SVE VL 1376
2076 10:06:57.334062 # ok 346 # SKIP SVE set SVE get SVE for VL 1376
2077 10:06:57.334207 # ok 347 # SKIP SVE set SVE get FPSIMD for VL 1376
2078 10:06:57.334349 # ok 348 # SKIP SVE set FPSIMD get SVE for VL 1376
2079 10:06:57.334532 # ok 349 Set SVE VL 1392
2080 10:06:57.334667 # ok 350 # SKIP SVE set SVE get SVE for VL 1392
2081 10:06:57.334811 # ok 351 # SKIP SVE set SVE get FPSIMD for VL 1392
2082 10:06:57.334953 # ok 352 # SKIP SVE set FPSIMD get SVE for VL 1392
2083 10:06:57.335097 # ok 353 Set SVE VL 1408
2084 10:06:57.335249 # ok 354 # SKIP SVE set SVE get SVE for VL 1408
2085 10:06:57.335417 # ok 355 # SKIP SVE set SVE get FPSIMD for VL 1408
2086 10:06:57.335574 # ok 356 # SKIP SVE set FPSIMD get SVE for VL 1408
2087 10:06:57.335754 # ok 357 Set SVE VL 1424
2088 10:06:57.335929 # ok 358 # SKIP SVE set SVE get SVE for VL 1424
2089 10:06:57.336059 # ok 359 # SKIP SVE set SVE get FPSIMD for VL 1424
2090 10:06:57.336175 # ok 360 # SKIP SVE set FPSIMD get SVE for VL 1424
2091 10:06:57.336292 # ok 361 Set SVE VL 1440
2092 10:06:57.336406 # ok 362 # SKIP SVE set SVE get SVE for VL 1440
2093 10:06:57.336522 # ok 363 # SKIP SVE set SVE get FPSIMD for VL 1440
2094 10:06:57.336637 # ok 364 # SKIP SVE set FPSIMD get SVE for VL 1440
2095 10:06:57.336779 # ok 365 Set SVE VL 1456
2096 10:06:57.336901 # ok 366 # SKIP SVE set SVE get SVE for VL 1456
2097 10:06:57.337017 # ok 367 # SKIP SVE set SVE get FPSIMD for VL 1456
2098 10:06:57.337131 # ok 368 # SKIP SVE set FPSIMD get SVE for VL 1456
2099 10:06:57.337246 # ok 369 Set SVE VL 1472
2100 10:06:57.337359 # ok 370 # SKIP SVE set SVE get SVE for VL 1472
2101 10:06:57.337699 # ok 371 # SKIP SVE set SVE get FPSIMD for VL 1472
2102 10:06:57.337827 # ok 372 # SKIP SVE set FPSIMD get SVE for VL 1472
2103 10:06:57.337946 # ok 373 Set SVE VL 1488
2104 10:06:57.338062 # ok 374 # SKIP SVE set SVE get SVE for VL 1488
2105 10:06:57.338176 # ok 375 # SKIP SVE set SVE get FPSIMD for VL 1488
2106 10:06:57.338290 # ok 376 # SKIP SVE set FPSIMD get SVE for VL 1488
2107 10:06:57.338403 # ok 377 Set SVE VL 1504
2108 10:06:57.344243 # ok 378 # SKIP SVE set SVE get SVE for VL 1504
2109 10:06:57.344440 # ok 379 # SKIP SVE set SVE get FPSIMD for VL 1504
2110 10:06:57.344632 # ok 380 # SKIP SVE set FPSIMD get SVE for VL 1504
2111 10:06:57.344784 # ok 381 Set SVE VL 1520
2112 10:06:57.344937 # ok 382 # SKIP SVE set SVE get SVE for VL 1520
2113 10:06:57.345091 # ok 383 # SKIP SVE set SVE get FPSIMD for VL 1520
2114 10:06:57.345277 # ok 384 # SKIP SVE set FPSIMD get SVE for VL 1520
2115 10:06:57.345439 # ok 385 Set SVE VL 1536
2116 10:06:57.345596 # ok 386 # SKIP SVE set SVE get SVE for VL 1536
2117 10:06:57.345767 # ok 387 # SKIP SVE set SVE get FPSIMD for VL 1536
2118 10:06:57.345929 # ok 388 # SKIP SVE set FPSIMD get SVE for VL 1536
2119 10:06:57.346080 # ok 389 Set SVE VL 1552
2120 10:06:57.346274 # ok 390 # SKIP SVE set SVE get SVE for VL 1552
2121 10:06:57.346450 # ok 391 # SKIP SVE set SVE get FPSIMD for VL 1552
2122 10:06:57.346647 # ok 392 # SKIP SVE set FPSIMD get SVE for VL 1552
2123 10:06:57.346836 # ok 393 Set SVE VL 1568
2124 10:06:57.346993 # ok 394 # SKIP SVE set SVE get SVE for VL 1568
2125 10:06:57.347151 # ok 395 # SKIP SVE set SVE get FPSIMD for VL 1568
2126 10:06:57.347304 # ok 396 # SKIP SVE set FPSIMD get SVE for VL 1568
2127 10:06:57.347456 # ok 397 Set SVE VL 1584
2128 10:06:57.347595 # ok 398 # SKIP SVE set SVE get SVE for VL 1584
2129 10:06:57.347780 # ok 399 # SKIP SVE set SVE get FPSIMD for VL 1584
2130 10:06:57.347923 # ok 400 # SKIP SVE set FPSIMD get SVE for VL 1584
2131 10:06:57.348039 # ok 401 Set SVE VL 1600
2132 10:06:57.348195 # ok 402 # SKIP SVE set SVE get SVE for VL 1600
2133 10:06:57.348321 # ok 403 # SKIP SVE set SVE get FPSIMD for VL 1600
2134 10:06:57.348433 # ok 404 # SKIP SVE set FPSIMD get SVE for VL 1600
2135 10:06:57.348578 # ok 405 Set SVE VL 1616
2136 10:06:57.348709 # ok 406 # SKIP SVE set SVE get SVE for VL 1616
2137 10:06:57.348825 # ok 407 # SKIP SVE set SVE get FPSIMD for VL 1616
2138 10:06:57.348938 # ok 408 # SKIP SVE set FPSIMD get SVE for VL 1616
2139 10:06:57.349051 # ok 409 Set SVE VL 1632
2140 10:06:57.349163 # ok 410 # SKIP SVE set SVE get SVE for VL 1632
2141 10:06:57.349276 # ok 411 # SKIP SVE set SVE get FPSIMD for VL 1632
2142 10:06:57.349388 # ok 412 # SKIP SVE set FPSIMD get SVE for VL 1632
2143 10:06:57.349500 # ok 413 Set SVE VL 1648
2144 10:06:57.349613 # ok 414 # SKIP SVE set SVE get SVE for VL 1648
2145 10:06:57.349840 # ok 415 # SKIP SVE set SVE get FPSIMD for VL 1648
2146 10:06:57.350033 # ok 416 # SKIP SVE set FPSIMD get SVE for VL 1648
2147 10:06:57.350218 # ok 417 Set SVE VL 1664
2148 10:06:57.352283 # ok 418 # SKIP SVE set SVE get SVE for VL 1664
2149 10:06:57.352718 # ok 419 # SKIP SVE set SVE get FPSIMD for VL 1664
2150 10:06:57.352929 # ok 420 # SKIP SVE set FPSIMD get SVE for VL 1664
2151 10:06:57.353115 # ok 421 Set SVE VL 1680
2152 10:06:57.353275 # ok 422 # SKIP SVE set SVE get SVE for VL 1680
2153 10:06:57.353495 # ok 423 # SKIP SVE set SVE get FPSIMD for VL 1680
2154 10:06:57.353684 # ok 424 # SKIP SVE set FPSIMD get SVE for VL 1680
2155 10:06:57.353844 # ok 425 Set SVE VL 1696
2156 10:06:57.354002 # ok 426 # SKIP SVE set SVE get SVE for VL 1696
2157 10:06:57.354152 # ok 427 # SKIP SVE set SVE get FPSIMD for VL 1696
2158 10:06:57.354298 # ok 428 # SKIP SVE set FPSIMD get SVE for VL 1696
2159 10:06:57.354460 # ok 429 Set SVE VL 1712
2160 10:06:57.354619 # ok 430 # SKIP SVE set SVE get SVE for VL 1712
2161 10:06:57.354808 # ok 431 # SKIP SVE set SVE get FPSIMD for VL 1712
2162 10:06:57.354976 # ok 432 # SKIP SVE set FPSIMD get SVE for VL 1712
2163 10:06:57.355135 # ok 433 Set SVE VL 1728
2164 10:06:57.355260 # ok 434 # SKIP SVE set SVE get SVE for VL 1728
2165 10:06:57.355378 # ok 435 # SKIP SVE set SVE get FPSIMD for VL 1728
2166 10:06:57.355492 # ok 436 # SKIP SVE set FPSIMD get SVE for VL 1728
2167 10:06:57.355604 # ok 437 Set SVE VL 1744
2168 10:06:57.355723 # ok 438 # SKIP SVE set SVE get SVE for VL 1744
2169 10:06:57.355840 # ok 439 # SKIP SVE set SVE get FPSIMD for VL 1744
2170 10:06:57.355953 # ok 440 # SKIP SVE set FPSIMD get SVE for VL 1744
2171 10:06:57.356065 # ok 441 Set SVE VL 1760
2172 10:06:57.356176 # ok 442 # SKIP SVE set SVE get SVE for VL 1760
2173 10:06:57.356287 # ok 443 # SKIP SVE set SVE get FPSIMD for VL 1760
2174 10:06:57.356428 # ok 444 # SKIP SVE set FPSIMD get SVE for VL 1760
2175 10:06:57.356546 # ok 445 Set SVE VL 1776
2176 10:06:57.356662 # ok 446 # SKIP SVE set SVE get SVE for VL 1776
2177 10:06:57.356775 # ok 447 # SKIP SVE set SVE get FPSIMD for VL 1776
2178 10:06:57.356886 # ok 448 # SKIP SVE set FPSIMD get SVE for VL 1776
2179 10:06:57.357000 # ok 449 Set SVE VL 1792
2180 10:06:57.357111 # ok 450 # SKIP SVE set SVE get SVE for VL 1792
2181 10:06:57.357221 # ok 451 # SKIP SVE set SVE get FPSIMD for VL 1792
2182 10:06:57.357333 # ok 452 # SKIP SVE set FPSIMD get SVE for VL 1792
2183 10:06:57.357444 # ok 453 Set SVE VL 1808
2184 10:06:57.360287 # ok 454 # SKIP SVE set SVE get SVE for VL 1808
2185 10:06:57.360690 # ok 455 # SKIP SVE set SVE get FPSIMD for VL 1808
2186 10:06:57.360802 # ok 456 # SKIP SVE set FPSIMD get SVE for VL 1808
2187 10:06:57.360894 # ok 457 Set SVE VL 1824
2188 10:06:57.360980 # ok 458 # SKIP SVE set SVE get SVE for VL 1824
2189 10:06:57.361065 # ok 459 # SKIP SVE set SVE get FPSIMD for VL 1824
2190 10:06:57.361150 # ok 460 # SKIP SVE set FPSIMD get SVE for VL 1824
2191 10:06:57.361235 # ok 461 Set SVE VL 1840
2192 10:06:57.361336 # ok 462 # SKIP SVE set SVE get SVE for VL 1840
2193 10:06:57.361424 # ok 463 # SKIP SVE set SVE get FPSIMD for VL 1840
2194 10:06:57.361510 # ok 464 # SKIP SVE set FPSIMD get SVE for VL 1840
2195 10:06:57.361595 # ok 465 Set SVE VL 1856
2196 10:06:57.361706 # ok 466 # SKIP SVE set SVE get SVE for VL 1856
2197 10:06:57.361795 # ok 467 # SKIP SVE set SVE get FPSIMD for VL 1856
2198 10:06:57.361878 # ok 468 # SKIP SVE set FPSIMD get SVE for VL 1856
2199 10:06:57.361976 # ok 469 Set SVE VL 1872
2200 10:06:57.362062 # ok 470 # SKIP SVE set SVE get SVE for VL 1872
2201 10:06:57.362163 # ok 471 # SKIP SVE set SVE get FPSIMD for VL 1872
2202 10:06:57.362265 # ok 472 # SKIP SVE set FPSIMD get SVE for VL 1872
2203 10:06:57.362366 # ok 473 Set SVE VL 1888
2204 10:06:57.362467 # ok 474 # SKIP SVE set SVE get SVE for VL 1888
2205 10:06:57.362571 # ok 475 # SKIP SVE set SVE get FPSIMD for VL 1888
2206 10:06:57.362684 # ok 476 # SKIP SVE set FPSIMD get SVE for VL 1888
2207 10:06:57.362783 # ok 477 Set SVE VL 1904
2208 10:06:57.362882 # ok 478 # SKIP SVE set SVE get SVE for VL 1904
2209 10:06:57.363104 # ok 479 # SKIP SVE set SVE get FPSIMD for VL 1904
2210 10:06:57.369836 # ok 480 # SKIP SVE set FPSIMD get SVE for VL 1904
2211 10:06:57.370020 # ok 481 Set SVE VL 1920
2212 10:06:57.370124 # ok 482 # SKIP SVE set SVE get SVE for VL 1920
2213 10:06:57.370211 # ok 483 # SKIP SVE set SVE get FPSIMD for VL 1920
2214 10:06:57.370296 # ok 484 # SKIP SVE set FPSIMD get SVE for VL 1920
2215 10:06:57.370395 # ok 485 Set SVE VL 1936
2216 10:06:57.370481 # ok 486 # SKIP SVE set SVE get SVE for VL 1936
2217 10:06:57.370583 # ok 487 # SKIP SVE set SVE get FPSIMD for VL 1936
2218 10:06:57.370676 # ok 488 # SKIP SVE set FPSIMD get SVE for VL 1936
2219 10:06:57.370776 # ok 489 Set SVE VL 1952
2220 10:06:57.370876 # ok 490 # SKIP SVE set SVE get SVE for VL 1952
2221 10:06:57.370979 # ok 491 # SKIP SVE set SVE get FPSIMD for VL 1952
2222 10:06:57.371342 # ok 492 # SKIP SVE set FPSIMD get SVE for VL 1952
2223 10:06:57.371447 # ok 493 Set SVE VL 1968
2224 10:06:57.371534 # ok 494 # SKIP SVE set SVE get SVE for VL 1968
2225 10:06:57.371636 # ok 495 # SKIP SVE set SVE get FPSIMD for VL 1968
2226 10:06:57.371744 # ok 496 # SKIP SVE set FPSIMD get SVE for VL 1968
2227 10:06:57.371844 # ok 497 Set SVE VL 1984
2228 10:06:57.372477 # ok 498 # SKIP SVE set SVE get SVE for VL 1984
2229 10:06:57.372955 # ok 499 # SKIP SVE set SVE get FPSIMD for VL 1984
2230 10:06:57.373151 # ok 500 # SKIP SVE set FPSIMD get SVE for VL 1984
2231 10:06:57.373323 # ok 501 Set SVE VL 2000
2232 10:06:57.373491 # ok 502 # SKIP SVE set SVE get SVE for VL 2000
2233 10:06:57.373663 # ok 503 # SKIP SVE set SVE get FPSIMD for VL 2000
2234 10:06:57.373782 # ok 504 # SKIP SVE set FPSIMD get SVE for VL 2000
2235 10:06:57.373894 # ok 505 Set SVE VL 2016
2236 10:06:57.374023 # ok 506 # SKIP SVE set SVE get SVE for VL 2016
2237 10:06:57.374185 # ok 507 # SKIP SVE set SVE get FPSIMD for VL 2016
2238 10:06:57.374338 # ok 508 # SKIP SVE set FPSIMD get SVE for VL 2016
2239 10:06:57.374500 # ok 509 Set SVE VL 2032
2240 10:06:57.374665 # ok 510 # SKIP SVE set SVE get SVE for VL 2032
2241 10:06:57.374823 # ok 511 # SKIP SVE set SVE get FPSIMD for VL 2032
2242 10:06:57.374960 # ok 512 # SKIP SVE set FPSIMD get SVE for VL 2032
2243 10:06:57.375105 # ok 513 Set SVE VL 2048
2244 10:06:57.375219 # ok 514 # SKIP SVE set SVE get SVE for VL 2048
2245 10:06:57.375342 # ok 515 # SKIP SVE set SVE get FPSIMD for VL 2048
2246 10:06:57.375470 # ok 516 # SKIP SVE set FPSIMD get SVE for VL 2048
2247 10:06:57.375603 # ok 517 Set SVE VL 2064
2248 10:06:57.375748 # ok 518 # SKIP SVE set SVE get SVE for VL 2064
2249 10:06:57.375880 # ok 519 # SKIP SVE set SVE get FPSIMD for VL 2064
2250 10:06:57.375978 # ok 520 # SKIP SVE set FPSIMD get SVE for VL 2064
2251 10:06:57.376065 # ok 521 Set SVE VL 2080
2252 10:06:57.376151 # ok 522 # SKIP SVE set SVE get SVE for VL 2080
2253 10:06:57.376237 # ok 523 # SKIP SVE set SVE get FPSIMD for VL 2080
2254 10:06:57.376343 # ok 524 # SKIP SVE set FPSIMD get SVE for VL 2080
2255 10:06:57.376435 # ok 525 Set SVE VL 2096
2256 10:06:57.376520 # ok 526 # SKIP SVE set SVE get SVE for VL 2096
2257 10:06:57.376605 # ok 527 # SKIP SVE set SVE get FPSIMD for VL 2096
2258 10:06:57.376689 # ok 528 # SKIP SVE set FPSIMD get SVE for VL 2096
2259 10:06:57.376777 # ok 529 Set SVE VL 2112
2260 10:06:57.380378 # ok 530 # SKIP SVE set SVE get SVE for VL 2112
2261 10:06:57.380801 # ok 531 # SKIP SVE set SVE get FPSIMD for VL 2112
2262 10:06:57.380979 # ok 532 # SKIP SVE set FPSIMD get SVE for VL 2112
2263 10:06:57.381177 # ok 533 Set SVE VL 2128
2264 10:06:57.381387 # ok 534 # SKIP SVE set SVE get SVE for VL 2128
2265 10:06:57.381635 # ok 535 # SKIP SVE set SVE get FPSIMD for VL 2128
2266 10:06:57.381864 # ok 536 # SKIP SVE set FPSIMD get SVE for VL 2128
2267 10:06:57.382064 # ok 537 Set SVE VL 2144
2268 10:06:57.382224 # ok 538 # SKIP SVE set SVE get SVE for VL 2144
2269 10:06:57.382377 # ok 539 # SKIP SVE set SVE get FPSIMD for VL 2144
2270 10:06:57.382543 # ok 540 # SKIP SVE set FPSIMD get SVE for VL 2144
2271 10:06:57.382714 # ok 541 Set SVE VL 2160
2272 10:06:57.382903 # ok 542 # SKIP SVE set SVE get SVE for VL 2160
2273 10:06:57.383161 # ok 543 # SKIP SVE set SVE get FPSIMD for VL 2160
2274 10:06:57.383356 # ok 544 # SKIP SVE set FPSIMD get SVE for VL 2160
2275 10:06:57.383587 # ok 545 Set SVE VL 2176
2276 10:06:57.383769 # ok 546 # SKIP SVE set SVE get SVE for VL 2176
2277 10:06:57.383958 # ok 547 # SKIP SVE set SVE get FPSIMD for VL 2176
2278 10:06:57.384088 # ok 548 # SKIP SVE set FPSIMD get SVE for VL 2176
2279 10:06:57.384204 # ok 549 Set SVE VL 2192
2280 10:06:57.384315 # ok 550 # SKIP SVE set SVE get SVE for VL 2192
2281 10:06:57.384428 # ok 551 # SKIP SVE set SVE get FPSIMD for VL 2192
2282 10:06:57.384540 # ok 552 # SKIP SVE set FPSIMD get SVE for VL 2192
2283 10:06:57.384651 # ok 553 Set SVE VL 2208
2284 10:06:57.384763 # ok 554 # SKIP SVE set SVE get SVE for VL 2208
2285 10:06:57.384874 # ok 555 # SKIP SVE set SVE get FPSIMD for VL 2208
2286 10:06:57.384986 # ok 556 # SKIP SVE set FPSIMD get SVE for VL 2208
2287 10:06:57.385097 # ok 557 Set SVE VL 2224
2288 10:06:57.385242 # ok 558 # SKIP SVE set SVE get SVE for VL 2224
2289 10:06:57.385362 # ok 559 # SKIP SVE set SVE get FPSIMD for VL 2224
2290 10:06:57.385475 # ok 560 # SKIP SVE set FPSIMD get SVE for VL 2224
2291 10:06:57.385589 # ok 561 Set SVE VL 2240
2292 10:06:57.385790 # ok 562 # SKIP SVE set SVE get SVE for VL 2240
2293 10:06:57.385989 # ok 563 # SKIP SVE set SVE get FPSIMD for VL 2240
2294 10:06:57.390989 # ok 564 # SKIP SVE set FPSIMD get SVE for VL 2240
2295 10:06:57.391416 # ok 565 Set SVE VL 2256
2296 10:06:57.391625 # ok 566 # SKIP SVE set SVE get SVE for VL 2256
2297 10:06:57.391844 # ok 567 # SKIP SVE set SVE get FPSIMD for VL 2256
2298 10:06:57.391998 # ok 568 # SKIP SVE set FPSIMD get SVE for VL 2256
2299 10:06:57.392174 # ok 569 Set SVE VL 2272
2300 10:06:57.392357 # ok 570 # SKIP SVE set SVE get SVE for VL 2272
2301 10:06:57.392531 # ok 571 # SKIP SVE set SVE get FPSIMD for VL 2272
2302 10:06:57.392742 # ok 572 # SKIP SVE set FPSIMD get SVE for VL 2272
2303 10:06:57.392970 # ok 573 Set SVE VL 2288
2304 10:06:57.393171 # ok 574 # SKIP SVE set SVE get SVE for VL 2288
2305 10:06:57.393368 # ok 575 # SKIP SVE set SVE get FPSIMD for VL 2288
2306 10:06:57.393582 # ok 576 # SKIP SVE set FPSIMD get SVE for VL 2288
2307 10:06:57.393772 # ok 577 Set SVE VL 2304
2308 10:06:57.393944 # ok 578 # SKIP SVE set SVE get SVE for VL 2304
2309 10:06:57.394093 # ok 579 # SKIP SVE set SVE get FPSIMD for VL 2304
2310 10:06:57.394235 # ok 580 # SKIP SVE set FPSIMD get SVE for VL 2304
2311 10:06:57.394392 # ok 581 Set SVE VL 2320
2312 10:06:57.394545 # ok 582 # SKIP SVE set SVE get SVE for VL 2320
2313 10:06:57.394689 # ok 583 # SKIP SVE set SVE get FPSIMD for VL 2320
2314 10:06:57.394845 # ok 584 # SKIP SVE set FPSIMD get SVE for VL 2320
2315 10:06:57.395047 # ok 585 Set SVE VL 2336
2316 10:06:57.395209 # ok 586 # SKIP SVE set SVE get SVE for VL 2336
2317 10:06:57.395373 # ok 587 # SKIP SVE set SVE get FPSIMD for VL 2336
2318 10:06:57.395518 # ok 588 # SKIP SVE set FPSIMD get SVE for VL 2336
2319 10:06:57.395647 # ok 589 Set SVE VL 2352
2320 10:06:57.395859 # ok 590 # SKIP SVE set SVE get SVE for VL 2352
2321 10:06:57.396022 # ok 591 # SKIP SVE set SVE get FPSIMD for VL 2352
2322 10:06:57.396166 # ok 592 # SKIP SVE set FPSIMD get SVE for VL 2352
2323 10:06:57.396302 # ok 593 Set SVE VL 2368
2324 10:06:57.396429 # ok 594 # SKIP SVE set SVE get SVE for VL 2368
2325 10:06:57.396580 # ok 595 # SKIP SVE set SVE get FPSIMD for VL 2368
2326 10:06:57.396736 # ok 596 # SKIP SVE set FPSIMD get SVE for VL 2368
2327 10:06:57.396896 # ok 597 Set SVE VL 2384
2328 10:06:57.397050 # ok 598 # SKIP SVE set SVE get SVE for VL 2384
2329 10:06:57.397200 # ok 599 # SKIP SVE set SVE get FPSIMD for VL 2384
2330 10:06:57.397381 # ok 600 # SKIP SVE set FPSIMD get SVE for VL 2384
2331 10:06:57.397514 # ok 601 Set SVE VL 2400
2332 10:06:57.397638 # ok 602 # SKIP SVE set SVE get SVE for VL 2400
2333 10:06:57.397880 # ok 603 # SKIP SVE set SVE get FPSIMD for VL 2400
2334 10:06:57.398069 # ok 604 # SKIP SVE set FPSIMD get SVE for VL 2400
2335 10:06:57.398251 # ok 605 Set SVE VL 2416
2336 10:06:57.398433 # ok 606 # SKIP SVE set SVE get SVE for VL 2416
2337 10:06:57.398615 # ok 607 # SKIP SVE set SVE get FPSIMD for VL 2416
2338 10:06:57.398774 # ok 608 # SKIP SVE set FPSIMD get SVE for VL 2416
2339 10:06:57.399116 # ok 609 Set SVE VL 2432
2340 10:06:57.399222 # ok 610 # SKIP SVE set SVE get SVE for VL 2432
2341 10:06:57.399334 # ok 611 # SKIP SVE set SVE get FPSIMD for VL 2432
2342 10:06:57.399443 # ok 612 # SKIP SVE set FPSIMD get SVE for VL 2432
2343 10:06:57.399551 # ok 613 Set SVE VL 2448
2344 10:06:57.399665 # ok 614 # SKIP SVE set SVE get SVE for VL 2448
2345 10:06:57.399774 # ok 615 # SKIP SVE set SVE get FPSIMD for VL 2448
2346 10:06:57.399863 # ok 616 # SKIP SVE set FPSIMD get SVE for VL 2448
2347 10:06:57.399937 # ok 617 Set SVE VL 2464
2348 10:06:57.400010 # ok 618 # SKIP SVE set SVE get SVE for VL 2464
2349 10:06:57.400082 # ok 619 # SKIP SVE set SVE get FPSIMD for VL 2464
2350 10:06:57.400154 # ok 620 # SKIP SVE set FPSIMD get SVE for VL 2464
2351 10:06:57.400226 # ok 621 Set SVE VL 2480
2352 10:06:57.400297 # ok 622 # SKIP SVE set SVE get SVE for VL 2480
2353 10:06:57.400392 # ok 623 # SKIP SVE set SVE get FPSIMD for VL 2480
2354 10:06:57.400477 # ok 624 # SKIP SVE set FPSIMD get SVE for VL 2480
2355 10:06:57.400557 # ok 625 Set SVE VL 2496
2356 10:06:57.400633 # ok 626 # SKIP SVE set SVE get SVE for VL 2496
2357 10:06:57.400694 # ok 627 # SKIP SVE set SVE get FPSIMD for VL 2496
2358 10:06:57.400773 # ok 628 # SKIP SVE set FPSIMD get SVE for VL 2496
2359 10:06:57.400839 # ok 629 Set SVE VL 2512
2360 10:06:57.400933 # ok 630 # SKIP SVE set SVE get SVE for VL 2512
2361 10:06:57.401004 # ok 631 # SKIP SVE set SVE get FPSIMD for VL 2512
2362 10:06:57.401107 # ok 632 # SKIP SVE set FPSIMD get SVE for VL 2512
2363 10:06:57.401213 # ok 633 Set SVE VL 2528
2364 10:06:57.401312 # ok 634 # SKIP SVE set SVE get SVE for VL 2528
2365 10:06:57.401398 # ok 635 # SKIP SVE set SVE get FPSIMD for VL 2528
2366 10:06:57.401489 # ok 636 # SKIP SVE set FPSIMD get SVE for VL 2528
2367 10:06:57.401563 # ok 637 Set SVE VL 2544
2368 10:06:57.401640 # ok 638 # SKIP SVE set SVE get SVE for VL 2544
2369 10:06:57.401755 # ok 639 # SKIP SVE set SVE get FPSIMD for VL 2544
2370 10:06:57.401853 # ok 640 # SKIP SVE set FPSIMD get SVE for VL 2544
2371 10:06:57.401930 # ok 641 Set SVE VL 2560
2372 10:06:57.401988 # ok 642 # SKIP SVE set SVE get SVE for VL 2560
2373 10:06:57.402044 # ok 643 # SKIP SVE set SVE get FPSIMD for VL 2560
2374 10:06:57.402100 # ok 644 # SKIP SVE set FPSIMD get SVE for VL 2560
2375 10:06:57.402156 # ok 645 Set SVE VL 2576
2376 10:06:57.402212 # ok 646 # SKIP SVE set SVE get SVE for VL 2576
2377 10:06:57.402268 # ok 647 # SKIP SVE set SVE get FPSIMD for VL 2576
2378 10:06:57.402324 # ok 648 # SKIP SVE set FPSIMD get SVE for VL 2576
2379 10:06:57.402380 # ok 649 Set SVE VL 2592
2380 10:06:57.402435 # ok 650 # SKIP SVE set SVE get SVE for VL 2592
2381 10:06:57.402491 # ok 651 # SKIP SVE set SVE get FPSIMD for VL 2592
2382 10:06:57.402738 # ok 652 # SKIP SVE set FPSIMD get SVE for VL 2592
2383 10:06:57.402819 # ok 653 Set SVE VL 2608
2384 10:06:57.402898 # ok 654 # SKIP SVE set SVE get SVE for VL 2608
2385 10:06:57.402972 # ok 655 # SKIP SVE set SVE get FPSIMD for VL 2608
2386 10:06:57.403046 # ok 656 # SKIP SVE set FPSIMD get SVE for VL 2608
2387 10:06:57.403119 # ok 657 Set SVE VL 2624
2388 10:06:57.403190 # ok 658 # SKIP SVE set SVE get SVE for VL 2624
2389 10:06:57.403262 # ok 659 # SKIP SVE set SVE get FPSIMD for VL 2624
2390 10:06:57.403334 # ok 660 # SKIP SVE set FPSIMD get SVE for VL 2624
2391 10:06:57.403406 # ok 661 Set SVE VL 2640
2392 10:06:57.403478 # ok 662 # SKIP SVE set SVE get SVE for VL 2640
2393 10:06:57.403549 # ok 663 # SKIP SVE set SVE get FPSIMD for VL 2640
2394 10:06:57.403623 # ok 664 # SKIP SVE set FPSIMD get SVE for VL 2640
2395 10:06:57.403694 # ok 665 Set SVE VL 2656
2396 10:06:57.403766 # ok 666 # SKIP SVE set SVE get SVE for VL 2656
2397 10:06:57.409246 # ok 667 # SKIP SVE set SVE get FPSIMD for VL 2656
2398 10:06:57.409389 # ok 668 # SKIP SVE set FPSIMD get SVE for VL 2656
2399 10:06:57.409494 # ok 669 Set SVE VL 2672
2400 10:06:57.409598 # ok 670 # SKIP SVE set SVE get SVE for VL 2672
2401 10:06:57.409732 # ok 671 # SKIP SVE set SVE get FPSIMD for VL 2672
2402 10:06:57.409812 # ok 672 # SKIP SVE set FPSIMD get SVE for VL 2672
2403 10:06:57.409894 # ok 673 Set SVE VL 2688
2404 10:06:57.409962 # ok 674 # SKIP SVE set SVE get SVE for VL 2688
2405 10:06:57.410062 # ok 675 # SKIP SVE set SVE get FPSIMD for VL 2688
2406 10:06:57.410153 # ok 676 # SKIP SVE set FPSIMD get SVE for VL 2688
2407 10:06:57.410236 # ok 677 Set SVE VL 2704
2408 10:06:57.410354 # ok 678 # SKIP SVE set SVE get SVE for VL 2704
2409 10:06:57.410436 # ok 679 # SKIP SVE set SVE get FPSIMD for VL 2704
2410 10:06:57.410512 # ok 680 # SKIP SVE set FPSIMD get SVE for VL 2704
2411 10:06:57.410620 # ok 681 Set SVE VL 2720
2412 10:06:57.410709 # ok 682 # SKIP SVE set SVE get SVE for VL 2720
2413 10:06:57.410794 # ok 683 # SKIP SVE set SVE get FPSIMD for VL 2720
2414 10:06:57.410859 # ok 684 # SKIP SVE set FPSIMD get SVE for VL 2720
2415 10:06:57.410924 # ok 685 Set SVE VL 2736
2416 10:06:57.411003 # ok 686 # SKIP SVE set SVE get SVE for VL 2736
2417 10:06:57.411066 # ok 687 # SKIP SVE set SVE get FPSIMD for VL 2736
2418 10:06:57.411142 # ok 688 # SKIP SVE set FPSIMD get SVE for VL 2736
2419 10:06:57.411228 # ok 689 Set SVE VL 2752
2420 10:06:57.411317 # ok 690 # SKIP SVE set SVE get SVE for VL 2752
2421 10:06:57.411393 # ok 691 # SKIP SVE set SVE get FPSIMD for VL 2752
2422 10:06:57.411484 # ok 692 # SKIP SVE set FPSIMD get SVE for VL 2752
2423 10:06:57.411572 # ok 693 Set SVE VL 2768
2424 10:06:57.411660 # ok 694 # SKIP SVE set SVE get SVE for VL 2768
2425 10:06:57.411747 # ok 695 # SKIP SVE set SVE get FPSIMD for VL 2768
2426 10:06:57.412317 # ok 696 # SKIP SVE set FPSIMD get SVE for VL 2768
2427 10:06:57.412604 # ok 697 Set SVE VL 2784
2428 10:06:57.412695 # ok 698 # SKIP SVE set SVE get SVE for VL 2784
2429 10:06:57.412785 # ok 699 # SKIP SVE set SVE get FPSIMD for VL 2784
2430 10:06:57.412892 # ok 700 # SKIP SVE set FPSIMD get SVE for VL 2784
2431 10:06:57.412967 # ok 701 Set SVE VL 2800
2432 10:06:57.413047 # ok 702 # SKIP SVE set SVE get SVE for VL 2800
2433 10:06:57.413142 # ok 703 # SKIP SVE set SVE get FPSIMD for VL 2800
2434 10:06:57.413235 # ok 704 # SKIP SVE set FPSIMD get SVE for VL 2800
2435 10:06:57.413342 # ok 705 Set SVE VL 2816
2436 10:06:57.413447 # ok 706 # SKIP SVE set SVE get SVE for VL 2816
2437 10:06:57.413563 # ok 707 # SKIP SVE set SVE get FPSIMD for VL 2816
2438 10:06:57.413653 # ok 708 # SKIP SVE set FPSIMD get SVE for VL 2816
2439 10:06:57.413746 # ok 709 Set SVE VL 2832
2440 10:06:57.413840 # ok 710 # SKIP SVE set SVE get SVE for VL 2832
2441 10:06:57.413936 # ok 711 # SKIP SVE set SVE get FPSIMD for VL 2832
2442 10:06:57.414033 # ok 712 # SKIP SVE set FPSIMD get SVE for VL 2832
2443 10:06:57.414113 # ok 713 Set SVE VL 2848
2444 10:06:57.414373 # ok 714 # SKIP SVE set SVE get SVE for VL 2848
2445 10:06:57.414463 # ok 715 # SKIP SVE set SVE get FPSIMD for VL 2848
2446 10:06:57.414547 # ok 716 # SKIP SVE set FPSIMD get SVE for VL 2848
2447 10:06:57.414670 # ok 717 Set SVE VL 2864
2448 10:06:57.414771 # ok 718 # SKIP SVE set SVE get SVE for VL 2864
2449 10:06:57.414858 # ok 719 # SKIP SVE set SVE get FPSIMD for VL 2864
2450 10:06:57.414980 # ok 720 # SKIP SVE set FPSIMD get SVE for VL 2864
2451 10:06:57.415088 # ok 721 Set SVE VL 2880
2452 10:06:57.415197 # ok 722 # SKIP SVE set SVE get SVE for VL 2880
2453 10:06:57.415287 # ok 723 # SKIP SVE set SVE get FPSIMD for VL 2880
2454 10:06:57.415373 # ok 724 # SKIP SVE set FPSIMD get SVE for VL 2880
2455 10:06:57.415473 # ok 725 Set SVE VL 2896
2456 10:06:57.415554 # ok 726 # SKIP SVE set SVE get SVE for VL 2896
2457 10:06:57.415628 # ok 727 # SKIP SVE set SVE get FPSIMD for VL 2896
2458 10:06:57.415721 # ok 728 # SKIP SVE set FPSIMD get SVE for VL 2896
2459 10:06:57.415791 # ok 729 Set SVE VL 2912
2460 10:06:57.415867 # ok 730 # SKIP SVE set SVE get SVE for VL 2912
2461 10:06:57.415957 # ok 731 # SKIP SVE set SVE get FPSIMD for VL 2912
2462 10:06:57.416061 # ok 732 # SKIP SVE set FPSIMD get SVE for VL 2912
2463 10:06:57.416153 # ok 733 Set SVE VL 2928
2464 10:06:57.416407 # ok 734 # SKIP SVE set SVE get SVE for VL 2928
2465 10:06:57.416476 # ok 735 # SKIP SVE set SVE get FPSIMD for VL 2928
2466 10:06:57.416536 # ok 736 # SKIP SVE set FPSIMD get SVE for VL 2928
2467 10:06:57.416607 # ok 737 Set SVE VL 2944
2468 10:06:57.416687 # ok 738 # SKIP SVE set SVE get SVE for VL 2944
2469 10:06:57.416769 # ok 739 # SKIP SVE set SVE get FPSIMD for VL 2944
2470 10:06:57.416853 # ok 740 # SKIP SVE set FPSIMD get SVE for VL 2944
2471 10:06:57.416939 # ok 741 Set SVE VL 2960
2472 10:06:57.417012 # ok 742 # SKIP SVE set SVE get SVE for VL 2960
2473 10:06:57.417086 # ok 743 # SKIP SVE set SVE get FPSIMD for VL 2960
2474 10:06:57.417163 # ok 744 # SKIP SVE set FPSIMD get SVE for VL 2960
2475 10:06:57.417241 # ok 745 Set SVE VL 2976
2476 10:06:57.417330 # ok 746 # SKIP SVE set SVE get SVE for VL 2976
2477 10:06:57.417418 # ok 747 # SKIP SVE set SVE get FPSIMD for VL 2976
2478 10:06:57.417701 # ok 748 # SKIP SVE set FPSIMD get SVE for VL 2976
2479 10:06:57.417808 # ok 749 Set SVE VL 2992
2480 10:06:57.417899 # ok 750 # SKIP SVE set SVE get SVE for VL 2992
2481 10:06:57.418002 # ok 751 # SKIP SVE set SVE get FPSIMD for VL 2992
2482 10:06:57.418102 # ok 752 # SKIP SVE set FPSIMD get SVE for VL 2992
2483 10:06:57.418201 # ok 753 Set SVE VL 3008
2484 10:06:57.418297 # ok 754 # SKIP SVE set SVE get SVE for VL 3008
2485 10:06:57.418396 # ok 755 # SKIP SVE set SVE get FPSIMD for VL 3008
2486 10:06:57.418694 # ok 756 # SKIP SVE set FPSIMD get SVE for VL 3008
2487 10:06:57.418817 # ok 757 Set SVE VL 3024
2488 10:06:57.418919 # ok 758 # SKIP SVE set SVE get SVE for VL 3024
2489 10:06:57.419010 # ok 759 # SKIP SVE set SVE get FPSIMD for VL 3024
2490 10:06:57.419111 # ok 760 # SKIP SVE set FPSIMD get SVE for VL 3024
2491 10:06:57.419212 # ok 761 Set SVE VL 3040
2492 10:06:57.419310 # ok 762 # SKIP SVE set SVE get SVE for VL 3040
2493 10:06:57.419412 # ok 763 # SKIP SVE set SVE get FPSIMD for VL 3040
2494 10:06:57.419516 # ok 764 # SKIP SVE set FPSIMD get SVE for VL 3040
2495 10:06:57.419618 # ok 765 Set SVE VL 3056
2496 10:06:57.419911 # ok 766 # SKIP SVE set SVE get SVE for VL 3056
2497 10:06:57.420023 # ok 767 # SKIP SVE set SVE get FPSIMD for VL 3056
2498 10:06:57.420129 # ok 768 # SKIP SVE set FPSIMD get SVE for VL 3056
2499 10:06:57.420230 # ok 769 Set SVE VL 3072
2500 10:06:57.420336 # ok 770 # SKIP SVE set SVE get SVE for VL 3072
2501 10:06:57.420444 # ok 771 # SKIP SVE set SVE get FPSIMD for VL 3072
2502 10:06:57.420782 # ok 772 # SKIP SVE set FPSIMD get SVE for VL 3072
2503 10:06:57.420976 # ok 773 Set SVE VL 3088
2504 10:06:57.421131 # ok 774 # SKIP SVE set SVE get SVE for VL 3088
2505 10:06:57.421281 # ok 775 # SKIP SVE set SVE get FPSIMD for VL 3088
2506 10:06:57.421419 # ok 776 # SKIP SVE set FPSIMD get SVE for VL 3088
2507 10:06:57.421581 # ok 777 Set SVE VL 3104
2508 10:06:57.421792 # ok 778 # SKIP SVE set SVE get SVE for VL 3104
2509 10:06:57.421961 # ok 779 # SKIP SVE set SVE get FPSIMD for VL 3104
2510 10:06:57.422125 # ok 780 # SKIP SVE set FPSIMD get SVE for VL 3104
2511 10:06:57.422291 # ok 781 Set SVE VL 3120
2512 10:06:57.422452 # ok 782 # SKIP SVE set SVE get SVE for VL 3120
2513 10:06:57.422609 # ok 783 # SKIP SVE set SVE get FPSIMD for VL 3120
2514 10:06:57.422746 # ok 784 # SKIP SVE set FPSIMD get SVE for VL 3120
2515 10:06:57.422887 # ok 785 Set SVE VL 3136
2516 10:06:57.422995 # ok 786 # SKIP SVE set SVE get SVE for VL 3136
2517 10:06:57.423113 # ok 787 # SKIP SVE set SVE get FPSIMD for VL 3136
2518 10:06:57.423206 # ok 788 # SKIP SVE set FPSIMD get SVE for VL 3136
2519 10:06:57.423308 # ok 789 Set SVE VL 3152
2520 10:06:57.423419 # ok 790 # SKIP SVE set SVE get SVE for VL 3152
2521 10:06:57.423528 # ok 791 # SKIP SVE set SVE get FPSIMD for VL 3152
2522 10:06:57.423635 # ok 792 # SKIP SVE set FPSIMD get SVE for VL 3152
2523 10:06:57.423736 # ok 793 Set SVE VL 3168
2524 10:06:57.423832 # ok 794 # SKIP SVE set SVE get SVE for VL 3168
2525 10:06:57.423937 # ok 795 # SKIP SVE set SVE get FPSIMD for VL 3168
2526 10:06:57.424067 # ok 796 # SKIP SVE set FPSIMD get SVE for VL 3168
2527 10:06:57.424174 # ok 797 Set SVE VL 3184
2528 10:06:57.424271 # ok 798 # SKIP SVE set SVE get SVE for VL 3184
2529 10:06:57.424377 # ok 799 # SKIP SVE set SVE get FPSIMD for VL 3184
2530 10:06:57.424479 # ok 800 # SKIP SVE set FPSIMD get SVE for VL 3184
2531 10:06:57.424589 # ok 801 Set SVE VL 3200
2532 10:06:57.424711 # ok 802 # SKIP SVE set SVE get SVE for VL 3200
2533 10:06:57.424822 # ok 803 # SKIP SVE set SVE get FPSIMD for VL 3200
2534 10:06:57.424914 # ok 804 # SKIP SVE set FPSIMD get SVE for VL 3200
2535 10:06:57.425029 # ok 805 Set SVE VL 3216
2536 10:06:57.425135 # ok 806 # SKIP SVE set SVE get SVE for VL 3216
2537 10:06:57.425283 # ok 807 # SKIP SVE set SVE get FPSIMD for VL 3216
2538 10:06:57.425398 # ok 808 # SKIP SVE set FPSIMD get SVE for VL 3216
2539 10:06:57.425507 # ok 809 Set SVE VL 3232
2540 10:06:57.425609 # ok 810 # SKIP SVE set SVE get SVE for VL 3232
2541 10:06:57.425769 # ok 811 # SKIP SVE set SVE get FPSIMD for VL 3232
2542 10:06:57.425917 # ok 812 # SKIP SVE set FPSIMD get SVE for VL 3232
2543 10:06:57.426055 # ok 813 Set SVE VL 3248
2544 10:06:57.426191 # ok 814 # SKIP SVE set SVE get SVE for VL 3248
2545 10:06:57.426329 # ok 815 # SKIP SVE set SVE get FPSIMD for VL 3248
2546 10:06:57.426680 # ok 816 # SKIP SVE set FPSIMD get SVE for VL 3248
2547 10:06:57.426800 # ok 817 Set SVE VL 3264
2548 10:06:57.426869 # ok 818 # SKIP SVE set SVE get SVE for VL 3264
2549 10:06:57.426939 # ok 819 # SKIP SVE set SVE get FPSIMD for VL 3264
2550 10:06:57.427009 # ok 820 # SKIP SVE set FPSIMD get SVE for VL 3264
2551 10:06:57.427084 # ok 821 Set SVE VL 3280
2552 10:06:57.427164 # ok 822 # SKIP SVE set SVE get SVE for VL 3280
2553 10:06:57.427243 # ok 823 # SKIP SVE set SVE get FPSIMD for VL 3280
2554 10:06:57.427320 # ok 824 # SKIP SVE set FPSIMD get SVE for VL 3280
2555 10:06:57.427399 # ok 825 Set SVE VL 3296
2556 10:06:57.427479 # ok 826 # SKIP SVE set SVE get SVE for VL 3296
2557 10:06:57.427562 # ok 827 # SKIP SVE set SVE get FPSIMD for VL 3296
2558 10:06:57.427643 # ok 828 # SKIP SVE set FPSIMD get SVE for VL 3296
2559 10:06:57.427733 # ok 829 Set SVE VL 3312
2560 10:06:57.427796 # ok 830 # SKIP SVE set SVE get SVE for VL 3312
2561 10:06:57.427859 # ok 831 # SKIP SVE set SVE get FPSIMD for VL 3312
2562 10:06:57.427917 # ok 832 # SKIP SVE set FPSIMD get SVE for VL 3312
2563 10:06:57.427975 # ok 833 Set SVE VL 3328
2564 10:06:57.428059 # ok 834 # SKIP SVE set SVE get SVE for VL 3328
2565 10:06:57.428130 # ok 835 # SKIP SVE set SVE get FPSIMD for VL 3328
2566 10:06:57.428201 # ok 836 # SKIP SVE set FPSIMD get SVE for VL 3328
2567 10:06:57.428262 # ok 837 Set SVE VL 3344
2568 10:06:57.428329 # ok 838 # SKIP SVE set SVE get SVE for VL 3344
2569 10:06:57.428415 # ok 839 # SKIP SVE set SVE get FPSIMD for VL 3344
2570 10:06:57.428498 # ok 840 # SKIP SVE set FPSIMD get SVE for VL 3344
2571 10:06:57.428574 # ok 841 Set SVE VL 3360
2572 10:06:57.428648 # ok 842 # SKIP SVE set SVE get SVE for VL 3360
2573 10:06:57.428721 # ok 843 # SKIP SVE set SVE get FPSIMD for VL 3360
2574 10:06:57.428799 # ok 844 # SKIP SVE set FPSIMD get SVE for VL 3360
2575 10:06:57.428860 # ok 845 Set SVE VL 3376
2576 10:06:57.428918 # ok 846 # SKIP SVE set SVE get SVE for VL 3376
2577 10:06:57.428993 # ok 847 # SKIP SVE set SVE get FPSIMD for VL 3376
2578 10:06:57.429086 # ok 848 # SKIP SVE set FPSIMD get SVE for VL 3376
2579 10:06:57.429156 # ok 849 Set SVE VL 3392
2580 10:06:57.429215 # ok 850 # SKIP SVE set SVE get SVE for VL 3392
2581 10:06:57.429286 # ok 851 # SKIP SVE set SVE get FPSIMD for VL 3392
2582 10:06:57.429346 # ok 852 # SKIP SVE set FPSIMD get SVE for VL 3392
2583 10:06:57.429406 # ok 853 Set SVE VL 3408
2584 10:06:57.429464 # ok 854 # SKIP SVE set SVE get SVE for VL 3408
2585 10:06:57.435698 # ok 855 # SKIP SVE set SVE get FPSIMD for VL 3408
2586 10:06:57.435871 # ok 856 # SKIP SVE set FPSIMD get SVE for VL 3408
2587 10:06:57.436231 # ok 857 Set SVE VL 3424
2588 10:06:57.436523 # ok 858 # SKIP SVE set SVE get SVE for VL 3424
2589 10:06:57.436617 # ok 859 # SKIP SVE set SVE get FPSIMD for VL 3424
2590 10:06:57.436709 # ok 860 # SKIP SVE set FPSIMD get SVE for VL 3424
2591 10:06:57.436789 # ok 861 Set SVE VL 3440
2592 10:06:57.436867 # ok 862 # SKIP SVE set SVE get SVE for VL 3440
2593 10:06:57.436960 # ok 863 # SKIP SVE set SVE get FPSIMD for VL 3440
2594 10:06:57.437064 # ok 864 # SKIP SVE set FPSIMD get SVE for VL 3440
2595 10:06:57.437183 # ok 865 Set SVE VL 3456
2596 10:06:57.437271 # ok 866 # SKIP SVE set SVE get SVE for VL 3456
2597 10:06:57.437364 # ok 867 # SKIP SVE set SVE get FPSIMD for VL 3456
2598 10:06:57.437427 # ok 868 # SKIP SVE set FPSIMD get SVE for VL 3456
2599 10:06:57.437505 # ok 869 Set SVE VL 3472
2600 10:06:57.437586 # ok 870 # SKIP SVE set SVE get SVE for VL 3472
2601 10:06:57.437681 # ok 871 # SKIP SVE set SVE get FPSIMD for VL 3472
2602 10:06:57.437762 # ok 872 # SKIP SVE set FPSIMD get SVE for VL 3472
2603 10:06:57.437846 # ok 873 Set SVE VL 3488
2604 10:06:57.437940 # ok 874 # SKIP SVE set SVE get SVE for VL 3488
2605 10:06:57.438035 # ok 875 # SKIP SVE set SVE get FPSIMD for VL 3488
2606 10:06:57.438127 # ok 876 # SKIP SVE set FPSIMD get SVE for VL 3488
2607 10:06:57.438223 # ok 877 Set SVE VL 3504
2608 10:06:57.438373 # ok 878 # SKIP SVE set SVE get SVE for VL 3504
2609 10:06:57.438605 # ok 879 # SKIP SVE set SVE get FPSIMD for VL 3504
2610 10:06:57.438793 # ok 880 # SKIP SVE set FPSIMD get SVE for VL 3504
2611 10:06:57.438917 # ok 881 Set SVE VL 3520
2612 10:06:57.439034 # ok 882 # SKIP SVE set SVE get SVE for VL 3520
2613 10:06:57.439171 # ok 883 # SKIP SVE set SVE get FPSIMD for VL 3520
2614 10:06:57.439291 # ok 884 # SKIP SVE set FPSIMD get SVE for VL 3520
2615 10:06:57.439408 # ok 885 Set SVE VL 3536
2616 10:06:57.439525 # ok 886 # SKIP SVE set SVE get SVE for VL 3536
2617 10:06:57.439672 # ok 887 # SKIP SVE set SVE get FPSIMD for VL 3536
2618 10:06:57.439797 # ok 888 # SKIP SVE set FPSIMD get SVE for VL 3536
2619 10:06:57.439915 # ok 889 Set SVE VL 3552
2620 10:06:57.440030 # ok 890 # SKIP SVE set SVE get SVE for VL 3552
2621 10:06:57.440145 # ok 891 # SKIP SVE set SVE get FPSIMD for VL 3552
2622 10:06:57.440283 # ok 892 # SKIP SVE set FPSIMD get SVE for VL 3552
2623 10:06:57.440405 # ok 893 Set SVE VL 3568
2624 10:06:57.440521 # ok 894 # SKIP SVE set SVE get SVE for VL 3568
2625 10:06:57.440637 # ok 895 # SKIP SVE set SVE get FPSIMD for VL 3568
2626 10:06:57.440753 # ok 896 # SKIP SVE set FPSIMD get SVE for VL 3568
2627 10:06:57.440874 # ok 897 Set SVE VL 3584
2628 10:06:57.441011 # ok 898 # SKIP SVE set SVE get SVE for VL 3584
2629 10:06:57.441131 # ok 899 # SKIP SVE set SVE get FPSIMD for VL 3584
2630 10:06:57.441248 # ok 900 # SKIP SVE set FPSIMD get SVE for VL 3584
2631 10:06:57.441364 # ok 901 Set SVE VL 3600
2632 10:06:57.441703 # ok 902 # SKIP SVE set SVE get SVE for VL 3600
2633 10:06:57.441820 # ok 903 # SKIP SVE set SVE get FPSIMD for VL 3600
2634 10:06:57.441901 # ok 904 # SKIP SVE set FPSIMD get SVE for VL 3600
2635 10:06:57.441982 # ok 905 Set SVE VL 3616
2636 10:06:57.442061 # ok 906 # SKIP SVE set SVE get SVE for VL 3616
2637 10:06:57.442139 # ok 907 # SKIP SVE set SVE get FPSIMD for VL 3616
2638 10:06:57.442218 # ok 908 # SKIP SVE set FPSIMD get SVE for VL 3616
2639 10:06:57.442298 # ok 909 Set SVE VL 3632
2640 10:06:57.442377 # ok 910 # SKIP SVE set SVE get SVE for VL 3632
2641 10:06:57.442472 # ok 911 # SKIP SVE set SVE get FPSIMD for VL 3632
2642 10:06:57.442555 # ok 912 # SKIP SVE set FPSIMD get SVE for VL 3632
2643 10:06:57.442635 # ok 913 Set SVE VL 3648
2644 10:06:57.442714 # ok 914 # SKIP SVE set SVE get SVE for VL 3648
2645 10:06:57.442794 # ok 915 # SKIP SVE set SVE get FPSIMD for VL 3648
2646 10:06:57.442873 # ok 916 # SKIP SVE set FPSIMD get SVE for VL 3648
2647 10:06:57.442968 # ok 917 Set SVE VL 3664
2648 10:06:57.443050 # ok 918 # SKIP SVE set SVE get SVE for VL 3664
2649 10:06:57.443130 # ok 919 # SKIP SVE set SVE get FPSIMD for VL 3664
2650 10:06:57.443209 # ok 920 # SKIP SVE set FPSIMD get SVE for VL 3664
2651 10:06:57.443288 # ok 921 Set SVE VL 3680
2652 10:06:57.443368 # ok 922 # SKIP SVE set SVE get SVE for VL 3680
2653 10:06:57.443462 # ok 923 # SKIP SVE set SVE get FPSIMD for VL 3680
2654 10:06:57.443544 # ok 924 # SKIP SVE set FPSIMD get SVE for VL 3680
2655 10:06:57.443625 # ok 925 Set SVE VL 3696
2656 10:06:57.443704 # ok 926 # SKIP SVE set SVE get SVE for VL 3696
2657 10:06:57.443798 # ok 927 # SKIP SVE set SVE get FPSIMD for VL 3696
2658 10:06:57.443880 # ok 928 # SKIP SVE set FPSIMD get SVE for VL 3696
2659 10:06:57.443974 # ok 929 Set SVE VL 3712
2660 10:06:57.444059 # ok 930 # SKIP SVE set SVE get SVE for VL 3712
2661 10:06:57.444151 # ok 931 # SKIP SVE set SVE get FPSIMD for VL 3712
2662 10:06:57.444244 # ok 932 # SKIP SVE set FPSIMD get SVE for VL 3712
2663 10:06:57.444530 # ok 933 Set SVE VL 3728
2664 10:06:57.444634 # ok 934 # SKIP SVE set SVE get SVE for VL 3728
2665 10:06:57.444739 # ok 935 # SKIP SVE set SVE get FPSIMD for VL 3728
2666 10:06:57.444833 # ok 936 # SKIP SVE set FPSIMD get SVE for VL 3728
2667 10:06:57.444930 # ok 937 Set SVE VL 3744
2668 10:06:57.445014 # ok 938 # SKIP SVE set SVE get SVE for VL 3744
2669 10:06:57.445111 # ok 939 # SKIP SVE set SVE get FPSIMD for VL 3744
2670 10:06:57.445209 # ok 940 # SKIP SVE set FPSIMD get SVE for VL 3744
2671 10:06:57.445308 # ok 941 Set SVE VL 3760
2672 10:06:57.445404 # ok 942 # SKIP SVE set SVE get SVE for VL 3760
2673 10:06:57.445509 # ok 943 # SKIP SVE set SVE get FPSIMD for VL 3760
2674 10:06:57.445825 # ok 944 # SKIP SVE set FPSIMD get SVE for VL 3760
2675 10:06:57.445927 # ok 945 Set SVE VL 3776
2676 10:06:57.446029 # ok 946 # SKIP SVE set SVE get SVE for VL 3776
2677 10:06:57.446116 # ok 947 # SKIP SVE set SVE get FPSIMD for VL 3776
2678 10:06:57.446215 # ok 948 # SKIP SVE set FPSIMD get SVE for VL 3776
2679 10:06:57.446300 # ok 949 Set SVE VL 3792
2680 10:06:57.446398 # ok 950 # SKIP SVE set SVE get SVE for VL 3792
2681 10:06:57.446682 # ok 951 # SKIP SVE set SVE get FPSIMD for VL 3792
2682 10:06:57.446781 # ok 952 # SKIP SVE set FPSIMD get SVE for VL 3792
2683 10:06:57.446890 # ok 953 Set SVE VL 3808
2684 10:06:57.446977 # ok 954 # SKIP SVE set SVE get SVE for VL 3808
2685 10:06:57.447076 # ok 955 # SKIP SVE set SVE get FPSIMD for VL 3808
2686 10:06:57.447177 # ok 956 # SKIP SVE set FPSIMD get SVE for VL 3808
2687 10:06:57.447279 # ok 957 Set SVE VL 3824
2688 10:06:57.447379 # ok 958 # SKIP SVE set SVE get SVE for VL 3824
2689 10:06:57.447481 # ok 959 # SKIP SVE set SVE get FPSIMD for VL 3824
2690 10:06:57.447775 # ok 960 # SKIP SVE set FPSIMD get SVE for VL 3824
2691 10:06:57.447869 # ok 961 Set SVE VL 3840
2692 10:06:57.448156 # ok 962 # SKIP SVE set SVE get SVE for VL 3840
2693 10:06:57.448262 # ok 963 # SKIP SVE set SVE get FPSIMD for VL 3840
2694 10:06:57.448346 # ok 964 # SKIP SVE set FPSIMD get SVE for VL 3840
2695 10:06:57.448447 # ok 965 Set SVE VL 3856
2696 10:06:57.448547 # ok 966 # SKIP SVE set SVE get SVE for VL 3856
2697 10:06:57.448647 # ok 967 # SKIP SVE set SVE get FPSIMD for VL 3856
2698 10:06:57.448748 # ok 968 # SKIP SVE set FPSIMD get SVE for VL 3856
2699 10:06:57.448853 # ok 969 Set SVE VL 3872
2700 10:06:57.448953 # ok 970 # SKIP SVE set SVE get SVE for VL 3872
2701 10:06:57.449240 # ok 971 # SKIP SVE set SVE get FPSIMD for VL 3872
2702 10:06:57.449331 # ok 972 # SKIP SVE set FPSIMD get SVE for VL 3872
2703 10:06:57.449431 # ok 973 Set SVE VL 3888
2704 10:06:57.449519 # ok 974 # SKIP SVE set SVE get SVE for VL 3888
2705 10:06:57.449619 # ok 975 # SKIP SVE set SVE get FPSIMD for VL 3888
2706 10:06:57.449729 # ok 976 # SKIP SVE set FPSIMD get SVE for VL 3888
2707 10:06:57.449829 # ok 977 Set SVE VL 3904
2708 10:06:57.449928 # ok 978 # SKIP SVE set SVE get SVE for VL 3904
2709 10:06:57.450036 # ok 979 # SKIP SVE set SVE get FPSIMD for VL 3904
2710 10:06:57.450135 # ok 980 # SKIP SVE set FPSIMD get SVE for VL 3904
2711 10:06:57.450235 # ok 981 Set SVE VL 3920
2712 10:06:57.450336 # ok 982 # SKIP SVE set SVE get SVE for VL 3920
2713 10:06:57.450625 # ok 983 # SKIP SVE set SVE get FPSIMD for VL 3920
2714 10:06:57.450706 # ok 984 # SKIP SVE set FPSIMD get SVE for VL 3920
2715 10:06:57.450788 # ok 985 Set SVE VL 3936
2716 10:06:57.450882 # ok 986 # SKIP SVE set SVE get SVE for VL 3936
2717 10:06:57.450974 # ok 987 # SKIP SVE set SVE get FPSIMD for VL 3936
2718 10:06:57.451069 # ok 988 # SKIP SVE set FPSIMD get SVE for VL 3936
2719 10:06:57.451343 # ok 989 Set SVE VL 3952
2720 10:06:57.451432 # ok 990 # SKIP SVE set SVE get SVE for VL 3952
2721 10:06:57.451508 # ok 991 # SKIP SVE set SVE get FPSIMD for VL 3952
2722 10:06:57.451597 # ok 992 # SKIP SVE set FPSIMD get SVE for VL 3952
2723 10:06:57.451672 # ok 993 Set SVE VL 3968
2724 10:06:57.451754 # ok 994 # SKIP SVE set SVE get SVE for VL 3968
2725 10:06:57.452020 # ok 995 # SKIP SVE set SVE get FPSIMD for VL 3968
2726 10:06:57.452121 # ok 996 # SKIP SVE set FPSIMD get SVE for VL 3968
2727 10:06:57.452222 # ok 997 Set SVE VL 3984
2728 10:06:57.452306 # ok 998 # SKIP SVE set SVE get SVE for VL 3984
2729 10:06:57.452401 # ok 999 # SKIP SVE set SVE get FPSIMD for VL 3984
2730 10:06:57.452500 # ok 1000 # SKIP SVE set FPSIMD get SVE for VL 3984
2731 10:06:57.452828 # ok 1001 Set SVE VL 4000
2732 10:06:57.452928 # ok 1002 # SKIP SVE set SVE get SVE for VL 4000
2733 10:06:57.453028 # ok 1003 # SKIP SVE set SVE get FPSIMD for VL 4000
2734 10:06:57.453129 # ok 1004 # SKIP SVE set FPSIMD get SVE for VL 4000
2735 10:06:57.453414 # ok 1005 Set SVE VL 4016
2736 10:06:57.453512 # ok 1006 # SKIP SVE set SVE get SVE for VL 4016
2737 10:06:57.453632 # ok 1007 # SKIP SVE set SVE get FPSIMD for VL 4016
2738 10:06:57.454058 # ok 1008 # SKIP SVE set FPSIMD get SVE for VL 4016
2739 10:06:57.454160 # ok 1009 Set SVE VL 4032
2740 10:06:57.454248 # ok 1010 # SKIP SVE set SVE get SVE for VL 4032
2741 10:06:57.454346 # ok 1011 # SKIP SVE set SVE get FPSIMD for VL 4032
2742 10:06:57.454452 # ok 1012 # SKIP SVE set FPSIMD get SVE for VL 4032
2743 10:06:57.454755 # ok 1013 Set SVE VL 4048
2744 10:06:57.454859 # ok 1014 # SKIP SVE set SVE get SVE for VL 4048
2745 10:06:57.454953 # ok 1015 # SKIP SVE set SVE get FPSIMD for VL 4048
2746 10:06:57.455019 # ok 1016 # SKIP SVE set FPSIMD get SVE for VL 4048
2747 10:06:57.455114 # ok 1017 Set SVE VL 4064
2748 10:06:57.455219 # ok 1018 # SKIP SVE set SVE get SVE for VL 4064
2749 10:06:57.455318 # ok 1019 # SKIP SVE set SVE get FPSIMD for VL 4064
2750 10:06:57.455397 # ok 1020 # SKIP SVE set FPSIMD get SVE for VL 4064
2751 10:06:57.455476 # ok 1021 Set SVE VL 4080
2752 10:06:57.455567 # ok 1022 # SKIP SVE set SVE get SVE for VL 4080
2753 10:06:57.455644 # ok 1023 # SKIP SVE set SVE get FPSIMD for VL 4080
2754 10:06:57.455758 # ok 1024 # SKIP SVE set FPSIMD get SVE for VL 4080
2755 10:06:57.455830 # ok 1025 Set SVE VL 4096
2756 10:06:57.455925 # ok 1026 # SKIP SVE set SVE get SVE for VL 4096
2757 10:06:57.456025 # ok 1027 # SKIP SVE set SVE get FPSIMD for VL 4096
2758 10:06:57.456139 # ok 1028 # SKIP SVE set FPSIMD get SVE for VL 4096
2759 10:06:57.456229 # ok 1029 Set SVE VL 4112
2760 10:06:57.456313 # ok 1030 # SKIP SVE set SVE get SVE for VL 4112
2761 10:06:57.456419 # ok 1031 # SKIP SVE set SVE get FPSIMD for VL 4112
2762 10:06:57.456516 # ok 1032 # SKIP SVE set FPSIMD get SVE for VL 4112
2763 10:06:57.456626 # ok 1033 Set SVE VL 4128
2764 10:06:57.456722 # ok 1034 # SKIP SVE set SVE get SVE for VL 4128
2765 10:06:57.456830 # ok 1035 # SKIP SVE set SVE get FPSIMD for VL 4128
2766 10:06:57.456942 # ok 1036 # SKIP SVE set FPSIMD get SVE for VL 4128
2767 10:06:57.457043 # ok 1037 Set SVE VL 4144
2768 10:06:57.457153 # ok 1038 # SKIP SVE set SVE get SVE for VL 4144
2769 10:06:57.457237 # ok 1039 # SKIP SVE set SVE get FPSIMD for VL 4144
2770 10:06:57.457326 # ok 1040 # SKIP SVE set FPSIMD get SVE for VL 4144
2771 10:06:57.465230 # ok 1041 Set SVE VL 4160
2772 10:06:57.465467 # ok 1042 # SKIP SVE set SVE get SVE for VL 4160
2773 10:06:57.465561 # ok 1043 # SKIP SVE set SVE get FPSIMD for VL 4160
2774 10:06:57.465677 # ok 1044 # SKIP SVE set FPSIMD get SVE for VL 4160
2775 10:06:57.465772 # ok 1045 Set SVE VL 4176
2776 10:06:57.465862 # ok 1046 # SKIP SVE set SVE get SVE for VL 4176
2777 10:06:57.465951 # ok 1047 # SKIP SVE set SVE get FPSIMD for VL 4176
2778 10:06:57.466055 # ok 1048 # SKIP SVE set FPSIMD get SVE for VL 4176
2779 10:06:57.466149 # ok 1049 Set SVE VL 4192
2780 10:06:57.466238 # ok 1050 # SKIP SVE set SVE get SVE for VL 4192
2781 10:06:57.466326 # ok 1051 # SKIP SVE set SVE get FPSIMD for VL 4192
2782 10:06:57.466430 # ok 1052 # SKIP SVE set FPSIMD get SVE for VL 4192
2783 10:06:57.466523 # ok 1053 Set SVE VL 4208
2784 10:06:57.466612 # ok 1054 # SKIP SVE set SVE get SVE for VL 4208
2785 10:06:57.466701 # ok 1055 # SKIP SVE set SVE get FPSIMD for VL 4208
2786 10:06:57.466790 # ok 1056 # SKIP SVE set FPSIMD get SVE for VL 4208
2787 10:06:57.466897 # ok 1057 Set SVE VL 4224
2788 10:06:57.466988 # ok 1058 # SKIP SVE set SVE get SVE for VL 4224
2789 10:06:57.467073 # ok 1059 # SKIP SVE set SVE get FPSIMD for VL 4224
2790 10:06:57.467156 # ok 1060 # SKIP SVE set FPSIMD get SVE for VL 4224
2791 10:06:57.467243 # ok 1061 Set SVE VL 4240
2792 10:06:57.467349 # ok 1062 # SKIP SVE set SVE get SVE for VL 4240
2793 10:06:57.467438 # ok 1063 # SKIP SVE set SVE get FPSIMD for VL 4240
2794 10:06:57.467528 # ok 1064 # SKIP SVE set FPSIMD get SVE for VL 4240
2795 10:06:57.467616 # ok 1065 Set SVE VL 4256
2796 10:06:57.467703 # ok 1066 # SKIP SVE set SVE get SVE for VL 4256
2797 10:06:57.467790 # ok 1067 # SKIP SVE set SVE get FPSIMD for VL 4256
2798 10:06:57.467899 # ok 1068 # SKIP SVE set FPSIMD get SVE for VL 4256
2799 10:06:57.467989 # ok 1069 Set SVE VL 4272
2800 10:06:57.468078 # ok 1070 # SKIP SVE set SVE get SVE for VL 4272
2801 10:06:57.469904 # ok 1071 # SKIP SVE set SVE get FPSIMD for VL 4272
2802 10:06:57.470238 # ok 1072 # SKIP SVE set FPSIMD get SVE for VL 4272
2803 10:06:57.470339 # ok 1073 Set SVE VL 4288
2804 10:06:57.470430 # ok 1074 # SKIP SVE set SVE get SVE for VL 4288
2805 10:06:57.470535 # ok 1075 # SKIP SVE set SVE get FPSIMD for VL 4288
2806 10:06:57.470626 # ok 1076 # SKIP SVE set FPSIMD get SVE for VL 4288
2807 10:06:57.470715 # ok 1077 Set SVE VL 4304
2808 10:06:57.470821 # ok 1078 # SKIP SVE set SVE get SVE for VL 4304
2809 10:06:57.470917 # ok 1079 # SKIP SVE set SVE get FPSIMD for VL 4304
2810 10:06:57.471008 # ok 1080 # SKIP SVE set FPSIMD get SVE for VL 4304
2811 10:06:57.471094 # ok 1081 Set SVE VL 4320
2812 10:06:57.471199 # ok 1082 # SKIP SVE set SVE get SVE for VL 4320
2813 10:06:57.471291 # ok 1083 # SKIP SVE set SVE get FPSIMD for VL 4320
2814 10:06:57.471380 # ok 1084 # SKIP SVE set FPSIMD get SVE for VL 4320
2815 10:06:57.471485 # ok 1085 Set SVE VL 4336
2816 10:06:57.471575 # ok 1086 # SKIP SVE set SVE get SVE for VL 4336
2817 10:06:57.471679 # ok 1087 # SKIP SVE set SVE get FPSIMD for VL 4336
2818 10:06:57.471785 # ok 1088 # SKIP SVE set FPSIMD get SVE for VL 4336
2819 10:06:57.472820 # ok 1089 Set SVE VL 4352
2820 10:06:57.473098 # ok 1090 # SKIP SVE set SVE get SVE for VL 4352
2821 10:06:57.473193 # ok 1091 # SKIP SVE set SVE get FPSIMD for VL 4352
2822 10:06:57.473297 # ok 1092 # SKIP SVE set FPSIMD get SVE for VL 4352
2823 10:06:57.473402 # ok 1093 Set SVE VL 4368
2824 10:06:57.473508 # ok 1094 # SKIP SVE set SVE get SVE for VL 4368
2825 10:06:57.473614 # ok 1095 # SKIP SVE set SVE get FPSIMD for VL 4368
2826 10:06:57.473728 # ok 1096 # SKIP SVE set FPSIMD get SVE for VL 4368
2827 10:06:57.473820 # ok 1097 Set SVE VL 4384
2828 10:06:57.473931 # ok 1098 # SKIP SVE set SVE get SVE for VL 4384
2829 10:06:57.474022 # ok 1099 # SKIP SVE set SVE get FPSIMD for VL 4384
2830 10:06:57.474123 # ok 1100 # SKIP SVE set FPSIMD get SVE for VL 4384
2831 10:06:57.474214 # ok 1101 Set SVE VL 4400
2832 10:06:57.474320 # ok 1102 # SKIP SVE set SVE get SVE for VL 4400
2833 10:06:57.474411 # ok 1103 # SKIP SVE set SVE get FPSIMD for VL 4400
2834 10:06:57.474514 # ok 1104 # SKIP SVE set FPSIMD get SVE for VL 4400
2835 10:06:57.474597 # ok 1105 Set SVE VL 4416
2836 10:06:57.474684 # ok 1106 # SKIP SVE set SVE get SVE for VL 4416
2837 10:06:57.474789 # ok 1107 # SKIP SVE set SVE get FPSIMD for VL 4416
2838 10:06:57.474882 # ok 1108 # SKIP SVE set FPSIMD get SVE for VL 4416
2839 10:06:57.474988 # ok 1109 Set SVE VL 4432
2840 10:06:57.475079 # ok 1110 # SKIP SVE set SVE get SVE for VL 4432
2841 10:06:57.475184 # ok 1111 # SKIP SVE set SVE get FPSIMD for VL 4432
2842 10:06:57.475276 # ok 1112 # SKIP SVE set FPSIMD get SVE for VL 4432
2843 10:06:57.475379 # ok 1113 Set SVE VL 4448
2844 10:06:57.475471 # ok 1114 # SKIP SVE set SVE get SVE for VL 4448
2845 10:06:57.475576 # ok 1115 # SKIP SVE set SVE get FPSIMD for VL 4448
2846 10:06:57.475668 # ok 1116 # SKIP SVE set FPSIMD get SVE for VL 4448
2847 10:06:57.475771 # ok 1117 Set SVE VL 4464
2848 10:06:57.475885 # ok 1118 # SKIP SVE set SVE get SVE for VL 4464
2849 10:06:57.476198 # ok 1119 # SKIP SVE set SVE get FPSIMD for VL 4464
2850 10:06:57.476303 # ok 1120 # SKIP SVE set FPSIMD get SVE for VL 4464
2851 10:06:57.476391 # ok 1121 Set SVE VL 4480
2852 10:06:57.476487 # ok 1122 # SKIP SVE set SVE get SVE for VL 4480
2853 10:06:57.476584 # ok 1123 # SKIP SVE set SVE get FPSIMD for VL 4480
2854 10:06:57.477170 # ok 1124 # SKIP SVE set FPSIMD get SVE for VL 4480
2855 10:06:57.477266 # ok 1125 Set SVE VL 4496
2856 10:06:57.477349 # ok 1126 # SKIP SVE set SVE get SVE for VL 4496
2857 10:06:57.477630 # ok 1127 # SKIP SVE set SVE get FPSIMD for VL 4496
2858 10:06:57.477739 # ok 1128 # SKIP SVE set FPSIMD get SVE for VL 4496
2859 10:06:57.477824 # ok 1129 Set SVE VL 4512
2860 10:06:57.477909 # ok 1130 # SKIP SVE set SVE get SVE for VL 4512
2861 10:06:57.478010 # ok 1131 # SKIP SVE set SVE get FPSIMD for VL 4512
2862 10:06:57.478098 # ok 1132 # SKIP SVE set FPSIMD get SVE for VL 4512
2863 10:06:57.478200 # ok 1133 Set SVE VL 4528
2864 10:06:57.478287 # ok 1134 # SKIP SVE set SVE get SVE for VL 4528
2865 10:06:57.478386 # ok 1135 # SKIP SVE set SVE get FPSIMD for VL 4528
2866 10:06:57.478671 # ok 1136 # SKIP SVE set FPSIMD get SVE for VL 4528
2867 10:06:57.478760 # ok 1137 Set SVE VL 4544
2868 10:06:57.478841 # ok 1138 # SKIP SVE set SVE get SVE for VL 4544
2869 10:06:57.478938 # ok 1139 # SKIP SVE set SVE get FPSIMD for VL 4544
2870 10:06:57.479036 # ok 1140 # SKIP SVE set FPSIMD get SVE for VL 4544
2871 10:06:57.479118 # ok 1141 Set SVE VL 4560
2872 10:06:57.479404 # ok 1142 # SKIP SVE set SVE get SVE for VL 4560
2873 10:06:57.479494 # ok 1143 # SKIP SVE set SVE get FPSIMD for VL 4560
2874 10:06:57.479592 # ok 1144 # SKIP SVE set FPSIMD get SVE for VL 4560
2875 10:06:57.479680 # ok 1145 Set SVE VL 4576
2876 10:06:57.479776 # ok 1146 # SKIP SVE set SVE get SVE for VL 4576
2877 10:06:57.480064 # ok 1147 # SKIP SVE set SVE get FPSIMD for VL 4576
2878 10:06:57.480178 # ok 1148 # SKIP SVE set FPSIMD get SVE for VL 4576
2879 10:06:57.480277 # ok 1149 Set SVE VL 4592
2880 10:06:57.480375 # ok 1150 # SKIP SVE set SVE get SVE for VL 4592
2881 10:06:57.480657 # ok 1151 # SKIP SVE set SVE get FPSIMD for VL 4592
2882 10:06:57.480744 # ok 1152 # SKIP SVE set FPSIMD get SVE for VL 4592
2883 10:06:57.480842 # ok 1153 Set SVE VL 4608
2884 10:06:57.480926 # ok 1154 # SKIP SVE set SVE get SVE for VL 4608
2885 10:06:57.481022 # ok 1155 # SKIP SVE set SVE get FPSIMD for VL 4608
2886 10:06:57.481128 # ok 1156 # SKIP SVE set FPSIMD get SVE for VL 4608
2887 10:06:57.481226 # ok 1157 Set SVE VL 4624
2888 10:06:57.481524 # ok 1158 # SKIP SVE set SVE get SVE for VL 4624
2889 10:06:57.481623 # ok 1159 # SKIP SVE set SVE get FPSIMD for VL 4624
2890 10:06:57.481737 # ok 1160 # SKIP SVE set FPSIMD get SVE for VL 4624
2891 10:06:57.481827 # ok 1161 Set SVE VL 4640
2892 10:06:57.481929 # ok 1162 # SKIP SVE set SVE get SVE for VL 4640
2893 10:06:57.482017 # ok 1163 # SKIP SVE set SVE get FPSIMD for VL 4640
2894 10:06:57.482120 # ok 1164 # SKIP SVE set FPSIMD get SVE for VL 4640
2895 10:06:57.482209 # ok 1165 Set SVE VL 4656
2896 10:06:57.482296 # ok 1166 # SKIP SVE set SVE get SVE for VL 4656
2897 10:06:57.482399 # ok 1167 # SKIP SVE set SVE get FPSIMD for VL 4656
2898 10:06:57.482493 # ok 1168 # SKIP SVE set FPSIMD get SVE for VL 4656
2899 10:06:57.482585 # ok 1169 Set SVE VL 4672
2900 10:06:57.482693 # ok 1170 # SKIP SVE set SVE get SVE for VL 4672
2901 10:06:57.482786 # ok 1171 # SKIP SVE set SVE get FPSIMD for VL 4672
2902 10:06:57.482899 # ok 1172 # SKIP SVE set FPSIMD get SVE for VL 4672
2903 10:06:57.482992 # ok 1173 Set SVE VL 4688
2904 10:06:57.483083 # ok 1174 # SKIP SVE set SVE get SVE for VL 4688
2905 10:06:57.483190 # ok 1175 # SKIP SVE set SVE get FPSIMD for VL 4688
2906 10:06:57.483283 # ok 1176 # SKIP SVE set FPSIMD get SVE for VL 4688
2907 10:06:57.483374 # ok 1177 Set SVE VL 4704
2908 10:06:57.483479 # ok 1178 # SKIP SVE set SVE get SVE for VL 4704
2909 10:06:57.483573 # ok 1179 # SKIP SVE set SVE get FPSIMD for VL 4704
2910 10:06:57.483681 # ok 1180 # SKIP SVE set FPSIMD get SVE for VL 4704
2911 10:06:57.483777 # ok 1181 Set SVE VL 4720
2912 10:06:57.483888 # ok 1182 # SKIP SVE set SVE get SVE for VL 4720
2913 10:06:57.483996 # ok 1183 # SKIP SVE set SVE get FPSIMD for VL 4720
2914 10:06:57.484113 # ok 1184 # SKIP SVE set FPSIMD get SVE for VL 4720
2915 10:06:57.484222 # ok 1185 Set SVE VL 4736
2916 10:06:57.484330 # ok 1186 # SKIP SVE set SVE get SVE for VL 4736
2917 10:06:57.484439 # ok 1187 # SKIP SVE set SVE get FPSIMD for VL 4736
2918 10:06:57.484547 # ok 1188 # SKIP SVE set FPSIMD get SVE for VL 4736
2919 10:06:57.484655 # ok 1189 Set SVE VL 4752
2920 10:06:57.484762 # ok 1190 # SKIP SVE set SVE get SVE for VL 4752
2921 10:06:57.484873 # ok 1191 # SKIP SVE set SVE get FPSIMD for VL 4752
2922 10:06:57.484983 # ok 1192 # SKIP SVE set FPSIMD get SVE for VL 4752
2923 10:06:57.485091 # ok 1193 Set SVE VL 4768
2924 10:06:57.485401 # ok 1194 # SKIP SVE set SVE get SVE for VL 4768
2925 10:06:57.485502 # ok 1195 # SKIP SVE set SVE get FPSIMD for VL 4768
2926 10:06:57.485600 # ok 1196 # SKIP SVE set FPSIMD get SVE for VL 4768
2927 10:06:57.485694 # ok 1197 Set SVE VL 4784
2928 10:06:57.485788 # ok 1198 # SKIP SVE set SVE get SVE for VL 4784
2929 10:06:57.486083 # ok 1199 # SKIP SVE set SVE get FPSIMD for VL 4784
2930 10:06:57.486182 # ok 1200 # SKIP SVE set FPSIMD get SVE for VL 4784
2931 10:06:57.486266 # ok 1201 Set SVE VL 4800
2932 10:06:57.486362 # ok 1202 # SKIP SVE set SVE get SVE for VL 4800
2933 10:06:57.486692 # ok 1203 # SKIP SVE set SVE get FPSIMD for VL 4800
2934 10:06:57.486791 # ok 1204 # SKIP SVE set FPSIMD get SVE for VL 4800
2935 10:06:57.486877 # ok 1205 Set SVE VL 4816
2936 10:06:57.486975 # ok 1206 # SKIP SVE set SVE get SVE for VL 4816
2937 10:06:57.487077 # ok 1207 # SKIP SVE set SVE get FPSIMD for VL 4816
2938 10:06:57.487177 # ok 1208 # SKIP SVE set FPSIMD get SVE for VL 4816
2939 10:06:57.487262 # ok 1209 Set SVE VL 4832
2940 10:06:57.487358 # ok 1210 # SKIP SVE set SVE get SVE for VL 4832
2941 10:06:57.487670 # ok 1211 # SKIP SVE set SVE get FPSIMD for VL 4832
2942 10:06:57.487763 # ok 1212 # SKIP SVE set FPSIMD get SVE for VL 4832
2943 10:06:57.487861 # ok 1213 Set SVE VL 4848
2944 10:06:57.488185 # ok 1214 # SKIP SVE set SVE get SVE for VL 4848
2945 10:06:57.488286 # ok 1215 # SKIP SVE set SVE get FPSIMD for VL 4848
2946 10:06:57.488386 # ok 1216 # SKIP SVE set FPSIMD get SVE for VL 4848
2947 10:06:57.488468 # ok 1217 Set SVE VL 4864
2948 10:06:57.488556 # ok 1218 # SKIP SVE set SVE get SVE for VL 4864
2949 10:06:57.488634 # ok 1219 # SKIP SVE set SVE get FPSIMD for VL 4864
2950 10:06:57.488727 # ok 1220 # SKIP SVE set FPSIMD get SVE for VL 4864
2951 10:06:57.488816 # ok 1221 Set SVE VL 4880
2952 10:06:57.489074 # ok 1222 # SKIP SVE set SVE get SVE for VL 4880
2953 10:06:57.489152 # ok 1223 # SKIP SVE set SVE get FPSIMD for VL 4880
2954 10:06:57.505512 # ok 1224 # SKIP SVE set FPSIMD get SVE for VL 4880
2955 10:06:57.505749 # ok 1225 Set SVE VL 4896
2956 10:06:57.505824 # ok 1226 # SKIP SVE set SVE get SVE for VL 4896
2957 10:06:57.505925 # ok 1227 # SKIP SVE set SVE get FPSIMD for VL 4896
2958 10:06:57.506001 # ok 1228 # SKIP SVE set FPSIMD get SVE for VL 4896
2959 10:06:57.506076 # ok 1229 Set SVE VL 4912
2960 10:06:57.506158 # ok 1230 # SKIP SVE set SVE get SVE for VL 4912
2961 10:06:57.506234 # ok 1231 # SKIP SVE set SVE get FPSIMD for VL 4912
2962 10:06:57.506296 # ok 1232 # SKIP SVE set FPSIMD get SVE for VL 4912
2963 10:06:57.506371 # ok 1233 Set SVE VL 4928
2964 10:06:57.506437 # ok 1234 # SKIP SVE set SVE get SVE for VL 4928
2965 10:06:57.506518 # ok 1235 # SKIP SVE set SVE get FPSIMD for VL 4928
2966 10:06:57.506610 # ok 1236 # SKIP SVE set FPSIMD get SVE for VL 4928
2967 10:06:57.506704 # ok 1237 Set SVE VL 4944
2968 10:06:57.506800 # ok 1238 # SKIP SVE set SVE get SVE for VL 4944
2969 10:06:57.506886 # ok 1239 # SKIP SVE set SVE get FPSIMD for VL 4944
2970 10:06:57.507212 # ok 1240 # SKIP SVE set FPSIMD get SVE for VL 4944
2971 10:06:57.507320 # ok 1241 Set SVE VL 4960
2972 10:06:57.507410 # ok 1242 # SKIP SVE set SVE get SVE for VL 4960
2973 10:06:57.507514 # ok 1243 # SKIP SVE set SVE get FPSIMD for VL 4960
2974 10:06:57.509256 # ok 1244 # SKIP SVE set FPSIMD get SVE for VL 4960
2975 10:06:57.509385 # ok 1245 Set SVE VL 4976
2976 10:06:57.510093 # ok 1246 # SKIP SVE set SVE get SVE for VL 4976
2977 10:06:57.510397 # ok 1247 # SKIP SVE set SVE get FPSIMD for VL 4976
2978 10:06:57.510511 # ok 1248 # SKIP SVE set FPSIMD get SVE for VL 4976
2979 10:06:57.510595 # ok 1249 Set SVE VL 4992
2980 10:06:57.510682 # ok 1250 # SKIP SVE set SVE get SVE for VL 4992
2981 10:06:57.510780 # ok 1251 # SKIP SVE set SVE get FPSIMD for VL 4992
2982 10:06:57.511073 # ok 1252 # SKIP SVE set FPSIMD get SVE for VL 4992
2983 10:06:57.511168 # ok 1253 Set SVE VL 5008
2984 10:06:57.511295 # ok 1254 # SKIP SVE set SVE get SVE for VL 5008
2985 10:06:57.511410 # ok 1255 # SKIP SVE set SVE get FPSIMD for VL 5008
2986 10:06:57.511526 # ok 1256 # SKIP SVE set FPSIMD get SVE for VL 5008
2987 10:06:57.511624 # ok 1257 Set SVE VL 5024
2988 10:06:57.513400 # ok 1258 # SKIP SVE set SVE get SVE for VL 5024
2989 10:06:57.513695 # ok 1259 # SKIP SVE set SVE get FPSIMD for VL 5024
2990 10:06:57.513782 # ok 1260 # SKIP SVE set FPSIMD get SVE for VL 5024
2991 10:06:57.513859 # ok 1261 Set SVE VL 5040
2992 10:06:57.513949 # ok 1262 # SKIP SVE set SVE get SVE for VL 5040
2993 10:06:57.514058 # ok 1263 # SKIP SVE set SVE get FPSIMD for VL 5040
2994 10:06:57.514338 # ok 1264 # SKIP SVE set FPSIMD get SVE for VL 5040
2995 10:06:57.514420 # ok 1265 Set SVE VL 5056
2996 10:06:57.514548 # ok 1266 # SKIP SVE set SVE get SVE for VL 5056
2997 10:06:57.514631 # ok 1267 # SKIP SVE set SVE get FPSIMD for VL 5056
2998 10:06:57.514747 # ok 1268 # SKIP SVE set FPSIMD get SVE for VL 5056
2999 10:06:57.514849 # ok 1269 Set SVE VL 5072
3000 10:06:57.514959 # ok 1270 # SKIP SVE set SVE get SVE for VL 5072
3001 10:06:57.515054 # ok 1271 # SKIP SVE set SVE get FPSIMD for VL 5072
3002 10:06:57.515348 # ok 1272 # SKIP SVE set FPSIMD get SVE for VL 5072
3003 10:06:57.515450 # ok 1273 Set SVE VL 5088
3004 10:06:57.515568 # ok 1274 # SKIP SVE set SVE get SVE for VL 5088
3005 10:06:57.515681 # ok 1275 # SKIP SVE set SVE get FPSIMD for VL 5088
3006 10:06:57.515783 # ok 1276 # SKIP SVE set FPSIMD get SVE for VL 5088
3007 10:06:57.516074 # ok 1277 Set SVE VL 5104
3008 10:06:57.516383 # ok 1278 # SKIP SVE set SVE get SVE for VL 5104
3009 10:06:57.516478 # ok 1279 # SKIP SVE set SVE get FPSIMD for VL 5104
3010 10:06:57.516606 # ok 1280 # SKIP SVE set FPSIMD get SVE for VL 5104
3011 10:06:57.516747 # ok 1281 Set SVE VL 5120
3012 10:06:57.516872 # ok 1282 # SKIP SVE set SVE get SVE for VL 5120
3013 10:06:57.516988 # ok 1283 # SKIP SVE set SVE get FPSIMD for VL 5120
3014 10:06:57.517106 # ok 1284 # SKIP SVE set FPSIMD get SVE for VL 5120
3015 10:06:57.517198 # ok 1285 Set SVE VL 5136
3016 10:06:57.517286 # ok 1286 # SKIP SVE set SVE get SVE for VL 5136
3017 10:06:57.517373 # ok 1287 # SKIP SVE set SVE get FPSIMD for VL 5136
3018 10:06:57.517676 # ok 1288 # SKIP SVE set FPSIMD get SVE for VL 5136
3019 10:06:57.517771 # ok 1289 Set SVE VL 5152
3020 10:06:57.517848 # ok 1290 # SKIP SVE set SVE get SVE for VL 5152
3021 10:06:57.517938 # ok 1291 # SKIP SVE set SVE get FPSIMD for VL 5152
3022 10:06:57.518024 # ok 1292 # SKIP SVE set FPSIMD get SVE for VL 5152
3023 10:06:57.518095 # ok 1293 Set SVE VL 5168
3024 10:06:57.518182 # ok 1294 # SKIP SVE set SVE get SVE for VL 5168
3025 10:06:57.518446 # ok 1295 # SKIP SVE set SVE get FPSIMD for VL 5168
3026 10:06:57.518516 # ok 1296 # SKIP SVE set FPSIMD get SVE for VL 5168
3027 10:06:57.518604 # ok 1297 Set SVE VL 5184
3028 10:06:57.518689 # ok 1298 # SKIP SVE set SVE get SVE for VL 5184
3029 10:06:57.518950 # ok 1299 # SKIP SVE set SVE get FPSIMD for VL 5184
3030 10:06:57.519020 # ok 1300 # SKIP SVE set FPSIMD get SVE for VL 5184
3031 10:06:57.519108 # ok 1301 Set SVE VL 5200
3032 10:06:57.519192 # ok 1302 # SKIP SVE set SVE get SVE for VL 5200
3033 10:06:57.519276 # ok 1303 # SKIP SVE set SVE get FPSIMD for VL 5200
3034 10:06:57.519545 # ok 1304 # SKIP SVE set FPSIMD get SVE for VL 5200
3035 10:06:57.519627 # ok 1305 Set SVE VL 5216
3036 10:06:57.519732 # ok 1306 # SKIP SVE set SVE get SVE for VL 5216
3037 10:06:57.520101 # ok 1307 # SKIP SVE set SVE get FPSIMD for VL 5216
3038 10:06:57.520354 # ok 1308 # SKIP SVE set FPSIMD get SVE for VL 5216
3039 10:06:57.520453 # ok 1309 Set SVE VL 5232
3040 10:06:57.520568 # ok 1310 # SKIP SVE set SVE get SVE for VL 5232
3041 10:06:57.520675 # ok 1311 # SKIP SVE set SVE get FPSIMD for VL 5232
3042 10:06:57.520784 # ok 1312 # SKIP SVE set FPSIMD get SVE for VL 5232
3043 10:06:57.520894 # ok 1313 Set SVE VL 5248
3044 10:06:57.521000 # ok 1314 # SKIP SVE set SVE get SVE for VL 5248
3045 10:06:57.521092 # ok 1315 # SKIP SVE set SVE get FPSIMD for VL 5248
3046 10:06:57.521384 # ok 1316 # SKIP SVE set FPSIMD get SVE for VL 5248
3047 10:06:57.521485 # ok 1317 Set SVE VL 5264
3048 10:06:57.521578 # ok 1318 # SKIP SVE set SVE get SVE for VL 5264
3049 10:06:57.521671 # ok 1319 # SKIP SVE set SVE get FPSIMD for VL 5264
3050 10:06:57.521784 # ok 1320 # SKIP SVE set FPSIMD get SVE for VL 5264
3051 10:06:57.521906 # ok 1321 Set SVE VL 5280
3052 10:06:57.522019 # ok 1322 # SKIP SVE set SVE get SVE for VL 5280
3053 10:06:57.527267 # ok 1323 # SKIP SVE set SVE get FPSIMD for VL 5280
3054 10:06:57.527491 # ok 1324 # SKIP SVE set FPSIMD get SVE for VL 5280
3055 10:06:57.527558 # ok 1325 Set SVE VL 5296
3056 10:06:57.527623 # ok 1326 # SKIP SVE set SVE get SVE for VL 5296
3057 10:06:57.527685 # ok 1327 # SKIP SVE set SVE get FPSIMD for VL 5296
3058 10:06:57.527744 # ok 1328 # SKIP SVE set FPSIMD get SVE for VL 5296
3059 10:06:57.527805 # ok 1329 Set SVE VL 5312
3060 10:06:57.527865 # ok 1330 # SKIP SVE set SVE get SVE for VL 5312
3061 10:06:57.527925 # ok 1331 # SKIP SVE set SVE get FPSIMD for VL 5312
3062 10:06:57.527985 # ok 1332 # SKIP SVE set FPSIMD get SVE for VL 5312
3063 10:06:57.528045 # ok 1333 Set SVE VL 5328
3064 10:06:57.528105 # ok 1334 # SKIP SVE set SVE get SVE for VL 5328
3065 10:06:57.528165 # ok 1335 # SKIP SVE set SVE get FPSIMD for VL 5328
3066 10:06:57.528224 # ok 1336 # SKIP SVE set FPSIMD get SVE for VL 5328
3067 10:06:57.528285 # ok 1337 Set SVE VL 5344
3068 10:06:57.528344 # ok 1338 # SKIP SVE set SVE get SVE for VL 5344
3069 10:06:57.528404 # ok 1339 # SKIP SVE set SVE get FPSIMD for VL 5344
3070 10:06:57.528464 # ok 1340 # SKIP SVE set FPSIMD get SVE for VL 5344
3071 10:06:57.528524 # ok 1341 Set SVE VL 5360
3072 10:06:57.528583 # ok 1342 # SKIP SVE set SVE get SVE for VL 5360
3073 10:06:57.528643 # ok 1343 # SKIP SVE set SVE get FPSIMD for VL 5360
3074 10:06:57.528703 # ok 1344 # SKIP SVE set FPSIMD get SVE for VL 5360
3075 10:06:57.528762 # ok 1345 Set SVE VL 5376
3076 10:06:57.528822 # ok 1346 # SKIP SVE set SVE get SVE for VL 5376
3077 10:06:57.528881 # ok 1347 # SKIP SVE set SVE get FPSIMD for VL 5376
3078 10:06:57.528941 # ok 1348 # SKIP SVE set FPSIMD get SVE for VL 5376
3079 10:06:57.529005 # ok 1349 Set SVE VL 5392
3080 10:06:57.529075 # ok 1350 # SKIP SVE set SVE get SVE for VL 5392
3081 10:06:57.529137 # ok 1351 # SKIP SVE set SVE get FPSIMD for VL 5392
3082 10:06:57.529203 # ok 1352 # SKIP SVE set FPSIMD get SVE for VL 5392
3083 10:06:57.529273 # ok 1353 Set SVE VL 5408
3084 10:06:57.529348 # ok 1354 # SKIP SVE set SVE get SVE for VL 5408
3085 10:06:57.529429 # ok 1355 # SKIP SVE set SVE get FPSIMD for VL 5408
3086 10:06:57.529512 # ok 1356 # SKIP SVE set FPSIMD get SVE for VL 5408
3087 10:06:57.529594 # ok 1357 Set SVE VL 5424
3088 10:06:57.529691 # ok 1358 # SKIP SVE set SVE get SVE for VL 5424
3089 10:06:57.529799 # ok 1359 # SKIP SVE set SVE get FPSIMD for VL 5424
3090 10:06:57.529883 # ok 1360 # SKIP SVE set FPSIMD get SVE for VL 5424
3091 10:06:57.530188 # ok 1361 Set SVE VL 5440
3092 10:06:57.530283 # ok 1362 # SKIP SVE set SVE get SVE for VL 5440
3093 10:06:57.530364 # ok 1363 # SKIP SVE set SVE get FPSIMD for VL 5440
3094 10:06:57.530431 # ok 1364 # SKIP SVE set FPSIMD get SVE for VL 5440
3095 10:06:57.530505 # ok 1365 Set SVE VL 5456
3096 10:06:57.530574 # ok 1366 # SKIP SVE set SVE get SVE for VL 5456
3097 10:06:57.530647 # ok 1367 # SKIP SVE set SVE get FPSIMD for VL 5456
3098 10:06:57.530709 # ok 1368 # SKIP SVE set FPSIMD get SVE for VL 5456
3099 10:06:57.530785 # ok 1369 Set SVE VL 5472
3100 10:06:57.530856 # ok 1370 # SKIP SVE set SVE get SVE for VL 5472
3101 10:06:57.530928 # ok 1371 # SKIP SVE set SVE get FPSIMD for VL 5472
3102 10:06:57.530998 # ok 1372 # SKIP SVE set FPSIMD get SVE for VL 5472
3103 10:06:57.531061 # ok 1373 Set SVE VL 5488
3104 10:06:57.531134 # ok 1374 # SKIP SVE set SVE get SVE for VL 5488
3105 10:06:57.531200 # ok 1375 # SKIP SVE set SVE get FPSIMD for VL 5488
3106 10:06:57.531264 # ok 1376 # SKIP SVE set FPSIMD get SVE for VL 5488
3107 10:06:57.531331 # ok 1377 Set SVE VL 5504
3108 10:06:57.531400 # ok 1378 # SKIP SVE set SVE get SVE for VL 5504
3109 10:06:57.531460 # ok 1379 # SKIP SVE set SVE get FPSIMD for VL 5504
3110 10:06:57.531717 # ok 1380 # SKIP SVE set FPSIMD get SVE for VL 5504
3111 10:06:57.531798 # ok 1381 Set SVE VL 5520
3112 10:06:57.531865 # ok 1382 # SKIP SVE set SVE get SVE for VL 5520
3113 10:06:57.531955 # ok 1383 # SKIP SVE set SVE get FPSIMD for VL 5520
3114 10:06:57.532036 # ok 1384 # SKIP SVE set FPSIMD get SVE for VL 5520
3115 10:06:57.532110 # ok 1385 Set SVE VL 5536
3116 10:06:57.532183 # ok 1386 # SKIP SVE set SVE get SVE for VL 5536
3117 10:06:57.532277 # ok 1387 # SKIP SVE set SVE get FPSIMD for VL 5536
3118 10:06:57.532369 # ok 1388 # SKIP SVE set FPSIMD get SVE for VL 5536
3119 10:06:57.532446 # ok 1389 Set SVE VL 5552
3120 10:06:57.532515 # ok 1390 # SKIP SVE set SVE get SVE for VL 5552
3121 10:06:57.532611 # ok 1391 # SKIP SVE set SVE get FPSIMD for VL 5552
3122 10:06:57.532690 # ok 1392 # SKIP SVE set FPSIMD get SVE for VL 5552
3123 10:06:57.532772 # ok 1393 Set SVE VL 5568
3124 10:06:57.532850 # ok 1394 # SKIP SVE set SVE get SVE for VL 5568
3125 10:06:57.532941 # ok 1395 # SKIP SVE set SVE get FPSIMD for VL 5568
3126 10:06:57.533015 # ok 1396 # SKIP SVE set FPSIMD get SVE for VL 5568
3127 10:06:57.533092 # ok 1397 Set SVE VL 5584
3128 10:06:57.533177 # ok 1398 # SKIP SVE set SVE get SVE for VL 5584
3129 10:06:57.533242 # ok 1399 # SKIP SVE set SVE get FPSIMD for VL 5584
3130 10:06:57.533321 # ok 1400 # SKIP SVE set FPSIMD get SVE for VL 5584
3131 10:06:57.533415 # ok 1401 Set SVE VL 5600
3132 10:06:57.533492 # ok 1402 # SKIP SVE set SVE get SVE for VL 5600
3133 10:06:57.533763 # ok 1403 # SKIP SVE set SVE get FPSIMD for VL 5600
3134 10:06:57.533869 # ok 1404 # SKIP SVE set FPSIMD get SVE for VL 5600
3135 10:06:57.533979 # ok 1405 Set SVE VL 5616
3136 10:06:57.534092 # ok 1406 # SKIP SVE set SVE get SVE for VL 5616
3137 10:06:57.544997 # ok 1407 # SKIP SVE set SVE get FPSIMD for VL 5616
3138 10:06:57.545440 # ok 1408 # SKIP SVE set FPSIMD get SVE for VL 5616
3139 10:06:57.545547 # ok 1409 Set SVE VL 5632
3140 10:06:57.545633 # ok 1410 # SKIP SVE set SVE get SVE for VL 5632
3141 10:06:57.545754 # ok 1411 # SKIP SVE set SVE get FPSIMD for VL 5632
3142 10:06:57.545850 # ok 1412 # SKIP SVE set FPSIMD get SVE for VL 5632
3143 10:06:57.545936 # ok 1413 Set SVE VL 5648
3144 10:06:57.546027 # ok 1414 # SKIP SVE set SVE get SVE for VL 5648
3145 10:06:57.546138 # ok 1415 # SKIP SVE set SVE get FPSIMD for VL 5648
3146 10:06:57.546222 # ok 1416 # SKIP SVE set FPSIMD get SVE for VL 5648
3147 10:06:57.546303 # ok 1417 Set SVE VL 5664
3148 10:06:57.546396 # ok 1418 # SKIP SVE set SVE get SVE for VL 5664
3149 10:06:57.546508 # ok 1419 # SKIP SVE set SVE get FPSIMD for VL 5664
3150 10:06:57.546598 # ok 1420 # SKIP SVE set FPSIMD get SVE for VL 5664
3151 10:06:57.546688 # ok 1421 Set SVE VL 5680
3152 10:06:57.546772 # ok 1422 # SKIP SVE set SVE get SVE for VL 5680
3153 10:06:57.546872 # ok 1423 # SKIP SVE set SVE get FPSIMD for VL 5680
3154 10:06:57.546979 # ok 1424 # SKIP SVE set FPSIMD get SVE for VL 5680
3155 10:06:57.547069 # ok 1425 Set SVE VL 5696
3156 10:06:57.547176 # ok 1426 # SKIP SVE set SVE get SVE for VL 5696
3157 10:06:57.547261 # ok 1427 # SKIP SVE set SVE get FPSIMD for VL 5696
3158 10:06:57.547359 # ok 1428 # SKIP SVE set FPSIMD get SVE for VL 5696
3159 10:06:57.547456 # ok 1429 Set SVE VL 5712
3160 10:06:57.547559 # ok 1430 # SKIP SVE set SVE get SVE for VL 5712
3161 10:06:57.547641 # ok 1431 # SKIP SVE set SVE get FPSIMD for VL 5712
3162 10:06:57.549089 # ok 1432 # SKIP SVE set FPSIMD get SVE for VL 5712
3163 10:06:57.549397 # ok 1433 Set SVE VL 5728
3164 10:06:57.549493 # ok 1434 # SKIP SVE set SVE get SVE for VL 5728
3165 10:06:57.549575 # ok 1435 # SKIP SVE set SVE get FPSIMD for VL 5728
3166 10:06:57.549669 # ok 1436 # SKIP SVE set FPSIMD get SVE for VL 5728
3167 10:06:57.549756 # ok 1437 Set SVE VL 5744
3168 10:06:57.549854 # ok 1438 # SKIP SVE set SVE get SVE for VL 5744
3169 10:06:57.549948 # ok 1439 # SKIP SVE set SVE get FPSIMD for VL 5744
3170 10:06:57.550074 # ok 1440 # SKIP SVE set FPSIMD get SVE for VL 5744
3171 10:06:57.550173 # ok 1441 Set SVE VL 5760
3172 10:06:57.550270 # ok 1442 # SKIP SVE set SVE get SVE for VL 5760
3173 10:06:57.550347 # ok 1443 # SKIP SVE set SVE get FPSIMD for VL 5760
3174 10:06:57.550444 # ok 1444 # SKIP SVE set FPSIMD get SVE for VL 5760
3175 10:06:57.550545 # ok 1445 Set SVE VL 5776
3176 10:06:57.550627 # ok 1446 # SKIP SVE set SVE get SVE for VL 5776
3177 10:06:57.550945 # ok 1447 # SKIP SVE set SVE get FPSIMD for VL 5776
3178 10:06:57.551044 # ok 1448 # SKIP SVE set FPSIMD get SVE for VL 5776
3179 10:06:57.551152 # ok 1449 Set SVE VL 5792
3180 10:06:57.551277 # ok 1450 # SKIP SVE set SVE get SVE for VL 5792
3181 10:06:57.551352 # ok 1451 # SKIP SVE set SVE get FPSIMD for VL 5792
3182 10:06:57.551465 # ok 1452 # SKIP SVE set FPSIMD get SVE for VL 5792
3183 10:06:57.551564 # ok 1453 Set SVE VL 5808
3184 10:06:57.551683 # ok 1454 # SKIP SVE set SVE get SVE for VL 5808
3185 10:06:57.551766 # ok 1455 # SKIP SVE set SVE get FPSIMD for VL 5808
3186 10:06:57.578730 # ok 1456 # SKIP SVE set FPSIMD get SVE for VL 5808
3187 10:06:57.578958 # ok 1457 Set SVE VL 5824
3188 10:06:57.579295 # ok 1458 # SKIP SVE set SVE get SVE for VL 5824
3189 10:06:57.579492 # ok 1459 # SKIP SVE set SVE get FPSIMD for VL 5824
3190 10:06:57.579662 # ok 1460 # SKIP SVE set FPSIMD get SVE for VL 5824
3191 10:06:57.579802 # ok 1461 Set SVE VL 5840
3192 10:06:57.579917 # ok 1462 # SKIP SVE set SVE get SVE for VL 5840
3193 10:06:57.580053 # ok 1463 # SKIP SVE set SVE get FPSIMD for VL 5840
3194 10:06:57.580169 # ok 1464 # SKIP SVE set FPSIMD get SVE for VL 5840
3195 10:06:57.580281 # ok 1465 Set SVE VL 5856
3196 10:06:57.580391 # ok 1466 # SKIP SVE set SVE get SVE for VL 5856
3197 10:06:57.580501 # ok 1467 # SKIP SVE set SVE get FPSIMD for VL 5856
3198 10:06:57.582754 # ok 1468 # SKIP SVE set FPSIMD get SVE for VL 5856
3199 10:06:57.582892 # ok 1469 Set SVE VL 5872
3200 10:06:57.583179 # ok 1470 # SKIP SVE set SVE get SVE for VL 5872
3201 10:06:57.583278 # ok 1471 # SKIP SVE set SVE get FPSIMD for VL 5872
3202 10:06:57.583361 # ok 1472 # SKIP SVE set FPSIMD get SVE for VL 5872
3203 10:06:57.583447 # ok 1473 Set SVE VL 5888
3204 10:06:57.583510 # ok 1474 # SKIP SVE set SVE get SVE for VL 5888
3205 10:06:57.583571 # ok 1475 # SKIP SVE set SVE get FPSIMD for VL 5888
3206 10:06:57.583681 # ok 1476 # SKIP SVE set FPSIMD get SVE for VL 5888
3207 10:06:57.583754 # ok 1477 Set SVE VL 5904
3208 10:06:57.583815 # ok 1478 # SKIP SVE set SVE get SVE for VL 5904
3209 10:06:57.584988 # ok 1479 # SKIP SVE set SVE get FPSIMD for VL 5904
3210 10:06:57.585265 # ok 1480 # SKIP SVE set FPSIMD get SVE for VL 5904
3211 10:06:57.585353 # ok 1481 Set SVE VL 5920
3212 10:06:57.585449 # ok 1482 # SKIP SVE set SVE get SVE for VL 5920
3213 10:06:57.585552 # ok 1483 # SKIP SVE set SVE get FPSIMD for VL 5920
3214 10:06:57.585624 # ok 1484 # SKIP SVE set FPSIMD get SVE for VL 5920
3215 10:06:57.585706 # ok 1485 Set SVE VL 5936
3216 10:06:57.585796 # ok 1486 # SKIP SVE set SVE get SVE for VL 5936
3217 10:06:57.585866 # ok 1487 # SKIP SVE set SVE get FPSIMD for VL 5936
3218 10:06:57.585955 # ok 1488 # SKIP SVE set FPSIMD get SVE for VL 5936
3219 10:06:57.586025 # ok 1489 Set SVE VL 5952
3220 10:06:57.586097 # ok 1490 # SKIP SVE set SVE get SVE for VL 5952
3221 10:06:57.586186 # ok 1491 # SKIP SVE set SVE get FPSIMD for VL 5952
3222 10:06:57.586255 # ok 1492 # SKIP SVE set FPSIMD get SVE for VL 5952
3223 10:06:57.586352 # ok 1493 Set SVE VL 5968
3224 10:06:57.586440 # ok 1494 # SKIP SVE set SVE get SVE for VL 5968
3225 10:06:57.586533 # ok 1495 # SKIP SVE set SVE get FPSIMD for VL 5968
3226 10:06:57.586636 # ok 1496 # SKIP SVE set FPSIMD get SVE for VL 5968
3227 10:06:57.586715 # ok 1497 Set SVE VL 5984
3228 10:06:57.586810 # ok 1498 # SKIP SVE set SVE get SVE for VL 5984
3229 10:06:57.586901 # ok 1499 # SKIP SVE set SVE get FPSIMD for VL 5984
3230 10:06:57.587030 # ok 1500 # SKIP SVE set FPSIMD get SVE for VL 5984
3231 10:06:57.587154 # ok 1501 Set SVE VL 6000
3232 10:06:57.587263 # ok 1502 # SKIP SVE set SVE get SVE for VL 6000
3233 10:06:57.587369 # ok 1503 # SKIP SVE set SVE get FPSIMD for VL 6000
3234 10:06:57.587675 # ok 1504 # SKIP SVE set FPSIMD get SVE for VL 6000
3235 10:06:57.587774 # ok 1505 Set SVE VL 6016
3236 10:06:57.588861 # ok 1506 # SKIP SVE set SVE get SVE for VL 6016
3237 10:06:57.589162 # ok 1507 # SKIP SVE set SVE get FPSIMD for VL 6016
3238 10:06:57.589253 # ok 1508 # SKIP SVE set FPSIMD get SVE for VL 6016
3239 10:06:57.589349 # ok 1509 Set SVE VL 6032
3240 10:06:57.589418 # ok 1510 # SKIP SVE set SVE get SVE for VL 6032
3241 10:06:57.589507 # ok 1511 # SKIP SVE set SVE get FPSIMD for VL 6032
3242 10:06:57.589591 # ok 1512 # SKIP SVE set FPSIMD get SVE for VL 6032
3243 10:06:57.589689 # ok 1513 Set SVE VL 6048
3244 10:06:57.589775 # ok 1514 # SKIP SVE set SVE get SVE for VL 6048
3245 10:06:57.589859 # ok 1515 # SKIP SVE set SVE get FPSIMD for VL 6048
3246 10:06:57.590131 # ok 1516 # SKIP SVE set FPSIMD get SVE for VL 6048
3247 10:06:57.590212 # ok 1517 Set SVE VL 6064
3248 10:06:57.590308 # ok 1518 # SKIP SVE set SVE get SVE for VL 6064
3249 10:06:57.590379 # ok 1519 # SKIP SVE set SVE get FPSIMD for VL 6064
3250 10:06:57.590467 # ok 1520 # SKIP SVE set FPSIMD get SVE for VL 6064
3251 10:06:57.590550 # ok 1521 Set SVE VL 6080
3252 10:06:57.590622 # ok 1522 # SKIP SVE set SVE get SVE for VL 6080
3253 10:06:57.590730 # ok 1523 # SKIP SVE set SVE get FPSIMD for VL 6080
3254 10:06:57.590823 # ok 1524 # SKIP SVE set FPSIMD get SVE for VL 6080
3255 10:06:57.590913 # ok 1525 Set SVE VL 6096
3256 10:06:57.591167 # ok 1526 # SKIP SVE set SVE get SVE for VL 6096
3257 10:06:57.591235 # ok 1527 # SKIP SVE set SVE get FPSIMD for VL 6096
3258 10:06:57.591315 # ok 1528 # SKIP SVE set FPSIMD get SVE for VL 6096
3259 10:06:57.591399 # ok 1529 Set SVE VL 6112
3260 10:06:57.591485 # ok 1530 # SKIP SVE set SVE get SVE for VL 6112
3261 10:06:57.591570 # ok 1531 # SKIP SVE set SVE get FPSIMD for VL 6112
3262 10:06:57.591656 # ok 1532 # SKIP SVE set FPSIMD get SVE for VL 6112
3263 10:06:57.592701 # ok 1533 Set SVE VL 6128
3264 10:06:57.592994 # ok 1534 # SKIP SVE set SVE get SVE for VL 6128
3265 10:06:57.593083 # ok 1535 # SKIP SVE set SVE get FPSIMD for VL 6128
3266 10:06:57.593190 # ok 1536 # SKIP SVE set FPSIMD get SVE for VL 6128
3267 10:06:57.593275 # ok 1537 Set SVE VL 6144
3268 10:06:57.593380 # ok 1538 # SKIP SVE set SVE get SVE for VL 6144
3269 10:06:57.593468 # ok 1539 # SKIP SVE set SVE get FPSIMD for VL 6144
3270 10:06:57.593573 # ok 1540 # SKIP SVE set FPSIMD get SVE for VL 6144
3271 10:06:57.593644 # ok 1541 Set SVE VL 6160
3272 10:06:57.593745 # ok 1542 # SKIP SVE set SVE get SVE for VL 6160
3273 10:06:57.593829 # ok 1543 # SKIP SVE set SVE get FPSIMD for VL 6160
3274 10:06:57.593914 # ok 1544 # SKIP SVE set FPSIMD get SVE for VL 6160
3275 10:06:57.593998 # ok 1545 Set SVE VL 6176
3276 10:06:57.594082 # ok 1546 # SKIP SVE set SVE get SVE for VL 6176
3277 10:06:57.594167 # ok 1547 # SKIP SVE set SVE get FPSIMD for VL 6176
3278 10:06:57.594439 # ok 1548 # SKIP SVE set FPSIMD get SVE for VL 6176
3279 10:06:57.594520 # ok 1549 Set SVE VL 6192
3280 10:06:57.594595 # ok 1550 # SKIP SVE set SVE get SVE for VL 6192
3281 10:06:57.594683 # ok 1551 # SKIP SVE set SVE get FPSIMD for VL 6192
3282 10:06:57.594763 # ok 1552 # SKIP SVE set FPSIMD get SVE for VL 6192
3283 10:06:57.594869 # ok 1553 Set SVE VL 6208
3284 10:06:57.594944 # ok 1554 # SKIP SVE set SVE get SVE for VL 6208
3285 10:06:57.595025 # ok 1555 # SKIP SVE set SVE get FPSIMD for VL 6208
3286 10:06:57.595089 # ok 1556 # SKIP SVE set FPSIMD get SVE for VL 6208
3287 10:06:57.595172 # ok 1557 Set SVE VL 6224
3288 10:06:57.595264 # ok 1558 # SKIP SVE set SVE get SVE for VL 6224
3289 10:06:57.595361 # ok 1559 # SKIP SVE set SVE get FPSIMD for VL 6224
3290 10:06:57.595450 # ok 1560 # SKIP SVE set FPSIMD get SVE for VL 6224
3291 10:06:57.595542 # ok 1561 Set SVE VL 6240
3292 10:06:57.595634 # ok 1562 # SKIP SVE set SVE get SVE for VL 6240
3293 10:06:57.596579 # ok 1563 # SKIP SVE set SVE get FPSIMD for VL 6240
3294 10:06:57.596840 # ok 1564 # SKIP SVE set FPSIMD get SVE for VL 6240
3295 10:06:57.596908 # ok 1565 Set SVE VL 6256
3296 10:06:57.596968 # ok 1566 # SKIP SVE set SVE get SVE for VL 6256
3297 10:06:57.597038 # ok 1567 # SKIP SVE set SVE get FPSIMD for VL 6256
3298 10:06:57.597106 # ok 1568 # SKIP SVE set FPSIMD get SVE for VL 6256
3299 10:06:57.597214 # ok 1569 Set SVE VL 6272
3300 10:06:57.597287 # ok 1570 # SKIP SVE set SVE get SVE for VL 6272
3301 10:06:57.597376 # ok 1571 # SKIP SVE set SVE get FPSIMD for VL 6272
3302 10:06:57.597460 # ok 1572 # SKIP SVE set FPSIMD get SVE for VL 6272
3303 10:06:57.597544 # ok 1573 Set SVE VL 6288
3304 10:06:57.597629 # ok 1574 # SKIP SVE set SVE get SVE for VL 6288
3305 10:06:57.597734 # ok 1575 # SKIP SVE set SVE get FPSIMD for VL 6288
3306 10:06:57.598015 # ok 1576 # SKIP SVE set FPSIMD get SVE for VL 6288
3307 10:06:57.598123 # ok 1577 Set SVE VL 6304
3308 10:06:57.598202 # ok 1578 # SKIP SVE set SVE get SVE for VL 6304
3309 10:06:57.598292 # ok 1579 # SKIP SVE set SVE get FPSIMD for VL 6304
3310 10:06:57.598375 # ok 1580 # SKIP SVE set FPSIMD get SVE for VL 6304
3311 10:06:57.598448 # ok 1581 Set SVE VL 6320
3312 10:06:57.598508 # ok 1582 # SKIP SVE set SVE get SVE for VL 6320
3313 10:06:57.598576 # ok 1583 # SKIP SVE set SVE get FPSIMD for VL 6320
3314 10:06:57.598643 # ok 1584 # SKIP SVE set FPSIMD get SVE for VL 6320
3315 10:06:57.598711 # ok 1585 Set SVE VL 6336
3316 10:06:57.598784 # ok 1586 # SKIP SVE set SVE get SVE for VL 6336
3317 10:06:57.598858 # ok 1587 # SKIP SVE set SVE get FPSIMD for VL 6336
3318 10:06:57.599112 # ok 1588 # SKIP SVE set FPSIMD get SVE for VL 6336
3319 10:06:57.599192 # ok 1589 Set SVE VL 6352
3320 10:06:57.602323 # ok 1590 # SKIP SVE set SVE get SVE for VL 6352
3321 10:06:57.602718 # ok 1591 # SKIP SVE set SVE get FPSIMD for VL 6352
3322 10:06:57.602940 # ok 1592 # SKIP SVE set FPSIMD get SVE for VL 6352
3323 10:06:57.603151 # ok 1593 Set SVE VL 6368
3324 10:06:57.603362 # ok 1594 # SKIP SVE set SVE get SVE for VL 6368
3325 10:06:57.603536 # ok 1595 # SKIP SVE set SVE get FPSIMD for VL 6368
3326 10:06:57.603735 # ok 1596 # SKIP SVE set FPSIMD get SVE for VL 6368
3327 10:06:57.603883 # ok 1597 Set SVE VL 6384
3328 10:06:57.603997 # ok 1598 # SKIP SVE set SVE get SVE for VL 6384
3329 10:06:57.604132 # ok 1599 # SKIP SVE set SVE get FPSIMD for VL 6384
3330 10:06:57.604250 # ok 1600 # SKIP SVE set FPSIMD get SVE for VL 6384
3331 10:06:57.604350 # ok 1601 Set SVE VL 6400
3332 10:06:57.604435 # ok 1602 # SKIP SVE set SVE get SVE for VL 6400
3333 10:06:57.604591 # ok 1603 # SKIP SVE set SVE get FPSIMD for VL 6400
3334 10:06:57.604728 # ok 1604 # SKIP SVE set FPSIMD get SVE for VL 6400
3335 10:06:57.604860 # ok 1605 Set SVE VL 6416
3336 10:06:57.604964 # ok 1606 # SKIP SVE set SVE get SVE for VL 6416
3337 10:06:57.605098 # ok 1607 # SKIP SVE set SVE get FPSIMD for VL 6416
3338 10:06:57.605210 # ok 1608 # SKIP SVE set FPSIMD get SVE for VL 6416
3339 10:06:57.605326 # ok 1609 Set SVE VL 6432
3340 10:06:57.605468 # ok 1610 # SKIP SVE set SVE get SVE for VL 6432
3341 10:06:57.605593 # ok 1611 # SKIP SVE set SVE get FPSIMD for VL 6432
3342 10:06:57.606100 # ok 1612 # SKIP SVE set FPSIMD get SVE for VL 6432
3343 10:06:57.606190 # ok 1613 Set SVE VL 6448
3344 10:06:57.606288 # ok 1614 # SKIP SVE set SVE get SVE for VL 6448
3345 10:06:57.606373 # ok 1615 # SKIP SVE set SVE get FPSIMD for VL 6448
3346 10:06:57.606468 # ok 1616 # SKIP SVE set FPSIMD get SVE for VL 6448
3347 10:06:57.606566 # ok 1617 Set SVE VL 6464
3348 10:06:57.606663 # ok 1618 # SKIP SVE set SVE get SVE for VL 6464
3349 10:06:57.606754 # ok 1619 # SKIP SVE set SVE get FPSIMD for VL 6464
3350 10:06:57.606856 # ok 1620 # SKIP SVE set FPSIMD get SVE for VL 6464
3351 10:06:57.606932 # ok 1621 Set SVE VL 6480
3352 10:06:57.607006 # ok 1622 # SKIP SVE set SVE get SVE for VL 6480
3353 10:06:57.607101 # ok 1623 # SKIP SVE set SVE get FPSIMD for VL 6480
3354 10:06:57.607187 # ok 1624 # SKIP SVE set FPSIMD get SVE for VL 6480
3355 10:06:57.607253 # ok 1625 Set SVE VL 6496
3356 10:06:57.607335 # ok 1626 # SKIP SVE set SVE get SVE for VL 6496
3357 10:06:57.607409 # ok 1627 # SKIP SVE set SVE get FPSIMD for VL 6496
3358 10:06:57.607486 # ok 1628 # SKIP SVE set FPSIMD get SVE for VL 6496
3359 10:06:57.607577 # ok 1629 Set SVE VL 6512
3360 10:06:57.607682 # ok 1630 # SKIP SVE set SVE get SVE for VL 6512
3361 10:06:57.607753 # ok 1631 # SKIP SVE set SVE get FPSIMD for VL 6512
3362 10:06:57.607823 # ok 1632 # SKIP SVE set FPSIMD get SVE for VL 6512
3363 10:06:57.607900 # ok 1633 Set SVE VL 6528
3364 10:06:57.608208 # ok 1634 # SKIP SVE set SVE get SVE for VL 6528
3365 10:06:57.608402 # ok 1635 # SKIP SVE set SVE get FPSIMD for VL 6528
3366 10:06:57.608569 # ok 1636 # SKIP SVE set FPSIMD get SVE for VL 6528
3367 10:06:57.608784 # ok 1637 Set SVE VL 6544
3368 10:06:57.609024 # ok 1638 # SKIP SVE set SVE get SVE for VL 6544
3369 10:06:57.609195 # ok 1639 # SKIP SVE set SVE get FPSIMD for VL 6544
3370 10:06:57.609331 # ok 1640 # SKIP SVE set FPSIMD get SVE for VL 6544
3371 10:06:57.609467 # ok 1641 Set SVE VL 6560
3372 10:06:57.609626 # ok 1642 # SKIP SVE set SVE get SVE for VL 6560
3373 10:06:57.609800 # ok 1643 # SKIP SVE set SVE get FPSIMD for VL 6560
3374 10:06:57.609965 # ok 1644 # SKIP SVE set FPSIMD get SVE for VL 6560
3375 10:06:57.610168 # ok 1645 Set SVE VL 6576
3376 10:06:57.610338 # ok 1646 # SKIP SVE set SVE get SVE for VL 6576
3377 10:06:57.610504 # ok 1647 # SKIP SVE set SVE get FPSIMD for VL 6576
3378 10:06:57.610673 # ok 1648 # SKIP SVE set FPSIMD get SVE for VL 6576
3379 10:06:57.610838 # ok 1649 Set SVE VL 6592
3380 10:06:57.610998 # ok 1650 # SKIP SVE set SVE get SVE for VL 6592
3381 10:06:57.611150 # ok 1651 # SKIP SVE set SVE get FPSIMD for VL 6592
3382 10:06:57.611305 # ok 1652 # SKIP SVE set FPSIMD get SVE for VL 6592
3383 10:06:57.611443 # ok 1653 Set SVE VL 6608
3384 10:06:57.611596 # ok 1654 # SKIP SVE set SVE get SVE for VL 6608
3385 10:06:57.611760 # ok 1655 # SKIP SVE set SVE get FPSIMD for VL 6608
3386 10:06:57.611954 # ok 1656 # SKIP SVE set FPSIMD get SVE for VL 6608
3387 10:06:57.612123 # ok 1657 Set SVE VL 6624
3388 10:06:57.612327 # ok 1658 # SKIP SVE set SVE get SVE for VL 6624
3389 10:06:57.612499 # ok 1659 # SKIP SVE set SVE get FPSIMD for VL 6624
3390 10:06:57.612663 # ok 1660 # SKIP SVE set FPSIMD get SVE for VL 6624
3391 10:06:57.612828 # ok 1661 Set SVE VL 6640
3392 10:06:57.612989 # ok 1662 # SKIP SVE set SVE get SVE for VL 6640
3393 10:06:57.613158 # ok 1663 # SKIP SVE set SVE get FPSIMD for VL 6640
3394 10:06:57.613323 # ok 1664 # SKIP SVE set FPSIMD get SVE for VL 6640
3395 10:06:57.613481 # ok 1665 Set SVE VL 6656
3396 10:06:57.613636 # ok 1666 # SKIP SVE set SVE get SVE for VL 6656
3397 10:06:57.613801 # ok 1667 # SKIP SVE set SVE get FPSIMD for VL 6656
3398 10:06:57.613957 # ok 1668 # SKIP SVE set FPSIMD get SVE for VL 6656
3399 10:06:57.614119 # ok 1669 Set SVE VL 6672
3400 10:06:57.614281 # ok 1670 # SKIP SVE set SVE get SVE for VL 6672
3401 10:06:57.614446 # ok 1671 # SKIP SVE set SVE get FPSIMD for VL 6672
3402 10:06:57.614608 # ok 1672 # SKIP SVE set FPSIMD get SVE for VL 6672
3403 10:06:57.614767 # ok 1673 Set SVE VL 6688
3404 10:06:57.614907 # ok 1674 # SKIP SVE set SVE get SVE for VL 6688
3405 10:06:57.615061 # ok 1675 # SKIP SVE set SVE get FPSIMD for VL 6688
3406 10:06:57.615471 # ok 1676 # SKIP SVE set FPSIMD get SVE for VL 6688
3407 10:06:57.615655 # ok 1677 Set SVE VL 6704
3408 10:06:57.615795 # ok 1678 # SKIP SVE set SVE get SVE for VL 6704
3409 10:06:57.615950 # ok 1679 # SKIP SVE set SVE get FPSIMD for VL 6704
3410 10:06:57.616110 # ok 1680 # SKIP SVE set FPSIMD get SVE for VL 6704
3411 10:06:57.616271 # ok 1681 Set SVE VL 6720
3412 10:06:57.616423 # ok 1682 # SKIP SVE set SVE get SVE for VL 6720
3413 10:06:57.616585 # ok 1683 # SKIP SVE set SVE get FPSIMD for VL 6720
3414 10:06:57.616747 # ok 1684 # SKIP SVE set FPSIMD get SVE for VL 6720
3415 10:06:57.616891 # ok 1685 Set SVE VL 6736
3416 10:06:57.617044 # ok 1686 # SKIP SVE set SVE get SVE for VL 6736
3417 10:06:57.617198 # ok 1687 # SKIP SVE set SVE get FPSIMD for VL 6736
3418 10:06:57.617303 # ok 1688 # SKIP SVE set FPSIMD get SVE for VL 6736
3419 10:06:57.617426 # ok 1689 Set SVE VL 6752
3420 10:06:57.617546 # ok 1690 # SKIP SVE set SVE get SVE for VL 6752
3421 10:06:57.617876 # ok 1691 # SKIP SVE set SVE get FPSIMD for VL 6752
3422 10:06:57.618015 # ok 1692 # SKIP SVE set FPSIMD get SVE for VL 6752
3423 10:06:57.618137 # ok 1693 Set SVE VL 6768
3424 10:06:57.618224 # ok 1694 # SKIP SVE set SVE get SVE for VL 6768
3425 10:06:57.618304 # ok 1695 # SKIP SVE set SVE get FPSIMD for VL 6768
3426 10:06:57.618376 # ok 1696 # SKIP SVE set FPSIMD get SVE for VL 6768
3427 10:06:57.618454 # ok 1697 Set SVE VL 6784
3428 10:06:57.618530 # ok 1698 # SKIP SVE set SVE get SVE for VL 6784
3429 10:06:57.618604 # ok 1699 # SKIP SVE set SVE get FPSIMD for VL 6784
3430 10:06:57.618676 # ok 1700 # SKIP SVE set FPSIMD get SVE for VL 6784
3431 10:06:57.618742 # ok 1701 Set SVE VL 6800
3432 10:06:57.618818 # ok 1702 # SKIP SVE set SVE get SVE for VL 6800
3433 10:06:57.618889 # ok 1703 # SKIP SVE set SVE get FPSIMD for VL 6800
3434 10:06:57.618967 # ok 1704 # SKIP SVE set FPSIMD get SVE for VL 6800
3435 10:06:57.619048 # ok 1705 Set SVE VL 6816
3436 10:06:57.619127 # ok 1706 # SKIP SVE set SVE get SVE for VL 6816
3437 10:06:57.619212 # ok 1707 # SKIP SVE set SVE get FPSIMD for VL 6816
3438 10:06:57.619311 # ok 1708 # SKIP SVE set FPSIMD get SVE for VL 6816
3439 10:06:57.619392 # ok 1709 Set SVE VL 6832
3440 10:06:57.619473 # ok 1710 # SKIP SVE set SVE get SVE for VL 6832
3441 10:06:57.619565 # ok 1711 # SKIP SVE set SVE get FPSIMD for VL 6832
3442 10:06:57.619649 # ok 1712 # SKIP SVE set FPSIMD get SVE for VL 6832
3443 10:06:57.619724 # ok 1713 Set SVE VL 6848
3444 10:06:57.619813 # ok 1714 # SKIP SVE set SVE get SVE for VL 6848
3445 10:06:57.619891 # ok 1715 # SKIP SVE set SVE get FPSIMD for VL 6848
3446 10:06:57.619967 # ok 1716 # SKIP SVE set FPSIMD get SVE for VL 6848
3447 10:06:57.620038 # ok 1717 Set SVE VL 6864
3448 10:06:57.620099 # ok 1718 # SKIP SVE set SVE get SVE for VL 6864
3449 10:06:57.620519 # ok 1719 # SKIP SVE set SVE get FPSIMD for VL 6864
3450 10:06:57.620614 # ok 1720 # SKIP SVE set FPSIMD get SVE for VL 6864
3451 10:06:57.620682 # ok 1721 Set SVE VL 6880
3452 10:06:57.620750 # ok 1722 # SKIP SVE set SVE get SVE for VL 6880
3453 10:06:57.620815 # ok 1723 # SKIP SVE set SVE get FPSIMD for VL 6880
3454 10:06:57.620883 # ok 1724 # SKIP SVE set FPSIMD get SVE for VL 6880
3455 10:06:57.620956 # ok 1725 Set SVE VL 6896
3456 10:06:57.621024 # ok 1726 # SKIP SVE set SVE get SVE for VL 6896
3457 10:06:57.621091 # ok 1727 # SKIP SVE set SVE get FPSIMD for VL 6896
3458 10:06:57.621169 # ok 1728 # SKIP SVE set FPSIMD get SVE for VL 6896
3459 10:06:57.621267 # ok 1729 Set SVE VL 6912
3460 10:06:57.621361 # ok 1730 # SKIP SVE set SVE get SVE for VL 6912
3461 10:06:57.621449 # ok 1731 # SKIP SVE set SVE get FPSIMD for VL 6912
3462 10:06:57.621524 # ok 1732 # SKIP SVE set FPSIMD get SVE for VL 6912
3463 10:06:57.621598 # ok 1733 Set SVE VL 6928
3464 10:06:57.621688 # ok 1734 # SKIP SVE set SVE get SVE for VL 6928
3465 10:06:57.621775 # ok 1735 # SKIP SVE set SVE get FPSIMD for VL 6928
3466 10:06:57.621852 # ok 1736 # SKIP SVE set FPSIMD get SVE for VL 6928
3467 10:06:57.621929 # ok 1737 Set SVE VL 6944
3468 10:06:57.621990 # ok 1738 # SKIP SVE set SVE get SVE for VL 6944
3469 10:06:57.622066 # ok 1739 # SKIP SVE set SVE get FPSIMD for VL 6944
3470 10:06:57.622141 # ok 1740 # SKIP SVE set FPSIMD get SVE for VL 6944
3471 10:06:57.622208 # ok 1741 Set SVE VL 6960
3472 10:06:57.622268 # ok 1742 # SKIP SVE set SVE get SVE for VL 6960
3473 10:06:57.622341 # ok 1743 # SKIP SVE set SVE get FPSIMD for VL 6960
3474 10:06:57.622412 # ok 1744 # SKIP SVE set FPSIMD get SVE for VL 6960
3475 10:06:57.622481 # ok 1745 Set SVE VL 6976
3476 10:06:57.622550 # ok 1746 # SKIP SVE set SVE get SVE for VL 6976
3477 10:06:57.622620 # ok 1747 # SKIP SVE set SVE get FPSIMD for VL 6976
3478 10:06:57.622678 # ok 1748 # SKIP SVE set FPSIMD get SVE for VL 6976
3479 10:06:57.622736 # ok 1749 Set SVE VL 6992
3480 10:06:57.622793 # ok 1750 # SKIP SVE set SVE get SVE for VL 6992
3481 10:06:57.622850 # ok 1751 # SKIP SVE set SVE get FPSIMD for VL 6992
3482 10:06:57.622908 # ok 1752 # SKIP SVE set FPSIMD get SVE for VL 6992
3483 10:06:57.622966 # ok 1753 Set SVE VL 7008
3484 10:06:57.623038 # ok 1754 # SKIP SVE set SVE get SVE for VL 7008
3485 10:06:57.623099 # ok 1755 # SKIP SVE set SVE get FPSIMD for VL 7008
3486 10:06:57.623158 # ok 1756 # SKIP SVE set FPSIMD get SVE for VL 7008
3487 10:06:57.623215 # ok 1757 Set SVE VL 7024
3488 10:06:57.623273 # ok 1758 # SKIP SVE set SVE get SVE for VL 7024
3489 10:06:57.623331 # ok 1759 # SKIP SVE set SVE get FPSIMD for VL 7024
3490 10:06:57.623389 # ok 1760 # SKIP SVE set FPSIMD get SVE for VL 7024
3491 10:06:57.623447 # ok 1761 Set SVE VL 7040
3492 10:06:57.623732 # ok 1762 # SKIP SVE set SVE get SVE for VL 7040
3493 10:06:57.623888 # ok 1763 # SKIP SVE set SVE get FPSIMD for VL 7040
3494 10:06:57.624009 # ok 1764 # SKIP SVE set FPSIMD get SVE for VL 7040
3495 10:06:57.624124 # ok 1765 Set SVE VL 7056
3496 10:06:57.624239 # ok 1766 # SKIP SVE set SVE get SVE for VL 7056
3497 10:06:57.624351 # ok 1767 # SKIP SVE set SVE get FPSIMD for VL 7056
3498 10:06:57.624464 # ok 1768 # SKIP SVE set FPSIMD get SVE for VL 7056
3499 10:06:57.624577 # ok 1769 Set SVE VL 7072
3500 10:06:57.624689 # ok 1770 # SKIP SVE set SVE get SVE for VL 7072
3501 10:06:57.624802 # ok 1771 # SKIP SVE set SVE get FPSIMD for VL 7072
3502 10:06:57.624912 # ok 1772 # SKIP SVE set FPSIMD get SVE for VL 7072
3503 10:06:57.625419 # ok 1773 Set SVE VL 7088
3504 10:06:57.625800 # ok 1774 # SKIP SVE set SVE get SVE for VL 7088
3505 10:06:57.625888 # ok 1775 # SKIP SVE set SVE get FPSIMD for VL 7088
3506 10:06:57.626000 # ok 1776 # SKIP SVE set FPSIMD get SVE for VL 7088
3507 10:06:57.626087 # ok 1777 Set SVE VL 7104
3508 10:06:57.626240 # ok 1778 # SKIP SVE set SVE get SVE for VL 7104
3509 10:06:57.626384 # ok 1779 # SKIP SVE set SVE get FPSIMD for VL 7104
3510 10:06:57.626499 # ok 1780 # SKIP SVE set FPSIMD get SVE for VL 7104
3511 10:06:57.626620 # ok 1781 Set SVE VL 7120
3512 10:06:57.626760 # ok 1782 # SKIP SVE set SVE get SVE for VL 7120
3513 10:06:57.626878 # ok 1783 # SKIP SVE set SVE get FPSIMD for VL 7120
3514 10:06:57.627002 # ok 1784 # SKIP SVE set FPSIMD get SVE for VL 7120
3515 10:06:57.627150 # ok 1785 Set SVE VL 7136
3516 10:06:57.627302 # ok 1786 # SKIP SVE set SVE get SVE for VL 7136
3517 10:06:57.627419 # ok 1787 # SKIP SVE set SVE get FPSIMD for VL 7136
3518 10:06:57.627531 # ok 1788 # SKIP SVE set FPSIMD get SVE for VL 7136
3519 10:06:57.627640 # ok 1789 Set SVE VL 7152
3520 10:06:57.627730 # ok 1790 # SKIP SVE set SVE get SVE for VL 7152
3521 10:06:57.627834 # ok 1791 # SKIP SVE set SVE get FPSIMD for VL 7152
3522 10:06:57.627921 # ok 1792 # SKIP SVE set FPSIMD get SVE for VL 7152
3523 10:06:57.628007 # ok 1793 Set SVE VL 7168
3524 10:06:57.628296 # ok 1794 # SKIP SVE set SVE get SVE for VL 7168
3525 10:06:57.628375 # ok 1795 # SKIP SVE set SVE get FPSIMD for VL 7168
3526 10:06:57.628447 # ok 1796 # SKIP SVE set FPSIMD get SVE for VL 7168
3527 10:06:57.628528 # ok 1797 Set SVE VL 7184
3528 10:06:57.628602 # ok 1798 # SKIP SVE set SVE get SVE for VL 7184
3529 10:06:57.628680 # ok 1799 # SKIP SVE set SVE get FPSIMD for VL 7184
3530 10:06:57.628754 # ok 1800 # SKIP SVE set FPSIMD get SVE for VL 7184
3531 10:06:57.628841 # ok 1801 Set SVE VL 7200
3532 10:06:57.628932 # ok 1802 # SKIP SVE set SVE get SVE for VL 7200
3533 10:06:57.629021 # ok 1803 # SKIP SVE set SVE get FPSIMD for VL 7200
3534 10:06:57.629286 # ok 1804 # SKIP SVE set FPSIMD get SVE for VL 7200
3535 10:06:57.629355 # ok 1805 Set SVE VL 7216
3536 10:06:57.629427 # ok 1806 # SKIP SVE set SVE get SVE for VL 7216
3537 10:06:57.629492 # ok 1807 # SKIP SVE set SVE get FPSIMD for VL 7216
3538 10:06:57.629581 # ok 1808 # SKIP SVE set FPSIMD get SVE for VL 7216
3539 10:06:57.629707 # ok 1809 Set SVE VL 7232
3540 10:06:57.629991 # ok 1810 # SKIP SVE set SVE get SVE for VL 7232
3541 10:06:57.630068 # ok 1811 # SKIP SVE set SVE get FPSIMD for VL 7232
3542 10:06:57.630174 # ok 1812 # SKIP SVE set FPSIMD get SVE for VL 7232
3543 10:06:57.630246 # ok 1813 Set SVE VL 7248
3544 10:06:57.630335 # ok 1814 # SKIP SVE set SVE get SVE for VL 7248
3545 10:06:57.630419 # ok 1815 # SKIP SVE set SVE get FPSIMD for VL 7248
3546 10:06:57.630503 # ok 1816 # SKIP SVE set FPSIMD get SVE for VL 7248
3547 10:06:57.630589 # ok 1817 Set SVE VL 7264
3548 10:06:57.630671 # ok 1818 # SKIP SVE set SVE get SVE for VL 7264
3549 10:06:57.630958 # ok 1819 # SKIP SVE set SVE get FPSIMD for VL 7264
3550 10:06:57.631058 # ok 1820 # SKIP SVE set FPSIMD get SVE for VL 7264
3551 10:06:57.631144 # ok 1821 Set SVE VL 7280
3552 10:06:57.631238 # ok 1822 # SKIP SVE set SVE get SVE for VL 7280
3553 10:06:57.631314 # ok 1823 # SKIP SVE set SVE get FPSIMD for VL 7280
3554 10:06:57.631435 # ok 1824 # SKIP SVE set FPSIMD get SVE for VL 7280
3555 10:06:57.631529 # ok 1825 Set SVE VL 7296
3556 10:06:57.631649 # ok 1826 # SKIP SVE set SVE get SVE for VL 7296
3557 10:06:57.631734 # ok 1827 # SKIP SVE set SVE get FPSIMD for VL 7296
3558 10:06:57.631842 # ok 1828 # SKIP SVE set FPSIMD get SVE for VL 7296
3559 10:06:57.631947 # ok 1829 Set SVE VL 7312
3560 10:06:57.632042 # ok 1830 # SKIP SVE set SVE get SVE for VL 7312
3561 10:06:57.632138 # ok 1831 # SKIP SVE set SVE get FPSIMD for VL 7312
3562 10:06:57.632234 # ok 1832 # SKIP SVE set FPSIMD get SVE for VL 7312
3563 10:06:57.632326 # ok 1833 Set SVE VL 7328
3564 10:06:57.632413 # ok 1834 # SKIP SVE set SVE get SVE for VL 7328
3565 10:06:57.632716 # ok 1835 # SKIP SVE set SVE get FPSIMD for VL 7328
3566 10:06:57.632856 # ok 1836 # SKIP SVE set FPSIMD get SVE for VL 7328
3567 10:06:57.633009 # ok 1837 Set SVE VL 7344
3568 10:06:57.633160 # ok 1838 # SKIP SVE set SVE get SVE for VL 7344
3569 10:06:57.633303 # ok 1839 # SKIP SVE set SVE get FPSIMD for VL 7344
3570 10:06:57.633443 # ok 1840 # SKIP SVE set FPSIMD get SVE for VL 7344
3571 10:06:57.633573 # ok 1841 Set SVE VL 7360
3572 10:06:57.633706 # ok 1842 # SKIP SVE set SVE get SVE for VL 7360
3573 10:06:57.633829 # ok 1843 # SKIP SVE set SVE get FPSIMD for VL 7360
3574 10:06:57.633964 # ok 1844 # SKIP SVE set FPSIMD get SVE for VL 7360
3575 10:06:57.634068 # ok 1845 Set SVE VL 7376
3576 10:06:57.634175 # ok 1846 # SKIP SVE set SVE get SVE for VL 7376
3577 10:06:57.634283 # ok 1847 # SKIP SVE set SVE get FPSIMD for VL 7376
3578 10:06:57.634420 # ok 1848 # SKIP SVE set FPSIMD get SVE for VL 7376
3579 10:06:57.634524 # ok 1849 Set SVE VL 7392
3580 10:06:57.634630 # ok 1850 # SKIP SVE set SVE get SVE for VL 7392
3581 10:06:57.634771 # ok 1851 # SKIP SVE set SVE get FPSIMD for VL 7392
3582 10:06:57.634923 # ok 1852 # SKIP SVE set FPSIMD get SVE for VL 7392
3583 10:06:57.635056 # ok 1853 Set SVE VL 7408
3584 10:06:57.635166 # ok 1854 # SKIP SVE set SVE get SVE for VL 7408
3585 10:06:57.635306 # ok 1855 # SKIP SVE set SVE get FPSIMD for VL 7408
3586 10:06:57.635409 # ok 1856 # SKIP SVE set FPSIMD get SVE for VL 7408
3587 10:06:57.635532 # ok 1857 Set SVE VL 7424
3588 10:06:57.635650 # ok 1858 # SKIP SVE set SVE get SVE for VL 7424
3589 10:06:57.635780 # ok 1859 # SKIP SVE set SVE get FPSIMD for VL 7424
3590 10:06:57.635906 # ok 1860 # SKIP SVE set FPSIMD get SVE for VL 7424
3591 10:06:57.636038 # ok 1861 Set SVE VL 7440
3592 10:06:57.636163 # ok 1862 # SKIP SVE set SVE get SVE for VL 7440
3593 10:06:57.636280 # ok 1863 # SKIP SVE set SVE get FPSIMD for VL 7440
3594 10:06:57.636424 # ok 1864 # SKIP SVE set FPSIMD get SVE for VL 7440
3595 10:06:57.636546 # ok 1865 Set SVE VL 7456
3596 10:06:57.636663 # ok 1866 # SKIP SVE set SVE get SVE for VL 7456
3597 10:06:57.636780 # ok 1867 # SKIP SVE set SVE get FPSIMD for VL 7456
3598 10:06:57.636897 # ok 1868 # SKIP SVE set FPSIMD get SVE for VL 7456
3599 10:06:57.637015 # ok 1869 Set SVE VL 7472
3600 10:06:57.637131 # ok 1870 # SKIP SVE set SVE get SVE for VL 7472
3601 10:06:57.637247 # ok 1871 # SKIP SVE set SVE get FPSIMD for VL 7472
3602 10:06:57.637386 # ok 1872 # SKIP SVE set FPSIMD get SVE for VL 7472
3603 10:06:57.637507 # ok 1873 Set SVE VL 7488
3604 10:06:57.637624 # ok 1874 # SKIP SVE set SVE get SVE for VL 7488
3605 10:06:57.637754 # ok 1875 # SKIP SVE set SVE get FPSIMD for VL 7488
3606 10:06:57.637870 # ok 1876 # SKIP SVE set FPSIMD get SVE for VL 7488
3607 10:06:57.637985 # ok 1877 Set SVE VL 7504
3608 10:06:57.638306 # ok 1878 # SKIP SVE set SVE get SVE for VL 7504
3609 10:06:57.638408 # ok 1879 # SKIP SVE set SVE get FPSIMD for VL 7504
3610 10:06:57.638495 # ok 1880 # SKIP SVE set FPSIMD get SVE for VL 7504
3611 10:06:57.638576 # ok 1881 Set SVE VL 7520
3612 10:06:57.638658 # ok 1882 # SKIP SVE set SVE get SVE for VL 7520
3613 10:06:57.638742 # ok 1883 # SKIP SVE set SVE get FPSIMD for VL 7520
3614 10:06:57.638825 # ok 1884 # SKIP SVE set FPSIMD get SVE for VL 7520
3615 10:06:57.638906 # ok 1885 Set SVE VL 7536
3616 10:06:57.638987 # ok 1886 # SKIP SVE set SVE get SVE for VL 7536
3617 10:06:57.639068 # ok 1887 # SKIP SVE set SVE get FPSIMD for VL 7536
3618 10:06:57.639150 # ok 1888 # SKIP SVE set FPSIMD get SVE for VL 7536
3619 10:06:57.639234 # ok 1889 Set SVE VL 7552
3620 10:06:57.639336 # ok 1890 # SKIP SVE set SVE get SVE for VL 7552
3621 10:06:57.639424 # ok 1891 # SKIP SVE set SVE get FPSIMD for VL 7552
3622 10:06:57.639510 # ok 1892 # SKIP SVE set FPSIMD get SVE for VL 7552
3623 10:06:57.639597 # ok 1893 Set SVE VL 7568
3624 10:06:57.639682 # ok 1894 # SKIP SVE set SVE get SVE for VL 7568
3625 10:06:57.639766 # ok 1895 # SKIP SVE set SVE get FPSIMD for VL 7568
3626 10:06:57.639852 # ok 1896 # SKIP SVE set FPSIMD get SVE for VL 7568
3627 10:06:57.639956 # ok 1897 Set SVE VL 7584
3628 10:06:57.640043 # ok 1898 # SKIP SVE set SVE get SVE for VL 7584
3629 10:06:57.640129 # ok 1899 # SKIP SVE set SVE get FPSIMD for VL 7584
3630 10:06:57.640232 # ok 1900 # SKIP SVE set FPSIMD get SVE for VL 7584
3631 10:06:57.640318 # ok 1901 Set SVE VL 7600
3632 10:06:57.640412 # ok 1902 # SKIP SVE set SVE get SVE for VL 7600
3633 10:06:57.640496 # ok 1903 # SKIP SVE set SVE get FPSIMD for VL 7600
3634 10:06:57.640590 # ok 1904 # SKIP SVE set FPSIMD get SVE for VL 7600
3635 10:06:57.640699 # ok 1905 Set SVE VL 7616
3636 10:06:57.640783 # ok 1906 # SKIP SVE set SVE get SVE for VL 7616
3637 10:06:57.640886 # ok 1907 # SKIP SVE set SVE get FPSIMD for VL 7616
3638 10:06:57.641183 # ok 1908 # SKIP SVE set FPSIMD get SVE for VL 7616
3639 10:06:57.641305 # ok 1909 Set SVE VL 7632
3640 10:06:57.641392 # ok 1910 # SKIP SVE set SVE get SVE for VL 7632
3641 10:06:57.641489 # ok 1911 # SKIP SVE set SVE get FPSIMD for VL 7632
3642 10:06:57.641596 # ok 1912 # SKIP SVE set FPSIMD get SVE for VL 7632
3643 10:06:57.641891 # ok 1913 Set SVE VL 7648
3644 10:06:57.641989 # ok 1914 # SKIP SVE set SVE get SVE for VL 7648
3645 10:06:57.642089 # ok 1915 # SKIP SVE set SVE get FPSIMD for VL 7648
3646 10:06:57.642174 # ok 1916 # SKIP SVE set FPSIMD get SVE for VL 7648
3647 10:06:57.642286 # ok 1917 Set SVE VL 7664
3648 10:06:57.642561 # ok 1918 # SKIP SVE set SVE get SVE for VL 7664
3649 10:06:57.642649 # ok 1919 # SKIP SVE set SVE get FPSIMD for VL 7664
3650 10:06:57.642744 # ok 1920 # SKIP SVE set FPSIMD get SVE for VL 7664
3651 10:06:57.642827 # ok 1921 Set SVE VL 7680
3652 10:06:57.642921 # ok 1922 # SKIP SVE set SVE get SVE for VL 7680
3653 10:06:57.643017 # ok 1923 # SKIP SVE set SVE get FPSIMD for VL 7680
3654 10:06:57.643114 # ok 1924 # SKIP SVE set FPSIMD get SVE for VL 7680
3655 10:06:57.643212 # ok 1925 Set SVE VL 7696
3656 10:06:57.643500 # ok 1926 # SKIP SVE set SVE get SVE for VL 7696
3657 10:06:57.643620 # ok 1927 # SKIP SVE set SVE get FPSIMD for VL 7696
3658 10:06:57.643728 # ok 1928 # SKIP SVE set FPSIMD get SVE for VL 7696
3659 10:06:57.643832 # ok 1929 Set SVE VL 7712
3660 10:06:57.643911 # ok 1930 # SKIP SVE set SVE get SVE for VL 7712
3661 10:06:57.643997 # ok 1931 # SKIP SVE set SVE get FPSIMD for VL 7712
3662 10:06:57.644079 # ok 1932 # SKIP SVE set FPSIMD get SVE for VL 7712
3663 10:06:57.644150 # ok 1933 Set SVE VL 7728
3664 10:06:57.644457 # ok 1934 # SKIP SVE set SVE get SVE for VL 7728
3665 10:06:57.644681 # ok 1935 # SKIP SVE set SVE get FPSIMD for VL 7728
3666 10:06:57.644871 # ok 1936 # SKIP SVE set FPSIMD get SVE for VL 7728
3667 10:06:57.645032 # ok 1937 Set SVE VL 7744
3668 10:06:57.645187 # ok 1938 # SKIP SVE set SVE get SVE for VL 7744
3669 10:06:57.645369 # ok 1939 # SKIP SVE set SVE get FPSIMD for VL 7744
3670 10:06:57.645527 # ok 1940 # SKIP SVE set FPSIMD get SVE for VL 7744
3671 10:06:57.645696 # ok 1941 Set SVE VL 7760
3672 10:06:57.645852 # ok 1942 # SKIP SVE set SVE get SVE for VL 7760
3673 10:06:57.646034 # ok 1943 # SKIP SVE set SVE get FPSIMD for VL 7760
3674 10:06:57.646198 # ok 1944 # SKIP SVE set FPSIMD get SVE for VL 7760
3675 10:06:57.646321 # ok 1945 Set SVE VL 7776
3676 10:06:57.646438 # ok 1946 # SKIP SVE set SVE get SVE for VL 7776
3677 10:06:57.646554 # ok 1947 # SKIP SVE set SVE get FPSIMD for VL 7776
3678 10:06:57.646695 # ok 1948 # SKIP SVE set FPSIMD get SVE for VL 7776
3679 10:06:57.646816 # ok 1949 Set SVE VL 7792
3680 10:06:57.646933 # ok 1950 # SKIP SVE set SVE get SVE for VL 7792
3681 10:06:57.647051 # ok 1951 # SKIP SVE set SVE get FPSIMD for VL 7792
3682 10:06:57.647167 # ok 1952 # SKIP SVE set FPSIMD get SVE for VL 7792
3683 10:06:57.647280 # ok 1953 Set SVE VL 7808
3684 10:06:57.647408 # ok 1954 # SKIP SVE set SVE get SVE for VL 7808
3685 10:06:57.647521 # ok 1955 # SKIP SVE set SVE get FPSIMD for VL 7808
3686 10:06:57.649709 # ok 1956 # SKIP SVE set FPSIMD get SVE for VL 7808
3687 10:06:57.649864 # ok 1957 Set SVE VL 7824
3688 10:06:57.649955 # ok 1958 # SKIP SVE set SVE get SVE for VL 7824
3689 10:06:57.650060 # ok 1959 # SKIP SVE set SVE get FPSIMD for VL 7824
3690 10:06:57.650148 # ok 1960 # SKIP SVE set FPSIMD get SVE for VL 7824
3691 10:06:57.650233 # ok 1961 Set SVE VL 7840
3692 10:06:57.650338 # ok 1962 # SKIP SVE set SVE get SVE for VL 7840
3693 10:06:57.650428 # ok 1963 # SKIP SVE set SVE get FPSIMD for VL 7840
3694 10:06:57.650528 # ok 1964 # SKIP SVE set FPSIMD get SVE for VL 7840
3695 10:06:57.650618 # ok 1965 Set SVE VL 7856
3696 10:06:57.650718 # ok 1966 # SKIP SVE set SVE get SVE for VL 7856
3697 10:06:57.650816 # ok 1967 # SKIP SVE set SVE get FPSIMD for VL 7856
3698 10:06:57.650915 # ok 1968 # SKIP SVE set FPSIMD get SVE for VL 7856
3699 10:06:57.650994 # ok 1969 Set SVE VL 7872
3700 10:06:57.651083 # ok 1970 # SKIP SVE set SVE get SVE for VL 7872
3701 10:06:57.651187 # ok 1971 # SKIP SVE set SVE get FPSIMD for VL 7872
3702 10:06:57.651922 # ok 1972 # SKIP SVE set FPSIMD get SVE for VL 7872
3703 10:06:57.652002 # ok 1973 Set SVE VL 7888
3704 10:06:57.652063 # ok 1974 # SKIP SVE set SVE get SVE for VL 7888
3705 10:06:57.652122 # ok 1975 # SKIP SVE set SVE get FPSIMD for VL 7888
3706 10:06:57.652178 # ok 1976 # SKIP SVE set FPSIMD get SVE for VL 7888
3707 10:06:57.652784 # ok 1977 Set SVE VL 7904
3708 10:06:57.653091 # ok 1978 # SKIP SVE set SVE get SVE for VL 7904
3709 10:06:57.653234 # ok 1979 # SKIP SVE set SVE get FPSIMD for VL 7904
3710 10:06:57.653352 # ok 1980 # SKIP SVE set FPSIMD get SVE for VL 7904
3711 10:06:57.653489 # ok 1981 Set SVE VL 7920
3712 10:06:57.653608 # ok 1982 # SKIP SVE set SVE get SVE for VL 7920
3713 10:06:57.653727 # ok 1983 # SKIP SVE set SVE get FPSIMD for VL 7920
3714 10:06:57.653832 # ok 1984 # SKIP SVE set FPSIMD get SVE for VL 7920
3715 10:06:57.653956 # ok 1985 Set SVE VL 7936
3716 10:06:57.654064 # ok 1986 # SKIP SVE set SVE get SVE for VL 7936
3717 10:06:57.654170 # ok 1987 # SKIP SVE set SVE get FPSIMD for VL 7936
3718 10:06:57.654272 # ok 1988 # SKIP SVE set FPSIMD get SVE for VL 7936
3719 10:06:57.654350 # ok 1989 Set SVE VL 7952
3720 10:06:57.654440 # ok 1990 # SKIP SVE set SVE get SVE for VL 7952
3721 10:06:57.654515 # ok 1991 # SKIP SVE set SVE get FPSIMD for VL 7952
3722 10:06:57.654588 # ok 1992 # SKIP SVE set FPSIMD get SVE for VL 7952
3723 10:06:57.654660 # ok 1993 Set SVE VL 7968
3724 10:06:57.654732 # ok 1994 # SKIP SVE set SVE get SVE for VL 7968
3725 10:06:57.654820 # ok 1995 # SKIP SVE set SVE get FPSIMD for VL 7968
3726 10:06:57.654895 # ok 1996 # SKIP SVE set FPSIMD get SVE for VL 7968
3727 10:06:57.654968 # ok 1997 Set SVE VL 7984
3728 10:06:57.655054 # ok 1998 # SKIP SVE set SVE get SVE for VL 7984
3729 10:06:57.655135 # ok 1999 # SKIP SVE set SVE get FPSIMD for VL 7984
3730 10:06:57.655215 # ok 2000 # SKIP SVE set FPSIMD get SVE for VL 7984
3731 10:06:57.655292 # ok 2001 Set SVE VL 8000
3732 10:06:57.655378 # ok 2002 # SKIP SVE set SVE get SVE for VL 8000
3733 10:06:57.655466 # ok 2003 # SKIP SVE set SVE get FPSIMD for VL 8000
3734 10:06:57.655572 # ok 2004 # SKIP SVE set FPSIMD get SVE for VL 8000
3735 10:06:57.655656 # ok 2005 Set SVE VL 8016
3736 10:06:57.655749 # ok 2006 # SKIP SVE set SVE get SVE for VL 8016
3737 10:06:57.655847 # ok 2007 # SKIP SVE set SVE get FPSIMD for VL 8016
3738 10:06:57.655943 # ok 2008 # SKIP SVE set FPSIMD get SVE for VL 8016
3739 10:06:57.656039 # ok 2009 Set SVE VL 8032
3740 10:06:57.656138 # ok 2010 # SKIP SVE set SVE get SVE for VL 8032
3741 10:06:57.656237 # ok 2011 # SKIP SVE set SVE get FPSIMD for VL 8032
3742 10:06:57.656339 # ok 2012 # SKIP SVE set FPSIMD get SVE for VL 8032
3743 10:06:57.656437 # ok 2013 Set SVE VL 8048
3744 10:06:57.656521 # ok 2014 # SKIP SVE set SVE get SVE for VL 8048
3745 10:06:57.656617 # ok 2015 # SKIP SVE set SVE get FPSIMD for VL 8048
3746 10:06:57.656718 # ok 2016 # SKIP SVE set FPSIMD get SVE for VL 8048
3747 10:06:57.656813 # ok 2017 Set SVE VL 8064
3748 10:06:57.656911 # ok 2018 # SKIP SVE set SVE get SVE for VL 8064
3749 10:06:57.657180 # ok 2019 # SKIP SVE set SVE get FPSIMD for VL 8064
3750 10:06:57.657262 # ok 2020 # SKIP SVE set FPSIMD get SVE for VL 8064
3751 10:06:57.657339 # ok 2021 Set SVE VL 8080
3752 10:06:57.657408 # ok 2022 # SKIP SVE set SVE get SVE for VL 8080
3753 10:06:57.657663 # ok 2023 # SKIP SVE set SVE get FPSIMD for VL 8080
3754 10:06:57.657728 # ok 2024 # SKIP SVE set FPSIMD get SVE for VL 8080
3755 10:06:57.657797 # ok 2025 Set SVE VL 8096
3756 10:06:57.657866 # ok 2026 # SKIP SVE set SVE get SVE for VL 8096
3757 10:06:57.658116 # ok 2027 # SKIP SVE set SVE get FPSIMD for VL 8096
3758 10:06:57.658200 # ok 2028 # SKIP SVE set FPSIMD get SVE for VL 8096
3759 10:06:57.658286 # ok 2029 Set SVE VL 8112
3760 10:06:57.658368 # ok 2030 # SKIP SVE set SVE get SVE for VL 8112
3761 10:06:57.665732 # ok 2031 # SKIP SVE set SVE get FPSIMD for VL 8112
3762 10:06:57.665860 # ok 2032 # SKIP SVE set FPSIMD get SVE for VL 8112
3763 10:06:57.665949 # ok 2033 Set SVE VL 8128
3764 10:06:57.666033 # ok 2034 # SKIP SVE set SVE get SVE for VL 8128
3765 10:06:57.666117 # ok 2035 # SKIP SVE set SVE get FPSIMD for VL 8128
3766 10:06:57.666198 # ok 2036 # SKIP SVE set FPSIMD get SVE for VL 8128
3767 10:06:57.666289 # ok 2037 Set SVE VL 8144
3768 10:06:57.666369 # ok 2038 # SKIP SVE set SVE get SVE for VL 8144
3769 10:06:57.666453 # ok 2039 # SKIP SVE set SVE get FPSIMD for VL 8144
3770 10:06:57.666533 # ok 2040 # SKIP SVE set FPSIMD get SVE for VL 8144
3771 10:06:57.666621 # ok 2041 Set SVE VL 8160
3772 10:06:57.666705 # ok 2042 # SKIP SVE set SVE get SVE for VL 8160
3773 10:06:57.666785 # ok 2043 # SKIP SVE set SVE get FPSIMD for VL 8160
3774 10:06:57.666865 # ok 2044 # SKIP SVE set FPSIMD get SVE for VL 8160
3775 10:06:57.666946 # ok 2045 Set SVE VL 8176
3776 10:06:57.667024 # ok 2046 # SKIP SVE set SVE get SVE for VL 8176
3777 10:06:57.667104 # ok 2047 # SKIP SVE set SVE get FPSIMD for VL 8176
3778 10:06:57.667184 # ok 2048 # SKIP SVE set FPSIMD get SVE for VL 8176
3779 10:06:57.667266 # ok 2049 Set SVE VL 8192
3780 10:06:57.667353 # ok 2050 # SKIP SVE set SVE get SVE for VL 8192
3781 10:06:57.667433 # ok 2051 # SKIP SVE set SVE get FPSIMD for VL 8192
3782 10:06:57.667515 # ok 2052 # SKIP SVE set FPSIMD get SVE for VL 8192
3783 10:06:57.667647 # ok 2053 Streaming SVE FPSIMD set via SVE: 0
3784 10:06:57.667732 # ok 2054 Streaming SVE get_fpsimd() gave same state
3785 10:06:57.667813 # ok 2055 Streaming SVE SVE_PT_VL_INHERIT set
3786 10:06:57.667894 # ok 2056 Streaming SVE SVE_PT_VL_INHERIT cleared
3787 10:06:57.667976 # ok 2057 Set Streaming SVE VL 16
3788 10:06:57.668059 # ok 2058 Set and get Streaming SVE data for VL 16
3789 10:06:57.668141 # ok 2059 Set and get FPSIMD data for Streaming SVE VL 16
3790 10:06:57.668221 # ok 2060 Set FPSIMD, read via SVE for Streaming SVE VL 16
3791 10:06:57.668300 # ok 2061 Set Streaming SVE VL 32
3792 10:06:57.668381 # ok 2062 Set and get Streaming SVE data for VL 32
3793 10:06:57.668463 # ok 2063 Set and get FPSIMD data for Streaming SVE VL 32
3794 10:06:57.668544 # ok 2064 Set FPSIMD, read via SVE for Streaming SVE VL 32
3795 10:06:57.668625 # ok 2065 Set Streaming SVE VL 48
3796 10:06:57.668703 # ok 2066 # SKIP Streaming SVE set SVE get SVE for VL 48
3797 10:06:57.668784 # ok 2067 # SKIP Streaming SVE set SVE get FPSIMD for VL 48
3798 10:06:57.668863 # ok 2068 # SKIP Streaming SVE set FPSIMD get SVE for VL 48
3799 10:06:57.668941 # ok 2069 Set Streaming SVE VL 64
3800 10:06:57.669021 # ok 2070 Set and get Streaming SVE data for VL 64
3801 10:06:57.669101 # ok 2071 Set and get FPSIMD data for Streaming SVE VL 64
3802 10:06:57.669409 # ok 2072 Set FPSIMD, read via SVE for Streaming SVE VL 64
3803 10:06:57.669508 # ok 2073 Set Streaming SVE VL 80
3804 10:06:57.669590 # ok 2074 # SKIP Streaming SVE set SVE get SVE for VL 80
3805 10:06:57.669680 # ok 2075 # SKIP Streaming SVE set SVE get FPSIMD for VL 80
3806 10:06:57.669763 # ok 2076 # SKIP Streaming SVE set FPSIMD get SVE for VL 80
3807 10:06:57.669844 # ok 2077 Set Streaming SVE VL 96
3808 10:06:57.669920 # ok 2078 # SKIP Streaming SVE set SVE get SVE for VL 96
3809 10:06:57.669996 # ok 2079 # SKIP Streaming SVE set SVE get FPSIMD for VL 96
3810 10:06:57.670070 # ok 2080 # SKIP Streaming SVE set FPSIMD get SVE for VL 96
3811 10:06:57.670143 # ok 2081 Set Streaming SVE VL 112
3812 10:06:57.670214 # ok 2082 # SKIP Streaming SVE set SVE get SVE for VL 112
3813 10:06:57.670283 # ok 2083 # SKIP Streaming SVE set SVE get FPSIMD for VL 112
3814 10:06:57.670353 # ok 2084 # SKIP Streaming SVE set FPSIMD get SVE for VL 112
3815 10:06:57.670424 # ok 2085 Set Streaming SVE VL 128
3816 10:06:57.670494 # ok 2086 Set and get Streaming SVE data for VL 128
3817 10:06:57.670563 # ok 2087 Set and get FPSIMD data for Streaming SVE VL 128
3818 10:06:57.670638 # ok 2088 Set FPSIMD, read via SVE for Streaming SVE VL 128
3819 10:06:57.670713 # ok 2089 Set Streaming SVE VL 144
3820 10:06:57.670795 # ok 2090 # SKIP Streaming SVE set SVE get SVE for VL 144
3821 10:06:57.670872 # ok 2091 # SKIP Streaming SVE set SVE get FPSIMD for VL 144
3822 10:06:57.670946 # ok 2092 # SKIP Streaming SVE set FPSIMD get SVE for VL 144
3823 10:06:57.671018 # ok 2093 Set Streaming SVE VL 160
3824 10:06:57.671089 # ok 2094 # SKIP Streaming SVE set SVE get SVE for VL 160
3825 10:06:57.671159 # ok 2095 # SKIP Streaming SVE set SVE get FPSIMD for VL 160
3826 10:06:57.671229 # ok 2096 # SKIP Streaming SVE set FPSIMD get SVE for VL 160
3827 10:06:57.671298 # ok 2097 Set Streaming SVE VL 176
3828 10:06:57.671366 # ok 2098 # SKIP Streaming SVE set SVE get SVE for VL 176
3829 10:06:57.671434 # ok 2099 # SKIP Streaming SVE set SVE get FPSIMD for VL 176
3830 10:06:57.671506 # ok 2100 # SKIP Streaming SVE set FPSIMD get SVE for VL 176
3831 10:06:57.671576 # ok 2101 Set Streaming SVE VL 192
3832 10:06:57.671647 # ok 2102 # SKIP Streaming SVE set SVE get SVE for VL 192
3833 10:06:57.671715 # ok 2103 # SKIP Streaming SVE set SVE get FPSIMD for VL 192
3834 10:06:57.671785 # ok 2104 # SKIP Streaming SVE set FPSIMD get SVE for VL 192
3835 10:06:57.671857 # ok 2105 Set Streaming SVE VL 208
3836 10:06:57.671927 # ok 2106 # SKIP Streaming SVE set SVE get SVE for VL 208
3837 10:06:57.671998 # ok 2107 # SKIP Streaming SVE set SVE get FPSIMD for VL 208
3838 10:06:57.672272 # ok 2108 # SKIP Streaming SVE set FPSIMD get SVE for VL 208
3839 10:06:57.672351 # ok 2109 Set Streaming SVE VL 224
3840 10:06:57.672421 # ok 2110 # SKIP Streaming SVE set SVE get SVE for VL 224
3841 10:06:57.672491 # ok 2111 # SKIP Streaming SVE set SVE get FPSIMD for VL 224
3842 10:06:57.672561 # ok 2112 # SKIP Streaming SVE set FPSIMD get SVE for VL 224
3843 10:06:57.672631 # ok 2113 Set Streaming SVE VL 240
3844 10:06:57.672703 # ok 2114 # SKIP Streaming SVE set SVE get SVE for VL 240
3845 10:06:57.672772 # ok 2115 # SKIP Streaming SVE set SVE get FPSIMD for VL 240
3846 10:06:57.672842 # ok 2116 # SKIP Streaming SVE set FPSIMD get SVE for VL 240
3847 10:06:57.672914 # ok 2117 Set Streaming SVE VL 256
3848 10:06:57.672984 # ok 2118 Set and get Streaming SVE data for VL 256
3849 10:06:57.673055 # ok 2119 Set and get FPSIMD data for Streaming SVE VL 256
3850 10:06:57.673126 # ok 2120 Set FPSIMD, read via SVE for Streaming SVE VL 256
3851 10:06:57.673194 # ok 2121 Set Streaming SVE VL 272
3852 10:06:57.673272 # ok 2122 # SKIP Streaming SVE set SVE get SVE for VL 272
3853 10:06:57.673355 # ok 2123 # SKIP Streaming SVE set SVE get FPSIMD for VL 272
3854 10:06:57.673439 # ok 2124 # SKIP Streaming SVE set FPSIMD get SVE for VL 272
3855 10:06:57.673511 # ok 2125 Set Streaming SVE VL 288
3856 10:06:57.674710 # ok 2126 # SKIP Streaming SVE set SVE get SVE for VL 288
3857 10:06:57.675022 # ok 2127 # SKIP Streaming SVE set SVE get FPSIMD for VL 288
3858 10:06:57.675110 # ok 2128 # SKIP Streaming SVE set FPSIMD get SVE for VL 288
3859 10:06:57.675238 # ok 2129 Set Streaming SVE VL 304
3860 10:06:57.675328 # ok 2130 # SKIP Streaming SVE set SVE get SVE for VL 304
3861 10:06:57.675438 # ok 2131 # SKIP Streaming SVE set SVE get FPSIMD for VL 304
3862 10:06:57.675552 # ok 2132 # SKIP Streaming SVE set FPSIMD get SVE for VL 304
3863 10:06:57.675660 # ok 2133 Set Streaming SVE VL 320
3864 10:06:57.676441 # ok 2134 # SKIP Streaming SVE set SVE get SVE for VL 320
3865 10:06:57.676707 # ok 2135 # SKIP Streaming SVE set SVE get FPSIMD for VL 320
3866 10:06:57.676781 # ok 2136 # SKIP Streaming SVE set FPSIMD get SVE for VL 320
3867 10:06:57.676873 # ok 2137 Set Streaming SVE VL 336
3868 10:06:57.676966 # ok 2138 # SKIP Streaming SVE set SVE get SVE for VL 336
3869 10:06:57.677050 # ok 2139 # SKIP Streaming SVE set SVE get FPSIMD for VL 336
3870 10:06:57.677140 # ok 2140 # SKIP Streaming SVE set FPSIMD get SVE for VL 336
3871 10:06:57.677253 # ok 2141 Set Streaming SVE VL 352
3872 10:06:57.677358 # ok 2142 # SKIP Streaming SVE set SVE get SVE for VL 352
3873 10:06:57.677736 # ok 2143 # SKIP Streaming SVE set SVE get FPSIMD for VL 352
3874 10:06:57.677806 # ok 2144 # SKIP Streaming SVE set FPSIMD get SVE for VL 352
3875 10:06:57.677866 # ok 2145 Set Streaming SVE VL 368
3876 10:06:57.677924 # ok 2146 # SKIP Streaming SVE set SVE get SVE for VL 368
3877 10:06:57.678162 # ok 2147 # SKIP Streaming SVE set SVE get FPSIMD for VL 368
3878 10:06:57.678248 # ok 2148 # SKIP Streaming SVE set FPSIMD get SVE for VL 368
3879 10:06:57.678335 # ok 2149 Set Streaming SVE VL 384
3880 10:06:57.678426 # ok 2150 # SKIP Streaming SVE set SVE get SVE for VL 384
3881 10:06:57.678512 # ok 2151 # SKIP Streaming SVE set SVE get FPSIMD for VL 384
3882 10:06:57.678590 # ok 2152 # SKIP Streaming SVE set FPSIMD get SVE for VL 384
3883 10:06:57.679525 # ok 2153 Set Streaming SVE VL 400
3884 10:06:57.679620 # ok 2154 # SKIP Streaming SVE set SVE get SVE for VL 400
3885 10:06:57.679699 # ok 2155 # SKIP Streaming SVE set SVE get FPSIMD for VL 400
3886 10:06:57.679760 # ok 2156 # SKIP Streaming SVE set FPSIMD get SVE for VL 400
3887 10:06:57.679818 # ok 2157 Set Streaming SVE VL 416
3888 10:06:57.679876 # ok 2158 # SKIP Streaming SVE set SVE get SVE for VL 416
3889 10:06:57.679941 # ok 2159 # SKIP Streaming SVE set SVE get FPSIMD for VL 416
3890 10:06:57.680042 # ok 2160 # SKIP Streaming SVE set FPSIMD get SVE for VL 416
3891 10:06:57.680154 # ok 2161 Set Streaming SVE VL 432
3892 10:06:57.680254 # ok 2162 # SKIP Streaming SVE set SVE get SVE for VL 432
3893 10:06:57.680352 # ok 2163 # SKIP Streaming SVE set SVE get FPSIMD for VL 432
3894 10:06:57.680640 # ok 2164 # SKIP Streaming SVE set FPSIMD get SVE for VL 432
3895 10:06:57.680742 # ok 2165 Set Streaming SVE VL 448
3896 10:06:57.680846 # ok 2166 # SKIP Streaming SVE set SVE get SVE for VL 448
3897 10:06:57.680963 # ok 2167 # SKIP Streaming SVE set SVE get FPSIMD for VL 448
3898 10:06:57.681060 # ok 2168 # SKIP Streaming SVE set FPSIMD get SVE for VL 448
3899 10:06:57.681170 # ok 2169 Set Streaming SVE VL 464
3900 10:06:57.681304 # ok 2170 # SKIP Streaming SVE set SVE get SVE for VL 464
3901 10:06:57.681418 # ok 2171 # SKIP Streaming SVE set SVE get FPSIMD for VL 464
3902 10:06:57.681518 # ok 2172 # SKIP Streaming SVE set FPSIMD get SVE for VL 464
3903 10:06:57.681656 # ok 2173 Set Streaming SVE VL 480
3904 10:06:57.681766 # ok 2174 # SKIP Streaming SVE set SVE get SVE for VL 480
3905 10:06:57.681838 # ok 2175 # SKIP Streaming SVE set SVE get FPSIMD for VL 480
3906 10:06:57.681904 # ok 2176 # SKIP Streaming SVE set FPSIMD get SVE for VL 480
3907 10:06:57.681974 # ok 2177 Set Streaming SVE VL 496
3908 10:06:57.682059 # ok 2178 # SKIP Streaming SVE set SVE get SVE for VL 496
3909 10:06:57.682136 # ok 2179 # SKIP Streaming SVE set SVE get FPSIMD for VL 496
3910 10:06:57.682221 # ok 2180 # SKIP Streaming SVE set FPSIMD get SVE for VL 496
3911 10:06:57.682302 # ok 2181 Set Streaming SVE VL 512
3912 10:06:57.682381 # ok 2182 # SKIP Streaming SVE set SVE get SVE for VL 512
3913 10:06:57.682479 # ok 2183 # SKIP Streaming SVE set SVE get FPSIMD for VL 512
3914 10:06:57.683182 # ok 2184 # SKIP Streaming SVE set FPSIMD get SVE for VL 512
3915 10:06:57.683297 # ok 2185 Set Streaming SVE VL 528
3916 10:06:57.683391 # ok 2186 # SKIP Streaming SVE set SVE get SVE for VL 528
3917 10:06:57.683471 # ok 2187 # SKIP Streaming SVE set SVE get FPSIMD for VL 528
3918 10:06:57.683545 # ok 2188 # SKIP Streaming SVE set FPSIMD get SVE for VL 528
3919 10:06:57.683632 # ok 2189 Set Streaming SVE VL 544
3920 10:06:57.683922 # ok 2190 # SKIP Streaming SVE set SVE get SVE for VL 544
3921 10:06:57.684013 # ok 2191 # SKIP Streaming SVE set SVE get FPSIMD for VL 544
3922 10:06:57.684088 # ok 2192 # SKIP Streaming SVE set FPSIMD get SVE for VL 544
3923 10:06:57.684164 # ok 2193 Set Streaming SVE VL 560
3924 10:06:57.684246 # ok 2194 # SKIP Streaming SVE set SVE get SVE for VL 560
3925 10:06:57.684311 # ok 2195 # SKIP Streaming SVE set SVE get FPSIMD for VL 560
3926 10:06:57.684384 # ok 2196 # SKIP Streaming SVE set FPSIMD get SVE for VL 560
3927 10:06:57.684449 # ok 2197 Set Streaming SVE VL 576
3928 10:06:57.684528 # ok 2198 # SKIP Streaming SVE set SVE get SVE for VL 576
3929 10:06:57.684807 # ok 2199 # SKIP Streaming SVE set SVE get FPSIMD for VL 576
3930 10:06:57.684894 # ok 2200 # SKIP Streaming SVE set FPSIMD get SVE for VL 576
3931 10:06:57.684964 # ok 2201 Set Streaming SVE VL 592
3932 10:06:57.685054 # ok 2202 # SKIP Streaming SVE set SVE get SVE for VL 592
3933 10:06:57.685144 # ok 2203 # SKIP Streaming SVE set SVE get FPSIMD for VL 592
3934 10:06:57.685440 # ok 2204 # SKIP Streaming SVE set FPSIMD get SVE for VL 592
3935 10:06:57.685550 # ok 2205 Set Streaming SVE VL 608
3936 10:06:57.685638 # ok 2206 # SKIP Streaming SVE set SVE get SVE for VL 608
3937 10:06:57.685737 # ok 2207 # SKIP Streaming SVE set SVE get FPSIMD for VL 608
3938 10:06:57.685824 # ok 2208 # SKIP Streaming SVE set FPSIMD get SVE for VL 608
3939 10:06:57.685913 # ok 2209 Set Streaming SVE VL 624
3940 10:06:57.685999 # ok 2210 # SKIP Streaming SVE set SVE get SVE for VL 624
3941 10:06:57.686293 # ok 2211 # SKIP Streaming SVE set SVE get FPSIMD for VL 624
3942 10:06:57.686393 # ok 2212 # SKIP Streaming SVE set FPSIMD get SVE for VL 624
3943 10:06:57.686491 # ok 2213 Set Streaming SVE VL 640
3944 10:06:57.686592 # ok 2214 # SKIP Streaming SVE set SVE get SVE for VL 640
3945 10:06:57.686858 # ok 2215 # SKIP Streaming SVE set SVE get FPSIMD for VL 640
3946 10:06:57.687005 # ok 2216 # SKIP Streaming SVE set FPSIMD get SVE for VL 640
3947 10:06:57.687112 # ok 2217 Set Streaming SVE VL 656
3948 10:06:57.687210 # ok 2218 # SKIP Streaming SVE set SVE get SVE for VL 656
3949 10:06:57.687515 # ok 2219 # SKIP Streaming SVE set SVE get FPSIMD for VL 656
3950 10:06:57.687669 # ok 2220 # SKIP Streaming SVE set FPSIMD get SVE for VL 656
3951 10:06:57.687964 # ok 2221 Set Streaming SVE VL 672
3952 10:06:57.688088 # ok 2222 # SKIP Streaming SVE set SVE get SVE for VL 672
3953 10:06:57.688237 # ok 2223 # SKIP Streaming SVE set SVE get FPSIMD for VL 672
3954 10:06:57.688369 # ok 2224 # SKIP Streaming SVE set FPSIMD get SVE for VL 672
3955 10:06:57.688661 # ok 2225 Set Streaming SVE VL 688
3956 10:06:57.688762 # ok 2226 # SKIP Streaming SVE set SVE get SVE for VL 688
3957 10:06:57.688862 # ok 2227 # SKIP Streaming SVE set SVE get FPSIMD for VL 688
3958 10:06:57.689156 # ok 2228 # SKIP Streaming SVE set FPSIMD get SVE for VL 688
3959 10:06:57.689254 # ok 2229 Set Streaming SVE VL 704
3960 10:06:57.689359 # ok 2230 # SKIP Streaming SVE set SVE get SVE for VL 704
3961 10:06:57.689472 # ok 2231 # SKIP Streaming SVE set SVE get FPSIMD for VL 704
3962 10:06:57.689591 # ok 2232 # SKIP Streaming SVE set FPSIMD get SVE for VL 704
3963 10:06:57.689717 # ok 2233 Set Streaming SVE VL 720
3964 10:06:57.689825 # ok 2234 # SKIP Streaming SVE set SVE get SVE for VL 720
3965 10:06:57.690130 # ok 2235 # SKIP Streaming SVE set SVE get FPSIMD for VL 720
3966 10:06:57.690243 # ok 2236 # SKIP Streaming SVE set FPSIMD get SVE for VL 720
3967 10:06:57.690339 # ok 2237 Set Streaming SVE VL 736
3968 10:06:57.690439 # ok 2238 # SKIP Streaming SVE set SVE get SVE for VL 736
3969 10:06:57.690543 # ok 2239 # SKIP Streaming SVE set SVE get FPSIMD for VL 736
3970 10:06:57.690836 # ok 2240 # SKIP Streaming SVE set FPSIMD get SVE for VL 736
3971 10:06:57.690926 # ok 2241 Set Streaming SVE VL 752
3972 10:06:57.691021 # ok 2242 # SKIP Streaming SVE set SVE get SVE for VL 752
3973 10:06:57.691120 # ok 2243 # SKIP Streaming SVE set SVE get FPSIMD for VL 752
3974 10:06:57.691219 # ok 2244 # SKIP Streaming SVE set FPSIMD get SVE for VL 752
3975 10:06:57.691316 # ok 2245 Set Streaming SVE VL 768
3976 10:06:57.691598 # ok 2246 # SKIP Streaming SVE set SVE get SVE for VL 768
3977 10:06:57.691688 # ok 2247 # SKIP Streaming SVE set SVE get FPSIMD for VL 768
3978 10:06:57.692112 # ok 2248 # SKIP Streaming SVE set FPSIMD get SVE for VL 768
3979 10:06:57.692195 # ok 2249 Set Streaming SVE VL 784
3980 10:06:57.692292 # ok 2250 # SKIP Streaming SVE set SVE get SVE for VL 784
3981 10:06:57.692388 # ok 2251 # SKIP Streaming SVE set SVE get FPSIMD for VL 784
3982 10:06:57.692650 # ok 2252 # SKIP Streaming SVE set FPSIMD get SVE for VL 784
3983 10:06:57.692748 # ok 2253 Set Streaming SVE VL 800
3984 10:06:57.692840 # ok 2254 # SKIP Streaming SVE set SVE get SVE for VL 800
3985 10:06:57.692918 # ok 2255 # SKIP Streaming SVE set SVE get FPSIMD for VL 800
3986 10:06:57.693006 # ok 2256 # SKIP Streaming SVE set FPSIMD get SVE for VL 800
3987 10:06:57.693093 # ok 2257 Set Streaming SVE VL 816
3988 10:06:57.693181 # ok 2258 # SKIP Streaming SVE set SVE get SVE for VL 816
3989 10:06:57.693269 # ok 2259 # SKIP Streaming SVE set SVE get FPSIMD for VL 816
3990 10:06:57.693553 # ok 2260 # SKIP Streaming SVE set FPSIMD get SVE for VL 816
3991 10:06:57.693658 # ok 2261 Set Streaming SVE VL 832
3992 10:06:57.693750 # ok 2262 # SKIP Streaming SVE set SVE get SVE for VL 832
3993 10:06:57.693827 # ok 2263 # SKIP Streaming SVE set SVE get FPSIMD for VL 832
3994 10:06:57.693915 # ok 2264 # SKIP Streaming SVE set FPSIMD get SVE for VL 832
3995 10:06:57.694003 # ok 2265 Set Streaming SVE VL 848
3996 10:06:57.694090 # ok 2266 # SKIP Streaming SVE set SVE get SVE for VL 848
3997 10:06:57.694418 # ok 2267 # SKIP Streaming SVE set SVE get FPSIMD for VL 848
3998 10:06:57.694515 # ok 2268 # SKIP Streaming SVE set FPSIMD get SVE for VL 848
3999 10:06:57.694606 # ok 2269 Set Streaming SVE VL 864
4000 10:06:57.694695 # ok 2270 # SKIP Streaming SVE set SVE get SVE for VL 864
4001 10:06:57.694784 # ok 2271 # SKIP Streaming SVE set SVE get FPSIMD for VL 864
4002 10:06:57.695088 # ok 2272 # SKIP Streaming SVE set FPSIMD get SVE for VL 864
4003 10:06:57.695182 # ok 2273 Set Streaming SVE VL 880
4004 10:06:57.695274 # ok 2274 # SKIP Streaming SVE set SVE get SVE for VL 880
4005 10:06:57.695366 # ok 2275 # SKIP Streaming SVE set SVE get FPSIMD for VL 880
4006 10:06:57.695453 # ok 2276 # SKIP Streaming SVE set FPSIMD get SVE for VL 880
4007 10:06:57.695540 # ok 2277 Set Streaming SVE VL 896
4008 10:06:57.695977 # ok 2278 # SKIP Streaming SVE set SVE get SVE for VL 896
4009 10:06:57.699293 # ok 2279 # SKIP Streaming SVE set SVE get FPSIMD for VL 896
4010 10:06:57.699521 # ok 2280 # SKIP Streaming SVE set FPSIMD get SVE for VL 896
4011 10:06:57.699643 # ok 2281 Set Streaming SVE VL 912
4012 10:06:57.699729 # ok 2282 # SKIP Streaming SVE set SVE get SVE for VL 912
4013 10:06:57.700670 # ok 2283 # SKIP Streaming SVE set SVE get FPSIMD for VL 912
4014 10:06:57.700989 # ok 2284 # SKIP Streaming SVE set FPSIMD get SVE for VL 912
4015 10:06:57.701102 # ok 2285 Set Streaming SVE VL 928
4016 10:06:57.701207 # ok 2286 # SKIP Streaming SVE set SVE get SVE for VL 928
4017 10:06:57.701502 # ok 2287 # SKIP Streaming SVE set SVE get FPSIMD for VL 928
4018 10:06:57.701607 # ok 2288 # SKIP Streaming SVE set FPSIMD get SVE for VL 928
4019 10:06:57.701699 # ok 2289 Set Streaming SVE VL 944
4020 10:06:57.701785 # ok 2290 # SKIP Streaming SVE set SVE get SVE for VL 944
4021 10:06:57.701852 # ok 2291 # SKIP Streaming SVE set SVE get FPSIMD for VL 944
4022 10:06:57.701935 # ok 2292 # SKIP Streaming SVE set FPSIMD get SVE for VL 944
4023 10:06:57.702027 # ok 2293 Set Streaming SVE VL 960
4024 10:06:57.702128 # ok 2294 # SKIP Streaming SVE set SVE get SVE for VL 960
4025 10:06:57.702214 # ok 2295 # SKIP Streaming SVE set SVE get FPSIMD for VL 960
4026 10:06:57.702318 # ok 2296 # SKIP Streaming SVE set FPSIMD get SVE for VL 960
4027 10:06:57.702397 # ok 2297 Set Streaming SVE VL 976
4028 10:06:57.702500 # ok 2298 # SKIP Streaming SVE set SVE get SVE for VL 976
4029 10:06:57.702614 # ok 2299 # SKIP Streaming SVE set SVE get FPSIMD for VL 976
4030 10:06:57.702702 # ok 2300 # SKIP Streaming SVE set FPSIMD get SVE for VL 976
4031 10:06:57.702797 # ok 2301 Set Streaming SVE VL 992
4032 10:06:57.702886 # ok 2302 # SKIP Streaming SVE set SVE get SVE for VL 992
4033 10:06:57.702958 # ok 2303 # SKIP Streaming SVE set SVE get FPSIMD for VL 992
4034 10:06:57.703225 # ok 2304 # SKIP Streaming SVE set FPSIMD get SVE for VL 992
4035 10:06:57.703299 # ok 2305 Set Streaming SVE VL 1008
4036 10:06:57.703386 # ok 2306 # SKIP Streaming SVE set SVE get SVE for VL 1008
4037 10:06:57.703455 # ok 2307 # SKIP Streaming SVE set SVE get FPSIMD for VL 1008
4038 10:06:57.703541 # ok 2308 # SKIP Streaming SVE set FPSIMD get SVE for VL 1008
4039 10:06:57.703642 # ok 2309 Set Streaming SVE VL 1024
4040 10:06:57.703935 # ok 2310 # SKIP Streaming SVE set SVE get SVE for VL 1024
4041 10:06:57.704214 # ok 2311 # SKIP Streaming SVE set SVE get FPSIMD for VL 1024
4042 10:06:57.704329 # ok 2312 # SKIP Streaming SVE set FPSIMD get SVE for VL 1024
4043 10:06:57.704422 # ok 2313 Set Streaming SVE VL 1040
4044 10:06:57.704512 # ok 2314 # SKIP Streaming SVE set SVE get SVE for VL 1040
4045 10:06:57.704600 # ok 2315 # SKIP Streaming SVE set SVE get FPSIMD for VL 1040
4046 10:06:57.704872 # ok 2316 # SKIP Streaming SVE set FPSIMD get SVE for VL 1040
4047 10:06:57.704954 # ok 2317 Set Streaming SVE VL 1056
4048 10:06:57.705042 # ok 2318 # SKIP Streaming SVE set SVE get SVE for VL 1056
4049 10:06:57.705129 # ok 2319 # SKIP Streaming SVE set SVE get FPSIMD for VL 1056
4050 10:06:57.705216 # ok 2320 # SKIP Streaming SVE set FPSIMD get SVE for VL 1056
4051 10:06:57.705302 # ok 2321 Set Streaming SVE VL 1072
4052 10:06:57.705387 # ok 2322 # SKIP Streaming SVE set SVE get SVE for VL 1072
4053 10:06:57.705668 # ok 2323 # SKIP Streaming SVE set SVE get FPSIMD for VL 1072
4054 10:06:57.705749 # ok 2324 # SKIP Streaming SVE set FPSIMD get SVE for VL 1072
4055 10:06:57.705834 # ok 2325 Set Streaming SVE VL 1088
4056 10:06:57.705910 # ok 2326 # SKIP Streaming SVE set SVE get SVE for VL 1088
4057 10:06:57.705997 # ok 2327 # SKIP Streaming SVE set SVE get FPSIMD for VL 1088
4058 10:06:57.706082 # ok 2328 # SKIP Streaming SVE set FPSIMD get SVE for VL 1088
4059 10:06:57.706168 # ok 2329 Set Streaming SVE VL 1104
4060 10:06:57.706454 # ok 2330 # SKIP Streaming SVE set SVE get SVE for VL 1104
4061 10:06:57.706557 # ok 2331 # SKIP Streaming SVE set SVE get FPSIMD for VL 1104
4062 10:06:57.706659 # ok 2332 # SKIP Streaming SVE set FPSIMD get SVE for VL 1104
4063 10:06:57.706747 # ok 2333 Set Streaming SVE VL 1120
4064 10:06:57.706845 # ok 2334 # SKIP Streaming SVE set SVE get SVE for VL 1120
4065 10:06:57.707146 # ok 2335 # SKIP Streaming SVE set SVE get FPSIMD for VL 1120
4066 10:06:57.707237 # ok 2336 # SKIP Streaming SVE set FPSIMD get SVE for VL 1120
4067 10:06:57.707340 # ok 2337 Set Streaming SVE VL 1136
4068 10:06:57.707443 # ok 2338 # SKIP Streaming SVE set SVE get SVE for VL 1136
4069 10:06:57.707726 # ok 2339 # SKIP Streaming SVE set SVE get FPSIMD for VL 1136
4070 10:06:57.708008 # ok 2340 # SKIP Streaming SVE set FPSIMD get SVE for VL 1136
4071 10:06:57.708112 # ok 2341 Set Streaming SVE VL 1152
4072 10:06:57.708393 # ok 2342 # SKIP Streaming SVE set SVE get SVE for VL 1152
4073 10:06:57.708488 # ok 2343 # SKIP Streaming SVE set SVE get FPSIMD for VL 1152
4074 10:06:57.708564 # ok 2344 # SKIP Streaming SVE set FPSIMD get SVE for VL 1152
4075 10:06:57.708642 # ok 2345 Set Streaming SVE VL 1168
4076 10:06:57.708922 # ok 2346 # SKIP Streaming SVE set SVE get SVE for VL 1168
4077 10:06:57.709016 # ok 2347 # SKIP Streaming SVE set SVE get FPSIMD for VL 1168
4078 10:06:57.709098 # ok 2348 # SKIP Streaming SVE set FPSIMD get SVE for VL 1168
4079 10:06:57.709356 # ok 2349 Set Streaming SVE VL 1184
4080 10:06:57.709472 # ok 2350 # SKIP Streaming SVE set SVE get SVE for VL 1184
4081 10:06:57.709593 # ok 2351 # SKIP Streaming SVE set SVE get FPSIMD for VL 1184
4082 10:06:57.709709 # ok 2352 # SKIP Streaming SVE set FPSIMD get SVE for VL 1184
4083 10:06:57.709801 # ok 2353 Set Streaming SVE VL 1200
4084 10:06:57.709910 # ok 2354 # SKIP Streaming SVE set SVE get SVE for VL 1200
4085 10:06:57.710017 # ok 2355 # SKIP Streaming SVE set SVE get FPSIMD for VL 1200
4086 10:06:57.710332 # ok 2356 # SKIP Streaming SVE set FPSIMD get SVE for VL 1200
4087 10:06:57.710434 # ok 2357 Set Streaming SVE VL 1216
4088 10:06:57.710530 # ok 2358 # SKIP Streaming SVE set SVE get SVE for VL 1216
4089 10:06:57.710627 # ok 2359 # SKIP Streaming SVE set SVE get FPSIMD for VL 1216
4090 10:06:57.710706 # ok 2360 # SKIP Streaming SVE set FPSIMD get SVE for VL 1216
4091 10:06:57.710784 # ok 2361 Set Streaming SVE VL 1232
4092 10:06:57.710901 # ok 2362 # SKIP Streaming SVE set SVE get SVE for VL 1232
4093 10:06:57.711009 # ok 2363 # SKIP Streaming SVE set SVE get FPSIMD for VL 1232
4094 10:06:57.711315 # ok 2364 # SKIP Streaming SVE set FPSIMD get SVE for VL 1232
4095 10:06:57.711409 # ok 2365 Set Streaming SVE VL 1248
4096 10:06:57.711532 # ok 2366 # SKIP Streaming SVE set SVE get SVE for VL 1248
4097 10:06:57.711622 # ok 2367 # SKIP Streaming SVE set SVE get FPSIMD for VL 1248
4098 10:06:57.711969 # ok 2368 # SKIP Streaming SVE set FPSIMD get SVE for VL 1248
4099 10:06:57.712269 # ok 2369 Set Streaming SVE VL 1264
4100 10:06:57.712354 # ok 2370 # SKIP Streaming SVE set SVE get SVE for VL 1264
4101 10:06:57.712449 # ok 2371 # SKIP Streaming SVE set SVE get FPSIMD for VL 1264
4102 10:06:57.712529 # ok 2372 # SKIP Streaming SVE set FPSIMD get SVE for VL 1264
4103 10:06:57.712621 # ok 2373 Set Streaming SVE VL 1280
4104 10:06:57.712698 # ok 2374 # SKIP Streaming SVE set SVE get SVE for VL 1280
4105 10:06:57.712792 # ok 2375 # SKIP Streaming SVE set SVE get FPSIMD for VL 1280
4106 10:06:57.712885 # ok 2376 # SKIP Streaming SVE set FPSIMD get SVE for VL 1280
4107 10:06:57.713158 # ok 2377 Set Streaming SVE VL 1296
4108 10:06:57.713241 # ok 2378 # SKIP Streaming SVE set SVE get SVE for VL 1296
4109 10:06:57.713332 # ok 2379 # SKIP Streaming SVE set SVE get FPSIMD for VL 1296
4110 10:06:57.713407 # ok 2380 # SKIP Streaming SVE set FPSIMD get SVE for VL 1296
4111 10:06:57.713496 # ok 2381 Set Streaming SVE VL 1312
4112 10:06:57.713570 # ok 2382 # SKIP Streaming SVE set SVE get SVE for VL 1312
4113 10:06:57.713666 # ok 2383 # SKIP Streaming SVE set SVE get FPSIMD for VL 1312
4114 10:06:57.713763 # ok 2384 # SKIP Streaming SVE set FPSIMD get SVE for VL 1312
4115 10:06:57.713851 # ok 2385 Set Streaming SVE VL 1328
4116 10:06:57.713939 # ok 2386 # SKIP Streaming SVE set SVE get SVE for VL 1328
4117 10:06:57.714229 # ok 2387 # SKIP Streaming SVE set SVE get FPSIMD for VL 1328
4118 10:06:57.714322 # ok 2388 # SKIP Streaming SVE set FPSIMD get SVE for VL 1328
4119 10:06:57.714408 # ok 2389 Set Streaming SVE VL 1344
4120 10:06:57.714646 # ok 2390 # SKIP Streaming SVE set SVE get SVE for VL 1344
4121 10:06:57.714756 # ok 2391 # SKIP Streaming SVE set SVE get FPSIMD for VL 1344
4122 10:06:57.715039 # ok 2392 # SKIP Streaming SVE set FPSIMD get SVE for VL 1344
4123 10:06:57.715140 # ok 2393 Set Streaming SVE VL 1360
4124 10:06:57.715225 # ok 2394 # SKIP Streaming SVE set SVE get SVE for VL 1360
4125 10:06:57.715315 # ok 2395 # SKIP Streaming SVE set SVE get FPSIMD for VL 1360
4126 10:06:57.715576 # ok 2396 # SKIP Streaming SVE set FPSIMD get SVE for VL 1360
4127 10:06:57.715880 # ok 2397 Set Streaming SVE VL 1376
4128 10:06:57.716172 # ok 2398 # SKIP Streaming SVE set SVE get SVE for VL 1376
4129 10:06:57.716259 # ok 2399 # SKIP Streaming SVE set SVE get FPSIMD for VL 1376
4130 10:06:57.716356 # ok 2400 # SKIP Streaming SVE set FPSIMD get SVE for VL 1376
4131 10:06:57.716479 # ok 2401 Set Streaming SVE VL 1392
4132 10:06:57.716593 # ok 2402 # SKIP Streaming SVE set SVE get SVE for VL 1392
4133 10:06:57.716703 # ok 2403 # SKIP Streaming SVE set SVE get FPSIMD for VL 1392
4134 10:06:57.756603 # ok 2404 # SKIP Streaming SVE set FPSIMD get SVE for VL 1392
4135 10:06:57.756784 # ok 2405 Set Streaming SVE VL 1408
4136 10:06:57.756852 # ok 2406 # SKIP Streaming SVE set SVE get SVE for VL 1408
4137 10:06:57.756929 # ok 2407 # SKIP Streaming SVE set SVE get FPSIMD for VL 1408
4138 10:06:57.757008 # ok 2408 # SKIP Streaming SVE set FPSIMD get SVE for VL 1408
4139 10:06:57.757084 # ok 2409 Set Streaming SVE VL 1424
4140 10:06:57.757159 # ok 2410 # SKIP Streaming SVE set SVE get SVE for VL 1424
4141 10:06:57.757232 # ok 2411 # SKIP Streaming SVE set SVE get FPSIMD for VL 1424
4142 10:06:57.757310 # ok 2412 # SKIP Streaming SVE set FPSIMD get SVE for VL 1424
4143 10:06:57.757374 # ok 2413 Set Streaming SVE VL 1440
4144 10:06:57.757445 # ok 2414 # SKIP Streaming SVE set SVE get SVE for VL 1440
4145 10:06:57.757508 # ok 2415 # SKIP Streaming SVE set SVE get FPSIMD for VL 1440
4146 10:06:57.757578 # ok 2416 # SKIP Streaming SVE set FPSIMD get SVE for VL 1440
4147 10:06:57.757656 # ok 2417 Set Streaming SVE VL 1456
4148 10:06:57.757722 # ok 2418 # SKIP Streaming SVE set SVE get SVE for VL 1456
4149 10:06:57.757799 # ok 2419 # SKIP Streaming SVE set SVE get FPSIMD for VL 1456
4150 10:06:57.757876 # ok 2420 # SKIP Streaming SVE set FPSIMD get SVE for VL 1456
4151 10:06:57.757947 # ok 2421 Set Streaming SVE VL 1472
4152 10:06:57.758005 # ok 2422 # SKIP Streaming SVE set SVE get SVE for VL 1472
4153 10:06:57.758068 # ok 2423 # SKIP Streaming SVE set SVE get FPSIMD for VL 1472
4154 10:06:57.758137 # ok 2424 # SKIP Streaming SVE set FPSIMD get SVE for VL 1472
4155 10:06:57.758209 # ok 2425 Set Streaming SVE VL 1488
4156 10:06:57.758281 # ok 2426 # SKIP Streaming SVE set SVE get SVE for VL 1488
4157 10:06:57.758357 # ok 2427 # SKIP Streaming SVE set SVE get FPSIMD for VL 1488
4158 10:06:57.758441 # ok 2428 # SKIP Streaming SVE set FPSIMD get SVE for VL 1488
4159 10:06:57.758521 # ok 2429 Set Streaming SVE VL 1504
4160 10:06:57.758597 # ok 2430 # SKIP Streaming SVE set SVE get SVE for VL 1504
4161 10:06:57.758669 # ok 2431 # SKIP Streaming SVE set SVE get FPSIMD for VL 1504
4162 10:06:57.758738 # ok 2432 # SKIP Streaming SVE set FPSIMD get SVE for VL 1504
4163 10:06:57.758834 # ok 2433 Set Streaming SVE VL 1520
4164 10:06:57.759133 # ok 2434 # SKIP Streaming SVE set SVE get SVE for VL 1520
4165 10:06:57.759233 # ok 2435 # SKIP Streaming SVE set SVE get FPSIMD for VL 1520
4166 10:06:57.759314 # ok 2436 # SKIP Streaming SVE set FPSIMD get SVE for VL 1520
4167 10:06:57.759377 # ok 2437 Set Streaming SVE VL 1536
4168 10:06:57.759451 # ok 2438 # SKIP Streaming SVE set SVE get SVE for VL 1536
4169 10:06:57.759539 # ok 2439 # SKIP Streaming SVE set SVE get FPSIMD for VL 1536
4170 10:06:57.759648 # ok 2440 # SKIP Streaming SVE set FPSIMD get SVE for VL 1536
4171 10:06:57.759730 # ok 2441 Set Streaming SVE VL 1552
4172 10:06:57.759794 # ok 2442 # SKIP Streaming SVE set SVE get SVE for VL 1552
4173 10:06:57.759871 # ok 2443 # SKIP Streaming SVE set SVE get FPSIMD for VL 1552
4174 10:06:57.759950 # ok 2444 # SKIP Streaming SVE set FPSIMD get SVE for VL 1552
4175 10:06:57.760028 # ok 2445 Set Streaming SVE VL 1568
4176 10:06:57.760107 # ok 2446 # SKIP Streaming SVE set SVE get SVE for VL 1568
4177 10:06:57.760184 # ok 2447 # SKIP Streaming SVE set SVE get FPSIMD for VL 1568
4178 10:06:57.760262 # ok 2448 # SKIP Streaming SVE set FPSIMD get SVE for VL 1568
4179 10:06:57.760338 # ok 2449 Set Streaming SVE VL 1584
4180 10:06:57.760419 # ok 2450 # SKIP Streaming SVE set SVE get SVE for VL 1584
4181 10:06:57.760497 # ok 2451 # SKIP Streaming SVE set SVE get FPSIMD for VL 1584
4182 10:06:57.760574 # ok 2452 # SKIP Streaming SVE set FPSIMD get SVE for VL 1584
4183 10:06:57.760653 # ok 2453 Set Streaming SVE VL 1600
4184 10:06:57.760723 # ok 2454 # SKIP Streaming SVE set SVE get SVE for VL 1600
4185 10:06:57.760797 # ok 2455 # SKIP Streaming SVE set SVE get FPSIMD for VL 1600
4186 10:06:57.760868 # ok 2456 # SKIP Streaming SVE set FPSIMD get SVE for VL 1600
4187 10:06:57.760944 # ok 2457 Set Streaming SVE VL 1616
4188 10:06:57.761024 # ok 2458 # SKIP Streaming SVE set SVE get SVE for VL 1616
4189 10:06:57.761099 # ok 2459 # SKIP Streaming SVE set SVE get FPSIMD for VL 1616
4190 10:06:57.761165 # ok 2460 # SKIP Streaming SVE set FPSIMD get SVE for VL 1616
4191 10:06:57.761247 # ok 2461 Set Streaming SVE VL 1632
4192 10:06:57.761314 # ok 2462 # SKIP Streaming SVE set SVE get SVE for VL 1632
4193 10:06:57.761385 # ok 2463 # SKIP Streaming SVE set SVE get FPSIMD for VL 1632
4194 10:06:57.761473 # ok 2464 # SKIP Streaming SVE set FPSIMD get SVE for VL 1632
4195 10:06:57.761551 # ok 2465 Set Streaming SVE VL 1648
4196 10:06:57.761631 # ok 2466 # SKIP Streaming SVE set SVE get SVE for VL 1648
4197 10:06:57.761722 # ok 2467 # SKIP Streaming SVE set SVE get FPSIMD for VL 1648
4198 10:06:57.761796 # ok 2468 # SKIP Streaming SVE set FPSIMD get SVE for VL 1648
4199 10:06:57.762089 # ok 2469 Set Streaming SVE VL 1664
4200 10:06:57.762170 # ok 2470 # SKIP Streaming SVE set SVE get SVE for VL 1664
4201 10:06:57.762247 # ok 2471 # SKIP Streaming SVE set SVE get FPSIMD for VL 1664
4202 10:06:57.762317 # ok 2472 # SKIP Streaming SVE set FPSIMD get SVE for VL 1664
4203 10:06:57.762389 # ok 2473 Set Streaming SVE VL 1680
4204 10:06:57.762469 # ok 2474 # SKIP Streaming SVE set SVE get SVE for VL 1680
4205 10:06:57.762538 # ok 2475 # SKIP Streaming SVE set SVE get FPSIMD for VL 1680
4206 10:06:57.762616 # ok 2476 # SKIP Streaming SVE set FPSIMD get SVE for VL 1680
4207 10:06:57.762687 # ok 2477 Set Streaming SVE VL 1696
4208 10:06:57.762761 # ok 2478 # SKIP Streaming SVE set SVE get SVE for VL 1696
4209 10:06:57.762840 # ok 2479 # SKIP Streaming SVE set SVE get FPSIMD for VL 1696
4210 10:06:57.762919 # ok 2480 # SKIP Streaming SVE set FPSIMD get SVE for VL 1696
4211 10:06:57.762998 # ok 2481 Set Streaming SVE VL 1712
4212 10:06:57.763076 # ok 2482 # SKIP Streaming SVE set SVE get SVE for VL 1712
4213 10:06:57.763148 # ok 2483 # SKIP Streaming SVE set SVE get FPSIMD for VL 1712
4214 10:06:57.763230 # ok 2484 # SKIP Streaming SVE set FPSIMD get SVE for VL 1712
4215 10:06:57.763316 # ok 2485 Set Streaming SVE VL 1728
4216 10:06:57.763401 # ok 2486 # SKIP Streaming SVE set SVE get SVE for VL 1728
4217 10:06:57.763470 # ok 2487 # SKIP Streaming SVE set SVE get FPSIMD for VL 1728
4218 10:06:57.763563 # ok 2488 # SKIP Streaming SVE set FPSIMD get SVE for VL 1728
4219 10:06:57.763660 # ok 2489 Set Streaming SVE VL 1744
4220 10:06:57.763728 # ok 2490 # SKIP Streaming SVE set SVE get SVE for VL 1744
4221 10:06:57.763802 # ok 2491 # SKIP Streaming SVE set SVE get FPSIMD for VL 1744
4222 10:06:57.763885 # ok 2492 # SKIP Streaming SVE set FPSIMD get SVE for VL 1744
4223 10:06:57.763958 # ok 2493 Set Streaming SVE VL 1760
4224 10:06:57.764030 # ok 2494 # SKIP Streaming SVE set SVE get SVE for VL 1760
4225 10:06:57.764113 # ok 2495 # SKIP Streaming SVE set SVE get FPSIMD for VL 1760
4226 10:06:57.764201 # ok 2496 # SKIP Streaming SVE set FPSIMD get SVE for VL 1760
4227 10:06:57.764274 # ok 2497 Set Streaming SVE VL 1776
4228 10:06:57.764368 # ok 2498 # SKIP Streaming SVE set SVE get SVE for VL 1776
4229 10:06:57.764475 # ok 2499 # SKIP Streaming SVE set SVE get FPSIMD for VL 1776
4230 10:06:57.764561 # ok 2500 # SKIP Streaming SVE set FPSIMD get SVE for VL 1776
4231 10:06:57.764635 # ok 2501 Set Streaming SVE VL 1792
4232 10:06:57.764715 # ok 2502 # SKIP Streaming SVE set SVE get SVE for VL 1792
4233 10:06:57.764789 # ok 2503 # SKIP Streaming SVE set SVE get FPSIMD for VL 1792
4234 10:06:57.765089 # ok 2504 # SKIP Streaming SVE set FPSIMD get SVE for VL 1792
4235 10:06:57.765185 # ok 2505 Set Streaming SVE VL 1808
4236 10:06:57.765257 # ok 2506 # SKIP Streaming SVE set SVE get SVE for VL 1808
4237 10:06:57.765344 # ok 2507 # SKIP Streaming SVE set SVE get FPSIMD for VL 1808
4238 10:06:57.765419 # ok 2508 # SKIP Streaming SVE set FPSIMD get SVE for VL 1808
4239 10:06:57.765512 # ok 2509 Set Streaming SVE VL 1824
4240 10:06:57.765593 # ok 2510 # SKIP Streaming SVE set SVE get SVE for VL 1824
4241 10:06:57.765690 # ok 2511 # SKIP Streaming SVE set SVE get FPSIMD for VL 1824
4242 10:06:57.765774 # ok 2512 # SKIP Streaming SVE set FPSIMD get SVE for VL 1824
4243 10:06:57.765849 # ok 2513 Set Streaming SVE VL 1840
4244 10:06:57.765921 # ok 2514 # SKIP Streaming SVE set SVE get SVE for VL 1840
4245 10:06:57.765989 # ok 2515 # SKIP Streaming SVE set SVE get FPSIMD for VL 1840
4246 10:06:57.766050 # ok 2516 # SKIP Streaming SVE set FPSIMD get SVE for VL 1840
4247 10:06:57.766109 # ok 2517 Set Streaming SVE VL 1856
4248 10:06:57.766168 # ok 2518 # SKIP Streaming SVE set SVE get SVE for VL 1856
4249 10:06:57.766227 # ok 2519 # SKIP Streaming SVE set SVE get FPSIMD for VL 1856
4250 10:06:57.766286 # ok 2520 # SKIP Streaming SVE set FPSIMD get SVE for VL 1856
4251 10:06:57.766344 # ok 2521 Set Streaming SVE VL 1872
4252 10:06:57.766427 # ok 2522 # SKIP Streaming SVE set SVE get SVE for VL 1872
4253 10:06:57.766514 # ok 2523 # SKIP Streaming SVE set SVE get FPSIMD for VL 1872
4254 10:06:57.766604 # ok 2524 # SKIP Streaming SVE set FPSIMD get SVE for VL 1872
4255 10:06:57.766676 # ok 2525 Set Streaming SVE VL 1888
4256 10:06:57.766756 # ok 2526 # SKIP Streaming SVE set SVE get SVE for VL 1888
4257 10:06:57.766828 # ok 2527 # SKIP Streaming SVE set SVE get FPSIMD for VL 1888
4258 10:06:57.766891 # ok 2528 # SKIP Streaming SVE set FPSIMD get SVE for VL 1888
4259 10:06:57.766953 # ok 2529 Set Streaming SVE VL 1904
4260 10:06:57.767015 # ok 2530 # SKIP Streaming SVE set SVE get SVE for VL 1904
4261 10:06:57.767077 # ok 2531 # SKIP Streaming SVE set SVE get FPSIMD for VL 1904
4262 10:06:57.767138 # ok 2532 # SKIP Streaming SVE set FPSIMD get SVE for VL 1904
4263 10:06:57.767198 # ok 2533 Set Streaming SVE VL 1920
4264 10:06:57.767262 # ok 2534 # SKIP Streaming SVE set SVE get SVE for VL 1920
4265 10:06:57.767327 # ok 2535 # SKIP Streaming SVE set SVE get FPSIMD for VL 1920
4266 10:06:57.767388 # ok 2536 # SKIP Streaming SVE set FPSIMD get SVE for VL 1920
4267 10:06:57.767487 # ok 2537 Set Streaming SVE VL 1936
4268 10:06:57.767563 # ok 2538 # SKIP Streaming SVE set SVE get SVE for VL 1936
4269 10:06:57.767821 # ok 2539 # SKIP Streaming SVE set SVE get FPSIMD for VL 1936
4270 10:06:57.767899 # ok 2540 # SKIP Streaming SVE set FPSIMD get SVE for VL 1936
4271 10:06:57.767962 # ok 2541 Set Streaming SVE VL 1952
4272 10:06:57.768049 # ok 2542 # SKIP Streaming SVE set SVE get SVE for VL 1952
4273 10:06:57.768114 # ok 2543 # SKIP Streaming SVE set SVE get FPSIMD for VL 1952
4274 10:06:57.768175 # ok 2544 # SKIP Streaming SVE set FPSIMD get SVE for VL 1952
4275 10:06:57.768234 # ok 2545 Set Streaming SVE VL 1968
4276 10:06:57.768292 # ok 2546 # SKIP Streaming SVE set SVE get SVE for VL 1968
4277 10:06:57.768351 # ok 2547 # SKIP Streaming SVE set SVE get FPSIMD for VL 1968
4278 10:06:57.768410 # ok 2548 # SKIP Streaming SVE set FPSIMD get SVE for VL 1968
4279 10:06:57.768471 # ok 2549 Set Streaming SVE VL 1984
4280 10:06:57.768530 # ok 2550 # SKIP Streaming SVE set SVE get SVE for VL 1984
4281 10:06:57.768589 # ok 2551 # SKIP Streaming SVE set SVE get FPSIMD for VL 1984
4282 10:06:57.768647 # ok 2552 # SKIP Streaming SVE set FPSIMD get SVE for VL 1984
4283 10:06:57.768706 # ok 2553 Set Streaming SVE VL 2000
4284 10:06:57.768764 # ok 2554 # SKIP Streaming SVE set SVE get SVE for VL 2000
4285 10:06:57.768823 # ok 2555 # SKIP Streaming SVE set SVE get FPSIMD for VL 2000
4286 10:06:57.768882 # ok 2556 # SKIP Streaming SVE set FPSIMD get SVE for VL 2000
4287 10:06:57.768941 # ok 2557 Set Streaming SVE VL 2016
4288 10:06:57.769000 # ok 2558 # SKIP Streaming SVE set SVE get SVE for VL 2016
4289 10:06:57.769058 # ok 2559 # SKIP Streaming SVE set SVE get FPSIMD for VL 2016
4290 10:06:57.769156 # ok 2560 # SKIP Streaming SVE set FPSIMD get SVE for VL 2016
4291 10:06:57.769240 # ok 2561 Set Streaming SVE VL 2032
4292 10:06:57.769323 # ok 2562 # SKIP Streaming SVE set SVE get SVE for VL 2032
4293 10:06:57.769402 # ok 2563 # SKIP Streaming SVE set SVE get FPSIMD for VL 2032
4294 10:06:57.769485 # ok 2564 # SKIP Streaming SVE set FPSIMD get SVE for VL 2032
4295 10:06:57.769585 # ok 2565 Set Streaming SVE VL 2048
4296 10:06:57.769680 # ok 2566 # SKIP Streaming SVE set SVE get SVE for VL 2048
4297 10:06:57.769774 # ok 2567 # SKIP Streaming SVE set SVE get FPSIMD for VL 2048
4298 10:06:57.769861 # ok 2568 # SKIP Streaming SVE set FPSIMD get SVE for VL 2048
4299 10:06:57.769928 # ok 2569 Set Streaming SVE VL 2064
4300 10:06:57.769988 # ok 2570 # SKIP Streaming SVE set SVE get SVE for VL 2064
4301 10:06:57.770047 # ok 2571 # SKIP Streaming SVE set SVE get FPSIMD for VL 2064
4302 10:06:57.770105 # ok 2572 # SKIP Streaming SVE set FPSIMD get SVE for VL 2064
4303 10:06:57.770163 # ok 2573 Set Streaming SVE VL 2080
4304 10:06:57.770221 # ok 2574 # SKIP Streaming SVE set SVE get SVE for VL 2080
4305 10:06:57.770469 # ok 2575 # SKIP Streaming SVE set SVE get FPSIMD for VL 2080
4306 10:06:57.770534 # ok 2576 # SKIP Streaming SVE set FPSIMD get SVE for VL 2080
4307 10:06:57.770594 # ok 2577 Set Streaming SVE VL 2096
4308 10:06:57.770653 # ok 2578 # SKIP Streaming SVE set SVE get SVE for VL 2096
4309 10:06:57.770712 # ok 2579 # SKIP Streaming SVE set SVE get FPSIMD for VL 2096
4310 10:06:57.770771 # ok 2580 # SKIP Streaming SVE set FPSIMD get SVE for VL 2096
4311 10:06:57.770829 # ok 2581 Set Streaming SVE VL 2112
4312 10:06:57.770887 # ok 2582 # SKIP Streaming SVE set SVE get SVE for VL 2112
4313 10:06:57.770945 # ok 2583 # SKIP Streaming SVE set SVE get FPSIMD for VL 2112
4314 10:06:57.771004 # ok 2584 # SKIP Streaming SVE set FPSIMD get SVE for VL 2112
4315 10:06:57.771062 # ok 2585 Set Streaming SVE VL 2128
4316 10:06:57.771121 # ok 2586 # SKIP Streaming SVE set SVE get SVE for VL 2128
4317 10:06:57.771179 # ok 2587 # SKIP Streaming SVE set SVE get FPSIMD for VL 2128
4318 10:06:57.771238 # ok 2588 # SKIP Streaming SVE set FPSIMD get SVE for VL 2128
4319 10:06:57.771297 # ok 2589 Set Streaming SVE VL 2144
4320 10:06:57.771355 # ok 2590 # SKIP Streaming SVE set SVE get SVE for VL 2144
4321 10:06:57.771413 # ok 2591 # SKIP Streaming SVE set SVE get FPSIMD for VL 2144
4322 10:06:57.771474 # ok 2592 # SKIP Streaming SVE set FPSIMD get SVE for VL 2144
4323 10:06:57.771557 # ok 2593 Set Streaming SVE VL 2160
4324 10:06:57.771628 # ok 2594 # SKIP Streaming SVE set SVE get SVE for VL 2160
4325 10:06:57.771689 # ok 2595 # SKIP Streaming SVE set SVE get FPSIMD for VL 2160
4326 10:06:57.771749 # ok 2596 # SKIP Streaming SVE set FPSIMD get SVE for VL 2160
4327 10:06:57.771809 # ok 2597 Set Streaming SVE VL 2176
4328 10:06:57.771867 # ok 2598 # SKIP Streaming SVE set SVE get SVE for VL 2176
4329 10:06:57.771926 # ok 2599 # SKIP Streaming SVE set SVE get FPSIMD for VL 2176
4330 10:06:57.771985 # ok 2600 # SKIP Streaming SVE set FPSIMD get SVE for VL 2176
4331 10:06:57.772044 # ok 2601 Set Streaming SVE VL 2192
4332 10:06:57.772107 # ok 2602 # SKIP Streaming SVE set SVE get SVE for VL 2192
4333 10:06:57.772168 # ok 2603 # SKIP Streaming SVE set SVE get FPSIMD for VL 2192
4334 10:06:57.772227 # ok 2604 # SKIP Streaming SVE set FPSIMD get SVE for VL 2192
4335 10:06:57.772286 # ok 2605 Set Streaming SVE VL 2208
4336 10:06:57.772345 # ok 2606 # SKIP Streaming SVE set SVE get SVE for VL 2208
4337 10:06:57.772403 # ok 2607 # SKIP Streaming SVE set SVE get FPSIMD for VL 2208
4338 10:06:57.772461 # ok 2608 # SKIP Streaming SVE set FPSIMD get SVE for VL 2208
4339 10:06:57.772520 # ok 2609 Set Streaming SVE VL 2224
4340 10:06:57.772779 # ok 2610 # SKIP Streaming SVE set SVE get SVE for VL 2224
4341 10:06:57.772845 # ok 2611 # SKIP Streaming SVE set SVE get FPSIMD for VL 2224
4342 10:06:57.772939 # ok 2612 # SKIP Streaming SVE set FPSIMD get SVE for VL 2224
4343 10:06:57.773014 # ok 2613 Set Streaming SVE VL 2240
4344 10:06:57.773107 # ok 2614 # SKIP Streaming SVE set SVE get SVE for VL 2240
4345 10:06:57.773186 # ok 2615 # SKIP Streaming SVE set SVE get FPSIMD for VL 2240
4346 10:06:57.773249 # ok 2616 # SKIP Streaming SVE set FPSIMD get SVE for VL 2240
4347 10:06:57.773342 # ok 2617 Set Streaming SVE VL 2256
4348 10:06:57.773431 # ok 2618 # SKIP Streaming SVE set SVE get SVE for VL 2256
4349 10:06:57.773513 # ok 2619 # SKIP Streaming SVE set SVE get FPSIMD for VL 2256
4350 10:06:57.773597 # ok 2620 # SKIP Streaming SVE set FPSIMD get SVE for VL 2256
4351 10:06:57.773677 # ok 2621 Set Streaming SVE VL 2272
4352 10:06:57.773740 # ok 2622 # SKIP Streaming SVE set SVE get SVE for VL 2272
4353 10:06:57.773801 # ok 2623 # SKIP Streaming SVE set SVE get FPSIMD for VL 2272
4354 10:06:57.773871 # ok 2624 # SKIP Streaming SVE set FPSIMD get SVE for VL 2272
4355 10:06:57.773967 # ok 2625 Set Streaming SVE VL 2288
4356 10:06:57.774052 # ok 2626 # SKIP Streaming SVE set SVE get SVE for VL 2288
4357 10:06:57.774150 # ok 2627 # SKIP Streaming SVE set SVE get FPSIMD for VL 2288
4358 10:06:57.774243 # ok 2628 # SKIP Streaming SVE set FPSIMD get SVE for VL 2288
4359 10:06:57.774319 # ok 2629 Set Streaming SVE VL 2304
4360 10:06:57.774391 # ok 2630 # SKIP Streaming SVE set SVE get SVE for VL 2304
4361 10:06:57.774469 # ok 2631 # SKIP Streaming SVE set SVE get FPSIMD for VL 2304
4362 10:06:57.774542 # ok 2632 # SKIP Streaming SVE set FPSIMD get SVE for VL 2304
4363 10:06:57.774626 # ok 2633 Set Streaming SVE VL 2320
4364 10:06:57.774710 # ok 2634 # SKIP Streaming SVE set SVE get SVE for VL 2320
4365 10:06:57.774771 # ok 2635 # SKIP Streaming SVE set SVE get FPSIMD for VL 2320
4366 10:06:57.774837 # ok 2636 # SKIP Streaming SVE set FPSIMD get SVE for VL 2320
4367 10:06:57.774897 # ok 2637 Set Streaming SVE VL 2336
4368 10:06:57.774954 # ok 2638 # SKIP Streaming SVE set SVE get SVE for VL 2336
4369 10:06:57.775011 # ok 2639 # SKIP Streaming SVE set SVE get FPSIMD for VL 2336
4370 10:06:57.775079 # ok 2640 # SKIP Streaming SVE set FPSIMD get SVE for VL 2336
4371 10:06:57.775176 # ok 2641 Set Streaming SVE VL 2352
4372 10:06:57.775247 # ok 2642 # SKIP Streaming SVE set SVE get SVE for VL 2352
4373 10:06:57.775318 # ok 2643 # SKIP Streaming SVE set SVE get FPSIMD for VL 2352
4374 10:06:57.775419 # ok 2644 # SKIP Streaming SVE set FPSIMD get SVE for VL 2352
4375 10:06:57.775725 # ok 2645 Set Streaming SVE VL 2368
4376 10:06:57.775809 # ok 2646 # SKIP Streaming SVE set SVE get SVE for VL 2368
4377 10:06:57.775875 # ok 2647 # SKIP Streaming SVE set SVE get FPSIMD for VL 2368
4378 10:06:57.775936 # ok 2648 # SKIP Streaming SVE set FPSIMD get SVE for VL 2368
4379 10:06:57.775997 # ok 2649 Set Streaming SVE VL 2384
4380 10:06:57.776057 # ok 2650 # SKIP Streaming SVE set SVE get SVE for VL 2384
4381 10:06:57.776165 # ok 2651 # SKIP Streaming SVE set SVE get FPSIMD for VL 2384
4382 10:06:57.776263 # ok 2652 # SKIP Streaming SVE set FPSIMD get SVE for VL 2384
4383 10:06:57.776357 # ok 2653 Set Streaming SVE VL 2400
4384 10:06:57.776446 # ok 2654 # SKIP Streaming SVE set SVE get SVE for VL 2400
4385 10:06:57.776517 # ok 2655 # SKIP Streaming SVE set SVE get FPSIMD for VL 2400
4386 10:06:57.776606 # ok 2656 # SKIP Streaming SVE set FPSIMD get SVE for VL 2400
4387 10:06:57.776699 # ok 2657 Set Streaming SVE VL 2416
4388 10:06:57.776776 # ok 2658 # SKIP Streaming SVE set SVE get SVE for VL 2416
4389 10:06:57.776875 # ok 2659 # SKIP Streaming SVE set SVE get FPSIMD for VL 2416
4390 10:06:57.776970 # ok 2660 # SKIP Streaming SVE set FPSIMD get SVE for VL 2416
4391 10:06:57.777067 # ok 2661 Set Streaming SVE VL 2432
4392 10:06:57.777157 # ok 2662 # SKIP Streaming SVE set SVE get SVE for VL 2432
4393 10:06:57.777232 # ok 2663 # SKIP Streaming SVE set SVE get FPSIMD for VL 2432
4394 10:06:57.777307 # ok 2664 # SKIP Streaming SVE set FPSIMD get SVE for VL 2432
4395 10:06:57.777380 # ok 2665 Set Streaming SVE VL 2448
4396 10:06:57.777454 # ok 2666 # SKIP Streaming SVE set SVE get SVE for VL 2448
4397 10:06:57.777535 # ok 2667 # SKIP Streaming SVE set SVE get FPSIMD for VL 2448
4398 10:06:57.777609 # ok 2668 # SKIP Streaming SVE set FPSIMD get SVE for VL 2448
4399 10:06:57.777733 # ok 2669 Set Streaming SVE VL 2464
4400 10:06:57.777831 # ok 2670 # SKIP Streaming SVE set SVE get SVE for VL 2464
4401 10:06:57.777928 # ok 2671 # SKIP Streaming SVE set SVE get FPSIMD for VL 2464
4402 10:06:57.778023 # ok 2672 # SKIP Streaming SVE set FPSIMD get SVE for VL 2464
4403 10:06:57.778121 # ok 2673 Set Streaming SVE VL 2480
4404 10:06:57.778215 # ok 2674 # SKIP Streaming SVE set SVE get SVE for VL 2480
4405 10:06:57.778313 # ok 2675 # SKIP Streaming SVE set SVE get FPSIMD for VL 2480
4406 10:06:57.778409 # ok 2676 # SKIP Streaming SVE set FPSIMD get SVE for VL 2480
4407 10:06:57.778499 # ok 2677 Set Streaming SVE VL 2496
4408 10:06:57.778575 # ok 2678 # SKIP Streaming SVE set SVE get SVE for VL 2496
4409 10:06:57.778650 # ok 2679 # SKIP Streaming SVE set SVE get FPSIMD for VL 2496
4410 10:06:57.778933 # ok 2680 # SKIP Streaming SVE set FPSIMD get SVE for VL 2496
4411 10:06:57.779024 # ok 2681 Set Streaming SVE VL 2512
4412 10:06:57.779100 # ok 2682 # SKIP Streaming SVE set SVE get SVE for VL 2512
4413 10:06:57.779182 # ok 2683 # SKIP Streaming SVE set SVE get FPSIMD for VL 2512
4414 10:06:57.779261 # ok 2684 # SKIP Streaming SVE set FPSIMD get SVE for VL 2512
4415 10:06:57.779366 # ok 2685 Set Streaming SVE VL 2528
4416 10:06:57.779477 # ok 2686 # SKIP Streaming SVE set SVE get SVE for VL 2528
4417 10:06:57.779585 # ok 2687 # SKIP Streaming SVE set SVE get FPSIMD for VL 2528
4418 10:06:57.779684 # ok 2688 # SKIP Streaming SVE set FPSIMD get SVE for VL 2528
4419 10:06:57.779758 # ok 2689 Set Streaming SVE VL 2544
4420 10:06:57.779828 # ok 2690 # SKIP Streaming SVE set SVE get SVE for VL 2544
4421 10:06:57.779909 # ok 2691 # SKIP Streaming SVE set SVE get FPSIMD for VL 2544
4422 10:06:57.779990 # ok 2692 # SKIP Streaming SVE set FPSIMD get SVE for VL 2544
4423 10:06:57.780073 # ok 2693 Set Streaming SVE VL 2560
4424 10:06:57.780148 # ok 2694 # SKIP Streaming SVE set SVE get SVE for VL 2560
4425 10:06:57.780226 # ok 2695 # SKIP Streaming SVE set SVE get FPSIMD for VL 2560
4426 10:06:57.780305 # ok 2696 # SKIP Streaming SVE set FPSIMD get SVE for VL 2560
4427 10:06:57.780389 # ok 2697 Set Streaming SVE VL 2576
4428 10:06:57.780457 # ok 2698 # SKIP Streaming SVE set SVE get SVE for VL 2576
4429 10:06:57.780533 # ok 2699 # SKIP Streaming SVE set SVE get FPSIMD for VL 2576
4430 10:06:57.780604 # ok 2700 # SKIP Streaming SVE set FPSIMD get SVE for VL 2576
4431 10:06:57.780685 # ok 2701 Set Streaming SVE VL 2592
4432 10:06:57.780763 # ok 2702 # SKIP Streaming SVE set SVE get SVE for VL 2592
4433 10:06:57.780858 # ok 2703 # SKIP Streaming SVE set SVE get FPSIMD for VL 2592
4434 10:06:57.780940 # ok 2704 # SKIP Streaming SVE set FPSIMD get SVE for VL 2592
4435 10:06:57.781005 # ok 2705 Set Streaming SVE VL 2608
4436 10:06:57.781077 # ok 2706 # SKIP Streaming SVE set SVE get SVE for VL 2608
4437 10:06:57.781154 # ok 2707 # SKIP Streaming SVE set SVE get FPSIMD for VL 2608
4438 10:06:57.781220 # ok 2708 # SKIP Streaming SVE set FPSIMD get SVE for VL 2608
4439 10:06:57.781293 # ok 2709 Set Streaming SVE VL 2624
4440 10:06:57.781361 # ok 2710 # SKIP Streaming SVE set SVE get SVE for VL 2624
4441 10:06:57.781422 # ok 2711 # SKIP Streaming SVE set SVE get FPSIMD for VL 2624
4442 10:06:57.781484 # ok 2712 # SKIP Streaming SVE set FPSIMD get SVE for VL 2624
4443 10:06:57.781543 # ok 2713 Set Streaming SVE VL 2640
4444 10:06:57.781606 # ok 2714 # SKIP Streaming SVE set SVE get SVE for VL 2640
4445 10:06:57.781685 # ok 2715 # SKIP Streaming SVE set SVE get FPSIMD for VL 2640
4446 10:06:57.782218 # ok 2716 # SKIP Streaming SVE set FPSIMD get SVE for VL 2640
4447 10:06:57.782326 # ok 2717 Set Streaming SVE VL 2656
4448 10:06:57.782420 # ok 2718 # SKIP Streaming SVE set SVE get SVE for VL 2656
4449 10:06:57.782496 # ok 2719 # SKIP Streaming SVE set SVE get FPSIMD for VL 2656
4450 10:06:57.782577 # ok 2720 # SKIP Streaming SVE set FPSIMD get SVE for VL 2656
4451 10:06:57.782652 # ok 2721 Set Streaming SVE VL 2672
4452 10:06:57.782727 # ok 2722 # SKIP Streaming SVE set SVE get SVE for VL 2672
4453 10:06:57.782799 # ok 2723 # SKIP Streaming SVE set SVE get FPSIMD for VL 2672
4454 10:06:57.782866 # ok 2724 # SKIP Streaming SVE set FPSIMD get SVE for VL 2672
4455 10:06:57.782931 # ok 2725 Set Streaming SVE VL 2688
4456 10:06:57.783003 # ok 2726 # SKIP Streaming SVE set SVE get SVE for VL 2688
4457 10:06:57.783063 # ok 2727 # SKIP Streaming SVE set SVE get FPSIMD for VL 2688
4458 10:06:57.783121 # ok 2728 # SKIP Streaming SVE set FPSIMD get SVE for VL 2688
4459 10:06:57.783196 # ok 2729 Set Streaming SVE VL 2704
4460 10:06:57.783268 # ok 2730 # SKIP Streaming SVE set SVE get SVE for VL 2704
4461 10:06:57.783366 # ok 2731 # SKIP Streaming SVE set SVE get FPSIMD for VL 2704
4462 10:06:57.783462 # ok 2732 # SKIP Streaming SVE set FPSIMD get SVE for VL 2704
4463 10:06:57.783543 # ok 2733 Set Streaming SVE VL 2720
4464 10:06:57.783616 # ok 2734 # SKIP Streaming SVE set SVE get SVE for VL 2720
4465 10:06:57.783681 # ok 2735 # SKIP Streaming SVE set SVE get FPSIMD for VL 2720
4466 10:06:57.783759 # ok 2736 # SKIP Streaming SVE set FPSIMD get SVE for VL 2720
4467 10:06:57.783843 # ok 2737 Set Streaming SVE VL 2736
4468 10:06:57.783923 # ok 2738 # SKIP Streaming SVE set SVE get SVE for VL 2736
4469 10:06:57.783997 # ok 2739 # SKIP Streaming SVE set SVE get FPSIMD for VL 2736
4470 10:06:57.784072 # ok 2740 # SKIP Streaming SVE set FPSIMD get SVE for VL 2736
4471 10:06:57.784136 # ok 2741 Set Streaming SVE VL 2752
4472 10:06:57.784206 # ok 2742 # SKIP Streaming SVE set SVE get SVE for VL 2752
4473 10:06:57.784270 # ok 2743 # SKIP Streaming SVE set SVE get FPSIMD for VL 2752
4474 10:06:57.784330 # ok 2744 # SKIP Streaming SVE set FPSIMD get SVE for VL 2752
4475 10:06:57.784393 # ok 2745 Set Streaming SVE VL 2768
4476 10:06:57.784456 # ok 2746 # SKIP Streaming SVE set SVE get SVE for VL 2768
4477 10:06:57.784530 # ok 2747 # SKIP Streaming SVE set SVE get FPSIMD for VL 2768
4478 10:06:57.784608 # ok 2748 # SKIP Streaming SVE set FPSIMD get SVE for VL 2768
4479 10:06:57.784687 # ok 2749 Set Streaming SVE VL 2784
4480 10:06:57.784753 # ok 2750 # SKIP Streaming SVE set SVE get SVE for VL 2784
4481 10:06:57.785029 # ok 2751 # SKIP Streaming SVE set SVE get FPSIMD for VL 2784
4482 10:06:57.785133 # ok 2752 # SKIP Streaming SVE set FPSIMD get SVE for VL 2784
4483 10:06:57.785240 # ok 2753 Set Streaming SVE VL 2800
4484 10:06:57.785346 # ok 2754 # SKIP Streaming SVE set SVE get SVE for VL 2800
4485 10:06:57.785452 # ok 2755 # SKIP Streaming SVE set SVE get FPSIMD for VL 2800
4486 10:06:57.785557 # ok 2756 # SKIP Streaming SVE set FPSIMD get SVE for VL 2800
4487 10:06:57.785673 # ok 2757 Set Streaming SVE VL 2816
4488 10:06:57.785768 # ok 2758 # SKIP Streaming SVE set SVE get SVE for VL 2816
4489 10:06:57.785843 # ok 2759 # SKIP Streaming SVE set SVE get FPSIMD for VL 2816
4490 10:06:57.785914 # ok 2760 # SKIP Streaming SVE set FPSIMD get SVE for VL 2816
4491 10:06:57.785973 # ok 2761 Set Streaming SVE VL 2832
4492 10:06:57.786045 # ok 2762 # SKIP Streaming SVE set SVE get SVE for VL 2832
4493 10:06:57.786119 # ok 2763 # SKIP Streaming SVE set SVE get FPSIMD for VL 2832
4494 10:06:57.786199 # ok 2764 # SKIP Streaming SVE set FPSIMD get SVE for VL 2832
4495 10:06:57.786280 # ok 2765 Set Streaming SVE VL 2848
4496 10:06:57.786344 # ok 2766 # SKIP Streaming SVE set SVE get SVE for VL 2848
4497 10:06:57.786407 # ok 2767 # SKIP Streaming SVE set SVE get FPSIMD for VL 2848
4498 10:06:57.786477 # ok 2768 # SKIP Streaming SVE set FPSIMD get SVE for VL 2848
4499 10:06:57.786565 # ok 2769 Set Streaming SVE VL 2864
4500 10:06:57.786644 # ok 2770 # SKIP Streaming SVE set SVE get SVE for VL 2864
4501 10:06:57.786720 # ok 2771 # SKIP Streaming SVE set SVE get FPSIMD for VL 2864
4502 10:06:57.786817 # ok 2772 # SKIP Streaming SVE set FPSIMD get SVE for VL 2864
4503 10:06:57.786913 # ok 2773 Set Streaming SVE VL 2880
4504 10:06:57.786996 # ok 2774 # SKIP Streaming SVE set SVE get SVE for VL 2880
4505 10:06:57.787078 # ok 2775 # SKIP Streaming SVE set SVE get FPSIMD for VL 2880
4506 10:06:57.787165 # ok 2776 # SKIP Streaming SVE set FPSIMD get SVE for VL 2880
4507 10:06:57.787242 # ok 2777 Set Streaming SVE VL 2896
4508 10:06:57.787323 # ok 2778 # SKIP Streaming SVE set SVE get SVE for VL 2896
4509 10:06:57.787418 # ok 2779 # SKIP Streaming SVE set SVE get FPSIMD for VL 2896
4510 10:06:57.787528 # ok 2780 # SKIP Streaming SVE set FPSIMD get SVE for VL 2896
4511 10:06:57.787627 # ok 2781 Set Streaming SVE VL 2912
4512 10:06:57.787708 # ok 2782 # SKIP Streaming SVE set SVE get SVE for VL 2912
4513 10:06:57.787794 # ok 2783 # SKIP Streaming SVE set SVE get FPSIMD for VL 2912
4514 10:06:57.787901 # ok 2784 # SKIP Streaming SVE set FPSIMD get SVE for VL 2912
4515 10:06:57.788007 # ok 2785 Set Streaming SVE VL 2928
4516 10:06:57.788342 # ok 2786 # SKIP Streaming SVE set SVE get SVE for VL 2928
4517 10:06:57.788435 # ok 2787 # SKIP Streaming SVE set SVE get FPSIMD for VL 2928
4518 10:06:57.788539 # ok 2788 # SKIP Streaming SVE set FPSIMD get SVE for VL 2928
4519 10:06:57.788638 # ok 2789 Set Streaming SVE VL 2944
4520 10:06:57.788725 # ok 2790 # SKIP Streaming SVE set SVE get SVE for VL 2944
4521 10:06:57.788816 # ok 2791 # SKIP Streaming SVE set SVE get FPSIMD for VL 2944
4522 10:06:57.788882 # ok 2792 # SKIP Streaming SVE set FPSIMD get SVE for VL 2944
4523 10:06:57.788970 # ok 2793 Set Streaming SVE VL 2960
4524 10:06:57.789062 # ok 2794 # SKIP Streaming SVE set SVE get SVE for VL 2960
4525 10:06:57.789147 # ok 2795 # SKIP Streaming SVE set SVE get FPSIMD for VL 2960
4526 10:06:57.789214 # ok 2796 # SKIP Streaming SVE set FPSIMD get SVE for VL 2960
4527 10:06:57.789297 # ok 2797 Set Streaming SVE VL 2976
4528 10:06:57.789388 # ok 2798 # SKIP Streaming SVE set SVE get SVE for VL 2976
4529 10:06:57.789468 # ok 2799 # SKIP Streaming SVE set SVE get FPSIMD for VL 2976
4530 10:06:57.789563 # ok 2800 # SKIP Streaming SVE set FPSIMD get SVE for VL 2976
4531 10:06:57.789669 # ok 2801 Set Streaming SVE VL 2992
4532 10:06:57.789751 # ok 2802 # SKIP Streaming SVE set SVE get SVE for VL 2992
4533 10:06:57.789825 # ok 2803 # SKIP Streaming SVE set SVE get FPSIMD for VL 2992
4534 10:06:57.789913 # ok 2804 # SKIP Streaming SVE set FPSIMD get SVE for VL 2992
4535 10:06:57.789976 # ok 2805 Set Streaming SVE VL 3008
4536 10:06:57.790034 # ok 2806 # SKIP Streaming SVE set SVE get SVE for VL 3008
4537 10:06:57.790118 # ok 2807 # SKIP Streaming SVE set SVE get FPSIMD for VL 3008
4538 10:06:57.790219 # ok 2808 # SKIP Streaming SVE set FPSIMD get SVE for VL 3008
4539 10:06:57.790306 # ok 2809 Set Streaming SVE VL 3024
4540 10:06:57.790391 # ok 2810 # SKIP Streaming SVE set SVE get SVE for VL 3024
4541 10:06:57.790455 # ok 2811 # SKIP Streaming SVE set SVE get FPSIMD for VL 3024
4542 10:06:57.790519 # ok 2812 # SKIP Streaming SVE set FPSIMD get SVE for VL 3024
4543 10:06:57.790600 # ok 2813 Set Streaming SVE VL 3040
4544 10:06:57.790680 # ok 2814 # SKIP Streaming SVE set SVE get SVE for VL 3040
4545 10:06:57.790756 # ok 2815 # SKIP Streaming SVE set SVE get FPSIMD for VL 3040
4546 10:06:57.790838 # ok 2816 # SKIP Streaming SVE set FPSIMD get SVE for VL 3040
4547 10:06:57.790915 # ok 2817 Set Streaming SVE VL 3056
4548 10:06:57.790994 # ok 2818 # SKIP Streaming SVE set SVE get SVE for VL 3056
4549 10:06:57.791073 # ok 2819 # SKIP Streaming SVE set SVE get FPSIMD for VL 3056
4550 10:06:57.791167 # ok 2820 # SKIP Streaming SVE set FPSIMD get SVE for VL 3056
4551 10:06:57.791773 # ok 2821 Set Streaming SVE VL 3072
4552 10:06:57.791874 # ok 2822 # SKIP Streaming SVE set SVE get SVE for VL 3072
4553 10:06:57.791973 # ok 2823 # SKIP Streaming SVE set SVE get FPSIMD for VL 3072
4554 10:06:57.792084 # ok 2824 # SKIP Streaming SVE set FPSIMD get SVE for VL 3072
4555 10:06:57.792186 # ok 2825 Set Streaming SVE VL 3088
4556 10:06:57.792284 # ok 2826 # SKIP Streaming SVE set SVE get SVE for VL 3088
4557 10:06:57.792383 # ok 2827 # SKIP Streaming SVE set SVE get FPSIMD for VL 3088
4558 10:06:57.792458 # ok 2828 # SKIP Streaming SVE set FPSIMD get SVE for VL 3088
4559 10:06:57.792534 # ok 2829 Set Streaming SVE VL 3104
4560 10:06:57.792598 # ok 2830 # SKIP Streaming SVE set SVE get SVE for VL 3104
4561 10:06:57.792668 # ok 2831 # SKIP Streaming SVE set SVE get FPSIMD for VL 3104
4562 10:06:57.792730 # ok 2832 # SKIP Streaming SVE set FPSIMD get SVE for VL 3104
4563 10:06:57.792789 # ok 2833 Set Streaming SVE VL 3120
4564 10:06:57.792855 # ok 2834 # SKIP Streaming SVE set SVE get SVE for VL 3120
4565 10:06:57.792934 # ok 2835 # SKIP Streaming SVE set SVE get FPSIMD for VL 3120
4566 10:06:57.793012 # ok 2836 # SKIP Streaming SVE set FPSIMD get SVE for VL 3120
4567 10:06:57.793076 # ok 2837 Set Streaming SVE VL 3136
4568 10:06:57.793136 # ok 2838 # SKIP Streaming SVE set SVE get SVE for VL 3136
4569 10:06:57.793218 # ok 2839 # SKIP Streaming SVE set SVE get FPSIMD for VL 3136
4570 10:06:57.793284 # ok 2840 # SKIP Streaming SVE set FPSIMD get SVE for VL 3136
4571 10:06:57.793357 # ok 2841 Set Streaming SVE VL 3152
4572 10:06:57.793428 # ok 2842 # SKIP Streaming SVE set SVE get SVE for VL 3152
4573 10:06:57.793495 # ok 2843 # SKIP Streaming SVE set SVE get FPSIMD for VL 3152
4574 10:06:57.793571 # ok 2844 # SKIP Streaming SVE set FPSIMD get SVE for VL 3152
4575 10:06:57.793667 # ok 2845 Set Streaming SVE VL 3168
4576 10:06:57.793761 # ok 2846 # SKIP Streaming SVE set SVE get SVE for VL 3168
4577 10:06:57.793851 # ok 2847 # SKIP Streaming SVE set SVE get FPSIMD for VL 3168
4578 10:06:57.793936 # ok 2848 # SKIP Streaming SVE set FPSIMD get SVE for VL 3168
4579 10:06:57.794020 # ok 2849 Set Streaming SVE VL 3184
4580 10:06:57.794109 # ok 2850 # SKIP Streaming SVE set SVE get SVE for VL 3184
4581 10:06:57.794171 # ok 2851 # SKIP Streaming SVE set SVE get FPSIMD for VL 3184
4582 10:06:57.794229 # ok 2852 # SKIP Streaming SVE set FPSIMD get SVE for VL 3184
4583 10:06:57.794287 # ok 2853 Set Streaming SVE VL 3200
4584 10:06:57.794345 # ok 2854 # SKIP Streaming SVE set SVE get SVE for VL 3200
4585 10:06:57.794404 # ok 2855 # SKIP Streaming SVE set SVE get FPSIMD for VL 3200
4586 10:06:57.794659 # ok 2856 # SKIP Streaming SVE set FPSIMD get SVE for VL 3200
4587 10:06:57.794738 # ok 2857 Set Streaming SVE VL 3216
4588 10:06:57.794799 # ok 2858 # SKIP Streaming SVE set SVE get SVE for VL 3216
4589 10:06:57.794856 # ok 2859 # SKIP Streaming SVE set SVE get FPSIMD for VL 3216
4590 10:06:57.794913 # ok 2860 # SKIP Streaming SVE set FPSIMD get SVE for VL 3216
4591 10:06:57.794969 # ok 2861 Set Streaming SVE VL 3232
4592 10:06:57.795025 # ok 2862 # SKIP Streaming SVE set SVE get SVE for VL 3232
4593 10:06:57.795081 # ok 2863 # SKIP Streaming SVE set SVE get FPSIMD for VL 3232
4594 10:06:57.795138 # ok 2864 # SKIP Streaming SVE set FPSIMD get SVE for VL 3232
4595 10:06:57.795194 # ok 2865 Set Streaming SVE VL 3248
4596 10:06:57.795250 # ok 2866 # SKIP Streaming SVE set SVE get SVE for VL 3248
4597 10:06:57.795306 # ok 2867 # SKIP Streaming SVE set SVE get FPSIMD for VL 3248
4598 10:06:57.795362 # ok 2868 # SKIP Streaming SVE set FPSIMD get SVE for VL 3248
4599 10:06:57.795418 # ok 2869 Set Streaming SVE VL 3264
4600 10:06:57.795474 # ok 2870 # SKIP Streaming SVE set SVE get SVE for VL 3264
4601 10:06:57.795535 # ok 2871 # SKIP Streaming SVE set SVE get FPSIMD for VL 3264
4602 10:06:57.795591 # ok 2872 # SKIP Streaming SVE set FPSIMD get SVE for VL 3264
4603 10:06:57.795647 # ok 2873 Set Streaming SVE VL 3280
4604 10:06:57.795703 # ok 2874 # SKIP Streaming SVE set SVE get SVE for VL 3280
4605 10:06:57.795759 # ok 2875 # SKIP Streaming SVE set SVE get FPSIMD for VL 3280
4606 10:06:57.795815 # ok 2876 # SKIP Streaming SVE set FPSIMD get SVE for VL 3280
4607 10:06:57.795871 # ok 2877 Set Streaming SVE VL 3296
4608 10:06:57.802995 # ok 2878 # SKIP Streaming SVE set SVE get SVE for VL 3296
4609 10:06:57.803216 # ok 2879 # SKIP Streaming SVE set SVE get FPSIMD for VL 3296
4610 10:06:57.803305 # ok 2880 # SKIP Streaming SVE set FPSIMD get SVE for VL 3296
4611 10:06:57.803408 # ok 2881 Set Streaming SVE VL 3312
4612 10:06:57.803507 # ok 2882 # SKIP Streaming SVE set SVE get SVE for VL 3312
4613 10:06:57.803614 # ok 2883 # SKIP Streaming SVE set SVE get FPSIMD for VL 3312
4614 10:06:57.810868 # ok 2884 # SKIP Streaming SVE set FPSIMD get SVE for VL 3312
4615 10:06:57.811322 # ok 2885 Set Streaming SVE VL 3328
4616 10:06:57.811406 # ok 2886 # SKIP Streaming SVE set SVE get SVE for VL 3328
4617 10:06:57.811493 # ok 2887 # SKIP Streaming SVE set SVE get FPSIMD for VL 3328
4618 10:06:57.811596 # ok 2888 # SKIP Streaming SVE set FPSIMD get SVE for VL 3328
4619 10:06:57.811712 # ok 2889 Set Streaming SVE VL 3344
4620 10:06:57.811789 # ok 2890 # SKIP Streaming SVE set SVE get SVE for VL 3344
4621 10:06:57.818303 # ok 2891 # SKIP Streaming SVE set SVE get FPSIMD for VL 3344
4622 10:06:57.818809 # ok 2892 # SKIP Streaming SVE set FPSIMD get SVE for VL 3344
4623 10:06:57.818935 # ok 2893 Set Streaming SVE VL 3360
4624 10:06:57.819031 # ok 2894 # SKIP Streaming SVE set SVE get SVE for VL 3360
4625 10:06:57.819127 # ok 2895 # SKIP Streaming SVE set SVE get FPSIMD for VL 3360
4626 10:06:57.819220 # ok 2896 # SKIP Streaming SVE set FPSIMD get SVE for VL 3360
4627 10:06:57.819321 # ok 2897 Set Streaming SVE VL 3376
4628 10:06:57.819629 # ok 2898 # SKIP Streaming SVE set SVE get SVE for VL 3376
4629 10:06:57.819744 # ok 2899 # SKIP Streaming SVE set SVE get FPSIMD for VL 3376
4630 10:06:57.819834 # ok 2900 # SKIP Streaming SVE set FPSIMD get SVE for VL 3376
4631 10:06:57.819921 # ok 2901 Set Streaming SVE VL 3392
4632 10:06:57.820006 # ok 2902 # SKIP Streaming SVE set SVE get SVE for VL 3392
4633 10:06:57.820091 # ok 2903 # SKIP Streaming SVE set SVE get FPSIMD for VL 3392
4634 10:06:57.820175 # ok 2904 # SKIP Streaming SVE set FPSIMD get SVE for VL 3392
4635 10:06:57.820260 # ok 2905 Set Streaming SVE VL 3408
4636 10:06:57.826280 # ok 2906 # SKIP Streaming SVE set SVE get SVE for VL 3408
4637 10:06:57.826649 # ok 2907 # SKIP Streaming SVE set SVE get FPSIMD for VL 3408
4638 10:06:57.826751 # ok 2908 # SKIP Streaming SVE set FPSIMD get SVE for VL 3408
4639 10:06:57.826838 # ok 2909 Set Streaming SVE VL 3424
4640 10:06:57.826935 # ok 2910 # SKIP Streaming SVE set SVE get SVE for VL 3424
4641 10:06:57.827017 # ok 2911 # SKIP Streaming SVE set SVE get FPSIMD for VL 3424
4642 10:06:57.827109 # ok 2912 # SKIP Streaming SVE set FPSIMD get SVE for VL 3424
4643 10:06:57.827202 # ok 2913 Set Streaming SVE VL 3440
4644 10:06:57.827292 # ok 2914 # SKIP Streaming SVE set SVE get SVE for VL 3440
4645 10:06:57.827585 # ok 2915 # SKIP Streaming SVE set SVE get FPSIMD for VL 3440
4646 10:06:57.827696 # ok 2916 # SKIP Streaming SVE set FPSIMD get SVE for VL 3440
4647 10:06:57.835113 # ok 2917 Set Streaming SVE VL 3456
4648 10:06:57.835243 # ok 2918 # SKIP Streaming SVE set SVE get SVE for VL 3456
4649 10:06:57.835371 # ok 2919 # SKIP Streaming SVE set SVE get FPSIMD for VL 3456
4650 10:06:57.835502 # ok 2920 # SKIP Streaming SVE set FPSIMD get SVE for VL 3456
4651 10:06:57.835605 # ok 2921 Set Streaming SVE VL 3472
4652 10:06:57.836958 # ok 2922 # SKIP Streaming SVE set SVE get SVE for VL 3472
4653 10:06:57.837304 # ok 2923 # SKIP Streaming SVE set SVE get FPSIMD for VL 3472
4654 10:06:57.837462 # ok 2924 # SKIP Streaming SVE set FPSIMD get SVE for VL 3472
4655 10:06:57.837855 # ok 2925 Set Streaming SVE VL 3488
4656 10:06:57.838013 # ok 2926 # SKIP Streaming SVE set SVE get SVE for VL 3488
4657 10:06:57.838132 # ok 2927 # SKIP Streaming SVE set SVE get FPSIMD for VL 3488
4658 10:06:57.838246 # ok 2928 # SKIP Streaming SVE set FPSIMD get SVE for VL 3488
4659 10:06:57.838359 # ok 2929 Set Streaming SVE VL 3504
4660 10:06:57.838471 # ok 2930 # SKIP Streaming SVE set SVE get SVE for VL 3504
4661 10:06:57.838768 # ok 2931 # SKIP Streaming SVE set SVE get FPSIMD for VL 3504
4662 10:06:57.838876 # ok 2932 # SKIP Streaming SVE set FPSIMD get SVE for VL 3504
4663 10:06:57.838956 # ok 2933 Set Streaming SVE VL 3520
4664 10:06:57.839033 # ok 2934 # SKIP Streaming SVE set SVE get SVE for VL 3520
4665 10:06:57.839111 # ok 2935 # SKIP Streaming SVE set SVE get FPSIMD for VL 3520
4666 10:06:57.839183 # ok 2936 # SKIP Streaming SVE set FPSIMD get SVE for VL 3520
4667 10:06:57.839260 # ok 2937 Set Streaming SVE VL 3536
4668 10:06:57.839332 # ok 2938 # SKIP Streaming SVE set SVE get SVE for VL 3536
4669 10:06:57.839413 # ok 2939 # SKIP Streaming SVE set SVE get FPSIMD for VL 3536
4670 10:06:57.839483 # ok 2940 # SKIP Streaming SVE set FPSIMD get SVE for VL 3536
4671 10:06:57.839564 # ok 2941 Set Streaming SVE VL 3552
4672 10:06:57.839630 # ok 2942 # SKIP Streaming SVE set SVE get SVE for VL 3552
4673 10:06:57.839689 # ok 2943 # SKIP Streaming SVE set SVE get FPSIMD for VL 3552
4674 10:06:57.839747 # ok 2944 # SKIP Streaming SVE set FPSIMD get SVE for VL 3552
4675 10:06:57.839806 # ok 2945 Set Streaming SVE VL 3568
4676 10:06:57.839864 # ok 2946 # SKIP Streaming SVE set SVE get SVE for VL 3568
4677 10:06:57.839922 # ok 2947 # SKIP Streaming SVE set SVE get FPSIMD for VL 3568
4678 10:06:57.845235 # ok 2948 # SKIP Streaming SVE set FPSIMD get SVE for VL 3568
4679 10:06:57.845534 # ok 2949 Set Streaming SVE VL 3584
4680 10:06:57.845624 # ok 2950 # SKIP Streaming SVE set SVE get SVE for VL 3584
4681 10:06:57.845727 # ok 2951 # SKIP Streaming SVE set SVE get FPSIMD for VL 3584
4682 10:06:57.845810 # ok 2952 # SKIP Streaming SVE set FPSIMD get SVE for VL 3584
4683 10:06:57.845892 # ok 2953 Set Streaming SVE VL 3600
4684 10:06:57.845981 # ok 2954 # SKIP Streaming SVE set SVE get SVE for VL 3600
4685 10:06:57.846071 # ok 2955 # SKIP Streaming SVE set SVE get FPSIMD for VL 3600
4686 10:06:57.846361 # ok 2956 # SKIP Streaming SVE set FPSIMD get SVE for VL 3600
4687 10:06:57.846448 # ok 2957 Set Streaming SVE VL 3616
4688 10:06:57.846536 # ok 2958 # SKIP Streaming SVE set SVE get SVE for VL 3616
4689 10:06:57.846607 # ok 2959 # SKIP Streaming SVE set SVE get FPSIMD for VL 3616
4690 10:06:57.846694 # ok 2960 # SKIP Streaming SVE set FPSIMD get SVE for VL 3616
4691 10:06:57.846786 # ok 2961 Set Streaming SVE VL 3632
4692 10:06:57.847079 # ok 2962 # SKIP Streaming SVE set SVE get SVE for VL 3632
4693 10:06:57.847155 # ok 2963 # SKIP Streaming SVE set SVE get FPSIMD for VL 3632
4694 10:06:57.847227 # ok 2964 # SKIP Streaming SVE set FPSIMD get SVE for VL 3632
4695 10:06:57.847290 # ok 2965 Set Streaming SVE VL 3648
4696 10:06:57.847371 # ok 2966 # SKIP Streaming SVE set SVE get SVE for VL 3648
4697 10:06:57.847459 # ok 2967 # SKIP Streaming SVE set SVE get FPSIMD for VL 3648
4698 10:06:57.847547 # ok 2968 # SKIP Streaming SVE set FPSIMD get SVE for VL 3648
4699 10:06:57.847655 # ok 2969 Set Streaming SVE VL 3664
4700 10:06:57.853342 # ok 2970 # SKIP Streaming SVE set SVE get SVE for VL 3664
4701 10:06:57.853755 # ok 2971 # SKIP Streaming SVE set SVE get FPSIMD for VL 3664
4702 10:06:57.853842 # ok 2972 # SKIP Streaming SVE set FPSIMD get SVE for VL 3664
4703 10:06:57.853913 # ok 2973 Set Streaming SVE VL 3680
4704 10:06:57.854004 # ok 2974 # SKIP Streaming SVE set SVE get SVE for VL 3680
4705 10:06:57.854110 # ok 2975 # SKIP Streaming SVE set SVE get FPSIMD for VL 3680
4706 10:06:57.854189 # ok 2976 # SKIP Streaming SVE set FPSIMD get SVE for VL 3680
4707 10:06:57.854262 # ok 2977 Set Streaming SVE VL 3696
4708 10:06:57.854344 # ok 2978 # SKIP Streaming SVE set SVE get SVE for VL 3696
4709 10:06:57.854420 # ok 2979 # SKIP Streaming SVE set SVE get FPSIMD for VL 3696
4710 10:06:57.854514 # ok 2980 # SKIP Streaming SVE set FPSIMD get SVE for VL 3696
4711 10:06:57.854600 # ok 2981 Set Streaming SVE VL 3712
4712 10:06:57.854698 # ok 2982 # SKIP Streaming SVE set SVE get SVE for VL 3712
4713 10:06:57.854784 # ok 2983 # SKIP Streaming SVE set SVE get FPSIMD for VL 3712
4714 10:06:57.854873 # ok 2984 # SKIP Streaming SVE set FPSIMD get SVE for VL 3712
4715 10:06:57.854981 # ok 2985 Set Streaming SVE VL 3728
4716 10:06:57.855081 # ok 2986 # SKIP Streaming SVE set SVE get SVE for VL 3728
4717 10:06:57.855351 # ok 2987 # SKIP Streaming SVE set SVE get FPSIMD for VL 3728
4718 10:06:57.855438 # ok 2988 # SKIP Streaming SVE set FPSIMD get SVE for VL 3728
4719 10:06:57.855522 # ok 2989 Set Streaming SVE VL 3744
4720 10:06:57.855604 # ok 2990 # SKIP Streaming SVE set SVE get SVE for VL 3744
4721 10:06:57.856318 # ok 2991 # SKIP Streaming SVE set SVE get FPSIMD for VL 3744
4722 10:06:57.856582 # ok 2992 # SKIP Streaming SVE set FPSIMD get SVE for VL 3744
4723 10:06:57.856667 # ok 2993 Set Streaming SVE VL 3760
4724 10:06:57.856754 # ok 2994 # SKIP Streaming SVE set SVE get SVE for VL 3760
4725 10:06:57.856834 # ok 2995 # SKIP Streaming SVE set SVE get FPSIMD for VL 3760
4726 10:06:57.856918 # ok 2996 # SKIP Streaming SVE set FPSIMD get SVE for VL 3760
4727 10:06:57.857009 # ok 2997 Set Streaming SVE VL 3776
4728 10:06:57.857097 # ok 2998 # SKIP Streaming SVE set SVE get SVE for VL 3776
4729 10:06:57.857370 # ok 2999 # SKIP Streaming SVE set SVE get FPSIMD for VL 3776
4730 10:06:57.857485 # ok 3000 # SKIP Streaming SVE set FPSIMD get SVE for VL 3776
4731 10:06:57.857562 # ok 3001 Set Streaming SVE VL 3792
4732 10:06:57.857643 # ok 3002 # SKIP Streaming SVE set SVE get SVE for VL 3792
4733 10:06:57.857911 # ok 3003 # SKIP Streaming SVE set SVE get FPSIMD for VL 3792
4734 10:06:57.857997 # ok 3004 # SKIP Streaming SVE set FPSIMD get SVE for VL 3792
4735 10:06:57.858085 # ok 3005 Set Streaming SVE VL 3808
4736 10:06:57.858161 # ok 3006 # SKIP Streaming SVE set SVE get SVE for VL 3808
4737 10:06:57.858252 # ok 3007 # SKIP Streaming SVE set SVE get FPSIMD for VL 3808
4738 10:06:57.858544 # ok 3008 # SKIP Streaming SVE set FPSIMD get SVE for VL 3808
4739 10:06:57.858639 # ok 3009 Set Streaming SVE VL 3824
4740 10:06:57.858727 # ok 3010 # SKIP Streaming SVE set SVE get SVE for VL 3824
4741 10:06:57.858809 # ok 3011 # SKIP Streaming SVE set SVE get FPSIMD for VL 3824
4742 10:06:57.859073 # ok 3012 # SKIP Streaming SVE set FPSIMD get SVE for VL 3824
4743 10:06:57.859151 # ok 3013 Set Streaming SVE VL 3840
4744 10:06:57.859226 # ok 3014 # SKIP Streaming SVE set SVE get SVE for VL 3840
4745 10:06:57.859311 # ok 3015 # SKIP Streaming SVE set SVE get FPSIMD for VL 3840
4746 10:06:57.859388 # ok 3016 # SKIP Streaming SVE set FPSIMD get SVE for VL 3840
4747 10:06:57.859453 # ok 3017 Set Streaming SVE VL 3856
4748 10:06:57.869201 # ok 3018 # SKIP Streaming SVE set SVE get SVE for VL 3856
4749 10:06:57.869634 # ok 3019 # SKIP Streaming SVE set SVE get FPSIMD for VL 3856
4750 10:06:57.869751 # ok 3020 # SKIP Streaming SVE set FPSIMD get SVE for VL 3856
4751 10:06:57.869841 # ok 3021 Set Streaming SVE VL 3872
4752 10:06:57.869928 # ok 3022 # SKIP Streaming SVE set SVE get SVE for VL 3872
4753 10:06:57.870028 # ok 3023 # SKIP Streaming SVE set SVE get FPSIMD for VL 3872
4754 10:06:57.870115 # ok 3024 # SKIP Streaming SVE set FPSIMD get SVE for VL 3872
4755 10:06:57.870214 # ok 3025 Set Streaming SVE VL 3888
4756 10:06:57.870312 # ok 3026 # SKIP Streaming SVE set SVE get SVE for VL 3888
4757 10:06:57.871194 # ok 3027 # SKIP Streaming SVE set SVE get FPSIMD for VL 3888
4758 10:06:57.871489 # ok 3028 # SKIP Streaming SVE set FPSIMD get SVE for VL 3888
4759 10:06:57.871585 # ok 3029 Set Streaming SVE VL 3904
4760 10:06:57.871686 # ok 3030 # SKIP Streaming SVE set SVE get SVE for VL 3904
4761 10:06:57.875609 # ok 3031 # SKIP Streaming SVE set SVE get FPSIMD for VL 3904
4762 10:06:57.881502 # ok 3032 # SKIP Streaming SVE set FPSIMD get SVE for VL 3904
4763 10:06:57.881724 # ok 3033 Set Streaming SVE VL 3920
4764 10:06:57.881829 # ok 3034 # SKIP Streaming SVE set SVE get SVE for VL 3920
4765 10:06:57.881920 # ok 3035 # SKIP Streaming SVE set SVE get FPSIMD for VL 3920
4766 10:06:57.882020 # ok 3036 # SKIP Streaming SVE set FPSIMD get SVE for VL 3920
4767 10:06:57.882105 # ok 3037 Set Streaming SVE VL 3936
4768 10:06:57.882205 # ok 3038 # SKIP Streaming SVE set SVE get SVE for VL 3936
4769 10:06:57.882505 # ok 3039 # SKIP Streaming SVE set SVE get FPSIMD for VL 3936
4770 10:06:57.882620 # ok 3040 # SKIP Streaming SVE set FPSIMD get SVE for VL 3936
4771 10:06:57.882734 # ok 3041 Set Streaming SVE VL 3952
4772 10:06:57.882814 # ok 3042 # SKIP Streaming SVE set SVE get SVE for VL 3952
4773 10:06:57.882904 # ok 3043 # SKIP Streaming SVE set SVE get FPSIMD for VL 3952
4774 10:06:57.883009 # ok 3044 # SKIP Streaming SVE set FPSIMD get SVE for VL 3952
4775 10:06:57.883095 # ok 3045 Set Streaming SVE VL 3968
4776 10:06:57.883187 # ok 3046 # SKIP Streaming SVE set SVE get SVE for VL 3968
4777 10:06:57.883280 # ok 3047 # SKIP Streaming SVE set SVE get FPSIMD for VL 3968
4778 10:06:57.883568 # ok 3048 # SKIP Streaming SVE set FPSIMD get SVE for VL 3968
4779 10:06:57.883650 # ok 3049 Set Streaming SVE VL 3984
4780 10:06:57.889447 # ok 3050 # SKIP Streaming SVE set SVE get SVE for VL 3984
4781 10:06:57.889703 # ok 3051 # SKIP Streaming SVE set SVE get FPSIMD for VL 3984
4782 10:06:57.889829 # ok 3052 # SKIP Streaming SVE set FPSIMD get SVE for VL 3984
4783 10:06:57.889918 # ok 3053 Set Streaming SVE VL 4000
4784 10:06:57.890022 # ok 3054 # SKIP Streaming SVE set SVE get SVE for VL 4000
4785 10:06:57.890140 # ok 3055 # SKIP Streaming SVE set SVE get FPSIMD for VL 4000
4786 10:06:57.890232 # ok 3056 # SKIP Streaming SVE set FPSIMD get SVE for VL 4000
4787 10:06:57.890320 # ok 3057 Set Streaming SVE VL 4016
4788 10:06:57.890404 # ok 3058 # SKIP Streaming SVE set SVE get SVE for VL 4016
4789 10:06:57.890502 # ok 3059 # SKIP Streaming SVE set SVE get FPSIMD for VL 4016
4790 10:06:57.890590 # ok 3060 # SKIP Streaming SVE set FPSIMD get SVE for VL 4016
4791 10:06:57.890679 # ok 3061 Set Streaming SVE VL 4032
4792 10:06:57.890776 # ok 3062 # SKIP Streaming SVE set SVE get SVE for VL 4032
4793 10:06:57.891056 # ok 3063 # SKIP Streaming SVE set SVE get FPSIMD for VL 4032
4794 10:06:57.891138 # ok 3064 # SKIP Streaming SVE set FPSIMD get SVE for VL 4032
4795 10:06:57.891233 # ok 3065 Set Streaming SVE VL 4048
4796 10:06:57.891335 # ok 3066 # SKIP Streaming SVE set SVE get SVE for VL 4048
4797 10:06:57.891631 # ok 3067 # SKIP Streaming SVE set SVE get FPSIMD for VL 4048
4798 10:06:57.897152 # ok 3068 # SKIP Streaming SVE set FPSIMD get SVE for VL 4048
4799 10:06:57.897550 # ok 3069 Set Streaming SVE VL 4064
4800 10:06:57.897638 # ok 3070 # SKIP Streaming SVE set SVE get SVE for VL 4064
4801 10:06:57.897750 # ok 3071 # SKIP Streaming SVE set SVE get FPSIMD for VL 4064
4802 10:06:57.897833 # ok 3072 # SKIP Streaming SVE set FPSIMD get SVE for VL 4064
4803 10:06:57.897909 # ok 3073 Set Streaming SVE VL 4080
4804 10:06:57.898013 # ok 3074 # SKIP Streaming SVE set SVE get SVE for VL 4080
4805 10:06:57.898107 # ok 3075 # SKIP Streaming SVE set SVE get FPSIMD for VL 4080
4806 10:06:57.898193 # ok 3076 # SKIP Streaming SVE set FPSIMD get SVE for VL 4080
4807 10:06:57.898260 # ok 3077 Set Streaming SVE VL 4096
4808 10:06:57.898337 # ok 3078 # SKIP Streaming SVE set SVE get SVE for VL 4096
4809 10:06:57.898424 # ok 3079 # SKIP Streaming SVE set SVE get FPSIMD for VL 4096
4810 10:06:57.898520 # ok 3080 # SKIP Streaming SVE set FPSIMD get SVE for VL 4096
4811 10:06:57.898651 # ok 3081 Set Streaming SVE VL 4112
4812 10:06:57.898759 # ok 3082 # SKIP Streaming SVE set SVE get SVE for VL 4112
4813 10:06:57.899055 # ok 3083 # SKIP Streaming SVE set SVE get FPSIMD for VL 4112
4814 10:06:57.899160 # ok 3084 # SKIP Streaming SVE set FPSIMD get SVE for VL 4112
4815 10:06:57.899263 # ok 3085 Set Streaming SVE VL 4128
4816 10:06:57.899350 # ok 3086 # SKIP Streaming SVE set SVE get SVE for VL 4128
4817 10:06:57.899450 # ok 3087 # SKIP Streaming SVE set SVE get FPSIMD for VL 4128
4818 10:06:57.905279 # ok 3088 # SKIP Streaming SVE set FPSIMD get SVE for VL 4128
4819 10:06:57.905734 # ok 3089 Set Streaming SVE VL 4144
4820 10:06:57.905833 # ok 3090 # SKIP Streaming SVE set SVE get SVE for VL 4144
4821 10:06:57.905921 # ok 3091 # SKIP Streaming SVE set SVE get FPSIMD for VL 4144
4822 10:06:57.906016 # ok 3092 # SKIP Streaming SVE set FPSIMD get SVE for VL 4144
4823 10:06:57.906096 # ok 3093 Set Streaming SVE VL 4160
4824 10:06:57.906175 # ok 3094 # SKIP Streaming SVE set SVE get SVE for VL 4160
4825 10:06:57.906266 # ok 3095 # SKIP Streaming SVE set SVE get FPSIMD for VL 4160
4826 10:06:57.906361 # ok 3096 # SKIP Streaming SVE set FPSIMD get SVE for VL 4160
4827 10:06:57.906487 # ok 3097 Set Streaming SVE VL 4176
4828 10:06:57.906607 # ok 3098 # SKIP Streaming SVE set SVE get SVE for VL 4176
4829 10:06:57.906717 # ok 3099 # SKIP Streaming SVE set SVE get FPSIMD for VL 4176
4830 10:06:57.906815 # ok 3100 # SKIP Streaming SVE set FPSIMD get SVE for VL 4176
4831 10:06:57.906922 # ok 3101 Set Streaming SVE VL 4192
4832 10:06:57.907215 # ok 3102 # SKIP Streaming SVE set SVE get SVE for VL 4192
4833 10:06:57.907307 # ok 3103 # SKIP Streaming SVE set SVE get FPSIMD for VL 4192
4834 10:06:57.907411 # ok 3104 # SKIP Streaming SVE set FPSIMD get SVE for VL 4192
4835 10:06:57.907512 # ok 3105 Set Streaming SVE VL 4208
4836 10:06:57.907624 # ok 3106 # SKIP Streaming SVE set SVE get SVE for VL 4208
4837 10:06:57.908163 # ok 3107 # SKIP Streaming SVE set SVE get FPSIMD for VL 4208
4838 10:06:57.908417 # ok 3108 # SKIP Streaming SVE set FPSIMD get SVE for VL 4208
4839 10:06:57.908513 # ok 3109 Set Streaming SVE VL 4224
4840 10:06:57.908624 # ok 3110 # SKIP Streaming SVE set SVE get SVE for VL 4224
4841 10:06:57.908722 # ok 3111 # SKIP Streaming SVE set SVE get FPSIMD for VL 4224
4842 10:06:57.908811 # ok 3112 # SKIP Streaming SVE set FPSIMD get SVE for VL 4224
4843 10:06:57.908912 # ok 3113 Set Streaming SVE VL 4240
4844 10:06:57.909012 # ok 3114 # SKIP Streaming SVE set SVE get SVE for VL 4240
4845 10:06:57.909305 # ok 3115 # SKIP Streaming SVE set SVE get FPSIMD for VL 4240
4846 10:06:57.909403 # ok 3116 # SKIP Streaming SVE set FPSIMD get SVE for VL 4240
4847 10:06:57.909488 # ok 3117 Set Streaming SVE VL 4256
4848 10:06:57.909571 # ok 3118 # SKIP Streaming SVE set SVE get SVE for VL 4256
4849 10:06:57.909667 # ok 3119 # SKIP Streaming SVE set SVE get FPSIMD for VL 4256
4850 10:06:57.909788 # ok 3120 # SKIP Streaming SVE set FPSIMD get SVE for VL 4256
4851 10:06:57.909882 # ok 3121 Set Streaming SVE VL 4272
4852 10:06:57.909991 # ok 3122 # SKIP Streaming SVE set SVE get SVE for VL 4272
4853 10:06:57.910093 # ok 3123 # SKIP Streaming SVE set SVE get FPSIMD for VL 4272
4854 10:06:57.910190 # ok 3124 # SKIP Streaming SVE set FPSIMD get SVE for VL 4272
4855 10:06:57.910305 # ok 3125 Set Streaming SVE VL 4288
4856 10:06:57.910411 # ok 3126 # SKIP Streaming SVE set SVE get SVE for VL 4288
4857 10:06:57.910695 # ok 3127 # SKIP Streaming SVE set SVE get FPSIMD for VL 4288
4858 10:06:57.910798 # ok 3128 # SKIP Streaming SVE set FPSIMD get SVE for VL 4288
4859 10:06:57.910889 # ok 3129 Set Streaming SVE VL 4304
4860 10:06:57.910968 # ok 3130 # SKIP Streaming SVE set SVE get SVE for VL 4304
4861 10:06:57.911047 # ok 3131 # SKIP Streaming SVE set SVE get FPSIMD for VL 4304
4862 10:06:57.911333 # ok 3132 # SKIP Streaming SVE set FPSIMD get SVE for VL 4304
4863 10:06:57.911425 # ok 3133 Set Streaming SVE VL 4320
4864 10:06:57.911540 # ok 3134 # SKIP Streaming SVE set SVE get SVE for VL 4320
4865 10:06:57.911633 # ok 3135 # SKIP Streaming SVE set SVE get FPSIMD for VL 4320
4866 10:06:57.919589 # ok 3136 # SKIP Streaming SVE set FPSIMD get SVE for VL 4320
4867 10:06:57.920740 # ok 3137 Set Streaming SVE VL 4336
4868 10:06:57.921024 # ok 3138 # SKIP Streaming SVE set SVE get SVE for VL 4336
4869 10:06:57.921131 # ok 3139 # SKIP Streaming SVE set SVE get FPSIMD for VL 4336
4870 10:06:57.921239 # ok 3140 # SKIP Streaming SVE set FPSIMD get SVE for VL 4336
4871 10:06:57.921340 # ok 3141 Set Streaming SVE VL 4352
4872 10:06:57.921665 # ok 3142 # SKIP Streaming SVE set SVE get SVE for VL 4352
4873 10:06:57.921790 # ok 3143 # SKIP Streaming SVE set SVE get FPSIMD for VL 4352
4874 10:06:57.921925 # ok 3144 # SKIP Streaming SVE set FPSIMD get SVE for VL 4352
4875 10:06:57.922030 # ok 3145 Set Streaming SVE VL 4368
4876 10:06:57.922143 # ok 3146 # SKIP Streaming SVE set SVE get SVE for VL 4368
4877 10:06:57.922239 # ok 3147 # SKIP Streaming SVE set SVE get FPSIMD for VL 4368
4878 10:06:57.922360 # ok 3148 # SKIP Streaming SVE set FPSIMD get SVE for VL 4368
4879 10:06:57.922453 # ok 3149 Set Streaming SVE VL 4384
4880 10:06:57.922556 # ok 3150 # SKIP Streaming SVE set SVE get SVE for VL 4384
4881 10:06:57.922662 # ok 3151 # SKIP Streaming SVE set SVE get FPSIMD for VL 4384
4882 10:06:57.922801 # ok 3152 # SKIP Streaming SVE set FPSIMD get SVE for VL 4384
4883 10:06:57.922959 # ok 3153 Set Streaming SVE VL 4400
4884 10:06:57.923123 # ok 3154 # SKIP Streaming SVE set SVE get SVE for VL 4400
4885 10:06:57.923299 # ok 3155 # SKIP Streaming SVE set SVE get FPSIMD for VL 4400
4886 10:06:57.923437 # ok 3156 # SKIP Streaming SVE set FPSIMD get SVE for VL 4400
4887 10:06:57.923561 # ok 3157 Set Streaming SVE VL 4416
4888 10:06:57.923719 # ok 3158 # SKIP Streaming SVE set SVE get SVE for VL 4416
4889 10:06:57.923837 # ok 3159 # SKIP Streaming SVE set SVE get FPSIMD for VL 4416
4890 10:06:57.929385 # ok 3160 # SKIP Streaming SVE set FPSIMD get SVE for VL 4416
4891 10:06:57.929695 # ok 3161 Set Streaming SVE VL 4432
4892 10:06:57.930111 # ok 3162 # SKIP Streaming SVE set SVE get SVE for VL 4432
4893 10:06:57.930307 # ok 3163 # SKIP Streaming SVE set SVE get FPSIMD for VL 4432
4894 10:06:57.930475 # ok 3164 # SKIP Streaming SVE set FPSIMD get SVE for VL 4432
4895 10:06:57.930637 # ok 3165 Set Streaming SVE VL 4448
4896 10:06:57.930804 # ok 3166 # SKIP Streaming SVE set SVE get SVE for VL 4448
4897 10:06:57.930997 # ok 3167 # SKIP Streaming SVE set SVE get FPSIMD for VL 4448
4898 10:06:57.931164 # ok 3168 # SKIP Streaming SVE set FPSIMD get SVE for VL 4448
4899 10:06:57.931322 # ok 3169 Set Streaming SVE VL 4464
4900 10:06:57.931443 # ok 3170 # SKIP Streaming SVE set SVE get SVE for VL 4464
4901 10:06:57.931612 # ok 3171 # SKIP Streaming SVE set SVE get FPSIMD for VL 4464
4902 10:06:57.931739 # ok 3172 # SKIP Streaming SVE set FPSIMD get SVE for VL 4464
4903 10:06:57.931855 # ok 3173 Set Streaming SVE VL 4480
4904 10:06:57.932004 # ok 3174 # SKIP Streaming SVE set SVE get SVE for VL 4480
4905 10:06:57.932130 # ok 3175 # SKIP Streaming SVE set SVE get FPSIMD for VL 4480
4906 10:06:57.932244 # ok 3176 # SKIP Streaming SVE set FPSIMD get SVE for VL 4480
4907 10:06:57.938094 # ok 3177 Set Streaming SVE VL 4496
4908 10:06:57.938380 # ok 3178 # SKIP Streaming SVE set SVE get SVE for VL 4496
4909 10:06:57.938577 # ok 3179 # SKIP Streaming SVE set SVE get FPSIMD for VL 4496
4910 10:06:57.938731 # ok 3180 # SKIP Streaming SVE set FPSIMD get SVE for VL 4496
4911 10:06:57.938896 # ok 3181 Set Streaming SVE VL 4512
4912 10:06:57.939045 # ok 3182 # SKIP Streaming SVE set SVE get SVE for VL 4512
4913 10:06:57.939200 # ok 3183 # SKIP Streaming SVE set SVE get FPSIMD for VL 4512
4914 10:06:57.939327 # ok 3184 # SKIP Streaming SVE set FPSIMD get SVE for VL 4512
4915 10:06:57.939498 # ok 3185 Set Streaming SVE VL 4528
4916 10:06:57.939685 # ok 3186 # SKIP Streaming SVE set SVE get SVE for VL 4528
4917 10:06:57.939874 # ok 3187 # SKIP Streaming SVE set SVE get FPSIMD for VL 4528
4918 10:06:57.940081 # ok 3188 # SKIP Streaming SVE set FPSIMD get SVE for VL 4528
4919 10:06:57.940220 # ok 3189 Set Streaming SVE VL 4544
4920 10:06:57.940360 # ok 3190 # SKIP Streaming SVE set SVE get SVE for VL 4544
4921 10:06:57.940500 # ok 3191 # SKIP Streaming SVE set SVE get FPSIMD for VL 4544
4922 10:06:57.948848 # ok 3192 # SKIP Streaming SVE set FPSIMD get SVE for VL 4544
4923 10:06:57.949161 # ok 3193 Set Streaming SVE VL 4560
4924 10:06:57.949608 # ok 3194 # SKIP Streaming SVE set SVE get SVE for VL 4560
4925 10:06:57.949802 # ok 3195 # SKIP Streaming SVE set SVE get FPSIMD for VL 4560
4926 10:06:57.949937 # ok 3196 # SKIP Streaming SVE set FPSIMD get SVE for VL 4560
4927 10:06:57.950137 # ok 3197 Set Streaming SVE VL 4576
4928 10:06:57.950319 # ok 3198 # SKIP Streaming SVE set SVE get SVE for VL 4576
4929 10:06:57.950475 # ok 3199 # SKIP Streaming SVE set SVE get FPSIMD for VL 4576
4930 10:06:57.950728 # ok 3200 # SKIP Streaming SVE set FPSIMD get SVE for VL 4576
4931 10:06:57.950925 # ok 3201 Set Streaming SVE VL 4592
4932 10:06:57.951099 # ok 3202 # SKIP Streaming SVE set SVE get SVE for VL 4592
4933 10:06:57.951239 # ok 3203 # SKIP Streaming SVE set SVE get FPSIMD for VL 4592
4934 10:06:57.951393 # ok 3204 # SKIP Streaming SVE set FPSIMD get SVE for VL 4592
4935 10:06:57.951562 # ok 3205 Set Streaming SVE VL 4608
4936 10:06:57.951696 # ok 3206 # SKIP Streaming SVE set SVE get SVE for VL 4608
4937 10:06:57.951814 # ok 3207 # SKIP Streaming SVE set SVE get FPSIMD for VL 4608
4938 10:06:57.951930 # ok 3208 # SKIP Streaming SVE set FPSIMD get SVE for VL 4608
4939 10:06:57.952086 # ok 3209 Set Streaming SVE VL 4624
4940 10:06:57.952209 # ok 3210 # SKIP Streaming SVE set SVE get SVE for VL 4624
4941 10:06:57.952325 # ok 3211 # SKIP Streaming SVE set SVE get FPSIMD for VL 4624
4942 10:06:57.952442 # ok 3212 # SKIP Streaming SVE set FPSIMD get SVE for VL 4624
4943 10:06:57.952557 # ok 3213 Set Streaming SVE VL 4640
4944 10:06:57.952672 # ok 3214 # SKIP Streaming SVE set SVE get SVE for VL 4640
4945 10:06:57.961039 # ok 3215 # SKIP Streaming SVE set SVE get FPSIMD for VL 4640
4946 10:06:57.961335 # ok 3216 # SKIP Streaming SVE set FPSIMD get SVE for VL 4640
4947 10:06:57.961511 # ok 3217 Set Streaming SVE VL 4656
4948 10:06:57.961734 # ok 3218 # SKIP Streaming SVE set SVE get SVE for VL 4656
4949 10:06:57.961899 # ok 3219 # SKIP Streaming SVE set SVE get FPSIMD for VL 4656
4950 10:06:57.962073 # ok 3220 # SKIP Streaming SVE set FPSIMD get SVE for VL 4656
4951 10:06:57.962253 # ok 3221 Set Streaming SVE VL 4672
4952 10:06:57.962405 # ok 3222 # SKIP Streaming SVE set SVE get SVE for VL 4672
4953 10:06:57.962561 # ok 3223 # SKIP Streaming SVE set SVE get FPSIMD for VL 4672
4954 10:06:57.962694 # ok 3224 # SKIP Streaming SVE set FPSIMD get SVE for VL 4672
4955 10:06:57.962817 # ok 3225 Set Streaming SVE VL 4688
4956 10:06:57.962944 # ok 3226 # SKIP Streaming SVE set SVE get SVE for VL 4688
4957 10:06:57.963066 # ok 3227 # SKIP Streaming SVE set SVE get FPSIMD for VL 4688
4958 10:06:57.963187 # ok 3228 # SKIP Streaming SVE set FPSIMD get SVE for VL 4688
4959 10:06:57.963324 # ok 3229 Set Streaming SVE VL 4704
4960 10:06:57.963511 # ok 3230 # SKIP Streaming SVE set SVE get SVE for VL 4704
4961 10:06:57.963699 # ok 3231 # SKIP Streaming SVE set SVE get FPSIMD for VL 4704
4962 10:06:57.963829 # ok 3232 # SKIP Streaming SVE set FPSIMD get SVE for VL 4704
4963 10:06:57.963945 # ok 3233 Set Streaming SVE VL 4720
4964 10:06:57.964098 # ok 3234 # SKIP Streaming SVE set SVE get SVE for VL 4720
4965 10:06:57.964225 # ok 3235 # SKIP Streaming SVE set SVE get FPSIMD for VL 4720
4966 10:06:57.964339 # ok 3236 # SKIP Streaming SVE set FPSIMD get SVE for VL 4720
4967 10:06:57.964453 # ok 3237 Set Streaming SVE VL 4736
4968 10:06:57.964564 # ok 3238 # SKIP Streaming SVE set SVE get SVE for VL 4736
4969 10:06:57.964702 # ok 3239 # SKIP Streaming SVE set SVE get FPSIMD for VL 4736
4970 10:06:57.977884 # ok 3240 # SKIP Streaming SVE set FPSIMD get SVE for VL 4736
4971 10:06:57.978435 # ok 3241 Set Streaming SVE VL 4752
4972 10:06:57.978620 # ok 3242 # SKIP Streaming SVE set SVE get SVE for VL 4752
4973 10:06:57.978790 # ok 3243 # SKIP Streaming SVE set SVE get FPSIMD for VL 4752
4974 10:06:57.978964 # ok 3244 # SKIP Streaming SVE set FPSIMD get SVE for VL 4752
4975 10:06:57.979120 # ok 3245 Set Streaming SVE VL 4768
4976 10:06:57.979287 # ok 3246 # SKIP Streaming SVE set SVE get SVE for VL 4768
4977 10:06:57.979467 # ok 3247 # SKIP Streaming SVE set SVE get FPSIMD for VL 4768
4978 10:06:57.979596 # ok 3248 # SKIP Streaming SVE set FPSIMD get SVE for VL 4768
4979 10:06:57.979711 # ok 3249 Set Streaming SVE VL 4784
4980 10:06:57.979824 # ok 3250 # SKIP Streaming SVE set SVE get SVE for VL 4784
4981 10:06:57.979937 # ok 3251 # SKIP Streaming SVE set SVE get FPSIMD for VL 4784
4982 10:06:57.980049 # ok 3252 # SKIP Streaming SVE set FPSIMD get SVE for VL 4784
4983 10:06:57.980185 # ok 3253 Set Streaming SVE VL 4800
4984 10:06:57.980301 # ok 3254 # SKIP Streaming SVE set SVE get SVE for VL 4800
4985 10:06:57.992968 # ok 3255 # SKIP Streaming SVE set SVE get FPSIMD for VL 4800
4986 10:06:57.993523 # ok 3256 # SKIP Streaming SVE set FPSIMD get SVE for VL 4800
4987 10:06:57.993731 # ok 3257 Set Streaming SVE VL 4816
4988 10:06:57.993946 # ok 3258 # SKIP Streaming SVE set SVE get SVE for VL 4816
4989 10:06:57.994160 # ok 3259 # SKIP Streaming SVE set SVE get FPSIMD for VL 4816
4990 10:06:57.994352 # ok 3260 # SKIP Streaming SVE set FPSIMD get SVE for VL 4816
4991 10:06:57.994520 # ok 3261 Set Streaming SVE VL 4832
4992 10:06:57.994729 # ok 3262 # SKIP Streaming SVE set SVE get SVE for VL 4832
4993 10:06:57.994900 # ok 3263 # SKIP Streaming SVE set SVE get FPSIMD for VL 4832
4994 10:06:57.995064 # ok 3264 # SKIP Streaming SVE set FPSIMD get SVE for VL 4832
4995 10:06:57.995214 # ok 3265 Set Streaming SVE VL 4848
4996 10:06:57.995386 # ok 3266 # SKIP Streaming SVE set SVE get SVE for VL 4848
4997 10:06:57.995572 # ok 3267 # SKIP Streaming SVE set SVE get FPSIMD for VL 4848
4998 10:06:57.995708 # ok 3268 # SKIP Streaming SVE set FPSIMD get SVE for VL 4848
4999 10:06:57.995826 # ok 3269 Set Streaming SVE VL 4864
5000 10:06:57.995977 # ok 3270 # SKIP Streaming SVE set SVE get SVE for VL 4864
5001 10:06:57.996145 # ok 3271 # SKIP Streaming SVE set SVE get FPSIMD for VL 4864
5002 10:06:57.996269 # ok 3272 # SKIP Streaming SVE set FPSIMD get SVE for VL 4864
5003 10:06:57.996386 # ok 3273 Set Streaming SVE VL 4880
5004 10:06:57.996502 # ok 3274 # SKIP Streaming SVE set SVE get SVE for VL 4880
5005 10:06:57.996617 # ok 3275 # SKIP Streaming SVE set SVE get FPSIMD for VL 4880
5006 10:06:57.996733 # ok 3276 # SKIP Streaming SVE set FPSIMD get SVE for VL 4880
5007 10:06:58.009418 # ok 3277 Set Streaming SVE VL 4896
5008 10:06:58.009999 # ok 3278 # SKIP Streaming SVE set SVE get SVE for VL 4896
5009 10:06:58.010193 # ok 3279 # SKIP Streaming SVE set SVE get FPSIMD for VL 4896
5010 10:06:58.010356 # ok 3280 # SKIP Streaming SVE set FPSIMD get SVE for VL 4896
5011 10:06:58.010503 # ok 3281 Set Streaming SVE VL 4912
5012 10:06:58.010674 # ok 3282 # SKIP Streaming SVE set SVE get SVE for VL 4912
5013 10:06:58.010911 # ok 3283 # SKIP Streaming SVE set SVE get FPSIMD for VL 4912
5014 10:06:58.011122 # ok 3284 # SKIP Streaming SVE set FPSIMD get SVE for VL 4912
5015 10:06:58.011346 # ok 3285 Set Streaming SVE VL 4928
5016 10:06:58.011547 # ok 3286 # SKIP Streaming SVE set SVE get SVE for VL 4928
5017 10:06:58.011684 # ok 3287 # SKIP Streaming SVE set SVE get FPSIMD for VL 4928
5018 10:06:58.011801 # ok 3288 # SKIP Streaming SVE set FPSIMD get SVE for VL 4928
5019 10:06:58.011948 # ok 3289 Set Streaming SVE VL 4944
5020 10:06:58.012068 # ok 3290 # SKIP Streaming SVE set SVE get SVE for VL 4944
5021 10:06:58.012184 # ok 3291 # SKIP Streaming SVE set SVE get FPSIMD for VL 4944
5022 10:06:58.012297 # ok 3292 # SKIP Streaming SVE set FPSIMD get SVE for VL 4944
5023 10:06:58.012410 # ok 3293 Set Streaming SVE VL 4960
5024 10:06:58.021518 # ok 3294 # SKIP Streaming SVE set SVE get SVE for VL 4960
5025 10:06:58.021905 # ok 3295 # SKIP Streaming SVE set SVE get FPSIMD for VL 4960
5026 10:06:58.022053 # ok 3296 # SKIP Streaming SVE set FPSIMD get SVE for VL 4960
5027 10:06:58.022281 # ok 3297 Set Streaming SVE VL 4976
5028 10:06:58.022453 # ok 3298 # SKIP Streaming SVE set SVE get SVE for VL 4976
5029 10:06:58.022608 # ok 3299 # SKIP Streaming SVE set SVE get FPSIMD for VL 4976
5030 10:06:58.022763 # ok 3300 # SKIP Streaming SVE set FPSIMD get SVE for VL 4976
5031 10:06:58.022883 # ok 3301 Set Streaming SVE VL 4992
5032 10:06:58.023024 # ok 3302 # SKIP Streaming SVE set SVE get SVE for VL 4992
5033 10:06:58.023155 # ok 3303 # SKIP Streaming SVE set SVE get FPSIMD for VL 4992
5034 10:06:58.023284 # ok 3304 # SKIP Streaming SVE set FPSIMD get SVE for VL 4992
5035 10:06:58.023477 # ok 3305 Set Streaming SVE VL 5008
5036 10:06:58.023652 # ok 3306 # SKIP Streaming SVE set SVE get SVE for VL 5008
5037 10:06:58.023808 # ok 3307 # SKIP Streaming SVE set SVE get FPSIMD for VL 5008
5038 10:06:58.023931 # ok 3308 # SKIP Streaming SVE set FPSIMD get SVE for VL 5008
5039 10:06:58.024046 # ok 3309 Set Streaming SVE VL 5024
5040 10:06:58.024158 # ok 3310 # SKIP Streaming SVE set SVE get SVE for VL 5024
5041 10:06:58.028596 # ok 3311 # SKIP Streaming SVE set SVE get FPSIMD for VL 5024
5042 10:06:58.029022 # ok 3312 # SKIP Streaming SVE set FPSIMD get SVE for VL 5024
5043 10:06:58.029194 # ok 3313 Set Streaming SVE VL 5040
5044 10:06:58.029365 # ok 3314 # SKIP Streaming SVE set SVE get SVE for VL 5040
5045 10:06:58.029572 # ok 3315 # SKIP Streaming SVE set SVE get FPSIMD for VL 5040
5046 10:06:58.029770 # ok 3316 # SKIP Streaming SVE set FPSIMD get SVE for VL 5040
5047 10:06:58.029942 # ok 3317 Set Streaming SVE VL 5056
5048 10:06:58.030085 # ok 3318 # SKIP Streaming SVE set SVE get SVE for VL 5056
5049 10:06:58.030260 # ok 3319 # SKIP Streaming SVE set SVE get FPSIMD for VL 5056
5050 10:06:58.030429 # ok 3320 # SKIP Streaming SVE set FPSIMD get SVE for VL 5056
5051 10:06:58.030599 # ok 3321 Set Streaming SVE VL 5072
5052 10:06:58.030742 # ok 3322 # SKIP Streaming SVE set SVE get SVE for VL 5072
5053 10:06:58.030882 # ok 3323 # SKIP Streaming SVE set SVE get FPSIMD for VL 5072
5054 10:06:58.031058 # ok 3324 # SKIP Streaming SVE set FPSIMD get SVE for VL 5072
5055 10:06:58.031193 # ok 3325 Set Streaming SVE VL 5088
5056 10:06:58.031334 # ok 3326 # SKIP Streaming SVE set SVE get SVE for VL 5088
5057 10:06:58.035472 # ok 3327 # SKIP Streaming SVE set SVE get FPSIMD for VL 5088
5058 10:06:58.035628 # ok 3328 # SKIP Streaming SVE set FPSIMD get SVE for VL 5088
5059 10:06:58.035768 # ok 3329 Set Streaming SVE VL 5104
5060 10:06:58.045150 # ok 3330 # SKIP Streaming SVE set SVE get SVE for VL 5104
5061 10:06:58.045560 # ok 3331 # SKIP Streaming SVE set SVE get FPSIMD for VL 5104
5062 10:06:58.045768 # ok 3332 # SKIP Streaming SVE set FPSIMD get SVE for VL 5104
5063 10:06:58.045956 # ok 3333 Set Streaming SVE VL 5120
5064 10:06:58.046220 # ok 3334 # SKIP Streaming SVE set SVE get SVE for VL 5120
5065 10:06:58.046419 # ok 3335 # SKIP Streaming SVE set SVE get FPSIMD for VL 5120
5066 10:06:58.046599 # ok 3336 # SKIP Streaming SVE set FPSIMD get SVE for VL 5120
5067 10:06:58.046788 # ok 3337 Set Streaming SVE VL 5136
5068 10:06:58.046986 # ok 3338 # SKIP Streaming SVE set SVE get SVE for VL 5136
5069 10:06:58.047205 # ok 3339 # SKIP Streaming SVE set SVE get FPSIMD for VL 5136
5070 10:06:58.047401 # ok 3340 # SKIP Streaming SVE set FPSIMD get SVE for VL 5136
5071 10:06:58.047571 # ok 3341 Set Streaming SVE VL 5152
5072 10:06:58.047692 # ok 3342 # SKIP Streaming SVE set SVE get SVE for VL 5152
5073 10:06:58.047803 # ok 3343 # SKIP Streaming SVE set SVE get FPSIMD for VL 5152
5074 10:06:58.047915 # ok 3344 # SKIP Streaming SVE set FPSIMD get SVE for VL 5152
5075 10:06:58.048029 # ok 3345 Set Streaming SVE VL 5168
5076 10:06:58.048139 # ok 3346 # SKIP Streaming SVE set SVE get SVE for VL 5168
5077 10:06:58.048250 # ok 3347 # SKIP Streaming SVE set SVE get FPSIMD for VL 5168
5078 10:06:58.048386 # ok 3348 # SKIP Streaming SVE set FPSIMD get SVE for VL 5168
5079 10:06:58.048504 # ok 3349 Set Streaming SVE VL 5184
5080 10:06:58.048615 # ok 3350 # SKIP Streaming SVE set SVE get SVE for VL 5184
5081 10:06:58.053124 # ok 3351 # SKIP Streaming SVE set SVE get FPSIMD for VL 5184
5082 10:06:58.053559 # ok 3352 # SKIP Streaming SVE set FPSIMD get SVE for VL 5184
5083 10:06:58.053755 # ok 3353 Set Streaming SVE VL 5200
5084 10:06:58.053906 # ok 3354 # SKIP Streaming SVE set SVE get SVE for VL 5200
5085 10:06:58.054047 # ok 3355 # SKIP Streaming SVE set SVE get FPSIMD for VL 5200
5086 10:06:58.054236 # ok 3356 # SKIP Streaming SVE set FPSIMD get SVE for VL 5200
5087 10:06:58.054401 # ok 3357 Set Streaming SVE VL 5216
5088 10:06:58.054599 # ok 3358 # SKIP Streaming SVE set SVE get SVE for VL 5216
5089 10:06:58.054777 # ok 3359 # SKIP Streaming SVE set SVE get FPSIMD for VL 5216
5090 10:06:58.054935 # ok 3360 # SKIP Streaming SVE set FPSIMD get SVE for VL 5216
5091 10:06:58.055069 # ok 3361 Set Streaming SVE VL 5232
5092 10:06:58.055214 # ok 3362 # SKIP Streaming SVE set SVE get SVE for VL 5232
5093 10:06:58.055335 # ok 3363 # SKIP Streaming SVE set SVE get FPSIMD for VL 5232
5094 10:06:58.055450 # ok 3364 # SKIP Streaming SVE set FPSIMD get SVE for VL 5232
5095 10:06:58.055565 # ok 3365 Set Streaming SVE VL 5248
5096 10:06:58.061068 # ok 3366 # SKIP Streaming SVE set SVE get SVE for VL 5248
5097 10:06:58.061640 # ok 3367 # SKIP Streaming SVE set SVE get FPSIMD for VL 5248
5098 10:06:58.061850 # ok 3368 # SKIP Streaming SVE set FPSIMD get SVE for VL 5248
5099 10:06:58.062037 # ok 3369 Set Streaming SVE VL 5264
5100 10:06:58.062234 # ok 3370 # SKIP Streaming SVE set SVE get SVE for VL 5264
5101 10:06:58.062396 # ok 3371 # SKIP Streaming SVE set SVE get FPSIMD for VL 5264
5102 10:06:58.062597 # ok 3372 # SKIP Streaming SVE set FPSIMD get SVE for VL 5264
5103 10:06:58.062836 # ok 3373 Set Streaming SVE VL 5280
5104 10:06:58.063019 # ok 3374 # SKIP Streaming SVE set SVE get SVE for VL 5280
5105 10:06:58.063228 # ok 3375 # SKIP Streaming SVE set SVE get FPSIMD for VL 5280
5106 10:06:58.063408 # ok 3376 # SKIP Streaming SVE set FPSIMD get SVE for VL 5280
5107 10:06:58.063609 # ok 3377 Set Streaming SVE VL 5296
5108 10:06:58.063744 # ok 3378 # SKIP Streaming SVE set SVE get SVE for VL 5296
5109 10:06:58.063862 # ok 3379 # SKIP Streaming SVE set SVE get FPSIMD for VL 5296
5110 10:06:58.063981 # ok 3380 # SKIP Streaming SVE set FPSIMD get SVE for VL 5296
5111 10:06:58.064127 # ok 3381 Set Streaming SVE VL 5312
5112 10:06:58.064251 # ok 3382 # SKIP Streaming SVE set SVE get SVE for VL 5312
5113 10:06:58.064368 # ok 3383 # SKIP Streaming SVE set SVE get FPSIMD for VL 5312
5114 10:06:58.064483 # ok 3384 # SKIP Streaming SVE set FPSIMD get SVE for VL 5312
5115 10:06:58.064598 # ok 3385 Set Streaming SVE VL 5328
5116 10:06:58.064712 # ok 3386 # SKIP Streaming SVE set SVE get SVE for VL 5328
5117 10:06:58.069418 # ok 3387 # SKIP Streaming SVE set SVE get FPSIMD for VL 5328
5118 10:06:58.069977 # ok 3388 # SKIP Streaming SVE set FPSIMD get SVE for VL 5328
5119 10:06:58.070177 # ok 3389 Set Streaming SVE VL 5344
5120 10:06:58.070340 # ok 3390 # SKIP Streaming SVE set SVE get SVE for VL 5344
5121 10:06:58.070500 # ok 3391 # SKIP Streaming SVE set SVE get FPSIMD for VL 5344
5122 10:06:58.070662 # ok 3392 # SKIP Streaming SVE set FPSIMD get SVE for VL 5344
5123 10:06:58.070860 # ok 3393 Set Streaming SVE VL 5360
5124 10:06:58.071024 # ok 3394 # SKIP Streaming SVE set SVE get SVE for VL 5360
5125 10:06:58.071180 # ok 3395 # SKIP Streaming SVE set SVE get FPSIMD for VL 5360
5126 10:06:58.071331 # ok 3396 # SKIP Streaming SVE set FPSIMD get SVE for VL 5360
5127 10:06:58.071491 # ok 3397 Set Streaming SVE VL 5376
5128 10:06:58.071668 # ok 3398 # SKIP Streaming SVE set SVE get SVE for VL 5376
5129 10:06:58.071796 # ok 3399 # SKIP Streaming SVE set SVE get FPSIMD for VL 5376
5130 10:06:58.071911 # ok 3400 # SKIP Streaming SVE set FPSIMD get SVE for VL 5376
5131 10:06:58.072094 # ok 3401 Set Streaming SVE VL 5392
5132 10:06:58.072275 # ok 3402 # SKIP Streaming SVE set SVE get SVE for VL 5392
5133 10:06:58.072438 # ok 3403 # SKIP Streaming SVE set SVE get FPSIMD for VL 5392
5134 10:06:58.072595 # ok 3404 # SKIP Streaming SVE set FPSIMD get SVE for VL 5392
5135 10:06:58.072728 # ok 3405 Set Streaming SVE VL 5408
5136 10:06:58.072880 # ok 3406 # SKIP Streaming SVE set SVE get SVE for VL 5408
5137 10:06:58.073036 # ok 3407 # SKIP Streaming SVE set SVE get FPSIMD for VL 5408
5138 10:06:58.073194 # ok 3408 # SKIP Streaming SVE set FPSIMD get SVE for VL 5408
5139 10:06:58.073333 # ok 3409 Set Streaming SVE VL 5424
5140 10:06:58.073473 # ok 3410 # SKIP Streaming SVE set SVE get SVE for VL 5424
5141 10:06:58.074398 # ok 3411 # SKIP Streaming SVE set SVE get FPSIMD for VL 5424
5142 10:06:58.074649 # ok 3412 # SKIP Streaming SVE set FPSIMD get SVE for VL 5424
5143 10:06:58.074838 # ok 3413 Set Streaming SVE VL 5440
5144 10:06:58.075020 # ok 3414 # SKIP Streaming SVE set SVE get SVE for VL 5440
5145 10:06:58.075227 # ok 3415 # SKIP Streaming SVE set SVE get FPSIMD for VL 5440
5146 10:06:58.075421 # ok 3416 # SKIP Streaming SVE set FPSIMD get SVE for VL 5440
5147 10:06:58.075623 # ok 3417 Set Streaming SVE VL 5456
5148 10:06:58.075771 # ok 3418 # SKIP Streaming SVE set SVE get SVE for VL 5456
5149 10:06:58.075889 # ok 3419 # SKIP Streaming SVE set SVE get FPSIMD for VL 5456
5150 10:06:58.076002 # ok 3420 # SKIP Streaming SVE set FPSIMD get SVE for VL 5456
5151 10:06:58.076115 # ok 3421 Set Streaming SVE VL 5472
5152 10:06:58.076226 # ok 3422 # SKIP Streaming SVE set SVE get SVE for VL 5472
5153 10:06:58.076570 # ok 3423 # SKIP Streaming SVE set SVE get FPSIMD for VL 5472
5154 10:06:58.076727 # ok 3424 # SKIP Streaming SVE set FPSIMD get SVE for VL 5472
5155 10:06:58.076849 # ok 3425 Set Streaming SVE VL 5488
5156 10:06:58.076965 # ok 3426 # SKIP Streaming SVE set SVE get SVE for VL 5488
5157 10:06:58.077082 # ok 3427 # SKIP Streaming SVE set SVE get FPSIMD for VL 5488
5158 10:06:58.077196 # ok 3428 # SKIP Streaming SVE set FPSIMD get SVE for VL 5488
5159 10:06:58.077311 # ok 3429 Set Streaming SVE VL 5504
5160 10:06:58.077424 # ok 3430 # SKIP Streaming SVE set SVE get SVE for VL 5504
5161 10:06:58.077539 # ok 3431 # SKIP Streaming SVE set SVE get FPSIMD for VL 5504
5162 10:06:58.077666 # ok 3432 # SKIP Streaming SVE set FPSIMD get SVE for VL 5504
5163 10:06:58.077784 # ok 3433 Set Streaming SVE VL 5520
5164 10:06:58.083556 # ok 3434 # SKIP Streaming SVE set SVE get SVE for VL 5520
5165 10:06:58.083801 # ok 3435 # SKIP Streaming SVE set SVE get FPSIMD for VL 5520
5166 10:06:58.084922 # ok 3436 # SKIP Streaming SVE set FPSIMD get SVE for VL 5520
5167 10:06:58.085368 # ok 3437 Set Streaming SVE VL 5536
5168 10:06:58.085556 # ok 3438 # SKIP Streaming SVE set SVE get SVE for VL 5536
5169 10:06:58.085743 # ok 3439 # SKIP Streaming SVE set SVE get FPSIMD for VL 5536
5170 10:06:58.085913 # ok 3440 # SKIP Streaming SVE set FPSIMD get SVE for VL 5536
5171 10:06:58.086139 # ok 3441 Set Streaming SVE VL 5552
5172 10:06:58.086331 # ok 3442 # SKIP Streaming SVE set SVE get SVE for VL 5552
5173 10:06:58.086524 # ok 3443 # SKIP Streaming SVE set SVE get FPSIMD for VL 5552
5174 10:06:58.086700 # ok 3444 # SKIP Streaming SVE set FPSIMD get SVE for VL 5552
5175 10:06:58.086946 # ok 3445 Set Streaming SVE VL 5568
5176 10:06:58.087126 # ok 3446 # SKIP Streaming SVE set SVE get SVE for VL 5568
5177 10:06:58.087291 # ok 3447 # SKIP Streaming SVE set SVE get FPSIMD for VL 5568
5178 10:06:58.087417 # ok 3448 # SKIP Streaming SVE set FPSIMD get SVE for VL 5568
5179 10:06:58.087551 # ok 3449 Set Streaming SVE VL 5584
5180 10:06:58.087672 # ok 3450 # SKIP Streaming SVE set SVE get SVE for VL 5584
5181 10:06:58.087786 # ok 3451 # SKIP Streaming SVE set SVE get FPSIMD for VL 5584
5182 10:06:58.087899 # ok 3452 # SKIP Streaming SVE set FPSIMD get SVE for VL 5584
5183 10:06:58.088010 # ok 3453 Set Streaming SVE VL 5600
5184 10:06:58.088150 # ok 3454 # SKIP Streaming SVE set SVE get SVE for VL 5600
5185 10:06:58.088267 # ok 3455 # SKIP Streaming SVE set SVE get FPSIMD for VL 5600
5186 10:06:58.088379 # ok 3456 # SKIP Streaming SVE set FPSIMD get SVE for VL 5600
5187 10:06:58.088491 # ok 3457 Set Streaming SVE VL 5616
5188 10:06:58.088603 # ok 3458 # SKIP Streaming SVE set SVE get SVE for VL 5616
5189 10:06:58.094696 # ok 3459 # SKIP Streaming SVE set SVE get FPSIMD for VL 5616
5190 10:06:58.095267 # ok 3460 # SKIP Streaming SVE set FPSIMD get SVE for VL 5616
5191 10:06:58.095455 # ok 3461 Set Streaming SVE VL 5632
5192 10:06:58.095583 # ok 3462 # SKIP Streaming SVE set SVE get SVE for VL 5632
5193 10:06:58.095700 # ok 3463 # SKIP Streaming SVE set SVE get FPSIMD for VL 5632
5194 10:06:58.095815 # ok 3464 # SKIP Streaming SVE set FPSIMD get SVE for VL 5632
5195 10:06:58.095952 # ok 3465 Set Streaming SVE VL 5648
5196 10:06:58.096074 # ok 3466 # SKIP Streaming SVE set SVE get SVE for VL 5648
5197 10:06:58.096812 # ok 3467 # SKIP Streaming SVE set SVE get FPSIMD for VL 5648
5198 10:06:58.097188 # ok 3468 # SKIP Streaming SVE set FPSIMD get SVE for VL 5648
5199 10:06:58.097424 # ok 3469 Set Streaming SVE VL 5664
5200 10:06:58.097630 # ok 3470 # SKIP Streaming SVE set SVE get SVE for VL 5664
5201 10:06:58.097828 # ok 3471 # SKIP Streaming SVE set SVE get FPSIMD for VL 5664
5202 10:06:58.097999 # ok 3472 # SKIP Streaming SVE set FPSIMD get SVE for VL 5664
5203 10:06:58.098145 # ok 3473 Set Streaming SVE VL 5680
5204 10:06:58.098321 # ok 3474 # SKIP Streaming SVE set SVE get SVE for VL 5680
5205 10:06:58.098459 # ok 3475 # SKIP Streaming SVE set SVE get FPSIMD for VL 5680
5206 10:06:58.098859 # ok 3476 # SKIP Streaming SVE set FPSIMD get SVE for VL 5680
5207 10:06:58.099096 # ok 3477 Set Streaming SVE VL 5696
5208 10:06:58.099293 # ok 3478 # SKIP Streaming SVE set SVE get SVE for VL 5696
5209 10:06:58.099510 # ok 3479 # SKIP Streaming SVE set SVE get FPSIMD for VL 5696
5210 10:06:58.099659 # ok 3480 # SKIP Streaming SVE set FPSIMD get SVE for VL 5696
5211 10:06:58.099782 # ok 3481 Set Streaming SVE VL 5712
5212 10:06:58.099920 # ok 3482 # SKIP Streaming SVE set SVE get SVE for VL 5712
5213 10:06:58.104991 # ok 3483 # SKIP Streaming SVE set SVE get FPSIMD for VL 5712
5214 10:06:58.105270 # ok 3484 # SKIP Streaming SVE set FPSIMD get SVE for VL 5712
5215 10:06:58.105441 # ok 3485 Set Streaming SVE VL 5728
5216 10:06:58.105602 # ok 3486 # SKIP Streaming SVE set SVE get SVE for VL 5728
5217 10:06:58.105835 # ok 3487 # SKIP Streaming SVE set SVE get FPSIMD for VL 5728
5218 10:06:58.106037 # ok 3488 # SKIP Streaming SVE set FPSIMD get SVE for VL 5728
5219 10:06:58.106216 # ok 3489 Set Streaming SVE VL 5744
5220 10:06:58.106378 # ok 3490 # SKIP Streaming SVE set SVE get SVE for VL 5744
5221 10:06:58.106540 # ok 3491 # SKIP Streaming SVE set SVE get FPSIMD for VL 5744
5222 10:06:58.106737 # ok 3492 # SKIP Streaming SVE set FPSIMD get SVE for VL 5744
5223 10:06:58.106901 # ok 3493 Set Streaming SVE VL 5760
5224 10:06:58.107062 # ok 3494 # SKIP Streaming SVE set SVE get SVE for VL 5760
5225 10:06:58.107223 # ok 3495 # SKIP Streaming SVE set SVE get FPSIMD for VL 5760
5226 10:06:58.107383 # ok 3496 # SKIP Streaming SVE set FPSIMD get SVE for VL 5760
5227 10:06:58.107516 # ok 3497 Set Streaming SVE VL 5776
5228 10:06:58.107632 # ok 3498 # SKIP Streaming SVE set SVE get SVE for VL 5776
5229 10:06:58.107774 # ok 3499 # SKIP Streaming SVE set SVE get FPSIMD for VL 5776
5230 10:06:58.107894 # ok 3500 # SKIP Streaming SVE set FPSIMD get SVE for VL 5776
5231 10:06:58.108008 # ok 3501 Set Streaming SVE VL 5792
5232 10:06:58.108123 # ok 3502 # SKIP Streaming SVE set SVE get SVE for VL 5792
5233 10:06:58.108237 # ok 3503 # SKIP Streaming SVE set SVE get FPSIMD for VL 5792
5234 10:06:58.108348 # ok 3504 # SKIP Streaming SVE set FPSIMD get SVE for VL 5792
5235 10:06:58.112576 # ok 3505 Set Streaming SVE VL 5808
5236 10:06:58.112836 # ok 3506 # SKIP Streaming SVE set SVE get SVE for VL 5808
5237 10:06:58.113040 # ok 3507 # SKIP Streaming SVE set SVE get FPSIMD for VL 5808
5238 10:06:58.113240 # ok 3508 # SKIP Streaming SVE set FPSIMD get SVE for VL 5808
5239 10:06:58.113433 # ok 3509 Set Streaming SVE VL 5824
5240 10:06:58.113601 # ok 3510 # SKIP Streaming SVE set SVE get SVE for VL 5824
5241 10:06:58.113842 # ok 3511 # SKIP Streaming SVE set SVE get FPSIMD for VL 5824
5242 10:06:58.113989 # ok 3512 # SKIP Streaming SVE set FPSIMD get SVE for VL 5824
5243 10:06:58.114180 # ok 3513 Set Streaming SVE VL 5840
5244 10:06:58.114357 # ok 3514 # SKIP Streaming SVE set SVE get SVE for VL 5840
5245 10:06:58.114568 # ok 3515 # SKIP Streaming SVE set SVE get FPSIMD for VL 5840
5246 10:06:58.114748 # ok 3516 # SKIP Streaming SVE set FPSIMD get SVE for VL 5840
5247 10:06:58.114917 # ok 3517 Set Streaming SVE VL 5856
5248 10:06:58.115089 # ok 3518 # SKIP Streaming SVE set SVE get SVE for VL 5856
5249 10:06:58.115269 # ok 3519 # SKIP Streaming SVE set SVE get FPSIMD for VL 5856
5250 10:06:58.115454 # ok 3520 # SKIP Streaming SVE set FPSIMD get SVE for VL 5856
5251 10:06:58.115645 # ok 3521 Set Streaming SVE VL 5872
5252 10:06:58.115807 # ok 3522 # SKIP Streaming SVE set SVE get SVE for VL 5872
5253 10:06:58.115955 # ok 3523 # SKIP Streaming SVE set SVE get FPSIMD for VL 5872
5254 10:06:58.116102 # ok 3524 # SKIP Streaming SVE set FPSIMD get SVE for VL 5872
5255 10:06:58.116246 # ok 3525 Set Streaming SVE VL 5888
5256 10:06:58.116393 # ok 3526 # SKIP Streaming SVE set SVE get SVE for VL 5888
5257 10:06:58.116537 # ok 3527 # SKIP Streaming SVE set SVE get FPSIMD for VL 5888
5258 10:06:58.116716 # ok 3528 # SKIP Streaming SVE set FPSIMD get SVE for VL 5888
5259 10:06:58.124200 # ok 3529 Set Streaming SVE VL 5904
5260 10:06:58.124601 # ok 3530 # SKIP Streaming SVE set SVE get SVE for VL 5904
5261 10:06:58.124692 # ok 3531 # SKIP Streaming SVE set SVE get FPSIMD for VL 5904
5262 10:06:58.124771 # ok 3532 # SKIP Streaming SVE set FPSIMD get SVE for VL 5904
5263 10:06:58.124850 # ok 3533 Set Streaming SVE VL 5920
5264 10:06:58.124917 # ok 3534 # SKIP Streaming SVE set SVE get SVE for VL 5920
5265 10:06:58.124987 # ok 3535 # SKIP Streaming SVE set SVE get FPSIMD for VL 5920
5266 10:06:58.125066 # ok 3536 # SKIP Streaming SVE set FPSIMD get SVE for VL 5920
5267 10:06:58.125214 # ok 3537 Set Streaming SVE VL 5936
5268 10:06:58.125444 # ok 3538 # SKIP Streaming SVE set SVE get SVE for VL 5936
5269 10:06:58.125667 # ok 3539 # SKIP Streaming SVE set SVE get FPSIMD for VL 5936
5270 10:06:58.125814 # ok 3540 # SKIP Streaming SVE set FPSIMD get SVE for VL 5936
5271 10:06:58.125966 # ok 3541 Set Streaming SVE VL 5952
5272 10:06:58.126151 # ok 3542 # SKIP Streaming SVE set SVE get SVE for VL 5952
5273 10:06:58.126311 # ok 3543 # SKIP Streaming SVE set SVE get FPSIMD for VL 5952
5274 10:06:58.126468 # ok 3544 # SKIP Streaming SVE set FPSIMD get SVE for VL 5952
5275 10:06:58.126619 # ok 3545 Set Streaming SVE VL 5968
5276 10:06:58.126800 # ok 3546 # SKIP Streaming SVE set SVE get SVE for VL 5968
5277 10:06:58.126955 # ok 3547 # SKIP Streaming SVE set SVE get FPSIMD for VL 5968
5278 10:06:58.127113 # ok 3548 # SKIP Streaming SVE set FPSIMD get SVE for VL 5968
5279 10:06:58.127267 # ok 3549 Set Streaming SVE VL 5984
5280 10:06:58.127459 # ok 3550 # SKIP Streaming SVE set SVE get SVE for VL 5984
5281 10:06:58.127620 # ok 3551 # SKIP Streaming SVE set SVE get FPSIMD for VL 5984
5282 10:06:58.127738 # ok 3552 # SKIP Streaming SVE set FPSIMD get SVE for VL 5984
5283 10:06:58.127850 # ok 3553 Set Streaming SVE VL 6000
5284 10:06:58.127960 # ok 3554 # SKIP Streaming SVE set SVE get SVE for VL 6000
5285 10:06:58.128071 # ok 3555 # SKIP Streaming SVE set SVE get FPSIMD for VL 6000
5286 10:06:58.138785 # ok 3556 # SKIP Streaming SVE set FPSIMD get SVE for VL 6000
5287 10:06:58.139356 # ok 3557 Set Streaming SVE VL 6016
5288 10:06:58.139604 # ok 3558 # SKIP Streaming SVE set SVE get SVE for VL 6016
5289 10:06:58.139737 # ok 3559 # SKIP Streaming SVE set SVE get FPSIMD for VL 6016
5290 10:06:58.139855 # ok 3560 # SKIP Streaming SVE set FPSIMD get SVE for VL 6016
5291 10:06:58.139970 # ok 3561 Set Streaming SVE VL 6032
5292 10:06:58.140109 # ok 3562 # SKIP Streaming SVE set SVE get SVE for VL 6032
5293 10:06:58.145138 # ok 3563 # SKIP Streaming SVE set SVE get FPSIMD for VL 6032
5294 10:06:58.145436 # ok 3564 # SKIP Streaming SVE set FPSIMD get SVE for VL 6032
5295 10:06:58.145861 # ok 3565 Set Streaming SVE VL 6048
5296 10:06:58.146050 # ok 3566 # SKIP Streaming SVE set SVE get SVE for VL 6048
5297 10:06:58.146196 # ok 3567 # SKIP Streaming SVE set SVE get FPSIMD for VL 6048
5298 10:06:58.146344 # ok 3568 # SKIP Streaming SVE set FPSIMD get SVE for VL 6048
5299 10:06:58.146507 # ok 3569 Set Streaming SVE VL 6064
5300 10:06:58.146654 # ok 3570 # SKIP Streaming SVE set SVE get SVE for VL 6064
5301 10:06:58.146852 # ok 3571 # SKIP Streaming SVE set SVE get FPSIMD for VL 6064
5302 10:06:58.147051 # ok 3572 # SKIP Streaming SVE set FPSIMD get SVE for VL 6064
5303 10:06:58.147234 # ok 3573 Set Streaming SVE VL 6080
5304 10:06:58.147392 # ok 3574 # SKIP Streaming SVE set SVE get SVE for VL 6080
5305 10:06:58.147532 # ok 3575 # SKIP Streaming SVE set SVE get FPSIMD for VL 6080
5306 10:06:58.147649 # ok 3576 # SKIP Streaming SVE set FPSIMD get SVE for VL 6080
5307 10:06:58.147763 # ok 3577 Set Streaming SVE VL 6096
5308 10:06:58.147876 # ok 3578 # SKIP Streaming SVE set SVE get SVE for VL 6096
5309 10:06:58.148018 # ok 3579 # SKIP Streaming SVE set SVE get FPSIMD for VL 6096
5310 10:06:58.148138 # ok 3580 # SKIP Streaming SVE set FPSIMD get SVE for VL 6096
5311 10:06:58.148255 # ok 3581 Set Streaming SVE VL 6112
5312 10:06:58.148369 # ok 3582 # SKIP Streaming SVE set SVE get SVE for VL 6112
5313 10:06:58.148484 # ok 3583 # SKIP Streaming SVE set SVE get FPSIMD for VL 6112
5314 10:06:58.153366 # ok 3584 # SKIP Streaming SVE set FPSIMD get SVE for VL 6112
5315 10:06:58.153668 # ok 3585 Set Streaming SVE VL 6128
5316 10:06:58.153876 # ok 3586 # SKIP Streaming SVE set SVE get SVE for VL 6128
5317 10:06:58.154065 # ok 3587 # SKIP Streaming SVE set SVE get FPSIMD for VL 6128
5318 10:06:58.154221 # ok 3588 # SKIP Streaming SVE set FPSIMD get SVE for VL 6128
5319 10:06:58.154365 # ok 3589 Set Streaming SVE VL 6144
5320 10:06:58.154495 # ok 3590 # SKIP Streaming SVE set SVE get SVE for VL 6144
5321 10:06:58.154665 # ok 3591 # SKIP Streaming SVE set SVE get FPSIMD for VL 6144
5322 10:06:58.154808 # ok 3592 # SKIP Streaming SVE set FPSIMD get SVE for VL 6144
5323 10:06:58.154949 # ok 3593 Set Streaming SVE VL 6160
5324 10:06:58.155065 # ok 3594 # SKIP Streaming SVE set SVE get SVE for VL 6160
5325 10:06:58.155181 # ok 3595 # SKIP Streaming SVE set SVE get FPSIMD for VL 6160
5326 10:06:58.155294 # ok 3596 # SKIP Streaming SVE set FPSIMD get SVE for VL 6160
5327 10:06:58.155454 # ok 3597 Set Streaming SVE VL 6176
5328 10:06:58.155576 # ok 3598 # SKIP Streaming SVE set SVE get SVE for VL 6176
5329 10:06:58.155693 # ok 3599 # SKIP Streaming SVE set SVE get FPSIMD for VL 6176
5330 10:06:58.155808 # ok 3600 # SKIP Streaming SVE set FPSIMD get SVE for VL 6176
5331 10:06:58.155923 # ok 3601 Set Streaming SVE VL 6192
5332 10:06:58.156036 # ok 3602 # SKIP Streaming SVE set SVE get SVE for VL 6192
5333 10:06:58.164963 # ok 3603 # SKIP Streaming SVE set SVE get FPSIMD for VL 6192
5334 10:06:58.165283 # ok 3604 # SKIP Streaming SVE set FPSIMD get SVE for VL 6192
5335 10:06:58.165743 # ok 3605 Set Streaming SVE VL 6208
5336 10:06:58.165951 # ok 3606 # SKIP Streaming SVE set SVE get SVE for VL 6208
5337 10:06:58.166152 # ok 3607 # SKIP Streaming SVE set SVE get FPSIMD for VL 6208
5338 10:06:58.166324 # ok 3608 # SKIP Streaming SVE set FPSIMD get SVE for VL 6208
5339 10:06:58.166485 # ok 3609 Set Streaming SVE VL 6224
5340 10:06:58.166650 # ok 3610 # SKIP Streaming SVE set SVE get SVE for VL 6224
5341 10:06:58.166893 # ok 3611 # SKIP Streaming SVE set SVE get FPSIMD for VL 6224
5342 10:06:58.167070 # ok 3612 # SKIP Streaming SVE set FPSIMD get SVE for VL 6224
5343 10:06:58.167274 # ok 3613 Set Streaming SVE VL 6240
5344 10:06:58.167493 # ok 3614 # SKIP Streaming SVE set SVE get SVE for VL 6240
5345 10:06:58.167627 # ok 3615 # SKIP Streaming SVE set SVE get FPSIMD for VL 6240
5346 10:06:58.167742 # ok 3616 # SKIP Streaming SVE set FPSIMD get SVE for VL 6240
5347 10:06:58.167856 # ok 3617 Set Streaming SVE VL 6256
5348 10:06:58.167968 # ok 3618 # SKIP Streaming SVE set SVE get SVE for VL 6256
5349 10:06:58.168079 # ok 3619 # SKIP Streaming SVE set SVE get FPSIMD for VL 6256
5350 10:06:58.168190 # ok 3620 # SKIP Streaming SVE set FPSIMD get SVE for VL 6256
5351 10:06:58.168301 # ok 3621 Set Streaming SVE VL 6272
5352 10:06:58.168439 # ok 3622 # SKIP Streaming SVE set SVE get SVE for VL 6272
5353 10:06:58.168560 # ok 3623 # SKIP Streaming SVE set SVE get FPSIMD for VL 6272
5354 10:06:58.168673 # ok 3624 # SKIP Streaming SVE set FPSIMD get SVE for VL 6272
5355 10:06:58.168785 # ok 3625 Set Streaming SVE VL 6288
5356 10:06:58.177585 # ok 3626 # SKIP Streaming SVE set SVE get SVE for VL 6288
5357 10:06:58.178160 # ok 3627 # SKIP Streaming SVE set SVE get FPSIMD for VL 6288
5358 10:06:58.178343 # ok 3628 # SKIP Streaming SVE set FPSIMD get SVE for VL 6288
5359 10:06:58.178564 # ok 3629 Set Streaming SVE VL 6304
5360 10:06:58.178763 # ok 3630 # SKIP Streaming SVE set SVE get SVE for VL 6304
5361 10:06:58.178944 # ok 3631 # SKIP Streaming SVE set SVE get FPSIMD for VL 6304
5362 10:06:58.179104 # ok 3632 # SKIP Streaming SVE set FPSIMD get SVE for VL 6304
5363 10:06:58.179287 # ok 3633 Set Streaming SVE VL 6320
5364 10:06:58.179505 # ok 3634 # SKIP Streaming SVE set SVE get SVE for VL 6320
5365 10:06:58.179662 # ok 3635 # SKIP Streaming SVE set SVE get FPSIMD for VL 6320
5366 10:06:58.179805 # ok 3636 # SKIP Streaming SVE set FPSIMD get SVE for VL 6320
5367 10:06:58.179990 # ok 3637 Set Streaming SVE VL 6336
5368 10:06:58.180141 # ok 3638 # SKIP Streaming SVE set SVE get SVE for VL 6336
5369 10:06:58.180266 # ok 3639 # SKIP Streaming SVE set SVE get FPSIMD for VL 6336
5370 10:06:58.180384 # ok 3640 # SKIP Streaming SVE set FPSIMD get SVE for VL 6336
5371 10:06:58.188796 # ok 3641 Set Streaming SVE VL 6352
5372 10:06:58.189363 # ok 3642 # SKIP Streaming SVE set SVE get SVE for VL 6352
5373 10:06:58.189533 # ok 3643 # SKIP Streaming SVE set SVE get FPSIMD for VL 6352
5374 10:06:58.189684 # ok 3644 # SKIP Streaming SVE set FPSIMD get SVE for VL 6352
5375 10:06:58.189814 # ok 3645 Set Streaming SVE VL 6368
5376 10:06:58.189940 # ok 3646 # SKIP Streaming SVE set SVE get SVE for VL 6368
5377 10:06:58.190132 # ok 3647 # SKIP Streaming SVE set SVE get FPSIMD for VL 6368
5378 10:06:58.190325 # ok 3648 # SKIP Streaming SVE set FPSIMD get SVE for VL 6368
5379 10:06:58.190501 # ok 3649 Set Streaming SVE VL 6384
5380 10:06:58.190700 # ok 3650 # SKIP Streaming SVE set SVE get SVE for VL 6384
5381 10:06:58.190873 # ok 3651 # SKIP Streaming SVE set SVE get FPSIMD for VL 6384
5382 10:06:58.191023 # ok 3652 # SKIP Streaming SVE set FPSIMD get SVE for VL 6384
5383 10:06:58.191164 # ok 3653 Set Streaming SVE VL 6400
5384 10:06:58.191337 # ok 3654 # SKIP Streaming SVE set SVE get SVE for VL 6400
5385 10:06:58.191533 # ok 3655 # SKIP Streaming SVE set SVE get FPSIMD for VL 6400
5386 10:06:58.191664 # ok 3656 # SKIP Streaming SVE set FPSIMD get SVE for VL 6400
5387 10:06:58.191778 # ok 3657 Set Streaming SVE VL 6416
5388 10:06:58.191913 # ok 3658 # SKIP Streaming SVE set SVE get SVE for VL 6416
5389 10:06:58.192055 # ok 3659 # SKIP Streaming SVE set SVE get FPSIMD for VL 6416
5390 10:06:58.192171 # ok 3660 # SKIP Streaming SVE set FPSIMD get SVE for VL 6416
5391 10:06:58.192285 # ok 3661 Set Streaming SVE VL 6432
5392 10:06:58.192398 # ok 3662 # SKIP Streaming SVE set SVE get SVE for VL 6432
5393 10:06:58.192510 # ok 3663 # SKIP Streaming SVE set SVE get FPSIMD for VL 6432
5394 10:06:58.192647 # ok 3664 # SKIP Streaming SVE set FPSIMD get SVE for VL 6432
5395 10:06:58.192768 # ok 3665 Set Streaming SVE VL 6448
5396 10:06:58.200924 # ok 3666 # SKIP Streaming SVE set SVE get SVE for VL 6448
5397 10:06:58.201229 # ok 3667 # SKIP Streaming SVE set SVE get FPSIMD for VL 6448
5398 10:06:58.201402 # ok 3668 # SKIP Streaming SVE set FPSIMD get SVE for VL 6448
5399 10:06:58.201607 # ok 3669 Set Streaming SVE VL 6464
5400 10:06:58.201799 # ok 3670 # SKIP Streaming SVE set SVE get SVE for VL 6464
5401 10:06:58.201961 # ok 3671 # SKIP Streaming SVE set SVE get FPSIMD for VL 6464
5402 10:06:58.202101 # ok 3672 # SKIP Streaming SVE set FPSIMD get SVE for VL 6464
5403 10:06:58.202266 # ok 3673 Set Streaming SVE VL 6480
5404 10:06:58.202460 # ok 3674 # SKIP Streaming SVE set SVE get SVE for VL 6480
5405 10:06:58.202644 # ok 3675 # SKIP Streaming SVE set SVE get FPSIMD for VL 6480
5406 10:06:58.202794 # ok 3676 # SKIP Streaming SVE set FPSIMD get SVE for VL 6480
5407 10:06:58.202950 # ok 3677 Set Streaming SVE VL 6496
5408 10:06:58.203096 # ok 3678 # SKIP Streaming SVE set SVE get SVE for VL 6496
5409 10:06:58.203252 # ok 3679 # SKIP Streaming SVE set SVE get FPSIMD for VL 6496
5410 10:06:58.203412 # ok 3680 # SKIP Streaming SVE set FPSIMD get SVE for VL 6496
5411 10:06:58.203546 # ok 3681 Set Streaming SVE VL 6512
5412 10:06:58.203659 # ok 3682 # SKIP Streaming SVE set SVE get SVE for VL 6512
5413 10:06:58.203773 # ok 3683 # SKIP Streaming SVE set SVE get FPSIMD for VL 6512
5414 10:06:58.203915 # ok 3684 # SKIP Streaming SVE set FPSIMD get SVE for VL 6512
5415 10:06:58.204035 # ok 3685 Set Streaming SVE VL 6528
5416 10:06:58.204150 # ok 3686 # SKIP Streaming SVE set SVE get SVE for VL 6528
5417 10:06:58.204262 # ok 3687 # SKIP Streaming SVE set SVE get FPSIMD for VL 6528
5418 10:06:58.204376 # ok 3688 # SKIP Streaming SVE set FPSIMD get SVE for VL 6528
5419 10:06:58.204490 # ok 3689 Set Streaming SVE VL 6544
5420 10:06:58.212829 # ok 3690 # SKIP Streaming SVE set SVE get SVE for VL 6544
5421 10:06:58.213377 # ok 3691 # SKIP Streaming SVE set SVE get FPSIMD for VL 6544
5422 10:06:58.213573 # ok 3692 # SKIP Streaming SVE set FPSIMD get SVE for VL 6544
5423 10:06:58.213791 # ok 3693 Set Streaming SVE VL 6560
5424 10:06:58.213976 # ok 3694 # SKIP Streaming SVE set SVE get SVE for VL 6560
5425 10:06:58.214152 # ok 3695 # SKIP Streaming SVE set SVE get FPSIMD for VL 6560
5426 10:06:58.214366 # ok 3696 # SKIP Streaming SVE set FPSIMD get SVE for VL 6560
5427 10:06:58.214524 # ok 3697 Set Streaming SVE VL 6576
5428 10:06:58.214652 # ok 3698 # SKIP Streaming SVE set SVE get SVE for VL 6576
5429 10:06:58.214792 # ok 3699 # SKIP Streaming SVE set SVE get FPSIMD for VL 6576
5430 10:06:58.214963 # ok 3700 # SKIP Streaming SVE set FPSIMD get SVE for VL 6576
5431 10:06:58.215136 # ok 3701 Set Streaming SVE VL 6592
5432 10:06:58.215268 # ok 3702 # SKIP Streaming SVE set SVE get SVE for VL 6592
5433 10:06:58.215450 # ok 3703 # SKIP Streaming SVE set SVE get FPSIMD for VL 6592
5434 10:06:58.215592 # ok 3704 # SKIP Streaming SVE set FPSIMD get SVE for VL 6592
5435 10:06:58.215708 # ok 3705 Set Streaming SVE VL 6608
5436 10:06:58.215820 # ok 3706 # SKIP Streaming SVE set SVE get SVE for VL 6608
5437 10:06:58.215944 # ok 3707 # SKIP Streaming SVE set SVE get FPSIMD for VL 6608
5438 10:06:58.216058 # ok 3708 # SKIP Streaming SVE set FPSIMD get SVE for VL 6608
5439 10:06:58.216169 # ok 3709 Set Streaming SVE VL 6624
5440 10:06:58.216280 # ok 3710 # SKIP Streaming SVE set SVE get SVE for VL 6624
5441 10:06:58.224964 # ok 3711 # SKIP Streaming SVE set SVE get FPSIMD for VL 6624
5442 10:06:58.225561 # ok 3712 # SKIP Streaming SVE set FPSIMD get SVE for VL 6624
5443 10:06:58.225758 # ok 3713 Set Streaming SVE VL 6640
5444 10:06:58.225911 # ok 3714 # SKIP Streaming SVE set SVE get SVE for VL 6640
5445 10:06:58.226058 # ok 3715 # SKIP Streaming SVE set SVE get FPSIMD for VL 6640
5446 10:06:58.226174 # ok 3716 # SKIP Streaming SVE set FPSIMD get SVE for VL 6640
5447 10:06:58.226329 # ok 3717 Set Streaming SVE VL 6656
5448 10:06:58.226525 # ok 3718 # SKIP Streaming SVE set SVE get SVE for VL 6656
5449 10:06:58.226686 # ok 3719 # SKIP Streaming SVE set SVE get FPSIMD for VL 6656
5450 10:06:58.226823 # ok 3720 # SKIP Streaming SVE set FPSIMD get SVE for VL 6656
5451 10:06:58.226971 # ok 3721 Set Streaming SVE VL 6672
5452 10:06:58.227115 # ok 3722 # SKIP Streaming SVE set SVE get SVE for VL 6672
5453 10:06:58.227255 # ok 3723 # SKIP Streaming SVE set SVE get FPSIMD for VL 6672
5454 10:06:58.227392 # ok 3724 # SKIP Streaming SVE set FPSIMD get SVE for VL 6672
5455 10:06:58.227567 # ok 3725 Set Streaming SVE VL 6688
5456 10:06:58.227721 # ok 3726 # SKIP Streaming SVE set SVE get SVE for VL 6688
5457 10:06:58.227840 # ok 3727 # SKIP Streaming SVE set SVE get FPSIMD for VL 6688
5458 10:06:58.227991 # ok 3728 # SKIP Streaming SVE set FPSIMD get SVE for VL 6688
5459 10:06:58.228120 # ok 3729 Set Streaming SVE VL 6704
5460 10:06:58.228234 # ok 3730 # SKIP Streaming SVE set SVE get SVE for VL 6704
5461 10:06:58.228346 # ok 3731 # SKIP Streaming SVE set SVE get FPSIMD for VL 6704
5462 10:06:58.228460 # ok 3732 # SKIP Streaming SVE set FPSIMD get SVE for VL 6704
5463 10:06:58.233738 # ok 3733 Set Streaming SVE VL 6720
5464 10:06:58.234206 # ok 3734 # SKIP Streaming SVE set SVE get SVE for VL 6720
5465 10:06:58.234414 # ok 3735 # SKIP Streaming SVE set SVE get FPSIMD for VL 6720
5466 10:06:58.234616 # ok 3736 # SKIP Streaming SVE set FPSIMD get SVE for VL 6720
5467 10:06:58.234748 # ok 3737 Set Streaming SVE VL 6736
5468 10:06:58.235332 # ok 3738 # SKIP Streaming SVE set SVE get SVE for VL 6736
5469 10:06:58.241308 # ok 3739 # SKIP Streaming SVE set SVE get FPSIMD for VL 6736
5470 10:06:58.242132 # ok 3740 # SKIP Streaming SVE set FPSIMD get SVE for VL 6736
5471 10:06:58.242320 # ok 3741 Set Streaming SVE VL 6752
5472 10:06:58.242549 # ok 3742 # SKIP Streaming SVE set SVE get SVE for VL 6752
5473 10:06:58.242740 # ok 3743 # SKIP Streaming SVE set SVE get FPSIMD for VL 6752
5474 10:06:58.242916 # ok 3744 # SKIP Streaming SVE set FPSIMD get SVE for VL 6752
5475 10:06:58.243121 # ok 3745 Set Streaming SVE VL 6768
5476 10:06:58.243279 # ok 3746 # SKIP Streaming SVE set SVE get SVE for VL 6768
5477 10:06:58.243447 # ok 3747 # SKIP Streaming SVE set SVE get FPSIMD for VL 6768
5478 10:06:58.243618 # ok 3748 # SKIP Streaming SVE set FPSIMD get SVE for VL 6768
5479 10:06:58.243830 # ok 3749 Set Streaming SVE VL 6784
5480 10:06:58.243996 # ok 3750 # SKIP Streaming SVE set SVE get SVE for VL 6784
5481 10:06:58.244128 # ok 3751 # SKIP Streaming SVE set SVE get FPSIMD for VL 6784
5482 10:06:58.244285 # ok 3752 # SKIP Streaming SVE set FPSIMD get SVE for VL 6784
5483 10:06:58.244470 # ok 3753 Set Streaming SVE VL 6800
5484 10:06:58.244635 # ok 3754 # SKIP Streaming SVE set SVE get SVE for VL 6800
5485 10:06:58.244789 # ok 3755 # SKIP Streaming SVE set SVE get FPSIMD for VL 6800
5486 10:06:58.244938 # ok 3756 # SKIP Streaming SVE set FPSIMD get SVE for VL 6800
5487 10:06:58.245120 # ok 3757 Set Streaming SVE VL 6816
5488 10:06:58.245383 # ok 3758 # SKIP Streaming SVE set SVE get SVE for VL 6816
5489 10:06:58.245555 # ok 3759 # SKIP Streaming SVE set SVE get FPSIMD for VL 6816
5490 10:06:58.245743 # ok 3760 # SKIP Streaming SVE set FPSIMD get SVE for VL 6816
5491 10:06:58.245940 # ok 3761 Set Streaming SVE VL 6832
5492 10:06:58.246121 # ok 3762 # SKIP Streaming SVE set SVE get SVE for VL 6832
5493 10:06:58.246303 # ok 3763 # SKIP Streaming SVE set SVE get FPSIMD for VL 6832
5494 10:06:58.246500 # ok 3764 # SKIP Streaming SVE set FPSIMD get SVE for VL 6832
5495 10:06:58.246709 # ok 3765 Set Streaming SVE VL 6848
5496 10:06:58.246838 # ok 3766 # SKIP Streaming SVE set SVE get SVE for VL 6848
5497 10:06:58.246955 # ok 3767 # SKIP Streaming SVE set SVE get FPSIMD for VL 6848
5498 10:06:58.247070 # ok 3768 # SKIP Streaming SVE set FPSIMD get SVE for VL 6848
5499 10:06:58.247184 # ok 3769 Set Streaming SVE VL 6864
5500 10:06:58.247297 # ok 3770 # SKIP Streaming SVE set SVE get SVE for VL 6864
5501 10:06:58.247458 # ok 3771 # SKIP Streaming SVE set SVE get FPSIMD for VL 6864
5502 10:06:58.247598 # ok 3772 # SKIP Streaming SVE set FPSIMD get SVE for VL 6864
5503 10:06:58.247716 # ok 3773 Set Streaming SVE VL 6880
5504 10:06:58.247830 # ok 3774 # SKIP Streaming SVE set SVE get SVE for VL 6880
5505 10:06:58.289596 # ok 3775 # SKIP Streaming SVE set SVE get FPSIMD for VL 6880
5506 10:06:58.290162 # ok 3776 # SKIP Streaming SVE set FPSIMD get SVE for VL 6880
5507 10:06:58.290368 # ok 3777 Set Streaming SVE VL 6896
5508 10:06:58.290548 # ok 3778 # SKIP Streaming SVE set SVE get SVE for VL 6896
5509 10:06:58.290763 # ok 3779 # SKIP Streaming SVE set SVE get FPSIMD for VL 6896
5510 10:06:58.291021 # ok 3780 # SKIP Streaming SVE set FPSIMD get SVE for VL 6896
5511 10:06:58.291202 # ok 3781 Set Streaming SVE VL 6912
5512 10:06:58.291359 # ok 3782 # SKIP Streaming SVE set SVE get SVE for VL 6912
5513 10:06:58.291492 # ok 3783 # SKIP Streaming SVE set SVE get FPSIMD for VL 6912
5514 10:06:58.291621 # ok 3784 # SKIP Streaming SVE set FPSIMD get SVE for VL 6912
5515 10:06:58.291768 # ok 3785 Set Streaming SVE VL 6928
5516 10:06:58.291884 # ok 3786 # SKIP Streaming SVE set SVE get SVE for VL 6928
5517 10:06:58.292021 # ok 3787 # SKIP Streaming SVE set SVE get FPSIMD for VL 6928
5518 10:06:58.292136 # ok 3788 # SKIP Streaming SVE set FPSIMD get SVE for VL 6928
5519 10:06:58.292247 # ok 3789 Set Streaming SVE VL 6944
5520 10:06:58.292355 # ok 3790 # SKIP Streaming SVE set SVE get SVE for VL 6944
5521 10:06:58.299884 # ok 3791 # SKIP Streaming SVE set SVE get FPSIMD for VL 6944
5522 10:06:58.300368 # ok 3792 # SKIP Streaming SVE set FPSIMD get SVE for VL 6944
5523 10:06:58.300564 # ok 3793 Set Streaming SVE VL 6960
5524 10:06:58.300768 # ok 3794 # SKIP Streaming SVE set SVE get SVE for VL 6960
5525 10:06:58.300962 # ok 3795 # SKIP Streaming SVE set SVE get FPSIMD for VL 6960
5526 10:06:58.301178 # ok 3796 # SKIP Streaming SVE set FPSIMD get SVE for VL 6960
5527 10:06:58.301371 # ok 3797 Set Streaming SVE VL 6976
5528 10:06:58.301591 # ok 3798 # SKIP Streaming SVE set SVE get SVE for VL 6976
5529 10:06:58.301790 # ok 3799 # SKIP Streaming SVE set SVE get FPSIMD for VL 6976
5530 10:06:58.301950 # ok 3800 # SKIP Streaming SVE set FPSIMD get SVE for VL 6976
5531 10:06:58.302109 # ok 3801 Set Streaming SVE VL 6992
5532 10:06:58.302267 # ok 3802 # SKIP Streaming SVE set SVE get SVE for VL 6992
5533 10:06:58.302430 # ok 3803 # SKIP Streaming SVE set SVE get FPSIMD for VL 6992
5534 10:06:58.302567 # ok 3804 # SKIP Streaming SVE set FPSIMD get SVE for VL 6992
5535 10:06:58.302788 # ok 3805 Set Streaming SVE VL 7008
5536 10:06:58.303011 # ok 3806 # SKIP Streaming SVE set SVE get SVE for VL 7008
5537 10:06:58.303193 # ok 3807 # SKIP Streaming SVE set SVE get FPSIMD for VL 7008
5538 10:06:58.303401 # ok 3808 # SKIP Streaming SVE set FPSIMD get SVE for VL 7008
5539 10:06:58.303571 # ok 3809 Set Streaming SVE VL 7024
5540 10:06:58.303696 # ok 3810 # SKIP Streaming SVE set SVE get SVE for VL 7024
5541 10:06:58.303813 # ok 3811 # SKIP Streaming SVE set SVE get FPSIMD for VL 7024
5542 10:06:58.303927 # ok 3812 # SKIP Streaming SVE set FPSIMD get SVE for VL 7024
5543 10:06:58.304072 # ok 3813 Set Streaming SVE VL 7040
5544 10:06:58.304195 # ok 3814 # SKIP Streaming SVE set SVE get SVE for VL 7040
5545 10:06:58.304310 # ok 3815 # SKIP Streaming SVE set SVE get FPSIMD for VL 7040
5546 10:06:58.304426 # ok 3816 # SKIP Streaming SVE set FPSIMD get SVE for VL 7040
5547 10:06:58.304543 # ok 3817 Set Streaming SVE VL 7056
5548 10:06:58.304656 # ok 3818 # SKIP Streaming SVE set SVE get SVE for VL 7056
5549 10:06:58.304771 # ok 3819 # SKIP Streaming SVE set SVE get FPSIMD for VL 7056
5550 10:06:58.305433 # ok 3820 # SKIP Streaming SVE set FPSIMD get SVE for VL 7056
5551 10:06:58.305778 # ok 3821 Set Streaming SVE VL 7072
5552 10:06:58.305889 # ok 3822 # SKIP Streaming SVE set SVE get SVE for VL 7072
5553 10:06:58.305981 # ok 3823 # SKIP Streaming SVE set SVE get FPSIMD for VL 7072
5554 10:06:58.306083 # ok 3824 # SKIP Streaming SVE set FPSIMD get SVE for VL 7072
5555 10:06:58.306171 # ok 3825 Set Streaming SVE VL 7088
5556 10:06:58.306270 # ok 3826 # SKIP Streaming SVE set SVE get SVE for VL 7088
5557 10:06:58.306372 # ok 3827 # SKIP Streaming SVE set SVE get FPSIMD for VL 7088
5558 10:06:58.306661 # ok 3828 # SKIP Streaming SVE set FPSIMD get SVE for VL 7088
5559 10:06:58.306754 # ok 3829 Set Streaming SVE VL 7104
5560 10:06:58.306856 # ok 3830 # SKIP Streaming SVE set SVE get SVE for VL 7104
5561 10:06:58.306958 # ok 3831 # SKIP Streaming SVE set SVE get FPSIMD for VL 7104
5562 10:06:58.307291 # ok 3832 # SKIP Streaming SVE set FPSIMD get SVE for VL 7104
5563 10:06:58.307476 # ok 3833 Set Streaming SVE VL 7120
5564 10:06:58.307607 # ok 3834 # SKIP Streaming SVE set SVE get SVE for VL 7120
5565 10:06:58.307748 # ok 3835 # SKIP Streaming SVE set SVE get FPSIMD for VL 7120
5566 10:06:58.314914 # ok 3836 # SKIP Streaming SVE set FPSIMD get SVE for VL 7120
5567 10:06:58.315461 # ok 3837 Set Streaming SVE VL 7136
5568 10:06:58.315621 # ok 3838 # SKIP Streaming SVE set SVE get SVE for VL 7136
5569 10:06:58.315742 # ok 3839 # SKIP Streaming SVE set SVE get FPSIMD for VL 7136
5570 10:06:58.315858 # ok 3840 # SKIP Streaming SVE set FPSIMD get SVE for VL 7136
5571 10:06:58.315973 # ok 3841 Set Streaming SVE VL 7152
5572 10:06:58.317995 # ok 3842 # SKIP Streaming SVE set SVE get SVE for VL 7152
5573 10:06:58.318426 # ok 3843 # SKIP Streaming SVE set SVE get FPSIMD for VL 7152
5574 10:06:58.318614 # ok 3844 # SKIP Streaming SVE set FPSIMD get SVE for VL 7152
5575 10:06:58.318768 # ok 3845 Set Streaming SVE VL 7168
5576 10:06:58.318914 # ok 3846 # SKIP Streaming SVE set SVE get SVE for VL 7168
5577 10:06:58.319096 # ok 3847 # SKIP Streaming SVE set SVE get FPSIMD for VL 7168
5578 10:06:58.319251 # ok 3848 # SKIP Streaming SVE set FPSIMD get SVE for VL 7168
5579 10:06:58.319402 # ok 3849 Set Streaming SVE VL 7184
5580 10:06:58.319545 # ok 3850 # SKIP Streaming SVE set SVE get SVE for VL 7184
5581 10:06:58.319660 # ok 3851 # SKIP Streaming SVE set SVE get FPSIMD for VL 7184
5582 10:06:58.319796 # ok 3852 # SKIP Streaming SVE set FPSIMD get SVE for VL 7184
5583 10:06:58.319911 # ok 3853 Set Streaming SVE VL 7200
5584 10:06:58.320022 # ok 3854 # SKIP Streaming SVE set SVE get SVE for VL 7200
5585 10:06:58.328538 # ok 3855 # SKIP Streaming SVE set SVE get FPSIMD for VL 7200
5586 10:06:58.329077 # ok 3856 # SKIP Streaming SVE set FPSIMD get SVE for VL 7200
5587 10:06:58.329255 # ok 3857 Set Streaming SVE VL 7216
5588 10:06:58.329411 # ok 3858 # SKIP Streaming SVE set SVE get SVE for VL 7216
5589 10:06:58.329558 # ok 3859 # SKIP Streaming SVE set SVE get FPSIMD for VL 7216
5590 10:06:58.329715 # ok 3860 # SKIP Streaming SVE set FPSIMD get SVE for VL 7216
5591 10:06:58.329868 # ok 3861 Set Streaming SVE VL 7232
5592 10:06:58.330036 # ok 3862 # SKIP Streaming SVE set SVE get SVE for VL 7232
5593 10:06:58.330199 # ok 3863 # SKIP Streaming SVE set SVE get FPSIMD for VL 7232
5594 10:06:58.330349 # ok 3864 # SKIP Streaming SVE set FPSIMD get SVE for VL 7232
5595 10:06:58.330506 # ok 3865 Set Streaming SVE VL 7248
5596 10:06:58.330700 # ok 3866 # SKIP Streaming SVE set SVE get SVE for VL 7248
5597 10:06:58.330873 # ok 3867 # SKIP Streaming SVE set SVE get FPSIMD for VL 7248
5598 10:06:58.331056 # ok 3868 # SKIP Streaming SVE set FPSIMD get SVE for VL 7248
5599 10:06:58.331256 # ok 3869 Set Streaming SVE VL 7264
5600 10:06:58.331457 # ok 3870 # SKIP Streaming SVE set SVE get SVE for VL 7264
5601 10:06:58.331594 # ok 3871 # SKIP Streaming SVE set SVE get FPSIMD for VL 7264
5602 10:06:58.331716 # ok 3872 # SKIP Streaming SVE set FPSIMD get SVE for VL 7264
5603 10:06:58.331828 # ok 3873 Set Streaming SVE VL 7280
5604 10:06:58.331942 # ok 3874 # SKIP Streaming SVE set SVE get SVE for VL 7280
5605 10:06:58.332053 # ok 3875 # SKIP Streaming SVE set SVE get FPSIMD for VL 7280
5606 10:06:58.332164 # ok 3876 # SKIP Streaming SVE set FPSIMD get SVE for VL 7280
5607 10:06:58.332275 # ok 3877 Set Streaming SVE VL 7296
5608 10:06:58.332412 # ok 3878 # SKIP Streaming SVE set SVE get SVE for VL 7296
5609 10:06:58.332530 # ok 3879 # SKIP Streaming SVE set SVE get FPSIMD for VL 7296
5610 10:06:58.341621 # ok 3880 # SKIP Streaming SVE set FPSIMD get SVE for VL 7296
5611 10:06:58.341924 # ok 3881 Set Streaming SVE VL 7312
5612 10:06:58.342371 # ok 3882 # SKIP Streaming SVE set SVE get SVE for VL 7312
5613 10:06:58.342553 # ok 3883 # SKIP Streaming SVE set SVE get FPSIMD for VL 7312
5614 10:06:58.342704 # ok 3884 # SKIP Streaming SVE set FPSIMD get SVE for VL 7312
5615 10:06:58.342847 # ok 3885 Set Streaming SVE VL 7328
5616 10:06:58.342990 # ok 3886 # SKIP Streaming SVE set SVE get SVE for VL 7328
5617 10:06:58.343359 # ok 3887 # SKIP Streaming SVE set SVE get FPSIMD for VL 7328
5618 10:06:58.343492 # ok 3888 # SKIP Streaming SVE set FPSIMD get SVE for VL 7328
5619 10:06:58.343603 # ok 3889 Set Streaming SVE VL 7344
5620 10:06:58.343690 # ok 3890 # SKIP Streaming SVE set SVE get SVE for VL 7344
5621 10:06:58.343770 # ok 3891 # SKIP Streaming SVE set SVE get FPSIMD for VL 7344
5622 10:06:58.343844 # ok 3892 # SKIP Streaming SVE set FPSIMD get SVE for VL 7344
5623 10:06:58.343920 # ok 3893 Set Streaming SVE VL 7360
5624 10:06:58.343998 # ok 3894 # SKIP Streaming SVE set SVE get SVE for VL 7360
5625 10:06:58.344092 # ok 3895 # SKIP Streaming SVE set SVE get FPSIMD for VL 7360
5626 10:06:58.348830 # ok 3896 # SKIP Streaming SVE set FPSIMD get SVE for VL 7360
5627 10:06:58.349313 # ok 3897 Set Streaming SVE VL 7376
5628 10:06:58.349502 # ok 3898 # SKIP Streaming SVE set SVE get SVE for VL 7376
5629 10:06:58.349688 # ok 3899 # SKIP Streaming SVE set SVE get FPSIMD for VL 7376
5630 10:06:58.349845 # ok 3900 # SKIP Streaming SVE set FPSIMD get SVE for VL 7376
5631 10:06:58.350019 # ok 3901 Set Streaming SVE VL 7392
5632 10:06:58.350165 # ok 3902 # SKIP Streaming SVE set SVE get SVE for VL 7392
5633 10:06:58.350308 # ok 3903 # SKIP Streaming SVE set SVE get FPSIMD for VL 7392
5634 10:06:58.350451 # ok 3904 # SKIP Streaming SVE set FPSIMD get SVE for VL 7392
5635 10:06:58.350600 # ok 3905 Set Streaming SVE VL 7408
5636 10:06:58.350777 # ok 3906 # SKIP Streaming SVE set SVE get SVE for VL 7408
5637 10:06:58.350934 # ok 3907 # SKIP Streaming SVE set SVE get FPSIMD for VL 7408
5638 10:06:58.351081 # ok 3908 # SKIP Streaming SVE set FPSIMD get SVE for VL 7408
5639 10:06:58.351227 # ok 3909 Set Streaming SVE VL 7424
5640 10:06:58.351372 # ok 3910 # SKIP Streaming SVE set SVE get SVE for VL 7424
5641 10:06:58.351518 # ok 3911 # SKIP Streaming SVE set SVE get FPSIMD for VL 7424
5642 10:06:58.351694 # ok 3912 # SKIP Streaming SVE set FPSIMD get SVE for VL 7424
5643 10:06:58.351845 # ok 3913 Set Streaming SVE VL 7440
5644 10:06:58.351992 # ok 3914 # SKIP Streaming SVE set SVE get SVE for VL 7440
5645 10:06:58.352138 # ok 3915 # SKIP Streaming SVE set SVE get FPSIMD for VL 7440
5646 10:06:58.356421 # ok 3916 # SKIP Streaming SVE set FPSIMD get SVE for VL 7440
5647 10:06:58.356871 # ok 3917 Set Streaming SVE VL 7456
5648 10:06:58.357000 # ok 3918 # SKIP Streaming SVE set SVE get SVE for VL 7456
5649 10:06:58.357149 # ok 3919 # SKIP Streaming SVE set SVE get FPSIMD for VL 7456
5650 10:06:58.357290 # ok 3920 # SKIP Streaming SVE set FPSIMD get SVE for VL 7456
5651 10:06:58.357439 # ok 3921 Set Streaming SVE VL 7472
5652 10:06:58.357567 # ok 3922 # SKIP Streaming SVE set SVE get SVE for VL 7472
5653 10:06:58.357705 # ok 3923 # SKIP Streaming SVE set SVE get FPSIMD for VL 7472
5654 10:06:58.357827 # ok 3924 # SKIP Streaming SVE set FPSIMD get SVE for VL 7472
5655 10:06:58.358656 # ok 3925 Set Streaming SVE VL 7488
5656 10:06:58.359059 # ok 3926 # SKIP Streaming SVE set SVE get SVE for VL 7488
5657 10:06:58.359165 # ok 3927 # SKIP Streaming SVE set SVE get FPSIMD for VL 7488
5658 10:06:58.359269 # ok 3928 # SKIP Streaming SVE set FPSIMD get SVE for VL 7488
5659 10:06:58.359353 # ok 3929 Set Streaming SVE VL 7504
5660 10:06:58.359452 # ok 3930 # SKIP Streaming SVE set SVE get SVE for VL 7504
5661 10:06:58.363910 # ok 3931 # SKIP Streaming SVE set SVE get FPSIMD for VL 7504
5662 10:06:58.364305 # ok 3932 # SKIP Streaming SVE set FPSIMD get SVE for VL 7504
5663 10:06:58.364446 # ok 3933 Set Streaming SVE VL 7520
5664 10:06:58.364588 # ok 3934 # SKIP Streaming SVE set SVE get SVE for VL 7520
5665 10:06:58.364709 # ok 3935 # SKIP Streaming SVE set SVE get FPSIMD for VL 7520
5666 10:06:58.364856 # ok 3936 # SKIP Streaming SVE set FPSIMD get SVE for VL 7520
5667 10:06:58.364986 # ok 3937 Set Streaming SVE VL 7536
5668 10:06:58.365117 # ok 3938 # SKIP Streaming SVE set SVE get SVE for VL 7536
5669 10:06:58.365264 # ok 3939 # SKIP Streaming SVE set SVE get FPSIMD for VL 7536
5670 10:06:58.365424 # ok 3940 # SKIP Streaming SVE set FPSIMD get SVE for VL 7536
5671 10:06:58.365621 # ok 3941 Set Streaming SVE VL 7552
5672 10:06:58.365799 # ok 3942 # SKIP Streaming SVE set SVE get SVE for VL 7552
5673 10:06:58.365946 # ok 3943 # SKIP Streaming SVE set SVE get FPSIMD for VL 7552
5674 10:06:58.366075 # ok 3944 # SKIP Streaming SVE set FPSIMD get SVE for VL 7552
5675 10:06:58.366223 # ok 3945 Set Streaming SVE VL 7568
5676 10:06:58.366366 # ok 3946 # SKIP Streaming SVE set SVE get SVE for VL 7568
5677 10:06:58.366512 # ok 3947 # SKIP Streaming SVE set SVE get FPSIMD for VL 7568
5678 10:06:58.366683 # ok 3948 # SKIP Streaming SVE set FPSIMD get SVE for VL 7568
5679 10:06:58.366818 # ok 3949 Set Streaming SVE VL 7584
5680 10:06:58.366973 # ok 3950 # SKIP Streaming SVE set SVE get SVE for VL 7584
5681 10:06:58.367091 # ok 3951 # SKIP Streaming SVE set SVE get FPSIMD for VL 7584
5682 10:06:58.367203 # ok 3952 # SKIP Streaming SVE set FPSIMD get SVE for VL 7584
5683 10:06:58.367344 # ok 3953 Set Streaming SVE VL 7600
5684 10:06:58.367529 # ok 3954 # SKIP Streaming SVE set SVE get SVE for VL 7600
5685 10:06:58.367677 # ok 3955 # SKIP Streaming SVE set SVE get FPSIMD for VL 7600
5686 10:06:58.367798 # ok 3956 # SKIP Streaming SVE set FPSIMD get SVE for VL 7600
5687 10:06:58.367913 # ok 3957 Set Streaming SVE VL 7616
5688 10:06:58.368053 # ok 3958 # SKIP Streaming SVE set SVE get SVE for VL 7616
5689 10:06:58.368174 # ok 3959 # SKIP Streaming SVE set SVE get FPSIMD for VL 7616
5690 10:06:58.368288 # ok 3960 # SKIP Streaming SVE set FPSIMD get SVE for VL 7616
5691 10:06:58.368401 # ok 3961 Set Streaming SVE VL 7632
5692 10:06:58.368512 # ok 3962 # SKIP Streaming SVE set SVE get SVE for VL 7632
5693 10:06:58.368624 # ok 3963 # SKIP Streaming SVE set SVE get FPSIMD for VL 7632
5694 10:06:58.371701 # ok 3964 # SKIP Streaming SVE set FPSIMD get SVE for VL 7632
5695 10:06:58.372056 # ok 3965 Set Streaming SVE VL 7648
5696 10:06:58.372161 # ok 3966 # SKIP Streaming SVE set SVE get SVE for VL 7648
5697 10:06:58.372249 # ok 3967 # SKIP Streaming SVE set SVE get FPSIMD for VL 7648
5698 10:06:58.372353 # ok 3968 # SKIP Streaming SVE set FPSIMD get SVE for VL 7648
5699 10:06:58.372442 # ok 3969 Set Streaming SVE VL 7664
5700 10:06:58.372543 # ok 3970 # SKIP Streaming SVE set SVE get SVE for VL 7664
5701 10:06:58.372632 # ok 3971 # SKIP Streaming SVE set SVE get FPSIMD for VL 7664
5702 10:06:58.372917 # ok 3972 # SKIP Streaming SVE set FPSIMD get SVE for VL 7664
5703 10:06:58.373023 # ok 3973 Set Streaming SVE VL 7680
5704 10:06:58.373109 # ok 3974 # SKIP Streaming SVE set SVE get SVE for VL 7680
5705 10:06:58.373194 # ok 3975 # SKIP Streaming SVE set SVE get FPSIMD for VL 7680
5706 10:06:58.373293 # ok 3976 # SKIP Streaming SVE set FPSIMD get SVE for VL 7680
5707 10:06:58.373391 # ok 3977 Set Streaming SVE VL 7696
5708 10:06:58.373683 # ok 3978 # SKIP Streaming SVE set SVE get SVE for VL 7696
5709 10:06:58.373775 # ok 3979 # SKIP Streaming SVE set SVE get FPSIMD for VL 7696
5710 10:06:58.373872 # ok 3980 # SKIP Streaming SVE set FPSIMD get SVE for VL 7696
5711 10:06:58.373957 # ok 3981 Set Streaming SVE VL 7712
5712 10:06:58.374052 # ok 3982 # SKIP Streaming SVE set SVE get SVE for VL 7712
5713 10:06:58.374340 # ok 3983 # SKIP Streaming SVE set SVE get FPSIMD for VL 7712
5714 10:06:58.374428 # ok 3984 # SKIP Streaming SVE set FPSIMD get SVE for VL 7712
5715 10:06:58.374524 # ok 3985 Set Streaming SVE VL 7728
5716 10:06:58.374810 # ok 3986 # SKIP Streaming SVE set SVE get SVE for VL 7728
5717 10:06:58.374910 # ok 3987 # SKIP Streaming SVE set SVE get FPSIMD for VL 7728
5718 10:06:58.374993 # ok 3988 # SKIP Streaming SVE set FPSIMD get SVE for VL 7728
5719 10:06:58.375076 # ok 3989 Set Streaming SVE VL 7744
5720 10:06:58.375172 # ok 3990 # SKIP Streaming SVE set SVE get SVE for VL 7744
5721 10:06:58.375268 # ok 3991 # SKIP Streaming SVE set SVE get FPSIMD for VL 7744
5722 10:06:58.375554 # ok 3992 # SKIP Streaming SVE set FPSIMD get SVE for VL 7744
5723 10:06:58.558135 # ok 3993 Set Streaming SVE VL 7760
5724 10:06:58.558450 # ok 3994 # SKIP Streaming SVE set SVE get SVE for VL 7760
5725 10:06:58.558819 # ok 3995 # SKIP Streaming SVE set SVE get FPSIMD for VL 7760
5726 10:06:58.558930 # ok 3996 # SKIP Streaming SVE set FPSIMD get SVE for VL 7760
5727 10:06:58.559019 # ok 3997 Set Streaming SVE VL 7776
5728 10:06:58.559106 # ok 3998 # SKIP Streaming SVE set SVE get SVE for VL 7776
5729 10:06:58.559188 # ok 3999 # SKIP Streaming SVE set SVE get FPSIMD for VL 7776
5730 10:06:58.559268 # ok 4000 # SKIP Streaming SVE set FPSIMD get SVE for VL 7776
5731 10:06:58.559386 # ok 4001 Set Streaming SVE VL 7792
5732 10:06:58.559477 # ok 4002 # SKIP Streaming SVE set SVE get SVE for VL 7792
5733 10:06:58.559559 # ok 4003 # SKIP Streaming SVE set SVE get FPSIMD for VL 7792
5734 10:06:58.559640 # ok 4004 # SKIP Streaming SVE set FPSIMD get SVE for VL 7792
5735 10:06:58.559736 # ok 4005 Set Streaming SVE VL 7808
5736 10:06:58.559834 # ok 4006 # SKIP Streaming SVE set SVE get SVE for VL 7808
5737 10:06:58.560173 # ok 4007 # SKIP Streaming SVE set SVE get FPSIMD for VL 7808
5738 10:06:58.560372 # ok 4008 # SKIP Streaming SVE set FPSIMD get SVE for VL 7808
5739 10:06:58.560558 # ok 4009 Set Streaming SVE VL 7824
5740 10:06:58.560720 # ok 4010 # SKIP Streaming SVE set SVE get SVE for VL 7824
5741 10:06:58.560868 # ok 4011 # SKIP Streaming SVE set SVE get FPSIMD for VL 7824
5742 10:06:58.561059 # ok 4012 # SKIP Streaming SVE set FPSIMD get SVE for VL 7824
5743 10:06:58.561221 # ok 4013 Set Streaming SVE VL 7840
5744 10:06:58.561368 # ok 4014 # SKIP Streaming SVE set SVE get SVE for VL 7840
5745 10:06:58.561520 # ok 4015 # SKIP Streaming SVE set SVE get FPSIMD for VL 7840
5746 10:06:58.561700 # ok 4016 # SKIP Streaming SVE set FPSIMD get SVE for VL 7840
5747 10:06:58.561864 # ok 4017 Set Streaming SVE VL 7856
5748 10:06:58.562024 # ok 4018 # SKIP Streaming SVE set SVE get SVE for VL 7856
5749 10:06:58.562186 # ok 4019 # SKIP Streaming SVE set SVE get FPSIMD for VL 7856
5750 10:06:58.562335 # ok 4020 # SKIP Streaming SVE set FPSIMD get SVE for VL 7856
5751 10:06:58.562495 # ok 4021 Set Streaming SVE VL 7872
5752 10:06:58.562690 # ok 4022 # SKIP Streaming SVE set SVE get SVE for VL 7872
5753 10:06:58.562854 # ok 4023 # SKIP Streaming SVE set SVE get FPSIMD for VL 7872
5754 10:06:58.563007 # ok 4024 # SKIP Streaming SVE set FPSIMD get SVE for VL 7872
5755 10:06:58.563166 # ok 4025 Set Streaming SVE VL 7888
5756 10:06:58.563331 # ok 4026 # SKIP Streaming SVE set SVE get SVE for VL 7888
5757 10:06:58.563517 # ok 4027 # SKIP Streaming SVE set SVE get FPSIMD for VL 7888
5758 10:06:58.563682 # ok 4028 # SKIP Streaming SVE set FPSIMD get SVE for VL 7888
5759 10:06:58.563851 # ok 4029 Set Streaming SVE VL 7904
5760 10:06:58.564036 # ok 4030 # SKIP Streaming SVE set SVE get SVE for VL 7904
5761 10:06:58.564161 # ok 4031 # SKIP Streaming SVE set SVE get FPSIMD for VL 7904
5762 10:06:58.564284 # ok 4032 # SKIP Streaming SVE set FPSIMD get SVE for VL 7904
5763 10:06:58.564404 # ok 4033 Set Streaming SVE VL 7920
5764 10:06:58.564523 # ok 4034 # SKIP Streaming SVE set SVE get SVE for VL 7920
5765 10:06:58.564641 # ok 4035 # SKIP Streaming SVE set SVE get FPSIMD for VL 7920
5766 10:06:58.564783 # ok 4036 # SKIP Streaming SVE set FPSIMD get SVE for VL 7920
5767 10:06:58.564907 # ok 4037 Set Streaming SVE VL 7936
5768 10:06:58.565027 # ok 4038 # SKIP Streaming SVE set SVE get SVE for VL 7936
5769 10:06:58.565149 # ok 4039 # SKIP Streaming SVE set SVE get FPSIMD for VL 7936
5770 10:06:58.565295 # ok 4040 # SKIP Streaming SVE set FPSIMD get SVE for VL 7936
5771 10:06:58.565425 # ok 4041 Set Streaming SVE VL 7952
5772 10:06:58.565566 # ok 4042 # SKIP Streaming SVE set SVE get SVE for VL 7952
5773 10:06:58.566492 # ok 4043 # SKIP Streaming SVE set SVE get FPSIMD for VL 7952
5774 10:06:58.566593 # ok 4044 # SKIP Streaming SVE set FPSIMD get SVE for VL 7952
5775 10:06:58.566679 # ok 4045 Set Streaming SVE VL 7968
5776 10:06:58.566762 # ok 4046 # SKIP Streaming SVE set SVE get SVE for VL 7968
5777 10:06:58.566845 # ok 4047 # SKIP Streaming SVE set SVE get FPSIMD for VL 7968
5778 10:06:58.566946 # ok 4048 # SKIP Streaming SVE set FPSIMD get SVE for VL 7968
5779 10:06:58.567031 # ok 4049 Set Streaming SVE VL 7984
5780 10:06:58.567111 # ok 4050 # SKIP Streaming SVE set SVE get SVE for VL 7984
5781 10:06:58.567206 # ok 4051 # SKIP Streaming SVE set SVE get FPSIMD for VL 7984
5782 10:06:58.567289 # ok 4052 # SKIP Streaming SVE set FPSIMD get SVE for VL 7984
5783 10:06:58.567384 # ok 4053 Set Streaming SVE VL 8000
5784 10:06:58.567713 # ok 4054 # SKIP Streaming SVE set SVE get SVE for VL 8000
5785 10:06:58.567897 # ok 4055 # SKIP Streaming SVE set SVE get FPSIMD for VL 8000
5786 10:06:58.568032 # ok 4056 # SKIP Streaming SVE set FPSIMD get SVE for VL 8000
5787 10:06:58.568179 # ok 4057 Set Streaming SVE VL 8016
5788 10:06:58.568308 # ok 4058 # SKIP Streaming SVE set SVE get SVE for VL 8016
5789 10:06:58.568428 # ok 4059 # SKIP Streaming SVE set SVE get FPSIMD for VL 8016
5790 10:06:58.568572 # ok 4060 # SKIP Streaming SVE set FPSIMD get SVE for VL 8016
5791 10:06:58.568699 # ok 4061 Set Streaming SVE VL 8032
5792 10:06:58.568821 # ok 4062 # SKIP Streaming SVE set SVE get SVE for VL 8032
5793 10:06:58.569042 # ok 4063 # SKIP Streaming SVE set SVE get FPSIMD for VL 8032
5794 10:06:58.569224 # ok 4064 # SKIP Streaming SVE set FPSIMD get SVE for VL 8032
5795 10:06:58.569393 # ok 4065 Set Streaming SVE VL 8048
5796 10:06:58.569551 # ok 4066 # SKIP Streaming SVE set SVE get SVE for VL 8048
5797 10:06:58.569724 # ok 4067 # SKIP Streaming SVE set SVE get FPSIMD for VL 8048
5798 10:06:58.569951 # ok 4068 # SKIP Streaming SVE set FPSIMD get SVE for VL 8048
5799 10:06:58.570110 # ok 4069 Set Streaming SVE VL 8064
5800 10:06:58.570254 # ok 4070 # SKIP Streaming SVE set SVE get SVE for VL 8064
5801 10:06:58.570395 # ok 4071 # SKIP Streaming SVE set SVE get FPSIMD for VL 8064
5802 10:06:58.570536 # ok 4072 # SKIP Streaming SVE set FPSIMD get SVE for VL 8064
5803 10:06:58.570734 # ok 4073 Set Streaming SVE VL 8080
5804 10:06:58.570964 # ok 4074 # SKIP Streaming SVE set SVE get SVE for VL 8080
5805 10:06:58.571184 # ok 4075 # SKIP Streaming SVE set SVE get FPSIMD for VL 8080
5806 10:06:58.571388 # ok 4076 # SKIP Streaming SVE set FPSIMD get SVE for VL 8080
5807 10:06:58.571535 # ok 4077 Set Streaming SVE VL 8096
5808 10:06:58.571704 # ok 4078 # SKIP Streaming SVE set SVE get SVE for VL 8096
5809 10:06:58.571870 # ok 4079 # SKIP Streaming SVE set SVE get FPSIMD for VL 8096
5810 10:06:58.572099 # ok 4080 # SKIP Streaming SVE set FPSIMD get SVE for VL 8096
5811 10:06:58.572310 # ok 4081 Set Streaming SVE VL 8112
5812 10:06:58.572512 # ok 4082 # SKIP Streaming SVE set SVE get SVE for VL 8112
5813 10:06:58.572732 # ok 4083 # SKIP Streaming SVE set SVE get FPSIMD for VL 8112
5814 10:06:58.572920 # ok 4084 # SKIP Streaming SVE set FPSIMD get SVE for VL 8112
5815 10:06:58.573163 # ok 4085 Set Streaming SVE VL 8128
5816 10:06:58.573360 # ok 4086 # SKIP Streaming SVE set SVE get SVE for VL 8128
5817 10:06:58.573558 # ok 4087 # SKIP Streaming SVE set SVE get FPSIMD for VL 8128
5818 10:06:58.574040 # ok 4088 # SKIP Streaming SVE set FPSIMD get SVE for VL 8128
5819 10:06:58.574206 # ok 4089 Set Streaming SVE VL 8144
5820 10:06:58.574607 # ok 4090 # SKIP Streaming SVE set SVE get SVE for VL 8144
5821 10:06:58.574771 # ok 4091 # SKIP Streaming SVE set SVE get FPSIMD for VL 8144
5822 10:06:58.574903 # ok 4092 # SKIP Streaming SVE set FPSIMD get SVE for VL 8144
5823 10:06:58.575032 # ok 4093 Set Streaming SVE VL 8160
5824 10:06:58.575169 # ok 4094 # SKIP Streaming SVE set SVE get SVE for VL 8160
5825 10:06:58.575300 # ok 4095 # SKIP Streaming SVE set SVE get FPSIMD for VL 8160
5826 10:06:58.575462 # ok 4096 # SKIP Streaming SVE set FPSIMD get SVE for VL 8160
5827 10:06:58.575603 # ok 4097 Set Streaming SVE VL 8176
5828 10:06:58.575781 # ok 4098 # SKIP Streaming SVE set SVE get SVE for VL 8176
5829 10:06:58.575947 # ok 4099 # SKIP Streaming SVE set SVE get FPSIMD for VL 8176
5830 10:06:58.576122 # ok 4100 # SKIP Streaming SVE set FPSIMD get SVE for VL 8176
5831 10:06:58.576266 # ok 4101 Set Streaming SVE VL 8192
5832 10:06:58.576409 # ok 4102 # SKIP Streaming SVE set SVE get SVE for VL 8192
5833 10:06:58.576592 # ok 4103 # SKIP Streaming SVE set SVE get FPSIMD for VL 8192
5834 10:06:58.576727 # ok 4104 # SKIP Streaming SVE set FPSIMD get SVE for VL 8192
5835 10:06:58.576869 # # Totals: pass:1095 fail:0 xfail:0 xpass:0 skip:3009 error:0
5836 10:06:58.577011 ok 30 selftests: arm64: sve-ptrace
5837 10:06:58.577152 # selftests: arm64: sve-probe-vls
5838 10:06:58.577292 # TAP version 13
5839 10:06:58.577432 # 1..2
5840 10:06:58.577573 # ok 1 Enumerated 16 vector lengths
5841 10:06:58.577728 # ok 2 All vector lengths valid
5842 10:06:58.577872 # # 16
5843 10:06:58.578012 # # 32
5844 10:06:58.578151 # # 48
5845 10:06:58.578291 # # 64
5846 10:06:58.578430 # # 80
5847 10:06:58.578570 # # 96
5848 10:06:58.578708 # # 112
5849 10:06:58.578846 # # 128
5850 10:06:58.578987 # # 144
5851 10:06:58.579127 # # 160
5852 10:06:58.579277 # # 176
5853 10:06:58.579434 # # 192
5854 10:06:58.579555 # # 208
5855 10:06:58.579670 # # 224
5856 10:06:58.579782 # # 240
5857 10:06:58.579895 # # 256
5858 10:06:58.580010 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
5859 10:06:58.580124 ok 31 selftests: arm64: sve-probe-vls
5860 10:06:58.712127 # selftests: arm64: vec-syscfg
5861 10:06:59.349203 # TAP version 13
5862 10:06:59.349480 # 1..20
5863 10:06:59.349640 # ok 1 SVE default vector length 64
5864 10:06:59.349991 # ok 2 SVE minimum vector length 16
5865 10:06:59.350122 # ok 3 SVE maximum vector length 256
5866 10:06:59.350242 # ok 4 SVE current VL is 64
5867 10:06:59.350359 # ok 5 SVE set VL 64 and have VL 64
5868 10:06:59.350477 # ok 6 SVE prctl() set min/max
5869 10:06:59.350592 # ok 7 SVE vector length used default
5870 10:06:59.350706 # ok 8 SVE vector length was inherited
5871 10:06:59.350819 # ok 9 SVE vector length set on exec
5872 10:06:59.350933 # ok 10 SVE prctl() set all VLs, 0 errors
5873 10:06:59.351050 # ok 11 SME default vector length 32
5874 10:06:59.351192 # ok 12 SME minimum vector length 16
5875 10:06:59.351311 # ok 13 SME maximum vector length 256
5876 10:06:59.351426 # ok 14 SME current VL is 32
5877 10:06:59.351543 # ok 15 SME set VL 32 and have VL 32
5878 10:06:59.351658 # ok 16 SME prctl() set min/max
5879 10:06:59.351773 # ok 17 SME vector length used default
5880 10:06:59.351887 # ok 18 SME vector length was inherited
5881 10:06:59.352000 # ok 19 SME vector length set on exec
5882 10:06:59.352113 # ok 20 SME prctl() set all VLs, 0 errors
5883 10:06:59.352227 # # Totals: pass:20 fail:0 xfail:0 xpass:0 skip:0 error:0
5884 10:06:59.365404 ok 32 selftests: arm64: vec-syscfg
5885 10:06:59.434924 # selftests: arm64: za-fork
5886 10:06:59.598199 # TAP version 13
5887 10:06:59.598479 # 1..1
5888 10:06:59.598605 # # PID: 1018
5889 10:06:59.598723 # ok 1 fork_test
5890 10:06:59.598837 # # Totals: pass:1 fail:0 xfail:0 xpass:0 skip:0 error:0
5891 10:06:59.625362 ok 33 selftests: arm64: za-fork
5892 10:06:59.797555 # selftests: arm64: za-ptrace
5893 10:06:59.968695 # TAP version 13
5894 10:06:59.969025 # 1..1536
5895 10:06:59.969205 # # Parent is 1036, child is 1037
5896 10:06:59.969340 # ok 1 Set VL 16
5897 10:06:59.969481 # ok 2 Disabled ZA for VL 16
5898 10:06:59.969621 # ok 3 Data match for VL 16
5899 10:06:59.969786 # ok 4 Set VL 32
5900 10:06:59.969945 # ok 5 Disabled ZA for VL 32
5901 10:06:59.970279 # ok 6 Data match for VL 32
5902 10:06:59.970389 # ok 7 Set VL 48
5903 10:06:59.970482 # ok 8 # SKIP Disabled ZA for VL 48
5904 10:06:59.970569 # ok 9 # SKIP Get and set data for VL 48
5905 10:06:59.970658 # ok 10 Set VL 64
5906 10:06:59.970746 # ok 11 Disabled ZA for VL 64
5907 10:06:59.970831 # ok 12 Data match for VL 64
5908 10:06:59.970912 # ok 13 Set VL 80
5909 10:06:59.970995 # ok 14 # SKIP Disabled ZA for VL 80
5910 10:06:59.971071 # ok 15 # SKIP Get and set data for VL 80
5911 10:06:59.971144 # ok 16 Set VL 96
5912 10:06:59.971216 # ok 17 # SKIP Disabled ZA for VL 96
5913 10:06:59.971286 # ok 18 # SKIP Get and set data for VL 96
5914 10:06:59.971356 # ok 19 Set VL 112
5915 10:06:59.971426 # ok 20 # SKIP Disabled ZA for VL 112
5916 10:06:59.971497 # ok 21 # SKIP Get and set data for VL 112
5917 10:06:59.971568 # ok 22 Set VL 128
5918 10:06:59.971639 # ok 23 Disabled ZA for VL 128
5919 10:06:59.971709 # ok 24 Data match for VL 128
5920 10:06:59.971778 # ok 25 Set VL 144
5921 10:06:59.971848 # ok 26 # SKIP Disabled ZA for VL 144
5922 10:06:59.971918 # ok 27 # SKIP Get and set data for VL 144
5923 10:06:59.971988 # ok 28 Set VL 160
5924 10:06:59.972059 # ok 29 # SKIP Disabled ZA for VL 160
5925 10:06:59.972132 # ok 30 # SKIP Get and set data for VL 160
5926 10:06:59.972203 # ok 31 Set VL 176
5927 10:06:59.972293 # ok 32 # SKIP Disabled ZA for VL 176
5928 10:06:59.972367 # ok 33 # SKIP Get and set data for VL 176
5929 10:06:59.972439 # ok 34 Set VL 192
5930 10:06:59.972509 # ok 35 # SKIP Disabled ZA for VL 192
5931 10:06:59.972580 # ok 36 # SKIP Get and set data for VL 192
5932 10:06:59.972651 # ok 37 Set VL 208
5933 10:06:59.972720 # ok 38 # SKIP Disabled ZA for VL 208
5934 10:06:59.977113 # ok 39 # SKIP Get and set data for VL 208
5935 10:06:59.977596 # ok 40 Set VL 224
5936 10:06:59.977764 # ok 41 # SKIP Disabled ZA for VL 224
5937 10:06:59.977892 # ok 42 # SKIP Get and set data for VL 224
5938 10:06:59.978010 # ok 43 Set VL 240
5939 10:06:59.978123 # ok 44 # SKIP Disabled ZA for VL 240
5940 10:06:59.978235 # ok 45 # SKIP Get and set data for VL 240
5941 10:06:59.978347 # ok 46 Set VL 256
5942 10:06:59.978487 # ok 47 Disabled ZA for VL 256
5943 10:06:59.978617 # ok 48 Data match for VL 256
5944 10:06:59.978743 # ok 49 Set VL 272
5945 10:06:59.978868 # ok 50 # SKIP Disabled ZA for VL 272
5946 10:06:59.978991 # ok 51 # SKIP Get and set data for VL 272
5947 10:06:59.979115 # ok 52 Set VL 288
5948 10:06:59.979230 # ok 53 # SKIP Disabled ZA for VL 288
5949 10:06:59.979343 # ok 54 # SKIP Get and set data for VL 288
5950 10:06:59.979458 # ok 55 Set VL 304
5951 10:06:59.979574 # ok 56 # SKIP Disabled ZA for VL 304
5952 10:06:59.979739 # ok 57 # SKIP Get and set data for VL 304
5953 10:06:59.979883 # ok 58 Set VL 320
5954 10:06:59.980013 # ok 59 # SKIP Disabled ZA for VL 320
5955 10:06:59.980152 # ok 60 # SKIP Get and set data for VL 320
5956 10:06:59.980311 # ok 61 Set VL 336
5957 10:06:59.980471 # ok 62 # SKIP Disabled ZA for VL 336
5958 10:06:59.980599 # ok 63 # SKIP Get and set data for VL 336
5959 10:06:59.980727 # ok 64 Set VL 352
5960 10:06:59.980848 # ok 65 # SKIP Disabled ZA for VL 352
5961 10:06:59.980968 # ok 66 # SKIP Get and set data for VL 352
5962 10:06:59.981088 # ok 67 Set VL 368
5963 10:06:59.981211 # ok 68 # SKIP Disabled ZA for VL 368
5964 10:06:59.981332 # ok 69 # SKIP Get and set data for VL 368
5965 10:06:59.981454 # ok 70 Set VL 384
5966 10:06:59.981575 # ok 71 # SKIP Disabled ZA for VL 384
5967 10:06:59.981710 # ok 72 # SKIP Get and set data for VL 384
5968 10:06:59.981833 # ok 73 Set VL 400
5969 10:06:59.981953 # ok 74 # SKIP Disabled ZA for VL 400
5970 10:06:59.982107 # ok 75 # SKIP Get and set data for VL 400
5971 10:06:59.982234 # ok 76 Set VL 416
5972 10:06:59.982357 # ok 77 # SKIP Disabled ZA for VL 416
5973 10:06:59.982478 # ok 78 # SKIP Get and set data for VL 416
5974 10:06:59.982602 # ok 79 Set VL 432
5975 10:06:59.982725 # ok 80 # SKIP Disabled ZA for VL 432
5976 10:06:59.982845 # ok 81 # SKIP Get and set data for VL 432
5977 10:06:59.982970 # ok 82 Set VL 448
5978 10:06:59.983091 # ok 83 # SKIP Disabled ZA for VL 448
5979 10:06:59.983211 # ok 84 # SKIP Get and set data for VL 448
5980 10:06:59.983332 # ok 85 Set VL 464
5981 10:06:59.983453 # ok 86 # SKIP Disabled ZA for VL 464
5982 10:06:59.983572 # ok 87 # SKIP Get and set data for VL 464
5983 10:06:59.983695 # ok 88 Set VL 480
5984 10:06:59.983810 # ok 89 # SKIP Disabled ZA for VL 480
5985 10:06:59.983929 # ok 90 # SKIP Get and set data for VL 480
5986 10:06:59.984043 # ok 91 Set VL 496
5987 10:06:59.984155 # ok 92 # SKIP Disabled ZA for VL 496
5988 10:06:59.984272 # ok 93 # SKIP Get and set data for VL 496
5989 10:06:59.984387 # ok 94 Set VL 512
5990 10:06:59.984500 # ok 95 # SKIP Disabled ZA for VL 512
5991 10:06:59.984613 # ok 96 # SKIP Get and set data for VL 512
5992 10:06:59.984970 # ok 97 Set VL 528
5993 10:06:59.985128 # ok 98 # SKIP Disabled ZA for VL 528
5994 10:06:59.985300 # ok 99 # SKIP Get and set data for VL 528
5995 10:06:59.985443 # ok 100 Set VL 544
5996 10:06:59.985583 # ok 101 # SKIP Disabled ZA for VL 544
5997 10:06:59.985738 # ok 102 # SKIP Get and set data for VL 544
5998 10:06:59.985880 # ok 103 Set VL 560
5999 10:06:59.986020 # ok 104 # SKIP Disabled ZA for VL 560
6000 10:06:59.986159 # ok 105 # SKIP Get and set data for VL 560
6001 10:06:59.986307 # ok 106 Set VL 576
6002 10:06:59.986454 # ok 107 # SKIP Disabled ZA for VL 576
6003 10:06:59.986574 # ok 108 # SKIP Get and set data for VL 576
6004 10:06:59.986690 # ok 109 Set VL 592
6005 10:06:59.986804 # ok 110 # SKIP Disabled ZA for VL 592
6006 10:06:59.986918 # ok 111 # SKIP Get and set data for VL 592
6007 10:06:59.987033 # ok 112 Set VL 608
6008 10:06:59.987146 # ok 113 # SKIP Disabled ZA for VL 608
6009 10:06:59.990794 # ok 114 # SKIP Get and set data for VL 608
6010 10:06:59.991149 # ok 115 Set VL 624
6011 10:06:59.991278 # ok 116 # SKIP Disabled ZA for VL 624
6012 10:06:59.991655 # ok 117 # SKIP Get and set data for VL 624
6013 10:06:59.992017 # ok 118 Set VL 640
6014 10:06:59.992185 # ok 119 # SKIP Disabled ZA for VL 640
6015 10:06:59.992308 # ok 120 # SKIP Get and set data for VL 640
6016 10:06:59.992426 # ok 121 Set VL 656
6017 10:06:59.992542 # ok 122 # SKIP Disabled ZA for VL 656
6018 10:06:59.992683 # ok 123 # SKIP Get and set data for VL 656
6019 10:06:59.992804 # ok 124 Set VL 672
6020 10:07:00.004679 # ok 125 # SKIP Disabled ZA for VL 672
6021 10:07:00.005234 # ok 126 # SKIP Get and set data for VL 672
6022 10:07:00.005438 # ok 127 Set VL 688
6023 10:07:00.005637 # ok 128 # SKIP Disabled ZA for VL 688
6024 10:07:00.005825 # ok 129 # SKIP Get and set data for VL 688
6025 10:07:00.005992 # ok 130 Set VL 704
6026 10:07:00.006164 # ok 131 # SKIP Disabled ZA for VL 704
6027 10:07:00.006376 # ok 132 # SKIP Get and set data for VL 704
6028 10:07:00.006530 # ok 133 Set VL 720
6029 10:07:00.006719 # ok 134 # SKIP Disabled ZA for VL 720
6030 10:07:00.006898 # ok 135 # SKIP Get and set data for VL 720
6031 10:07:00.007034 # ok 136 Set VL 736
6032 10:07:00.007148 # ok 137 # SKIP Disabled ZA for VL 736
6033 10:07:00.007260 # ok 138 # SKIP Get and set data for VL 736
6034 10:07:00.007369 # ok 139 Set VL 752
6035 10:07:00.007479 # ok 140 # SKIP Disabled ZA for VL 752
6036 10:07:00.007588 # ok 141 # SKIP Get and set data for VL 752
6037 10:07:00.007698 # ok 142 Set VL 768
6038 10:07:00.007806 # ok 143 # SKIP Disabled ZA for VL 768
6039 10:07:00.007914 # ok 144 # SKIP Get and set data for VL 768
6040 10:07:00.008023 # ok 145 Set VL 784
6041 10:07:00.008161 # ok 146 # SKIP Disabled ZA for VL 784
6042 10:07:00.008279 # ok 147 # SKIP Get and set data for VL 784
6043 10:07:00.008391 # ok 148 Set VL 800
6044 10:07:00.008501 # ok 149 # SKIP Disabled ZA for VL 800
6045 10:07:00.008610 # ok 150 # SKIP Get and set data for VL 800
6046 10:07:00.008722 # ok 151 Set VL 816
6047 10:07:00.008829 # ok 152 # SKIP Disabled ZA for VL 816
6048 10:07:00.016178 # ok 153 # SKIP Get and set data for VL 816
6049 10:07:00.016385 # ok 154 Set VL 832
6050 10:07:00.016679 # ok 155 # SKIP Disabled ZA for VL 832
6051 10:07:00.016782 # ok 156 # SKIP Get and set data for VL 832
6052 10:07:00.016870 # ok 157 Set VL 848
6053 10:07:00.016954 # ok 158 # SKIP Disabled ZA for VL 848
6054 10:07:00.017038 # ok 159 # SKIP Get and set data for VL 848
6055 10:07:00.017139 # ok 160 Set VL 864
6056 10:07:00.017224 # ok 161 # SKIP Disabled ZA for VL 864
6057 10:07:00.017308 # ok 162 # SKIP Get and set data for VL 864
6058 10:07:00.017395 # ok 163 Set VL 880
6059 10:07:00.017479 # ok 164 # SKIP Disabled ZA for VL 880
6060 10:07:00.017561 # ok 165 # SKIP Get and set data for VL 880
6061 10:07:00.017668 # ok 166 Set VL 896
6062 10:07:00.017760 # ok 167 # SKIP Disabled ZA for VL 896
6063 10:07:00.017843 # ok 168 # SKIP Get and set data for VL 896
6064 10:07:00.017927 # ok 169 Set VL 912
6065 10:07:00.018011 # ok 170 # SKIP Disabled ZA for VL 912
6066 10:07:00.018108 # ok 171 # SKIP Get and set data for VL 912
6067 10:07:00.018191 # ok 172 Set VL 928
6068 10:07:00.018276 # ok 173 # SKIP Disabled ZA for VL 928
6069 10:07:00.018356 # ok 174 # SKIP Get and set data for VL 928
6070 10:07:00.018454 # ok 175 Set VL 944
6071 10:07:00.018539 # ok 176 # SKIP Disabled ZA for VL 944
6072 10:07:00.018623 # ok 177 # SKIP Get and set data for VL 944
6073 10:07:00.018722 # ok 178 Set VL 960
6074 10:07:00.018812 # ok 179 # SKIP Disabled ZA for VL 960
6075 10:07:00.018911 # ok 180 # SKIP Get and set data for VL 960
6076 10:07:00.018988 # ok 181 Set VL 976
6077 10:07:00.023660 # ok 182 # SKIP Disabled ZA for VL 976
6078 10:07:00.024166 # ok 183 # SKIP Get and set data for VL 976
6079 10:07:00.024348 # ok 184 Set VL 992
6080 10:07:00.024486 # ok 185 # SKIP Disabled ZA for VL 992
6081 10:07:00.024618 # ok 186 # SKIP Get and set data for VL 992
6082 10:07:00.024771 # ok 187 Set VL 1008
6083 10:07:00.024921 # ok 188 # SKIP Disabled ZA for VL 1008
6084 10:07:00.025158 # ok 189 # SKIP Get and set data for VL 1008
6085 10:07:00.025392 # ok 190 Set VL 1024
6086 10:07:00.025606 # ok 191 # SKIP Disabled ZA for VL 1024
6087 10:07:00.025817 # ok 192 # SKIP Get and set data for VL 1024
6088 10:07:00.026005 # ok 193 Set VL 1040
6089 10:07:00.026161 # ok 194 # SKIP Disabled ZA for VL 1040
6090 10:07:00.026320 # ok 195 # SKIP Get and set data for VL 1040
6091 10:07:00.026469 # ok 196 Set VL 1056
6092 10:07:00.026622 # ok 197 # SKIP Disabled ZA for VL 1056
6093 10:07:00.026807 # ok 198 # SKIP Get and set data for VL 1056
6094 10:07:00.026977 # ok 199 Set VL 1072
6095 10:07:00.027097 # ok 200 # SKIP Disabled ZA for VL 1072
6096 10:07:00.027208 # ok 201 # SKIP Get and set data for VL 1072
6097 10:07:00.027317 # ok 202 Set VL 1088
6098 10:07:00.027425 # ok 203 # SKIP Disabled ZA for VL 1088
6099 10:07:00.027533 # ok 204 # SKIP Get and set data for VL 1088
6100 10:07:00.027641 # ok 205 Set VL 1104
6101 10:07:00.027749 # ok 206 # SKIP Disabled ZA for VL 1104
6102 10:07:00.027860 # ok 207 # SKIP Get and set data for VL 1104
6103 10:07:00.027971 # ok 208 Set VL 1120
6104 10:07:00.028079 # ok 209 # SKIP Disabled ZA for VL 1120
6105 10:07:00.028188 # ok 210 # SKIP Get and set data for VL 1120
6106 10:07:00.028296 # ok 211 Set VL 1136
6107 10:07:00.028404 # ok 212 # SKIP Disabled ZA for VL 1136
6108 10:07:00.028512 # ok 213 # SKIP Get and set data for VL 1136
6109 10:07:00.028620 # ok 214 Set VL 1152
6110 10:07:00.028727 # ok 215 # SKIP Disabled ZA for VL 1152
6111 10:07:00.028835 # ok 216 # SKIP Get and set data for VL 1152
6112 10:07:00.028943 # ok 217 Set VL 1168
6113 10:07:00.029050 # ok 218 # SKIP Disabled ZA for VL 1168
6114 10:07:00.029156 # ok 219 # SKIP Get and set data for VL 1168
6115 10:07:00.029265 # ok 220 Set VL 1184
6116 10:07:00.034081 # ok 221 # SKIP Disabled ZA for VL 1184
6117 10:07:00.034602 # ok 222 # SKIP Get and set data for VL 1184
6118 10:07:00.034783 # ok 223 Set VL 1200
6119 10:07:00.034992 # ok 224 # SKIP Disabled ZA for VL 1200
6120 10:07:00.035151 # ok 225 # SKIP Get and set data for VL 1200
6121 10:07:00.035275 # ok 226 Set VL 1216
6122 10:07:00.035390 # ok 227 # SKIP Disabled ZA for VL 1216
6123 10:07:00.035504 # ok 228 # SKIP Get and set data for VL 1216
6124 10:07:00.035659 # ok 229 Set VL 1232
6125 10:07:00.035796 # ok 230 # SKIP Disabled ZA for VL 1232
6126 10:07:00.036000 # ok 231 # SKIP Get and set data for VL 1232
6127 10:07:00.036172 # ok 232 Set VL 1248
6128 10:07:00.036342 # ok 233 # SKIP Disabled ZA for VL 1248
6129 10:07:00.036540 # ok 234 # SKIP Get and set data for VL 1248
6130 10:07:00.036741 # ok 235 Set VL 1264
6131 10:07:00.036892 # ok 236 # SKIP Disabled ZA for VL 1264
6132 10:07:00.037049 # ok 237 # SKIP Get and set data for VL 1264
6133 10:07:00.037211 # ok 238 Set VL 1280
6134 10:07:00.037359 # ok 239 # SKIP Disabled ZA for VL 1280
6135 10:07:00.037498 # ok 240 # SKIP Get and set data for VL 1280
6136 10:07:00.037619 # ok 241 Set VL 1296
6137 10:07:00.037828 # ok 242 # SKIP Disabled ZA for VL 1296
6138 10:07:00.038013 # ok 243 # SKIP Get and set data for VL 1296
6139 10:07:00.038203 # ok 244 Set VL 1312
6140 10:07:00.038418 # ok 245 # SKIP Disabled ZA for VL 1312
6141 10:07:00.038612 # ok 246 # SKIP Get and set data for VL 1312
6142 10:07:00.038822 # ok 247 Set VL 1328
6143 10:07:00.039027 # ok 248 # SKIP Disabled ZA for VL 1328
6144 10:07:00.039160 # ok 249 # SKIP Get and set data for VL 1328
6145 10:07:00.039274 # ok 250 Set VL 1344
6146 10:07:00.039383 # ok 251 # SKIP Disabled ZA for VL 1344
6147 10:07:00.039493 # ok 252 # SKIP Get and set data for VL 1344
6148 10:07:00.039602 # ok 253 Set VL 1360
6149 10:07:00.039710 # ok 254 # SKIP Disabled ZA for VL 1360
6150 10:07:00.039820 # ok 255 # SKIP Get and set data for VL 1360
6151 10:07:00.039928 # ok 256 Set VL 1376
6152 10:07:00.040036 # ok 257 # SKIP Disabled ZA for VL 1376
6153 10:07:00.040144 # ok 258 # SKIP Get and set data for VL 1376
6154 10:07:00.040252 # ok 259 Set VL 1392
6155 10:07:00.040359 # ok 260 # SKIP Disabled ZA for VL 1392
6156 10:07:00.040467 # ok 261 # SKIP Get and set data for VL 1392
6157 10:07:00.040576 # ok 262 Set VL 1408
6158 10:07:00.040684 # ok 263 # SKIP Disabled ZA for VL 1408
6159 10:07:00.040792 # ok 264 # SKIP Get and set data for VL 1408
6160 10:07:00.040900 # ok 265 Set VL 1424
6161 10:07:00.041035 # ok 266 # SKIP Disabled ZA for VL 1424
6162 10:07:00.041150 # ok 267 # SKIP Get and set data for VL 1424
6163 10:07:00.041260 # ok 268 Set VL 1440
6164 10:07:00.041367 # ok 269 # SKIP Disabled ZA for VL 1440
6165 10:07:00.041476 # ok 270 # SKIP Get and set data for VL 1440
6166 10:07:00.041584 # ok 271 Set VL 1456
6167 10:07:00.041772 # ok 272 # SKIP Disabled ZA for VL 1456
6168 10:07:00.046938 # ok 273 # SKIP Get and set data for VL 1456
6169 10:07:00.047169 # ok 274 Set VL 1472
6170 10:07:00.049801 # ok 275 # SKIP Disabled ZA for VL 1472
6171 10:07:00.050304 # ok 276 # SKIP Get and set data for VL 1472
6172 10:07:00.050504 # ok 277 Set VL 1488
6173 10:07:00.050686 # ok 278 # SKIP Disabled ZA for VL 1488
6174 10:07:00.050841 # ok 279 # SKIP Get and set data for VL 1488
6175 10:07:00.050981 # ok 280 Set VL 1504
6176 10:07:00.051094 # ok 281 # SKIP Disabled ZA for VL 1504
6177 10:07:00.051233 # ok 282 # SKIP Get and set data for VL 1504
6178 10:07:00.051349 # ok 283 Set VL 1520
6179 10:07:00.051459 # ok 284 # SKIP Disabled ZA for VL 1520
6180 10:07:00.051569 # ok 285 # SKIP Get and set data for VL 1520
6181 10:07:00.051677 # ok 286 Set VL 1536
6182 10:07:00.051784 # ok 287 # SKIP Disabled ZA for VL 1536
6183 10:07:00.051891 # ok 288 # SKIP Get and set data for VL 1536
6184 10:07:00.054190 # ok 289 Set VL 1552
6185 10:07:00.054608 # ok 290 # SKIP Disabled ZA for VL 1552
6186 10:07:00.054767 # ok 291 # SKIP Get and set data for VL 1552
6187 10:07:00.054937 # ok 292 Set VL 1568
6188 10:07:00.055079 # ok 293 # SKIP Disabled ZA for VL 1568
6189 10:07:00.055218 # ok 294 # SKIP Get and set data for VL 1568
6190 10:07:00.055356 # ok 295 Set VL 1584
6191 10:07:00.055528 # ok 296 # SKIP Disabled ZA for VL 1584
6192 10:07:00.055663 # ok 297 # SKIP Get and set data for VL 1584
6193 10:07:00.055806 # ok 298 Set VL 1600
6194 10:07:00.055949 # ok 299 # SKIP Disabled ZA for VL 1600
6195 10:07:00.109245 # ok 300 # SKIP Get and set data for VL 1600
6196 10:07:00.109811 # ok 301 Set VL 1616
6197 10:07:00.110023 # ok 302 # SKIP Disabled ZA for VL 1616
6198 10:07:00.110187 # ok 303 # SKIP Get and set data for VL 1616
6199 10:07:00.110392 # ok 304 Set VL 1632
6200 10:07:00.110547 # ok 305 # SKIP Disabled ZA for VL 1632
6201 10:07:00.110689 # ok 306 # SKIP Get and set data for VL 1632
6202 10:07:00.110852 # ok 307 Set VL 1648
6203 10:07:00.110996 # ok 308 # SKIP Disabled ZA for VL 1648
6204 10:07:00.111143 # ok 309 # SKIP Get and set data for VL 1648
6205 10:07:00.111263 # ok 310 Set VL 1664
6206 10:07:00.111377 # ok 311 # SKIP Disabled ZA for VL 1664
6207 10:07:00.111487 # ok 312 # SKIP Get and set data for VL 1664
6208 10:07:00.111597 # ok 313 Set VL 1680
6209 10:07:00.111706 # ok 314 # SKIP Disabled ZA for VL 1680
6210 10:07:00.111815 # ok 315 # SKIP Get and set data for VL 1680
6211 10:07:00.111923 # ok 316 Set VL 1696
6212 10:07:00.112030 # ok 317 # SKIP Disabled ZA for VL 1696
6213 10:07:00.112139 # ok 318 # SKIP Get and set data for VL 1696
6214 10:07:00.112249 # ok 319 Set VL 1712
6215 10:07:00.112357 # ok 320 # SKIP Disabled ZA for VL 1712
6216 10:07:00.112466 # ok 321 # SKIP Get and set data for VL 1712
6217 10:07:00.134487 # ok 322 Set VL 1728
6218 10:07:00.134827 # ok 323 # SKIP Disabled ZA for VL 1728
6219 10:07:00.135226 # ok 324 # SKIP Get and set data for VL 1728
6220 10:07:00.135379 # ok 325 Set VL 1744
6221 10:07:00.135505 # ok 326 # SKIP Disabled ZA for VL 1744
6222 10:07:00.135628 # ok 327 # SKIP Get and set data for VL 1744
6223 10:07:00.135752 # ok 328 Set VL 1760
6224 10:07:00.146230 # ok 329 # SKIP Disabled ZA for VL 1760
6225 10:07:00.146546 # ok 330 # SKIP Get and set data for VL 1760
6226 10:07:00.146748 # ok 331 Set VL 1776
6227 10:07:00.147158 # ok 332 # SKIP Disabled ZA for VL 1776
6228 10:07:00.147312 # ok 333 # SKIP Get and set data for VL 1776
6229 10:07:00.147459 # ok 334 Set VL 1792
6230 10:07:00.147602 # ok 335 # SKIP Disabled ZA for VL 1792
6231 10:07:00.147745 # ok 336 # SKIP Get and set data for VL 1792
6232 10:07:00.147889 # ok 337 Set VL 1808
6233 10:07:00.148030 # ok 338 # SKIP Disabled ZA for VL 1808
6234 10:07:00.148171 # ok 339 # SKIP Get and set data for VL 1808
6235 10:07:00.156523 # ok 340 Set VL 1824
6236 10:07:00.157189 # ok 341 # SKIP Disabled ZA for VL 1824
6237 10:07:00.157382 # ok 342 # SKIP Get and set data for VL 1824
6238 10:07:00.157576 # ok 343 Set VL 1840
6239 10:07:00.157789 # ok 344 # SKIP Disabled ZA for VL 1840
6240 10:07:00.157946 # ok 345 # SKIP Get and set data for VL 1840
6241 10:07:00.158101 # ok 346 Set VL 1856
6242 10:07:00.158217 # ok 347 # SKIP Disabled ZA for VL 1856
6243 10:07:00.158329 # ok 348 # SKIP Get and set data for VL 1856
6244 10:07:00.158466 # ok 349 Set VL 1872
6245 10:07:00.158582 # ok 350 # SKIP Disabled ZA for VL 1872
6246 10:07:00.158693 # ok 351 # SKIP Get and set data for VL 1872
6247 10:07:00.158803 # ok 352 Set VL 1888
6248 10:07:00.158912 # ok 353 # SKIP Disabled ZA for VL 1888
6249 10:07:00.159024 # ok 354 # SKIP Get and set data for VL 1888
6250 10:07:00.159131 # ok 355 Set VL 1904
6251 10:07:00.159238 # ok 356 # SKIP Disabled ZA for VL 1904
6252 10:07:00.159346 # ok 357 # SKIP Get and set data for VL 1904
6253 10:07:00.159454 # ok 358 Set VL 1920
6254 10:07:00.165091 # ok 359 # SKIP Disabled ZA for VL 1920
6255 10:07:00.165677 # ok 360 # SKIP Get and set data for VL 1920
6256 10:07:00.165886 # ok 361 Set VL 1936
6257 10:07:00.166093 # ok 362 # SKIP Disabled ZA for VL 1936
6258 10:07:00.166294 # ok 363 # SKIP Get and set data for VL 1936
6259 10:07:00.166482 # ok 364 Set VL 1952
6260 10:07:00.166648 # ok 365 # SKIP Disabled ZA for VL 1952
6261 10:07:00.166811 # ok 366 # SKIP Get and set data for VL 1952
6262 10:07:00.166949 # ok 367 Set VL 1968
6263 10:07:00.167094 # ok 368 # SKIP Disabled ZA for VL 1968
6264 10:07:00.167215 # ok 369 # SKIP Get and set data for VL 1968
6265 10:07:00.167329 # ok 370 Set VL 1984
6266 10:07:00.167440 # ok 371 # SKIP Disabled ZA for VL 1984
6267 10:07:00.167551 # ok 372 # SKIP Get and set data for VL 1984
6268 10:07:00.167661 # ok 373 Set VL 2000
6269 10:07:00.167772 # ok 374 # SKIP Disabled ZA for VL 2000
6270 10:07:00.167882 # ok 375 # SKIP Get and set data for VL 2000
6271 10:07:00.167994 # ok 376 Set VL 2016
6272 10:07:00.168102 # ok 377 # SKIP Disabled ZA for VL 2016
6273 10:07:00.168212 # ok 378 # SKIP Get and set data for VL 2016
6274 10:07:00.168323 # ok 379 Set VL 2032
6275 10:07:00.168433 # ok 380 # SKIP Disabled ZA for VL 2032
6276 10:07:00.172822 # ok 381 # SKIP Get and set data for VL 2032
6277 10:07:00.173148 # ok 382 Set VL 2048
6278 10:07:00.173579 # ok 383 # SKIP Disabled ZA for VL 2048
6279 10:07:00.173775 # ok 384 # SKIP Get and set data for VL 2048
6280 10:07:00.173935 # ok 385 Set VL 2064
6281 10:07:00.174156 # ok 386 # SKIP Disabled ZA for VL 2064
6282 10:07:00.174374 # ok 387 # SKIP Get and set data for VL 2064
6283 10:07:00.174585 # ok 388 Set VL 2080
6284 10:07:00.174765 # ok 389 # SKIP Disabled ZA for VL 2080
6285 10:07:00.174927 # ok 390 # SKIP Get and set data for VL 2080
6286 10:07:00.175051 # ok 391 Set VL 2096
6287 10:07:00.175190 # ok 392 # SKIP Disabled ZA for VL 2096
6288 10:07:00.175307 # ok 393 # SKIP Get and set data for VL 2096
6289 10:07:00.175418 # ok 394 Set VL 2112
6290 10:07:00.175528 # ok 395 # SKIP Disabled ZA for VL 2112
6291 10:07:00.175638 # ok 396 # SKIP Get and set data for VL 2112
6292 10:07:00.175747 # ok 397 Set VL 2128
6293 10:07:00.175855 # ok 398 # SKIP Disabled ZA for VL 2128
6294 10:07:00.175965 # ok 399 # SKIP Get and set data for VL 2128
6295 10:07:00.176076 # ok 400 Set VL 2144
6296 10:07:00.176184 # ok 401 # SKIP Disabled ZA for VL 2144
6297 10:07:00.176292 # ok 402 # SKIP Get and set data for VL 2144
6298 10:07:00.176401 # ok 403 Set VL 2160
6299 10:07:00.176509 # ok 404 # SKIP Disabled ZA for VL 2160
6300 10:07:00.176617 # ok 405 # SKIP Get and set data for VL 2160
6301 10:07:00.176726 # ok 406 Set VL 2176
6302 10:07:00.181132 # ok 407 # SKIP Disabled ZA for VL 2176
6303 10:07:00.181428 # ok 408 # SKIP Get and set data for VL 2176
6304 10:07:00.181864 # ok 409 Set VL 2192
6305 10:07:00.182057 # ok 410 # SKIP Disabled ZA for VL 2192
6306 10:07:00.182227 # ok 411 # SKIP Get and set data for VL 2192
6307 10:07:00.182375 # ok 412 Set VL 2208
6308 10:07:00.182558 # ok 413 # SKIP Disabled ZA for VL 2208
6309 10:07:00.182746 # ok 414 # SKIP Get and set data for VL 2208
6310 10:07:00.182919 # ok 415 Set VL 2224
6311 10:07:00.183046 # ok 416 # SKIP Disabled ZA for VL 2224
6312 10:07:00.183161 # ok 417 # SKIP Get and set data for VL 2224
6313 10:07:00.183302 # ok 418 Set VL 2240
6314 10:07:00.183421 # ok 419 # SKIP Disabled ZA for VL 2240
6315 10:07:00.183536 # ok 420 # SKIP Get and set data for VL 2240
6316 10:07:00.183662 # ok 421 Set VL 2256
6317 10:07:00.183777 # ok 422 # SKIP Disabled ZA for VL 2256
6318 10:07:00.183889 # ok 423 # SKIP Get and set data for VL 2256
6319 10:07:00.184001 # ok 424 Set VL 2272
6320 10:07:00.184113 # ok 425 # SKIP Disabled ZA for VL 2272
6321 10:07:00.184223 # ok 426 # SKIP Get and set data for VL 2272
6322 10:07:00.184335 # ok 427 Set VL 2288
6323 10:07:00.184447 # ok 428 # SKIP Disabled ZA for VL 2288
6324 10:07:00.184558 # ok 429 # SKIP Get and set data for VL 2288
6325 10:07:00.184696 # ok 430 Set VL 2304
6326 10:07:00.184815 # ok 431 # SKIP Disabled ZA for VL 2304
6327 10:07:00.184928 # ok 432 # SKIP Get and set data for VL 2304
6328 10:07:00.185040 # ok 433 Set VL 2320
6329 10:07:00.185153 # ok 434 # SKIP Disabled ZA for VL 2320
6330 10:07:00.185265 # ok 435 # SKIP Get and set data for VL 2320
6331 10:07:00.185376 # ok 436 Set VL 2336
6332 10:07:00.185510 # ok 437 # SKIP Disabled ZA for VL 2336
6333 10:07:00.185626 # ok 438 # SKIP Get and set data for VL 2336
6334 10:07:00.185752 # ok 439 Set VL 2352
6335 10:07:00.185866 # ok 440 # SKIP Disabled ZA for VL 2352
6336 10:07:00.185981 # ok 441 # SKIP Get and set data for VL 2352
6337 10:07:00.186098 # ok 442 Set VL 2368
6338 10:07:00.186237 # ok 443 # SKIP Disabled ZA for VL 2368
6339 10:07:00.186358 # ok 444 # SKIP Get and set data for VL 2368
6340 10:07:00.186473 # ok 445 Set VL 2384
6341 10:07:00.186585 # ok 446 # SKIP Disabled ZA for VL 2384
6342 10:07:00.186699 # ok 447 # SKIP Get and set data for VL 2384
6343 10:07:00.186817 # ok 448 Set VL 2400
6344 10:07:00.186942 # ok 449 # SKIP Disabled ZA for VL 2400
6345 10:07:00.187097 # ok 450 # SKIP Get and set data for VL 2400
6346 10:07:00.187220 # ok 451 Set VL 2416
6347 10:07:00.187335 # ok 452 # SKIP Disabled ZA for VL 2416
6348 10:07:00.187448 # ok 453 # SKIP Get and set data for VL 2416
6349 10:07:00.187563 # ok 454 Set VL 2432
6350 10:07:00.187677 # ok 455 # SKIP Disabled ZA for VL 2432
6351 10:07:00.193069 # ok 456 # SKIP Get and set data for VL 2432
6352 10:07:00.193552 # ok 457 Set VL 2448
6353 10:07:00.193771 # ok 458 # SKIP Disabled ZA for VL 2448
6354 10:07:00.193931 # ok 459 # SKIP Get and set data for VL 2448
6355 10:07:00.194082 # ok 460 Set VL 2464
6356 10:07:00.194235 # ok 461 # SKIP Disabled ZA for VL 2464
6357 10:07:00.194372 # ok 462 # SKIP Get and set data for VL 2464
6358 10:07:00.194586 # ok 463 Set VL 2480
6359 10:07:00.194780 # ok 464 # SKIP Disabled ZA for VL 2480
6360 10:07:00.194990 # ok 465 # SKIP Get and set data for VL 2480
6361 10:07:00.195127 # ok 466 Set VL 2496
6362 10:07:00.195244 # ok 467 # SKIP Disabled ZA for VL 2496
6363 10:07:00.195357 # ok 468 # SKIP Get and set data for VL 2496
6364 10:07:00.195501 # ok 469 Set VL 2512
6365 10:07:00.195636 # ok 470 # SKIP Disabled ZA for VL 2512
6366 10:07:00.195751 # ok 471 # SKIP Get and set data for VL 2512
6367 10:07:00.195862 # ok 472 Set VL 2528
6368 10:07:00.195974 # ok 473 # SKIP Disabled ZA for VL 2528
6369 10:07:00.196086 # ok 474 # SKIP Get and set data for VL 2528
6370 10:07:00.196195 # ok 475 Set VL 2544
6371 10:07:00.196305 # ok 476 # SKIP Disabled ZA for VL 2544
6372 10:07:00.196417 # ok 477 # SKIP Get and set data for VL 2544
6373 10:07:00.196529 # ok 478 Set VL 2560
6374 10:07:00.196640 # ok 479 # SKIP Disabled ZA for VL 2560
6375 10:07:00.196752 # ok 480 # SKIP Get and set data for VL 2560
6376 10:07:00.200551 # ok 481 Set VL 2576
6377 10:07:00.200838 # ok 482 # SKIP Disabled ZA for VL 2576
6378 10:07:00.201236 # ok 483 # SKIP Get and set data for VL 2576
6379 10:07:00.201338 # ok 484 Set VL 2592
6380 10:07:00.201423 # ok 485 # SKIP Disabled ZA for VL 2592
6381 10:07:00.201504 # ok 486 # SKIP Get and set data for VL 2592
6382 10:07:00.201585 # ok 487 Set VL 2608
6383 10:07:00.201673 # ok 488 # SKIP Disabled ZA for VL 2608
6384 10:07:00.201755 # ok 489 # SKIP Get and set data for VL 2608
6385 10:07:00.201836 # ok 490 Set VL 2624
6386 10:07:00.201933 # ok 491 # SKIP Disabled ZA for VL 2624
6387 10:07:00.202016 # ok 492 # SKIP Get and set data for VL 2624
6388 10:07:00.202098 # ok 493 Set VL 2640
6389 10:07:00.202180 # ok 494 # SKIP Disabled ZA for VL 2640
6390 10:07:00.202262 # ok 495 # SKIP Get and set data for VL 2640
6391 10:07:00.202342 # ok 496 Set VL 2656
6392 10:07:00.202440 # ok 497 # SKIP Disabled ZA for VL 2656
6393 10:07:00.202523 # ok 498 # SKIP Get and set data for VL 2656
6394 10:07:00.202604 # ok 499 Set VL 2672
6395 10:07:00.202682 # ok 500 # SKIP Disabled ZA for VL 2672
6396 10:07:00.202779 # ok 501 # SKIP Get and set data for VL 2672
6397 10:07:00.202877 # ok 502 Set VL 2688
6398 10:07:00.202963 # ok 503 # SKIP Disabled ZA for VL 2688
6399 10:07:00.203037 # ok 504 # SKIP Get and set data for VL 2688
6400 10:07:00.203123 # ok 505 Set VL 2704
6401 10:07:00.209981 # ok 506 # SKIP Disabled ZA for VL 2704
6402 10:07:00.210485 # ok 507 # SKIP Get and set data for VL 2704
6403 10:07:00.210589 # ok 508 Set VL 2720
6404 10:07:00.210673 # ok 509 # SKIP Disabled ZA for VL 2720
6405 10:07:00.210760 # ok 510 # SKIP Get and set data for VL 2720
6406 10:07:00.210841 # ok 511 Set VL 2736
6407 10:07:00.210934 # ok 512 # SKIP Disabled ZA for VL 2736
6408 10:07:00.211016 # ok 513 # SKIP Get and set data for VL 2736
6409 10:07:00.211109 # ok 514 Set VL 2752
6410 10:07:00.211186 # ok 515 # SKIP Disabled ZA for VL 2752
6411 10:07:00.211257 # ok 516 # SKIP Get and set data for VL 2752
6412 10:07:00.211327 # ok 517 Set VL 2768
6413 10:07:00.211397 # ok 518 # SKIP Disabled ZA for VL 2768
6414 10:07:00.212863 # ok 519 # SKIP Get and set data for VL 2768
6415 10:07:00.212968 # ok 520 Set VL 2784
6416 10:07:00.213069 # ok 521 # SKIP Disabled ZA for VL 2784
6417 10:07:00.213157 # ok 522 # SKIP Get and set data for VL 2784
6418 10:07:00.213251 # ok 523 Set VL 2800
6419 10:07:00.213348 # ok 524 # SKIP Disabled ZA for VL 2800
6420 10:07:00.213430 # ok 525 # SKIP Get and set data for VL 2800
6421 10:07:00.213524 # ok 526 Set VL 2816
6422 10:07:00.213618 # ok 527 # SKIP Disabled ZA for VL 2816
6423 10:07:00.213725 # ok 528 # SKIP Get and set data for VL 2816
6424 10:07:00.213823 # ok 529 Set VL 2832
6425 10:07:00.213918 # ok 530 # SKIP Disabled ZA for VL 2832
6426 10:07:00.214016 # ok 531 # SKIP Get and set data for VL 2832
6427 10:07:00.214347 # ok 532 Set VL 2848
6428 10:07:00.214533 # ok 533 # SKIP Disabled ZA for VL 2848
6429 10:07:00.214765 # ok 534 # SKIP Get and set data for VL 2848
6430 10:07:00.214957 # ok 535 Set VL 2864
6431 10:07:00.215128 # ok 536 # SKIP Disabled ZA for VL 2864
6432 10:07:00.215292 # ok 537 # SKIP Get and set data for VL 2864
6433 10:07:00.215477 # ok 538 Set VL 2880
6434 10:07:00.215722 # ok 539 # SKIP Disabled ZA for VL 2880
6435 10:07:00.215909 # ok 540 # SKIP Get and set data for VL 2880
6436 10:07:00.216076 # ok 541 Set VL 2896
6437 10:07:00.216221 # ok 542 # SKIP Disabled ZA for VL 2896
6438 10:07:00.216347 # ok 543 # SKIP Get and set data for VL 2896
6439 10:07:00.216466 # ok 544 Set VL 2912
6440 10:07:00.216588 # ok 545 # SKIP Disabled ZA for VL 2912
6441 10:07:00.216780 # ok 546 # SKIP Get and set data for VL 2912
6442 10:07:00.216963 # ok 547 Set VL 2928
6443 10:07:00.217143 # ok 548 # SKIP Disabled ZA for VL 2928
6444 10:07:00.217347 # ok 549 # SKIP Get and set data for VL 2928
6445 10:07:00.217505 # ok 550 Set VL 2944
6446 10:07:00.217701 # ok 551 # SKIP Disabled ZA for VL 2944
6447 10:07:00.217883 # ok 552 # SKIP Get and set data for VL 2944
6448 10:07:00.218009 # ok 553 Set VL 2960
6449 10:07:00.218123 # ok 554 # SKIP Disabled ZA for VL 2960
6450 10:07:00.218234 # ok 555 # SKIP Get and set data for VL 2960
6451 10:07:00.218344 # ok 556 Set VL 2976
6452 10:07:00.218453 # ok 557 # SKIP Disabled ZA for VL 2976
6453 10:07:00.218562 # ok 558 # SKIP Get and set data for VL 2976
6454 10:07:00.218672 # ok 559 Set VL 2992
6455 10:07:00.218781 # ok 560 # SKIP Disabled ZA for VL 2992
6456 10:07:00.218891 # ok 561 # SKIP Get and set data for VL 2992
6457 10:07:00.219000 # ok 562 Set VL 3008
6458 10:07:00.219108 # ok 563 # SKIP Disabled ZA for VL 3008
6459 10:07:00.219247 # ok 564 # SKIP Get and set data for VL 3008
6460 10:07:00.219364 # ok 565 Set VL 3024
6461 10:07:00.219476 # ok 566 # SKIP Disabled ZA for VL 3024
6462 10:07:00.219587 # ok 567 # SKIP Get and set data for VL 3024
6463 10:07:00.219697 # ok 568 Set VL 3040
6464 10:07:00.219806 # ok 569 # SKIP Disabled ZA for VL 3040
6465 10:07:00.219918 # ok 570 # SKIP Get and set data for VL 3040
6466 10:07:00.228683 # ok 571 Set VL 3056
6467 10:07:00.229013 # ok 572 # SKIP Disabled ZA for VL 3056
6468 10:07:00.229447 # ok 573 # SKIP Get and set data for VL 3056
6469 10:07:00.229644 # ok 574 Set VL 3072
6470 10:07:00.229839 # ok 575 # SKIP Disabled ZA for VL 3072
6471 10:07:00.230056 # ok 576 # SKIP Get and set data for VL 3072
6472 10:07:00.230225 # ok 577 Set VL 3088
6473 10:07:00.230346 # ok 578 # SKIP Disabled ZA for VL 3088
6474 10:07:00.230458 # ok 579 # SKIP Get and set data for VL 3088
6475 10:07:00.230571 # ok 580 Set VL 3104
6476 10:07:00.230682 # ok 581 # SKIP Disabled ZA for VL 3104
6477 10:07:00.230843 # ok 582 # SKIP Get and set data for VL 3104
6478 10:07:00.230989 # ok 583 Set VL 3120
6479 10:07:00.231107 # ok 584 # SKIP Disabled ZA for VL 3120
6480 10:07:00.231221 # ok 585 # SKIP Get and set data for VL 3120
6481 10:07:00.231334 # ok 586 Set VL 3136
6482 10:07:00.231445 # ok 587 # SKIP Disabled ZA for VL 3136
6483 10:07:00.231570 # ok 588 # SKIP Get and set data for VL 3136
6484 10:07:00.231683 # ok 589 Set VL 3152
6485 10:07:00.238174 # ok 590 # SKIP Disabled ZA for VL 3152
6486 10:07:00.238735 # ok 591 # SKIP Get and set data for VL 3152
6487 10:07:00.238929 # ok 592 Set VL 3168
6488 10:07:00.239065 # ok 593 # SKIP Disabled ZA for VL 3168
6489 10:07:00.239182 # ok 594 # SKIP Get and set data for VL 3168
6490 10:07:00.239303 # ok 595 Set VL 3184
6491 10:07:00.239417 # ok 596 # SKIP Disabled ZA for VL 3184
6492 10:07:00.239557 # ok 597 # SKIP Get and set data for VL 3184
6493 10:07:00.239718 # ok 598 Set VL 3200
6494 10:07:00.239897 # ok 599 # SKIP Disabled ZA for VL 3200
6495 10:07:00.240120 # ok 600 # SKIP Get and set data for VL 3200
6496 10:07:00.240298 # ok 601 Set VL 3216
6497 10:07:00.240519 # ok 602 # SKIP Disabled ZA for VL 3216
6498 10:07:00.240681 # ok 603 # SKIP Get and set data for VL 3216
6499 10:07:00.240838 # ok 604 Set VL 3232
6500 10:07:00.240991 # ok 605 # SKIP Disabled ZA for VL 3232
6501 10:07:00.241148 # ok 606 # SKIP Get and set data for VL 3232
6502 10:07:00.241344 # ok 607 Set VL 3248
6503 10:07:00.241512 # ok 608 # SKIP Disabled ZA for VL 3248
6504 10:07:00.241683 # ok 609 # SKIP Get and set data for VL 3248
6505 10:07:00.241831 # ok 610 Set VL 3264
6506 10:07:00.241987 # ok 611 # SKIP Disabled ZA for VL 3264
6507 10:07:00.242137 # ok 612 # SKIP Get and set data for VL 3264
6508 10:07:00.242289 # ok 613 Set VL 3280
6509 10:07:00.242439 # ok 614 # SKIP Disabled ZA for VL 3280
6510 10:07:00.242596 # ok 615 # SKIP Get and set data for VL 3280
6511 10:07:00.242755 # ok 616 Set VL 3296
6512 10:07:00.242973 # ok 617 # SKIP Disabled ZA for VL 3296
6513 10:07:00.243123 # ok 618 # SKIP Get and set data for VL 3296
6514 10:07:00.243241 # ok 619 Set VL 3312
6515 10:07:00.243351 # ok 620 # SKIP Disabled ZA for VL 3312
6516 10:07:00.243462 # ok 621 # SKIP Get and set data for VL 3312
6517 10:07:00.243573 # ok 622 Set VL 3328
6518 10:07:00.243683 # ok 623 # SKIP Disabled ZA for VL 3328
6519 10:07:00.243793 # ok 624 # SKIP Get and set data for VL 3328
6520 10:07:00.243903 # ok 625 Set VL 3344
6521 10:07:00.244013 # ok 626 # SKIP Disabled ZA for VL 3344
6522 10:07:00.244123 # ok 627 # SKIP Get and set data for VL 3344
6523 10:07:00.244233 # ok 628 Set VL 3360
6524 10:07:00.244342 # ok 629 # SKIP Disabled ZA for VL 3360
6525 10:07:00.244452 # ok 630 # SKIP Get and set data for VL 3360
6526 10:07:00.244562 # ok 631 Set VL 3376
6527 10:07:00.244672 # ok 632 # SKIP Disabled ZA for VL 3376
6528 10:07:00.252364 # ok 633 # SKIP Get and set data for VL 3376
6529 10:07:00.252688 # ok 634 Set VL 3392
6530 10:07:00.253132 # ok 635 # SKIP Disabled ZA for VL 3392
6531 10:07:00.253355 # ok 636 # SKIP Get and set data for VL 3392
6532 10:07:00.253545 # ok 637 Set VL 3408
6533 10:07:00.253782 # ok 638 # SKIP Disabled ZA for VL 3408
6534 10:07:00.254001 # ok 639 # SKIP Get and set data for VL 3408
6535 10:07:00.254208 # ok 640 Set VL 3424
6536 10:07:00.254425 # ok 641 # SKIP Disabled ZA for VL 3424
6537 10:07:00.254646 # ok 642 # SKIP Get and set data for VL 3424
6538 10:07:00.254840 # ok 643 Set VL 3440
6539 10:07:00.255047 # ok 644 # SKIP Disabled ZA for VL 3440
6540 10:07:00.255179 # ok 645 # SKIP Get and set data for VL 3440
6541 10:07:00.255295 # ok 646 Set VL 3456
6542 10:07:00.255406 # ok 647 # SKIP Disabled ZA for VL 3456
6543 10:07:00.255517 # ok 648 # SKIP Get and set data for VL 3456
6544 10:07:00.255629 # ok 649 Set VL 3472
6545 10:07:00.255740 # ok 650 # SKIP Disabled ZA for VL 3472
6546 10:07:00.255852 # ok 651 # SKIP Get and set data for VL 3472
6547 10:07:00.255964 # ok 652 Set VL 3488
6548 10:07:00.256075 # ok 653 # SKIP Disabled ZA for VL 3488
6549 10:07:00.256185 # ok 654 # SKIP Get and set data for VL 3488
6550 10:07:00.256296 # ok 655 Set VL 3504
6551 10:07:00.256406 # ok 656 # SKIP Disabled ZA for VL 3504
6552 10:07:00.256517 # ok 657 # SKIP Get and set data for VL 3504
6553 10:07:00.256679 # ok 658 Set VL 3520
6554 10:07:00.256901 # ok 659 # SKIP Disabled ZA for VL 3520
6555 10:07:00.257070 # ok 660 # SKIP Get and set data for VL 3520
6556 10:07:00.257210 # ok 661 Set VL 3536
6557 10:07:00.257350 # ok 662 # SKIP Disabled ZA for VL 3536
6558 10:07:00.257495 # ok 663 # SKIP Get and set data for VL 3536
6559 10:07:00.258426 # ok 664 Set VL 3552
6560 10:07:00.258617 # ok 665 # SKIP Disabled ZA for VL 3552
6561 10:07:00.258786 # ok 666 # SKIP Get and set data for VL 3552
6562 10:07:00.258930 # ok 667 Set VL 3568
6563 10:07:00.259070 # ok 668 # SKIP Disabled ZA for VL 3568
6564 10:07:00.259214 # ok 669 # SKIP Get and set data for VL 3568
6565 10:07:00.259355 # ok 670 Set VL 3584
6566 10:07:00.259495 # ok 671 # SKIP Disabled ZA for VL 3584
6567 10:07:00.259635 # ok 672 # SKIP Get and set data for VL 3584
6568 10:07:00.259774 # ok 673 Set VL 3600
6569 10:07:00.259914 # ok 674 # SKIP Disabled ZA for VL 3600
6570 10:07:00.260053 # ok 675 # SKIP Get and set data for VL 3600
6571 10:07:00.260192 # ok 676 Set VL 3616
6572 10:07:00.260374 # ok 677 # SKIP Disabled ZA for VL 3616
6573 10:07:00.260506 # ok 678 # SKIP Get and set data for VL 3616
6574 10:07:00.260646 # ok 679 Set VL 3632
6575 10:07:00.260785 # ok 680 # SKIP Disabled ZA for VL 3632
6576 10:07:00.260924 # ok 681 # SKIP Get and set data for VL 3632
6577 10:07:00.261063 # ok 682 Set VL 3648
6578 10:07:00.261203 # ok 683 # SKIP Disabled ZA for VL 3648
6579 10:07:00.261345 # ok 684 # SKIP Get and set data for VL 3648
6580 10:07:00.261486 # ok 685 Set VL 3664
6581 10:07:00.261626 # ok 686 # SKIP Disabled ZA for VL 3664
6582 10:07:00.261779 # ok 687 # SKIP Get and set data for VL 3664
6583 10:07:00.262145 # ok 688 Set VL 3680
6584 10:07:00.262283 # ok 689 # SKIP Disabled ZA for VL 3680
6585 10:07:00.262425 # ok 690 # SKIP Get and set data for VL 3680
6586 10:07:00.262566 # ok 691 Set VL 3696
6587 10:07:00.266083 # ok 692 # SKIP Disabled ZA for VL 3696
6588 10:07:00.266593 # ok 693 # SKIP Get and set data for VL 3696
6589 10:07:00.266764 # ok 694 Set VL 3712
6590 10:07:00.266922 # ok 695 # SKIP Disabled ZA for VL 3712
6591 10:07:00.267078 # ok 696 # SKIP Get and set data for VL 3712
6592 10:07:00.267234 # ok 697 Set VL 3728
6593 10:07:00.267388 # ok 698 # SKIP Disabled ZA for VL 3728
6594 10:07:00.267540 # ok 699 # SKIP Get and set data for VL 3728
6595 10:07:00.267722 # ok 700 Set VL 3744
6596 10:07:00.267880 # ok 701 # SKIP Disabled ZA for VL 3744
6597 10:07:00.268033 # ok 702 # SKIP Get and set data for VL 3744
6598 10:07:00.268186 # ok 703 Set VL 3760
6599 10:07:00.268602 # ok 704 # SKIP Disabled ZA for VL 3760
6600 10:07:00.268986 # ok 705 # SKIP Get and set data for VL 3760
6601 10:07:00.269151 # ok 706 Set VL 3776
6602 10:07:00.269305 # ok 707 # SKIP Disabled ZA for VL 3776
6603 10:07:00.269460 # ok 708 # SKIP Get and set data for VL 3776
6604 10:07:00.269642 # ok 709 Set VL 3792
6605 10:07:00.269812 # ok 710 # SKIP Disabled ZA for VL 3792
6606 10:07:00.269967 # ok 711 # SKIP Get and set data for VL 3792
6607 10:07:00.270121 # ok 712 Set VL 3808
6608 10:07:00.270273 # ok 713 # SKIP Disabled ZA for VL 3808
6609 10:07:00.270427 # ok 714 # SKIP Get and set data for VL 3808
6610 10:07:00.270612 # ok 715 Set VL 3824
6611 10:07:00.270770 # ok 716 # SKIP Disabled ZA for VL 3824
6612 10:07:00.270925 # ok 717 # SKIP Get and set data for VL 3824
6613 10:07:00.271079 # ok 718 Set VL 3840
6614 10:07:00.271233 # ok 719 # SKIP Disabled ZA for VL 3840
6615 10:07:00.271387 # ok 720 # SKIP Get and set data for VL 3840
6616 10:07:00.271541 # ok 721 Set VL 3856
6617 10:07:00.271694 # ok 722 # SKIP Disabled ZA for VL 3856
6618 10:07:00.271848 # ok 723 # SKIP Get and set data for VL 3856
6619 10:07:00.272002 # ok 724 Set VL 3872
6620 10:07:00.272155 # ok 725 # SKIP Disabled ZA for VL 3872
6621 10:07:00.272338 # ok 726 # SKIP Get and set data for VL 3872
6622 10:07:00.272497 # ok 727 Set VL 3888
6623 10:07:00.272650 # ok 728 # SKIP Disabled ZA for VL 3888
6624 10:07:00.276582 # ok 729 # SKIP Get and set data for VL 3888
6625 10:07:00.277092 # ok 730 Set VL 3904
6626 10:07:00.277290 # ok 731 # SKIP Disabled ZA for VL 3904
6627 10:07:00.277445 # ok 732 # SKIP Get and set data for VL 3904
6628 10:07:00.277594 # ok 733 Set VL 3920
6629 10:07:00.277753 # ok 734 # SKIP Disabled ZA for VL 3920
6630 10:07:00.277924 # ok 735 # SKIP Get and set data for VL 3920
6631 10:07:00.278068 # ok 736 Set VL 3936
6632 10:07:00.278189 # ok 737 # SKIP Disabled ZA for VL 3936
6633 10:07:00.278309 # ok 738 # SKIP Get and set data for VL 3936
6634 10:07:00.278425 # ok 739 Set VL 3952
6635 10:07:00.278541 # ok 740 # SKIP Disabled ZA for VL 3952
6636 10:07:00.278660 # ok 741 # SKIP Get and set data for VL 3952
6637 10:07:00.278788 # ok 742 Set VL 3968
6638 10:07:00.278906 # ok 743 # SKIP Disabled ZA for VL 3968
6639 10:07:00.279023 # ok 744 # SKIP Get and set data for VL 3968
6640 10:07:00.279134 # ok 745 Set VL 3984
6641 10:07:00.279248 # ok 746 # SKIP Disabled ZA for VL 3984
6642 10:07:00.279389 # ok 747 # SKIP Get and set data for VL 3984
6643 10:07:00.279506 # ok 748 Set VL 4000
6644 10:07:00.279617 # ok 749 # SKIP Disabled ZA for VL 4000
6645 10:07:00.279729 # ok 750 # SKIP Get and set data for VL 4000
6646 10:07:00.279840 # ok 751 Set VL 4016
6647 10:07:00.279950 # ok 752 # SKIP Disabled ZA for VL 4016
6648 10:07:00.280062 # ok 753 # SKIP Get and set data for VL 4016
6649 10:07:00.280172 # ok 754 Set VL 4032
6650 10:07:00.280283 # ok 755 # SKIP Disabled ZA for VL 4032
6651 10:07:00.280393 # ok 756 # SKIP Get and set data for VL 4032
6652 10:07:00.280505 # ok 757 Set VL 4048
6653 10:07:00.280615 # ok 758 # SKIP Disabled ZA for VL 4048
6654 10:07:00.280724 # ok 759 # SKIP Get and set data for VL 4048
6655 10:07:00.286995 # ok 760 Set VL 4064
6656 10:07:00.292889 # ok 761 # SKIP Disabled ZA for VL 4064
6657 10:07:00.293110 # ok 762 # SKIP Get and set data for VL 4064
6658 10:07:00.293198 # ok 763 Set VL 4080
6659 10:07:00.293299 # ok 764 # SKIP Disabled ZA for VL 4080
6660 10:07:00.293384 # ok 765 # SKIP Get and set data for VL 4080
6661 10:07:00.293467 # ok 766 Set VL 4096
6662 10:07:00.293548 # ok 767 # SKIP Disabled ZA for VL 4096
6663 10:07:00.293656 # ok 768 # SKIP Get and set data for VL 4096
6664 10:07:00.293741 # ok 769 Set VL 4112
6665 10:07:00.293821 # ok 770 # SKIP Disabled ZA for VL 4112
6666 10:07:00.293919 # ok 771 # SKIP Get and set data for VL 4112
6667 10:07:00.294004 # ok 772 Set VL 4128
6668 10:07:00.294085 # ok 773 # SKIP Disabled ZA for VL 4128
6669 10:07:00.294184 # ok 774 # SKIP Get and set data for VL 4128
6670 10:07:00.294275 # ok 775 Set VL 4144
6671 10:07:00.294356 # ok 776 # SKIP Disabled ZA for VL 4144
6672 10:07:00.294452 # ok 777 # SKIP Get and set data for VL 4144
6673 10:07:00.294536 # ok 778 Set VL 4160
6674 10:07:00.294619 # ok 779 # SKIP Disabled ZA for VL 4160
6675 10:07:00.294716 # ok 780 # SKIP Get and set data for VL 4160
6676 10:07:00.294799 # ok 781 Set VL 4176
6677 10:07:00.294887 # ok 782 # SKIP Disabled ZA for VL 4176
6678 10:07:00.304658 # ok 783 # SKIP Get and set data for VL 4176
6679 10:07:00.304896 # ok 784 Set VL 4192
6680 10:07:00.305188 # ok 785 # SKIP Disabled ZA for VL 4192
6681 10:07:00.305279 # ok 786 # SKIP Get and set data for VL 4192
6682 10:07:00.305366 # ok 787 Set VL 4208
6683 10:07:00.305449 # ok 788 # SKIP Disabled ZA for VL 4208
6684 10:07:00.305531 # ok 789 # SKIP Get and set data for VL 4208
6685 10:07:00.305612 # ok 790 Set VL 4224
6686 10:07:00.305722 # ok 791 # SKIP Disabled ZA for VL 4224
6687 10:07:00.305809 # ok 792 # SKIP Get and set data for VL 4224
6688 10:07:00.305892 # ok 793 Set VL 4240
6689 10:07:00.305973 # ok 794 # SKIP Disabled ZA for VL 4240
6690 10:07:00.306072 # ok 795 # SKIP Get and set data for VL 4240
6691 10:07:00.306157 # ok 796 Set VL 4256
6692 10:07:00.306237 # ok 797 # SKIP Disabled ZA for VL 4256
6693 10:07:00.306316 # ok 798 # SKIP Get and set data for VL 4256
6694 10:07:00.306413 # ok 799 Set VL 4272
6695 10:07:00.306495 # ok 800 # SKIP Disabled ZA for VL 4272
6696 10:07:00.306575 # ok 801 # SKIP Get and set data for VL 4272
6697 10:07:00.306671 # ok 802 Set VL 4288
6698 10:07:00.306754 # ok 803 # SKIP Disabled ZA for VL 4288
6699 10:07:00.306846 # ok 804 # SKIP Get and set data for VL 4288
6700 10:07:00.306921 # ok 805 Set VL 4304
6701 10:07:00.318559 # ok 806 # SKIP Disabled ZA for VL 4304
6702 10:07:00.319020 # ok 807 # SKIP Get and set data for VL 4304
6703 10:07:00.319104 # ok 808 Set VL 4320
6704 10:07:00.319174 # ok 809 # SKIP Disabled ZA for VL 4320
6705 10:07:00.319246 # ok 810 # SKIP Get and set data for VL 4320
6706 10:07:00.319316 # ok 811 Set VL 4336
6707 10:07:00.320408 # ok 812 # SKIP Disabled ZA for VL 4336
6708 10:07:00.320503 # ok 813 # SKIP Get and set data for VL 4336
6709 10:07:00.320789 # ok 814 Set VL 4352
6710 10:07:00.320893 # ok 815 # SKIP Disabled ZA for VL 4352
6711 10:07:00.320977 # ok 816 # SKIP Get and set data for VL 4352
6712 10:07:00.321059 # ok 817 Set VL 4368
6713 10:07:00.321139 # ok 818 # SKIP Disabled ZA for VL 4368
6714 10:07:00.321225 # ok 819 # SKIP Get and set data for VL 4368
6715 10:07:00.321297 # ok 820 Set VL 4384
6716 10:07:00.321369 # ok 821 # SKIP Disabled ZA for VL 4384
6717 10:07:00.322289 # ok 822 # SKIP Get and set data for VL 4384
6718 10:07:00.322610 # ok 823 Set VL 4400
6719 10:07:00.322708 # ok 824 # SKIP Disabled ZA for VL 4400
6720 10:07:00.322808 # ok 825 # SKIP Get and set data for VL 4400
6721 10:07:00.322886 # ok 826 Set VL 4416
6722 10:07:00.322958 # ok 827 # SKIP Disabled ZA for VL 4416
6723 10:07:00.323030 # ok 828 # SKIP Get and set data for VL 4416
6724 10:07:00.340221 # ok 829 Set VL 4432
6725 10:07:00.340834 # ok 830 # SKIP Disabled ZA for VL 4432
6726 10:07:00.341029 # ok 831 # SKIP Get and set data for VL 4432
6727 10:07:00.341196 # ok 832 Set VL 4448
6728 10:07:00.341345 # ok 833 # SKIP Disabled ZA for VL 4448
6729 10:07:00.341489 # ok 834 # SKIP Get and set data for VL 4448
6730 10:07:00.341626 # ok 835 Set VL 4464
6731 10:07:00.341766 # ok 836 # SKIP Disabled ZA for VL 4464
6732 10:07:00.341882 # ok 837 # SKIP Get and set data for VL 4464
6733 10:07:00.342034 # ok 838 Set VL 4480
6734 10:07:00.342198 # ok 839 # SKIP Disabled ZA for VL 4480
6735 10:07:00.342330 # ok 840 # SKIP Get and set data for VL 4480
6736 10:07:00.342457 # ok 841 Set VL 4496
6737 10:07:00.342586 # ok 842 # SKIP Disabled ZA for VL 4496
6738 10:07:00.342734 # ok 843 # SKIP Get and set data for VL 4496
6739 10:07:00.342901 # ok 844 Set VL 4512
6740 10:07:00.343035 # ok 845 # SKIP Disabled ZA for VL 4512
6741 10:07:00.343149 # ok 846 # SKIP Get and set data for VL 4512
6742 10:07:00.343261 # ok 847 Set VL 4528
6743 10:07:00.343369 # ok 848 # SKIP Disabled ZA for VL 4528
6744 10:07:00.343481 # ok 849 # SKIP Get and set data for VL 4528
6745 10:07:00.343589 # ok 850 Set VL 4544
6746 10:07:00.343697 # ok 851 # SKIP Disabled ZA for VL 4544
6747 10:07:00.343806 # ok 852 # SKIP Get and set data for VL 4544
6748 10:07:00.343943 # ok 853 Set VL 4560
6749 10:07:00.344059 # ok 854 # SKIP Disabled ZA for VL 4560
6750 10:07:00.344170 # ok 855 # SKIP Get and set data for VL 4560
6751 10:07:00.344281 # ok 856 Set VL 4576
6752 10:07:00.344390 # ok 857 # SKIP Disabled ZA for VL 4576
6753 10:07:00.344498 # ok 858 # SKIP Get and set data for VL 4576
6754 10:07:00.344606 # ok 859 Set VL 4592
6755 10:07:00.344713 # ok 860 # SKIP Disabled ZA for VL 4592
6756 10:07:00.344821 # ok 861 # SKIP Get and set data for VL 4592
6757 10:07:00.344929 # ok 862 Set VL 4608
6758 10:07:00.345036 # ok 863 # SKIP Disabled ZA for VL 4608
6759 10:07:00.356953 # ok 864 # SKIP Get and set data for VL 4608
6760 10:07:00.357259 # ok 865 Set VL 4624
6761 10:07:00.357753 # ok 866 # SKIP Disabled ZA for VL 4624
6762 10:07:00.357937 # ok 867 # SKIP Get and set data for VL 4624
6763 10:07:00.358069 # ok 868 Set VL 4640
6764 10:07:00.358183 # ok 869 # SKIP Disabled ZA for VL 4640
6765 10:07:00.358294 # ok 870 # SKIP Get and set data for VL 4640
6766 10:07:00.358409 # ok 871 Set VL 4656
6767 10:07:00.358529 # ok 872 # SKIP Disabled ZA for VL 4656
6768 10:07:00.358655 # ok 873 # SKIP Get and set data for VL 4656
6769 10:07:00.358793 # ok 874 Set VL 4672
6770 10:07:00.358917 # ok 875 # SKIP Disabled ZA for VL 4672
6771 10:07:00.359263 # ok 876 # SKIP Get and set data for VL 4672
6772 10:07:00.359411 # ok 877 Set VL 4688
6773 10:07:00.359526 # ok 878 # SKIP Disabled ZA for VL 4688
6774 10:07:00.359639 # ok 879 # SKIP Get and set data for VL 4688
6775 10:07:00.359751 # ok 880 Set VL 4704
6776 10:07:00.359860 # ok 881 # SKIP Disabled ZA for VL 4704
6777 10:07:00.359971 # ok 882 # SKIP Get and set data for VL 4704
6778 10:07:00.360081 # ok 883 Set VL 4720
6779 10:07:00.360192 # ok 884 # SKIP Disabled ZA for VL 4720
6780 10:07:00.360301 # ok 885 # SKIP Get and set data for VL 4720
6781 10:07:00.360411 # ok 886 Set VL 4736
6782 10:07:00.360520 # ok 887 # SKIP Disabled ZA for VL 4736
6783 10:07:00.360633 # ok 888 # SKIP Get and set data for VL 4736
6784 10:07:00.360744 # ok 889 Set VL 4752
6785 10:07:00.372826 # ok 890 # SKIP Disabled ZA for VL 4752
6786 10:07:00.373177 # ok 891 # SKIP Get and set data for VL 4752
6787 10:07:00.373327 # ok 892 Set VL 4768
6788 10:07:00.373748 # ok 893 # SKIP Disabled ZA for VL 4768
6789 10:07:00.373924 # ok 894 # SKIP Get and set data for VL 4768
6790 10:07:00.374104 # ok 895 Set VL 4784
6791 10:07:00.374269 # ok 896 # SKIP Disabled ZA for VL 4784
6792 10:07:00.374457 # ok 897 # SKIP Get and set data for VL 4784
6793 10:07:00.374618 # ok 898 Set VL 4800
6794 10:07:00.374775 # ok 899 # SKIP Disabled ZA for VL 4800
6795 10:07:00.374903 # ok 900 # SKIP Get and set data for VL 4800
6796 10:07:00.375017 # ok 901 Set VL 4816
6797 10:07:00.375127 # ok 902 # SKIP Disabled ZA for VL 4816
6798 10:07:00.375265 # ok 903 # SKIP Get and set data for VL 4816
6799 10:07:00.375384 # ok 904 Set VL 4832
6800 10:07:00.375499 # ok 905 # SKIP Disabled ZA for VL 4832
6801 10:07:00.375611 # ok 906 # SKIP Get and set data for VL 4832
6802 10:07:00.375722 # ok 907 Set VL 4848
6803 10:07:00.375832 # ok 908 # SKIP Disabled ZA for VL 4848
6804 10:07:00.375942 # ok 909 # SKIP Get and set data for VL 4848
6805 10:07:00.376053 # ok 910 Set VL 4864
6806 10:07:00.376187 # ok 911 # SKIP Disabled ZA for VL 4864
6807 10:07:00.376303 # ok 912 # SKIP Get and set data for VL 4864
6808 10:07:00.376416 # ok 913 Set VL 4880
6809 10:07:00.376527 # ok 914 # SKIP Disabled ZA for VL 4880
6810 10:07:00.376636 # ok 915 # SKIP Get and set data for VL 4880
6811 10:07:00.376747 # ok 916 Set VL 4896
6812 10:07:00.376856 # ok 917 # SKIP Disabled ZA for VL 4896
6813 10:07:00.385545 # ok 918 # SKIP Get and set data for VL 4896
6814 10:07:00.385795 # ok 919 Set VL 4912
6815 10:07:00.386099 # ok 920 # SKIP Disabled ZA for VL 4912
6816 10:07:00.386199 # ok 921 # SKIP Get and set data for VL 4912
6817 10:07:00.386285 # ok 922 Set VL 4928
6818 10:07:00.386368 # ok 923 # SKIP Disabled ZA for VL 4928
6819 10:07:00.386452 # ok 924 # SKIP Get and set data for VL 4928
6820 10:07:00.386536 # ok 925 Set VL 4944
6821 10:07:00.386636 # ok 926 # SKIP Disabled ZA for VL 4944
6822 10:07:00.386724 # ok 927 # SKIP Get and set data for VL 4944
6823 10:07:00.386805 # ok 928 Set VL 4960
6824 10:07:00.386892 # ok 929 # SKIP Disabled ZA for VL 4960
6825 10:07:00.386961 # ok 930 # SKIP Get and set data for VL 4960
6826 10:07:00.387019 # ok 931 Set VL 4976
6827 10:07:00.387090 # ok 932 # SKIP Disabled ZA for VL 4976
6828 10:07:00.388104 # ok 933 # SKIP Get and set data for VL 4976
6829 10:07:00.388395 # ok 934 Set VL 4992
6830 10:07:00.388543 # ok 935 # SKIP Disabled ZA for VL 4992
6831 10:07:00.388690 # ok 936 # SKIP Get and set data for VL 4992
6832 10:07:00.388818 # ok 937 Set VL 5008
6833 10:07:00.388961 # ok 938 # SKIP Disabled ZA for VL 5008
6834 10:07:00.389109 # ok 939 # SKIP Get and set data for VL 5008
6835 10:07:00.389233 # ok 940 Set VL 5024
6836 10:07:00.389375 # ok 941 # SKIP Disabled ZA for VL 5024
6837 10:07:00.389520 # ok 942 # SKIP Get and set data for VL 5024
6838 10:07:00.389675 # ok 943 Set VL 5040
6839 10:07:00.389820 # ok 944 # SKIP Disabled ZA for VL 5040
6840 10:07:00.389963 # ok 945 # SKIP Get and set data for VL 5040
6841 10:07:00.390106 # ok 946 Set VL 5056
6842 10:07:00.390248 # ok 947 # SKIP Disabled ZA for VL 5056
6843 10:07:00.390389 # ok 948 # SKIP Get and set data for VL 5056
6844 10:07:00.390502 # ok 949 Set VL 5072
6845 10:07:00.390818 # ok 950 # SKIP Disabled ZA for VL 5072
6846 10:07:00.390981 # ok 951 # SKIP Get and set data for VL 5072
6847 10:07:00.391100 # ok 952 Set VL 5088
6848 10:07:00.397016 # ok 953 # SKIP Disabled ZA for VL 5088
6849 10:07:00.397568 # ok 954 # SKIP Get and set data for VL 5088
6850 10:07:00.397775 # ok 955 Set VL 5104
6851 10:07:00.397939 # ok 956 # SKIP Disabled ZA for VL 5104
6852 10:07:00.398082 # ok 957 # SKIP Get and set data for VL 5104
6853 10:07:00.398228 # ok 958 Set VL 5120
6854 10:07:00.398391 # ok 959 # SKIP Disabled ZA for VL 5120
6855 10:07:00.398581 # ok 960 # SKIP Get and set data for VL 5120
6856 10:07:00.398734 # ok 961 Set VL 5136
6857 10:07:00.398870 # ok 962 # SKIP Disabled ZA for VL 5136
6858 10:07:00.398985 # ok 963 # SKIP Get and set data for VL 5136
6859 10:07:00.399097 # ok 964 Set VL 5152
6860 10:07:00.399207 # ok 965 # SKIP Disabled ZA for VL 5152
6861 10:07:00.399317 # ok 966 # SKIP Get and set data for VL 5152
6862 10:07:00.399427 # ok 967 Set VL 5168
6863 10:07:00.399535 # ok 968 # SKIP Disabled ZA for VL 5168
6864 10:07:00.399645 # ok 969 # SKIP Get and set data for VL 5168
6865 10:07:00.399755 # ok 970 Set VL 5184
6866 10:07:00.399865 # ok 971 # SKIP Disabled ZA for VL 5184
6867 10:07:00.400000 # ok 972 # SKIP Get and set data for VL 5184
6868 10:07:00.400117 # ok 973 Set VL 5200
6869 10:07:00.400228 # ok 974 # SKIP Disabled ZA for VL 5200
6870 10:07:00.405130 # ok 975 # SKIP Get and set data for VL 5200
6871 10:07:00.405324 # ok 976 Set VL 5216
6872 10:07:00.405409 # ok 977 # SKIP Disabled ZA for VL 5216
6873 10:07:00.405513 # ok 978 # SKIP Get and set data for VL 5216
6874 10:07:00.405597 # ok 979 Set VL 5232
6875 10:07:00.405710 # ok 980 # SKIP Disabled ZA for VL 5232
6876 10:07:00.405837 # ok 981 # SKIP Get and set data for VL 5232
6877 10:07:00.405930 # ok 982 Set VL 5248
6878 10:07:00.406020 # ok 983 # SKIP Disabled ZA for VL 5248
6879 10:07:00.406097 # ok 984 # SKIP Get and set data for VL 5248
6880 10:07:00.406183 # ok 985 Set VL 5264
6881 10:07:00.406253 # ok 986 # SKIP Disabled ZA for VL 5264
6882 10:07:00.406332 # ok 987 # SKIP Get and set data for VL 5264
6883 10:07:00.406404 # ok 988 Set VL 5280
6884 10:07:00.406492 # ok 989 # SKIP Disabled ZA for VL 5280
6885 10:07:00.406566 # ok 990 # SKIP Get and set data for VL 5280
6886 10:07:00.406644 # ok 991 Set VL 5296
6887 10:07:00.406734 # ok 992 # SKIP Disabled ZA for VL 5296
6888 10:07:00.406833 # ok 993 # SKIP Get and set data for VL 5296
6889 10:07:00.406916 # ok 994 Set VL 5312
6890 10:07:00.413341 # ok 995 # SKIP Disabled ZA for VL 5312
6891 10:07:00.413797 # ok 996 # SKIP Get and set data for VL 5312
6892 10:07:00.413995 # ok 997 Set VL 5328
6893 10:07:00.414158 # ok 998 # SKIP Disabled ZA for VL 5328
6894 10:07:00.414318 # ok 999 # SKIP Get and set data for VL 5328
6895 10:07:00.414486 # ok 1000 Set VL 5344
6896 10:07:00.414688 # ok 1001 # SKIP Disabled ZA for VL 5344
6897 10:07:00.414854 # ok 1002 # SKIP Get and set data for VL 5344
6898 10:07:00.414981 # ok 1003 Set VL 5360
6899 10:07:00.415097 # ok 1004 # SKIP Disabled ZA for VL 5360
6900 10:07:00.415210 # ok 1005 # SKIP Get and set data for VL 5360
6901 10:07:00.415325 # ok 1006 Set VL 5376
6902 10:07:00.415438 # ok 1007 # SKIP Disabled ZA for VL 5376
6903 10:07:00.415552 # ok 1008 # SKIP Get and set data for VL 5376
6904 10:07:00.415666 # ok 1009 Set VL 5392
6905 10:07:00.415779 # ok 1010 # SKIP Disabled ZA for VL 5392
6906 10:07:00.415917 # ok 1011 # SKIP Get and set data for VL 5392
6907 10:07:00.416036 # ok 1012 Set VL 5408
6908 10:07:00.422572 # ok 1013 # SKIP Disabled ZA for VL 5408
6909 10:07:00.422814 # ok 1014 # SKIP Get and set data for VL 5408
6910 10:07:00.423092 # ok 1015 Set VL 5424
6911 10:07:00.423163 # ok 1016 # SKIP Disabled ZA for VL 5424
6912 10:07:00.423224 # ok 1017 # SKIP Get and set data for VL 5424
6913 10:07:00.424843 # ok 1018 Set VL 5440
6914 10:07:00.424944 # ok 1019 # SKIP Disabled ZA for VL 5440
6915 10:07:00.425050 # ok 1020 # SKIP Get and set data for VL 5440
6916 10:07:00.425137 # ok 1021 Set VL 5456
6917 10:07:00.425217 # ok 1022 # SKIP Disabled ZA for VL 5456
6918 10:07:00.425497 # ok 1023 # SKIP Get and set data for VL 5456
6919 10:07:00.425603 # ok 1024 Set VL 5472
6920 10:07:00.425705 # ok 1025 # SKIP Disabled ZA for VL 5472
6921 10:07:00.425793 # ok 1026 # SKIP Get and set data for VL 5472
6922 10:07:00.425877 # ok 1027 Set VL 5488
6923 10:07:00.425964 # ok 1028 # SKIP Disabled ZA for VL 5488
6924 10:07:00.426052 # ok 1029 # SKIP Get and set data for VL 5488
6925 10:07:00.426140 # ok 1030 Set VL 5504
6926 10:07:00.426241 # ok 1031 # SKIP Disabled ZA for VL 5504
6927 10:07:00.426327 # ok 1032 # SKIP Get and set data for VL 5504
6928 10:07:00.426411 # ok 1033 Set VL 5520
6929 10:07:00.426494 # ok 1034 # SKIP Disabled ZA for VL 5520
6930 10:07:00.426578 # ok 1035 # SKIP Get and set data for VL 5520
6931 10:07:00.426662 # ok 1036 Set VL 5536
6932 10:07:00.426762 # ok 1037 # SKIP Disabled ZA for VL 5536
6933 10:07:00.426847 # ok 1038 # SKIP Get and set data for VL 5536
6934 10:07:00.426921 # ok 1039 Set VL 5552
6935 10:07:00.426993 # ok 1040 # SKIP Disabled ZA for VL 5552
6936 10:07:00.427079 # ok 1041 # SKIP Get and set data for VL 5552
6937 10:07:00.432499 # ok 1042 Set VL 5568
6938 10:07:00.433093 # ok 1043 # SKIP Disabled ZA for VL 5568
6939 10:07:00.433271 # ok 1044 # SKIP Get and set data for VL 5568
6940 10:07:00.433407 # ok 1045 Set VL 5584
6941 10:07:00.433525 # ok 1046 # SKIP Disabled ZA for VL 5584
6942 10:07:00.433644 # ok 1047 # SKIP Get and set data for VL 5584
6943 10:07:00.433775 # ok 1048 Set VL 5600
6944 10:07:00.433888 # ok 1049 # SKIP Disabled ZA for VL 5600
6945 10:07:00.434025 # ok 1050 # SKIP Get and set data for VL 5600
6946 10:07:00.434142 # ok 1051 Set VL 5616
6947 10:07:00.434255 # ok 1052 # SKIP Disabled ZA for VL 5616
6948 10:07:00.434975 # ok 1053 # SKIP Get and set data for VL 5616
6949 10:07:00.435128 # ok 1054 Set VL 5632
6950 10:07:00.440677 # ok 1055 # SKIP Disabled ZA for VL 5632
6951 10:07:00.440855 # ok 1056 # SKIP Get and set data for VL 5632
6952 10:07:00.441017 # ok 1057 Set VL 5648
6953 10:07:00.441190 # ok 1058 # SKIP Disabled ZA for VL 5648
6954 10:07:00.441329 # ok 1059 # SKIP Get and set data for VL 5648
6955 10:07:00.441506 # ok 1060 Set VL 5664
6956 10:07:00.441684 # ok 1061 # SKIP Disabled ZA for VL 5664
6957 10:07:00.441881 # ok 1062 # SKIP Get and set data for VL 5664
6958 10:07:00.442048 # ok 1063 Set VL 5680
6959 10:07:00.442209 # ok 1064 # SKIP Disabled ZA for VL 5680
6960 10:07:00.442370 # ok 1065 # SKIP Get and set data for VL 5680
6961 10:07:00.442528 # ok 1066 Set VL 5696
6962 10:07:00.442685 # ok 1067 # SKIP Disabled ZA for VL 5696
6963 10:07:00.442824 # ok 1068 # SKIP Get and set data for VL 5696
6964 10:07:00.442940 # ok 1069 Set VL 5712
6965 10:07:00.443054 # ok 1070 # SKIP Disabled ZA for VL 5712
6966 10:07:00.443198 # ok 1071 # SKIP Get and set data for VL 5712
6967 10:07:00.443318 # ok 1072 Set VL 5728
6968 10:07:00.443452 # ok 1073 # SKIP Disabled ZA for VL 5728
6969 10:07:00.443612 # ok 1074 # SKIP Get and set data for VL 5728
6970 10:07:00.443771 # ok 1075 Set VL 5744
6971 10:07:00.443927 # ok 1076 # SKIP Disabled ZA for VL 5744
6972 10:07:00.444089 # ok 1077 # SKIP Get and set data for VL 5744
6973 10:07:00.444243 # ok 1078 Set VL 5760
6974 10:07:00.444363 # ok 1079 # SKIP Disabled ZA for VL 5760
6975 10:07:00.444509 # ok 1080 # SKIP Get and set data for VL 5760
6976 10:07:00.444640 # ok 1081 Set VL 5776
6977 10:07:00.444759 # ok 1082 # SKIP Disabled ZA for VL 5776
6978 10:07:00.444875 # ok 1083 # SKIP Get and set data for VL 5776
6979 10:07:00.444992 # ok 1084 Set VL 5792
6980 10:07:00.445107 # ok 1085 # SKIP Disabled ZA for VL 5792
6981 10:07:00.445222 # ok 1086 # SKIP Get and set data for VL 5792
6982 10:07:00.445341 # ok 1087 Set VL 5808
6983 10:07:00.445455 # ok 1088 # SKIP Disabled ZA for VL 5808
6984 10:07:00.445580 # ok 1089 # SKIP Get and set data for VL 5808
6985 10:07:00.446160 # ok 1090 Set VL 5824
6986 10:07:00.446337 # ok 1091 # SKIP Disabled ZA for VL 5824
6987 10:07:00.446545 # ok 1092 # SKIP Get and set data for VL 5824
6988 10:07:00.446713 # ok 1093 Set VL 5840
6989 10:07:00.446868 # ok 1094 # SKIP Disabled ZA for VL 5840
6990 10:07:00.446987 # ok 1095 # SKIP Get and set data for VL 5840
6991 10:07:00.447099 # ok 1096 Set VL 5856
6992 10:07:00.447209 # ok 1097 # SKIP Disabled ZA for VL 5856
6993 10:07:00.447318 # ok 1098 # SKIP Get and set data for VL 5856
6994 10:07:00.447428 # ok 1099 Set VL 5872
6995 10:07:00.447536 # ok 1100 # SKIP Disabled ZA for VL 5872
6996 10:07:00.447643 # ok 1101 # SKIP Get and set data for VL 5872
6997 10:07:00.447751 # ok 1102 Set VL 5888
6998 10:07:00.447858 # ok 1103 # SKIP Disabled ZA for VL 5888
6999 10:07:00.447967 # ok 1104 # SKIP Get and set data for VL 5888
7000 10:07:00.448075 # ok 1105 Set VL 5904
7001 10:07:00.448184 # ok 1106 # SKIP Disabled ZA for VL 5904
7002 10:07:00.448527 # ok 1107 # SKIP Get and set data for VL 5904
7003 10:07:00.448705 # ok 1108 Set VL 5920
7004 10:07:00.448840 # ok 1109 # SKIP Disabled ZA for VL 5920
7005 10:07:00.448961 # ok 1110 # SKIP Get and set data for VL 5920
7006 10:07:00.449080 # ok 1111 Set VL 5936
7007 10:07:00.449196 # ok 1112 # SKIP Disabled ZA for VL 5936
7008 10:07:00.449311 # ok 1113 # SKIP Get and set data for VL 5936
7009 10:07:00.449430 # ok 1114 Set VL 5952
7010 10:07:00.449547 # ok 1115 # SKIP Disabled ZA for VL 5952
7011 10:07:00.449678 # ok 1116 # SKIP Get and set data for VL 5952
7012 10:07:00.449796 # ok 1117 Set VL 5968
7013 10:07:00.456536 # ok 1118 # SKIP Disabled ZA for VL 5968
7014 10:07:00.456943 # ok 1119 # SKIP Get and set data for VL 5968
7015 10:07:00.457089 # ok 1120 Set VL 5984
7016 10:07:00.457246 # ok 1121 # SKIP Disabled ZA for VL 5984
7017 10:07:00.457399 # ok 1122 # SKIP Get and set data for VL 5984
7018 10:07:00.457572 # ok 1123 Set VL 6000
7019 10:07:00.457773 # ok 1124 # SKIP Disabled ZA for VL 6000
7020 10:07:00.457913 # ok 1125 # SKIP Get and set data for VL 6000
7021 10:07:00.458054 # ok 1126 Set VL 6016
7022 10:07:00.458194 # ok 1127 # SKIP Disabled ZA for VL 6016
7023 10:07:00.458354 # ok 1128 # SKIP Get and set data for VL 6016
7024 10:07:00.458530 # ok 1129 Set VL 6032
7025 10:07:00.458679 # ok 1130 # SKIP Disabled ZA for VL 6032
7026 10:07:00.458858 # ok 1131 # SKIP Get and set data for VL 6032
7027 10:07:00.458997 # ok 1132 Set VL 6048
7028 10:07:00.459144 # ok 1133 # SKIP Disabled ZA for VL 6048
7029 10:07:00.459268 # ok 1134 # SKIP Get and set data for VL 6048
7030 10:07:00.459387 # ok 1135 Set VL 6064
7031 10:07:00.459502 # ok 1136 # SKIP Disabled ZA for VL 6064
7032 10:07:00.459618 # ok 1137 # SKIP Get and set data for VL 6064
7033 10:07:00.459757 # ok 1138 Set VL 6080
7034 10:07:00.459882 # ok 1139 # SKIP Disabled ZA for VL 6080
7035 10:07:00.460005 # ok 1140 # SKIP Get and set data for VL 6080
7036 10:07:00.460181 # ok 1141 Set VL 6096
7037 10:07:00.460353 # ok 1142 # SKIP Disabled ZA for VL 6096
7038 10:07:00.460498 # ok 1143 # SKIP Get and set data for VL 6096
7039 10:07:00.460643 # ok 1144 Set VL 6112
7040 10:07:00.460842 # ok 1145 # SKIP Disabled ZA for VL 6112
7041 10:07:00.461027 # ok 1146 # SKIP Get and set data for VL 6112
7042 10:07:00.461204 # ok 1147 Set VL 6128
7043 10:07:00.461361 # ok 1148 # SKIP Disabled ZA for VL 6128
7044 10:07:00.461511 # ok 1149 # SKIP Get and set data for VL 6128
7045 10:07:00.461660 # ok 1150 Set VL 6144
7046 10:07:00.461820 # ok 1151 # SKIP Disabled ZA for VL 6144
7047 10:07:00.462008 # ok 1152 # SKIP Get and set data for VL 6144
7048 10:07:00.462197 # ok 1153 Set VL 6160
7049 10:07:00.462383 # ok 1154 # SKIP Disabled ZA for VL 6160
7050 10:07:00.462554 # ok 1155 # SKIP Get and set data for VL 6160
7051 10:07:00.462750 # ok 1156 Set VL 6176
7052 10:07:00.462957 # ok 1157 # SKIP Disabled ZA for VL 6176
7053 10:07:00.463100 # ok 1158 # SKIP Get and set data for VL 6176
7054 10:07:00.463224 # ok 1159 Set VL 6192
7055 10:07:00.463339 # ok 1160 # SKIP Disabled ZA for VL 6192
7056 10:07:00.463455 # ok 1161 # SKIP Get and set data for VL 6192
7057 10:07:00.463573 # ok 1162 Set VL 6208
7058 10:07:00.463687 # ok 1163 # SKIP Disabled ZA for VL 6208
7059 10:07:00.463854 # ok 1164 # SKIP Get and set data for VL 6208
7060 10:07:00.463982 # ok 1165 Set VL 6224
7061 10:07:00.464098 # ok 1166 # SKIP Disabled ZA for VL 6224
7062 10:07:00.464214 # ok 1167 # SKIP Get and set data for VL 6224
7063 10:07:00.464330 # ok 1168 Set VL 6240
7064 10:07:00.464444 # ok 1169 # SKIP Disabled ZA for VL 6240
7065 10:07:00.464559 # ok 1170 # SKIP Get and set data for VL 6240
7066 10:07:00.464672 # ok 1171 Set VL 6256
7067 10:07:00.465000 # ok 1172 # SKIP Disabled ZA for VL 6256
7068 10:07:00.465131 # ok 1173 # SKIP Get and set data for VL 6256
7069 10:07:00.465250 # ok 1174 Set VL 6272
7070 10:07:00.465367 # ok 1175 # SKIP Disabled ZA for VL 6272
7071 10:07:00.465482 # ok 1176 # SKIP Get and set data for VL 6272
7072 10:07:00.465598 # ok 1177 Set VL 6288
7073 10:07:00.465736 # ok 1178 # SKIP Disabled ZA for VL 6288
7074 10:07:00.465854 # ok 1179 # SKIP Get and set data for VL 6288
7075 10:07:00.465972 # ok 1180 Set VL 6304
7076 10:07:00.469975 # ok 1181 # SKIP Disabled ZA for VL 6304
7077 10:07:00.470353 # ok 1182 # SKIP Get and set data for VL 6304
7078 10:07:00.470464 # ok 1183 Set VL 6320
7079 10:07:00.470547 # ok 1184 # SKIP Disabled ZA for VL 6320
7080 10:07:00.470629 # ok 1185 # SKIP Get and set data for VL 6320
7081 10:07:00.470713 # ok 1186 Set VL 6336
7082 10:07:00.470817 # ok 1187 # SKIP Disabled ZA for VL 6336
7083 10:07:00.470906 # ok 1188 # SKIP Get and set data for VL 6336
7084 10:07:00.470991 # ok 1189 Set VL 6352
7085 10:07:00.471075 # ok 1190 # SKIP Disabled ZA for VL 6352
7086 10:07:00.471175 # ok 1191 # SKIP Get and set data for VL 6352
7087 10:07:00.480542 # ok 1192 Set VL 6368
7088 10:07:00.480791 # ok 1193 # SKIP Disabled ZA for VL 6368
7089 10:07:00.481088 # ok 1194 # SKIP Get and set data for VL 6368
7090 10:07:00.481191 # ok 1195 Set VL 6384
7091 10:07:00.481275 # ok 1196 # SKIP Disabled ZA for VL 6384
7092 10:07:00.481355 # ok 1197 # SKIP Get and set data for VL 6384
7093 10:07:00.481434 # ok 1198 Set VL 6400
7094 10:07:00.481512 # ok 1199 # SKIP Disabled ZA for VL 6400
7095 10:07:00.481606 # ok 1200 # SKIP Get and set data for VL 6400
7096 10:07:00.481698 # ok 1201 Set VL 6416
7097 10:07:00.481776 # ok 1202 # SKIP Disabled ZA for VL 6416
7098 10:07:00.481854 # ok 1203 # SKIP Get and set data for VL 6416
7099 10:07:00.481931 # ok 1204 Set VL 6432
7100 10:07:00.482007 # ok 1205 # SKIP Disabled ZA for VL 6432
7101 10:07:00.482100 # ok 1206 # SKIP Get and set data for VL 6432
7102 10:07:00.482179 # ok 1207 Set VL 6448
7103 10:07:00.482255 # ok 1208 # SKIP Disabled ZA for VL 6448
7104 10:07:00.482346 # ok 1209 # SKIP Get and set data for VL 6448
7105 10:07:00.482428 # ok 1210 Set VL 6464
7106 10:07:00.482505 # ok 1211 # SKIP Disabled ZA for VL 6464
7107 10:07:00.482594 # ok 1212 # SKIP Get and set data for VL 6464
7108 10:07:00.482677 # ok 1213 Set VL 6480
7109 10:07:00.482752 # ok 1214 # SKIP Disabled ZA for VL 6480
7110 10:07:00.482840 # ok 1215 # SKIP Get and set data for VL 6480
7111 10:07:00.482917 # ok 1216 Set VL 6496
7112 10:07:00.482992 # ok 1217 # SKIP Disabled ZA for VL 6496
7113 10:07:00.488216 # ok 1218 # SKIP Get and set data for VL 6496
7114 10:07:00.488528 # ok 1219 Set VL 6512
7115 10:07:00.488636 # ok 1220 # SKIP Disabled ZA for VL 6512
7116 10:07:00.488721 # ok 1221 # SKIP Get and set data for VL 6512
7117 10:07:00.488845 # ok 1222 Set VL 6528
7118 10:07:00.488932 # ok 1223 # SKIP Disabled ZA for VL 6528
7119 10:07:00.489010 # ok 1224 # SKIP Get and set data for VL 6528
7120 10:07:00.489090 # ok 1225 Set VL 6544
7121 10:07:00.489167 # ok 1226 # SKIP Disabled ZA for VL 6544
7122 10:07:00.489259 # ok 1227 # SKIP Get and set data for VL 6544
7123 10:07:00.489340 # ok 1228 Set VL 6560
7124 10:07:00.489417 # ok 1229 # SKIP Disabled ZA for VL 6560
7125 10:07:00.489493 # ok 1230 # SKIP Get and set data for VL 6560
7126 10:07:00.489569 # ok 1231 Set VL 6576
7127 10:07:00.489671 # ok 1232 # SKIP Disabled ZA for VL 6576
7128 10:07:00.489752 # ok 1233 # SKIP Get and set data for VL 6576
7129 10:07:00.489829 # ok 1234 Set VL 6592
7130 10:07:00.489905 # ok 1235 # SKIP Disabled ZA for VL 6592
7131 10:07:00.489995 # ok 1236 # SKIP Get and set data for VL 6592
7132 10:07:00.490074 # ok 1237 Set VL 6608
7133 10:07:00.490150 # ok 1238 # SKIP Disabled ZA for VL 6608
7134 10:07:00.490239 # ok 1239 # SKIP Get and set data for VL 6608
7135 10:07:00.490317 # ok 1240 Set VL 6624
7136 10:07:00.490406 # ok 1241 # SKIP Disabled ZA for VL 6624
7137 10:07:00.490484 # ok 1242 # SKIP Get and set data for VL 6624
7138 10:07:00.490558 # ok 1243 Set VL 6640
7139 10:07:00.490650 # ok 1244 # SKIP Disabled ZA for VL 6640
7140 10:07:00.490737 # ok 1245 # SKIP Get and set data for VL 6640
7141 10:07:00.490826 # ok 1246 Set VL 6656
7142 10:07:00.490905 # ok 1247 # SKIP Disabled ZA for VL 6656
7143 10:07:00.493704 # ok 1248 # SKIP Get and set data for VL 6656
7144 10:07:00.493992 # ok 1249 Set VL 6672
7145 10:07:00.494093 # ok 1250 # SKIP Disabled ZA for VL 6672
7146 10:07:00.494186 # ok 1251 # SKIP Get and set data for VL 6672
7147 10:07:00.494266 # ok 1252 Set VL 6688
7148 10:07:00.494344 # ok 1253 # SKIP Disabled ZA for VL 6688
7149 10:07:00.494434 # ok 1254 # SKIP Get and set data for VL 6688
7150 10:07:00.494514 # ok 1255 Set VL 6704
7151 10:07:00.494603 # ok 1256 # SKIP Disabled ZA for VL 6704
7152 10:07:00.494683 # ok 1257 # SKIP Get and set data for VL 6704
7153 10:07:00.494772 # ok 1258 Set VL 6720
7154 10:07:00.494849 # ok 1259 # SKIP Disabled ZA for VL 6720
7155 10:07:00.495532 # ok 1260 # SKIP Get and set data for VL 6720
7156 10:07:00.495729 # ok 1261 Set VL 6736
7157 10:07:00.496116 # ok 1262 # SKIP Disabled ZA for VL 6736
7158 10:07:00.496288 # ok 1263 # SKIP Get and set data for VL 6736
7159 10:07:00.496447 # ok 1264 Set VL 6752
7160 10:07:00.496586 # ok 1265 # SKIP Disabled ZA for VL 6752
7161 10:07:00.496712 # ok 1266 # SKIP Get and set data for VL 6752
7162 10:07:00.496864 # ok 1267 Set VL 6768
7163 10:07:00.497071 # ok 1268 # SKIP Disabled ZA for VL 6768
7164 10:07:00.497208 # ok 1269 # SKIP Get and set data for VL 6768
7165 10:07:00.497325 # ok 1270 Set VL 6784
7166 10:07:00.497437 # ok 1271 # SKIP Disabled ZA for VL 6784
7167 10:07:00.497549 # ok 1272 # SKIP Get and set data for VL 6784
7168 10:07:00.497679 # ok 1273 Set VL 6800
7169 10:07:00.497794 # ok 1274 # SKIP Disabled ZA for VL 6800
7170 10:07:00.497906 # ok 1275 # SKIP Get and set data for VL 6800
7171 10:07:00.498066 # ok 1276 Set VL 6816
7172 10:07:00.498257 # ok 1277 # SKIP Disabled ZA for VL 6816
7173 10:07:00.498472 # ok 1278 # SKIP Get and set data for VL 6816
7174 10:07:00.498635 # ok 1279 Set VL 6832
7175 10:07:00.498871 # ok 1280 # SKIP Disabled ZA for VL 6832
7176 10:07:00.499041 # ok 1281 # SKIP Get and set data for VL 6832
7177 10:07:00.499185 # ok 1282 Set VL 6848
7178 10:07:00.499360 # ok 1283 # SKIP Disabled ZA for VL 6848
7179 10:07:00.499498 # ok 1284 # SKIP Get and set data for VL 6848
7180 10:07:00.499639 # ok 1285 Set VL 6864
7181 10:07:00.499779 # ok 1286 # SKIP Disabled ZA for VL 6864
7182 10:07:00.504263 # ok 1287 # SKIP Get and set data for VL 6864
7183 10:07:00.504450 # ok 1288 Set VL 6880
7184 10:07:00.504627 # ok 1289 # SKIP Disabled ZA for VL 6880
7185 10:07:00.504857 # ok 1290 # SKIP Get and set data for VL 6880
7186 10:07:00.505016 # ok 1291 Set VL 6896
7187 10:07:00.505178 # ok 1292 # SKIP Disabled ZA for VL 6896
7188 10:07:00.505348 # ok 1293 # SKIP Get and set data for VL 6896
7189 10:07:00.505489 # ok 1294 Set VL 6912
7190 10:07:00.505628 # ok 1295 # SKIP Disabled ZA for VL 6912
7191 10:07:00.505820 # ok 1296 # SKIP Get and set data for VL 6912
7192 10:07:00.505955 # ok 1297 Set VL 6928
7193 10:07:00.506096 # ok 1298 # SKIP Disabled ZA for VL 6928
7194 10:07:00.506236 # ok 1299 # SKIP Get and set data for VL 6928
7195 10:07:00.506377 # ok 1300 Set VL 6944
7196 10:07:00.506515 # ok 1301 # SKIP Disabled ZA for VL 6944
7197 10:07:00.506677 # ok 1302 # SKIP Get and set data for VL 6944
7198 10:07:00.506826 # ok 1303 Set VL 6960
7199 10:07:00.506965 # ok 1304 # SKIP Disabled ZA for VL 6960
7200 10:07:00.507104 # ok 1305 # SKIP Get and set data for VL 6960
7201 10:07:00.507242 # ok 1306 Set VL 6976
7202 10:07:00.507415 # ok 1307 # SKIP Disabled ZA for VL 6976
7203 10:07:00.507547 # ok 1308 # SKIP Get and set data for VL 6976
7204 10:07:00.507688 # ok 1309 Set VL 6992
7205 10:07:00.507827 # ok 1310 # SKIP Disabled ZA for VL 6992
7206 10:07:00.507965 # ok 1311 # SKIP Get and set data for VL 6992
7207 10:07:00.508103 # ok 1312 Set VL 7008
7208 10:07:00.508241 # ok 1313 # SKIP Disabled ZA for VL 7008
7209 10:07:00.508379 # ok 1314 # SKIP Get and set data for VL 7008
7210 10:07:00.508519 # ok 1315 Set VL 7024
7211 10:07:00.508657 # ok 1316 # SKIP Disabled ZA for VL 7024
7212 10:07:00.515767 # ok 1317 # SKIP Get and set data for VL 7024
7213 10:07:00.516209 # ok 1318 Set VL 7040
7214 10:07:00.516396 # ok 1319 # SKIP Disabled ZA for VL 7040
7215 10:07:00.516538 # ok 1320 # SKIP Get and set data for VL 7040
7216 10:07:00.516697 # ok 1321 Set VL 7056
7217 10:07:00.516844 # ok 1322 # SKIP Disabled ZA for VL 7056
7218 10:07:00.517015 # ok 1323 # SKIP Get and set data for VL 7056
7219 10:07:00.517185 # ok 1324 Set VL 7072
7220 10:07:00.517378 # ok 1325 # SKIP Disabled ZA for VL 7072
7221 10:07:00.517549 # ok 1326 # SKIP Get and set data for VL 7072
7222 10:07:00.517760 # ok 1327 Set VL 7088
7223 10:07:00.517932 # ok 1328 # SKIP Disabled ZA for VL 7088
7224 10:07:00.518080 # ok 1329 # SKIP Get and set data for VL 7088
7225 10:07:00.518228 # ok 1330 Set VL 7104
7226 10:07:00.518375 # ok 1331 # SKIP Disabled ZA for VL 7104
7227 10:07:00.518526 # ok 1332 # SKIP Get and set data for VL 7104
7228 10:07:00.518705 # ok 1333 Set VL 7120
7229 10:07:00.518848 # ok 1334 # SKIP Disabled ZA for VL 7120
7230 10:07:00.518963 # ok 1335 # SKIP Get and set data for VL 7120
7231 10:07:00.519074 # ok 1336 Set VL 7136
7232 10:07:00.519184 # ok 1337 # SKIP Disabled ZA for VL 7136
7233 10:07:00.519295 # ok 1338 # SKIP Get and set data for VL 7136
7234 10:07:00.519406 # ok 1339 Set VL 7152
7235 10:07:00.519516 # ok 1340 # SKIP Disabled ZA for VL 7152
7236 10:07:00.519625 # ok 1341 # SKIP Get and set data for VL 7152
7237 10:07:00.519735 # ok 1342 Set VL 7168
7238 10:07:00.519845 # ok 1343 # SKIP Disabled ZA for VL 7168
7239 10:07:00.519955 # ok 1344 # SKIP Get and set data for VL 7168
7240 10:07:00.520065 # ok 1345 Set VL 7184
7241 10:07:00.520173 # ok 1346 # SKIP Disabled ZA for VL 7184
7242 10:07:00.520283 # ok 1347 # SKIP Get and set data for VL 7184
7243 10:07:00.520394 # ok 1348 Set VL 7200
7244 10:07:00.520504 # ok 1349 # SKIP Disabled ZA for VL 7200
7245 10:07:00.520614 # ok 1350 # SKIP Get and set data for VL 7200
7246 10:07:00.520723 # ok 1351 Set VL 7216
7247 10:07:00.520834 # ok 1352 # SKIP Disabled ZA for VL 7216
7248 10:07:00.520968 # ok 1353 # SKIP Get and set data for VL 7216
7249 10:07:00.523518 # ok 1354 Set VL 7232
7250 10:07:00.523949 # ok 1355 # SKIP Disabled ZA for VL 7232
7251 10:07:00.524131 # ok 1356 # SKIP Get and set data for VL 7232
7252 10:07:00.524323 # ok 1357 Set VL 7248
7253 10:07:00.524493 # ok 1358 # SKIP Disabled ZA for VL 7248
7254 10:07:00.524641 # ok 1359 # SKIP Get and set data for VL 7248
7255 10:07:00.524787 # ok 1360 Set VL 7264
7256 10:07:00.524958 # ok 1361 # SKIP Disabled ZA for VL 7264
7257 10:07:00.525084 # ok 1362 # SKIP Get and set data for VL 7264
7258 10:07:00.525203 # ok 1363 Set VL 7280
7259 10:07:00.525318 # ok 1364 # SKIP Disabled ZA for VL 7280
7260 10:07:00.525433 # ok 1365 # SKIP Get and set data for VL 7280
7261 10:07:00.525549 # ok 1366 Set VL 7296
7262 10:07:00.525677 # ok 1367 # SKIP Disabled ZA for VL 7296
7263 10:07:00.525795 # ok 1368 # SKIP Get and set data for VL 7296
7264 10:07:00.525935 # ok 1369 Set VL 7312
7265 10:07:00.526100 # ok 1370 # SKIP Disabled ZA for VL 7312
7266 10:07:00.526292 # ok 1371 # SKIP Get and set data for VL 7312
7267 10:07:00.526461 # ok 1372 Set VL 7328
7268 10:07:00.526654 # ok 1373 # SKIP Disabled ZA for VL 7328
7269 10:07:00.526811 # ok 1374 # SKIP Get and set data for VL 7328
7270 10:07:00.526931 # ok 1375 Set VL 7344
7271 10:07:00.527046 # ok 1376 # SKIP Disabled ZA for VL 7344
7272 10:07:00.527160 # ok 1377 # SKIP Get and set data for VL 7344
7273 10:07:00.527273 # ok 1378 Set VL 7360
7274 10:07:00.527386 # ok 1379 # SKIP Disabled ZA for VL 7360
7275 10:07:00.527500 # ok 1380 # SKIP Get and set data for VL 7360
7276 10:07:00.527611 # ok 1381 Set VL 7376
7277 10:07:00.527722 # ok 1382 # SKIP Disabled ZA for VL 7376
7278 10:07:00.527837 # ok 1383 # SKIP Get and set data for VL 7376
7279 10:07:00.527950 # ok 1384 Set VL 7392
7280 10:07:00.528062 # ok 1385 # SKIP Disabled ZA for VL 7392
7281 10:07:00.528175 # ok 1386 # SKIP Get and set data for VL 7392
7282 10:07:00.528288 # ok 1387 Set VL 7408
7283 10:07:00.528399 # ok 1388 # SKIP Disabled ZA for VL 7408
7284 10:07:00.528511 # ok 1389 # SKIP Get and set data for VL 7408
7285 10:07:00.528623 # ok 1390 Set VL 7424
7286 10:07:00.528734 # ok 1391 # SKIP Disabled ZA for VL 7424
7287 10:07:00.528872 # ok 1392 # SKIP Get and set data for VL 7424
7288 10:07:00.528991 # ok 1393 Set VL 7440
7289 10:07:00.536478 # ok 1394 # SKIP Disabled ZA for VL 7440
7290 10:07:00.536957 # ok 1395 # SKIP Get and set data for VL 7440
7291 10:07:00.537158 # ok 1396 Set VL 7456
7292 10:07:00.537373 # ok 1397 # SKIP Disabled ZA for VL 7456
7293 10:07:00.537575 # ok 1398 # SKIP Get and set data for VL 7456
7294 10:07:00.537772 # ok 1399 Set VL 7472
7295 10:07:00.537949 # ok 1400 # SKIP Disabled ZA for VL 7472
7296 10:07:00.538143 # ok 1401 # SKIP Get and set data for VL 7472
7297 10:07:00.538296 # ok 1402 Set VL 7488
7298 10:07:00.538445 # ok 1403 # SKIP Disabled ZA for VL 7488
7299 10:07:00.538599 # ok 1404 # SKIP Get and set data for VL 7488
7300 10:07:00.538747 # ok 1405 Set VL 7504
7301 10:07:00.538897 # ok 1406 # SKIP Disabled ZA for VL 7504
7302 10:07:00.539024 # ok 1407 # SKIP Get and set data for VL 7504
7303 10:07:00.539136 # ok 1408 Set VL 7520
7304 10:07:00.539246 # ok 1409 # SKIP Disabled ZA for VL 7520
7305 10:07:00.539355 # ok 1410 # SKIP Get and set data for VL 7520
7306 10:07:00.539463 # ok 1411 Set VL 7536
7307 10:07:00.539572 # ok 1412 # SKIP Disabled ZA for VL 7536
7308 10:07:00.539681 # ok 1413 # SKIP Get and set data for VL 7536
7309 10:07:00.539790 # ok 1414 Set VL 7552
7310 10:07:00.539897 # ok 1415 # SKIP Disabled ZA for VL 7552
7311 10:07:00.540005 # ok 1416 # SKIP Get and set data for VL 7552
7312 10:07:00.540141 # ok 1417 Set VL 7568
7313 10:07:00.540258 # ok 1418 # SKIP Disabled ZA for VL 7568
7314 10:07:00.540372 # ok 1419 # SKIP Get and set data for VL 7568
7315 10:07:00.540483 # ok 1420 Set VL 7584
7316 10:07:00.540592 # ok 1421 # SKIP Disabled ZA for VL 7584
7317 10:07:00.540700 # ok 1422 # SKIP Get and set data for VL 7584
7318 10:07:00.540808 # ok 1423 Set VL 7600
7319 10:07:00.540917 # ok 1424 # SKIP Disabled ZA for VL 7600
7320 10:07:00.552771 # ok 1425 # SKIP Get and set data for VL 7600
7321 10:07:00.552972 # ok 1426 Set VL 7616
7322 10:07:00.553175 # ok 1427 # SKIP Disabled ZA for VL 7616
7323 10:07:00.553399 # ok 1428 # SKIP Get and set data for VL 7616
7324 10:07:00.553559 # ok 1429 Set VL 7632
7325 10:07:00.553708 # ok 1430 # SKIP Disabled ZA for VL 7632
7326 10:07:00.553838 # ok 1431 # SKIP Get and set data for VL 7632
7327 10:07:00.554021 # ok 1432 Set VL 7648
7328 10:07:00.554217 # ok 1433 # SKIP Disabled ZA for VL 7648
7329 10:07:00.554433 # ok 1434 # SKIP Get and set data for VL 7648
7330 10:07:00.554662 # ok 1435 Set VL 7664
7331 10:07:00.554878 # ok 1436 # SKIP Disabled ZA for VL 7664
7332 10:07:00.555014 # ok 1437 # SKIP Get and set data for VL 7664
7333 10:07:00.555129 # ok 1438 Set VL 7680
7334 10:07:00.555242 # ok 1439 # SKIP Disabled ZA for VL 7680
7335 10:07:00.555354 # ok 1440 # SKIP Get and set data for VL 7680
7336 10:07:00.555466 # ok 1441 Set VL 7696
7337 10:07:00.555577 # ok 1442 # SKIP Disabled ZA for VL 7696
7338 10:07:00.555689 # ok 1443 # SKIP Get and set data for VL 7696
7339 10:07:00.555801 # ok 1444 Set VL 7712
7340 10:07:00.555912 # ok 1445 # SKIP Disabled ZA for VL 7712
7341 10:07:00.556023 # ok 1446 # SKIP Get and set data for VL 7712
7342 10:07:00.556135 # ok 1447 Set VL 7728
7343 10:07:00.556246 # ok 1448 # SKIP Disabled ZA for VL 7728
7344 10:07:00.556357 # ok 1449 # SKIP Get and set data for VL 7728
7345 10:07:00.556468 # ok 1450 Set VL 7744
7346 10:07:00.566560 # ok 1451 # SKIP Disabled ZA for VL 7744
7347 10:07:00.566744 # ok 1452 # SKIP Get and set data for VL 7744
7348 10:07:00.567103 # ok 1453 Set VL 7760
7349 10:07:00.567232 # ok 1454 # SKIP Disabled ZA for VL 7760
7350 10:07:00.567351 # ok 1455 # SKIP Get and set data for VL 7760
7351 10:07:00.568134 # ok 1456 Set VL 7776
7352 10:07:00.568238 # ok 1457 # SKIP Disabled ZA for VL 7776
7353 10:07:00.568334 # ok 1458 # SKIP Get and set data for VL 7776
7354 10:07:00.568413 # ok 1459 Set VL 7792
7355 10:07:00.568490 # ok 1460 # SKIP Disabled ZA for VL 7792
7356 10:07:00.568578 # ok 1461 # SKIP Get and set data for VL 7792
7357 10:07:00.568656 # ok 1462 Set VL 7808
7358 10:07:00.568888 # ok 1463 # SKIP Disabled ZA for VL 7808
7359 10:07:00.568996 # ok 1464 # SKIP Get and set data for VL 7808
7360 10:07:00.569077 # ok 1465 Set VL 7824
7361 10:07:00.569153 # ok 1466 # SKIP Disabled ZA for VL 7824
7362 10:07:00.569228 # ok 1467 # SKIP Get and set data for VL 7824
7363 10:07:00.569318 # ok 1468 Set VL 7840
7364 10:07:00.569395 # ok 1469 # SKIP Disabled ZA for VL 7840
7365 10:07:00.569471 # ok 1470 # SKIP Get and set data for VL 7840
7366 10:07:00.569546 # ok 1471 Set VL 7856
7367 10:07:00.569621 # ok 1472 # SKIP Disabled ZA for VL 7856
7368 10:07:00.569704 # ok 1473 # SKIP Get and set data for VL 7856
7369 10:07:00.569795 # ok 1474 Set VL 7872
7370 10:07:00.569872 # ok 1475 # SKIP Disabled ZA for VL 7872
7371 10:07:00.569951 # ok 1476 # SKIP Get and set data for VL 7872
7372 10:07:00.570028 # ok 1477 Set VL 7888
7373 10:07:00.570105 # ok 1478 # SKIP Disabled ZA for VL 7888
7374 10:07:00.570196 # ok 1479 # SKIP Get and set data for VL 7888
7375 10:07:00.570275 # ok 1480 Set VL 7904
7376 10:07:00.570353 # ok 1481 # SKIP Disabled ZA for VL 7904
7377 10:07:00.570429 # ok 1482 # SKIP Get and set data for VL 7904
7378 10:07:00.570506 # ok 1483 Set VL 7920
7379 10:07:00.570596 # ok 1484 # SKIP Disabled ZA for VL 7920
7380 10:07:00.570686 # ok 1485 # SKIP Get and set data for VL 7920
7381 10:07:00.570765 # ok 1486 Set VL 7936
7382 10:07:00.570842 # ok 1487 # SKIP Disabled ZA for VL 7936
7383 10:07:00.570919 # ok 1488 # SKIP Get and set data for VL 7936
7384 10:07:00.571008 # ok 1489 Set VL 7952
7385 10:07:00.579910 # ok 1490 # SKIP Disabled ZA for VL 7952
7386 10:07:00.580332 # ok 1491 # SKIP Get and set data for VL 7952
7387 10:07:00.580519 # ok 1492 Set VL 7968
7388 10:07:00.580676 # ok 1493 # SKIP Disabled ZA for VL 7968
7389 10:07:00.580833 # ok 1494 # SKIP Get and set data for VL 7968
7390 10:07:00.580966 # ok 1495 Set VL 7984
7391 10:07:00.581107 # ok 1496 # SKIP Disabled ZA for VL 7984
7392 10:07:00.581225 # ok 1497 # SKIP Get and set data for VL 7984
7393 10:07:00.581340 # ok 1498 Set VL 8000
7394 10:07:00.581451 # ok 1499 # SKIP Disabled ZA for VL 8000
7395 10:07:00.581563 # ok 1500 # SKIP Get and set data for VL 8000
7396 10:07:00.581709 # ok 1501 Set VL 8016
7397 10:07:00.581911 # ok 1502 # SKIP Disabled ZA for VL 8016
7398 10:07:00.582130 # ok 1503 # SKIP Get and set data for VL 8016
7399 10:07:00.582308 # ok 1504 Set VL 8032
7400 10:07:00.582481 # ok 1505 # SKIP Disabled ZA for VL 8032
7401 10:07:00.582679 # ok 1506 # SKIP Get and set data for VL 8032
7402 10:07:00.582850 # ok 1507 Set VL 8048
7403 10:07:00.583029 # ok 1508 # SKIP Disabled ZA for VL 8048
7404 10:07:00.583166 # ok 1509 # SKIP Get and set data for VL 8048
7405 10:07:00.583309 # ok 1510 Set VL 8064
7406 10:07:00.583450 # ok 1511 # SKIP Disabled ZA for VL 8064
7407 10:07:00.583591 # ok 1512 # SKIP Get and set data for VL 8064
7408 10:07:00.583730 # ok 1513 Set VL 8080
7409 10:07:00.583873 # ok 1514 # SKIP Disabled ZA for VL 8080
7410 10:07:00.592362 # ok 1515 # SKIP Get and set data for VL 8080
7411 10:07:00.592949 # ok 1516 Set VL 8096
7412 10:07:00.593050 # ok 1517 # SKIP Disabled ZA for VL 8096
7413 10:07:00.593133 # ok 1518 # SKIP Get and set data for VL 8096
7414 10:07:00.593211 # ok 1519 Set VL 8112
7415 10:07:00.593286 # ok 1520 # SKIP Disabled ZA for VL 8112
7416 10:07:00.593362 # ok 1521 # SKIP Get and set data for VL 8112
7417 10:07:00.593438 # ok 1522 Set VL 8128
7418 10:07:00.593528 # ok 1523 # SKIP Disabled ZA for VL 8128
7419 10:07:00.593607 # ok 1524 # SKIP Get and set data for VL 8128
7420 10:07:00.593686 # ok 1525 Set VL 8144
7421 10:07:00.593754 # ok 1526 # SKIP Disabled ZA for VL 8144
7422 10:07:00.593818 # ok 1527 # SKIP Get and set data for VL 8144
7423 10:07:00.593888 # ok 1528 Set VL 8160
7424 10:07:00.593968 # ok 1529 # SKIP Disabled ZA for VL 8160
7425 10:07:00.594059 # ok 1530 # SKIP Get and set data for VL 8160
7426 10:07:00.594137 # ok 1531 Set VL 8176
7427 10:07:00.594213 # ok 1532 # SKIP Disabled ZA for VL 8176
7428 10:07:00.594289 # ok 1533 # SKIP Get and set data for VL 8176
7429 10:07:00.594364 # ok 1534 Set VL 8192
7430 10:07:00.594439 # ok 1535 # SKIP Disabled ZA for VL 8192
7431 10:07:00.594528 # ok 1536 # SKIP Get and set data for VL 8192
7432 10:07:00.594605 # # Totals: pass:522 fail:0 xfail:0 xpass:0 skip:1014 error:0
7433 10:07:00.594682 ok 34 selftests: arm64: za-ptrace
7434 10:07:00.594758 # selftests: arm64: check_buffer_fill
7435 10:07:01.041317 # 1..20
7436 10:07:01.041674 # ok 1 Check buffer correctness by byte with sync err mode and mmap memory
7437 10:07:01.041885 # ok 2 Check buffer correctness by byte with async err mode and mmap memory
7438 10:07:01.042077 # ok 3 Check buffer correctness by byte with sync err mode and mmap/mprotect memory
7439 10:07:01.042522 # ok 4 Check buffer correctness by byte with async err mode and mmap/mprotect memory
7440 10:07:01.042725 # not ok 5 Check buffer write underflow by byte with sync mode and mmap memory
7441 10:07:01.042900 # not ok 6 Check buffer write underflow by byte with async mode and mmap memory
7442 10:07:01.043031 # ok 7 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7443 10:07:01.043147 # ok 8 Check buffer write underflow by byte with sync mode and mmap memory
7444 10:07:01.043261 # ok 9 Check buffer write underflow by byte with async mode and mmap memory
7445 10:07:01.043401 # ok 10 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7446 10:07:01.043521 # not ok 11 Check buffer write overflow by byte with sync mode and mmap memory
7447 10:07:01.046245 # not ok 12 Check buffer write overflow by byte with async mode and mmap memory
7448 10:07:01.046755 # ok 13 Check buffer write overflow by byte with tag fault ignore mode and mmap memory
7449 10:07:01.054274 # not ok 14 Check buffer write correctness by block with sync mode and mmap memory
7450 10:07:01.054711 # not ok 15 Check buffer write correctness by block with async mode and mmap memory
7451 10:07:01.054878 # ok 16 Check buffer write correctness by block with tag fault ignore and mmap memory
7452 10:07:01.055006 # ok 17 Check initial tags with private mapping, sync error mode and mmap memory
7453 10:07:01.073867 # ok 18 Check initial tags with private mapping, sync error mode and mmap/mprotect memory
7454 10:07:01.074079 # ok 19 Check initial tags with shared mapping, sync error mode and mmap memory
7455 10:07:01.074265 # ok 20 Check initial tags with shared mapping, sync error mode and mmap/mprotect memory
7456 10:07:01.074391 # # Totals: pass:14 fail:6 xfail:0 xpass:0 skip:0 error:0
7457 10:07:01.080649 not ok 35 selftests: arm64: check_buffer_fill # exit=1
7458 10:07:01.233431 # selftests: arm64: check_child_memory
7459 10:07:01.716666 # 1..12
7460 10:07:01.717010 # not ok 1 Check child anonymous memory with private mapping, precise mode and mmap memory
7461 10:07:01.717426 # not ok 2 Check child anonymous memory with shared mapping, precise mode and mmap memory
7462 10:07:01.717592 # not ok 3 Check child anonymous memory with private mapping, imprecise mode and mmap memory
7463 10:07:01.717762 # not ok 4 Check child anonymous memory with shared mapping, imprecise mode and mmap memory
7464 10:07:01.717903 # not ok 5 Check child anonymous memory with private mapping, precise mode and mmap/mprotect memory
7465 10:07:01.718091 # not ok 6 Check child anonymous memory with shared mapping, precise mode and mmap/mprotect memory
7466 10:07:01.718249 # not ok 7 Check child file memory with private mapping, precise mode and mmap memory
7467 10:07:01.718410 # not ok 8 Check child file memory with shared mapping, precise mode and mmap memory
7468 10:07:01.718565 # not ok 9 Check child file memory with private mapping, imprecise mode and mmap memory
7469 10:07:01.718756 # not ok 10 Check child file memory with shared mapping, imprecise mode and mmap memory
7470 10:07:01.718905 # not ok 11 Check child file memory with private mapping, precise mode and mmap/mprotect memory
7471 10:07:01.734333 # not ok 12 Check child file memory with shared mapping, precise mode and mmap/mprotect memory
7472 10:07:01.734713 # # Totals: pass:0 fail:12 xfail:0 xpass:0 skip:0 error:0
7473 10:07:01.754335 not ok 36 selftests: arm64: check_child_memory # exit=1
7474 10:07:01.905247 # selftests: arm64: check_gcr_el1_cswitch
7475 10:07:47.096731 <47>[ 101.768954] systemd-journald[109]: Sent WATCHDOG=1 notification.
7476 10:07:47.736021 <47>[ 102.409604] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3308 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
7477 10:07:47.736617 <47>[ 102.410181] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
7478 10:07:47.736786 <47>[ 102.410591] systemd-journald[109]: Rotating...
7479 10:07:47.772352 <47>[ 102.446183] systemd-journald[109]: Reserving 333 entries in field hash table.
7480 10:07:47.815860 <47>[ 102.489657] systemd-journald[109]: Reserving 4408 entries in data hash table.
7481 10:07:47.832557 <47>[ 102.506390] systemd-journald[109]: Vacuuming...
7482 10:07:47.863410 <47>[ 102.536988] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
7483 10:07:48.359718 # 1..1
7484 10:07:48.359940 # 1..1
7485 10:07:48.360061 # 1..1
7486 10:07:48.360168 # 1..1
7487 10:07:48.360270 # 1..1
7488 10:07:48.360474 # 1..1
7489 10:07:48.360661 # 1..1
7490 10:07:48.361068 # 1..1
7491 10:07:48.361211 # 1..1
7492 10:07:48.361334 # 1..1
7493 10:07:48.361453 # 1..1
7494 10:07:48.361573 # 1..1
7495 10:07:48.361705 # 1..1
7496 10:07:48.361824 # 1..1
7497 10:07:48.361941 # 1..1
7498 10:07:48.362058 # 1..1
7499 10:07:48.362175 # 1..1
7500 10:07:48.362293 # 1..1
7501 10:07:48.362410 # 1..1
7502 10:07:48.362528 # 1..1
7503 10:07:48.362643 # 1..1
7504 10:07:48.362761 # 1..1
7505 10:07:48.362879 # 1..1
7506 10:07:48.362995 # 1..1
7507 10:07:48.363114 # 1..1
7508 10:07:48.363231 # 1..1
7509 10:07:48.363356 # 1..1
7510 10:07:48.363476 # 1..1
7511 10:07:48.363593 # 1..1
7512 10:07:48.363705 # 1..1
7513 10:07:48.363820 # 1..1
7514 10:07:48.363930 # 1..1
7515 10:07:48.364045 # 1..1
7516 10:07:48.364156 # 1..1
7517 10:07:48.364266 # 1..1
7518 10:07:48.364383 # 1..1
7519 10:07:48.364495 # 1..1
7520 10:07:48.364605 # 1..1
7521 10:07:48.364714 # 1..1
7522 10:07:48.364823 # 1..1
7523 10:07:48.364933 # 1..1
7524 10:07:48.365048 # 1..1
7525 10:07:48.365160 # 1..1
7526 10:07:48.365271 # 1..1
7527 10:07:48.365381 # 1..1
7528 10:07:48.365491 # 1..1
7529 10:07:48.365600 # 1..1
7530 10:07:48.365722 # 1..1
7531 10:07:48.365832 # 1..1
7532 10:07:48.365943 # 1..1
7533 10:07:48.366053 # 1..1
7534 10:07:48.366162 # 1..1
7535 10:07:48.366271 # 1..1
7536 10:07:48.366391 # 1..1
7537 10:07:48.366503 # 1..1
7538 10:07:48.366612 # 1..1
7539 10:07:48.366723 # 1..1
7540 10:07:48.366832 # 1..1
7541 10:07:48.407842 # 1..1
7542 10:07:48.408039 # 1..1
7543 10:07:48.408197 # 1..1
7544 10:07:48.408356 # 1..1
7545 10:07:48.408514 # 1..1
7546 10:07:48.408860 # 1..1
7547 10:07:48.409035 # 1..1
7548 10:07:48.409161 # 1..1
7549 10:07:48.409275 # 1..1
7550 10:07:48.409386 # 1..1
7551 10:07:48.409496 # 1..1
7552 10:07:48.409606 # 1..1
7553 10:07:48.409754 # 1..1
7554 10:07:48.409865 # 1..1
7555 10:07:48.409973 # 1..1
7556 10:07:48.410079 # 1..1
7557 10:07:48.410187 # 1..1
7558 10:07:48.410294 # 1..1
7559 10:07:48.410402 # 1..1
7560 10:07:48.410509 # 1..1
7561 10:07:48.410617 # 1..1
7562 10:07:48.410723 # 1..1
7563 10:07:48.410831 # 1..1
7564 10:07:48.410938 # 1..1
7565 10:07:48.411046 # 1..1
7566 10:07:48.411153 # 1..1
7567 10:07:48.411260 # 1..1
7568 10:07:48.411367 # 1..1
7569 10:07:48.411474 # 1..1
7570 10:07:48.411581 # 1..1
7571 10:07:48.411687 # 1..1
7572 10:07:48.411793 # 1..1
7573 10:07:48.411900 # 1..1
7574 10:07:48.412007 # 1..1
7575 10:07:48.412113 # 1..1
7576 10:07:48.412221 # 1..1
7577 10:07:48.412328 # 1..1
7578 10:07:48.412434 # 1..1
7579 10:07:48.412541 # 1..1
7580 10:07:48.412648 # 1..1
7581 10:07:48.412756 # 1..1
7582 10:07:48.412864 # 1..1
7583 10:07:48.412996 # 1..1
7584 10:07:48.413109 # 1..1
7585 10:07:48.413219 # 1..1
7586 10:07:48.413327 # 1..1
7587 10:07:48.438978 # 1..1
7588 10:07:48.439159 # 1..1
7589 10:07:48.439357 # 1..1
7590 10:07:48.439781 # 1..1
7591 10:07:48.439976 # 1..1
7592 10:07:48.440128 # 1..1
7593 10:07:48.440290 # 1..1
7594 10:07:48.440432 # 1..1
7595 10:07:48.440564 # 1..1
7596 10:07:48.440707 # 1..1
7597 10:07:48.440899 # 1..1
7598 10:07:48.441050 # 1..1
7599 10:07:48.441176 # 1..1
7600 10:07:48.441315 # 1..1
7601 10:07:48.441455 # 1..1
7602 10:07:48.441600 # 1..1
7603 10:07:48.441777 # 1..1
7604 10:07:48.441916 # 1..1
7605 10:07:48.442075 # 1..1
7606 10:07:48.442222 # 1..1
7607 10:07:48.442364 # 1..1
7608 10:07:48.442525 # 1..1
7609 10:07:48.442662 # 1..1
7610 10:07:48.442821 # 1..1
7611 10:07:48.442967 # 1..1
7612 10:07:48.443110 # 1..1
7613 10:07:48.443271 # 1..1
7614 10:07:48.443407 # 1..1
7615 10:07:48.443566 # 1..1
7616 10:07:48.443711 # 1..1
7617 10:07:48.443854 # 1..1
7618 10:07:48.444014 # 1..1
7619 10:07:48.444151 # 1..1
7620 10:07:48.444311 # 1..1
7621 10:07:48.444455 # 1..1
7622 10:07:48.444601 # 1..1
7623 10:07:48.444756 # 1..1
7624 10:07:48.444934 # 1..1
7625 10:07:48.445102 # 1..1
7626 10:07:48.445239 # 1..1
7627 10:07:48.445399 # 1..1
7628 10:07:48.445544 # 1..1
7629 10:07:48.445699 # 1..1
7630 10:07:48.445854 # 1..1
7631 10:07:48.445992 # 1..1
7632 10:07:48.446150 # 1..1
7633 10:07:48.446289 # 1..1
7634 10:07:48.446441 # 1..1
7635 10:07:48.446588 # 1..1
7636 10:07:48.446728 # 1..1
7637 10:07:48.446865 # 1..1
7638 10:07:48.446977 # 1..1
7639 10:07:48.447089 # 1..1
7640 10:07:48.447208 # 1..1
7641 10:07:48.447323 # 1..1
7642 10:07:48.447466 # 1..1
7643 10:07:48.447604 # 1..1
7644 10:07:48.447753 # 1..1
7645 10:07:48.447885 # 1..1
7646 10:07:48.448024 # 1..1
7647 10:07:48.448164 # 1..1
7648 10:07:48.448312 # 1..1
7649 10:07:48.448436 # 1..1
7650 10:07:48.448550 # 1..1
7651 10:07:48.448670 # 1..1
7652 10:07:48.448786 # 1..1
7653 10:07:48.448936 # 1..1
7654 10:07:48.449071 # 1..1
7655 10:07:48.449229 # 1..1
7656 10:07:48.449348 # 1..1
7657 10:07:48.449499 # 1..1
7658 10:07:48.449634 # 1..1
7659 10:07:48.449806 # 1..1
7660 10:07:48.449950 # 1..1
7661 10:07:48.450097 # 1..1
7662 10:07:48.450259 # 1..1
7663 10:07:48.450395 # 1..1
7664 10:07:48.450553 # 1..1
7665 10:07:48.450704 # 1..1
7666 10:07:48.450843 # 1..1
7667 10:07:48.451007 # 1..1
7668 10:07:48.451147 # 1..1
7669 10:07:48.451300 # 1..1
7670 10:07:48.451455 # 1..1
7671 10:07:48.451593 # 1..1
7672 10:07:48.451756 # 1..1
7673 10:07:48.451902 # 1..1
7674 10:07:48.452053 # 1..1
7675 10:07:48.452233 # 1..1
7676 10:07:48.452425 # 1..1
7677 10:07:48.452575 # 1..1
7678 10:07:48.452738 # 1..1
7679 10:07:48.452881 # 1..1
7680 10:07:48.453030 # 1..1
7681 10:07:48.453189 # 1..1
7682 10:07:48.453326 # 1..1
7683 10:07:48.453484 # 1..1
7684 10:07:48.453627 # 1..1
7685 10:07:48.453824 # 1..1
7686 10:07:48.453985 # 1..1
7687 10:07:48.454131 # 1..1
7688 10:07:48.454294 # 1..1
7689 10:07:48.454432 # 1..1
7690 10:07:48.454593 # 1..1
7691 10:07:48.454739 # 1..1
7692 10:07:48.454886 # 1..1
7693 10:07:48.455044 # 1..1
7694 10:07:48.455181 # 1..1
7695 10:07:48.455341 # 1..1
7696 10:07:48.455484 # 1..1
7697 10:07:48.455632 # 1..1
7698 10:07:48.455788 # 1..1
7699 10:07:48.455925 # 1..1
7700 10:07:48.456087 # 1..1
7701 10:07:48.456228 # 1..1
7702 10:07:48.456376 # 1..1
7703 10:07:48.456532 # 1..1
7704 10:07:48.456669 # 1..1
7705 10:07:48.456830 # 1..1
7706 10:07:48.456971 # 1..1
7707 10:07:48.457122 # 1..1
7708 10:07:48.457275 # 1..1
7709 10:07:48.457413 # 1..1
7710 10:07:48.457575 # 1..1
7711 10:07:48.457725 # 1..1
7712 10:07:48.457879 # 1..1
7713 10:07:48.458031 # 1..1
7714 10:07:48.458170 # 1..1
7715 10:07:48.458332 # 1..1
7716 10:07:48.458470 # 1..1
7717 10:07:48.458625 # 1..1
7718 10:07:48.458774 # 1..1
7719 10:07:48.458913 # 1..1
7720 10:07:48.459074 # 1..1
7721 10:07:48.459211 # 1..1
7722 10:07:48.459366 # 1..1
7723 10:07:48.459516 # 1..1
7724 10:07:48.459656 # 1..1
7725 10:07:48.459817 # 1..1
7726 10:07:48.471350 # 1..1
7727 10:07:48.471501 # 1..1
7728 10:07:48.471689 # 1..1
7729 10:07:48.471865 # 1..1
7730 10:07:48.472031 # 1..1
7731 10:07:48.472388 # 1..1
7732 10:07:48.472519 # 1..1
7733 10:07:48.472658 # 1..1
7734 10:07:48.472796 # 1..1
7735 10:07:48.472934 # 1..1
7736 10:07:48.473072 # 1..1
7737 10:07:48.473207 # 1..1
7738 10:07:48.473342 # 1..1
7739 10:07:48.473477 # 1..1
7740 10:07:48.473612 # 1..1
7741 10:07:48.473761 # 1..1
7742 10:07:48.473898 # 1..1
7743 10:07:48.474032 # 1..1
7744 10:07:48.474167 # 1..1
7745 10:07:48.474303 # 1..1
7746 10:07:48.474440 # 1..1
7747 10:07:48.474575 # 1..1
7748 10:07:48.474709 # 1..1
7749 10:07:48.474844 # 1..1
7750 10:07:48.474980 # 1..1
7751 10:07:48.475115 # 1..1
7752 10:07:48.475249 # 1..1
7753 10:07:48.475385 # 1..1
7754 10:07:48.475521 # 1..1
7755 10:07:48.475656 # 1..1
7756 10:07:48.475792 # 1..1
7757 10:07:48.475927 # 1..1
7758 10:07:48.476062 # 1..1
7759 10:07:48.476197 # 1..1
7760 10:07:48.476331 # 1..1
7761 10:07:48.476469 # 1..1
7762 10:07:48.476605 # 1..1
7763 10:07:48.476742 # 1..1
7764 10:07:48.476912 # 1..1
7765 10:07:48.477044 # 1..1
7766 10:07:48.477181 # 1..1
7767 10:07:48.477319 # 1..1
7768 10:07:48.477453 # 1..1
7769 10:07:48.477590 # 1..1
7770 10:07:48.477737 # 1..1
7771 10:07:48.477876 # 1..1
7772 10:07:48.478013 # 1..1
7773 10:07:48.478149 # 1..1
7774 10:07:48.478286 # 1..1
7775 10:07:48.478422 # 1..1
7776 10:07:48.478559 # 1..1
7777 10:07:48.478695 # 1..1
7778 10:07:48.478830 # 1..1
7779 10:07:48.478966 # 1..1
7780 10:07:48.479102 # 1..1
7781 10:07:48.479237 # 1..1
7782 10:07:48.479373 # 1..1
7783 10:07:48.479508 # 1..1
7784 10:07:48.479644 # 1..1
7785 10:07:48.479778 # 1..1
7786 10:07:48.491298 # 1..1
7787 10:07:48.491506 # 1..1
7788 10:07:48.491664 # 1..1
7789 10:07:48.491854 # 1..1
7790 10:07:48.492049 # 1..1
7791 10:07:48.492441 # 1..1
7792 10:07:48.492611 # 1..1
7793 10:07:48.492773 # 1..1
7794 10:07:48.492924 # 1..1
7795 10:07:48.493063 # 1..1
7796 10:07:48.493180 # 1..1
7797 10:07:48.493291 # 1..1
7798 10:07:48.493402 # 1..1
7799 10:07:48.493510 # 1..1
7800 10:07:48.493620 # 1..1
7801 10:07:48.493745 # 1..1
7802 10:07:48.493852 # 1..1
7803 10:07:48.493959 # 1..1
7804 10:07:48.494066 # 1..1
7805 10:07:48.494172 # 1..1
7806 10:07:48.494279 # 1..1
7807 10:07:48.494386 # 1..1
7808 10:07:48.494492 # 1..1
7809 10:07:48.494598 # 1..1
7810 10:07:48.494705 # 1..1
7811 10:07:48.494812 # 1..1
7812 10:07:48.494918 # 1..1
7813 10:07:48.495025 # 1..1
7814 10:07:48.495132 # 1..1
7815 10:07:48.495238 # 1..1
7816 10:07:48.495345 # 1..1
7817 10:07:48.495453 # 1..1
7818 10:07:48.495559 # 1..1
7819 10:07:48.495666 # 1..1
7820 10:07:48.495772 # 1..1
7821 10:07:48.495879 # 1..1
7822 10:07:48.495985 # 1..1
7823 10:07:48.496091 # 1..1
7824 10:07:48.496197 # 1..1
7825 10:07:48.496303 # 1..1
7826 10:07:48.496410 # 1..1
7827 10:07:48.496517 # 1..1
7828 10:07:48.496622 # 1..1
7829 10:07:48.496729 # 1..1
7830 10:07:48.496835 # 1..1
7831 10:07:48.496942 # 1..1
7832 10:07:48.497049 # 1..1
7833 10:07:48.497156 # 1..1
7834 10:07:48.497263 # 1..1
7835 10:07:48.497371 # 1..1
7836 10:07:48.497478 # 1..1
7837 10:07:48.497584 # 1..1
7838 10:07:48.497697 # 1..1
7839 10:07:48.497832 # 1..1
7840 10:07:48.497946 # 1..1
7841 10:07:48.498054 # 1..1
7842 10:07:48.498162 # 1..1
7843 10:07:48.498270 # 1..1
7844 10:07:48.498377 # 1..1
7845 10:07:48.498483 # 1..1
7846 10:07:48.498589 # 1..1
7847 10:07:48.498696 # 1..1
7848 10:07:48.498801 # 1..1
7849 10:07:48.498908 # 1..1
7850 10:07:48.499014 # 1..1
7851 10:07:48.499120 # 1..1
7852 10:07:48.499225 # 1..1
7853 10:07:48.499332 # 1..1
7854 10:07:48.499437 # 1..1
7855 10:07:48.499544 # 1..1
7856 10:07:48.499649 # 1..1
7857 10:07:48.499756 # 1..1
7858 10:07:48.499862 # 1..1
7859 10:07:48.499969 # 1..1
7860 10:07:48.510569 # 1..1
7861 10:07:48.510750 # 1..1
7862 10:07:48.510911 # 1..1
7863 10:07:48.511064 # 1..1
7864 10:07:48.511223 # 1..1
7865 10:07:48.511402 # 1..1
7866 10:07:48.511555 # 1..1
7867 10:07:48.512004 # 1..1
7868 10:07:48.512192 # 1..1
7869 10:07:48.512375 # 1..1
7870 10:07:48.512544 # 1..1
7871 10:07:48.512698 # 1..1
7872 10:07:48.512851 # 1..1
7873 10:07:48.512995 # 1..1
7874 10:07:48.513109 # 1..1
7875 10:07:48.513216 # 1..1
7876 10:07:48.513324 # 1..1
7877 10:07:48.513432 # 1..1
7878 10:07:48.513540 # 1..1
7879 10:07:48.513657 # 1..1
7880 10:07:48.513853 # 1..1
7881 10:07:48.514031 # 1..1
7882 10:07:48.514201 # 1..1
7883 10:07:48.514339 # 1..1
7884 10:07:48.514477 # 1..1
7885 10:07:48.514610 # 1..1
7886 10:07:48.514746 # 1..1
7887 10:07:48.514880 # 1..1
7888 10:07:48.515015 # 1..1
7889 10:07:48.515152 # 1..1
7890 10:07:48.515287 # 1..1
7891 10:07:48.515423 # 1..1
7892 10:07:48.515557 # 1..1
7893 10:07:48.515692 # 1..1
7894 10:07:48.515827 # 1..1
7895 10:07:48.515960 # 1..1
7896 10:07:48.516095 # 1..1
7897 10:07:48.516229 # 1..1
7898 10:07:48.516364 # 1..1
7899 10:07:48.516498 # 1..1
7900 10:07:48.516632 # 1..1
7901 10:07:48.516767 # 1..1
7902 10:07:48.516901 # 1..1
7903 10:07:48.517035 # 1..1
7904 10:07:48.517169 # 1..1
7905 10:07:48.517303 # 1..1
7906 10:07:48.517437 # 1..1
7907 10:07:48.517572 # 1..1
7908 10:07:48.517717 # 1..1
7909 10:07:48.517855 # 1..1
7910 10:07:48.517991 # 1..1
7911 10:07:48.518126 # 1..1
7912 10:07:48.518262 # 1..1
7913 10:07:48.518398 # 1..1
7914 10:07:48.518560 # 1..1
7915 10:07:48.518733 # 1..1
7916 10:07:48.518880 # 1..1
7917 10:07:48.519015 # 1..1
7918 10:07:48.519150 # 1..1
7919 10:07:48.519285 # 1..1
7920 10:07:48.519421 # 1..1
7921 10:07:48.519555 # 1..1
7922 10:07:48.519689 # 1..1
7923 10:07:48.519824 # 1..1
7924 10:07:48.519997 # 1..1
7925 10:07:48.520125 # 1..1
7926 10:07:48.520260 # 1..1
7927 10:07:48.520395 # 1..1
7928 10:07:48.520529 # 1..1
7929 10:07:48.520663 # 1..1
7930 10:07:48.520798 # 1..1
7931 10:07:48.520940 # 1..1
7932 10:07:48.521075 # 1..1
7933 10:07:48.521210 # 1..1
7934 10:07:48.521344 # 1..1
7935 10:07:48.521478 # 1..1
7936 10:07:48.521618 # 1..1
7937 10:07:48.521763 # 1..1
7938 10:07:48.521898 # 1..1
7939 10:07:48.522033 # 1..1
7940 10:07:48.522166 # 1..1
7941 10:07:48.522300 # 1..1
7942 10:07:48.522434 # 1..1
7943 10:07:48.522570 # 1..1
7944 10:07:48.522703 # 1..1
7945 10:07:48.522837 # 1..1
7946 10:07:48.522971 # 1..1
7947 10:07:48.523104 # 1..1
7948 10:07:48.523239 # 1..1
7949 10:07:48.523372 # 1..1
7950 10:07:48.523506 # 1..1
7951 10:07:48.523640 # 1..1
7952 10:07:48.523773 # 1..1
7953 10:07:48.523907 # 1..1
7954 10:07:48.524041 # 1..1
7955 10:07:48.524176 # 1..1
7956 10:07:48.524310 # 1..1
7957 10:07:48.524444 # 1..1
7958 10:07:48.524577 # 1..1
7959 10:07:48.524716 # 1..1
7960 10:07:48.524851 # 1..1
7961 10:07:48.524984 # 1..1
7962 10:07:48.525118 # 1..1
7963 10:07:48.525252 # 1..1
7964 10:07:48.525386 # 1..1
7965 10:07:48.525520 # 1..1
7966 10:07:48.525661 # 1..1
7967 10:07:48.539478 # 1..1
7968 10:07:48.539671 # 1..1
7969 10:07:48.539829 # 1..1
7970 10:07:48.539982 # 1..1
7971 10:07:48.540379 # 1..1
7972 10:07:48.540549 # 1..1
7973 10:07:48.540668 # 1..1
7974 10:07:48.540780 # 1..1
7975 10:07:48.540891 # 1..1
7976 10:07:48.541002 # 1..1
7977 10:07:48.541112 # 1..1
7978 10:07:48.541222 # 1..1
7979 10:07:48.541332 # 1..1
7980 10:07:48.541443 # 1..1
7981 10:07:48.541553 # 1..1
7982 10:07:48.541675 # 1..1
7983 10:07:48.541787 # 1..1
7984 10:07:48.541897 # 1..1
7985 10:07:48.542006 # 1..1
7986 10:07:48.542116 # 1..1
7987 10:07:48.542226 # 1..1
7988 10:07:48.542336 # 1..1
7989 10:07:48.542447 # 1..1
7990 10:07:48.542556 # 1..1
7991 10:07:48.542664 # 1..1
7992 10:07:48.542773 # 1..1
7993 10:07:48.542884 # 1..1
7994 10:07:48.542993 # 1..1
7995 10:07:48.543102 # 1..1
7996 10:07:48.543210 # 1..1
7997 10:07:48.543319 # 1..1
7998 10:07:48.543430 # 1..1
7999 10:07:48.543539 # 1..1
8000 10:07:48.543649 # 1..1
8001 10:07:48.543758 # 1..1
8002 10:07:48.543868 # 1..1
8003 10:07:48.543977 # 1..1
8004 10:07:48.544087 # 1..1
8005 10:07:48.544221 # 1..1
8006 10:07:48.544337 # 1..1
8007 10:07:48.544448 # 1..1
8008 10:07:48.544557 # 1..1
8009 10:07:48.544666 # 1..1
8010 10:07:48.544776 # 1..1
8011 10:07:48.544886 # 1..1
8012 10:07:48.559543 #
8013 10:07:48.559902 not ok 37 selftests: arm64: check_gcr_el1_cswitch # TIMEOUT 45 seconds
8014 10:07:48.951879 # selftests: arm64: check_ksm_options
8015 10:07:49.494914 # 1..4
8016 10:07:49.495184 # # Invalid MTE synchronous exception caught!
8017 10:07:49.575587 not ok 38 selftests: arm64: check_ksm_options # exit=1
8018 10:07:50.039283 # selftests: arm64: check_mmap_options
8019 10:07:51.263297 # 1..22
8020 10:07:51.263814 # ok 1 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check off
8021 10:07:51.263972 # ok 2 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check off
8022 10:07:51.264098 # ok 3 Check anonymous memory with private mapping, no error mode, mmap memory and tag check off
8023 10:07:51.264239 # ok 4 Check file memory with private mapping, no error mode, mmap/mprotect memory and tag check off
8024 10:07:51.264358 # not ok 5 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check on
8025 10:07:51.264683 # not ok 6 Check anonymous memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
8026 10:07:51.264810 # not ok 7 Check anonymous memory with shared mapping, sync error mode, mmap memory and tag check on
8027 10:07:51.264952 # not ok 8 Check anonymous memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
8028 10:07:51.265070 # not ok 9 Check anonymous memory with private mapping, async error mode, mmap memory and tag check on
8029 10:07:51.274869 # not ok 10 Check anonymous memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8030 10:07:51.275325 # not ok 11 Check anonymous memory with shared mapping, async error mode, mmap memory and tag check on
8031 10:07:51.275452 # not ok 12 Check anonymous memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8032 10:07:51.275621 # not ok 13 Check file memory with private mapping, sync error mode, mmap memory and tag check on
8033 10:07:51.275813 # not ok 14 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
8034 10:07:51.275980 # not ok 15 Check file memory with shared mapping, sync error mode, mmap memory and tag check on
8035 10:07:51.276184 # not ok 16 Check file memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
8036 10:07:51.276366 # not ok 17 Check file memory with private mapping, async error mode, mmap memory and tag check on
8037 10:07:51.276549 # not ok 18 Check file memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8038 10:07:51.276729 # not ok 19 Check file memory with shared mapping, async error mode, mmap memory and tag check on
8039 10:07:51.276954 # not ok 20 Check file memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8040 10:07:51.311718 # not ok 21 Check clear PROT_MTE flags with private mapping, sync error mode and mmap memory
8041 10:07:51.312258 # not ok 22 Check clear PROT_MTE flags with private mapping and sync error mode and mmap/mprotect memory
8042 10:07:51.312413 # # Totals: pass:4 fail:18 xfail:0 xpass:0 skip:0 error:0
8043 10:07:51.360290 not ok 39 selftests: arm64: check_mmap_options # exit=1
8044 10:07:51.860192 # selftests: arm64: check_prctl
8045 10:07:52.367778 # TAP version 13
8046 10:07:52.368065 # 1..5
8047 10:07:52.368440 # ok 1 check_basic_read
8048 10:07:52.368575 # ok 2 NONE
8049 10:07:52.368695 # ok 3 SYNC
8050 10:07:52.368808 # ok 4 ASYNC
8051 10:07:52.368951 # ok 5 SYNC+ASYNC
8052 10:07:52.369092 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8053 10:07:52.412515 ok 40 selftests: arm64: check_prctl
8054 10:07:53.032378 # selftests: arm64: check_tags_inclusion
8055 10:07:53.534868 # 1..4
8056 10:07:53.535165 # # Unexpected fault recorded for 0x500ffff9ec94000-0x500ffff9ec94050 in mode 1
8057 10:07:53.535546 # not ok 1 Check an included tag value with sync mode
8058 10:07:53.535706 # # Unexpected fault recorded for 0x600ffff9ec94000-0x600ffff9ec94050 in mode 1
8059 10:07:53.535832 # not ok 2 Check different included tags value with sync mode
8060 10:07:53.535951 # ok 3 Check none included tags value with sync mode
8061 10:07:53.536067 # # Unexpected fault recorded for 0x300ffff9ec94000-0x300ffff9ec94050 in mode 1
8062 10:07:53.536186 # not ok 4 Check all included tags value with sync mode
8063 10:07:53.536324 # # Totals: pass:1 fail:3 xfail:0 xpass:0 skip:0 error:0
8064 10:07:53.607609 not ok 41 selftests: arm64: check_tags_inclusion # exit=1
8065 10:07:54.084788 # selftests: arm64: check_user_mem
8066 10:08:03.683662 # 1..64
8067 10:08:03.684046 # ok 1 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8068 10:08:03.685069 # ok 2 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8069 10:08:03.685279 # ok 3 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8070 10:08:03.685448 # ok 4 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8071 10:08:03.685618 # ok 5 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8072 10:08:03.685788 # ok 6 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8073 10:08:03.685928 # ok 7 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8074 10:08:03.686057 # ok 8 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8075 10:08:03.693684 # ok 9 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8076 10:08:03.694242 # ok 10 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8077 10:08:03.694485 # ok 11 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8078 10:08:03.694676 # ok 12 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8079 10:08:03.695106 # ok 13 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8080 10:08:03.695312 # ok 14 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8081 10:08:03.695488 # ok 15 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8082 10:08:03.695664 # ok 16 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8083 10:08:03.695835 # ok 17 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8084 10:08:03.696022 # ok 18 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8085 10:08:03.696273 # ok 19 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8086 10:08:03.696515 # ok 20 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8087 10:08:03.696747 # ok 21 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8088 10:08:03.696949 # ok 22 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8089 10:08:03.697154 # ok 23 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8090 10:08:03.697298 # ok 24 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8091 10:08:03.697450 # ok 25 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8092 10:08:03.697573 # ok 26 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8093 10:08:03.697747 # ok 27 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8094 10:08:03.697997 # ok 28 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8095 10:08:03.698252 # ok 29 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8096 10:08:03.698521 # ok 30 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8097 10:08:03.698731 # ok 31 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8098 10:08:03.699203 # ok 32 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8099 10:08:03.699417 # ok 33 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8100 10:08:03.699589 # ok 34 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8101 10:08:03.699812 # ok 35 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8102 10:08:03.699986 # ok 36 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8103 10:08:03.700156 # ok 37 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8104 10:08:03.700356 # ok 38 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8105 10:08:03.700556 # ok 39 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8106 10:08:03.700758 # ok 40 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8107 10:08:03.701016 # ok 41 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8108 10:08:03.701216 # ok 42 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8109 10:08:03.701377 # ok 43 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8110 10:08:03.706052 # ok 44 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8111 10:08:03.706482 # ok 45 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8112 10:08:03.706593 # ok 46 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8113 10:08:03.706707 # ok 47 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8114 10:08:03.706991 # ok 48 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8115 10:08:03.707104 # ok 49 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8116 10:08:03.707236 # ok 50 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8117 10:08:03.707545 # ok 51 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8118 10:08:05.390877 # ok 52 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8119 10:08:05.391472 # ok 53 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8120 10:08:05.391631 # ok 54 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8121 10:08:05.391759 # ok 55 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8122 10:08:05.391878 # ok 56 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8123 10:08:05.392213 # ok 57 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8124 10:08:05.392656 # ok 58 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8125 10:08:05.392827 # ok 59 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8126 10:08:05.392971 # ok 60 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8127 10:08:05.393127 # ok 61 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8128 10:08:05.393282 # ok 62 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8129 10:08:05.393399 # ok 63 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8130 10:08:05.393513 # ok 64 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8131 10:08:05.393635 # # Totals: pass:64 fail:0 xfail:0 xpass:0 skip:0 error:0
8132 10:08:05.420034 ok 42 selftests: arm64: check_user_mem
8133 10:08:05.628087 # selftests: arm64: btitest
8134 10:08:05.775008 # TAP version 13
8135 10:08:05.775237 # 1..18
8136 10:08:05.775333 # # HWCAP_PACA present
8137 10:08:05.775426 # # HWCAP2_BTI present
8138 10:08:05.775751 # # Test binary built for BTI
8139 10:08:05.775934 # # [SIGILL in nohint_func/call_using_br_x0, BTYPE=11 (expected)]
8140 10:08:05.776090 # ok 1 nohint_func/call_using_br_x0
8141 10:08:05.776251 # # [SIGILL in nohint_func/call_using_br_x16, BTYPE=01 (expected)]
8142 10:08:05.776443 # ok 2 nohint_func/call_using_br_x16
8143 10:08:05.776649 # # [SIGILL in nohint_func/call_using_blr, BTYPE=10 (expected)]
8144 10:08:05.776818 # ok 3 nohint_func/call_using_blr
8145 10:08:05.776978 # # [SIGILL in bti_none_func/call_using_br_x0, BTYPE=11 (expected)]
8146 10:08:05.777101 # ok 4 bti_none_func/call_using_br_x0
8147 10:08:05.777215 # # [SIGILL in bti_none_func/call_using_br_x16, BTYPE=01 (expected)]
8148 10:08:05.777328 # ok 5 bti_none_func/call_using_br_x16
8149 10:08:05.777466 # # [SIGILL in bti_none_func/call_using_blr, BTYPE=10 (expected)]
8150 10:08:05.777582 # ok 6 bti_none_func/call_using_blr
8151 10:08:05.777758 # # [SIGILL in bti_c_func/call_using_br_x0, BTYPE=11 (expected)]
8152 10:08:05.788460 # ok 7 bti_c_func/call_using_br_x0
8153 10:08:05.789011 # ok 8 bti_c_func/call_using_br_x16
8154 10:08:05.789169 # ok 9 bti_c_func/call_using_blr
8155 10:08:05.789291 # ok 10 bti_j_func/call_using_br_x0
8156 10:08:05.789410 # ok 11 bti_j_func/call_using_br_x16
8157 10:08:05.789525 # # [SIGILL in bti_j_func/call_using_blr, BTYPE=10 (expected)]
8158 10:08:05.789640 # ok 12 bti_j_func/call_using_blr
8159 10:08:05.800223 # ok 13 bti_jc_func/call_using_br_x0
8160 10:08:05.800803 # ok 14 bti_jc_func/call_using_br_x16
8161 10:08:05.801007 # ok 15 bti_jc_func/call_using_blr
8162 10:08:05.801147 # # [SIGILL in paciasp_func/call_using_br_x0, BTYPE=11 (expected)]
8163 10:08:05.801271 # ok 16 paciasp_func/call_using_br_x0
8164 10:08:05.801390 # ok 17 paciasp_func/call_using_br_x16
8165 10:08:05.801532 # ok 18 paciasp_func/call_using_blr
8166 10:08:05.801696 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8167 10:08:05.811391 ok 43 selftests: arm64: btitest
8168 10:08:05.956606 # selftests: arm64: nobtitest
8169 10:08:06.091788 # TAP version 13
8170 10:08:06.092135 # 1..18
8171 10:08:06.092624 # # HWCAP_PACA present
8172 10:08:06.092824 # # HWCAP2_BTI present
8173 10:08:06.093027 # # Test binary not built for BTI
8174 10:08:06.093199 # ok 1 nohint_func/call_using_br_x0
8175 10:08:06.093347 # ok 2 nohint_func/call_using_br_x16
8176 10:08:06.093488 # ok 3 nohint_func/call_using_blr
8177 10:08:06.093672 # ok 4 bti_none_func/call_using_br_x0
8178 10:08:06.093843 # ok 5 bti_none_func/call_using_br_x16
8179 10:08:06.093986 # ok 6 bti_none_func/call_using_blr
8180 10:08:06.094126 # ok 7 bti_c_func/call_using_br_x0
8181 10:08:06.094264 # ok 8 bti_c_func/call_using_br_x16
8182 10:08:06.094439 # ok 9 bti_c_func/call_using_blr
8183 10:08:06.094575 # ok 10 bti_j_func/call_using_br_x0
8184 10:08:06.094717 # ok 11 bti_j_func/call_using_br_x16
8185 10:08:06.098774 # ok 12 bti_j_func/call_using_blr
8186 10:08:06.099270 # ok 13 bti_jc_func/call_using_br_x0
8187 10:08:06.099420 # ok 14 bti_jc_func/call_using_br_x16
8188 10:08:06.099542 # ok 15 bti_jc_func/call_using_blr
8189 10:08:06.099660 # ok 16 paciasp_func/call_using_br_x0
8190 10:08:06.099775 # ok 17 paciasp_func/call_using_br_x16
8191 10:08:06.099888 # ok 18 paciasp_func/call_using_blr
8192 10:08:06.100030 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8193 10:08:06.119081 ok 44 selftests: arm64: nobtitest
8194 10:08:06.272047 # selftests: arm64: hwcap
8195 10:08:06.476446 # TAP version 13
8196 10:08:06.476751 # 1..28
8197 10:08:06.476966 # # RNG present
8198 10:08:06.477124 # ok 1 cpuinfo_match_RNG
8199 10:08:06.477248 # ok 2 sigill_RNG
8200 10:08:06.477363 # # SME present
8201 10:08:06.477506 # ok 3 cpuinfo_match_SME
8202 10:08:06.477627 # ok 4 sigill_SME
8203 10:08:06.477761 # # SVE present
8204 10:08:06.477875 # ok 5 cpuinfo_match_SVE
8205 10:08:06.477986 # ok 6 sigill_SVE
8206 10:08:06.478096 # # SVE 2 present
8207 10:08:06.478207 # ok 7 cpuinfo_match_SVE 2
8208 10:08:06.478318 # ok 8 sigill_SVE 2
8209 10:08:06.478427 # # SVE AES present
8210 10:08:06.478536 # ok 9 cpuinfo_match_SVE AES
8211 10:08:06.478645 # ok 10 sigill_SVE AES
8212 10:08:06.483546 # # SVE2 PMULL present
8213 10:08:06.484060 # ok 11 cpuinfo_match_SVE2 PMULL
8214 10:08:06.484239 # ok 12 sigill_SVE2 PMULL
8215 10:08:06.484436 # # SVE2 BITPERM present
8216 10:08:06.484621 # ok 13 cpuinfo_match_SVE2 BITPERM
8217 10:08:06.484807 # ok 14 sigill_SVE2 BITPERM
8218 10:08:06.484986 # # SVE2 SHA3 present
8219 10:08:06.485151 # ok 15 cpuinfo_match_SVE2 SHA3
8220 10:08:06.485275 # ok 16 sigill_SVE2 SHA3
8221 10:08:06.485417 # # SVE2 SM4 present
8222 10:08:06.485537 # ok 17 cpuinfo_match_SVE2 SM4
8223 10:08:06.485666 # ok 18 sigill_SVE2 SM4
8224 10:08:06.485782 # # SVE2 I8MM present
8225 10:08:06.485897 # ok 19 cpuinfo_match_SVE2 I8MM
8226 10:08:06.486008 # ok 20 sigill_SVE2 I8MM
8227 10:08:06.486118 # # SVE2 F32MM present
8228 10:08:06.486228 # ok 21 cpuinfo_match_SVE2 F32MM
8229 10:08:06.486338 # ok 22 sigill_SVE2 F32MM
8230 10:08:06.486447 # # SVE2 F64MM present
8231 10:08:06.486556 # ok 23 cpuinfo_match_SVE2 F64MM
8232 10:08:06.486667 # ok 24 sigill_SVE2 F64MM
8233 10:08:06.486782 # # SVE2 BF16 present
8234 10:08:06.494610 # ok 25 cpuinfo_match_SVE2 BF16
8235 10:08:06.494917 # ok 26 sigill_SVE2 BF16
8236 10:08:06.495258 # ok 27 cpuinfo_match_SVE2 EBF16
8237 10:08:06.495381 # ok 28 # SKIP sigill_SVE2 EBF16
8238 10:08:06.495495 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:1 error:0
8239 10:08:06.515146 ok 45 selftests: arm64: hwcap
8240 10:08:06.722983 # selftests: arm64: ptrace
8241 10:08:06.923196 # TAP version 13
8242 10:08:06.923477 # 1..7
8243 10:08:06.923606 # # Parent is 4446, child is 4447
8244 10:08:06.923724 # ok 1 read_tpidr_one
8245 10:08:06.923837 # ok 2 write_tpidr_one
8246 10:08:06.923949 # ok 3 verify_tpidr_one
8247 10:08:06.924060 # ok 4 count_tpidrs
8248 10:08:06.924172 # ok 5 tpidr2_write
8249 10:08:06.924282 # ok 6 tpidr2_read
8250 10:08:06.924392 # ok 7 write_tpidr_only
8251 10:08:06.924724 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
8252 10:08:06.950794 ok 46 selftests: arm64: ptrace
8253 10:08:07.099062 # selftests: arm64: syscall-abi
8254 10:08:09.727493 # TAP version 13
8255 10:08:09.727931 # 1..514
8256 10:08:09.728132 # # SME with FA64
8257 10:08:09.728302 # ok 1 getpid() FPSIMD
8258 10:08:09.728469 # ok 2 getpid() SVE VL 256
8259 10:08:09.728634 # ok 3 getpid() SVE VL 256/SME VL 256 SM+ZA
8260 10:08:09.728790 # ok 4 getpid() SVE VL 256/SME VL 256 SM
8261 10:08:09.728970 # ok 5 getpid() SVE VL 256/SME VL 256 ZA
8262 10:08:09.729105 # ok 6 getpid() SVE VL 256/SME VL 128 SM+ZA
8263 10:08:09.729224 # ok 7 getpid() SVE VL 256/SME VL 128 SM
8264 10:08:09.729341 # ok 8 getpid() SVE VL 256/SME VL 128 ZA
8265 10:08:09.729457 # ok 9 getpid() SVE VL 256/SME VL 64 SM+ZA
8266 10:08:09.729573 # ok 10 getpid() SVE VL 256/SME VL 64 SM
8267 10:08:09.729704 # ok 11 getpid() SVE VL 256/SME VL 64 ZA
8268 10:08:09.729821 # ok 12 getpid() SVE VL 256/SME VL 32 SM+ZA
8269 10:08:09.729980 # ok 13 getpid() SVE VL 256/SME VL 32 SM
8270 10:08:09.730142 # ok 14 getpid() SVE VL 256/SME VL 32 ZA
8271 10:08:09.730326 # ok 15 getpid() SVE VL 256/SME VL 16 SM+ZA
8272 10:08:09.730485 # ok 16 getpid() SVE VL 256/SME VL 16 SM
8273 10:08:09.730628 # ok 17 getpid() SVE VL 256/SME VL 16 ZA
8274 10:08:09.730785 # ok 18 getpid() SVE VL 240
8275 10:08:09.730936 # ok 19 getpid() SVE VL 240/SME VL 256 SM+ZA
8276 10:08:09.731093 # ok 20 getpid() SVE VL 240/SME VL 256 SM
8277 10:08:09.731285 # ok 21 getpid() SVE VL 240/SME VL 256 ZA
8278 10:08:09.731434 # ok 22 getpid() SVE VL 240/SME VL 128 SM+ZA
8279 10:08:09.731595 # ok 23 getpid() SVE VL 240/SME VL 128 SM
8280 10:08:09.731718 # ok 24 getpid() SVE VL 240/SME VL 128 ZA
8281 10:08:09.731832 # ok 25 getpid() SVE VL 240/SME VL 64 SM+ZA
8282 10:08:09.731958 # ok 26 getpid() SVE VL 240/SME VL 64 SM
8283 10:08:09.732108 # ok 27 getpid() SVE VL 240/SME VL 64 ZA
8284 10:08:09.732252 # ok 28 getpid() SVE VL 240/SME VL 32 SM+ZA
8285 10:08:09.732403 # ok 29 getpid() SVE VL 240/SME VL 32 SM
8286 10:08:09.732565 # ok 30 getpid() SVE VL 240/SME VL 32 ZA
8287 10:08:09.732766 # ok 31 getpid() SVE VL 240/SME VL 16 SM+ZA
8288 10:08:09.732925 # ok 32 getpid() SVE VL 240/SME VL 16 SM
8289 10:08:09.733069 # ok 33 getpid() SVE VL 240/SME VL 16 ZA
8290 10:08:09.733183 # ok 34 getpid() SVE VL 224
8291 10:08:09.733293 # ok 35 getpid() SVE VL 224/SME VL 256 SM+ZA
8292 10:08:09.733402 # ok 36 getpid() SVE VL 224/SME VL 256 SM
8293 10:08:09.733511 # ok 37 getpid() SVE VL 224/SME VL 256 ZA
8294 10:08:09.733620 # ok 38 getpid() SVE VL 224/SME VL 128 SM+ZA
8295 10:08:09.733840 # ok 39 getpid() SVE VL 224/SME VL 128 SM
8296 10:08:09.734032 # ok 40 getpid() SVE VL 224/SME VL 128 ZA
8297 10:08:09.734212 # ok 41 getpid() SVE VL 224/SME VL 64 SM+ZA
8298 10:08:09.734391 # ok 42 getpid() SVE VL 224/SME VL 64 SM
8299 10:08:09.734569 # ok 43 getpid() SVE VL 224/SME VL 64 ZA
8300 10:08:09.734750 # ok 44 getpid() SVE VL 224/SME VL 32 SM+ZA
8301 10:08:09.734891 # ok 45 getpid() SVE VL 224/SME VL 32 SM
8302 10:08:09.735030 # ok 46 getpid() SVE VL 224/SME VL 32 ZA
8303 10:08:09.735386 # ok 47 getpid() SVE VL 224/SME VL 16 SM+ZA
8304 10:08:09.735524 # ok 48 getpid() SVE VL 224/SME VL 16 SM
8305 10:08:09.737520 # ok 49 getpid() SVE VL 224/SME VL 16 ZA
8306 10:08:09.737739 # ok 50 getpid() SVE VL 208
8307 10:08:09.738145 # ok 51 getpid() SVE VL 208/SME VL 256 SM+ZA
8308 10:08:09.738322 # ok 52 getpid() SVE VL 208/SME VL 256 SM
8309 10:08:09.738519 # ok 53 getpid() SVE VL 208/SME VL 256 ZA
8310 10:08:09.738724 # ok 54 getpid() SVE VL 208/SME VL 128 SM+ZA
8311 10:08:09.738881 # ok 55 getpid() SVE VL 208/SME VL 128 SM
8312 10:08:09.739061 # ok 56 getpid() SVE VL 208/SME VL 128 ZA
8313 10:08:09.739198 # ok 57 getpid() SVE VL 208/SME VL 64 SM+ZA
8314 10:08:09.739340 # ok 58 getpid() SVE VL 208/SME VL 64 SM
8315 10:08:09.739481 # ok 59 getpid() SVE VL 208/SME VL 64 ZA
8316 10:08:09.739655 # ok 60 getpid() SVE VL 208/SME VL 32 SM+ZA
8317 10:08:09.739864 # ok 61 getpid() SVE VL 208/SME VL 32 SM
8318 10:08:09.740066 # ok 62 getpid() SVE VL 208/SME VL 32 ZA
8319 10:08:09.740243 # ok 63 getpid() SVE VL 208/SME VL 16 SM+ZA
8320 10:08:09.740376 # ok 64 getpid() SVE VL 208/SME VL 16 SM
8321 10:08:09.740547 # ok 65 getpid() SVE VL 208/SME VL 16 ZA
8322 10:08:09.740705 # ok 66 getpid() SVE VL 192
8323 10:08:09.740853 # ok 67 getpid() SVE VL 192/SME VL 256 SM+ZA
8324 10:08:09.741013 # ok 68 getpid() SVE VL 192/SME VL 256 SM
8325 10:08:09.741143 # ok 69 getpid() SVE VL 192/SME VL 256 ZA
8326 10:08:09.741258 # ok 70 getpid() SVE VL 192/SME VL 128 SM+ZA
8327 10:08:09.741372 # ok 71 getpid() SVE VL 192/SME VL 128 SM
8328 10:08:09.741485 # ok 72 getpid() SVE VL 192/SME VL 128 ZA
8329 10:08:09.741599 # ok 73 getpid() SVE VL 192/SME VL 64 SM+ZA
8330 10:08:09.741732 # ok 74 getpid() SVE VL 192/SME VL 64 SM
8331 10:08:09.741849 # ok 75 getpid() SVE VL 192/SME VL 64 ZA
8332 10:08:09.741967 # ok 76 getpid() SVE VL 192/SME VL 32 SM+ZA
8333 10:08:09.742080 # ok 77 getpid() SVE VL 192/SME VL 32 SM
8334 10:08:09.742195 # ok 78 getpid() SVE VL 192/SME VL 32 ZA
8335 10:08:09.742309 # ok 79 getpid() SVE VL 192/SME VL 16 SM+ZA
8336 10:08:09.742451 # ok 80 getpid() SVE VL 192/SME VL 16 SM
8337 10:08:09.742572 # ok 81 getpid() SVE VL 192/SME VL 16 ZA
8338 10:08:09.742687 # ok 82 getpid() SVE VL 176
8339 10:08:09.742802 # ok 83 getpid() SVE VL 176/SME VL 256 SM+ZA
8340 10:08:09.745261 # ok 84 getpid() SVE VL 176/SME VL 256 SM
8341 10:08:09.745695 # ok 85 getpid() SVE VL 176/SME VL 256 ZA
8342 10:08:09.745915 # ok 86 getpid() SVE VL 176/SME VL 128 SM+ZA
8343 10:08:09.746144 # ok 87 getpid() SVE VL 176/SME VL 128 SM
8344 10:08:09.746349 # ok 88 getpid() SVE VL 176/SME VL 128 ZA
8345 10:08:09.746543 # ok 89 getpid() SVE VL 176/SME VL 64 SM+ZA
8346 10:08:09.746707 # ok 90 getpid() SVE VL 176/SME VL 64 SM
8347 10:08:09.746836 # ok 91 getpid() SVE VL 176/SME VL 64 ZA
8348 10:08:09.746951 # ok 92 getpid() SVE VL 176/SME VL 32 SM+ZA
8349 10:08:09.747066 # ok 93 getpid() SVE VL 176/SME VL 32 SM
8350 10:08:09.747180 # ok 94 getpid() SVE VL 176/SME VL 32 ZA
8351 10:08:09.747294 # ok 95 getpid() SVE VL 176/SME VL 16 SM+ZA
8352 10:08:09.747408 # ok 96 getpid() SVE VL 176/SME VL 16 SM
8353 10:08:09.747522 # ok 97 getpid() SVE VL 176/SME VL 16 ZA
8354 10:08:09.747634 # ok 98 getpid() SVE VL 160
8355 10:08:12.198013 # ok 99 getpid() SVE VL 160/SME VL 256 SM+ZA
8356 10:08:12.198530 # ok 100 getpid() SVE VL 160/SME VL 256 SM
8357 10:08:12.198638 # ok 101 getpid() SVE VL 160/SME VL 256 ZA
8358 10:08:12.198732 # ok 102 getpid() SVE VL 160/SME VL 128 SM+ZA
8359 10:08:12.198823 # ok 103 getpid() SVE VL 160/SME VL 128 SM
8360 10:08:12.198912 # ok 104 getpid() SVE VL 160/SME VL 128 ZA
8361 10:08:12.198996 # ok 105 getpid() SVE VL 160/SME VL 64 SM+ZA
8362 10:08:12.199076 # ok 106 getpid() SVE VL 160/SME VL 64 SM
8363 10:08:12.199173 # ok 107 getpid() SVE VL 160/SME VL 64 ZA
8364 10:08:12.199255 # ok 108 getpid() SVE VL 160/SME VL 32 SM+ZA
8365 10:08:12.199335 # ok 109 getpid() SVE VL 160/SME VL 32 SM
8366 10:08:12.199413 # ok 110 getpid() SVE VL 160/SME VL 32 ZA
8367 10:08:12.199497 # ok 111 getpid() SVE VL 160/SME VL 16 SM+ZA
8368 10:08:12.199576 # ok 112 getpid() SVE VL 160/SME VL 16 SM
8369 10:08:12.199655 # ok 113 getpid() SVE VL 160/SME VL 16 ZA
8370 10:08:12.199751 # ok 114 getpid() SVE VL 144
8371 10:08:12.199833 # ok 115 getpid() SVE VL 144/SME VL 256 SM+ZA
8372 10:08:12.199913 # ok 116 getpid() SVE VL 144/SME VL 256 SM
8373 10:08:12.199991 # ok 117 getpid() SVE VL 144/SME VL 256 ZA
8374 10:08:12.200069 # ok 118 getpid() SVE VL 144/SME VL 128 SM+ZA
8375 10:08:12.200147 # ok 119 getpid() SVE VL 144/SME VL 128 SM
8376 10:08:12.200225 # ok 120 getpid() SVE VL 144/SME VL 128 ZA
8377 10:08:12.200303 # ok 121 getpid() SVE VL 144/SME VL 64 SM+ZA
8378 10:08:12.200381 # ok 122 getpid() SVE VL 144/SME VL 64 SM
8379 10:08:12.200475 # ok 123 getpid() SVE VL 144/SME VL 64 ZA
8380 10:08:12.200554 # ok 124 getpid() SVE VL 144/SME VL 32 SM+ZA
8381 10:08:12.200627 # ok 125 getpid() SVE VL 144/SME VL 32 SM
8382 10:08:12.200700 # ok 126 getpid() SVE VL 144/SME VL 32 ZA
8383 10:08:12.200778 # ok 127 getpid() SVE VL 144/SME VL 16 SM+ZA
8384 10:08:12.200861 # ok 128 getpid() SVE VL 144/SME VL 16 SM
8385 10:08:12.200951 # ok 129 getpid() SVE VL 144/SME VL 16 ZA
8386 10:08:12.201059 # ok 130 getpid() SVE VL 128
8387 10:08:12.201149 # ok 131 getpid() SVE VL 128/SME VL 256 SM+ZA
8388 10:08:12.201229 # ok 132 getpid() SVE VL 128/SME VL 256 SM
8389 10:08:12.201311 # ok 133 getpid() SVE VL 128/SME VL 256 ZA
8390 10:08:12.201400 # ok 134 getpid() SVE VL 128/SME VL 128 SM+ZA
8391 10:08:12.201483 # ok 135 getpid() SVE VL 128/SME VL 128 SM
8392 10:08:12.201546 # ok 136 getpid() SVE VL 128/SME VL 128 ZA
8393 10:08:12.201604 # ok 137 getpid() SVE VL 128/SME VL 64 SM+ZA
8394 10:08:12.201672 # ok 138 getpid() SVE VL 128/SME VL 64 SM
8395 10:08:12.205542 # ok 139 getpid() SVE VL 128/SME VL 64 ZA
8396 10:08:12.205719 # ok 140 getpid() SVE VL 128/SME VL 32 SM+ZA
8397 10:08:12.206021 # ok 141 getpid() SVE VL 128/SME VL 32 SM
8398 10:08:12.206124 # ok 142 getpid() SVE VL 128/SME VL 32 ZA
8399 10:08:12.206209 # ok 143 getpid() SVE VL 128/SME VL 16 SM+ZA
8400 10:08:12.206288 # ok 144 getpid() SVE VL 128/SME VL 16 SM
8401 10:08:12.206364 # ok 145 getpid() SVE VL 128/SME VL 16 ZA
8402 10:08:12.206440 # ok 146 getpid() SVE VL 112
8403 10:08:12.206718 # ok 147 getpid() SVE VL 112/SME VL 256 SM+ZA
8404 10:08:12.206814 # ok 148 getpid() SVE VL 112/SME VL 256 SM
8405 10:08:12.206893 # ok 149 getpid() SVE VL 112/SME VL 256 ZA
8406 10:08:12.206970 # ok 150 getpid() SVE VL 112/SME VL 128 SM+ZA
8407 10:08:12.207047 # ok 151 getpid() SVE VL 112/SME VL 128 SM
8408 10:08:12.207122 # ok 152 getpid() SVE VL 112/SME VL 128 ZA
8409 10:08:12.207197 # ok 153 getpid() SVE VL 112/SME VL 64 SM+ZA
8410 10:08:12.207288 # ok 154 getpid() SVE VL 112/SME VL 64 SM
8411 10:08:12.207366 # ok 155 getpid() SVE VL 112/SME VL 64 ZA
8412 10:08:12.207442 # ok 156 getpid() SVE VL 112/SME VL 32 SM+ZA
8413 10:08:12.207517 # ok 157 getpid() SVE VL 112/SME VL 32 SM
8414 10:08:12.207593 # ok 158 getpid() SVE VL 112/SME VL 32 ZA
8415 10:08:12.207669 # ok 159 getpid() SVE VL 112/SME VL 16 SM+ZA
8416 10:08:12.207760 # ok 160 getpid() SVE VL 112/SME VL 16 SM
8417 10:08:12.207838 # ok 161 getpid() SVE VL 112/SME VL 16 ZA
8418 10:08:12.207913 # ok 162 getpid() SVE VL 96
8419 10:08:12.207988 # ok 163 getpid() SVE VL 96/SME VL 256 SM+ZA
8420 10:08:12.208063 # ok 164 getpid() SVE VL 96/SME VL 256 SM
8421 10:08:12.208138 # ok 165 getpid() SVE VL 96/SME VL 256 ZA
8422 10:08:12.208213 # ok 166 getpid() SVE VL 96/SME VL 128 SM+ZA
8423 10:08:12.208305 # ok 167 getpid() SVE VL 96/SME VL 128 SM
8424 10:08:12.208383 # ok 168 getpid() SVE VL 96/SME VL 128 ZA
8425 10:08:12.208459 # ok 169 getpid() SVE VL 96/SME VL 64 SM+ZA
8426 10:08:12.208534 # ok 170 getpid() SVE VL 96/SME VL 64 SM
8427 10:08:12.208609 # ok 171 getpid() SVE VL 96/SME VL 64 ZA
8428 10:08:12.208684 # ok 172 getpid() SVE VL 96/SME VL 32 SM+ZA
8429 10:08:12.208775 # ok 173 getpid() SVE VL 96/SME VL 32 SM
8430 10:08:12.208853 # ok 174 getpid() SVE VL 96/SME VL 32 ZA
8431 10:08:12.208930 # ok 175 getpid() SVE VL 96/SME VL 16 SM+ZA
8432 10:08:12.209006 # ok 176 getpid() SVE VL 96/SME VL 16 SM
8433 10:08:12.209080 # ok 177 getpid() SVE VL 96/SME VL 16 ZA
8434 10:08:12.209155 # ok 178 getpid() SVE VL 80
8435 10:08:12.209230 # ok 179 getpid() SVE VL 80/SME VL 256 SM+ZA
8436 10:08:12.209305 # ok 180 getpid() SVE VL 80/SME VL 256 SM
8437 10:08:12.209394 # ok 181 getpid() SVE VL 80/SME VL 256 ZA
8438 10:08:12.209472 # ok 182 getpid() SVE VL 80/SME VL 128 SM+ZA
8439 10:08:12.209739 # ok 183 getpid() SVE VL 80/SME VL 128 SM
8440 10:08:12.217743 # ok 184 getpid() SVE VL 80/SME VL 128 ZA
8441 10:08:12.217917 # ok 185 getpid() SVE VL 80/SME VL 64 SM+ZA
8442 10:08:12.218045 # ok 186 getpid() SVE VL 80/SME VL 64 SM
8443 10:08:12.218162 # ok 187 getpid() SVE VL 80/SME VL 64 ZA
8444 10:08:12.218275 # ok 188 getpid() SVE VL 80/SME VL 32 SM+ZA
8445 10:08:12.218389 # ok 189 getpid() SVE VL 80/SME VL 32 SM
8446 10:08:12.218500 # ok 190 getpid() SVE VL 80/SME VL 32 ZA
8447 10:08:12.218615 # ok 191 getpid() SVE VL 80/SME VL 16 SM+ZA
8448 10:08:12.218727 # ok 192 getpid() SVE VL 80/SME VL 16 SM
8449 10:08:12.218838 # ok 193 getpid() SVE VL 80/SME VL 16 ZA
8450 10:08:12.218950 # ok 194 getpid() SVE VL 64
8451 10:08:12.219060 # ok 195 getpid() SVE VL 64/SME VL 256 SM+ZA
8452 10:08:14.491009 # ok 196 getpid() SVE VL 64/SME VL 256 SM
8453 10:08:14.491858 # ok 197 getpid() SVE VL 64/SME VL 256 ZA
8454 10:08:14.492067 # ok 198 getpid() SVE VL 64/SME VL 128 SM+ZA
8455 10:08:14.492257 # ok 199 getpid() SVE VL 64/SME VL 128 SM
8456 10:08:14.492419 # ok 200 getpid() SVE VL 64/SME VL 128 ZA
8457 10:08:14.492580 # ok 201 getpid() SVE VL 64/SME VL 64 SM+ZA
8458 10:08:14.492740 # ok 202 getpid() SVE VL 64/SME VL 64 SM
8459 10:08:14.492898 # ok 203 getpid() SVE VL 64/SME VL 64 ZA
8460 10:08:14.493039 # ok 204 getpid() SVE VL 64/SME VL 32 SM+ZA
8461 10:08:14.493156 # ok 205 getpid() SVE VL 64/SME VL 32 SM
8462 10:08:14.493269 # ok 206 getpid() SVE VL 64/SME VL 32 ZA
8463 10:08:14.493419 # ok 207 getpid() SVE VL 64/SME VL 16 SM+ZA
8464 10:08:14.493540 # ok 208 getpid() SVE VL 64/SME VL 16 SM
8465 10:08:14.493688 # ok 209 getpid() SVE VL 64/SME VL 16 ZA
8466 10:08:14.493866 # ok 210 getpid() SVE VL 48
8467 10:08:14.494015 # ok 211 getpid() SVE VL 48/SME VL 256 SM+ZA
8468 10:08:14.494158 # ok 212 getpid() SVE VL 48/SME VL 256 SM
8469 10:08:14.494327 # ok 213 getpid() SVE VL 48/SME VL 256 ZA
8470 10:08:14.494515 # ok 214 getpid() SVE VL 48/SME VL 128 SM+ZA
8471 10:08:14.494671 # ok 215 getpid() SVE VL 48/SME VL 128 SM
8472 10:08:14.494814 # ok 216 getpid() SVE VL 48/SME VL 128 ZA
8473 10:08:14.494958 # ok 217 getpid() SVE VL 48/SME VL 64 SM+ZA
8474 10:08:14.495077 # ok 218 getpid() SVE VL 48/SME VL 64 SM
8475 10:08:14.495193 # ok 219 getpid() SVE VL 48/SME VL 64 ZA
8476 10:08:14.495308 # ok 220 getpid() SVE VL 48/SME VL 32 SM+ZA
8477 10:08:14.495422 # ok 221 getpid() SVE VL 48/SME VL 32 SM
8478 10:08:14.495537 # ok 222 getpid() SVE VL 48/SME VL 32 ZA
8479 10:08:14.495652 # ok 223 getpid() SVE VL 48/SME VL 16 SM+ZA
8480 10:08:14.501583 # ok 224 getpid() SVE VL 48/SME VL 16 SM
8481 10:08:14.501922 # ok 225 getpid() SVE VL 48/SME VL 16 ZA
8482 10:08:14.502050 # ok 226 getpid() SVE VL 32
8483 10:08:14.502142 # ok 227 getpid() SVE VL 32/SME VL 256 SM+ZA
8484 10:08:14.502243 # ok 228 getpid() SVE VL 32/SME VL 256 SM
8485 10:08:14.502329 # ok 229 getpid() SVE VL 32/SME VL 256 ZA
8486 10:08:14.502617 # ok 230 getpid() SVE VL 32/SME VL 128 SM+ZA
8487 10:08:14.502721 # ok 231 getpid() SVE VL 32/SME VL 128 SM
8488 10:08:14.502805 # ok 232 getpid() SVE VL 32/SME VL 128 ZA
8489 10:08:14.502887 # ok 233 getpid() SVE VL 32/SME VL 64 SM+ZA
8490 10:08:14.502965 # ok 234 getpid() SVE VL 32/SME VL 64 SM
8491 10:08:14.503063 # ok 235 getpid() SVE VL 32/SME VL 64 ZA
8492 10:08:14.503144 # ok 236 getpid() SVE VL 32/SME VL 32 SM+ZA
8493 10:08:14.503237 # ok 237 getpid() SVE VL 32/SME VL 32 SM
8494 10:08:14.503318 # ok 238 getpid() SVE VL 32/SME VL 32 ZA
8495 10:08:14.503395 # ok 239 getpid() SVE VL 32/SME VL 16 SM+ZA
8496 10:08:14.503487 # ok 240 getpid() SVE VL 32/SME VL 16 SM
8497 10:08:14.503983 # ok 241 getpid() SVE VL 32/SME VL 16 ZA
8498 10:08:14.504085 # ok 242 getpid() SVE VL 16
8499 10:08:14.504168 # ok 243 getpid() SVE VL 16/SME VL 256 SM+ZA
8500 10:08:14.504293 # ok 244 getpid() SVE VL 16/SME VL 256 SM
8501 10:08:14.504374 # ok 245 getpid() SVE VL 16/SME VL 256 ZA
8502 10:08:14.505058 # ok 246 getpid() SVE VL 16/SME VL 128 SM+ZA
8503 10:08:14.505164 # ok 247 getpid() SVE VL 16/SME VL 128 SM
8504 10:08:14.505247 # ok 248 getpid() SVE VL 16/SME VL 128 ZA
8505 10:08:14.505327 # ok 249 getpid() SVE VL 16/SME VL 64 SM+ZA
8506 10:08:14.505406 # ok 250 getpid() SVE VL 16/SME VL 64 SM
8507 10:08:14.505486 # ok 251 getpid() SVE VL 16/SME VL 64 ZA
8508 10:08:14.505564 # ok 252 getpid() SVE VL 16/SME VL 32 SM+ZA
8509 10:08:14.505643 # ok 253 getpid() SVE VL 16/SME VL 32 SM
8510 10:08:14.505927 # ok 254 getpid() SVE VL 16/SME VL 32 ZA
8511 10:08:14.506029 # ok 255 getpid() SVE VL 16/SME VL 16 SM+ZA
8512 10:08:14.506352 # ok 256 getpid() SVE VL 16/SME VL 16 SM
8513 10:08:14.506556 # ok 257 getpid() SVE VL 16/SME VL 16 ZA
8514 10:08:14.506759 # ok 258 sched_yield() FPSIMD
8515 10:08:14.506974 # ok 259 sched_yield() SVE VL 256
8516 10:08:14.507303 # ok 260 sched_yield() SVE VL 256/SME VL 256 SM+ZA
8517 10:08:14.507487 # ok 261 sched_yield() SVE VL 256/SME VL 256 SM
8518 10:08:14.507650 # ok 262 sched_yield() SVE VL 256/SME VL 256 ZA
8519 10:08:14.507808 # ok 263 sched_yield() SVE VL 256/SME VL 128 SM+ZA
8520 10:08:14.507962 # ok 264 sched_yield() SVE VL 256/SME VL 128 SM
8521 10:08:14.508114 # ok 265 sched_yield() SVE VL 256/SME VL 128 ZA
8522 10:08:14.508270 # ok 266 sched_yield() SVE VL 256/SME VL 64 SM+ZA
8523 10:08:14.508429 # ok 267 sched_yield() SVE VL 256/SME VL 64 SM
8524 10:08:14.508592 # ok 268 sched_yield() SVE VL 256/SME VL 64 ZA
8525 10:08:14.508796 # ok 269 sched_yield() SVE VL 256/SME VL 32 SM+ZA
8526 10:08:14.508962 # ok 270 sched_yield() SVE VL 256/SME VL 32 SM
8527 10:08:14.509094 # ok 271 sched_yield() SVE VL 256/SME VL 32 ZA
8528 10:08:14.509209 # ok 272 sched_yield() SVE VL 256/SME VL 16 SM+ZA
8529 10:08:14.509321 # ok 273 sched_yield() SVE VL 256/SME VL 16 SM
8530 10:08:14.509434 # ok 274 sched_yield() SVE VL 256/SME VL 16 ZA
8531 10:08:14.509545 # ok 275 sched_yield() SVE VL 240
8532 10:08:14.509677 # ok 276 sched_yield() SVE VL 240/SME VL 256 SM+ZA
8533 10:08:14.509885 # ok 277 sched_yield() SVE VL 240/SME VL 256 SM
8534 10:08:14.510068 # ok 278 sched_yield() SVE VL 240/SME VL 256 ZA
8535 10:08:14.510249 # ok 279 sched_yield() SVE VL 240/SME VL 128 SM+ZA
8536 10:08:14.510424 # ok 280 sched_yield() SVE VL 240/SME VL 128 SM
8537 10:08:14.510566 # ok 281 sched_yield() SVE VL 240/SME VL 128 ZA
8538 10:08:14.510744 # ok 282 sched_yield() SVE VL 240/SME VL 64 SM+ZA
8539 10:08:14.510879 # ok 283 sched_yield() SVE VL 240/SME VL 64 SM
8540 10:08:14.511020 # ok 284 sched_yield() SVE VL 240/SME VL 64 ZA
8541 10:08:14.514116 # ok 285 sched_yield() SVE VL 240/SME VL 32 SM+ZA
8542 10:08:14.514506 # ok 286 sched_yield() SVE VL 240/SME VL 32 SM
8543 10:08:14.514608 # ok 287 sched_yield() SVE VL 240/SME VL 32 ZA
8544 10:08:14.514693 # ok 288 sched_yield() SVE VL 240/SME VL 16 SM+ZA
8545 10:08:14.514772 # ok 289 sched_yield() SVE VL 240/SME VL 16 SM
8546 10:08:16.586180 # ok 290 sched_yield() SVE VL 240/SME VL 16 ZA
8547 10:08:16.586636 # ok 291 sched_yield() SVE VL 224
8548 10:08:16.586816 # ok 292 sched_yield() SVE VL 224/SME VL 256 SM+ZA
8549 10:08:16.586994 # ok 293 sched_yield() SVE VL 224/SME VL 256 SM
8550 10:08:16.587144 # ok 294 sched_yield() SVE VL 224/SME VL 256 ZA
8551 10:08:16.587325 # ok 295 sched_yield() SVE VL 224/SME VL 128 SM+ZA
8552 10:08:16.587464 # ok 296 sched_yield() SVE VL 224/SME VL 128 SM
8553 10:08:16.587608 # ok 297 sched_yield() SVE VL 224/SME VL 128 ZA
8554 10:08:16.587752 # ok 298 sched_yield() SVE VL 224/SME VL 64 SM+ZA
8555 10:08:16.587894 # ok 299 sched_yield() SVE VL 224/SME VL 64 SM
8556 10:08:16.588070 # ok 300 sched_yield() SVE VL 224/SME VL 64 ZA
8557 10:08:16.588203 # ok 301 sched_yield() SVE VL 224/SME VL 32 SM+ZA
8558 10:08:16.588344 # ok 302 sched_yield() SVE VL 224/SME VL 32 SM
8559 10:08:16.588486 # ok 303 sched_yield() SVE VL 224/SME VL 32 ZA
8560 10:08:16.588626 # ok 304 sched_yield() SVE VL 224/SME VL 16 SM+ZA
8561 10:08:16.588800 # ok 305 sched_yield() SVE VL 224/SME VL 16 SM
8562 10:08:16.588934 # ok 306 sched_yield() SVE VL 224/SME VL 16 ZA
8563 10:08:16.589074 # ok 307 sched_yield() SVE VL 208
8564 10:08:16.589215 # ok 308 sched_yield() SVE VL 208/SME VL 256 SM+ZA
8565 10:08:16.589354 # ok 309 sched_yield() SVE VL 208/SME VL 256 SM
8566 10:08:16.589525 # ok 310 sched_yield() SVE VL 208/SME VL 256 ZA
8567 10:08:16.593661 # ok 311 sched_yield() SVE VL 208/SME VL 128 SM+ZA
8568 10:08:16.594053 # ok 312 sched_yield() SVE VL 208/SME VL 128 SM
8569 10:08:16.594205 # ok 313 sched_yield() SVE VL 208/SME VL 128 ZA
8570 10:08:16.594352 # ok 314 sched_yield() SVE VL 208/SME VL 64 SM+ZA
8571 10:08:16.594524 # ok 315 sched_yield() SVE VL 208/SME VL 64 SM
8572 10:08:16.594660 # ok 316 sched_yield() SVE VL 208/SME VL 64 ZA
8573 10:08:16.594830 # ok 317 sched_yield() SVE VL 208/SME VL 32 SM+ZA
8574 10:08:16.594966 # ok 318 sched_yield() SVE VL 208/SME VL 32 SM
8575 10:08:16.595137 # ok 319 sched_yield() SVE VL 208/SME VL 32 ZA
8576 10:08:16.595270 # ok 320 sched_yield() SVE VL 208/SME VL 16 SM+ZA
8577 10:08:16.595410 # ok 321 sched_yield() SVE VL 208/SME VL 16 SM
8578 10:08:16.595549 # ok 322 sched_yield() SVE VL 208/SME VL 16 ZA
8579 10:08:16.595721 # ok 323 sched_yield() SVE VL 192
8580 10:08:16.595860 # ok 324 sched_yield() SVE VL 192/SME VL 256 SM+ZA
8581 10:08:16.596001 # ok 325 sched_yield() SVE VL 192/SME VL 256 SM
8582 10:08:16.596142 # ok 326 sched_yield() SVE VL 192/SME VL 256 ZA
8583 10:08:16.596314 # ok 327 sched_yield() SVE VL 192/SME VL 128 SM+ZA
8584 10:08:16.596451 # ok 328 sched_yield() SVE VL 192/SME VL 128 SM
8585 10:08:16.596591 # ok 329 sched_yield() SVE VL 192/SME VL 128 ZA
8586 10:08:16.596763 # ok 330 sched_yield() SVE VL 192/SME VL 64 SM+ZA
8587 10:08:16.596911 # ok 331 sched_yield() SVE VL 192/SME VL 64 SM
8588 10:08:16.597085 # ok 332 sched_yield() SVE VL 192/SME VL 64 ZA
8589 10:08:16.597230 # ok 333 sched_yield() SVE VL 192/SME VL 32 SM+ZA
8590 10:08:16.597405 # ok 334 sched_yield() SVE VL 192/SME VL 32 SM
8591 10:08:16.597543 # ok 335 sched_yield() SVE VL 192/SME VL 32 ZA
8592 10:08:16.601480 # ok 336 sched_yield() SVE VL 192/SME VL 16 SM+ZA
8593 10:08:16.601759 # ok 337 sched_yield() SVE VL 192/SME VL 16 SM
8594 10:08:16.601868 # ok 338 sched_yield() SVE VL 192/SME VL 16 ZA
8595 10:08:16.601952 # ok 339 sched_yield() SVE VL 176
8596 10:08:16.602045 # ok 340 sched_yield() SVE VL 176/SME VL 256 SM+ZA
8597 10:08:16.602126 # ok 341 sched_yield() SVE VL 176/SME VL 256 SM
8598 10:08:16.602216 # ok 342 sched_yield() SVE VL 176/SME VL 256 ZA
8599 10:08:16.602308 # ok 343 sched_yield() SVE VL 176/SME VL 128 SM+ZA
8600 10:08:16.602399 # ok 344 sched_yield() SVE VL 176/SME VL 128 SM
8601 10:08:16.602491 # ok 345 sched_yield() SVE VL 176/SME VL 128 ZA
8602 10:08:16.602861 # ok 346 sched_yield() SVE VL 176/SME VL 64 SM+ZA
8603 10:08:16.603091 # ok 347 sched_yield() SVE VL 176/SME VL 64 SM
8604 10:08:16.603274 # ok 348 sched_yield() SVE VL 176/SME VL 64 ZA
8605 10:08:16.603433 # ok 349 sched_yield() SVE VL 176/SME VL 32 SM+ZA
8606 10:08:16.603880 # ok 350 sched_yield() SVE VL 176/SME VL 32 SM
8607 10:08:16.604104 # ok 351 sched_yield() SVE VL 176/SME VL 32 ZA
8608 10:08:16.604284 # ok 352 sched_yield() SVE VL 176/SME VL 16 SM+ZA
8609 10:08:16.604447 # ok 353 sched_yield() SVE VL 176/SME VL 16 SM
8610 10:08:16.604612 # ok 354 sched_yield() SVE VL 176/SME VL 16 ZA
8611 10:08:16.604773 # ok 355 sched_yield() SVE VL 160
8612 10:08:16.604937 # ok 356 sched_yield() SVE VL 160/SME VL 256 SM+ZA
8613 10:08:16.605122 # ok 357 sched_yield() SVE VL 160/SME VL 256 SM
8614 10:08:16.605255 # ok 358 sched_yield() SVE VL 160/SME VL 256 ZA
8615 10:08:16.605399 # ok 359 sched_yield() SVE VL 160/SME VL 128 SM+ZA
8616 10:08:16.605518 # ok 360 sched_yield() SVE VL 160/SME VL 128 SM
8617 10:08:16.605632 # ok 361 sched_yield() SVE VL 160/SME VL 128 ZA
8618 10:08:16.605841 # ok 362 sched_yield() SVE VL 160/SME VL 64 SM+ZA
8619 10:08:16.606031 # ok 363 sched_yield() SVE VL 160/SME VL 64 SM
8620 10:08:16.606204 # ok 364 sched_yield() SVE VL 160/SME VL 64 ZA
8621 10:08:16.606345 # ok 365 sched_yield() SVE VL 160/SME VL 32 SM+ZA
8622 10:08:16.606485 # ok 366 sched_yield() SVE VL 160/SME VL 32 SM
8623 10:08:16.606624 # ok 367 sched_yield() SVE VL 160/SME VL 32 ZA
8624 10:08:16.606763 # ok 368 sched_yield() SVE VL 160/SME VL 16 SM+ZA
8625 10:08:16.609380 # ok 369 sched_yield() SVE VL 160/SME VL 16 SM
8626 10:08:16.609927 # ok 370 sched_yield() SVE VL 160/SME VL 16 ZA
8627 10:08:16.610265 # ok 371 sched_yield() SVE VL 144
8628 10:08:16.610395 # ok 372 sched_yield() SVE VL 144/SME VL 256 SM+ZA
8629 10:08:16.610513 # ok 373 sched_yield() SVE VL 144/SME VL 256 SM
8630 10:08:16.610654 # ok 374 sched_yield() SVE VL 144/SME VL 256 ZA
8631 10:08:16.610776 # ok 375 sched_yield() SVE VL 144/SME VL 128 SM+ZA
8632 10:08:16.610892 # ok 376 sched_yield() SVE VL 144/SME VL 128 SM
8633 10:08:18.699901 # ok 377 sched_yield() SVE VL 144/SME VL 128 ZA
8634 10:08:18.700461 # ok 378 sched_yield() SVE VL 144/SME VL 64 SM+ZA
8635 10:08:18.700570 # ok 379 sched_yield() SVE VL 144/SME VL 64 SM
8636 10:08:18.700654 # ok 380 sched_yield() SVE VL 144/SME VL 64 ZA
8637 10:08:18.700733 # ok 381 sched_yield() SVE VL 144/SME VL 32 SM+ZA
8638 10:08:18.700831 # ok 382 sched_yield() SVE VL 144/SME VL 32 SM
8639 10:08:18.700915 # ok 383 sched_yield() SVE VL 144/SME VL 32 ZA
8640 10:08:18.700993 # ok 384 sched_yield() SVE VL 144/SME VL 16 SM+ZA
8641 10:08:18.701069 # ok 385 sched_yield() SVE VL 144/SME VL 16 SM
8642 10:08:18.701160 # ok 386 sched_yield() SVE VL 144/SME VL 16 ZA
8643 10:08:18.709514 # ok 387 sched_yield() SVE VL 128
8644 10:08:18.709846 # ok 388 sched_yield() SVE VL 128/SME VL 256 SM+ZA
8645 10:08:18.709954 # ok 389 sched_yield() SVE VL 128/SME VL 256 SM
8646 10:08:18.710041 # ok 390 sched_yield() SVE VL 128/SME VL 256 ZA
8647 10:08:18.710140 # ok 391 sched_yield() SVE VL 128/SME VL 128 SM+ZA
8648 10:08:18.710221 # ok 392 sched_yield() SVE VL 128/SME VL 128 SM
8649 10:08:18.710312 # ok 393 sched_yield() SVE VL 128/SME VL 128 ZA
8650 10:08:18.710605 # ok 394 sched_yield() SVE VL 128/SME VL 64 SM+ZA
8651 10:08:18.710710 # ok 395 sched_yield() SVE VL 128/SME VL 64 SM
8652 10:08:18.710810 # ok 396 sched_yield() SVE VL 128/SME VL 64 ZA
8653 10:08:18.710889 # ok 397 sched_yield() SVE VL 128/SME VL 32 SM+ZA
8654 10:08:18.710980 # ok 398 sched_yield() SVE VL 128/SME VL 32 SM
8655 10:08:18.711072 # ok 399 sched_yield() SVE VL 128/SME VL 32 ZA
8656 10:08:18.711164 # ok 400 sched_yield() SVE VL 128/SME VL 16 SM+ZA
8657 10:08:18.711262 # ok 401 sched_yield() SVE VL 128/SME VL 16 SM
8658 10:08:18.711411 # ok 402 sched_yield() SVE VL 128/SME VL 16 ZA
8659 10:08:18.711529 # ok 403 sched_yield() SVE VL 112
8660 10:08:18.711822 # ok 404 sched_yield() SVE VL 112/SME VL 256 SM+ZA
8661 10:08:18.711921 # ok 405 sched_yield() SVE VL 112/SME VL 256 SM
8662 10:08:18.712014 # ok 406 sched_yield() SVE VL 112/SME VL 256 ZA
8663 10:08:18.712093 # ok 407 sched_yield() SVE VL 112/SME VL 128 SM+ZA
8664 10:08:18.712961 # ok 408 sched_yield() SVE VL 112/SME VL 128 SM
8665 10:08:18.713061 # ok 409 sched_yield() SVE VL 112/SME VL 128 ZA
8666 10:08:18.713141 # ok 410 sched_yield() SVE VL 112/SME VL 64 SM+ZA
8667 10:08:18.713219 # ok 411 sched_yield() SVE VL 112/SME VL 64 SM
8668 10:08:18.713296 # ok 412 sched_yield() SVE VL 112/SME VL 64 ZA
8669 10:08:18.713373 # ok 413 sched_yield() SVE VL 112/SME VL 32 SM+ZA
8670 10:08:18.713452 # ok 414 sched_yield() SVE VL 112/SME VL 32 SM
8671 10:08:18.713529 # ok 415 sched_yield() SVE VL 112/SME VL 32 ZA
8672 10:08:18.713611 # ok 416 sched_yield() SVE VL 112/SME VL 16 SM+ZA
8673 10:08:18.713713 # ok 417 sched_yield() SVE VL 112/SME VL 16 SM
8674 10:08:18.713793 # ok 418 sched_yield() SVE VL 112/SME VL 16 ZA
8675 10:08:18.713872 # ok 419 sched_yield() SVE VL 96
8676 10:08:18.713949 # ok 420 sched_yield() SVE VL 96/SME VL 256 SM+ZA
8677 10:08:18.714459 # ok 421 sched_yield() SVE VL 96/SME VL 256 SM
8678 10:08:18.714815 # ok 422 sched_yield() SVE VL 96/SME VL 256 ZA
8679 10:08:18.715239 # ok 423 sched_yield() SVE VL 96/SME VL 128 SM+ZA
8680 10:08:18.715343 # ok 424 sched_yield() SVE VL 96/SME VL 128 SM
8681 10:08:18.715442 # ok 425 sched_yield() SVE VL 96/SME VL 128 ZA
8682 10:08:18.715522 # ok 426 sched_yield() SVE VL 96/SME VL 64 SM+ZA
8683 10:08:18.715599 # ok 427 sched_yield() SVE VL 96/SME VL 64 SM
8684 10:08:18.715675 # ok 428 sched_yield() SVE VL 96/SME VL 64 ZA
8685 10:08:18.715750 # ok 429 sched_yield() SVE VL 96/SME VL 32 SM+ZA
8686 10:08:18.715830 # ok 430 sched_yield() SVE VL 96/SME VL 32 SM
8687 10:08:18.715920 # ok 431 sched_yield() SVE VL 96/SME VL 32 ZA
8688 10:08:18.715998 # ok 432 sched_yield() SVE VL 96/SME VL 16 SM+ZA
8689 10:08:18.716087 # ok 433 sched_yield() SVE VL 96/SME VL 16 SM
8690 10:08:18.716164 # ok 434 sched_yield() SVE VL 96/SME VL 16 ZA
8691 10:08:18.716240 # ok 435 sched_yield() SVE VL 80
8692 10:08:18.716866 # ok 436 sched_yield() SVE VL 80/SME VL 256 SM+ZA
8693 10:08:18.717002 # ok 437 sched_yield() SVE VL 80/SME VL 256 SM
8694 10:08:18.717091 # ok 438 sched_yield() SVE VL 80/SME VL 256 ZA
8695 10:08:18.717168 # ok 439 sched_yield() SVE VL 80/SME VL 128 SM+ZA
8696 10:08:18.717245 # ok 440 sched_yield() SVE VL 80/SME VL 128 SM
8697 10:08:18.717321 # ok 441 sched_yield() SVE VL 80/SME VL 128 ZA
8698 10:08:18.717397 # ok 442 sched_yield() SVE VL 80/SME VL 64 SM+ZA
8699 10:08:18.717474 # ok 443 sched_yield() SVE VL 80/SME VL 64 SM
8700 10:08:18.717747 # ok 444 sched_yield() SVE VL 80/SME VL 64 ZA
8701 10:08:18.717847 # ok 445 sched_yield() SVE VL 80/SME VL 32 SM+ZA
8702 10:08:18.717926 # ok 446 sched_yield() SVE VL 80/SME VL 32 SM
8703 10:08:18.721775 # ok 447 sched_yield() SVE VL 80/SME VL 32 ZA
8704 10:08:18.722068 # ok 448 sched_yield() SVE VL 80/SME VL 16 SM+ZA
8705 10:08:18.722166 # ok 449 sched_yield() SVE VL 80/SME VL 16 SM
8706 10:08:18.722268 # ok 450 sched_yield() SVE VL 80/SME VL 16 ZA
8707 10:08:18.722361 # ok 451 sched_yield() SVE VL 64
8708 10:08:18.722633 # ok 452 sched_yield() SVE VL 64/SME VL 256 SM+ZA
8709 10:08:18.722716 # ok 453 sched_yield() SVE VL 64/SME VL 256 SM
8710 10:08:18.722793 # ok 454 sched_yield() SVE VL 64/SME VL 256 ZA
8711 10:08:18.722885 # ok 455 sched_yield() SVE VL 64/SME VL 128 SM+ZA
8712 10:08:18.723148 # ok 456 sched_yield() SVE VL 64/SME VL 128 SM
8713 10:08:18.723228 # ok 457 sched_yield() SVE VL 64/SME VL 128 ZA
8714 10:08:18.723317 # ok 458 sched_yield() SVE VL 64/SME VL 64 SM+ZA
8715 10:08:18.723621 # ok 459 sched_yield() SVE VL 64/SME VL 64 SM
8716 10:08:18.723705 # ok 460 sched_yield() SVE VL 64/SME VL 64 ZA
8717 10:08:18.723964 # ok 461 sched_yield() SVE VL 64/SME VL 32 SM+ZA
8718 10:08:18.724044 # ok 462 sched_yield() SVE VL 64/SME VL 32 SM
8719 10:08:18.724120 # ok 463 sched_yield() SVE VL 64/SME VL 32 ZA
8720 10:08:19.405759 # ok 464 sched_yield() SVE VL 64/SME VL 16 SM+ZA
8721 10:08:19.405969 # ok 465 sched_yield() SVE VL 64/SME VL 16 SM
8722 10:08:19.406052 # ok 466 sched_yield() SVE VL 64/SME VL 16 ZA
8723 10:08:19.406150 # ok 467 sched_yield() SVE VL 48
8724 10:08:19.406230 # ok 468 sched_yield() SVE VL 48/SME VL 256 SM+ZA
8725 10:08:19.406307 # ok 469 sched_yield() SVE VL 48/SME VL 256 SM
8726 10:08:19.406384 # ok 470 sched_yield() SVE VL 48/SME VL 256 ZA
8727 10:08:19.406475 # ok 471 sched_yield() SVE VL 48/SME VL 128 SM+ZA
8728 10:08:19.406566 # ok 472 sched_yield() SVE VL 48/SME VL 128 SM
8729 10:08:19.406645 # ok 473 sched_yield() SVE VL 48/SME VL 128 ZA
8730 10:08:19.407041 # ok 474 sched_yield() SVE VL 48/SME VL 64 SM+ZA
8731 10:08:19.407209 # ok 475 sched_yield() SVE VL 48/SME VL 64 SM
8732 10:08:19.407490 # ok 476 sched_yield() SVE VL 48/SME VL 64 ZA
8733 10:08:19.407901 # ok 477 sched_yield() SVE VL 48/SME VL 32 SM+ZA
8734 10:08:19.408006 # ok 478 sched_yield() SVE VL 48/SME VL 32 SM
8735 10:08:19.408086 # ok 479 sched_yield() SVE VL 48/SME VL 32 ZA
8736 10:08:19.408168 # ok 480 sched_yield() SVE VL 48/SME VL 16 SM+ZA
8737 10:08:19.408244 # ok 481 sched_yield() SVE VL 48/SME VL 16 SM
8738 10:08:19.408334 # ok 482 sched_yield() SVE VL 48/SME VL 16 ZA
8739 10:08:19.408413 # ok 483 sched_yield() SVE VL 32
8740 10:08:19.408865 # ok 484 sched_yield() SVE VL 32/SME VL 256 SM+ZA
8741 10:08:19.409035 # ok 485 sched_yield() SVE VL 32/SME VL 256 SM
8742 10:08:19.409124 # ok 486 sched_yield() SVE VL 32/SME VL 256 ZA
8743 10:08:19.409201 # ok 487 sched_yield() SVE VL 32/SME VL 128 SM+ZA
8744 10:08:19.409277 # ok 488 sched_yield() SVE VL 32/SME VL 128 SM
8745 10:08:19.409368 # ok 489 sched_yield() SVE VL 32/SME VL 128 ZA
8746 10:08:19.409447 # ok 490 sched_yield() SVE VL 32/SME VL 64 SM+ZA
8747 10:08:19.416800 # ok 491 sched_yield() SVE VL 32/SME VL 64 SM
8748 10:08:19.417153 # ok 492 sched_yield() SVE VL 32/SME VL 64 ZA
8749 10:08:19.417253 # ok 493 sched_yield() SVE VL 32/SME VL 32 SM+ZA
8750 10:08:19.417628 # ok 494 sched_yield() SVE VL 32/SME VL 32 SM
8751 10:08:19.417735 # ok 495 sched_yield() SVE VL 32/SME VL 32 ZA
8752 10:08:19.417828 # ok 496 sched_yield() SVE VL 32/SME VL 16 SM+ZA
8753 10:08:19.417919 # ok 497 sched_yield() SVE VL 32/SME VL 16 SM
8754 10:08:19.417998 # ok 498 sched_yield() SVE VL 32/SME VL 16 ZA
8755 10:08:19.418087 # ok 499 sched_yield() SVE VL 16
8756 10:08:19.418173 # ok 500 sched_yield() SVE VL 16/SME VL 256 SM+ZA
8757 10:08:19.418262 # ok 501 sched_yield() SVE VL 16/SME VL 256 SM
8758 10:08:19.418539 # ok 502 sched_yield() SVE VL 16/SME VL 256 ZA
8759 10:08:19.418638 # ok 503 sched_yield() SVE VL 16/SME VL 128 SM+ZA
8760 10:08:19.418716 # ok 504 sched_yield() SVE VL 16/SME VL 128 SM
8761 10:08:19.418807 # ok 505 sched_yield() SVE VL 16/SME VL 128 ZA
8762 10:08:19.418885 # ok 506 sched_yield() SVE VL 16/SME VL 64 SM+ZA
8763 10:08:19.418974 # ok 507 sched_yield() SVE VL 16/SME VL 64 SM
8764 10:08:19.419064 # ok 508 sched_yield() SVE VL 16/SME VL 64 ZA
8765 10:08:19.419159 # ok 509 sched_yield() SVE VL 16/SME VL 32 SM+ZA
8766 10:08:19.419249 # ok 510 sched_yield() SVE VL 16/SME VL 32 SM
8767 10:08:19.419346 # ok 511 sched_yield() SVE VL 16/SME VL 32 ZA
8768 10:08:19.419637 # ok 512 sched_yield() SVE VL 16/SME VL 16 SM+ZA
8769 10:08:19.419737 # ok 513 sched_yield() SVE VL 16/SME VL 16 SM
8770 10:08:19.419831 # ok 514 sched_yield() SVE VL 16/SME VL 16 ZA
8771 10:08:19.419910 # # Totals: pass:514 fail:0 xfail:0 xpass:0 skip:0 error:0
8772 10:08:19.420202 ok 47 selftests: arm64: syscall-abi
8773 10:08:19.467389 # selftests: arm64: tpidr2
8774 10:08:19.626116 # TAP version 13
8775 10:08:19.626642 # 1..5
8776 10:08:19.626759 # # PID: 4481
8777 10:08:19.626856 # ok 1 default_value
8778 10:08:19.626946 # ok 2 write_read
8779 10:08:19.627034 # ok 3 write_sleep_read
8780 10:08:19.627134 # ok 4 write_fork_read
8781 10:08:19.627219 # ok 5 write_clone_read
8782 10:08:19.627301 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8783 10:08:19.642832 ok 48 selftests: arm64: tpidr2
8784 10:08:20.147866 arm64_tags_test pass
8785 10:08:20.148458 arm64_run_tags_test_sh pass
8786 10:08:20.148663 arm64_fake_sigreturn_bad_magic pass
8787 10:08:20.148838 arm64_fake_sigreturn_bad_size pass
8788 10:08:20.148993 arm64_fake_sigreturn_bad_size_for_magic0 pass
8789 10:08:20.149126 arm64_fake_sigreturn_duplicated_fpsimd pass
8790 10:08:20.149282 arm64_fake_sigreturn_misaligned_sp pass
8791 10:08:20.149451 arm64_fake_sigreturn_missing_fpsimd pass
8792 10:08:20.149581 arm64_fake_sigreturn_sme_change_vl pass
8793 10:08:20.149726 arm64_fake_sigreturn_sve_change_vl pass
8794 10:08:20.149870 arm64_mangle_pstate_invalid_compat_toggle pass
8795 10:08:20.150008 arm64_mangle_pstate_invalid_daif_bits pass
8796 10:08:20.150154 arm64_mangle_pstate_invalid_mode_el1h pass
8797 10:08:20.150316 arm64_mangle_pstate_invalid_mode_el1t pass
8798 10:08:20.150476 arm64_mangle_pstate_invalid_mode_el2h pass
8799 10:08:20.150633 arm64_mangle_pstate_invalid_mode_el2t pass
8800 10:08:20.150793 arm64_mangle_pstate_invalid_mode_el3h pass
8801 10:08:20.150989 arm64_mangle_pstate_invalid_mode_el3t pass
8802 10:08:20.151152 arm64_sme_trap_no_sm pass
8803 10:08:20.151306 arm64_sme_trap_non_streaming skip
8804 10:08:20.151444 arm64_sme_trap_za pass
8805 10:08:20.151603 arm64_sme_vl pass
8806 10:08:20.151756 arm64_ssve_regs pass
8807 10:08:20.151902 arm64_sve_regs pass
8808 10:08:20.152072 arm64_sve_vl pass
8809 10:08:20.152245 arm64_za_no_regs pass
8810 10:08:20.152392 arm64_za_regs pass
8811 10:08:20.152548 arm64_pac_global_corrupt_pac pass
8812 10:08:20.152683 arm64_pac_global_pac_instructions_not_nop pass
8813 10:08:20.153446 arm64_pac_global_pac_instructions_not_nop_generic pass
8814 10:08:20.153600 arm64_pac_global_single_thread_different_keys pass
8815 10:08:20.153736 arm64_pac_global_exec_changed_keys pass
8816 10:08:20.153852 arm64_pac_global_context_switch_keep_keys pass
8817 10:08:20.153967 arm64_pac_global_context_switch_keep_keys_generic pass
8818 10:08:20.154081 arm64_pac pass
8819 10:08:20.154194 arm64_fp-stress_FPSIMD-0-0 pass
8820 10:08:20.154342 arm64_fp-stress_SVE-VL-256-0 pass
8821 10:08:20.154463 arm64_fp-stress_SVE-VL-240-0 pass
8822 10:08:20.154578 arm64_fp-stress_SVE-VL-224-0 pass
8823 10:08:20.154692 arm64_fp-stress_SVE-VL-208-0 pass
8824 10:08:20.154805 arm64_fp-stress_SVE-VL-192-0 pass
8825 10:08:20.154919 arm64_fp-stress_SVE-VL-176-0 pass
8826 10:08:20.155033 arm64_fp-stress_SVE-VL-160-0 pass
8827 10:08:20.155145 arm64_fp-stress_SVE-VL-144-0 pass
8828 10:08:20.155260 arm64_fp-stress_SVE-VL-128-0 pass
8829 10:08:20.155372 arm64_fp-stress_SVE-VL-112-0 pass
8830 10:08:20.155486 arm64_fp-stress_SVE-VL-96-0 pass
8831 10:08:20.155601 arm64_fp-stress_SVE-VL-80-0 pass
8832 10:08:20.155714 arm64_fp-stress_SVE-VL-64-0 pass
8833 10:08:20.155825 arm64_fp-stress_SVE-VL-48-0 pass
8834 10:08:20.155937 arm64_fp-stress_SVE-VL-32-0 pass
8835 10:08:20.156051 arm64_fp-stress_SVE-VL-16-0 pass
8836 10:08:20.156162 arm64_fp-stress_SSVE-VL-256-0 pass
8837 10:08:20.156274 arm64_fp-stress_ZA-VL-256-0 pass
8838 10:08:20.156386 arm64_fp-stress_SSVE-VL-128-0 pass
8839 10:08:20.156724 arm64_fp-stress_ZA-VL-128-0 pass
8840 10:08:20.156871 arm64_fp-stress_SSVE-VL-64-0 pass
8841 10:08:20.157060 arm64_fp-stress_ZA-VL-64-0 pass
8842 10:08:20.157275 arm64_fp-stress_SSVE-VL-32-0 pass
8843 10:08:20.157488 arm64_fp-stress_ZA-VL-32-0 pass
8844 10:08:20.157674 arm64_fp-stress_SSVE-VL-16-0 pass
8845 10:08:20.157891 arm64_fp-stress_ZA-VL-16-0 pass
8846 10:08:20.158062 arm64_fp-stress pass
8847 10:08:20.158281 arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 pass
8848 10:08:20.158448 arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state pass
8849 10:08:20.158616 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set pass
8850 10:08:20.158769 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared pass
8851 10:08:20.158931 arm64_sve-ptrace_Set_SVE_VL_16 pass
8852 10:08:20.159094 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 pass
8853 10:08:20.159287 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 pass
8854 10:08:20.159432 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 pass
8855 10:08:20.159561 arm64_sve-ptrace_Set_SVE_VL_32 pass
8856 10:08:20.159692 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 pass
8857 10:08:20.159849 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 pass
8858 10:08:20.160007 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 pass
8859 10:08:20.160165 arm64_sve-ptrace_Set_SVE_VL_48 pass
8860 10:08:20.160362 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 pass
8861 10:08:20.160527 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 pass
8862 10:08:20.160689 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 pass
8863 10:08:20.160830 arm64_sve-ptrace_Set_SVE_VL_64 pass
8864 10:08:20.160986 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 pass
8865 10:08:20.161112 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 pass
8866 10:08:20.161224 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 pass
8867 10:08:20.161336 arm64_sve-ptrace_Set_SVE_VL_80 pass
8868 10:08:20.161448 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 pass
8869 10:08:20.161559 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 pass
8870 10:08:20.161761 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 pass
8871 10:08:20.161968 arm64_sve-ptrace_Set_SVE_VL_96 pass
8872 10:08:20.162154 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 pass
8873 10:08:20.162336 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 pass
8874 10:08:20.162517 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 pass
8875 10:08:20.162699 arm64_sve-ptrace_Set_SVE_VL_112 pass
8876 10:08:20.165204 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 pass
8877 10:08:20.165665 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 pass
8878 10:08:20.165843 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 pass
8879 10:08:20.166042 arm64_sve-ptrace_Set_SVE_VL_128 pass
8880 10:08:20.166226 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 pass
8881 10:08:20.166429 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 pass
8882 10:08:20.166596 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 pass
8883 10:08:20.166756 arm64_sve-ptrace_Set_SVE_VL_144 pass
8884 10:08:20.166915 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 pass
8885 10:08:20.167077 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 pass
8886 10:08:20.167236 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 pass
8887 10:08:20.167399 arm64_sve-ptrace_Set_SVE_VL_160 pass
8888 10:08:20.167574 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 pass
8889 10:08:20.167736 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 pass
8890 10:08:20.167893 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 pass
8891 10:08:20.168054 arm64_sve-ptrace_Set_SVE_VL_176 pass
8892 10:08:20.168212 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 pass
8893 10:08:20.168369 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 pass
8894 10:08:20.168528 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 pass
8895 10:08:20.168687 arm64_sve-ptrace_Set_SVE_VL_192 pass
8896 10:08:20.168862 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 pass
8897 10:08:20.168989 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 pass
8898 10:08:20.169106 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 pass
8899 10:08:20.169220 arm64_sve-ptrace_Set_SVE_VL_208 pass
8900 10:08:20.169332 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 pass
8901 10:08:20.169443 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 pass
8902 10:08:20.169557 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 pass
8903 10:08:20.169726 arm64_sve-ptrace_Set_SVE_VL_224 pass
8904 10:08:20.169935 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 pass
8905 10:08:20.170118 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 pass
8906 10:08:20.170338 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 pass
8907 10:08:20.170527 arm64_sve-ptrace_Set_SVE_VL_240 pass
8908 10:08:20.170704 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 pass
8909 10:08:20.173415 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 pass
8910 10:08:20.173588 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 pass
8911 10:08:20.173793 arm64_sve-ptrace_Set_SVE_VL_256 pass
8912 10:08:20.173957 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 pass
8913 10:08:20.174119 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 pass
8914 10:08:20.174282 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 pass
8915 10:08:20.174475 arm64_sve-ptrace_Set_SVE_VL_272 pass
8916 10:08:20.174642 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 skip
8917 10:08:20.174802 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
8918 10:08:20.174955 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
8919 10:08:20.175103 arm64_sve-ptrace_Set_SVE_VL_288 pass
8920 10:08:20.175253 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 skip
8921 10:08:20.175437 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
8922 10:08:20.175608 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
8923 10:08:20.175745 arm64_sve-ptrace_Set_SVE_VL_304 pass
8924 10:08:20.175873 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 skip
8925 10:08:20.176017 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
8926 10:08:20.176147 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
8927 10:08:20.176299 arm64_sve-ptrace_Set_SVE_VL_320 pass
8928 10:08:20.176474 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 skip
8929 10:08:20.176678 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
8930 10:08:20.176856 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
8931 10:08:20.177004 arm64_sve-ptrace_Set_SVE_VL_336 pass
8932 10:08:20.177120 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 skip
8933 10:08:20.177233 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
8934 10:08:20.177345 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
8935 10:08:20.177459 arm64_sve-ptrace_Set_SVE_VL_352 pass
8936 10:08:20.177572 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 skip
8937 10:08:20.177731 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
8938 10:08:20.177934 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
8939 10:08:20.178120 arm64_sve-ptrace_Set_SVE_VL_368 pass
8940 10:08:20.178336 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 skip
8941 10:08:20.178524 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
8942 10:08:20.181224 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
8943 10:08:20.181434 arm64_sve-ptrace_Set_SVE_VL_384 pass
8944 10:08:20.181856 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 skip
8945 10:08:20.181970 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
8946 10:08:20.182059 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
8947 10:08:20.182145 arm64_sve-ptrace_Set_SVE_VL_400 pass
8948 10:08:20.182229 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 skip
8949 10:08:20.182327 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
8950 10:08:20.182412 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
8951 10:08:20.182495 arm64_sve-ptrace_Set_SVE_VL_416 pass
8952 10:08:20.182594 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 skip
8953 10:08:20.182693 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
8954 10:08:20.182793 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
8955 10:08:20.182894 arm64_sve-ptrace_Set_SVE_VL_432 pass
8956 10:08:20.183304 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 skip
8957 10:08:20.183505 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
8958 10:08:20.183755 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
8959 10:08:20.183917 arm64_sve-ptrace_Set_SVE_VL_448 pass
8960 10:08:20.184064 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 skip
8961 10:08:20.184207 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
8962 10:08:20.197274 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
8963 10:08:20.197706 arm64_sve-ptrace_Set_SVE_VL_464 pass
8964 10:08:20.197816 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 skip
8965 10:08:20.197906 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
8966 10:08:20.197991 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
8967 10:08:20.198092 arm64_sve-ptrace_Set_SVE_VL_480 pass
8968 10:08:20.198179 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 skip
8969 10:08:20.198281 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
8970 10:08:20.198385 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
8971 10:08:20.198474 arm64_sve-ptrace_Set_SVE_VL_496 pass
8972 10:08:20.198573 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 skip
8973 10:08:20.198882 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
8974 10:08:20.198985 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
8975 10:08:20.199088 arm64_sve-ptrace_Set_SVE_VL_512 pass
8976 10:08:20.199174 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 skip
8977 10:08:20.199271 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
8978 10:08:20.199608 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
8979 10:08:20.199801 arm64_sve-ptrace_Set_SVE_VL_528 pass
8980 10:08:20.199980 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 skip
8981 10:08:20.200147 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
8982 10:08:20.200310 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
8983 10:08:20.200467 arm64_sve-ptrace_Set_SVE_VL_544 pass
8984 10:08:20.200657 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 skip
8985 10:08:20.200824 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
8986 10:08:20.200988 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
8987 10:08:20.201170 arm64_sve-ptrace_Set_SVE_VL_560 pass
8988 10:08:20.201318 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 skip
8989 10:08:20.201495 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
8990 10:08:20.201633 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
8991 10:08:20.201789 arm64_sve-ptrace_Set_SVE_VL_576 pass
8992 10:08:20.201929 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 skip
8993 10:08:20.205195 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
8994 10:08:20.205604 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
8995 10:08:20.205817 arm64_sve-ptrace_Set_SVE_VL_592 pass
8996 10:08:20.206001 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 skip
8997 10:08:20.206186 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
8998 10:08:20.206323 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
8999 10:08:20.206466 arm64_sve-ptrace_Set_SVE_VL_608 pass
9000 10:08:20.206616 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 skip
9001 10:08:20.206808 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
9002 10:08:20.207005 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
9003 10:08:20.207173 arm64_sve-ptrace_Set_SVE_VL_624 pass
9004 10:08:20.207332 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 skip
9005 10:08:20.207489 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
9006 10:08:20.207647 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
9007 10:08:20.207804 arm64_sve-ptrace_Set_SVE_VL_640 pass
9008 10:08:20.207960 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 skip
9009 10:08:20.208117 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
9010 10:08:20.208314 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
9011 10:08:20.208484 arm64_sve-ptrace_Set_SVE_VL_656 pass
9012 10:08:20.208646 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 skip
9013 10:08:20.208804 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
9014 10:08:20.208960 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
9015 10:08:20.209080 arm64_sve-ptrace_Set_SVE_VL_672 pass
9016 10:08:20.209193 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 skip
9017 10:08:20.209305 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
9018 10:08:20.209417 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
9019 10:08:20.209581 arm64_sve-ptrace_Set_SVE_VL_688 pass
9020 10:08:20.210324 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 skip
9021 10:08:20.210501 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
9022 10:08:20.210707 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
9023 10:08:20.210882 arm64_sve-ptrace_Set_SVE_VL_704 pass
9024 10:08:20.211051 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 skip
9025 10:08:20.211217 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
9026 10:08:20.211352 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
9027 10:08:20.211471 arm64_sve-ptrace_Set_SVE_VL_720 pass
9028 10:08:20.211585 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 skip
9029 10:08:20.213198 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
9030 10:08:20.213612 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
9031 10:08:20.213828 arm64_sve-ptrace_Set_SVE_VL_736 pass
9032 10:08:20.214003 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 skip
9033 10:08:20.214173 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
9034 10:08:20.214369 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
9035 10:08:20.214523 arm64_sve-ptrace_Set_SVE_VL_752 pass
9036 10:08:20.214675 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 skip
9037 10:08:20.214825 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
9038 10:08:20.214985 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
9039 10:08:20.215118 arm64_sve-ptrace_Set_SVE_VL_768 pass
9040 10:08:20.215270 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 skip
9041 10:08:20.215448 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
9042 10:08:20.215580 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
9043 10:08:20.215720 arm64_sve-ptrace_Set_SVE_VL_784 pass
9044 10:08:20.215876 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 skip
9045 10:08:20.216039 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
9046 10:08:20.216200 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
9047 10:08:20.216348 arm64_sve-ptrace_Set_SVE_VL_800 pass
9048 10:08:20.216505 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 skip
9049 10:08:20.216701 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
9050 10:08:20.216875 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
9051 10:08:20.217027 arm64_sve-ptrace_Set_SVE_VL_816 pass
9052 10:08:20.217145 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 skip
9053 10:08:20.217260 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
9054 10:08:20.217373 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
9055 10:08:20.217486 arm64_sve-ptrace_Set_SVE_VL_832 pass
9056 10:08:20.217599 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 skip
9057 10:08:20.217806 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
9058 10:08:20.218002 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
9059 10:08:20.218222 arm64_sve-ptrace_Set_SVE_VL_848 pass
9060 10:08:20.218409 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 skip
9061 10:08:20.218591 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
9062 10:08:20.221166 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
9063 10:08:20.221678 arm64_sve-ptrace_Set_SVE_VL_864 pass
9064 10:08:20.221877 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 skip
9065 10:08:20.222043 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
9066 10:08:20.222223 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
9067 10:08:20.222385 arm64_sve-ptrace_Set_SVE_VL_880 pass
9068 10:08:20.222545 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 skip
9069 10:08:20.222701 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
9070 10:08:20.222862 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
9071 10:08:20.223026 arm64_sve-ptrace_Set_SVE_VL_896 pass
9072 10:08:20.223227 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 skip
9073 10:08:20.223394 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
9074 10:08:20.223555 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
9075 10:08:20.223710 arm64_sve-ptrace_Set_SVE_VL_912 pass
9076 10:08:20.223870 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 skip
9077 10:08:20.224031 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
9078 10:08:20.224191 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
9079 10:08:20.224337 arm64_sve-ptrace_Set_SVE_VL_928 pass
9080 10:08:20.224530 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 skip
9081 10:08:20.224773 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
9082 10:08:20.224965 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
9083 10:08:20.225114 arm64_sve-ptrace_Set_SVE_VL_944 pass
9084 10:08:20.225230 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 skip
9085 10:08:20.225343 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
9086 10:08:20.225454 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
9087 10:08:20.225566 arm64_sve-ptrace_Set_SVE_VL_960 pass
9088 10:08:20.225736 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 skip
9089 10:08:20.225943 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
9090 10:08:20.226126 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
9091 10:08:20.226306 arm64_sve-ptrace_Set_SVE_VL_976 pass
9092 10:08:20.226486 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 skip
9093 10:08:20.226668 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
9094 10:08:20.226855 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
9095 10:08:20.226991 arm64_sve-ptrace_Set_SVE_VL_992 pass
9096 10:08:20.229189 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 skip
9097 10:08:20.229638 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
9098 10:08:20.229853 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
9099 10:08:20.230028 arm64_sve-ptrace_Set_SVE_VL_1008 pass
9100 10:08:20.230184 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 skip
9101 10:08:20.230373 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
9102 10:08:20.230539 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
9103 10:08:20.230749 arm64_sve-ptrace_Set_SVE_VL_1024 pass
9104 10:08:20.230931 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 skip
9105 10:08:20.231135 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
9106 10:08:20.231324 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
9107 10:08:20.231498 arm64_sve-ptrace_Set_SVE_VL_1040 pass
9108 10:08:20.231690 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 skip
9109 10:08:20.231857 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
9110 10:08:20.232017 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
9111 10:08:20.232174 arm64_sve-ptrace_Set_SVE_VL_1056 pass
9112 10:08:20.232374 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 skip
9113 10:08:20.232544 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
9114 10:08:20.232716 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
9115 10:08:20.232884 arm64_sve-ptrace_Set_SVE_VL_1072 pass
9116 10:08:20.233014 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 skip
9117 10:08:20.233128 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
9118 10:08:20.233238 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
9119 10:08:20.233349 arm64_sve-ptrace_Set_SVE_VL_1088 pass
9120 10:08:20.233487 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 skip
9121 10:08:20.233604 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
9122 10:08:20.233814 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
9123 10:08:20.234008 arm64_sve-ptrace_Set_SVE_VL_1104 pass
9124 10:08:20.246725 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 skip
9125 10:08:20.247141 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
9126 10:08:20.247246 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
9127 10:08:20.247337 arm64_sve-ptrace_Set_SVE_VL_1120 pass
9128 10:08:20.247439 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 skip
9129 10:08:20.247530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
9130 10:08:20.247629 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
9131 10:08:20.247728 arm64_sve-ptrace_Set_SVE_VL_1136 pass
9132 10:08:20.247827 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 skip
9133 10:08:20.248129 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
9134 10:08:20.248249 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
9135 10:08:20.248349 arm64_sve-ptrace_Set_SVE_VL_1152 pass
9136 10:08:20.248665 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 skip
9137 10:08:20.248771 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
9138 10:08:20.248872 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
9139 10:08:20.248956 arm64_sve-ptrace_Set_SVE_VL_1168 pass
9140 10:08:20.249251 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 skip
9141 10:08:20.249348 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
9142 10:08:20.249450 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
9143 10:08:20.249552 arm64_sve-ptrace_Set_SVE_VL_1184 pass
9144 10:08:20.249660 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 skip
9145 10:08:20.250143 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
9146 10:08:20.250237 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
9147 10:08:20.250325 arm64_sve-ptrace_Set_SVE_VL_1200 pass
9148 10:08:20.250428 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 skip
9149 10:08:20.250514 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
9150 10:08:20.250598 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
9151 10:08:20.250698 arm64_sve-ptrace_Set_SVE_VL_1216 pass
9152 10:08:20.250787 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 skip
9153 10:08:20.250883 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
9154 10:08:20.250983 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
9155 10:08:20.251543 arm64_sve-ptrace_Set_SVE_VL_1232 pass
9156 10:08:20.251736 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 skip
9157 10:08:20.251912 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
9158 10:08:20.252071 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
9159 10:08:20.252259 arm64_sve-ptrace_Set_SVE_VL_1248 pass
9160 10:08:20.252396 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 skip
9161 10:08:20.252538 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
9162 10:08:20.252692 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
9163 10:08:20.252854 arm64_sve-ptrace_Set_SVE_VL_1264 pass
9164 10:08:20.253009 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 skip
9165 10:08:20.253217 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
9166 10:08:20.253347 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
9167 10:08:20.253463 arm64_sve-ptrace_Set_SVE_VL_1280 pass
9168 10:08:20.253577 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 skip
9169 10:08:20.253708 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
9170 10:08:20.253826 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
9171 10:08:20.257248 arm64_sve-ptrace_Set_SVE_VL_1296 pass
9172 10:08:20.257706 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 skip
9173 10:08:20.257904 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
9174 10:08:20.258074 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
9175 10:08:20.258271 arm64_sve-ptrace_Set_SVE_VL_1312 pass
9176 10:08:20.258537 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 skip
9177 10:08:20.258740 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
9178 10:08:20.258967 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
9179 10:08:20.259146 arm64_sve-ptrace_Set_SVE_VL_1328 pass
9180 10:08:20.259364 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 skip
9181 10:08:20.259577 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
9182 10:08:20.259740 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
9183 10:08:20.259903 arm64_sve-ptrace_Set_SVE_VL_1344 pass
9184 10:08:20.260079 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 skip
9185 10:08:20.260777 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
9186 10:08:20.261031 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
9187 10:08:20.261220 arm64_sve-ptrace_Set_SVE_VL_1360 pass
9188 10:08:20.261370 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 skip
9189 10:08:20.261564 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
9190 10:08:20.261776 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
9191 10:08:20.261920 arm64_sve-ptrace_Set_SVE_VL_1376 pass
9192 10:08:20.262098 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 skip
9193 10:08:20.262225 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
9194 10:08:20.262343 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
9195 10:08:20.262459 arm64_sve-ptrace_Set_SVE_VL_1392 pass
9196 10:08:20.262575 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 skip
9197 10:08:20.262690 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
9198 10:08:20.262808 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
9199 10:08:20.262926 arm64_sve-ptrace_Set_SVE_VL_1408 pass
9200 10:08:20.263042 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 skip
9201 10:08:20.265232 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
9202 10:08:20.265657 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
9203 10:08:20.265762 arm64_sve-ptrace_Set_SVE_VL_1424 pass
9204 10:08:20.265858 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 skip
9205 10:08:20.265958 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
9206 10:08:20.266044 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
9207 10:08:20.266143 arm64_sve-ptrace_Set_SVE_VL_1440 pass
9208 10:08:20.266241 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 skip
9209 10:08:20.266493 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
9210 10:08:20.266612 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
9211 10:08:20.266699 arm64_sve-ptrace_Set_SVE_VL_1456 pass
9212 10:08:20.266800 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 skip
9213 10:08:20.267007 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
9214 10:08:20.267127 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
9215 10:08:20.267427 arm64_sve-ptrace_Set_SVE_VL_1472 pass
9216 10:08:20.267526 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 skip
9217 10:08:20.267623 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
9218 10:08:20.267723 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
9219 10:08:20.267828 arm64_sve-ptrace_Set_SVE_VL_1488 pass
9220 10:08:20.268124 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 skip
9221 10:08:20.268223 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
9222 10:08:20.268509 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
9223 10:08:20.268598 arm64_sve-ptrace_Set_SVE_VL_1504 pass
9224 10:08:20.268699 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 skip
9225 10:08:20.268786 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
9226 10:08:20.268912 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
9227 10:08:20.269015 arm64_sve-ptrace_Set_SVE_VL_1520 pass
9228 10:08:20.269139 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 skip
9229 10:08:20.277156 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
9230 10:08:20.277543 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
9231 10:08:20.277776 arm64_sve-ptrace_Set_SVE_VL_1536 pass
9232 10:08:20.277990 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 skip
9233 10:08:20.278204 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
9234 10:08:20.278392 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
9235 10:08:20.278559 arm64_sve-ptrace_Set_SVE_VL_1552 pass
9236 10:08:20.278727 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 skip
9237 10:08:20.278955 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
9238 10:08:20.279170 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
9239 10:08:20.279317 arm64_sve-ptrace_Set_SVE_VL_1568 pass
9240 10:08:20.279496 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 skip
9241 10:08:20.279699 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
9242 10:08:20.279906 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
9243 10:08:20.280088 arm64_sve-ptrace_Set_SVE_VL_1584 pass
9244 10:08:20.280274 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 skip
9245 10:08:20.280473 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
9246 10:08:20.280649 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
9247 10:08:20.280799 arm64_sve-ptrace_Set_SVE_VL_1600 pass
9248 10:08:20.280952 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 skip
9249 10:08:20.281090 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
9250 10:08:20.281223 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
9251 10:08:20.281338 arm64_sve-ptrace_Set_SVE_VL_1616 pass
9252 10:08:20.281451 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 skip
9253 10:08:20.281562 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
9254 10:08:20.281769 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
9255 10:08:20.281977 arm64_sve-ptrace_Set_SVE_VL_1632 pass
9256 10:08:20.282162 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 skip
9257 10:08:20.282346 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
9258 10:08:20.285193 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
9259 10:08:20.285401 arm64_sve-ptrace_Set_SVE_VL_1648 pass
9260 10:08:20.285817 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 skip
9261 10:08:20.286009 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
9262 10:08:20.286175 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
9263 10:08:20.286330 arm64_sve-ptrace_Set_SVE_VL_1664 pass
9264 10:08:20.286520 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 skip
9265 10:08:20.286672 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
9266 10:08:20.286852 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
9267 10:08:20.287062 arm64_sve-ptrace_Set_SVE_VL_1680 pass
9268 10:08:20.287233 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 skip
9269 10:08:20.287406 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
9270 10:08:20.287571 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
9271 10:08:20.287769 arm64_sve-ptrace_Set_SVE_VL_1696 pass
9272 10:08:20.287964 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 skip
9273 10:08:20.288137 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
9274 10:08:20.288290 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
9275 10:08:20.288419 arm64_sve-ptrace_Set_SVE_VL_1712 pass
9276 10:08:20.288581 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 skip
9277 10:08:20.288716 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
9278 10:08:20.288834 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
9279 10:08:20.288949 arm64_sve-ptrace_Set_SVE_VL_1728 pass
9280 10:08:20.289062 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 skip
9281 10:08:20.289175 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
9282 10:08:20.289286 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
9283 10:08:20.289398 arm64_sve-ptrace_Set_SVE_VL_1744 pass
9284 10:08:20.298078 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 skip
9285 10:08:20.298509 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
9286 10:08:20.298677 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
9287 10:08:20.298832 arm64_sve-ptrace_Set_SVE_VL_1760 pass
9288 10:08:20.298967 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 skip
9289 10:08:20.299202 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
9290 10:08:20.299391 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
9291 10:08:20.299554 arm64_sve-ptrace_Set_SVE_VL_1776 pass
9292 10:08:20.299718 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 skip
9293 10:08:20.299854 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
9294 10:08:20.300033 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
9295 10:08:20.300248 arm64_sve-ptrace_Set_SVE_VL_1792 pass
9296 10:08:20.300415 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 skip
9297 10:08:20.300590 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
9298 10:08:20.300789 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
9299 10:08:20.300941 arm64_sve-ptrace_Set_SVE_VL_1808 pass
9300 10:08:20.301080 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 skip
9301 10:08:20.301228 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
9302 10:08:20.301348 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
9303 10:08:20.301460 arm64_sve-ptrace_Set_SVE_VL_1824 pass
9304 10:08:20.301571 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 skip
9305 10:08:20.301716 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
9306 10:08:20.301924 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
9307 10:08:20.302104 arm64_sve-ptrace_Set_SVE_VL_1840 pass
9308 10:08:20.302247 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 skip
9309 10:08:20.305226 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
9310 10:08:20.305707 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
9311 10:08:20.305920 arm64_sve-ptrace_Set_SVE_VL_1856 pass
9312 10:08:20.306088 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 skip
9313 10:08:20.306291 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
9314 10:08:20.306528 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
9315 10:08:20.306730 arm64_sve-ptrace_Set_SVE_VL_1872 pass
9316 10:08:20.306961 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 skip
9317 10:08:20.307380 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
9318 10:08:20.307622 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
9319 10:08:20.307827 arm64_sve-ptrace_Set_SVE_VL_1888 pass
9320 10:08:20.308059 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 skip
9321 10:08:20.308327 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
9322 10:08:20.308555 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
9323 10:08:20.308782 arm64_sve-ptrace_Set_SVE_VL_1904 pass
9324 10:08:20.309009 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 skip
9325 10:08:20.309164 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
9326 10:08:20.309284 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
9327 10:08:20.309398 arm64_sve-ptrace_Set_SVE_VL_1920 pass
9328 10:08:20.309511 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 skip
9329 10:08:20.309624 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
9330 10:08:20.309822 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
9331 10:08:20.310011 arm64_sve-ptrace_Set_SVE_VL_1936 pass
9332 10:08:20.310192 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 skip
9333 10:08:20.310326 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
9334 10:08:20.310467 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
9335 10:08:20.310608 arm64_sve-ptrace_Set_SVE_VL_1952 pass
9336 10:08:20.310748 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 skip
9337 10:08:20.310890 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
9338 10:08:20.311033 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
9339 10:08:20.311174 arm64_sve-ptrace_Set_SVE_VL_1968 pass
9340 10:08:20.313203 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 skip
9341 10:08:20.313707 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
9342 10:08:20.313934 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
9343 10:08:20.314131 arm64_sve-ptrace_Set_SVE_VL_1984 pass
9344 10:08:20.314302 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 skip
9345 10:08:20.314499 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
9346 10:08:20.314692 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
9347 10:08:20.314860 arm64_sve-ptrace_Set_SVE_VL_2000 pass
9348 10:08:20.315007 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 skip
9349 10:08:20.315151 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
9350 10:08:20.315301 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
9351 10:08:20.315457 arm64_sve-ptrace_Set_SVE_VL_2016 pass
9352 10:08:20.315658 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 skip
9353 10:08:20.315847 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
9354 10:08:20.315995 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
9355 10:08:20.316139 arm64_sve-ptrace_Set_SVE_VL_2032 pass
9356 10:08:20.316265 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 skip
9357 10:08:20.316382 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
9358 10:08:20.316500 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
9359 10:08:20.316620 arm64_sve-ptrace_Set_SVE_VL_2048 pass
9360 10:08:20.316738 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 skip
9361 10:08:20.316883 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
9362 10:08:20.317056 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
9363 10:08:20.317190 arm64_sve-ptrace_Set_SVE_VL_2064 pass
9364 10:08:20.317300 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 skip
9365 10:08:20.317393 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
9366 10:08:20.317482 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
9367 10:08:20.317572 arm64_sve-ptrace_Set_SVE_VL_2080 pass
9368 10:08:20.318126 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 skip
9369 10:08:20.318224 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
9370 10:08:20.318303 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
9371 10:08:20.318389 arm64_sve-ptrace_Set_SVE_VL_2096 pass
9372 10:08:20.318478 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 skip
9373 10:08:20.322028 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
9374 10:08:20.322131 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
9375 10:08:20.322209 arm64_sve-ptrace_Set_SVE_VL_2112 pass
9376 10:08:20.322282 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 skip
9377 10:08:20.322538 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
9378 10:08:20.322617 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
9379 10:08:20.322695 arm64_sve-ptrace_Set_SVE_VL_2128 pass
9380 10:08:20.322771 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 skip
9381 10:08:20.322845 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
9382 10:08:20.322924 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
9383 10:08:20.323003 arm64_sve-ptrace_Set_SVE_VL_2144 pass
9384 10:08:20.323071 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 skip
9385 10:08:20.323134 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
9386 10:08:20.323194 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
9387 10:08:20.323257 arm64_sve-ptrace_Set_SVE_VL_2160 pass
9388 10:08:20.323366 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 skip
9389 10:08:20.323454 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
9390 10:08:20.323547 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
9391 10:08:20.323636 arm64_sve-ptrace_Set_SVE_VL_2176 pass
9392 10:08:20.323733 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 skip
9393 10:08:20.323817 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
9394 10:08:20.323900 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
9395 10:08:20.323986 arm64_sve-ptrace_Set_SVE_VL_2192 pass
9396 10:08:20.324075 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 skip
9397 10:08:20.324163 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
9398 10:08:20.324464 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
9399 10:08:20.324565 arm64_sve-ptrace_Set_SVE_VL_2208 pass
9400 10:08:20.324648 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 skip
9401 10:08:20.324747 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
9402 10:08:20.324826 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
9403 10:08:20.324924 arm64_sve-ptrace_Set_SVE_VL_2224 pass
9404 10:08:20.325007 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 skip
9405 10:08:20.329175 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
9406 10:08:20.329497 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
9407 10:08:20.329626 arm64_sve-ptrace_Set_SVE_VL_2240 pass
9408 10:08:20.329763 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 skip
9409 10:08:20.329881 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
9410 10:08:20.329960 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
9411 10:08:20.330037 arm64_sve-ptrace_Set_SVE_VL_2256 pass
9412 10:08:20.330125 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 skip
9413 10:08:20.330204 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
9414 10:08:20.330294 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
9415 10:08:20.330584 arm64_sve-ptrace_Set_SVE_VL_2272 pass
9416 10:08:20.330699 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 skip
9417 10:08:20.330813 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
9418 10:08:20.330925 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
9419 10:08:20.331020 arm64_sve-ptrace_Set_SVE_VL_2288 pass
9420 10:08:20.331446 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 skip
9421 10:08:20.331539 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
9422 10:08:20.331613 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
9423 10:08:20.331906 arm64_sve-ptrace_Set_SVE_VL_2304 pass
9424 10:08:20.332013 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 skip
9425 10:08:20.332105 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
9426 10:08:20.332201 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
9427 10:08:20.332285 arm64_sve-ptrace_Set_SVE_VL_2320 pass
9428 10:08:20.332392 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 skip
9429 10:08:20.332488 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
9430 10:08:20.332611 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
9431 10:08:20.332709 arm64_sve-ptrace_Set_SVE_VL_2336 pass
9432 10:08:20.333036 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 skip
9433 10:08:20.333117 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
9434 10:08:20.337221 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
9435 10:08:20.337529 arm64_sve-ptrace_Set_SVE_VL_2352 pass
9436 10:08:20.337653 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 skip
9437 10:08:20.337752 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
9438 10:08:20.337864 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
9439 10:08:20.337950 arm64_sve-ptrace_Set_SVE_VL_2368 pass
9440 10:08:20.338227 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 skip
9441 10:08:20.338307 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
9442 10:08:20.338369 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
9443 10:08:20.338429 arm64_sve-ptrace_Set_SVE_VL_2384 pass
9444 10:08:20.351220 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 skip
9445 10:08:20.351573 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
9446 10:08:20.351714 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
9447 10:08:20.351840 arm64_sve-ptrace_Set_SVE_VL_2400 pass
9448 10:08:20.352069 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 skip
9449 10:08:20.352235 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
9450 10:08:20.352390 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
9451 10:08:20.352539 arm64_sve-ptrace_Set_SVE_VL_2416 pass
9452 10:08:20.352721 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 skip
9453 10:08:20.352891 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
9454 10:08:20.353043 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
9455 10:08:20.353181 arm64_sve-ptrace_Set_SVE_VL_2432 pass
9456 10:08:20.353346 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 skip
9457 10:08:20.353591 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
9458 10:08:20.353780 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
9459 10:08:20.353928 arm64_sve-ptrace_Set_SVE_VL_2448 pass
9460 10:08:20.354048 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 skip
9461 10:08:20.354169 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
9462 10:08:20.354331 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
9463 10:08:20.354495 arm64_sve-ptrace_Set_SVE_VL_2464 pass
9464 10:08:20.354654 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 skip
9465 10:08:20.354781 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
9466 10:08:20.354922 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
9467 10:08:20.355076 arm64_sve-ptrace_Set_SVE_VL_2480 pass
9468 10:08:20.355234 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 skip
9469 10:08:20.355425 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
9470 10:08:20.355587 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
9471 10:08:20.355741 arm64_sve-ptrace_Set_SVE_VL_2496 pass
9472 10:08:20.355900 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 skip
9473 10:08:20.356058 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
9474 10:08:20.356210 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
9475 10:08:20.356352 arm64_sve-ptrace_Set_SVE_VL_2512 pass
9476 10:08:20.356508 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 skip
9477 10:08:20.356658 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
9478 10:08:20.356810 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
9479 10:08:20.357017 arm64_sve-ptrace_Set_SVE_VL_2528 pass
9480 10:08:20.357170 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 skip
9481 10:08:20.357290 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
9482 10:08:20.357405 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
9483 10:08:20.357730 arm64_sve-ptrace_Set_SVE_VL_2544 pass
9484 10:08:20.357882 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 skip
9485 10:08:20.358009 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
9486 10:08:20.358127 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
9487 10:08:20.358240 arm64_sve-ptrace_Set_SVE_VL_2560 pass
9488 10:08:20.358354 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 skip
9489 10:08:20.358468 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
9490 10:08:20.358581 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
9491 10:08:20.358694 arm64_sve-ptrace_Set_SVE_VL_2576 pass
9492 10:08:20.361456 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 skip
9493 10:08:20.361635 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
9494 10:08:20.361889 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
9495 10:08:20.362085 arm64_sve-ptrace_Set_SVE_VL_2592 pass
9496 10:08:20.362284 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 skip
9497 10:08:20.362456 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
9498 10:08:20.362660 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
9499 10:08:20.362855 arm64_sve-ptrace_Set_SVE_VL_2608 pass
9500 10:08:20.363043 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 skip
9501 10:08:20.363215 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
9502 10:08:20.363380 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
9503 10:08:20.363582 arm64_sve-ptrace_Set_SVE_VL_2624 pass
9504 10:08:20.363774 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 skip
9505 10:08:20.363953 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
9506 10:08:20.364092 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
9507 10:08:20.364223 arm64_sve-ptrace_Set_SVE_VL_2640 pass
9508 10:08:20.364389 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 skip
9509 10:08:20.364581 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
9510 10:08:20.364766 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
9511 10:08:20.364965 arm64_sve-ptrace_Set_SVE_VL_2656 pass
9512 10:08:20.365127 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 skip
9513 10:08:20.365255 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
9514 10:08:20.365376 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
9515 10:08:20.365529 arm64_sve-ptrace_Set_SVE_VL_2672 pass
9516 10:08:20.365699 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 skip
9517 10:08:20.365903 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
9518 10:08:20.366089 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
9519 10:08:20.366269 arm64_sve-ptrace_Set_SVE_VL_2688 pass
9520 10:08:20.366449 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 skip
9521 10:08:20.366619 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
9522 10:08:20.366760 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
9523 10:08:20.366937 arm64_sve-ptrace_Set_SVE_VL_2704 pass
9524 10:08:20.367110 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 skip
9525 10:08:20.369390 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
9526 10:08:20.369889 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
9527 10:08:20.370124 arm64_sve-ptrace_Set_SVE_VL_2720 pass
9528 10:08:20.370323 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 skip
9529 10:08:20.370493 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
9530 10:08:20.370686 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
9531 10:08:20.370857 arm64_sve-ptrace_Set_SVE_VL_2736 pass
9532 10:08:20.371011 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 skip
9533 10:08:20.371467 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
9534 10:08:20.371665 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
9535 10:08:20.371827 arm64_sve-ptrace_Set_SVE_VL_2752 pass
9536 10:08:20.371990 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 skip
9537 10:08:20.372150 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
9538 10:08:20.372340 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
9539 10:08:20.372511 arm64_sve-ptrace_Set_SVE_VL_2768 pass
9540 10:08:20.372679 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 skip
9541 10:08:20.372868 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
9542 10:08:20.373055 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
9543 10:08:20.373217 arm64_sve-ptrace_Set_SVE_VL_2784 pass
9544 10:08:20.373377 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 skip
9545 10:08:20.373769 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
9546 10:08:20.373923 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
9547 10:08:20.374019 arm64_sve-ptrace_Set_SVE_VL_2800 pass
9548 10:08:20.374106 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 skip
9549 10:08:20.374193 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
9550 10:08:20.374280 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
9551 10:08:20.374366 arm64_sve-ptrace_Set_SVE_VL_2816 pass
9552 10:08:20.374453 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 skip
9553 10:08:20.374540 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
9554 10:08:20.374626 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
9555 10:08:20.374712 arm64_sve-ptrace_Set_SVE_VL_2832 pass
9556 10:08:20.374799 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 skip
9557 10:08:20.374885 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
9558 10:08:20.374972 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
9559 10:08:20.375059 arm64_sve-ptrace_Set_SVE_VL_2848 pass
9560 10:08:20.375144 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 skip
9561 10:08:20.377284 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
9562 10:08:20.377767 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
9563 10:08:20.378004 arm64_sve-ptrace_Set_SVE_VL_2864 pass
9564 10:08:20.378271 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 skip
9565 10:08:20.378506 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
9566 10:08:20.378665 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
9567 10:08:20.378823 arm64_sve-ptrace_Set_SVE_VL_2880 pass
9568 10:08:20.378954 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 skip
9569 10:08:20.379078 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
9570 10:08:20.379208 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
9571 10:08:20.379317 arm64_sve-ptrace_Set_SVE_VL_2896 pass
9572 10:08:20.379437 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 skip
9573 10:08:20.379549 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
9574 10:08:20.379654 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
9575 10:08:20.379760 arm64_sve-ptrace_Set_SVE_VL_2912 pass
9576 10:08:20.379906 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 skip
9577 10:08:20.380025 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
9578 10:08:20.380129 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
9579 10:08:20.380242 arm64_sve-ptrace_Set_SVE_VL_2928 pass
9580 10:08:20.380361 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 skip
9581 10:08:20.380498 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
9582 10:08:20.380619 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
9583 10:08:20.380731 arm64_sve-ptrace_Set_SVE_VL_2944 pass
9584 10:08:20.380867 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 skip
9585 10:08:20.380990 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
9586 10:08:20.381115 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
9587 10:08:20.381208 arm64_sve-ptrace_Set_SVE_VL_2960 pass
9588 10:08:20.381294 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 skip
9589 10:08:20.381381 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
9590 10:08:20.385205 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
9591 10:08:20.385504 arm64_sve-ptrace_Set_SVE_VL_2976 pass
9592 10:08:20.385678 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 skip
9593 10:08:20.385868 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
9594 10:08:20.386024 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
9595 10:08:20.386202 arm64_sve-ptrace_Set_SVE_VL_2992 pass
9596 10:08:20.386355 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 skip
9597 10:08:20.386508 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
9598 10:08:20.386665 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
9599 10:08:20.386855 arm64_sve-ptrace_Set_SVE_VL_3008 pass
9600 10:08:20.386970 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 skip
9601 10:08:20.387079 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
9602 10:08:20.387171 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
9603 10:08:20.387258 arm64_sve-ptrace_Set_SVE_VL_3024 pass
9604 10:08:20.403016 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 skip
9605 10:08:20.403419 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
9606 10:08:20.403509 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
9607 10:08:20.403595 arm64_sve-ptrace_Set_SVE_VL_3040 pass
9608 10:08:20.403698 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 skip
9609 10:08:20.403819 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
9610 10:08:20.403939 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
9611 10:08:20.404032 arm64_sve-ptrace_Set_SVE_VL_3056 pass
9612 10:08:20.404129 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 skip
9613 10:08:20.404228 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
9614 10:08:20.404515 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
9615 10:08:20.404627 arm64_sve-ptrace_Set_SVE_VL_3072 pass
9616 10:08:20.404736 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 skip
9617 10:08:20.404842 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
9618 10:08:20.404936 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
9619 10:08:20.405041 arm64_sve-ptrace_Set_SVE_VL_3088 pass
9620 10:08:20.405134 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 skip
9621 10:08:20.405420 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
9622 10:08:20.405530 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
9623 10:08:20.405619 arm64_sve-ptrace_Set_SVE_VL_3104 pass
9624 10:08:20.405717 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 skip
9625 10:08:20.405821 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
9626 10:08:20.405911 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
9627 10:08:20.405999 arm64_sve-ptrace_Set_SVE_VL_3120 pass
9628 10:08:20.406110 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 skip
9629 10:08:20.406203 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
9630 10:08:20.406291 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
9631 10:08:20.406396 arm64_sve-ptrace_Set_SVE_VL_3136 pass
9632 10:08:20.406504 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 skip
9633 10:08:20.406595 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
9634 10:08:20.406703 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
9635 10:08:20.406793 arm64_sve-ptrace_Set_SVE_VL_3152 pass
9636 10:08:20.406881 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 skip
9637 10:08:20.406981 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
9638 10:08:20.407072 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
9639 10:08:20.407355 arm64_sve-ptrace_Set_SVE_VL_3168 pass
9640 10:08:20.407448 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 skip
9641 10:08:20.407535 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
9642 10:08:20.407637 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
9643 10:08:20.407726 arm64_sve-ptrace_Set_SVE_VL_3184 pass
9644 10:08:20.407830 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 skip
9645 10:08:20.407919 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
9646 10:08:20.408022 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
9647 10:08:20.408127 arm64_sve-ptrace_Set_SVE_VL_3200 pass
9648 10:08:20.408425 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 skip
9649 10:08:20.408517 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
9650 10:08:20.408614 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
9651 10:08:20.408701 arm64_sve-ptrace_Set_SVE_VL_3216 pass
9652 10:08:20.408801 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 skip
9653 10:08:20.409095 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
9654 10:08:20.413326 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
9655 10:08:20.413695 arm64_sve-ptrace_Set_SVE_VL_3232 pass
9656 10:08:20.413799 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 skip
9657 10:08:20.413887 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
9658 10:08:20.413987 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
9659 10:08:20.414276 arm64_sve-ptrace_Set_SVE_VL_3248 pass
9660 10:08:20.414371 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 skip
9661 10:08:20.414454 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
9662 10:08:20.414555 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
9663 10:08:20.414641 arm64_sve-ptrace_Set_SVE_VL_3264 pass
9664 10:08:20.414726 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 skip
9665 10:08:20.414822 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
9666 10:08:20.414905 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
9667 10:08:20.414997 arm64_sve-ptrace_Set_SVE_VL_3280 pass
9668 10:08:20.415090 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 skip
9669 10:08:20.415382 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
9670 10:08:20.415759 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
9671 10:08:20.415856 arm64_sve-ptrace_Set_SVE_VL_3296 pass
9672 10:08:20.415943 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 skip
9673 10:08:20.416249 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
9674 10:08:20.416352 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
9675 10:08:20.416441 arm64_sve-ptrace_Set_SVE_VL_3312 pass
9676 10:08:20.416541 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 skip
9677 10:08:20.416628 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
9678 10:08:20.416728 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
9679 10:08:20.416826 arm64_sve-ptrace_Set_SVE_VL_3328 pass
9680 10:08:20.416911 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 skip
9681 10:08:20.417009 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
9682 10:08:20.421527 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
9683 10:08:20.421756 arm64_sve-ptrace_Set_SVE_VL_3344 pass
9684 10:08:20.421850 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 skip
9685 10:08:20.422186 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
9686 10:08:20.422325 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
9687 10:08:20.422452 arm64_sve-ptrace_Set_SVE_VL_3360 pass
9688 10:08:20.422548 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 skip
9689 10:08:20.422635 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
9690 10:08:20.422740 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
9691 10:08:20.422830 arm64_sve-ptrace_Set_SVE_VL_3376 pass
9692 10:08:20.422916 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 skip
9693 10:08:20.423003 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
9694 10:08:20.423110 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
9695 10:08:20.423197 arm64_sve-ptrace_Set_SVE_VL_3392 pass
9696 10:08:20.423295 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 skip
9697 10:08:20.423400 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
9698 10:08:20.424618 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
9699 10:08:20.424731 arm64_sve-ptrace_Set_SVE_VL_3408 pass
9700 10:08:20.424818 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 skip
9701 10:08:20.424906 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
9702 10:08:20.425009 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
9703 10:08:20.425101 arm64_sve-ptrace_Set_SVE_VL_3424 pass
9704 10:08:20.425185 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 skip
9705 10:08:20.425267 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
9706 10:08:20.425346 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
9707 10:08:20.425425 arm64_sve-ptrace_Set_SVE_VL_3440 pass
9708 10:08:20.425504 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 skip
9709 10:08:20.425587 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
9710 10:08:20.425679 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
9711 10:08:20.425966 arm64_sve-ptrace_Set_SVE_VL_3456 pass
9712 10:08:20.426065 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 skip
9713 10:08:20.426159 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
9714 10:08:20.429546 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
9715 10:08:20.429748 arm64_sve-ptrace_Set_SVE_VL_3472 pass
9716 10:08:20.429850 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 skip
9717 10:08:20.429934 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
9718 10:08:20.430033 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
9719 10:08:20.430124 arm64_sve-ptrace_Set_SVE_VL_3488 pass
9720 10:08:20.430224 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 skip
9721 10:08:20.430522 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
9722 10:08:20.430611 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
9723 10:08:20.430710 arm64_sve-ptrace_Set_SVE_VL_3504 pass
9724 10:08:20.430808 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 skip
9725 10:08:20.431115 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
9726 10:08:20.431205 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
9727 10:08:20.431480 arm64_sve-ptrace_Set_SVE_VL_3520 pass
9728 10:08:20.431566 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 skip
9729 10:08:20.431649 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
9730 10:08:20.431745 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
9731 10:08:20.431830 arm64_sve-ptrace_Set_SVE_VL_3536 pass
9732 10:08:20.431926 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 skip
9733 10:08:20.432218 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
9734 10:08:20.432307 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
9735 10:08:20.432402 arm64_sve-ptrace_Set_SVE_VL_3552 pass
9736 10:08:20.432486 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 skip
9737 10:08:20.432599 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
9738 10:08:20.432704 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
9739 10:08:20.432999 arm64_sve-ptrace_Set_SVE_VL_3568 pass
9740 10:08:20.433103 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 skip
9741 10:08:20.441326 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
9742 10:08:20.441765 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
9743 10:08:20.441859 arm64_sve-ptrace_Set_SVE_VL_3584 pass
9744 10:08:20.441941 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 skip
9745 10:08:20.442041 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
9746 10:08:20.442126 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
9747 10:08:20.442208 arm64_sve-ptrace_Set_SVE_VL_3600 pass
9748 10:08:20.442291 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 skip
9749 10:08:20.442389 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
9750 10:08:20.442474 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
9751 10:08:20.442571 arm64_sve-ptrace_Set_SVE_VL_3616 pass
9752 10:08:20.442667 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 skip
9753 10:08:20.442764 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
9754 10:08:20.443040 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
9755 10:08:20.443128 arm64_sve-ptrace_Set_SVE_VL_3632 pass
9756 10:08:20.443226 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 skip
9757 10:08:20.443500 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
9758 10:08:20.443588 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
9759 10:08:20.443671 arm64_sve-ptrace_Set_SVE_VL_3648 pass
9760 10:08:20.443767 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 skip
9761 10:08:20.444050 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
9762 10:08:20.444147 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
9763 10:08:20.444230 arm64_sve-ptrace_Set_SVE_VL_3664 pass
9764 10:08:20.458591 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 skip
9765 10:08:20.458845 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
9766 10:08:20.459156 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
9767 10:08:20.459258 arm64_sve-ptrace_Set_SVE_VL_3680 pass
9768 10:08:20.459351 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 skip
9769 10:08:20.459443 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
9770 10:08:20.459535 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
9771 10:08:20.459628 arm64_sve-ptrace_Set_SVE_VL_3696 pass
9772 10:08:20.459736 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 skip
9773 10:08:20.459829 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
9774 10:08:20.459920 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
9775 10:08:20.460010 arm64_sve-ptrace_Set_SVE_VL_3712 pass
9776 10:08:20.460101 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 skip
9777 10:08:20.460191 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
9778 10:08:20.460301 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
9779 10:08:20.460393 arm64_sve-ptrace_Set_SVE_VL_3728 pass
9780 10:08:20.460484 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 skip
9781 10:08:20.460574 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
9782 10:08:20.460670 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
9783 10:08:20.460779 arm64_sve-ptrace_Set_SVE_VL_3744 pass
9784 10:08:20.460871 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 skip
9785 10:08:20.460962 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
9786 10:08:20.461053 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
9787 10:08:20.461143 arm64_sve-ptrace_Set_SVE_VL_3760 pass
9788 10:08:20.461250 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 skip
9789 10:08:20.465327 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
9790 10:08:20.465716 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
9791 10:08:20.465826 arm64_sve-ptrace_Set_SVE_VL_3776 pass
9792 10:08:20.465924 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 skip
9793 10:08:20.466019 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
9794 10:08:20.466130 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
9795 10:08:20.466235 arm64_sve-ptrace_Set_SVE_VL_3792 pass
9796 10:08:20.466330 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 skip
9797 10:08:20.466424 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
9798 10:08:20.466535 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
9799 10:08:20.466630 arm64_sve-ptrace_Set_SVE_VL_3808 pass
9800 10:08:20.466742 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 skip
9801 10:08:20.466838 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
9802 10:08:20.466931 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
9803 10:08:20.467043 arm64_sve-ptrace_Set_SVE_VL_3824 pass
9804 10:08:20.467139 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 skip
9805 10:08:20.467253 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
9806 10:08:20.467349 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
9807 10:08:20.467460 arm64_sve-ptrace_Set_SVE_VL_3840 pass
9808 10:08:20.467556 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 skip
9809 10:08:20.467665 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
9810 10:08:20.467774 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
9811 10:08:20.467894 arm64_sve-ptrace_Set_SVE_VL_3856 pass
9812 10:08:20.467981 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 skip
9813 10:08:20.468095 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
9814 10:08:20.468202 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
9815 10:08:20.468295 arm64_sve-ptrace_Set_SVE_VL_3872 pass
9816 10:08:20.468565 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 skip
9817 10:08:20.468687 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
9818 10:08:20.468778 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
9819 10:08:20.468885 arm64_sve-ptrace_Set_SVE_VL_3888 pass
9820 10:08:20.468987 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 skip
9821 10:08:20.469074 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
9822 10:08:20.473232 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
9823 10:08:20.473563 arm64_sve-ptrace_Set_SVE_VL_3904 pass
9824 10:08:20.473653 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 skip
9825 10:08:20.473726 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
9826 10:08:20.473817 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
9827 10:08:20.473887 arm64_sve-ptrace_Set_SVE_VL_3920 pass
9828 10:08:20.473964 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 skip
9829 10:08:20.474040 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
9830 10:08:20.474119 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
9831 10:08:20.474381 arm64_sve-ptrace_Set_SVE_VL_3936 pass
9832 10:08:20.474464 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 skip
9833 10:08:20.474542 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
9834 10:08:20.474609 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
9835 10:08:20.474673 arm64_sve-ptrace_Set_SVE_VL_3952 pass
9836 10:08:20.474747 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 skip
9837 10:08:20.474811 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
9838 10:08:20.475063 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
9839 10:08:20.475134 arm64_sve-ptrace_Set_SVE_VL_3968 pass
9840 10:08:20.475204 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 skip
9841 10:08:20.475292 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
9842 10:08:20.475369 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
9843 10:08:20.475484 arm64_sve-ptrace_Set_SVE_VL_3984 pass
9844 10:08:20.475592 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 skip
9845 10:08:20.475689 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
9846 10:08:20.475977 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
9847 10:08:20.476075 arm64_sve-ptrace_Set_SVE_VL_4000 pass
9848 10:08:20.476167 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 skip
9849 10:08:20.476263 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
9850 10:08:20.476552 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
9851 10:08:20.476656 arm64_sve-ptrace_Set_SVE_VL_4016 pass
9852 10:08:20.476725 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 skip
9853 10:08:20.476804 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
9854 10:08:20.476893 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
9855 10:08:20.476982 arm64_sve-ptrace_Set_SVE_VL_4032 pass
9856 10:08:20.481252 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 skip
9857 10:08:20.481639 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
9858 10:08:20.481736 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
9859 10:08:20.481840 arm64_sve-ptrace_Set_SVE_VL_4048 pass
9860 10:08:20.481958 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 skip
9861 10:08:20.482078 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
9862 10:08:20.482174 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
9863 10:08:20.482276 arm64_sve-ptrace_Set_SVE_VL_4064 pass
9864 10:08:20.482580 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 skip
9865 10:08:20.482667 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
9866 10:08:20.482756 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
9867 10:08:20.482833 arm64_sve-ptrace_Set_SVE_VL_4080 pass
9868 10:08:20.482924 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 skip
9869 10:08:20.482995 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
9870 10:08:20.483069 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
9871 10:08:20.483172 arm64_sve-ptrace_Set_SVE_VL_4096 pass
9872 10:08:20.483262 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 skip
9873 10:08:20.483352 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
9874 10:08:20.483443 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
9875 10:08:20.483516 arm64_sve-ptrace_Set_SVE_VL_4112 pass
9876 10:08:20.483605 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 skip
9877 10:08:20.483714 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
9878 10:08:20.483786 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
9879 10:08:20.483861 arm64_sve-ptrace_Set_SVE_VL_4128 pass
9880 10:08:20.483957 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 skip
9881 10:08:20.484034 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
9882 10:08:20.484111 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
9883 10:08:20.484183 arm64_sve-ptrace_Set_SVE_VL_4144 pass
9884 10:08:20.484256 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 skip
9885 10:08:20.484515 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
9886 10:08:20.484608 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
9887 10:08:20.484713 arm64_sve-ptrace_Set_SVE_VL_4160 pass
9888 10:08:20.484814 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 skip
9889 10:08:20.484885 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
9890 10:08:20.484976 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
9891 10:08:20.485094 arm64_sve-ptrace_Set_SVE_VL_4176 pass
9892 10:08:20.485184 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 skip
9893 10:08:20.489403 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
9894 10:08:20.489552 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
9895 10:08:20.489640 arm64_sve-ptrace_Set_SVE_VL_4192 pass
9896 10:08:20.489739 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 skip
9897 10:08:20.489826 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
9898 10:08:20.489897 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
9899 10:08:20.489987 arm64_sve-ptrace_Set_SVE_VL_4208 pass
9900 10:08:20.490058 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 skip
9901 10:08:20.490158 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
9902 10:08:20.490232 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
9903 10:08:20.490322 arm64_sve-ptrace_Set_SVE_VL_4224 pass
9904 10:08:20.490409 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 skip
9905 10:08:20.490495 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
9906 10:08:20.490591 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
9907 10:08:20.490670 arm64_sve-ptrace_Set_SVE_VL_4240 pass
9908 10:08:20.490762 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 skip
9909 10:08:20.491045 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
9910 10:08:20.491139 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
9911 10:08:20.491217 arm64_sve-ptrace_Set_SVE_VL_4256 pass
9912 10:08:20.491302 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 skip
9913 10:08:20.491369 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
9914 10:08:20.491443 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
9915 10:08:20.491702 arm64_sve-ptrace_Set_SVE_VL_4272 pass
9916 10:08:20.491785 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 skip
9917 10:08:20.491863 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
9918 10:08:20.491929 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
9919 10:08:20.492003 arm64_sve-ptrace_Set_SVE_VL_4288 pass
9920 10:08:20.492078 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 skip
9921 10:08:20.492154 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
9922 10:08:20.492417 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
9923 10:08:20.492498 arm64_sve-ptrace_Set_SVE_VL_4304 pass
9924 10:08:20.509136 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 skip
9925 10:08:20.509666 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
9926 10:08:20.509848 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
9927 10:08:20.510019 arm64_sve-ptrace_Set_SVE_VL_4320 pass
9928 10:08:20.510173 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 skip
9929 10:08:20.510403 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
9930 10:08:20.510584 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
9931 10:08:20.510796 arm64_sve-ptrace_Set_SVE_VL_4336 pass
9932 10:08:20.510999 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 skip
9933 10:08:20.511230 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
9934 10:08:20.511428 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
9935 10:08:20.511634 arm64_sve-ptrace_Set_SVE_VL_4352 pass
9936 10:08:20.511858 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 skip
9937 10:08:20.512066 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
9938 10:08:20.512316 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
9939 10:08:20.512506 arm64_sve-ptrace_Set_SVE_VL_4368 pass
9940 10:08:20.512650 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 skip
9941 10:08:20.512846 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
9942 10:08:20.513036 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
9943 10:08:20.513214 arm64_sve-ptrace_Set_SVE_VL_4384 pass
9944 10:08:20.513364 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 skip
9945 10:08:20.513545 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
9946 10:08:20.513696 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
9947 10:08:20.513843 arm64_sve-ptrace_Set_SVE_VL_4400 pass
9948 10:08:20.513986 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 skip
9949 10:08:20.514130 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
9950 10:08:20.517206 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
9951 10:08:20.517633 arm64_sve-ptrace_Set_SVE_VL_4416 pass
9952 10:08:20.517843 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 skip
9953 10:08:20.518010 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
9954 10:08:20.518207 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
9955 10:08:20.518376 arm64_sve-ptrace_Set_SVE_VL_4432 pass
9956 10:08:20.518533 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 skip
9957 10:08:20.518682 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
9958 10:08:20.518818 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
9959 10:08:20.518977 arm64_sve-ptrace_Set_SVE_VL_4448 pass
9960 10:08:20.519125 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 skip
9961 10:08:20.519260 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
9962 10:08:20.519385 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
9963 10:08:20.519529 arm64_sve-ptrace_Set_SVE_VL_4464 pass
9964 10:08:20.519671 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 skip
9965 10:08:20.519880 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
9966 10:08:20.520082 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
9967 10:08:20.520306 arm64_sve-ptrace_Set_SVE_VL_4480 pass
9968 10:08:20.520522 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 skip
9969 10:08:20.520738 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
9970 10:08:20.520927 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
9971 10:08:20.521091 arm64_sve-ptrace_Set_SVE_VL_4496 pass
9972 10:08:20.521213 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 skip
9973 10:08:20.521356 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
9974 10:08:20.521477 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
9975 10:08:20.521591 arm64_sve-ptrace_Set_SVE_VL_4512 pass
9976 10:08:20.521793 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 skip
9977 10:08:20.521991 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
9978 10:08:20.522173 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
9979 10:08:20.522354 arm64_sve-ptrace_Set_SVE_VL_4528 pass
9980 10:08:20.522534 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 skip
9981 10:08:20.522719 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
9982 10:08:20.525238 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
9983 10:08:20.525714 arm64_sve-ptrace_Set_SVE_VL_4544 pass
9984 10:08:20.525925 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 skip
9985 10:08:20.526110 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
9986 10:08:20.526312 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
9987 10:08:20.526481 arm64_sve-ptrace_Set_SVE_VL_4560 pass
9988 10:08:20.526638 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 skip
9989 10:08:20.526792 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
9990 10:08:20.526945 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
9991 10:08:20.527104 arm64_sve-ptrace_Set_SVE_VL_4576 pass
9992 10:08:20.527301 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 skip
9993 10:08:20.527475 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
9994 10:08:20.527635 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
9995 10:08:20.527784 arm64_sve-ptrace_Set_SVE_VL_4592 pass
9996 10:08:20.527936 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 skip
9997 10:08:20.528075 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
9998 10:08:20.528227 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
9999 10:08:20.528391 arm64_sve-ptrace_Set_SVE_VL_4608 pass
10000 10:08:20.528585 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 skip
10001 10:08:20.528786 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
10002 10:08:20.528982 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
10003 10:08:20.529112 arm64_sve-ptrace_Set_SVE_VL_4624 pass
10004 10:08:20.529227 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 skip
10005 10:08:20.529342 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
10006 10:08:20.529454 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
10007 10:08:20.529566 arm64_sve-ptrace_Set_SVE_VL_4640 pass
10008 10:08:20.529740 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 skip
10009 10:08:20.529945 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
10010 10:08:20.530128 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
10011 10:08:20.530353 arm64_sve-ptrace_Set_SVE_VL_4656 pass
10012 10:08:20.530540 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 skip
10013 10:08:20.530718 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
10014 10:08:20.533215 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
10015 10:08:20.533637 arm64_sve-ptrace_Set_SVE_VL_4672 pass
10016 10:08:20.533831 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 skip
10017 10:08:20.534020 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
10018 10:08:20.534263 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
10019 10:08:20.534418 arm64_sve-ptrace_Set_SVE_VL_4688 pass
10020 10:08:20.534561 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 skip
10021 10:08:20.534686 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
10022 10:08:20.534812 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
10023 10:08:20.534965 arm64_sve-ptrace_Set_SVE_VL_4704 pass
10024 10:08:20.535093 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 skip
10025 10:08:20.535218 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
10026 10:08:20.535341 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
10027 10:08:20.535465 arm64_sve-ptrace_Set_SVE_VL_4720 pass
10028 10:08:20.535615 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 skip
10029 10:08:20.535746 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
10030 10:08:20.535875 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
10031 10:08:20.536002 arm64_sve-ptrace_Set_SVE_VL_4736 pass
10032 10:08:20.536124 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 skip
10033 10:08:20.536251 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
10034 10:08:20.536373 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
10035 10:08:20.536527 arm64_sve-ptrace_Set_SVE_VL_4752 pass
10036 10:08:20.536663 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 skip
10037 10:08:20.536792 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
10038 10:08:20.536918 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
10039 10:08:20.537044 arm64_sve-ptrace_Set_SVE_VL_4768 pass
10040 10:08:20.537161 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 skip
10041 10:08:20.537280 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
10042 10:08:20.537396 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
10043 10:08:20.537537 arm64_sve-ptrace_Set_SVE_VL_4784 pass
10044 10:08:20.537668 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 skip
10045 10:08:20.537789 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
10046 10:08:20.541188 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
10047 10:08:20.541536 arm64_sve-ptrace_Set_SVE_VL_4800 pass
10048 10:08:20.541642 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 skip
10049 10:08:20.541743 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
10050 10:08:20.541848 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
10051 10:08:20.541938 arm64_sve-ptrace_Set_SVE_VL_4816 pass
10052 10:08:20.542025 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 skip
10053 10:08:20.542131 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
10054 10:08:20.542230 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
10055 10:08:20.542320 arm64_sve-ptrace_Set_SVE_VL_4832 pass
10056 10:08:20.542423 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 skip
10057 10:08:20.542526 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
10058 10:08:20.542631 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
10059 10:08:20.542733 arm64_sve-ptrace_Set_SVE_VL_4848 pass
10060 10:08:20.542831 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 skip
10061 10:08:20.542932 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
10062 10:08:20.543035 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
10063 10:08:20.543137 arm64_sve-ptrace_Set_SVE_VL_4864 pass
10064 10:08:20.543241 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 skip
10065 10:08:20.543541 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
10066 10:08:20.543648 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
10067 10:08:20.543753 arm64_sve-ptrace_Set_SVE_VL_4880 pass
10068 10:08:20.543856 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 skip
10069 10:08:20.543945 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
10070 10:08:20.544240 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
10071 10:08:20.544354 arm64_sve-ptrace_Set_SVE_VL_4896 pass
10072 10:08:20.544444 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 skip
10073 10:08:20.544536 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
10074 10:08:20.544724 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
10075 10:08:20.544897 arm64_sve-ptrace_Set_SVE_VL_4912 pass
10076 10:08:20.544990 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 skip
10077 10:08:20.545093 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
10078 10:08:20.545186 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
10079 10:08:20.549185 arm64_sve-ptrace_Set_SVE_VL_4928 pass
10080 10:08:20.549523 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 skip
10081 10:08:20.549630 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
10082 10:08:20.549745 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
10083 10:08:20.549837 arm64_sve-ptrace_Set_SVE_VL_4944 pass
10084 10:08:20.561684 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 skip
10085 10:08:20.562105 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
10086 10:08:20.562215 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
10087 10:08:20.562305 arm64_sve-ptrace_Set_SVE_VL_4960 pass
10088 10:08:20.562401 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 skip
10089 10:08:20.562504 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
10090 10:08:20.562590 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
10091 10:08:20.562692 arm64_sve-ptrace_Set_SVE_VL_4976 pass
10092 10:08:20.562781 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 skip
10093 10:08:20.562880 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
10094 10:08:20.562982 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
10095 10:08:20.563082 arm64_sve-ptrace_Set_SVE_VL_4992 pass
10096 10:08:20.563376 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 skip
10097 10:08:20.563486 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
10098 10:08:20.563578 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
10099 10:08:20.563684 arm64_sve-ptrace_Set_SVE_VL_5008 pass
10100 10:08:20.563777 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 skip
10101 10:08:20.563880 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
10102 10:08:20.563970 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
10103 10:08:20.564076 arm64_sve-ptrace_Set_SVE_VL_5024 pass
10104 10:08:20.564179 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 skip
10105 10:08:20.564269 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
10106 10:08:20.564378 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
10107 10:08:20.564468 arm64_sve-ptrace_Set_SVE_VL_5040 pass
10108 10:08:20.564571 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 skip
10109 10:08:20.564666 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
10110 10:08:20.564779 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
10111 10:08:20.564887 arm64_sve-ptrace_Set_SVE_VL_5056 pass
10112 10:08:20.564992 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 skip
10113 10:08:20.569216 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
10114 10:08:20.569564 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
10115 10:08:20.569671 arm64_sve-ptrace_Set_SVE_VL_5072 pass
10116 10:08:20.569753 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 skip
10117 10:08:20.569856 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
10118 10:08:20.569949 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
10119 10:08:20.570034 arm64_sve-ptrace_Set_SVE_VL_5088 pass
10120 10:08:20.570132 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 skip
10121 10:08:20.570236 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
10122 10:08:20.570324 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
10123 10:08:20.570425 arm64_sve-ptrace_Set_SVE_VL_5104 pass
10124 10:08:20.570521 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 skip
10125 10:08:20.570619 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
10126 10:08:20.570719 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
10127 10:08:20.570821 arm64_sve-ptrace_Set_SVE_VL_5120 pass
10128 10:08:20.571120 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 skip
10129 10:08:20.571221 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
10130 10:08:20.571315 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
10131 10:08:20.571414 arm64_sve-ptrace_Set_SVE_VL_5136 pass
10132 10:08:20.571729 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 skip
10133 10:08:20.571835 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
10134 10:08:20.571937 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
10135 10:08:20.572023 arm64_sve-ptrace_Set_SVE_VL_5152 pass
10136 10:08:20.572124 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 skip
10137 10:08:20.572229 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
10138 10:08:20.572527 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
10139 10:08:20.572637 arm64_sve-ptrace_Set_SVE_VL_5168 pass
10140 10:08:20.572947 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 skip
10141 10:08:20.573050 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
10142 10:08:20.573136 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
10143 10:08:20.573233 arm64_sve-ptrace_Set_SVE_VL_5184 pass
10144 10:08:20.577433 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 skip
10145 10:08:20.577586 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
10146 10:08:20.577706 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
10147 10:08:20.577798 arm64_sve-ptrace_Set_SVE_VL_5200 pass
10148 10:08:20.578099 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 skip
10149 10:08:20.578205 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
10150 10:08:20.578296 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
10151 10:08:20.578402 arm64_sve-ptrace_Set_SVE_VL_5216 pass
10152 10:08:20.578493 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 skip
10153 10:08:20.578599 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
10154 10:08:20.578707 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
10155 10:08:20.578797 arm64_sve-ptrace_Set_SVE_VL_5232 pass
10156 10:08:20.578903 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 skip
10157 10:08:20.579011 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
10158 10:08:20.579322 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
10159 10:08:20.579427 arm64_sve-ptrace_Set_SVE_VL_5248 pass
10160 10:08:20.579529 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 skip
10161 10:08:20.579821 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
10162 10:08:20.579926 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
10163 10:08:20.580032 arm64_sve-ptrace_Set_SVE_VL_5264 pass
10164 10:08:20.580123 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 skip
10165 10:08:20.580227 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
10166 10:08:20.580316 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
10167 10:08:20.580425 arm64_sve-ptrace_Set_SVE_VL_5280 pass
10168 10:08:20.580511 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 skip
10169 10:08:20.580797 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
10170 10:08:20.580901 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
10171 10:08:20.581004 arm64_sve-ptrace_Set_SVE_VL_5296 pass
10172 10:08:20.581092 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 skip
10173 10:08:20.585420 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
10174 10:08:20.585576 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
10175 10:08:20.585677 arm64_sve-ptrace_Set_SVE_VL_5312 pass
10176 10:08:20.585779 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 skip
10177 10:08:20.585865 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
10178 10:08:20.585964 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
10179 10:08:20.586257 arm64_sve-ptrace_Set_SVE_VL_5328 pass
10180 10:08:20.586361 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 skip
10181 10:08:20.586444 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
10182 10:08:20.586540 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
10183 10:08:20.586626 arm64_sve-ptrace_Set_SVE_VL_5344 pass
10184 10:08:20.586712 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 skip
10185 10:08:20.586812 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
10186 10:08:20.586897 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
10187 10:08:20.586994 arm64_sve-ptrace_Set_SVE_VL_5360 pass
10188 10:08:20.587078 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 skip
10189 10:08:20.587178 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
10190 10:08:20.587278 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
10191 10:08:20.587364 arm64_sve-ptrace_Set_SVE_VL_5376 pass
10192 10:08:20.587466 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 skip
10193 10:08:20.587569 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
10194 10:08:20.587673 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
10195 10:08:20.587763 arm64_sve-ptrace_Set_SVE_VL_5392 pass
10196 10:08:20.588121 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 skip
10197 10:08:20.588300 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
10198 10:08:20.588530 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
10199 10:08:20.588806 arm64_sve-ptrace_Set_SVE_VL_5408 pass
10200 10:08:20.589018 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 skip
10201 10:08:20.589197 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
10202 10:08:20.589329 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
10203 10:08:20.589448 arm64_sve-ptrace_Set_SVE_VL_5424 pass
10204 10:08:20.589591 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 skip
10205 10:08:20.589729 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
10206 10:08:20.593228 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
10207 10:08:20.593555 arm64_sve-ptrace_Set_SVE_VL_5440 pass
10208 10:08:20.593667 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 skip
10209 10:08:20.593771 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
10210 10:08:20.593857 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
10211 10:08:20.593956 arm64_sve-ptrace_Set_SVE_VL_5456 pass
10212 10:08:20.594054 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 skip
10213 10:08:20.594153 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
10214 10:08:20.594261 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
10215 10:08:20.594397 arm64_sve-ptrace_Set_SVE_VL_5472 pass
10216 10:08:20.594782 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 skip
10217 10:08:20.594888 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
10218 10:08:20.594987 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
10219 10:08:20.595285 arm64_sve-ptrace_Set_SVE_VL_5488 pass
10220 10:08:20.595388 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 skip
10221 10:08:20.595493 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
10222 10:08:20.595591 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
10223 10:08:20.595686 arm64_sve-ptrace_Set_SVE_VL_5504 pass
10224 10:08:20.595791 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 skip
10225 10:08:20.596091 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
10226 10:08:20.596207 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
10227 10:08:20.596308 arm64_sve-ptrace_Set_SVE_VL_5520 pass
10228 10:08:20.596635 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 skip
10229 10:08:20.596741 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
10230 10:08:20.596839 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
10231 10:08:20.596941 arm64_sve-ptrace_Set_SVE_VL_5536 pass
10232 10:08:20.601364 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 skip
10233 10:08:20.601541 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
10234 10:08:20.601835 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
10235 10:08:20.601940 arm64_sve-ptrace_Set_SVE_VL_5552 pass
10236 10:08:20.602028 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 skip
10237 10:08:20.602131 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
10238 10:08:20.602222 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
10239 10:08:20.602307 arm64_sve-ptrace_Set_SVE_VL_5568 pass
10240 10:08:20.602408 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 skip
10241 10:08:20.602495 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
10242 10:08:20.602595 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
10243 10:08:20.602696 arm64_sve-ptrace_Set_SVE_VL_5584 pass
10244 10:08:20.614800 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 skip
10245 10:08:20.615208 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
10246 10:08:20.615310 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
10247 10:08:20.615399 arm64_sve-ptrace_Set_SVE_VL_5600 pass
10248 10:08:20.615507 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 skip
10249 10:08:20.615592 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
10250 10:08:20.615675 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
10251 10:08:20.615774 arm64_sve-ptrace_Set_SVE_VL_5616 pass
10252 10:08:20.615862 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 skip
10253 10:08:20.615947 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
10254 10:08:20.616048 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
10255 10:08:20.616134 arm64_sve-ptrace_Set_SVE_VL_5632 pass
10256 10:08:20.616216 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 skip
10257 10:08:20.616315 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
10258 10:08:20.616403 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
10259 10:08:20.616495 arm64_sve-ptrace_Set_SVE_VL_5648 pass
10260 10:08:20.616597 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 skip
10261 10:08:20.616687 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
10262 10:08:20.616788 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
10263 10:08:20.616893 arm64_sve-ptrace_Set_SVE_VL_5664 pass
10264 10:08:20.616996 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 skip
10265 10:08:20.617325 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
10266 10:08:20.617495 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
10267 10:08:20.617716 arm64_sve-ptrace_Set_SVE_VL_5680 pass
10268 10:08:20.617862 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 skip
10269 10:08:20.618038 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
10270 10:08:20.618176 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
10271 10:08:20.618319 arm64_sve-ptrace_Set_SVE_VL_5696 pass
10272 10:08:20.618462 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 skip
10273 10:08:20.618639 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
10274 10:08:20.618823 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
10275 10:08:20.619042 arm64_sve-ptrace_Set_SVE_VL_5712 pass
10276 10:08:20.619256 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 skip
10277 10:08:20.619430 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
10278 10:08:20.619578 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
10279 10:08:20.619760 arm64_sve-ptrace_Set_SVE_VL_5728 pass
10280 10:08:20.619898 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 skip
10281 10:08:20.620043 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
10282 10:08:20.620192 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
10283 10:08:20.620353 arm64_sve-ptrace_Set_SVE_VL_5744 pass
10284 10:08:20.620571 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 skip
10285 10:08:20.620723 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
10286 10:08:20.620866 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
10287 10:08:20.621013 arm64_sve-ptrace_Set_SVE_VL_5760 pass
10288 10:08:20.621154 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 skip
10289 10:08:20.621338 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
10290 10:08:20.621474 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
10291 10:08:20.621617 arm64_sve-ptrace_Set_SVE_VL_5776 pass
10292 10:08:20.621770 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 skip
10293 10:08:20.621913 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
10294 10:08:20.622054 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
10295 10:08:20.622196 arm64_sve-ptrace_Set_SVE_VL_5792 pass
10296 10:08:20.622338 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 skip
10297 10:08:20.622481 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
10298 10:08:20.622621 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
10299 10:08:20.622761 arm64_sve-ptrace_Set_SVE_VL_5808 pass
10300 10:08:20.622901 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 skip
10301 10:08:20.623043 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
10302 10:08:20.625237 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
10303 10:08:20.625656 arm64_sve-ptrace_Set_SVE_VL_5824 pass
10304 10:08:20.625762 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 skip
10305 10:08:20.625848 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
10306 10:08:20.625933 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
10307 10:08:20.626038 arm64_sve-ptrace_Set_SVE_VL_5840 pass
10308 10:08:20.626132 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 skip
10309 10:08:20.626219 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
10310 10:08:20.626323 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
10311 10:08:20.626412 arm64_sve-ptrace_Set_SVE_VL_5856 pass
10312 10:08:20.626501 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 skip
10313 10:08:20.626606 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
10314 10:08:20.626695 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
10315 10:08:20.626799 arm64_sve-ptrace_Set_SVE_VL_5872 pass
10316 10:08:20.626888 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 skip
10317 10:08:20.626991 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
10318 10:08:20.627094 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
10319 10:08:20.627183 arm64_sve-ptrace_Set_SVE_VL_5888 pass
10320 10:08:20.627285 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 skip
10321 10:08:20.627684 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
10322 10:08:20.627791 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
10323 10:08:20.627900 arm64_sve-ptrace_Set_SVE_VL_5904 pass
10324 10:08:20.627991 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 skip
10325 10:08:20.628094 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
10326 10:08:20.628184 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
10327 10:08:20.628286 arm64_sve-ptrace_Set_SVE_VL_5920 pass
10328 10:08:20.628390 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 skip
10329 10:08:20.628495 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
10330 10:08:20.628598 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
10331 10:08:20.628701 arm64_sve-ptrace_Set_SVE_VL_5936 pass
10332 10:08:20.629025 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 skip
10333 10:08:20.633273 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
10334 10:08:20.633725 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
10335 10:08:20.633911 arm64_sve-ptrace_Set_SVE_VL_5952 pass
10336 10:08:20.634075 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 skip
10337 10:08:20.634252 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
10338 10:08:20.634415 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
10339 10:08:20.634616 arm64_sve-ptrace_Set_SVE_VL_5968 pass
10340 10:08:20.634772 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 skip
10341 10:08:20.634903 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
10342 10:08:20.635071 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
10343 10:08:20.635219 arm64_sve-ptrace_Set_SVE_VL_5984 pass
10344 10:08:20.635392 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 skip
10345 10:08:20.635587 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
10346 10:08:20.635874 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
10347 10:08:20.636060 arm64_sve-ptrace_Set_SVE_VL_6000 pass
10348 10:08:20.636233 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 skip
10349 10:08:20.636395 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
10350 10:08:20.636544 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
10351 10:08:20.636698 arm64_sve-ptrace_Set_SVE_VL_6016 pass
10352 10:08:20.636912 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 skip
10353 10:08:20.637115 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
10354 10:08:20.637254 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
10355 10:08:20.637369 arm64_sve-ptrace_Set_SVE_VL_6032 pass
10356 10:08:20.637483 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 skip
10357 10:08:20.637628 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
10358 10:08:20.637858 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
10359 10:08:20.638050 arm64_sve-ptrace_Set_SVE_VL_6048 pass
10360 10:08:20.638230 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 skip
10361 10:08:20.638411 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
10362 10:08:20.638587 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
10363 10:08:20.638732 arm64_sve-ptrace_Set_SVE_VL_6064 pass
10364 10:08:20.638874 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 skip
10365 10:08:20.645225 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
10366 10:08:20.645615 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
10367 10:08:20.645730 arm64_sve-ptrace_Set_SVE_VL_6080 pass
10368 10:08:20.645820 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 skip
10369 10:08:20.646133 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
10370 10:08:20.646236 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
10371 10:08:20.646322 arm64_sve-ptrace_Set_SVE_VL_6096 pass
10372 10:08:20.646405 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 skip
10373 10:08:20.646486 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
10374 10:08:20.646593 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
10375 10:08:20.646681 arm64_sve-ptrace_Set_SVE_VL_6112 pass
10376 10:08:20.646766 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 skip
10377 10:08:20.646868 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
10378 10:08:20.646957 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
10379 10:08:20.647040 arm64_sve-ptrace_Set_SVE_VL_6128 pass
10380 10:08:20.647138 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 skip
10381 10:08:20.647242 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
10382 10:08:20.647330 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
10383 10:08:20.647437 arm64_sve-ptrace_Set_SVE_VL_6144 pass
10384 10:08:20.647528 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 skip
10385 10:08:20.647634 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
10386 10:08:20.647956 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
10387 10:08:20.648061 arm64_sve-ptrace_Set_SVE_VL_6160 pass
10388 10:08:20.648389 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 skip
10389 10:08:20.648497 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
10390 10:08:20.648587 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
10391 10:08:20.648814 arm64_sve-ptrace_Set_SVE_VL_6176 pass
10392 10:08:20.649169 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 skip
10393 10:08:20.649272 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
10394 10:08:20.649358 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
10395 10:08:20.649442 arm64_sve-ptrace_Set_SVE_VL_6192 pass
10396 10:08:20.653370 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 skip
10397 10:08:20.653502 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
10398 10:08:20.653837 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
10399 10:08:20.654039 arm64_sve-ptrace_Set_SVE_VL_6208 pass
10400 10:08:20.654201 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 skip
10401 10:08:20.654362 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
10402 10:08:20.654486 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
10403 10:08:20.654602 arm64_sve-ptrace_Set_SVE_VL_6224 pass
10404 10:08:20.666583 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 skip
10405 10:08:20.667025 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
10406 10:08:20.667133 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
10407 10:08:20.667227 arm64_sve-ptrace_Set_SVE_VL_6240 pass
10408 10:08:20.667330 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 skip
10409 10:08:20.667419 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
10410 10:08:20.667508 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
10411 10:08:20.667614 arm64_sve-ptrace_Set_SVE_VL_6256 pass
10412 10:08:20.667698 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 skip
10413 10:08:20.667795 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
10414 10:08:20.667882 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
10415 10:08:20.667980 arm64_sve-ptrace_Set_SVE_VL_6272 pass
10416 10:08:20.668080 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 skip
10417 10:08:20.668179 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
10418 10:08:20.668276 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
10419 10:08:20.668426 arm64_sve-ptrace_Set_SVE_VL_6288 pass
10420 10:08:20.668650 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 skip
10421 10:08:20.669042 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
10422 10:08:20.669229 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
10423 10:08:20.669392 arm64_sve-ptrace_Set_SVE_VL_6304 pass
10424 10:08:20.669540 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 skip
10425 10:08:20.669716 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
10426 10:08:20.669869 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
10427 10:08:20.670008 arm64_sve-ptrace_Set_SVE_VL_6320 pass
10428 10:08:20.670140 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 skip
10429 10:08:20.670271 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
10430 10:08:20.670427 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
10431 10:08:20.670629 arm64_sve-ptrace_Set_SVE_VL_6336 pass
10432 10:08:20.670787 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 skip
10433 10:08:20.670944 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
10434 10:08:20.671085 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
10435 10:08:20.671224 arm64_sve-ptrace_Set_SVE_VL_6352 pass
10436 10:08:20.671361 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 skip
10437 10:08:20.671501 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
10438 10:08:20.671641 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
10439 10:08:20.671779 arm64_sve-ptrace_Set_SVE_VL_6368 pass
10440 10:08:20.671958 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 skip
10441 10:08:20.672120 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
10442 10:08:20.672276 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
10443 10:08:20.672430 arm64_sve-ptrace_Set_SVE_VL_6384 pass
10444 10:08:20.672576 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 skip
10445 10:08:20.672734 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
10446 10:08:20.672894 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
10447 10:08:20.673066 arm64_sve-ptrace_Set_SVE_VL_6400 pass
10448 10:08:20.673188 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 skip
10449 10:08:20.673303 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
10450 10:08:20.673415 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
10451 10:08:20.673528 arm64_sve-ptrace_Set_SVE_VL_6416 pass
10452 10:08:20.673678 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 skip
10453 10:08:20.673802 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
10454 10:08:20.673916 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
10455 10:08:20.674034 arm64_sve-ptrace_Set_SVE_VL_6432 pass
10456 10:08:20.674148 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 skip
10457 10:08:20.674262 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
10458 10:08:20.674377 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
10459 10:08:20.674704 arm64_sve-ptrace_Set_SVE_VL_6448 pass
10460 10:08:20.674831 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 skip
10461 10:08:20.674948 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
10462 10:08:20.675065 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
10463 10:08:20.675180 arm64_sve-ptrace_Set_SVE_VL_6464 pass
10464 10:08:20.677473 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 skip
10465 10:08:20.677591 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
10466 10:08:20.677702 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
10467 10:08:20.677805 arm64_sve-ptrace_Set_SVE_VL_6480 pass
10468 10:08:20.677904 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 skip
10469 10:08:20.678200 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
10470 10:08:20.678302 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
10471 10:08:20.678403 arm64_sve-ptrace_Set_SVE_VL_6496 pass
10472 10:08:20.678501 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 skip
10473 10:08:20.678785 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
10474 10:08:20.678898 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
10475 10:08:20.678984 arm64_sve-ptrace_Set_SVE_VL_6512 pass
10476 10:08:20.679079 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 skip
10477 10:08:20.679176 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
10478 10:08:20.679549 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
10479 10:08:20.679656 arm64_sve-ptrace_Set_SVE_VL_6528 pass
10480 10:08:20.679755 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 skip
10481 10:08:20.680079 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
10482 10:08:20.680314 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
10483 10:08:20.680583 arm64_sve-ptrace_Set_SVE_VL_6544 pass
10484 10:08:20.680829 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 skip
10485 10:08:20.681016 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
10486 10:08:20.681181 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
10487 10:08:20.681307 arm64_sve-ptrace_Set_SVE_VL_6560 pass
10488 10:08:20.681422 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 skip
10489 10:08:20.681564 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
10490 10:08:20.689227 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
10491 10:08:20.689479 arm64_sve-ptrace_Set_SVE_VL_6576 pass
10492 10:08:20.689919 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 skip
10493 10:08:20.690122 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
10494 10:08:20.690271 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
10495 10:08:20.690433 arm64_sve-ptrace_Set_SVE_VL_6592 pass
10496 10:08:20.690590 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 skip
10497 10:08:20.690765 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
10498 10:08:20.690911 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
10499 10:08:20.691072 arm64_sve-ptrace_Set_SVE_VL_6608 pass
10500 10:08:20.691233 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 skip
10501 10:08:20.691393 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
10502 10:08:20.691551 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
10503 10:08:20.691699 arm64_sve-ptrace_Set_SVE_VL_6624 pass
10504 10:08:20.691878 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 skip
10505 10:08:20.692006 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
10506 10:08:20.692128 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
10507 10:08:20.692253 arm64_sve-ptrace_Set_SVE_VL_6640 pass
10508 10:08:20.692374 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 skip
10509 10:08:20.692516 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
10510 10:08:20.692675 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
10511 10:08:20.692831 arm64_sve-ptrace_Set_SVE_VL_6656 pass
10512 10:08:20.693005 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 skip
10513 10:08:20.693139 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
10514 10:08:20.693256 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
10515 10:08:20.693370 arm64_sve-ptrace_Set_SVE_VL_6672 pass
10516 10:08:20.693485 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 skip
10517 10:08:20.693601 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
10518 10:08:20.693791 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
10519 10:08:20.693986 arm64_sve-ptrace_Set_SVE_VL_6688 pass
10520 10:08:20.694169 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 skip
10521 10:08:20.694350 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
10522 10:08:20.694531 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
10523 10:08:20.694716 arm64_sve-ptrace_Set_SVE_VL_6704 pass
10524 10:08:20.697236 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 skip
10525 10:08:20.697640 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
10526 10:08:20.697758 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
10527 10:08:20.697852 arm64_sve-ptrace_Set_SVE_VL_6720 pass
10528 10:08:20.697944 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 skip
10529 10:08:20.698049 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
10530 10:08:20.698145 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
10531 10:08:20.698250 arm64_sve-ptrace_Set_SVE_VL_6736 pass
10532 10:08:20.698354 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 skip
10533 10:08:20.698456 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
10534 10:08:20.698759 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
10535 10:08:20.698919 arm64_sve-ptrace_Set_SVE_VL_6752 pass
10536 10:08:20.699131 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 skip
10537 10:08:20.699245 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
10538 10:08:20.699547 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
10539 10:08:20.699655 arm64_sve-ptrace_Set_SVE_VL_6768 pass
10540 10:08:20.699748 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 skip
10541 10:08:20.700045 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
10542 10:08:20.700148 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
10543 10:08:20.700248 arm64_sve-ptrace_Set_SVE_VL_6784 pass
10544 10:08:20.700334 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 skip
10545 10:08:20.700430 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
10546 10:08:20.700754 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
10547 10:08:20.700859 arm64_sve-ptrace_Set_SVE_VL_6800 pass
10548 10:08:20.700962 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 skip
10549 10:08:20.701049 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
10550 10:08:20.705248 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
10551 10:08:20.705378 arm64_sve-ptrace_Set_SVE_VL_6816 pass
10552 10:08:20.705672 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 skip
10553 10:08:20.705775 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
10554 10:08:20.705875 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
10555 10:08:20.705977 arm64_sve-ptrace_Set_SVE_VL_6832 pass
10556 10:08:20.706064 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 skip
10557 10:08:20.706361 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
10558 10:08:20.706462 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
10559 10:08:20.706548 arm64_sve-ptrace_Set_SVE_VL_6848 pass
10560 10:08:20.706645 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 skip
10561 10:08:20.706730 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
10562 10:08:20.706827 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
10563 10:08:20.706925 arm64_sve-ptrace_Set_SVE_VL_6864 pass
10564 10:08:20.719321 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 skip
10565 10:08:20.719568 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
10566 10:08:20.719882 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
10567 10:08:20.720011 arm64_sve-ptrace_Set_SVE_VL_6880 pass
10568 10:08:20.720118 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 skip
10569 10:08:20.720219 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
10570 10:08:20.720318 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
10571 10:08:20.720415 arm64_sve-ptrace_Set_SVE_VL_6896 pass
10572 10:08:20.720714 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 skip
10573 10:08:20.720856 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
10574 10:08:20.721156 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
10575 10:08:20.721261 arm64_sve-ptrace_Set_SVE_VL_6912 pass
10576 10:08:20.721363 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 skip
10577 10:08:20.721464 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
10578 10:08:20.721752 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
10579 10:08:20.721867 arm64_sve-ptrace_Set_SVE_VL_6928 pass
10580 10:08:20.721964 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 skip
10581 10:08:20.722270 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
10582 10:08:20.722464 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
10583 10:08:20.722571 arm64_sve-ptrace_Set_SVE_VL_6944 pass
10584 10:08:20.722658 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 skip
10585 10:08:20.722756 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
10586 10:08:20.723051 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
10587 10:08:20.723155 arm64_sve-ptrace_Set_SVE_VL_6960 pass
10588 10:08:20.723450 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 skip
10589 10:08:20.723552 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
10590 10:08:20.723649 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
10591 10:08:20.723737 arm64_sve-ptrace_Set_SVE_VL_6976 pass
10592 10:08:20.723833 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 skip
10593 10:08:20.724125 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
10594 10:08:20.724240 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
10595 10:08:20.724329 arm64_sve-ptrace_Set_SVE_VL_6992 pass
10596 10:08:20.724433 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 skip
10597 10:08:20.724723 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
10598 10:08:20.724873 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
10599 10:08:20.724965 arm64_sve-ptrace_Set_SVE_VL_7008 pass
10600 10:08:20.729225 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 skip
10601 10:08:20.729594 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
10602 10:08:20.729701 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
10603 10:08:20.729786 arm64_sve-ptrace_Set_SVE_VL_7024 pass
10604 10:08:20.729889 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 skip
10605 10:08:20.729990 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
10606 10:08:20.730320 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
10607 10:08:20.730515 arm64_sve-ptrace_Set_SVE_VL_7040 pass
10608 10:08:20.730676 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 skip
10609 10:08:20.730851 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
10610 10:08:20.731029 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
10611 10:08:20.731254 arm64_sve-ptrace_Set_SVE_VL_7056 pass
10612 10:08:20.731460 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 skip
10613 10:08:20.731667 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
10614 10:08:20.731896 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
10615 10:08:20.732099 arm64_sve-ptrace_Set_SVE_VL_7072 pass
10616 10:08:20.732287 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 skip
10617 10:08:20.732468 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
10618 10:08:20.732678 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
10619 10:08:20.732889 arm64_sve-ptrace_Set_SVE_VL_7088 pass
10620 10:08:20.733128 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 skip
10621 10:08:20.733262 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
10622 10:08:20.733379 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
10623 10:08:20.733493 arm64_sve-ptrace_Set_SVE_VL_7104 pass
10624 10:08:20.733607 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 skip
10625 10:08:20.733799 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
10626 10:08:20.733991 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
10627 10:08:20.734174 arm64_sve-ptrace_Set_SVE_VL_7120 pass
10628 10:08:20.734355 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 skip
10629 10:08:20.734498 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
10630 10:08:20.737246 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
10631 10:08:20.737667 arm64_sve-ptrace_Set_SVE_VL_7136 pass
10632 10:08:20.737818 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 skip
10633 10:08:20.737962 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
10634 10:08:20.738112 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
10635 10:08:20.738297 arm64_sve-ptrace_Set_SVE_VL_7152 pass
10636 10:08:20.738441 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 skip
10637 10:08:20.738590 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
10638 10:08:20.738743 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
10639 10:08:20.738896 arm64_sve-ptrace_Set_SVE_VL_7168 pass
10640 10:08:20.739073 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 skip
10641 10:08:20.739204 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
10642 10:08:20.739324 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
10643 10:08:20.739442 arm64_sve-ptrace_Set_SVE_VL_7184 pass
10644 10:08:20.739560 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 skip
10645 10:08:20.739684 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
10646 10:08:20.739865 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
10647 10:08:20.740035 arm64_sve-ptrace_Set_SVE_VL_7200 pass
10648 10:08:20.740200 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 skip
10649 10:08:20.740365 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
10650 10:08:20.740533 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
10651 10:08:20.740683 arm64_sve-ptrace_Set_SVE_VL_7216 pass
10652 10:08:20.740871 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 skip
10653 10:08:20.741026 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
10654 10:08:20.741147 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
10655 10:08:20.741260 arm64_sve-ptrace_Set_SVE_VL_7232 pass
10656 10:08:20.741373 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 skip
10657 10:08:20.741486 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
10658 10:08:20.741622 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
10659 10:08:20.741824 arm64_sve-ptrace_Set_SVE_VL_7248 pass
10660 10:08:20.741951 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 skip
10661 10:08:20.745405 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
10662 10:08:20.745619 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
10663 10:08:20.745799 arm64_sve-ptrace_Set_SVE_VL_7264 pass
10664 10:08:20.746232 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 skip
10665 10:08:20.746424 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
10666 10:08:20.746595 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
10667 10:08:20.746749 arm64_sve-ptrace_Set_SVE_VL_7280 pass
10668 10:08:20.746890 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 skip
10669 10:08:20.747024 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
10670 10:08:20.747171 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
10671 10:08:20.747292 arm64_sve-ptrace_Set_SVE_VL_7296 pass
10672 10:08:20.747411 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 skip
10673 10:08:20.747539 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
10674 10:08:20.747696 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
10675 10:08:20.747857 arm64_sve-ptrace_Set_SVE_VL_7312 pass
10676 10:08:20.747990 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 skip
10677 10:08:20.748105 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
10678 10:08:20.748219 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
10679 10:08:20.748359 arm64_sve-ptrace_Set_SVE_VL_7328 pass
10680 10:08:20.748480 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 skip
10681 10:08:20.748593 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
10682 10:08:20.748706 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
10683 10:08:20.748821 arm64_sve-ptrace_Set_SVE_VL_7344 pass
10684 10:08:20.749860 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 skip
10685 10:08:20.750034 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
10686 10:08:20.750157 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
10687 10:08:20.750272 arm64_sve-ptrace_Set_SVE_VL_7360 pass
10688 10:08:20.750387 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 skip
10689 10:08:20.750500 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
10690 10:08:20.750613 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
10691 10:08:20.750725 arm64_sve-ptrace_Set_SVE_VL_7376 pass
10692 10:08:20.750839 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 skip
10693 10:08:20.753550 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
10694 10:08:20.753776 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
10695 10:08:20.753948 arm64_sve-ptrace_Set_SVE_VL_7392 pass
10696 10:08:20.754116 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 skip
10697 10:08:20.754517 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
10698 10:08:20.754683 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
10699 10:08:20.754806 arm64_sve-ptrace_Set_SVE_VL_7408 pass
10700 10:08:20.754906 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 skip
10701 10:08:20.755021 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
10702 10:08:20.755142 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
10703 10:08:20.755243 arm64_sve-ptrace_Set_SVE_VL_7424 pass
10704 10:08:20.755357 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 skip
10705 10:08:20.755509 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
10706 10:08:20.755639 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
10707 10:08:20.755764 arm64_sve-ptrace_Set_SVE_VL_7440 pass
10708 10:08:20.755884 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 skip
10709 10:08:20.756013 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
10710 10:08:20.756144 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
10711 10:08:20.756275 arm64_sve-ptrace_Set_SVE_VL_7456 pass
10712 10:08:20.756405 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 skip
10713 10:08:20.756534 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
10714 10:08:20.756702 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
10715 10:08:20.756833 arm64_sve-ptrace_Set_SVE_VL_7472 pass
10716 10:08:20.756960 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 skip
10717 10:08:20.757085 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
10718 10:08:20.757194 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
10719 10:08:20.757284 arm64_sve-ptrace_Set_SVE_VL_7488 pass
10720 10:08:20.757370 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 skip
10721 10:08:20.757455 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
10722 10:08:20.757540 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
10723 10:08:20.757626 arm64_sve-ptrace_Set_SVE_VL_7504 pass
10724 10:08:20.773372 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 skip
10725 10:08:20.773613 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
10726 10:08:20.773958 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
10727 10:08:20.774040 arm64_sve-ptrace_Set_SVE_VL_7520 pass
10728 10:08:20.774112 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 skip
10729 10:08:20.774183 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
10730 10:08:20.774260 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
10731 10:08:20.774326 arm64_sve-ptrace_Set_SVE_VL_7536 pass
10732 10:08:20.774388 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 skip
10733 10:08:20.774461 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
10734 10:08:20.774535 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
10735 10:08:20.774598 arm64_sve-ptrace_Set_SVE_VL_7552 pass
10736 10:08:20.774699 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 skip
10737 10:08:20.774810 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
10738 10:08:20.774915 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
10739 10:08:20.775002 arm64_sve-ptrace_Set_SVE_VL_7568 pass
10740 10:08:20.775104 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 skip
10741 10:08:20.775205 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
10742 10:08:20.775308 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
10743 10:08:20.775397 arm64_sve-ptrace_Set_SVE_VL_7584 pass
10744 10:08:20.775501 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 skip
10745 10:08:20.775590 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
10746 10:08:20.775695 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
10747 10:08:20.775798 arm64_sve-ptrace_Set_SVE_VL_7600 pass
10748 10:08:20.775901 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 skip
10749 10:08:20.776003 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
10750 10:08:20.776104 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
10751 10:08:20.776203 arm64_sve-ptrace_Set_SVE_VL_7616 pass
10752 10:08:20.776289 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 skip
10753 10:08:20.776392 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
10754 10:08:20.776481 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
10755 10:08:20.776585 arm64_sve-ptrace_Set_SVE_VL_7632 pass
10756 10:08:20.776682 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 skip
10757 10:08:20.776775 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
10758 10:08:20.777079 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
10759 10:08:20.777192 arm64_sve-ptrace_Set_SVE_VL_7648 pass
10760 10:08:20.781137 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 skip
10761 10:08:20.781436 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
10762 10:08:20.781525 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
10763 10:08:20.781617 arm64_sve-ptrace_Set_SVE_VL_7664 pass
10764 10:08:20.781739 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 skip
10765 10:08:20.781832 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
10766 10:08:20.781944 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
10767 10:08:20.782048 arm64_sve-ptrace_Set_SVE_VL_7680 pass
10768 10:08:20.782327 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 skip
10769 10:08:20.782410 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
10770 10:08:20.782474 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
10771 10:08:20.782549 arm64_sve-ptrace_Set_SVE_VL_7696 pass
10772 10:08:20.782612 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 skip
10773 10:08:20.782684 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
10774 10:08:20.782767 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
10775 10:08:20.783071 arm64_sve-ptrace_Set_SVE_VL_7712 pass
10776 10:08:20.783184 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 skip
10777 10:08:20.783296 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
10778 10:08:20.783391 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
10779 10:08:20.783499 arm64_sve-ptrace_Set_SVE_VL_7728 pass
10780 10:08:20.783593 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 skip
10781 10:08:20.783702 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
10782 10:08:20.783800 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
10783 10:08:20.783907 arm64_sve-ptrace_Set_SVE_VL_7744 pass
10784 10:08:20.784015 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 skip
10785 10:08:20.784304 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
10786 10:08:20.784401 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
10787 10:08:20.784494 arm64_sve-ptrace_Set_SVE_VL_7760 pass
10788 10:08:20.784601 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 skip
10789 10:08:20.784695 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
10790 10:08:20.784808 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
10791 10:08:20.784903 arm64_sve-ptrace_Set_SVE_VL_7776 pass
10792 10:08:20.784996 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 skip
10793 10:08:20.785105 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
10794 10:08:20.785198 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
10795 10:08:20.789270 arm64_sve-ptrace_Set_SVE_VL_7792 pass
10796 10:08:20.789382 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 skip
10797 10:08:20.789671 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
10798 10:08:20.789769 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
10799 10:08:20.789859 arm64_sve-ptrace_Set_SVE_VL_7808 pass
10800 10:08:20.789950 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 skip
10801 10:08:20.790058 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
10802 10:08:20.790151 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
10803 10:08:20.790241 arm64_sve-ptrace_Set_SVE_VL_7824 pass
10804 10:08:20.790332 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 skip
10805 10:08:20.790441 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
10806 10:08:20.790535 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
10807 10:08:20.790625 arm64_sve-ptrace_Set_SVE_VL_7840 pass
10808 10:08:20.790716 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 skip
10809 10:08:20.790828 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
10810 10:08:20.790920 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
10811 10:08:20.791011 arm64_sve-ptrace_Set_SVE_VL_7856 pass
10812 10:08:20.791117 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 skip
10813 10:08:20.791209 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
10814 10:08:20.791315 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
10815 10:08:20.791407 arm64_sve-ptrace_Set_SVE_VL_7872 pass
10816 10:08:20.791511 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 skip
10817 10:08:20.791603 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
10818 10:08:20.791708 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
10819 10:08:20.791820 arm64_sve-ptrace_Set_SVE_VL_7888 pass
10820 10:08:20.791926 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 skip
10821 10:08:20.792017 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
10822 10:08:20.792122 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
10823 10:08:20.792214 arm64_sve-ptrace_Set_SVE_VL_7904 pass
10824 10:08:20.792510 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 skip
10825 10:08:20.792606 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
10826 10:08:20.792713 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
10827 10:08:20.792809 arm64_sve-ptrace_Set_SVE_VL_7920 pass
10828 10:08:20.792900 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 skip
10829 10:08:20.792990 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
10830 10:08:20.793096 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
10831 10:08:20.793188 arm64_sve-ptrace_Set_SVE_VL_7936 pass
10832 10:08:20.797347 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 skip
10833 10:08:20.797830 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
10834 10:08:20.797975 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
10835 10:08:20.798133 arm64_sve-ptrace_Set_SVE_VL_7952 pass
10836 10:08:20.798288 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 skip
10837 10:08:20.798443 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
10838 10:08:20.798590 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
10839 10:08:20.798720 arm64_sve-ptrace_Set_SVE_VL_7968 pass
10840 10:08:20.798821 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 skip
10841 10:08:20.798925 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
10842 10:08:20.799242 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
10843 10:08:20.799357 arm64_sve-ptrace_Set_SVE_VL_7984 pass
10844 10:08:20.799480 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 skip
10845 10:08:20.799604 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
10846 10:08:20.799756 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
10847 10:08:20.799854 arm64_sve-ptrace_Set_SVE_VL_8000 pass
10848 10:08:20.799929 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 skip
10849 10:08:20.800003 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
10850 10:08:20.800093 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
10851 10:08:20.800164 arm64_sve-ptrace_Set_SVE_VL_8016 pass
10852 10:08:20.800253 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 skip
10853 10:08:20.800338 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
10854 10:08:20.800408 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
10855 10:08:20.800496 arm64_sve-ptrace_Set_SVE_VL_8032 pass
10856 10:08:20.800566 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 skip
10857 10:08:20.800653 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
10858 10:08:20.800739 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
10859 10:08:20.800809 arm64_sve-ptrace_Set_SVE_VL_8048 pass
10860 10:08:20.800898 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 skip
10861 10:08:20.800967 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
10862 10:08:20.805102 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
10863 10:08:20.805379 arm64_sve-ptrace_Set_SVE_VL_8064 pass
10864 10:08:20.805467 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 skip
10865 10:08:20.805578 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
10866 10:08:20.805694 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
10867 10:08:20.805991 arm64_sve-ptrace_Set_SVE_VL_8080 pass
10868 10:08:20.806109 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 skip
10869 10:08:20.806221 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
10870 10:08:20.806353 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
10871 10:08:20.806456 arm64_sve-ptrace_Set_SVE_VL_8096 pass
10872 10:08:20.806562 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 skip
10873 10:08:20.806668 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
10874 10:08:20.806775 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
10875 10:08:20.806910 arm64_sve-ptrace_Set_SVE_VL_8112 pass
10876 10:08:20.807011 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 skip
10877 10:08:20.807117 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
10878 10:08:20.807224 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
10879 10:08:20.807354 arm64_sve-ptrace_Set_SVE_VL_8128 pass
10880 10:08:20.807455 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 skip
10881 10:08:20.807561 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
10882 10:08:20.807667 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
10883 10:08:20.807773 arm64_sve-ptrace_Set_SVE_VL_8144 pass
10884 10:08:20.819611 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 skip
10885 10:08:20.819965 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
10886 10:08:20.820130 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
10887 10:08:20.820325 arm64_sve-ptrace_Set_SVE_VL_8160 pass
10888 10:08:20.820532 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 skip
10889 10:08:20.820670 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
10890 10:08:20.820812 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
10891 10:08:20.820997 arm64_sve-ptrace_Set_SVE_VL_8176 pass
10892 10:08:20.821169 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 skip
10893 10:08:20.821312 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
10894 10:08:20.821453 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
10895 10:08:20.821632 arm64_sve-ptrace_Set_SVE_VL_8192 pass
10896 10:08:20.821785 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 skip
10897 10:08:20.821931 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
10898 10:08:20.822073 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
10899 10:08:20.822215 arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 pass
10900 10:08:20.822376 arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state pass
10901 10:08:20.822560 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set pass
10902 10:08:20.822733 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared pass
10903 10:08:20.822878 arm64_sve-ptrace_Set_Streaming_SVE_VL_16 pass
10904 10:08:20.823096 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 pass
10905 10:08:20.823253 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 pass
10906 10:08:20.823425 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 pass
10907 10:08:20.823607 arm64_sve-ptrace_Set_Streaming_SVE_VL_32 pass
10908 10:08:20.823777 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 pass
10909 10:08:20.823924 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 pass
10910 10:08:20.824068 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 pass
10911 10:08:20.824209 arm64_sve-ptrace_Set_Streaming_SVE_VL_48 pass
10912 10:08:20.824348 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 skip
10913 10:08:20.824488 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 skip
10914 10:08:20.824628 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 skip
10915 10:08:20.824768 arm64_sve-ptrace_Set_Streaming_SVE_VL_64 pass
10916 10:08:20.824925 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 pass
10917 10:08:20.825131 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 pass
10918 10:08:20.825271 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 pass
10919 10:08:20.825633 arm64_sve-ptrace_Set_Streaming_SVE_VL_80 pass
10920 10:08:20.825780 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 skip
10921 10:08:20.825928 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 skip
10922 10:08:20.826070 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 skip
10923 10:08:20.826212 arm64_sve-ptrace_Set_Streaming_SVE_VL_96 pass
10924 10:08:20.826353 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 skip
10925 10:08:20.826494 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 skip
10926 10:08:20.826634 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 skip
10927 10:08:20.826774 arm64_sve-ptrace_Set_Streaming_SVE_VL_112 pass
10928 10:08:20.826917 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 skip
10929 10:08:20.827056 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 skip
10930 10:08:20.827197 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 skip
10931 10:08:20.827337 arm64_sve-ptrace_Set_Streaming_SVE_VL_128 pass
10932 10:08:20.827477 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 pass
10933 10:08:20.827618 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 pass
10934 10:08:20.829161 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 pass
10935 10:08:20.829505 arm64_sve-ptrace_Set_Streaming_SVE_VL_144 pass
10936 10:08:20.829641 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 skip
10937 10:08:20.829801 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 skip
10938 10:08:20.829979 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 skip
10939 10:08:20.830150 arm64_sve-ptrace_Set_Streaming_SVE_VL_160 pass
10940 10:08:20.830321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 skip
10941 10:08:20.830486 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 skip
10942 10:08:20.830741 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 skip
10943 10:08:20.830932 arm64_sve-ptrace_Set_Streaming_SVE_VL_176 pass
10944 10:08:20.831119 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 skip
10945 10:08:20.831271 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 skip
10946 10:08:20.831436 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 skip
10947 10:08:20.831599 arm64_sve-ptrace_Set_Streaming_SVE_VL_192 pass
10948 10:08:20.831794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 skip
10949 10:08:20.832010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 skip
10950 10:08:20.832169 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 skip
10951 10:08:20.832316 arm64_sve-ptrace_Set_Streaming_SVE_VL_208 pass
10952 10:08:20.832441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 skip
10953 10:08:20.832561 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 skip
10954 10:08:20.832689 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 skip
10955 10:08:20.832830 arm64_sve-ptrace_Set_Streaming_SVE_VL_224 pass
10956 10:08:20.832995 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 skip
10957 10:08:20.833165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 skip
10958 10:08:20.833294 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 skip
10959 10:08:20.833439 arm64_sve-ptrace_Set_Streaming_SVE_VL_240 pass
10960 10:08:20.833560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 skip
10961 10:08:20.833692 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 skip
10962 10:08:20.833809 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 skip
10963 10:08:20.833925 arm64_sve-ptrace_Set_Streaming_SVE_VL_256 pass
10964 10:08:20.834037 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 pass
10965 10:08:20.834150 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 pass
10966 10:08:20.837273 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 pass
10967 10:08:20.837384 arm64_sve-ptrace_Set_Streaming_SVE_VL_272 pass
10968 10:08:20.837676 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 skip
10969 10:08:20.837781 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
10970 10:08:20.837882 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
10971 10:08:20.837970 arm64_sve-ptrace_Set_Streaming_SVE_VL_288 pass
10972 10:08:20.838066 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 skip
10973 10:08:20.838621 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
10974 10:08:20.838792 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
10975 10:08:20.838959 arm64_sve-ptrace_Set_Streaming_SVE_VL_304 pass
10976 10:08:20.839123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 skip
10977 10:08:20.839331 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
10978 10:08:20.839537 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
10979 10:08:20.839740 arm64_sve-ptrace_Set_Streaming_SVE_VL_320 pass
10980 10:08:20.839954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 skip
10981 10:08:20.840146 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
10982 10:08:20.840392 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
10983 10:08:20.840571 arm64_sve-ptrace_Set_Streaming_SVE_VL_336 pass
10984 10:08:20.840740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 skip
10985 10:08:20.840921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
10986 10:08:20.841078 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
10987 10:08:20.841199 arm64_sve-ptrace_Set_Streaming_SVE_VL_352 pass
10988 10:08:20.841314 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 skip
10989 10:08:20.841428 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
10990 10:08:20.841569 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
10991 10:08:20.841733 arm64_sve-ptrace_Set_Streaming_SVE_VL_368 pass
10992 10:08:20.841936 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 skip
10993 10:08:20.845229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
10994 10:08:20.845674 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
10995 10:08:20.845874 arm64_sve-ptrace_Set_Streaming_SVE_VL_384 pass
10996 10:08:20.846045 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 skip
10997 10:08:20.846212 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
10998 10:08:20.846383 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
10999 10:08:20.846577 arm64_sve-ptrace_Set_Streaming_SVE_VL_400 pass
11000 10:08:20.846754 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 skip
11001 10:08:20.846904 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
11002 10:08:20.847046 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
11003 10:08:20.847232 arm64_sve-ptrace_Set_Streaming_SVE_VL_416 pass
11004 10:08:20.847428 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 skip
11005 10:08:20.847596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
11006 10:08:20.847751 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
11007 10:08:20.847903 arm64_sve-ptrace_Set_Streaming_SVE_VL_432 pass
11008 10:08:20.848048 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 skip
11009 10:08:20.848191 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
11010 10:08:20.848332 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
11011 10:08:20.848468 arm64_sve-ptrace_Set_Streaming_SVE_VL_448 pass
11012 10:08:20.848618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 skip
11013 10:08:20.848774 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
11014 10:08:20.848897 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
11015 10:08:20.849047 arm64_sve-ptrace_Set_Streaming_SVE_VL_464 pass
11016 10:08:20.849176 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 skip
11017 10:08:20.849288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
11018 10:08:20.849399 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
11019 10:08:20.849544 arm64_sve-ptrace_Set_Streaming_SVE_VL_480 pass
11020 10:08:20.849720 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 skip
11021 10:08:20.865827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
11022 10:08:20.865947 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
11023 10:08:20.866293 arm64_sve-ptrace_Set_Streaming_SVE_VL_496 pass
11024 10:08:20.866491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 skip
11025 10:08:20.866644 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
11026 10:08:20.866827 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
11027 10:08:20.866992 arm64_sve-ptrace_Set_Streaming_SVE_VL_512 pass
11028 10:08:20.867150 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 skip
11029 10:08:20.867311 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
11030 10:08:20.867467 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
11031 10:08:20.867634 arm64_sve-ptrace_Set_Streaming_SVE_VL_528 pass
11032 10:08:20.867786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 skip
11033 10:08:20.867946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
11034 10:08:20.868076 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
11035 10:08:20.868196 arm64_sve-ptrace_Set_Streaming_SVE_VL_544 pass
11036 10:08:20.868315 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 skip
11037 10:08:20.868467 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
11038 10:08:20.868596 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
11039 10:08:20.868721 arm64_sve-ptrace_Set_Streaming_SVE_VL_560 pass
11040 10:08:20.868858 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 skip
11041 10:08:20.869015 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
11042 10:08:20.869158 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
11043 10:08:20.869280 arm64_sve-ptrace_Set_Streaming_SVE_VL_576 pass
11044 10:08:20.869401 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 skip
11045 10:08:20.869550 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
11046 10:08:20.869712 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
11047 10:08:20.869918 arm64_sve-ptrace_Set_Streaming_SVE_VL_592 pass
11048 10:08:20.870107 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 skip
11049 10:08:20.870290 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
11050 10:08:20.873183 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
11051 10:08:20.873630 arm64_sve-ptrace_Set_Streaming_SVE_VL_608 pass
11052 10:08:20.873827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 skip
11053 10:08:20.873994 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
11054 10:08:20.874209 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
11055 10:08:20.874393 arm64_sve-ptrace_Set_Streaming_SVE_VL_624 pass
11056 10:08:20.874618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 skip
11057 10:08:20.874829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
11058 10:08:20.875088 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
11059 10:08:20.875286 arm64_sve-ptrace_Set_Streaming_SVE_VL_640 pass
11060 10:08:20.875463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 skip
11061 10:08:20.875627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
11062 10:08:20.875774 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
11063 10:08:20.875957 arm64_sve-ptrace_Set_Streaming_SVE_VL_656 pass
11064 10:08:20.876212 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 skip
11065 10:08:20.876399 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
11066 10:08:20.876586 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
11067 10:08:20.876763 arm64_sve-ptrace_Set_Streaming_SVE_VL_672 pass
11068 10:08:20.876925 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 skip
11069 10:08:20.877096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
11070 10:08:20.877224 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
11071 10:08:20.877367 arm64_sve-ptrace_Set_Streaming_SVE_VL_688 pass
11072 10:08:20.877488 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 skip
11073 10:08:20.877603 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
11074 10:08:20.877732 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
11075 10:08:20.877845 arm64_sve-ptrace_Set_Streaming_SVE_VL_704 pass
11076 10:08:20.877962 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 skip
11077 10:08:20.881233 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
11078 10:08:20.881365 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
11079 10:08:20.881710 arm64_sve-ptrace_Set_Streaming_SVE_VL_720 pass
11080 10:08:20.881848 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 skip
11081 10:08:20.882018 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
11082 10:08:20.882202 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
11083 10:08:20.882422 arm64_sve-ptrace_Set_Streaming_SVE_VL_736 pass
11084 10:08:20.882622 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 skip
11085 10:08:20.882849 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
11086 10:08:20.883036 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
11087 10:08:20.883232 arm64_sve-ptrace_Set_Streaming_SVE_VL_752 pass
11088 10:08:20.883428 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 skip
11089 10:08:20.883673 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
11090 10:08:20.883896 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
11091 10:08:20.884107 arm64_sve-ptrace_Set_Streaming_SVE_VL_768 pass
11092 10:08:20.884290 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 skip
11093 10:08:20.884498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
11094 10:08:20.884682 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
11095 10:08:20.885587 arm64_sve-ptrace_Set_Streaming_SVE_VL_784 pass
11096 10:08:20.885736 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 skip
11097 10:08:20.885854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
11098 10:08:20.885996 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
11099 10:08:20.886116 arm64_sve-ptrace_Set_Streaming_SVE_VL_800 pass
11100 10:08:20.886230 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 skip
11101 10:08:20.886344 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
11102 10:08:20.889183 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
11103 10:08:20.889622 arm64_sve-ptrace_Set_Streaming_SVE_VL_816 pass
11104 10:08:20.889849 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 skip
11105 10:08:20.890063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
11106 10:08:20.890307 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
11107 10:08:20.890502 arm64_sve-ptrace_Set_Streaming_SVE_VL_832 pass
11108 10:08:20.890678 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 skip
11109 10:08:20.890837 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
11110 10:08:20.891038 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
11111 10:08:20.891182 arm64_sve-ptrace_Set_Streaming_SVE_VL_848 pass
11112 10:08:20.891307 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 skip
11113 10:08:20.891462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
11114 10:08:20.891594 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
11115 10:08:20.891765 arm64_sve-ptrace_Set_Streaming_SVE_VL_864 pass
11116 10:08:20.891899 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 skip
11117 10:08:20.892044 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
11118 10:08:20.892174 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
11119 10:08:20.892365 arm64_sve-ptrace_Set_Streaming_SVE_VL_880 pass
11120 10:08:20.892494 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 skip
11121 10:08:20.892633 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
11122 10:08:20.892794 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
11123 10:08:20.892942 arm64_sve-ptrace_Set_Streaming_SVE_VL_896 pass
11124 10:08:20.893075 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 skip
11125 10:08:20.893176 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
11126 10:08:20.893265 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
11127 10:08:20.893351 arm64_sve-ptrace_Set_Streaming_SVE_VL_912 pass
11128 10:08:20.897188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 skip
11129 10:08:20.897556 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
11130 10:08:20.897682 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
11131 10:08:20.897806 arm64_sve-ptrace_Set_Streaming_SVE_VL_928 pass
11132 10:08:20.897906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 skip
11133 10:08:20.897998 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
11134 10:08:20.898089 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
11135 10:08:20.898181 arm64_sve-ptrace_Set_Streaming_SVE_VL_944 pass
11136 10:08:20.898482 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 skip
11137 10:08:20.898588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
11138 10:08:20.898709 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
11139 10:08:20.898822 arm64_sve-ptrace_Set_Streaming_SVE_VL_960 pass
11140 10:08:20.899125 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 skip
11141 10:08:20.899233 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
11142 10:08:20.899337 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
11143 10:08:20.899437 arm64_sve-ptrace_Set_Streaming_SVE_VL_976 pass
11144 10:08:20.899536 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 skip
11145 10:08:20.899894 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
11146 10:08:20.900001 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
11147 10:08:20.900104 arm64_sve-ptrace_Set_Streaming_SVE_VL_992 pass
11148 10:08:20.900201 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 skip
11149 10:08:20.900505 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
11150 10:08:20.900620 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
11151 10:08:20.900727 arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 pass
11152 10:08:20.901051 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 skip
11153 10:08:20.905239 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
11154 10:08:20.905694 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
11155 10:08:20.905850 arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 pass
11156 10:08:20.905974 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 skip
11157 10:08:20.915418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
11158 10:08:20.915821 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
11159 10:08:20.915994 arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 pass
11160 10:08:20.916152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 skip
11161 10:08:20.916342 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
11162 10:08:20.916493 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
11163 10:08:20.916653 arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 pass
11164 10:08:20.916804 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 skip
11165 10:08:20.917027 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
11166 10:08:20.917217 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
11167 10:08:20.917402 arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 pass
11168 10:08:20.917571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 skip
11169 10:08:20.917775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
11170 10:08:20.918048 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
11171 10:08:20.918247 arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 pass
11172 10:08:20.918428 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 skip
11173 10:08:20.918616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
11174 10:08:20.918761 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
11175 10:08:20.918922 arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 pass
11176 10:08:20.919134 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 skip
11177 10:08:20.919426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
11178 10:08:20.919621 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
11179 10:08:20.919772 arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 pass
11180 10:08:20.919952 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 skip
11181 10:08:20.920185 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
11182 10:08:20.920408 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
11183 10:08:20.920598 arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 pass
11184 10:08:20.920831 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 skip
11185 10:08:20.921048 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
11186 10:08:20.921247 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
11187 10:08:20.921379 arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 pass
11188 10:08:20.921496 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 skip
11189 10:08:20.921613 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
11190 10:08:20.921951 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
11191 10:08:20.922080 arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 pass
11192 10:08:20.922194 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 skip
11193 10:08:20.922306 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
11194 10:08:20.922419 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
11195 10:08:20.922531 arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 pass
11196 10:08:20.922643 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 skip
11197 10:08:20.922755 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
11198 10:08:20.922868 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
11199 10:08:20.922983 arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 pass
11200 10:08:20.925219 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 skip
11201 10:08:20.925637 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
11202 10:08:20.925861 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
11203 10:08:20.926080 arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 pass
11204 10:08:20.926298 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 skip
11205 10:08:20.926463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
11206 10:08:20.926666 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
11207 10:08:20.926821 arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 pass
11208 10:08:20.926981 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 skip
11209 10:08:20.927132 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
11210 10:08:20.927295 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
11211 10:08:20.927464 arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 pass
11212 10:08:20.927626 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 skip
11213 10:08:20.927820 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
11214 10:08:20.927985 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
11215 10:08:20.928145 arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 pass
11216 10:08:20.928281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 skip
11217 10:08:20.928417 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
11218 10:08:20.928571 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
11219 10:08:20.928735 arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 pass
11220 10:08:20.928937 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 skip
11221 10:08:20.929090 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
11222 10:08:20.929207 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
11223 10:08:20.929317 arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 pass
11224 10:08:20.929427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 skip
11225 10:08:20.929537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
11226 10:08:20.929678 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
11227 10:08:20.929926 arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 pass
11228 10:08:20.933190 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 skip
11229 10:08:20.933670 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
11230 10:08:20.933848 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
11231 10:08:20.934000 arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 pass
11232 10:08:20.934222 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 skip
11233 10:08:20.934432 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
11234 10:08:20.934613 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
11235 10:08:20.934816 arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 pass
11236 10:08:20.934962 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 skip
11237 10:08:20.935117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
11238 10:08:20.935350 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
11239 10:08:20.935567 arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 pass
11240 10:08:20.935796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 skip
11241 10:08:20.935976 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
11242 10:08:20.936144 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
11243 10:08:20.936294 arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 pass
11244 10:08:20.936450 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 skip
11245 10:08:20.936609 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
11246 10:08:20.936816 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
11247 10:08:20.936997 arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 pass
11248 10:08:20.937139 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 skip
11249 10:08:20.937254 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
11250 10:08:20.937368 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
11251 10:08:20.937480 arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 pass
11252 10:08:20.937590 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 skip
11253 10:08:20.937824 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
11254 10:08:20.941262 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
11255 10:08:20.941724 arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 pass
11256 10:08:20.941918 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 skip
11257 10:08:20.942080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
11258 10:08:20.942260 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
11259 10:08:20.942422 arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 pass
11260 10:08:20.942577 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 skip
11261 10:08:20.942766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
11262 10:08:20.942937 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
11263 10:08:20.943094 arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 pass
11264 10:08:20.943250 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 skip
11265 10:08:20.943415 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
11266 10:08:20.943584 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
11267 10:08:20.943751 arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 pass
11268 10:08:20.943893 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 skip
11269 10:08:20.944052 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
11270 10:08:20.944246 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
11271 10:08:20.944395 arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 pass
11272 10:08:20.944594 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 skip
11273 10:08:20.944774 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
11274 10:08:20.944937 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
11275 10:08:20.945071 arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 pass
11276 10:08:20.945188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 skip
11277 10:08:20.945327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
11278 10:08:20.945445 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
11279 10:08:20.945557 arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 pass
11280 10:08:20.945734 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 skip
11281 10:08:20.945940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
11282 10:08:20.949193 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
11283 10:08:20.949639 arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 pass
11284 10:08:20.949839 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 skip
11285 10:08:20.950045 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
11286 10:08:20.950231 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
11287 10:08:20.950363 arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 pass
11288 10:08:20.950489 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 skip
11289 10:08:20.950593 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
11290 10:08:20.950737 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
11291 10:08:20.967582 arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 pass
11292 10:08:20.967888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 skip
11293 10:08:20.968260 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
11294 10:08:20.968417 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
11295 10:08:20.968558 arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 pass
11296 10:08:20.968707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 skip
11297 10:08:20.968823 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
11298 10:08:20.968976 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
11299 10:08:20.969099 arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 pass
11300 10:08:20.969208 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 skip
11301 10:08:20.969316 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
11302 10:08:20.969447 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
11303 10:08:20.969549 arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 pass
11304 10:08:20.969686 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 skip
11305 10:08:20.969796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
11306 10:08:20.970130 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
11307 10:08:20.970251 arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 pass
11308 10:08:20.970363 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 skip
11309 10:08:20.970499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
11310 10:08:20.970610 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
11311 10:08:20.970720 arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 pass
11312 10:08:20.971018 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 skip
11313 10:08:20.971121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
11314 10:08:20.971231 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
11315 10:08:20.971341 arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 pass
11316 10:08:20.971451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 skip
11317 10:08:20.971581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
11318 10:08:20.971879 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
11319 10:08:20.971975 arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 pass
11320 10:08:20.972080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 skip
11321 10:08:20.972184 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
11322 10:08:20.972672 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
11323 10:08:20.972789 arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 pass
11324 10:08:20.972879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 skip
11325 10:08:20.973021 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
11326 10:08:20.973123 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
11327 10:08:20.977204 arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 pass
11328 10:08:20.977517 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 skip
11329 10:08:20.977621 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
11330 10:08:20.977755 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
11331 10:08:20.977870 arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 pass
11332 10:08:20.977986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 skip
11333 10:08:20.978115 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
11334 10:08:20.978263 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
11335 10:08:20.978398 arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 pass
11336 10:08:20.978508 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 skip
11337 10:08:20.978646 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
11338 10:08:20.978800 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
11339 10:08:20.978948 arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 pass
11340 10:08:20.979070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 skip
11341 10:08:20.979196 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
11342 10:08:20.979346 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
11343 10:08:20.979460 arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 pass
11344 10:08:20.979580 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 skip
11345 10:08:20.979698 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
11346 10:08:20.979807 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
11347 10:08:20.979952 arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 pass
11348 10:08:20.980071 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 skip
11349 10:08:20.980192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
11350 10:08:20.980299 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
11351 10:08:20.980440 arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 pass
11352 10:08:20.980563 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 skip
11353 10:08:20.980706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
11354 10:08:20.980858 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
11355 10:08:20.980983 arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 pass
11356 10:08:20.981091 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 skip
11357 10:08:20.985400 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
11358 10:08:20.985573 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
11359 10:08:20.985745 arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 pass
11360 10:08:20.985945 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 skip
11361 10:08:20.986097 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
11362 10:08:20.986303 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
11363 10:08:20.986518 arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 pass
11364 10:08:20.986772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 skip
11365 10:08:20.986981 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
11366 10:08:20.987163 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
11367 10:08:20.987351 arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 pass
11368 10:08:20.987526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 skip
11369 10:08:20.987681 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
11370 10:08:20.987845 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
11371 10:08:20.987997 arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 pass
11372 10:08:20.988137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 skip
11373 10:08:20.988313 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
11374 10:08:20.988457 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
11375 10:08:20.988611 arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 pass
11376 10:08:20.988755 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 skip
11377 10:08:20.988895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
11378 10:08:20.989085 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
11379 10:08:20.989216 arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 pass
11380 10:08:20.989329 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 skip
11381 10:08:20.989442 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
11382 10:08:20.989554 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
11383 10:08:20.989715 arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 pass
11384 10:08:20.993181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 skip
11385 10:08:20.993581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
11386 10:08:20.993801 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
11387 10:08:20.993988 arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 pass
11388 10:08:20.994166 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 skip
11389 10:08:20.994293 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
11390 10:08:20.994410 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
11391 10:08:20.994517 arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 pass
11392 10:08:20.994697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 skip
11393 10:08:20.994845 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
11394 10:08:20.994955 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
11395 10:08:20.995084 arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 pass
11396 10:08:20.995213 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 skip
11397 10:08:20.995327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
11398 10:08:20.995456 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
11399 10:08:20.995578 arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 pass
11400 10:08:20.995697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 skip
11401 10:08:20.995838 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
11402 10:08:20.995979 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
11403 10:08:20.996121 arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 pass
11404 10:08:20.996262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 skip
11405 10:08:20.996378 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
11406 10:08:20.996480 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
11407 10:08:20.996607 arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 pass
11408 10:08:20.997227 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 skip
11409 10:08:20.997328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
11410 10:08:20.997415 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
11411 10:08:20.997489 arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 pass
11412 10:08:20.997582 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 skip
11413 10:08:20.997662 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
11414 10:08:20.997751 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
11415 10:08:20.997840 arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 pass
11416 10:08:20.998139 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 skip
11417 10:08:20.998231 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
11418 10:08:21.008305 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
11419 10:08:21.008417 arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 pass
11420 10:08:21.008480 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 skip
11421 10:08:21.008541 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
11422 10:08:21.008601 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
11423 10:08:21.008661 arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 pass
11424 10:08:21.008720 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 skip
11425 10:08:21.016172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
11426 10:08:21.016536 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
11427 10:08:21.016733 arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 pass
11428 10:08:21.016953 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 skip
11429 10:08:21.017125 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
11430 10:08:21.017283 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
11431 10:08:21.017441 arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 pass
11432 10:08:21.017630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 skip
11433 10:08:21.017805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
11434 10:08:21.017965 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
11435 10:08:21.018122 arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 pass
11436 10:08:21.018346 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 skip
11437 10:08:21.018564 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
11438 10:08:21.018767 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
11439 10:08:21.019001 arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 pass
11440 10:08:21.019220 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 skip
11441 10:08:21.019428 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
11442 10:08:21.019659 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
11443 10:08:21.019870 arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 pass
11444 10:08:21.020093 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 skip
11445 10:08:21.020354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
11446 10:08:21.020563 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
11447 10:08:21.020759 arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 pass
11448 10:08:21.020979 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 skip
11449 10:08:21.021144 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
11450 10:08:21.021274 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
11451 10:08:21.021387 arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 pass
11452 10:08:21.021499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 skip
11453 10:08:21.021610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
11454 10:08:21.021863 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
11455 10:08:21.022056 arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 pass
11456 10:08:21.022240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 skip
11457 10:08:21.022644 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
11458 10:08:21.025168 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
11459 10:08:21.025658 arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 pass
11460 10:08:21.025836 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 skip
11461 10:08:21.026019 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
11462 10:08:21.026214 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
11463 10:08:21.026387 arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 pass
11464 10:08:21.026575 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 skip
11465 10:08:21.026740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
11466 10:08:21.026880 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
11467 10:08:21.027042 arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 pass
11468 10:08:21.027186 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 skip
11469 10:08:21.027389 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
11470 10:08:21.027580 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
11471 10:08:21.027778 arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 pass
11472 10:08:21.027959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 skip
11473 10:08:21.028116 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
11474 10:08:21.028270 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
11475 10:08:21.028422 arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 pass
11476 10:08:21.028550 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 skip
11477 10:08:21.028690 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
11478 10:08:21.028889 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
11479 10:08:21.029033 arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 pass
11480 10:08:21.029151 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 skip
11481 10:08:21.029271 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
11482 10:08:21.029387 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
11483 10:08:21.029502 arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 pass
11484 10:08:21.029617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 skip
11485 10:08:21.029744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
11486 10:08:21.033287 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
11487 10:08:21.033485 arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 pass
11488 10:08:21.033893 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 skip
11489 10:08:21.034089 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
11490 10:08:21.034255 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
11491 10:08:21.034424 arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 pass
11492 10:08:21.034573 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 skip
11493 10:08:21.034744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
11494 10:08:21.034906 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
11495 10:08:21.035081 arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 pass
11496 10:08:21.035286 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 skip
11497 10:08:21.035454 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
11498 10:08:21.035668 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
11499 10:08:21.035835 arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 pass
11500 10:08:21.036023 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 skip
11501 10:08:21.036187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
11502 10:08:21.036339 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
11503 10:08:21.036485 arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 pass
11504 10:08:21.036669 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 skip
11505 10:08:21.036868 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
11506 10:08:21.037039 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
11507 10:08:21.037212 arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 pass
11508 10:08:21.037346 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 skip
11509 10:08:21.037463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
11510 10:08:21.037575 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
11511 10:08:21.037703 arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 pass
11512 10:08:21.037815 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 skip
11513 10:08:21.037930 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
11514 10:08:21.041287 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
11515 10:08:21.041707 arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 pass
11516 10:08:21.041914 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 skip
11517 10:08:21.042154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
11518 10:08:21.042354 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
11519 10:08:21.042551 arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 pass
11520 10:08:21.042781 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 skip
11521 10:08:21.042979 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
11522 10:08:21.043213 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
11523 10:08:21.043421 arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 pass
11524 10:08:21.043627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 skip
11525 10:08:21.043889 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
11526 10:08:21.044098 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
11527 10:08:21.044309 arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 pass
11528 10:08:21.044548 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 skip
11529 10:08:21.044766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
11530 10:08:21.044983 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
11531 10:08:21.045132 arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 pass
11532 10:08:21.045248 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 skip
11533 10:08:21.045389 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
11534 10:08:21.045508 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
11535 10:08:21.045623 arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 pass
11536 10:08:21.045804 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 skip
11537 10:08:21.045930 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
11538 10:08:21.046053 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
11539 10:08:21.046207 arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 pass
11540 10:08:21.049173 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 skip
11541 10:08:21.049703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
11542 10:08:21.049903 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
11543 10:08:21.050090 arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 pass
11544 10:08:21.050335 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 skip
11545 10:08:21.050543 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
11546 10:08:21.050731 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
11547 10:08:21.050911 arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 pass
11548 10:08:21.051105 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 skip
11549 10:08:21.051318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
11550 10:08:21.051521 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
11551 10:08:21.051674 arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 pass
11552 10:08:21.051878 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 skip
11553 10:08:21.052044 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
11554 10:08:21.052194 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
11555 10:08:21.052321 arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 pass
11556 10:08:21.052503 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 skip
11557 10:08:21.052689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
11558 10:08:21.052852 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
11559 10:08:21.066480 arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 pass
11560 10:08:21.066903 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 skip
11561 10:08:21.067007 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
11562 10:08:21.067097 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
11563 10:08:21.067197 arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 pass
11564 10:08:21.067282 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 skip
11565 10:08:21.067382 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
11566 10:08:21.067482 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
11567 10:08:21.067583 arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 pass
11568 10:08:21.067929 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 skip
11569 10:08:21.068274 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
11570 10:08:21.068462 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
11571 10:08:21.068617 arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 pass
11572 10:08:21.068806 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 skip
11573 10:08:21.068969 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
11574 10:08:21.069097 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
11575 10:08:21.069219 arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 pass
11576 10:08:21.069369 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 skip
11577 10:08:21.073217 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
11578 10:08:21.073677 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
11579 10:08:21.073890 arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 pass
11580 10:08:21.074132 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 skip
11581 10:08:21.074313 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
11582 10:08:21.074532 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
11583 10:08:21.074749 arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 pass
11584 10:08:21.075031 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 skip
11585 10:08:21.075246 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
11586 10:08:21.075417 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
11587 10:08:21.075580 arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 pass
11588 10:08:21.075781 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 skip
11589 10:08:21.075996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
11590 10:08:21.076205 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
11591 10:08:21.076387 arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 pass
11592 10:08:21.076552 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 skip
11593 10:08:21.076733 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
11594 10:08:21.076905 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
11595 10:08:21.077054 arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 pass
11596 10:08:21.077179 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 skip
11597 10:08:21.077322 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
11598 10:08:21.077444 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
11599 10:08:21.077557 arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 pass
11600 10:08:21.077706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 skip
11601 10:08:21.077910 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
11602 10:08:21.078093 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
11603 10:08:21.078274 arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 pass
11604 10:08:21.081192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 skip
11605 10:08:21.081615 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
11606 10:08:21.081799 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
11607 10:08:21.081994 arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 pass
11608 10:08:21.082162 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 skip
11609 10:08:21.082314 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
11610 10:08:21.082474 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
11611 10:08:21.082625 arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 pass
11612 10:08:21.082773 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 skip
11613 10:08:21.082916 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
11614 10:08:21.083091 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
11615 10:08:21.083265 arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 pass
11616 10:08:21.083398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 skip
11617 10:08:21.083585 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
11618 10:08:21.083775 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
11619 10:08:21.083930 arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 pass
11620 10:08:21.084083 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 skip
11621 10:08:21.084245 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
11622 10:08:21.084401 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
11623 10:08:21.084585 arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 pass
11624 10:08:21.084782 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 skip
11625 10:08:21.084977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
11626 10:08:21.085130 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
11627 10:08:21.085248 arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 pass
11628 10:08:21.085364 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 skip
11629 10:08:21.085475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
11630 10:08:21.085611 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
11631 10:08:21.085837 arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 pass
11632 10:08:21.089166 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 skip
11633 10:08:21.089596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
11634 10:08:21.089787 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
11635 10:08:21.089945 arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 pass
11636 10:08:21.090105 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 skip
11637 10:08:21.090293 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
11638 10:08:21.090455 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
11639 10:08:21.090611 arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 pass
11640 10:08:21.090763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 skip
11641 10:08:21.090945 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
11642 10:08:21.091103 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
11643 10:08:21.091255 arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 pass
11644 10:08:21.091411 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 skip
11645 10:08:21.091570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
11646 10:08:21.091726 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
11647 10:08:21.091879 arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 pass
11648 10:08:21.092063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 skip
11649 10:08:21.092226 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
11650 10:08:21.092380 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
11651 10:08:21.092539 arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 pass
11652 10:08:21.092695 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 skip
11653 10:08:21.092854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
11654 10:08:21.093006 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
11655 10:08:21.093125 arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 pass
11656 10:08:21.093263 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 skip
11657 10:08:21.093379 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
11658 10:08:21.093489 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
11659 10:08:21.093598 arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 pass
11660 10:08:21.093720 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 skip
11661 10:08:21.093830 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
11662 10:08:21.093940 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
11663 10:08:21.094048 arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 pass
11664 10:08:21.097228 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 skip
11665 10:08:21.097709 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
11666 10:08:21.097911 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
11667 10:08:21.098075 arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 pass
11668 10:08:21.098229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 skip
11669 10:08:21.098414 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
11670 10:08:21.098572 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
11671 10:08:21.098725 arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 pass
11672 10:08:21.098878 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 skip
11673 10:08:21.099031 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
11674 10:08:21.099213 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
11675 10:08:21.099372 arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 pass
11676 10:08:21.099526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 skip
11677 10:08:21.099679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
11678 10:08:21.099832 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
11679 10:08:21.099984 arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 pass
11680 10:08:21.100169 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 skip
11681 10:08:21.100326 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
11682 10:08:21.100483 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
11683 10:08:21.100636 arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 pass
11684 10:08:21.100789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 skip
11685 10:08:21.100951 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
11686 10:08:21.101104 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
11687 10:08:21.101257 arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 pass
11688 10:08:21.101441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 skip
11689 10:08:21.101598 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
11690 10:08:21.101763 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
11691 10:08:21.101916 arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 pass
11692 10:08:21.102068 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 skip
11693 10:08:21.115437 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
11694 10:08:21.115950 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
11695 10:08:21.116115 arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 pass
11696 10:08:21.116271 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 skip
11697 10:08:21.116432 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
11698 10:08:21.116622 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
11699 10:08:21.116771 arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 pass
11700 10:08:21.116891 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 skip
11701 10:08:21.117005 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
11702 10:08:21.117143 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
11703 10:08:21.117290 arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 pass
11704 10:08:21.117478 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 skip
11705 10:08:21.117635 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
11706 10:08:21.117821 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
11707 10:08:21.117983 arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 pass
11708 10:08:21.118192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 skip
11709 10:08:21.118385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
11710 10:08:21.118542 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
11711 10:08:21.118703 arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 pass
11712 10:08:21.118844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 skip
11713 10:08:21.118962 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
11714 10:08:21.119097 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
11715 10:08:21.119221 arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 pass
11716 10:08:21.119384 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 skip
11717 10:08:21.119559 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
11718 10:08:21.119718 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
11719 10:08:21.119870 arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 pass
11720 10:08:21.120011 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 skip
11721 10:08:21.120170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
11722 10:08:21.120309 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
11723 10:08:21.120445 arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 pass
11724 10:08:21.120606 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 skip
11725 10:08:21.120740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
11726 10:08:21.121091 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
11727 10:08:21.121240 arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 pass
11728 10:08:21.125285 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 skip
11729 10:08:21.125619 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
11730 10:08:21.125716 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
11731 10:08:21.125795 arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 pass
11732 10:08:21.126060 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 skip
11733 10:08:21.126147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
11734 10:08:21.126441 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
11735 10:08:21.126594 arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 pass
11736 10:08:21.126753 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 skip
11737 10:08:21.126896 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
11738 10:08:21.127055 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
11739 10:08:21.127217 arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 pass
11740 10:08:21.127440 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 skip
11741 10:08:21.127620 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
11742 10:08:21.127780 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
11743 10:08:21.127942 arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 pass
11744 10:08:21.128105 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 skip
11745 10:08:21.128236 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
11746 10:08:21.128387 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
11747 10:08:21.128529 arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 pass
11748 10:08:21.128687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 skip
11749 10:08:21.129029 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
11750 10:08:21.129154 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
11751 10:08:21.133308 arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 pass
11752 10:08:21.133739 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 skip
11753 10:08:21.133893 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
11754 10:08:21.134034 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
11755 10:08:21.134153 arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 pass
11756 10:08:21.134289 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 skip
11757 10:08:21.134434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
11758 10:08:21.134628 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
11759 10:08:21.134796 arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 pass
11760 10:08:21.134986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 skip
11761 10:08:21.135151 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
11762 10:08:21.135342 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
11763 10:08:21.135553 arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 pass
11764 10:08:21.135757 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 skip
11765 10:08:21.135911 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
11766 10:08:21.136043 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
11767 10:08:21.136252 arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 pass
11768 10:08:21.136418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 skip
11769 10:08:21.136650 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
11770 10:08:21.136875 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
11771 10:08:21.137028 arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 pass
11772 10:08:21.137146 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 skip
11773 10:08:21.137260 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
11774 10:08:21.141412 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
11775 10:08:21.141974 arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 pass
11776 10:08:21.142193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 skip
11777 10:08:21.142375 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
11778 10:08:21.142576 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
11779 10:08:21.142726 arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 pass
11780 10:08:21.142896 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 skip
11781 10:08:21.143053 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
11782 10:08:21.143194 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
11783 10:08:21.143353 arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 pass
11784 10:08:21.143520 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 skip
11785 10:08:21.143679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
11786 10:08:21.143803 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
11787 10:08:21.143916 arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 pass
11788 10:08:21.144057 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 skip
11789 10:08:21.144196 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
11790 10:08:21.144343 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
11791 10:08:21.144501 arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 pass
11792 10:08:21.144664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 skip
11793 10:08:21.144827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
11794 10:08:21.144969 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
11795 10:08:21.145086 arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 pass
11796 10:08:21.145223 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 skip
11797 10:08:21.145342 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
11798 10:08:21.145456 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
11799 10:08:21.149411 arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 pass
11800 10:08:21.149901 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 skip
11801 10:08:21.150056 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
11802 10:08:21.150258 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
11803 10:08:21.150443 arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 pass
11804 10:08:21.150601 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 skip
11805 10:08:21.150743 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
11806 10:08:21.150940 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
11807 10:08:21.151144 arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 pass
11808 10:08:21.151336 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 skip
11809 10:08:21.151543 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
11810 10:08:21.151780 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
11811 10:08:21.151947 arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 pass
11812 10:08:21.152103 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 skip
11813 10:08:21.152255 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
11814 10:08:21.152394 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
11815 10:08:21.152530 arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 pass
11816 10:08:21.152737 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 skip
11817 10:08:21.152934 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
11818 10:08:21.153118 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
11819 10:08:21.153247 arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 pass
11820 10:08:21.153363 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 skip
11821 10:08:21.153480 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
11822 10:08:21.153618 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
11823 10:08:21.153753 arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 pass
11824 10:08:21.157540 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 skip
11825 10:08:21.158130 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
11826 10:08:21.158275 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
11827 10:08:21.175634 arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 pass
11828 10:08:21.176212 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 skip
11829 10:08:21.176404 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
11830 10:08:21.176619 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
11831 10:08:21.176818 arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 pass
11832 10:08:21.177057 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 skip
11833 10:08:21.177243 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
11834 10:08:21.177446 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
11835 10:08:21.177600 arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 pass
11836 10:08:21.177745 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 skip
11837 10:08:21.177880 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
11838 10:08:21.178023 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
11839 10:08:21.178218 arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 pass
11840 10:08:21.178386 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 skip
11841 10:08:21.178569 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
11842 10:08:21.178741 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
11843 10:08:21.178893 arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 pass
11844 10:08:21.179028 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 skip
11845 10:08:21.179182 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
11846 10:08:21.179323 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
11847 10:08:21.179474 arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 pass
11848 10:08:21.179682 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 skip
11849 10:08:21.179862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
11850 10:08:21.180023 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
11851 10:08:21.180157 arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 pass
11852 10:08:21.180320 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 skip
11853 10:08:21.180457 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
11854 10:08:21.180603 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
11855 10:08:21.180751 arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 pass
11856 10:08:21.180912 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 skip
11857 10:08:21.181090 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
11858 10:08:21.181290 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
11859 10:08:21.181425 arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 pass
11860 10:08:21.181718 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 skip
11861 10:08:21.181846 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
11862 10:08:21.181964 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
11863 10:08:21.182080 arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 pass
11864 10:08:21.182193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 skip
11865 10:08:21.182307 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
11866 10:08:21.182420 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
11867 10:08:21.185355 arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 pass
11868 10:08:21.185827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 skip
11869 10:08:21.186047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
11870 10:08:21.186210 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
11871 10:08:21.186364 arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 pass
11872 10:08:21.186551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 skip
11873 10:08:21.186706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
11874 10:08:21.186866 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
11875 10:08:21.187003 arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 pass
11876 10:08:21.187152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 skip
11877 10:08:21.187303 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
11878 10:08:21.187427 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
11879 10:08:21.187565 arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 pass
11880 10:08:21.187713 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 skip
11881 10:08:21.187914 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
11882 10:08:21.188155 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
11883 10:08:21.188338 arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 pass
11884 10:08:21.188493 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 skip
11885 10:08:21.188634 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
11886 10:08:21.188754 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
11887 10:08:21.188898 arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 pass
11888 10:08:21.189134 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 skip
11889 10:08:21.189297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
11890 10:08:21.189431 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
11891 10:08:21.189547 arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 pass
11892 10:08:21.189669 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 skip
11893 10:08:21.193272 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
11894 10:08:21.193698 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
11895 10:08:21.193833 arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 pass
11896 10:08:21.193966 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 skip
11897 10:08:21.194095 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
11898 10:08:21.194228 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
11899 10:08:21.194357 arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 pass
11900 10:08:21.194487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 skip
11901 10:08:21.194629 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
11902 10:08:21.194776 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
11903 10:08:21.194932 arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 pass
11904 10:08:21.195276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 skip
11905 10:08:21.195433 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
11906 10:08:21.195569 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
11907 10:08:21.195679 arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 pass
11908 10:08:21.195791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 skip
11909 10:08:21.196074 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
11910 10:08:21.196354 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
11911 10:08:21.196434 arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 pass
11912 10:08:21.196510 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 skip
11913 10:08:21.196879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
11914 10:08:21.197138 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
11915 10:08:21.197312 arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 pass
11916 10:08:21.201211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 skip
11917 10:08:21.201685 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
11918 10:08:21.201870 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
11919 10:08:21.202069 arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 pass
11920 10:08:21.202232 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 skip
11921 10:08:21.202416 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
11922 10:08:21.202584 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
11923 10:08:21.202757 arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 pass
11924 10:08:21.202946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 skip
11925 10:08:21.203115 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
11926 10:08:21.203306 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
11927 10:08:21.203478 arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 pass
11928 10:08:21.203664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 skip
11929 10:08:21.203825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
11930 10:08:21.204018 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
11931 10:08:21.204215 arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 pass
11932 10:08:21.204400 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 skip
11933 10:08:21.204607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
11934 10:08:21.204776 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
11935 10:08:21.204970 arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 pass
11936 10:08:21.205164 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 skip
11937 10:08:21.213233 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
11938 10:08:21.213735 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
11939 10:08:21.213916 arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 pass
11940 10:08:21.214076 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 skip
11941 10:08:21.214249 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
11942 10:08:21.217804 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
11943 10:08:21.217966 arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 pass
11944 10:08:21.218085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 skip
11945 10:08:21.218199 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
11946 10:08:21.218309 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
11947 10:08:21.218420 arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 pass
11948 10:08:21.218531 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 skip
11949 10:08:21.218643 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
11950 10:08:21.218751 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
11951 10:08:21.218860 arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 pass
11952 10:08:21.218969 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 skip
11953 10:08:21.219077 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
11954 10:08:21.219187 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
11955 10:08:21.219295 arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 pass
11956 10:08:21.219404 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 skip
11957 10:08:21.219514 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
11958 10:08:21.219625 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
11959 10:08:21.219732 arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 pass
11960 10:08:21.219840 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 skip
11961 10:08:21.233715 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
11962 10:08:21.234149 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
11963 10:08:21.234335 arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 pass
11964 10:08:21.234474 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 skip
11965 10:08:21.234651 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
11966 10:08:21.234816 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
11967 10:08:21.234982 arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 pass
11968 10:08:21.235153 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 skip
11969 10:08:21.235296 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
11970 10:08:21.235454 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
11971 10:08:21.235609 arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 pass
11972 10:08:21.235763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 skip
11973 10:08:21.235919 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
11974 10:08:21.236090 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
11975 10:08:21.236256 arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 pass
11976 10:08:21.236418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 skip
11977 10:08:21.236614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
11978 10:08:21.236785 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
11979 10:08:21.236955 arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 pass
11980 10:08:21.237084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 skip
11981 10:08:21.237197 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
11982 10:08:21.237310 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
11983 10:08:21.237420 arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 pass
11984 10:08:21.237532 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 skip
11985 10:08:21.237671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
11986 10:08:21.237865 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
11987 10:08:21.238070 arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 pass
11988 10:08:21.238295 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 skip
11989 10:08:21.238430 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
11990 10:08:21.241254 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
11991 10:08:21.241593 arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 pass
11992 10:08:21.241714 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 skip
11993 10:08:21.241813 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
11994 10:08:21.241925 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
11995 10:08:21.242038 arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 pass
11996 10:08:21.242148 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 skip
11997 10:08:21.242271 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
11998 10:08:21.242363 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
11999 10:08:21.242467 arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 pass
12000 10:08:21.242622 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 skip
12001 10:08:21.242758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
12002 10:08:21.242881 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
12003 10:08:21.242987 arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 pass
12004 10:08:21.243120 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 skip
12005 10:08:21.243236 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
12006 10:08:21.243384 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
12007 10:08:21.243518 arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 pass
12008 10:08:21.243680 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 skip
12009 10:08:21.243809 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
12010 10:08:21.243931 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
12011 10:08:21.244094 arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 pass
12012 10:08:21.244211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 skip
12013 10:08:21.244341 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
12014 10:08:21.244464 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
12015 10:08:21.244580 arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 pass
12016 10:08:21.244704 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 skip
12017 10:08:21.244832 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
12018 10:08:21.244971 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
12019 10:08:21.245111 arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 pass
12020 10:08:21.245262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 skip
12021 10:08:21.249157 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
12022 10:08:21.249499 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
12023 10:08:21.249635 arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 pass
12024 10:08:21.249808 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 skip
12025 10:08:21.249948 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
12026 10:08:21.250101 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
12027 10:08:21.250205 arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 pass
12028 10:08:21.250372 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 skip
12029 10:08:21.250491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
12030 10:08:21.250589 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
12031 10:08:21.250695 arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 pass
12032 10:08:21.250789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 skip
12033 10:08:21.250882 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
12034 10:08:21.251000 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
12035 10:08:21.251092 arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 pass
12036 10:08:21.251178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 skip
12037 10:08:21.251284 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
12038 10:08:21.251435 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
12039 10:08:21.251555 arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 pass
12040 10:08:21.251701 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 skip
12041 10:08:21.251818 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
12042 10:08:21.251950 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
12043 10:08:21.252048 arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 pass
12044 10:08:21.252176 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 skip
12045 10:08:21.252277 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
12046 10:08:21.252421 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
12047 10:08:21.252540 arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 pass
12048 10:08:21.252671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 skip
12049 10:08:21.252796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
12050 10:08:21.252948 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
12051 10:08:21.253051 arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 pass
12052 10:08:21.257229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 skip
12053 10:08:21.257363 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
12054 10:08:21.257661 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
12055 10:08:21.257765 arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 pass
12056 10:08:21.257852 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 skip
12057 10:08:21.257951 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
12058 10:08:21.258035 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
12059 10:08:21.258117 arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 pass
12060 10:08:21.258211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 skip
12061 10:08:21.258518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
12062 10:08:21.258640 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
12063 10:08:21.258743 arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 pass
12064 10:08:21.258839 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 skip
12065 10:08:21.259133 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
12066 10:08:21.259248 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
12067 10:08:21.259336 arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 pass
12068 10:08:21.259433 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 skip
12069 10:08:21.259715 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
12070 10:08:21.259816 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
12071 10:08:21.259902 arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 pass
12072 10:08:21.260000 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 skip
12073 10:08:21.260312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
12074 10:08:21.260483 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
12075 10:08:21.260626 arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 pass
12076 10:08:21.260805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 skip
12077 10:08:21.260966 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
12078 10:08:21.261086 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
12079 10:08:21.261177 arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 pass
12080 10:08:21.265251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 skip
12081 10:08:21.265369 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
12082 10:08:21.265707 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
12083 10:08:21.265823 arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 pass
12084 10:08:21.265922 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 skip
12085 10:08:21.266132 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
12086 10:08:21.266265 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
12087 10:08:21.266412 arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 pass
12088 10:08:21.266534 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 skip
12089 10:08:21.266716 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
12090 10:08:21.266833 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
12091 10:08:21.266923 arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 pass
12092 10:08:21.267009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 skip
12093 10:08:21.267095 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
12094 10:08:21.267183 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
12095 10:08:21.279929 arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 pass
12096 10:08:21.280104 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 skip
12097 10:08:21.280465 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
12098 10:08:21.280636 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
12099 10:08:21.280826 arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 pass
12100 10:08:21.281036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 skip
12101 10:08:21.281272 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
12102 10:08:21.281448 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
12103 10:08:21.281611 arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 pass
12104 10:08:21.281774 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 skip
12105 10:08:21.281913 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
12106 10:08:21.282110 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
12107 10:08:21.282278 arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 pass
12108 10:08:21.282441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 skip
12109 10:08:21.282597 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
12110 10:08:21.282753 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
12111 10:08:21.282910 arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 pass
12112 10:08:21.283101 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 skip
12113 10:08:21.283266 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
12114 10:08:21.283423 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
12115 10:08:21.283580 arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 pass
12116 10:08:21.283740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 skip
12117 10:08:21.283902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
12118 10:08:21.284032 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
12119 10:08:21.284160 arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 pass
12120 10:08:21.284321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 skip
12121 10:08:21.284508 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
12122 10:08:21.284668 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
12123 10:08:21.284836 arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 pass
12124 10:08:21.284996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 skip
12125 10:08:21.285164 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
12126 10:08:21.285295 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
12127 10:08:21.285433 arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 pass
12128 10:08:21.285770 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 skip
12129 10:08:21.285877 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
12130 10:08:21.285970 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
12131 10:08:21.286059 arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 pass
12132 10:08:21.286147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 skip
12133 10:08:21.286235 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
12134 10:08:21.286323 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
12135 10:08:21.286413 arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 pass
12136 10:08:21.286502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 skip
12137 10:08:21.286592 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
12138 10:08:21.289304 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
12139 10:08:21.289737 arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 pass
12140 10:08:21.289919 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 skip
12141 10:08:21.290104 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
12142 10:08:21.290293 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
12143 10:08:21.290471 arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 pass
12144 10:08:21.290653 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 skip
12145 10:08:21.290814 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
12146 10:08:21.290992 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
12147 10:08:21.291233 arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 pass
12148 10:08:21.291430 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 skip
12149 10:08:21.291622 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
12150 10:08:21.291793 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
12151 10:08:21.291966 arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 pass
12152 10:08:21.292147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 skip
12153 10:08:21.292325 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
12154 10:08:21.292468 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
12155 10:08:21.292636 arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 pass
12156 10:08:21.292814 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 skip
12157 10:08:21.293036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
12158 10:08:21.293207 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
12159 10:08:21.293335 arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 pass
12160 10:08:21.293477 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 skip
12161 10:08:21.293597 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
12162 10:08:21.293729 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
12163 10:08:21.293843 arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 pass
12164 10:08:21.293961 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 skip
12165 10:08:21.297195 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
12166 10:08:21.297520 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
12167 10:08:21.297625 arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 pass
12168 10:08:21.297729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 skip
12169 10:08:21.297841 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
12170 10:08:21.297951 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
12171 10:08:21.298045 arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 pass
12172 10:08:21.298136 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 skip
12173 10:08:21.298246 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
12174 10:08:21.298358 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
12175 10:08:21.298455 arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 pass
12176 10:08:21.298549 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 skip
12177 10:08:21.298662 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
12178 10:08:21.298757 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
12179 10:08:21.298850 arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 pass
12180 10:08:21.298963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 skip
12181 10:08:21.299059 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
12182 10:08:21.299150 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
12183 10:08:21.299258 arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 pass
12184 10:08:21.299355 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 skip
12185 10:08:21.299463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
12186 10:08:21.299561 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
12187 10:08:21.299670 arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 pass
12188 10:08:21.299773 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 skip
12189 10:08:21.299880 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
12190 10:08:21.299977 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
12191 10:08:21.300088 arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 pass
12192 10:08:21.300200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 skip
12193 10:08:21.300348 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
12194 10:08:21.300471 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
12195 10:08:21.300584 arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 pass
12196 10:08:21.300701 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 skip
12197 10:08:21.300800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
12198 10:08:21.301098 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
12199 10:08:21.301202 arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 pass
12200 10:08:21.305166 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 skip
12201 10:08:21.305504 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
12202 10:08:21.305781 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
12203 10:08:21.306023 arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 pass
12204 10:08:21.306234 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 skip
12205 10:08:21.306498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
12206 10:08:21.306708 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
12207 10:08:21.306885 arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 pass
12208 10:08:21.307079 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 skip
12209 10:08:21.307247 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
12210 10:08:21.307747 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
12211 10:08:21.307975 arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 pass
12212 10:08:21.308246 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 skip
12213 10:08:21.308466 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
12214 10:08:21.308671 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
12215 10:08:21.308851 arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 pass
12216 10:08:21.309029 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 skip
12217 10:08:21.309219 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
12218 10:08:21.309374 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
12219 10:08:21.309531 arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 pass
12220 10:08:21.309674 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 skip
12221 10:08:21.309800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
12222 10:08:21.309920 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
12223 10:08:21.310098 arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 pass
12224 10:08:21.310268 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 skip
12225 10:08:21.313200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
12226 10:08:21.313617 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
12227 10:08:21.313787 arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 pass
12228 10:08:21.313910 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 skip
12229 10:08:21.326986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
12230 10:08:21.327291 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
12231 10:08:21.327387 arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 pass
12232 10:08:21.327502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 skip
12233 10:08:21.327593 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
12234 10:08:21.327875 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
12235 10:08:21.327995 arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 pass
12236 10:08:21.328100 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 skip
12237 10:08:21.328200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
12238 10:08:21.328492 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
12239 10:08:21.328595 arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 pass
12240 10:08:21.328694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 skip
12241 10:08:21.328991 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
12242 10:08:21.329282 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
12243 10:08:21.329392 arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 pass
12244 10:08:21.329503 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 skip
12245 10:08:21.329810 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
12246 10:08:21.329902 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
12247 10:08:21.330009 arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 pass
12248 10:08:21.330108 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 skip
12249 10:08:21.330399 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
12250 10:08:21.330484 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
12251 10:08:21.330601 arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 pass
12252 10:08:21.330691 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 skip
12253 10:08:21.330802 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
12254 10:08:21.330909 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
12255 10:08:21.331193 arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 pass
12256 10:08:21.331277 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 skip
12257 10:08:21.331390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
12258 10:08:21.331482 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
12259 10:08:21.331557 arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 pass
12260 10:08:21.331646 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 skip
12261 10:08:21.331910 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
12262 10:08:21.332012 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
12263 10:08:21.332119 arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 pass
12264 10:08:21.332216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 skip
12265 10:08:21.332482 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
12266 10:08:21.332595 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
12267 10:08:21.332699 arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 pass
12268 10:08:21.332780 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 skip
12269 10:08:21.333049 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
12270 10:08:21.337183 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
12271 10:08:21.337518 arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 pass
12272 10:08:21.337723 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 skip
12273 10:08:21.337932 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
12274 10:08:21.338119 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
12275 10:08:21.338291 arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 pass
12276 10:08:21.338519 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 skip
12277 10:08:21.338707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
12278 10:08:21.338874 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
12279 10:08:21.339040 arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 pass
12280 10:08:21.339202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 skip
12281 10:08:21.339395 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
12282 10:08:21.339619 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
12283 10:08:21.339838 arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 pass
12284 10:08:21.340052 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 skip
12285 10:08:21.340245 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
12286 10:08:21.340428 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
12287 10:08:21.340638 arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 pass
12288 10:08:21.340866 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 skip
12289 10:08:21.341420 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
12290 10:08:21.341570 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
12291 10:08:21.341700 arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 pass
12292 10:08:21.341818 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 skip
12293 10:08:21.341934 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
12294 10:08:21.342049 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
12295 10:08:21.342163 arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 pass
12296 10:08:21.342305 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 skip
12297 10:08:21.342427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
12298 10:08:21.345299 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
12299 10:08:21.345423 arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 pass
12300 10:08:21.345694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 skip
12301 10:08:21.345784 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
12302 10:08:21.346052 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
12303 10:08:21.346132 arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 pass
12304 10:08:21.346197 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 skip
12305 10:08:21.346259 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
12306 10:08:21.346334 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
12307 10:08:21.346396 arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 pass
12308 10:08:21.346458 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 skip
12309 10:08:21.346532 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
12310 10:08:21.346781 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
12311 10:08:21.346850 arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 pass
12312 10:08:21.347093 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 skip
12313 10:08:21.347161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
12314 10:08:21.347224 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
12315 10:08:21.347297 arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 pass
12316 10:08:21.347362 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 skip
12317 10:08:21.347612 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
12318 10:08:21.347683 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
12319 10:08:21.347747 arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 pass
12320 10:08:21.347825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 skip
12321 10:08:21.348069 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
12322 10:08:21.348138 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
12323 10:08:21.348212 arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 pass
12324 10:08:21.348286 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 skip
12325 10:08:21.348536 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
12326 10:08:21.348617 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
12327 10:08:21.348682 arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 pass
12328 10:08:21.348756 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 skip
12329 10:08:21.349008 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
12330 10:08:21.353275 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
12331 10:08:21.353742 arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 pass
12332 10:08:21.353895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 skip
12333 10:08:21.353998 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
12334 10:08:21.354093 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
12335 10:08:21.354207 arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 pass
12336 10:08:21.354304 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 skip
12337 10:08:21.354427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
12338 10:08:21.354553 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
12339 10:08:21.354674 arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 pass
12340 10:08:21.354776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 skip
12341 10:08:21.354877 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
12342 10:08:21.354994 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
12343 10:08:21.355092 arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 pass
12344 10:08:21.355186 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 skip
12345 10:08:21.355298 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
12346 10:08:21.355391 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
12347 10:08:21.355485 arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 pass
12348 10:08:21.355598 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 skip
12349 10:08:21.355697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
12350 10:08:21.355807 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
12351 10:08:21.355907 arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 pass
12352 10:08:21.356001 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 skip
12353 10:08:21.356111 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
12354 10:08:21.356210 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
12355 10:08:21.356304 arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 pass
12356 10:08:21.356415 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 skip
12357 10:08:21.356508 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
12358 10:08:21.356613 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
12359 10:08:21.356709 arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 pass
12360 10:08:21.356816 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 skip
12361 10:08:21.356921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
12362 10:08:21.357214 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
12363 10:08:21.374154 arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 pass
12364 10:08:21.374499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 skip
12365 10:08:21.374588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
12366 10:08:21.374665 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
12367 10:08:21.374757 arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 pass
12368 10:08:21.374853 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 skip
12369 10:08:21.374942 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
12370 10:08:21.375018 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
12371 10:08:21.375105 arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 pass
12372 10:08:21.375199 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 skip
12373 10:08:21.375318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
12374 10:08:21.375631 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
12375 10:08:21.375732 arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 pass
12376 10:08:21.375828 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 skip
12377 10:08:21.375931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
12378 10:08:21.376028 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
12379 10:08:21.376135 arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 pass
12380 10:08:21.376427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 skip
12381 10:08:21.376547 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
12382 10:08:21.376654 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
12383 10:08:21.376924 arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 pass
12384 10:08:21.377036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 skip
12385 10:08:21.381170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
12386 10:08:21.381468 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
12387 10:08:21.381570 arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 pass
12388 10:08:21.381696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 skip
12389 10:08:21.381795 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
12390 10:08:21.381905 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
12391 10:08:21.381994 arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 pass
12392 10:08:21.382085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 skip
12393 10:08:21.382335 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
12394 10:08:21.382402 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
12395 10:08:21.382471 arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 pass
12396 10:08:21.382542 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 skip
12397 10:08:21.382796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
12398 10:08:21.382898 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
12399 10:08:21.382992 arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 pass
12400 10:08:21.383290 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 skip
12401 10:08:21.383378 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
12402 10:08:21.383483 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
12403 10:08:21.383556 arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 pass
12404 10:08:21.383836 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 skip
12405 10:08:21.383922 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
12406 10:08:21.384039 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
12407 10:08:21.384131 arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 pass
12408 10:08:21.384256 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 skip
12409 10:08:21.384382 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
12410 10:08:21.384735 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
12411 10:08:21.384830 arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 pass
12412 10:08:21.384935 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 skip
12413 10:08:21.389152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
12414 10:08:21.389472 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
12415 10:08:21.389572 arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 pass
12416 10:08:21.389869 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 skip
12417 10:08:21.389977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
12418 10:08:21.390106 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
12419 10:08:21.390175 arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 pass
12420 10:08:21.390251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 skip
12421 10:08:21.390721 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
12422 10:08:21.390812 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
12423 10:08:21.390915 arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 pass
12424 10:08:21.391004 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 skip
12425 10:08:21.391293 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
12426 10:08:21.391377 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
12427 10:08:21.391487 arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 pass
12428 10:08:21.391590 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 skip
12429 10:08:21.391691 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
12430 10:08:21.391789 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
12431 10:08:21.392079 arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 pass
12432 10:08:21.392183 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 skip
12433 10:08:21.392284 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
12434 10:08:21.392387 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
12435 10:08:21.392675 arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 pass
12436 10:08:21.392787 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 skip
12437 10:08:21.392888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
12438 10:08:21.393185 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
12439 10:08:21.397328 arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 pass
12440 10:08:21.397444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 skip
12441 10:08:21.397533 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
12442 10:08:21.397812 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
12443 10:08:21.397895 arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 pass
12444 10:08:21.398010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 skip
12445 10:08:21.398119 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
12446 10:08:21.398434 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
12447 10:08:21.398559 arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 pass
12448 10:08:21.398664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 skip
12449 10:08:21.398925 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
12450 10:08:21.399021 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
12451 10:08:21.399293 arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 pass
12452 10:08:21.399365 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 skip
12453 10:08:21.399457 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
12454 10:08:21.399540 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
12455 10:08:21.399624 arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 pass
12456 10:08:21.399896 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 skip
12457 10:08:21.399999 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
12458 10:08:21.400096 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
12459 10:08:21.400182 arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 pass
12460 10:08:21.400288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 skip
12461 10:08:21.400403 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
12462 10:08:21.400497 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
12463 10:08:21.400702 arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 pass
12464 10:08:21.400823 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 skip
12465 10:08:21.401117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
12466 10:08:21.405126 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
12467 10:08:21.405422 arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 pass
12468 10:08:21.405523 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 skip
12469 10:08:21.405652 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
12470 10:08:21.405750 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
12471 10:08:21.405842 arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 pass
12472 10:08:21.405970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 skip
12473 10:08:21.406267 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
12474 10:08:21.406393 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
12475 10:08:21.406497 arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 pass
12476 10:08:21.406785 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 skip
12477 10:08:21.406906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
12478 10:08:21.407037 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
12479 10:08:21.407338 arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 pass
12480 10:08:21.407439 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 skip
12481 10:08:21.407540 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
12482 10:08:21.407640 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
12483 10:08:21.407739 arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 pass
12484 10:08:21.408029 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 skip
12485 10:08:21.408118 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
12486 10:08:21.408218 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
12487 10:08:21.408511 arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 pass
12488 10:08:21.408625 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 skip
12489 10:08:21.408725 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
12490 10:08:21.408900 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
12491 10:08:21.413153 arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 pass
12492 10:08:21.413447 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 skip
12493 10:08:21.413749 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
12494 10:08:21.413850 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
12495 10:08:21.413951 arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 pass
12496 10:08:21.414051 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 skip
12497 10:08:21.424225 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
12498 10:08:21.424820 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
12499 10:08:21.424945 arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 pass
12500 10:08:21.425036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 skip
12501 10:08:21.425117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
12502 10:08:21.425221 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
12503 10:08:21.425322 arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 pass
12504 10:08:21.425430 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 skip
12505 10:08:21.425507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
12506 10:08:21.425598 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
12507 10:08:21.425696 arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 pass
12508 10:08:21.425805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 skip
12509 10:08:21.425878 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
12510 10:08:21.425968 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
12511 10:08:21.426266 arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 pass
12512 10:08:21.426359 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 skip
12513 10:08:21.426451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
12514 10:08:21.426530 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
12515 10:08:21.426609 arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 pass
12516 10:08:21.426683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 skip
12517 10:08:21.427032 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
12518 10:08:21.427267 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
12519 10:08:21.427369 arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 pass
12520 10:08:21.427457 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 skip
12521 10:08:21.427556 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
12522 10:08:21.427641 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
12523 10:08:21.427739 arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 pass
12524 10:08:21.427837 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 skip
12525 10:08:21.428121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
12526 10:08:21.428223 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
12527 10:08:21.428323 arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 pass
12528 10:08:21.428617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 skip
12529 10:08:21.428733 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
12530 10:08:21.428820 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
12531 10:08:21.428919 arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 pass
12532 10:08:21.433566 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 skip
12533 10:08:21.433761 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
12534 10:08:21.433952 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
12535 10:08:21.434169 arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 pass
12536 10:08:21.434629 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 skip
12537 10:08:21.434825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
12538 10:08:21.434990 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
12539 10:08:21.435148 arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 pass
12540 10:08:21.435299 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 skip
12541 10:08:21.435451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
12542 10:08:21.435606 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
12543 10:08:21.435808 arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 pass
12544 10:08:21.436016 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 skip
12545 10:08:21.436224 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
12546 10:08:21.436443 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
12547 10:08:21.436646 arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 pass
12548 10:08:21.436860 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 skip
12549 10:08:21.437067 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
12550 10:08:21.437208 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
12551 10:08:21.437355 arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 pass
12552 10:08:21.437477 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 skip
12553 10:08:21.437591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
12554 10:08:21.437774 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
12555 10:08:21.437970 arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 pass
12556 10:08:21.438152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 skip
12557 10:08:21.438333 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
12558 10:08:21.438493 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
12559 10:08:21.438634 arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 pass
12560 10:08:21.441379 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 skip
12561 10:08:21.441823 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
12562 10:08:21.442034 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
12563 10:08:21.442250 arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 pass
12564 10:08:21.442486 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 skip
12565 10:08:21.442685 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
12566 10:08:21.442887 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
12567 10:08:21.443086 arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 pass
12568 10:08:21.443268 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 skip
12569 10:08:21.443484 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
12570 10:08:21.443683 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
12571 10:08:21.443895 arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 pass
12572 10:08:21.444096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 skip
12573 10:08:21.444315 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
12574 10:08:21.444522 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
12575 10:08:21.444778 arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 pass
12576 10:08:21.444994 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 skip
12577 10:08:21.445177 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
12578 10:08:21.445308 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
12579 10:08:21.445423 arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 pass
12580 10:08:21.445537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 skip
12581 10:08:21.445664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
12582 10:08:21.445781 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
12583 10:08:21.445892 arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 pass
12584 10:08:21.446033 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 skip
12585 10:08:21.446152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
12586 10:08:21.449215 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
12587 10:08:21.449630 arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 pass
12588 10:08:21.449833 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 skip
12589 10:08:21.450010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
12590 10:08:21.450209 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
12591 10:08:21.450380 arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 pass
12592 10:08:21.450540 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 skip
12593 10:08:21.450696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
12594 10:08:21.450886 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
12595 10:08:21.451054 arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 pass
12596 10:08:21.451218 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 skip
12597 10:08:21.451405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
12598 10:08:21.451642 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
12599 10:08:21.451822 arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 pass
12600 10:08:21.451993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 skip
12601 10:08:21.452160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
12602 10:08:21.452317 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
12603 10:08:21.452509 arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 pass
12604 10:08:21.452729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 skip
12605 10:08:21.452897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
12606 10:08:21.453090 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
12607 10:08:21.453223 arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 pass
12608 10:08:21.453337 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 skip
12609 10:08:21.453451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
12610 10:08:21.453564 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
12611 10:08:21.453733 arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 pass
12612 10:08:21.453973 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 skip
12613 10:08:21.454157 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
12614 10:08:21.457183 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
12615 10:08:21.457614 arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 pass
12616 10:08:21.457806 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 skip
12617 10:08:21.458026 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
12618 10:08:21.458247 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
12619 10:08:21.458429 arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 pass
12620 10:08:21.458594 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 skip
12621 10:08:21.458756 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
12622 10:08:21.458958 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
12623 10:08:21.459126 arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 pass
12624 10:08:21.459288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 skip
12625 10:08:21.459449 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
12626 10:08:21.459590 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
12627 10:08:21.459747 arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 pass
12628 10:08:21.459865 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 skip
12629 10:08:21.459999 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
12630 10:08:21.460133 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
12631 10:08:21.472958 arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 pass
12632 10:08:21.473214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 skip
12633 10:08:21.473619 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
12634 10:08:21.473821 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
12635 10:08:21.473972 arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 pass
12636 10:08:21.474156 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 skip
12637 10:08:21.474308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
12638 10:08:21.474434 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
12639 10:08:21.474557 arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 pass
12640 10:08:21.474707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 skip
12641 10:08:21.474845 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
12642 10:08:21.474991 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
12643 10:08:21.475166 arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 pass
12644 10:08:21.475500 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 skip
12645 10:08:21.475724 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
12646 10:08:21.475921 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
12647 10:08:21.476062 arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 pass
12648 10:08:21.476187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 skip
12649 10:08:21.476308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
12650 10:08:21.476458 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
12651 10:08:21.476586 arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 pass
12652 10:08:21.476765 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 skip
12653 10:08:21.476929 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
12654 10:08:21.477086 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
12655 10:08:21.477211 arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 pass
12656 10:08:21.477325 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 skip
12657 10:08:21.481316 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
12658 10:08:21.481699 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
12659 10:08:21.481838 arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 pass
12660 10:08:21.481987 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 skip
12661 10:08:21.482114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
12662 10:08:21.482262 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
12663 10:08:21.482391 arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 pass
12664 10:08:21.482541 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 skip
12665 10:08:21.482687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
12666 10:08:21.483030 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
12667 10:08:21.483168 arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 pass
12668 10:08:21.483312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 skip
12669 10:08:21.483438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
12670 10:08:21.483590 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
12671 10:08:21.483714 arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 pass
12672 10:08:21.483859 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 skip
12673 10:08:21.484003 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
12674 10:08:21.484158 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
12675 10:08:21.484492 arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 pass
12676 10:08:21.484635 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 skip
12677 10:08:21.484850 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
12678 10:08:21.485007 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
12679 10:08:21.485177 arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 pass
12680 10:08:21.485345 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 skip
12681 10:08:21.485504 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
12682 10:08:21.489289 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
12683 10:08:21.489682 arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 pass
12684 10:08:21.489820 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 skip
12685 10:08:21.489963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
12686 10:08:21.490091 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
12687 10:08:21.490235 arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 pass
12688 10:08:21.490359 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 skip
12689 10:08:21.490531 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
12690 10:08:21.490717 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
12691 10:08:21.490885 arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 pass
12692 10:08:21.491017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 skip
12693 10:08:21.491166 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
12694 10:08:21.491294 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
12695 10:08:21.491443 arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 pass
12696 10:08:21.491564 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 skip
12697 10:08:21.491715 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
12698 10:08:21.491862 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
12699 10:08:21.492012 arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 pass
12700 10:08:21.492161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 skip
12701 10:08:21.492518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
12702 10:08:21.492675 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
12703 10:08:21.492824 arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 pass
12704 10:08:21.492970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 skip
12705 10:08:21.493187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
12706 10:08:21.497376 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
12707 10:08:21.498026 arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 pass
12708 10:08:21.498461 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 skip
12709 10:08:21.498708 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
12710 10:08:21.498908 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
12711 10:08:21.499055 arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 pass
12712 10:08:21.499216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 skip
12713 10:08:21.499365 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
12714 10:08:21.499552 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
12715 10:08:21.499745 arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 pass
12716 10:08:21.499985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 skip
12717 10:08:21.500180 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
12718 10:08:21.500363 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
12719 10:08:21.500558 arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 pass
12720 10:08:21.500867 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 skip
12721 10:08:21.501119 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
12722 10:08:21.501274 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
12723 10:08:21.501396 arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 pass
12724 10:08:21.501568 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 skip
12725 10:08:21.501740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
12726 10:08:21.501927 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
12727 10:08:21.502099 arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 pass
12728 10:08:21.505748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 skip
12729 10:08:21.506017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
12730 10:08:21.506479 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
12731 10:08:21.506685 arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 pass
12732 10:08:21.506854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 skip
12733 10:08:21.507017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
12734 10:08:21.507409 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
12735 10:08:21.507593 arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 pass
12736 10:08:21.507755 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 skip
12737 10:08:21.507988 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
12738 10:08:21.508166 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
12739 10:08:21.508326 arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 pass
12740 10:08:21.508483 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 skip
12741 10:08:21.508689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
12742 10:08:21.508857 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
12743 10:08:21.509016 arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 pass
12744 10:08:21.509179 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 skip
12745 10:08:21.509337 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
12746 10:08:21.509495 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
12747 10:08:21.509669 arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 pass
12748 10:08:21.509860 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 skip
12749 10:08:21.510024 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
12750 10:08:21.513273 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
12751 10:08:21.513729 arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 pass
12752 10:08:21.513912 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 skip
12753 10:08:21.514130 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
12754 10:08:21.514294 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
12755 10:08:21.514431 arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 pass
12756 10:08:21.515279 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 skip
12757 10:08:21.515479 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
12758 10:08:21.515648 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
12759 10:08:21.515791 arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 pass
12760 10:08:21.515906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 skip
12761 10:08:21.516020 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
12762 10:08:21.516361 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
12763 10:08:21.516547 arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 pass
12764 10:08:21.516723 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 skip
12765 10:08:21.538899 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
12766 10:08:21.539383 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
12767 10:08:21.539490 arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 pass
12768 10:08:21.539575 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 skip
12769 10:08:21.539656 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
12770 10:08:21.539752 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
12771 10:08:21.539852 arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 pass
12772 10:08:21.540172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 skip
12773 10:08:21.540371 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
12774 10:08:21.540558 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
12775 10:08:21.540728 arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 pass
12776 10:08:21.540915 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 skip
12777 10:08:21.541071 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
12778 10:08:21.541252 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
12779 10:08:21.541405 arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 pass
12780 10:08:21.541582 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 skip
12781 10:08:21.541751 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
12782 10:08:21.541900 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
12783 10:08:21.542078 arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 pass
12784 10:08:21.542223 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 skip
12785 10:08:21.542334 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
12786 10:08:21.542464 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
12787 10:08:21.542578 arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 pass
12788 10:08:21.542708 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 skip
12789 10:08:21.542839 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
12790 10:08:21.543192 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
12791 10:08:21.543352 arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 pass
12792 10:08:21.543687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 skip
12793 10:08:21.543809 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
12794 10:08:21.543952 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
12795 10:08:21.544311 arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 pass
12796 10:08:21.544454 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 skip
12797 10:08:21.544851 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
12798 10:08:21.545122 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
12799 10:08:21.545249 arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 pass
12800 10:08:21.545386 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 skip
12801 10:08:21.549480 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
12802 10:08:21.550066 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
12803 10:08:21.550174 arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 pass
12804 10:08:21.550260 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 skip
12805 10:08:21.550355 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
12806 10:08:21.550436 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
12807 10:08:21.550528 arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 pass
12808 10:08:21.550621 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 skip
12809 10:08:21.550898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
12810 10:08:21.551168 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
12811 10:08:21.551251 arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 pass
12812 10:08:21.551523 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 skip
12813 10:08:21.551606 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
12814 10:08:21.551697 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
12815 10:08:21.551789 arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 pass
12816 10:08:21.552229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 skip
12817 10:08:21.552324 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
12818 10:08:21.552415 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
12819 10:08:21.552684 arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 pass
12820 10:08:21.553001 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 skip
12821 10:08:21.553088 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
12822 10:08:21.561576 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
12823 10:08:21.561763 arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 pass
12824 10:08:21.562041 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 skip
12825 10:08:21.562206 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
12826 10:08:21.562310 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
12827 10:08:21.562397 arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 pass
12828 10:08:21.562500 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 skip
12829 10:08:21.562585 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
12830 10:08:21.562688 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
12831 10:08:21.562776 arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 pass
12832 10:08:21.562877 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 skip
12833 10:08:21.562996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
12834 10:08:21.563288 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
12835 10:08:21.563396 arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 pass
12836 10:08:21.563734 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 skip
12837 10:08:21.563906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
12838 10:08:21.564067 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
12839 10:08:21.564200 arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 pass
12840 10:08:21.564350 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 skip
12841 10:08:21.564480 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
12842 10:08:21.564626 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
12843 10:08:21.564756 arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 pass
12844 10:08:21.564954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 skip
12845 10:08:21.565095 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
12846 10:08:21.569559 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
12847 10:08:21.569779 arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 pass
12848 10:08:21.570198 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 skip
12849 10:08:21.570368 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
12850 10:08:21.570493 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
12851 10:08:21.570610 arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 pass
12852 10:08:21.570991 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 skip
12853 10:08:21.571146 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
12854 10:08:21.571288 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
12855 10:08:21.571469 arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 pass
12856 10:08:21.571645 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 skip
12857 10:08:21.571806 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
12858 10:08:21.571984 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
12859 10:08:21.572222 arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 pass
12860 10:08:21.572392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 skip
12861 10:08:21.572552 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
12862 10:08:21.572708 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
12863 10:08:21.572862 arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 pass
12864 10:08:21.573016 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 skip
12865 10:08:21.573148 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
12866 10:08:21.573295 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
12867 10:08:21.573419 arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 pass
12868 10:08:21.573536 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 skip
12869 10:08:21.573664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
12870 10:08:21.573781 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
12871 10:08:21.573896 arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 pass
12872 10:08:21.574011 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 skip
12873 10:08:21.577428 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
12874 10:08:21.577894 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
12875 10:08:21.578086 arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 pass
12876 10:08:21.578272 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 skip
12877 10:08:21.578467 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
12878 10:08:21.578629 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
12879 10:08:21.578846 arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 pass
12880 10:08:21.579024 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 skip
12881 10:08:21.579243 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
12882 10:08:21.579460 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
12883 10:08:21.579673 arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 pass
12884 10:08:21.579871 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 skip
12885 10:08:21.580127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
12886 10:08:21.580322 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
12887 10:08:21.580530 arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 pass
12888 10:08:21.580734 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 skip
12889 10:08:21.580941 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
12890 10:08:21.581107 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
12891 10:08:21.581236 arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 pass
12892 10:08:21.581355 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 skip
12893 10:08:21.581500 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
12894 10:08:21.581623 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
12895 10:08:21.581755 arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 pass
12896 10:08:21.581870 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 skip
12897 10:08:21.581985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
12898 10:08:21.585283 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
12899 10:08:21.596899 arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 pass
12900 10:08:21.597261 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 skip
12901 10:08:21.597371 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
12902 10:08:21.598001 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
12903 10:08:21.598102 arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 pass
12904 10:08:21.598183 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 skip
12905 10:08:21.598261 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
12906 10:08:21.598338 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
12907 10:08:21.598658 arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 pass
12908 10:08:21.598793 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 skip
12909 10:08:21.598916 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
12910 10:08:21.599047 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
12911 10:08:21.599194 arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 pass
12912 10:08:21.599315 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 skip
12913 10:08:21.599398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
12914 10:08:21.599478 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
12915 10:08:21.599555 arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 pass
12916 10:08:21.599631 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 skip
12917 10:08:21.599722 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
12918 10:08:21.599800 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
12919 10:08:21.599876 arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 pass
12920 10:08:21.599950 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 skip
12921 10:08:21.600039 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
12922 10:08:21.600128 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
12923 10:08:21.600417 arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 pass
12924 10:08:21.600513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 skip
12925 10:08:21.600592 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
12926 10:08:21.600683 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
12927 10:08:21.600762 arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 pass
12928 10:08:21.600858 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 skip
12929 10:08:21.605278 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
12930 10:08:21.605588 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
12931 10:08:21.605692 arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 pass
12932 10:08:21.605772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 skip
12933 10:08:21.605862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
12934 10:08:21.606123 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
12935 10:08:21.606249 arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 pass
12936 10:08:21.606334 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 skip
12937 10:08:21.606426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
12938 10:08:21.606505 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
12939 10:08:21.606594 arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 pass
12940 10:08:21.606879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 skip
12941 10:08:21.606988 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
12942 10:08:21.607262 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
12943 10:08:21.607357 arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 pass
12944 10:08:21.607462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 skip
12945 10:08:21.607741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
12946 10:08:21.607883 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
12947 10:08:21.607964 arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 pass
12948 10:08:21.608054 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 skip
12949 10:08:21.608132 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
12950 10:08:21.608222 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
12951 10:08:21.608487 arm64_sve-ptrace pass
12952 10:08:21.608568 arm64_sve-probe-vls_Enumerated_16_vector_lengths pass
12953 10:08:21.608658 arm64_sve-probe-vls_All_vector_lengths_valid pass
12954 10:08:21.608737 arm64_sve-probe-vls pass
12955 10:08:21.608826 arm64_vec-syscfg_SVE_default_vector_length_64 pass
12956 10:08:21.608916 arm64_vec-syscfg_SVE_minimum_vector_length_16 pass
12957 10:08:21.608994 arm64_vec-syscfg_SVE_maximum_vector_length_256 pass
12958 10:08:21.609084 arm64_vec-syscfg_SVE_current_VL_is_64 pass
12959 10:08:21.613221 arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 pass
12960 10:08:21.613616 arm64_vec-syscfg_SVE_prctl_set_min_max pass
12961 10:08:21.613756 arm64_vec-syscfg_SVE_vector_length_used_default pass
12962 10:08:21.613847 arm64_vec-syscfg_SVE_vector_length_was_inherited pass
12963 10:08:21.613933 arm64_vec-syscfg_SVE_vector_length_set_on_exec pass
12964 10:08:21.614040 arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors pass
12965 10:08:21.614130 arm64_vec-syscfg_SME_default_vector_length_32 pass
12966 10:08:21.614217 arm64_vec-syscfg_SME_minimum_vector_length_16 pass
12967 10:08:21.614300 arm64_vec-syscfg_SME_maximum_vector_length_256 pass
12968 10:08:21.614399 arm64_vec-syscfg_SME_current_VL_is_32 pass
12969 10:08:21.614482 arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 pass
12970 10:08:21.614563 arm64_vec-syscfg_SME_prctl_set_min_max pass
12971 10:08:21.614642 arm64_vec-syscfg_SME_vector_length_used_default pass
12972 10:08:21.614736 arm64_vec-syscfg_SME_vector_length_was_inherited pass
12973 10:08:21.614822 arm64_vec-syscfg_SME_vector_length_set_on_exec pass
12974 10:08:21.614903 arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors pass
12975 10:08:21.614986 arm64_vec-syscfg pass
12976 10:08:21.615089 arm64_za-fork_fork_test pass
12977 10:08:21.615178 arm64_za-fork pass
12978 10:08:21.615263 arm64_za-ptrace_Set_VL_16 pass
12979 10:08:21.615348 arm64_za-ptrace_Disabled_ZA_for_VL_16 pass
12980 10:08:21.615432 arm64_za-ptrace_Data_match_for_VL_16 pass
12981 10:08:21.615535 arm64_za-ptrace_Set_VL_32 pass
12982 10:08:21.615624 arm64_za-ptrace_Disabled_ZA_for_VL_32 pass
12983 10:08:21.615708 arm64_za-ptrace_Data_match_for_VL_32 pass
12984 10:08:21.615791 arm64_za-ptrace_Set_VL_48 pass
12985 10:08:21.615892 arm64_za-ptrace_Disabled_ZA_for_VL_48 skip
12986 10:08:21.615977 arm64_za-ptrace_Get_and_set_data_for_VL_48 skip
12987 10:08:21.616061 arm64_za-ptrace_Set_VL_64 pass
12988 10:08:21.616149 arm64_za-ptrace_Disabled_ZA_for_VL_64 pass
12989 10:08:21.616237 arm64_za-ptrace_Data_match_for_VL_64 pass
12990 10:08:21.616325 arm64_za-ptrace_Set_VL_80 pass
12991 10:08:21.616433 arm64_za-ptrace_Disabled_ZA_for_VL_80 skip
12992 10:08:21.616524 arm64_za-ptrace_Get_and_set_data_for_VL_80 skip
12993 10:08:21.616611 arm64_za-ptrace_Set_VL_96 pass
12994 10:08:21.616694 arm64_za-ptrace_Disabled_ZA_for_VL_96 skip
12995 10:08:21.616776 arm64_za-ptrace_Get_and_set_data_for_VL_96 skip
12996 10:08:21.616878 arm64_za-ptrace_Set_VL_112 pass
12997 10:08:21.616963 arm64_za-ptrace_Disabled_ZA_for_VL_112 skip
12998 10:08:21.617066 arm64_za-ptrace_Get_and_set_data_for_VL_112 skip
12999 10:08:21.617153 arm64_za-ptrace_Set_VL_128 pass
13000 10:08:21.617238 arm64_za-ptrace_Disabled_ZA_for_VL_128 pass
13001 10:08:21.617321 arm64_za-ptrace_Data_match_for_VL_128 pass
13002 10:08:21.617404 arm64_za-ptrace_Set_VL_144 pass
13003 10:08:21.621501 arm64_za-ptrace_Disabled_ZA_for_VL_144 skip
13004 10:08:21.621721 arm64_za-ptrace_Get_and_set_data_for_VL_144 skip
13005 10:08:21.621885 arm64_za-ptrace_Set_VL_160 pass
13006 10:08:21.622039 arm64_za-ptrace_Disabled_ZA_for_VL_160 skip
13007 10:08:21.622228 arm64_za-ptrace_Get_and_set_data_for_VL_160 skip
13008 10:08:21.622682 arm64_za-ptrace_Set_VL_176 pass
13009 10:08:21.622839 arm64_za-ptrace_Disabled_ZA_for_VL_176 skip
13010 10:08:21.622964 arm64_za-ptrace_Get_and_set_data_for_VL_176 skip
13011 10:08:21.623080 arm64_za-ptrace_Set_VL_192 pass
13012 10:08:21.623199 arm64_za-ptrace_Disabled_ZA_for_VL_192 skip
13013 10:08:21.623312 arm64_za-ptrace_Get_and_set_data_for_VL_192 skip
13014 10:08:21.623432 arm64_za-ptrace_Set_VL_208 pass
13015 10:08:21.623550 arm64_za-ptrace_Disabled_ZA_for_VL_208 skip
13016 10:08:21.623664 arm64_za-ptrace_Get_and_set_data_for_VL_208 skip
13017 10:08:21.623780 arm64_za-ptrace_Set_VL_224 pass
13018 10:08:21.623894 arm64_za-ptrace_Disabled_ZA_for_VL_224 skip
13019 10:08:21.624009 arm64_za-ptrace_Get_and_set_data_for_VL_224 skip
13020 10:08:21.624124 arm64_za-ptrace_Set_VL_240 pass
13021 10:08:21.624239 arm64_za-ptrace_Disabled_ZA_for_VL_240 skip
13022 10:08:21.624354 arm64_za-ptrace_Get_and_set_data_for_VL_240 skip
13023 10:08:21.624466 arm64_za-ptrace_Set_VL_256 pass
13024 10:08:21.624581 arm64_za-ptrace_Disabled_ZA_for_VL_256 pass
13025 10:08:21.625009 arm64_za-ptrace_Data_match_for_VL_256 pass
13026 10:08:21.625164 arm64_za-ptrace_Set_VL_272 pass
13027 10:08:21.625284 arm64_za-ptrace_Disabled_ZA_for_VL_272 skip
13028 10:08:21.625401 arm64_za-ptrace_Get_and_set_data_for_VL_272 skip
13029 10:08:21.625522 arm64_za-ptrace_Set_VL_288 pass
13030 10:08:21.625637 arm64_za-ptrace_Disabled_ZA_for_VL_288 skip
13031 10:08:21.625766 arm64_za-ptrace_Get_and_set_data_for_VL_288 skip
13032 10:08:21.625882 arm64_za-ptrace_Set_VL_304 pass
13033 10:08:21.625997 arm64_za-ptrace_Disabled_ZA_for_VL_304 skip
13034 10:08:21.626111 arm64_za-ptrace_Get_and_set_data_for_VL_304 skip
13035 10:08:21.626227 arm64_za-ptrace_Set_VL_320 pass
13036 10:08:21.626341 arm64_za-ptrace_Disabled_ZA_for_VL_320 skip
13037 10:08:21.626455 arm64_za-ptrace_Get_and_set_data_for_VL_320 skip
13038 10:08:21.626569 arm64_za-ptrace_Set_VL_336 pass
13039 10:08:21.626683 arm64_za-ptrace_Disabled_ZA_for_VL_336 skip
13040 10:08:21.626799 arm64_za-ptrace_Get_and_set_data_for_VL_336 skip
13041 10:08:21.626914 arm64_za-ptrace_Set_VL_352 pass
13042 10:08:21.627028 arm64_za-ptrace_Disabled_ZA_for_VL_352 skip
13043 10:08:21.627141 arm64_za-ptrace_Get_and_set_data_for_VL_352 skip
13044 10:08:21.627254 arm64_za-ptrace_Set_VL_368 pass
13045 10:08:21.627368 arm64_za-ptrace_Disabled_ZA_for_VL_368 skip
13046 10:08:21.627482 arm64_za-ptrace_Get_and_set_data_for_VL_368 skip
13047 10:08:21.627597 arm64_za-ptrace_Set_VL_384 pass
13048 10:08:21.627712 arm64_za-ptrace_Disabled_ZA_for_VL_384 skip
13049 10:08:21.627826 arm64_za-ptrace_Get_and_set_data_for_VL_384 skip
13050 10:08:21.627940 arm64_za-ptrace_Set_VL_400 pass
13051 10:08:21.628053 arm64_za-ptrace_Disabled_ZA_for_VL_400 skip
13052 10:08:21.628378 arm64_za-ptrace_Get_and_set_data_for_VL_400 skip
13053 10:08:21.628505 arm64_za-ptrace_Set_VL_416 pass
13054 10:08:21.629364 arm64_za-ptrace_Disabled_ZA_for_VL_416 skip
13055 10:08:21.629848 arm64_za-ptrace_Get_and_set_data_for_VL_416 skip
13056 10:08:21.630036 arm64_za-ptrace_Set_VL_432 pass
13057 10:08:21.630207 arm64_za-ptrace_Disabled_ZA_for_VL_432 skip
13058 10:08:21.630368 arm64_za-ptrace_Get_and_set_data_for_VL_432 skip
13059 10:08:21.630498 arm64_za-ptrace_Set_VL_448 pass
13060 10:08:21.630651 arm64_za-ptrace_Disabled_ZA_for_VL_448 skip
13061 10:08:21.630769 arm64_za-ptrace_Get_and_set_data_for_VL_448 skip
13062 10:08:21.630906 arm64_za-ptrace_Set_VL_464 pass
13063 10:08:21.631044 arm64_za-ptrace_Disabled_ZA_for_VL_464 skip
13064 10:08:21.631174 arm64_za-ptrace_Get_and_set_data_for_VL_464 skip
13065 10:08:21.631282 arm64_za-ptrace_Set_VL_480 pass
13066 10:08:21.631389 arm64_za-ptrace_Disabled_ZA_for_VL_480 skip
13067 10:08:21.631498 arm64_za-ptrace_Get_and_set_data_for_VL_480 skip
13068 10:08:21.631603 arm64_za-ptrace_Set_VL_496 pass
13069 10:08:21.631710 arm64_za-ptrace_Disabled_ZA_for_VL_496 skip
13070 10:08:21.650129 arm64_za-ptrace_Get_and_set_data_for_VL_496 skip
13071 10:08:21.650346 arm64_za-ptrace_Set_VL_512 pass
13072 10:08:21.650431 arm64_za-ptrace_Disabled_ZA_for_VL_512 skip
13073 10:08:21.650718 arm64_za-ptrace_Get_and_set_data_for_VL_512 skip
13074 10:08:21.650819 arm64_za-ptrace_Set_VL_528 pass
13075 10:08:21.650900 arm64_za-ptrace_Disabled_ZA_for_VL_528 skip
13076 10:08:21.650976 arm64_za-ptrace_Get_and_set_data_for_VL_528 skip
13077 10:08:21.651052 arm64_za-ptrace_Set_VL_544 pass
13078 10:08:21.651127 arm64_za-ptrace_Disabled_ZA_for_VL_544 skip
13079 10:08:21.651203 arm64_za-ptrace_Get_and_set_data_for_VL_544 skip
13080 10:08:21.651294 arm64_za-ptrace_Set_VL_560 pass
13081 10:08:21.651373 arm64_za-ptrace_Disabled_ZA_for_VL_560 skip
13082 10:08:21.651448 arm64_za-ptrace_Get_and_set_data_for_VL_560 skip
13083 10:08:21.651524 arm64_za-ptrace_Set_VL_576 pass
13084 10:08:21.651599 arm64_za-ptrace_Disabled_ZA_for_VL_576 skip
13085 10:08:21.651674 arm64_za-ptrace_Get_and_set_data_for_VL_576 skip
13086 10:08:21.651750 arm64_za-ptrace_Set_VL_592 pass
13087 10:08:21.651842 arm64_za-ptrace_Disabled_ZA_for_VL_592 skip
13088 10:08:21.651920 arm64_za-ptrace_Get_and_set_data_for_VL_592 skip
13089 10:08:21.651995 arm64_za-ptrace_Set_VL_608 pass
13090 10:08:21.652070 arm64_za-ptrace_Disabled_ZA_for_VL_608 skip
13091 10:08:21.652145 arm64_za-ptrace_Get_and_set_data_for_VL_608 skip
13092 10:08:21.652219 arm64_za-ptrace_Set_VL_624 pass
13093 10:08:21.652308 arm64_za-ptrace_Disabled_ZA_for_VL_624 skip
13094 10:08:21.652385 arm64_za-ptrace_Get_and_set_data_for_VL_624 skip
13095 10:08:21.652461 arm64_za-ptrace_Set_VL_640 pass
13096 10:08:21.652550 arm64_za-ptrace_Disabled_ZA_for_VL_640 skip
13097 10:08:21.652628 arm64_za-ptrace_Get_and_set_data_for_VL_640 skip
13098 10:08:21.652704 arm64_za-ptrace_Set_VL_656 pass
13099 10:08:21.652779 arm64_za-ptrace_Disabled_ZA_for_VL_656 skip
13100 10:08:21.653060 arm64_za-ptrace_Get_and_set_data_for_VL_656 skip
13101 10:08:21.653166 arm64_za-ptrace_Set_VL_672 pass
13102 10:08:21.653258 arm64_za-ptrace_Disabled_ZA_for_VL_672 skip
13103 10:08:21.653345 arm64_za-ptrace_Get_and_set_data_for_VL_672 skip
13104 10:08:21.653426 arm64_za-ptrace_Set_VL_688 pass
13105 10:08:21.653516 arm64_za-ptrace_Disabled_ZA_for_VL_688 skip
13106 10:08:21.657285 arm64_za-ptrace_Get_and_set_data_for_VL_688 skip
13107 10:08:21.657399 arm64_za-ptrace_Set_VL_704 pass
13108 10:08:21.657813 arm64_za-ptrace_Disabled_ZA_for_VL_704 skip
13109 10:08:21.658081 arm64_za-ptrace_Get_and_set_data_for_VL_704 skip
13110 10:08:21.658173 arm64_za-ptrace_Set_VL_720 pass
13111 10:08:21.658260 arm64_za-ptrace_Disabled_ZA_for_VL_720 skip
13112 10:08:21.658344 arm64_za-ptrace_Get_and_set_data_for_VL_720 skip
13113 10:08:21.658448 arm64_za-ptrace_Set_VL_736 pass
13114 10:08:21.658544 arm64_za-ptrace_Disabled_ZA_for_VL_736 skip
13115 10:08:21.658629 arm64_za-ptrace_Get_and_set_data_for_VL_736 skip
13116 10:08:21.658714 arm64_za-ptrace_Set_VL_752 pass
13117 10:08:21.658799 arm64_za-ptrace_Disabled_ZA_for_VL_752 skip
13118 10:08:21.658882 arm64_za-ptrace_Get_and_set_data_for_VL_752 skip
13119 10:08:21.658966 arm64_za-ptrace_Set_VL_768 pass
13120 10:08:21.659050 arm64_za-ptrace_Disabled_ZA_for_VL_768 skip
13121 10:08:21.659135 arm64_za-ptrace_Get_and_set_data_for_VL_768 skip
13122 10:08:21.659239 arm64_za-ptrace_Set_VL_784 pass
13123 10:08:21.659327 arm64_za-ptrace_Disabled_ZA_for_VL_784 skip
13124 10:08:21.659412 arm64_za-ptrace_Get_and_set_data_for_VL_784 skip
13125 10:08:21.659497 arm64_za-ptrace_Set_VL_800 pass
13126 10:08:21.659579 arm64_za-ptrace_Disabled_ZA_for_VL_800 skip
13127 10:08:21.659662 arm64_za-ptrace_Get_and_set_data_for_VL_800 skip
13128 10:08:21.659749 arm64_za-ptrace_Set_VL_816 pass
13129 10:08:21.659837 arm64_za-ptrace_Disabled_ZA_for_VL_816 skip
13130 10:08:21.659922 arm64_za-ptrace_Get_and_set_data_for_VL_816 skip
13131 10:08:21.660009 arm64_za-ptrace_Set_VL_832 pass
13132 10:08:21.660093 arm64_za-ptrace_Disabled_ZA_for_VL_832 skip
13133 10:08:21.660199 arm64_za-ptrace_Get_and_set_data_for_VL_832 skip
13134 10:08:21.660287 arm64_za-ptrace_Set_VL_848 pass
13135 10:08:21.660371 arm64_za-ptrace_Disabled_ZA_for_VL_848 skip
13136 10:08:21.660455 arm64_za-ptrace_Get_and_set_data_for_VL_848 skip
13137 10:08:21.660539 arm64_za-ptrace_Set_VL_864 pass
13138 10:08:21.660622 arm64_za-ptrace_Disabled_ZA_for_VL_864 skip
13139 10:08:21.660708 arm64_za-ptrace_Get_and_set_data_for_VL_864 skip
13140 10:08:21.660793 arm64_za-ptrace_Set_VL_880 pass
13141 10:08:21.660877 arm64_za-ptrace_Disabled_ZA_for_VL_880 skip
13142 10:08:21.660962 arm64_za-ptrace_Get_and_set_data_for_VL_880 skip
13143 10:08:21.661065 arm64_za-ptrace_Set_VL_896 pass
13144 10:08:21.661152 arm64_za-ptrace_Disabled_ZA_for_VL_896 skip
13145 10:08:21.661236 arm64_za-ptrace_Get_and_set_data_for_VL_896 skip
13146 10:08:21.661321 arm64_za-ptrace_Set_VL_912 pass
13147 10:08:21.661399 arm64_za-ptrace_Disabled_ZA_for_VL_912 skip
13148 10:08:21.661479 arm64_za-ptrace_Get_and_set_data_for_VL_912 skip
13149 10:08:21.661562 arm64_za-ptrace_Set_VL_928 pass
13150 10:08:21.661643 arm64_za-ptrace_Disabled_ZA_for_VL_928 skip
13151 10:08:21.662390 arm64_za-ptrace_Get_and_set_data_for_VL_928 skip
13152 10:08:21.662480 arm64_za-ptrace_Set_VL_944 pass
13153 10:08:21.662566 arm64_za-ptrace_Disabled_ZA_for_VL_944 skip
13154 10:08:21.665335 arm64_za-ptrace_Get_and_set_data_for_VL_944 skip
13155 10:08:21.665475 arm64_za-ptrace_Set_VL_960 pass
13156 10:08:21.665990 arm64_za-ptrace_Disabled_ZA_for_VL_960 skip
13157 10:08:21.666099 arm64_za-ptrace_Get_and_set_data_for_VL_960 skip
13158 10:08:21.666184 arm64_za-ptrace_Set_VL_976 pass
13159 10:08:21.666274 arm64_za-ptrace_Disabled_ZA_for_VL_976 skip
13160 10:08:21.666355 arm64_za-ptrace_Get_and_set_data_for_VL_976 skip
13161 10:08:21.666439 arm64_za-ptrace_Set_VL_992 pass
13162 10:08:21.666524 arm64_za-ptrace_Disabled_ZA_for_VL_992 skip
13163 10:08:21.666619 arm64_za-ptrace_Get_and_set_data_for_VL_992 skip
13164 10:08:21.666703 arm64_za-ptrace_Set_VL_1008 pass
13165 10:08:21.666784 arm64_za-ptrace_Disabled_ZA_for_VL_1008 skip
13166 10:08:21.666864 arm64_za-ptrace_Get_and_set_data_for_VL_1008 skip
13167 10:08:21.666944 arm64_za-ptrace_Set_VL_1024 pass
13168 10:08:21.667026 arm64_za-ptrace_Disabled_ZA_for_VL_1024 skip
13169 10:08:21.667127 arm64_za-ptrace_Get_and_set_data_for_VL_1024 skip
13170 10:08:21.667210 arm64_za-ptrace_Set_VL_1040 pass
13171 10:08:21.667292 arm64_za-ptrace_Disabled_ZA_for_VL_1040 skip
13172 10:08:21.667373 arm64_za-ptrace_Get_and_set_data_for_VL_1040 skip
13173 10:08:21.667455 arm64_za-ptrace_Set_VL_1056 pass
13174 10:08:21.667530 arm64_za-ptrace_Disabled_ZA_for_VL_1056 skip
13175 10:08:21.667607 arm64_za-ptrace_Get_and_set_data_for_VL_1056 skip
13176 10:08:21.667689 arm64_za-ptrace_Set_VL_1072 pass
13177 10:08:21.667784 arm64_za-ptrace_Disabled_ZA_for_VL_1072 skip
13178 10:08:21.667865 arm64_za-ptrace_Get_and_set_data_for_VL_1072 skip
13179 10:08:21.667931 arm64_za-ptrace_Set_VL_1088 pass
13180 10:08:21.668005 arm64_za-ptrace_Disabled_ZA_for_VL_1088 skip
13181 10:08:21.668091 arm64_za-ptrace_Get_and_set_data_for_VL_1088 skip
13182 10:08:21.668172 arm64_za-ptrace_Set_VL_1104 pass
13183 10:08:21.668249 arm64_za-ptrace_Disabled_ZA_for_VL_1104 skip
13184 10:08:21.668327 arm64_za-ptrace_Get_and_set_data_for_VL_1104 skip
13185 10:08:21.668423 arm64_za-ptrace_Set_VL_1120 pass
13186 10:08:21.668496 arm64_za-ptrace_Disabled_ZA_for_VL_1120 skip
13187 10:08:21.668574 arm64_za-ptrace_Get_and_set_data_for_VL_1120 skip
13188 10:08:21.668651 arm64_za-ptrace_Set_VL_1136 pass
13189 10:08:21.668728 arm64_za-ptrace_Disabled_ZA_for_VL_1136 skip
13190 10:08:21.668841 arm64_za-ptrace_Get_and_set_data_for_VL_1136 skip
13191 10:08:21.668928 arm64_za-ptrace_Set_VL_1152 pass
13192 10:08:21.668995 arm64_za-ptrace_Disabled_ZA_for_VL_1152 skip
13193 10:08:21.669056 arm64_za-ptrace_Get_and_set_data_for_VL_1152 skip
13194 10:08:21.669117 arm64_za-ptrace_Set_VL_1168 pass
13195 10:08:21.669175 arm64_za-ptrace_Disabled_ZA_for_VL_1168 skip
13196 10:08:21.669246 arm64_za-ptrace_Get_and_set_data_for_VL_1168 skip
13197 10:08:21.669307 arm64_za-ptrace_Set_VL_1184 pass
13198 10:08:21.673423 arm64_za-ptrace_Disabled_ZA_for_VL_1184 skip
13199 10:08:21.673644 arm64_za-ptrace_Get_and_set_data_for_VL_1184 skip
13200 10:08:21.673810 arm64_za-ptrace_Set_VL_1200 pass
13201 10:08:21.674195 arm64_za-ptrace_Disabled_ZA_for_VL_1200 skip
13202 10:08:21.674412 arm64_za-ptrace_Get_and_set_data_for_VL_1200 skip
13203 10:08:21.674622 arm64_za-ptrace_Set_VL_1216 pass
13204 10:08:21.674791 arm64_za-ptrace_Disabled_ZA_for_VL_1216 skip
13205 10:08:21.674954 arm64_za-ptrace_Get_and_set_data_for_VL_1216 skip
13206 10:08:21.675159 arm64_za-ptrace_Set_VL_1232 pass
13207 10:08:21.675321 arm64_za-ptrace_Disabled_ZA_for_VL_1232 skip
13208 10:08:21.675501 arm64_za-ptrace_Get_and_set_data_for_VL_1232 skip
13209 10:08:21.675727 arm64_za-ptrace_Set_VL_1248 pass
13210 10:08:21.675960 arm64_za-ptrace_Disabled_ZA_for_VL_1248 skip
13211 10:08:21.676125 arm64_za-ptrace_Get_and_set_data_for_VL_1248 skip
13212 10:08:21.676332 arm64_za-ptrace_Set_VL_1264 pass
13213 10:08:21.676537 arm64_za-ptrace_Disabled_ZA_for_VL_1264 skip
13214 10:08:21.676713 arm64_za-ptrace_Get_and_set_data_for_VL_1264 skip
13215 10:08:21.676874 arm64_za-ptrace_Set_VL_1280 pass
13216 10:08:21.676995 arm64_za-ptrace_Disabled_ZA_for_VL_1280 skip
13217 10:08:21.677109 arm64_za-ptrace_Get_and_set_data_for_VL_1280 skip
13218 10:08:21.677221 arm64_za-ptrace_Set_VL_1296 pass
13219 10:08:21.677331 arm64_za-ptrace_Disabled_ZA_for_VL_1296 skip
13220 10:08:21.677447 arm64_za-ptrace_Get_and_set_data_for_VL_1296 skip
13221 10:08:21.677558 arm64_za-ptrace_Set_VL_1312 pass
13222 10:08:21.677696 arm64_za-ptrace_Disabled_ZA_for_VL_1312 skip
13223 10:08:21.677901 arm64_za-ptrace_Get_and_set_data_for_VL_1312 skip
13224 10:08:21.678086 arm64_za-ptrace_Set_VL_1328 pass
13225 10:08:21.678267 arm64_za-ptrace_Disabled_ZA_for_VL_1328 skip
13226 10:08:21.678461 arm64_za-ptrace_Get_and_set_data_for_VL_1328 skip
13227 10:08:21.678651 arm64_za-ptrace_Set_VL_1344 pass
13228 10:08:21.678823 arm64_za-ptrace_Disabled_ZA_for_VL_1344 skip
13229 10:08:21.678989 arm64_za-ptrace_Get_and_set_data_for_VL_1344 skip
13230 10:08:21.679135 arm64_za-ptrace_Set_VL_1360 pass
13231 10:08:21.679254 arm64_za-ptrace_Disabled_ZA_for_VL_1360 skip
13232 10:08:21.679371 arm64_za-ptrace_Get_and_set_data_for_VL_1360 skip
13233 10:08:21.679486 arm64_za-ptrace_Set_VL_1376 pass
13234 10:08:21.679600 arm64_za-ptrace_Disabled_ZA_for_VL_1376 skip
13235 10:08:21.679714 arm64_za-ptrace_Get_and_set_data_for_VL_1376 skip
13236 10:08:21.679829 arm64_za-ptrace_Set_VL_1392 pass
13237 10:08:21.679944 arm64_za-ptrace_Disabled_ZA_for_VL_1392 skip
13238 10:08:21.680060 arm64_za-ptrace_Get_and_set_data_for_VL_1392 skip
13239 10:08:21.680176 arm64_za-ptrace_Set_VL_1408 pass
13240 10:08:21.681462 arm64_za-ptrace_Disabled_ZA_for_VL_1408 skip
13241 10:08:21.681698 arm64_za-ptrace_Get_and_set_data_for_VL_1408 skip
13242 10:08:21.681853 arm64_za-ptrace_Set_VL_1424 pass
13243 10:08:21.682233 arm64_za-ptrace_Disabled_ZA_for_VL_1424 skip
13244 10:08:21.682435 arm64_za-ptrace_Get_and_set_data_for_VL_1424 skip
13245 10:08:21.682636 arm64_za-ptrace_Set_VL_1440 pass
13246 10:08:21.682818 arm64_za-ptrace_Disabled_ZA_for_VL_1440 skip
13247 10:08:21.682975 arm64_za-ptrace_Get_and_set_data_for_VL_1440 skip
13248 10:08:21.683127 arm64_za-ptrace_Set_VL_1456 pass
13249 10:08:21.683280 arm64_za-ptrace_Disabled_ZA_for_VL_1456 skip
13250 10:08:21.683444 arm64_za-ptrace_Get_and_set_data_for_VL_1456 skip
13251 10:08:21.683573 arm64_za-ptrace_Set_VL_1472 pass
13252 10:08:21.683722 arm64_za-ptrace_Disabled_ZA_for_VL_1472 skip
13253 10:08:21.683860 arm64_za-ptrace_Get_and_set_data_for_VL_1472 skip
13254 10:08:21.683998 arm64_za-ptrace_Set_VL_1488 pass
13255 10:08:21.684120 arm64_za-ptrace_Disabled_ZA_for_VL_1488 skip
13256 10:08:21.684237 arm64_za-ptrace_Get_and_set_data_for_VL_1488 skip
13257 10:08:21.684352 arm64_za-ptrace_Set_VL_1504 pass
13258 10:08:21.684468 arm64_za-ptrace_Disabled_ZA_for_VL_1504 skip
13259 10:08:21.684583 arm64_za-ptrace_Get_and_set_data_for_VL_1504 skip
13260 10:08:21.684698 arm64_za-ptrace_Set_VL_1520 pass
13261 10:08:21.684812 arm64_za-ptrace_Disabled_ZA_for_VL_1520 skip
13262 10:08:21.684927 arm64_za-ptrace_Get_and_set_data_for_VL_1520 skip
13263 10:08:21.685043 arm64_za-ptrace_Set_VL_1536 pass
13264 10:08:21.685160 arm64_za-ptrace_Disabled_ZA_for_VL_1536 skip
13265 10:08:21.701479 arm64_za-ptrace_Get_and_set_data_for_VL_1536 skip
13266 10:08:21.701660 arm64_za-ptrace_Set_VL_1552 pass
13267 10:08:21.701744 arm64_za-ptrace_Disabled_ZA_for_VL_1552 skip
13268 10:08:21.702021 arm64_za-ptrace_Get_and_set_data_for_VL_1552 skip
13269 10:08:21.702107 arm64_za-ptrace_Set_VL_1568 pass
13270 10:08:21.702190 arm64_za-ptrace_Disabled_ZA_for_VL_1568 skip
13271 10:08:21.702269 arm64_za-ptrace_Get_and_set_data_for_VL_1568 skip
13272 10:08:21.702361 arm64_za-ptrace_Set_VL_1584 pass
13273 10:08:21.702439 arm64_za-ptrace_Disabled_ZA_for_VL_1584 skip
13274 10:08:21.702520 arm64_za-ptrace_Get_and_set_data_for_VL_1584 skip
13275 10:08:21.702596 arm64_za-ptrace_Set_VL_1600 pass
13276 10:08:21.702686 arm64_za-ptrace_Disabled_ZA_for_VL_1600 skip
13277 10:08:21.702765 arm64_za-ptrace_Get_and_set_data_for_VL_1600 skip
13278 10:08:21.702840 arm64_za-ptrace_Set_VL_1616 pass
13279 10:08:21.702929 arm64_za-ptrace_Disabled_ZA_for_VL_1616 skip
13280 10:08:21.703007 arm64_za-ptrace_Get_and_set_data_for_VL_1616 skip
13281 10:08:21.703083 arm64_za-ptrace_Set_VL_1632 pass
13282 10:08:21.703173 arm64_za-ptrace_Disabled_ZA_for_VL_1632 skip
13283 10:08:21.703251 arm64_za-ptrace_Get_and_set_data_for_VL_1632 skip
13284 10:08:21.703327 arm64_za-ptrace_Set_VL_1648 pass
13285 10:08:21.703417 arm64_za-ptrace_Disabled_ZA_for_VL_1648 skip
13286 10:08:21.703495 arm64_za-ptrace_Get_and_set_data_for_VL_1648 skip
13287 10:08:21.703576 arm64_za-ptrace_Set_VL_1664 pass
13288 10:08:21.703664 arm64_za-ptrace_Disabled_ZA_for_VL_1664 skip
13289 10:08:21.703742 arm64_za-ptrace_Get_and_set_data_for_VL_1664 skip
13290 10:08:21.703831 arm64_za-ptrace_Set_VL_1680 pass
13291 10:08:21.703921 arm64_za-ptrace_Disabled_ZA_for_VL_1680 skip
13292 10:08:21.704012 arm64_za-ptrace_Get_and_set_data_for_VL_1680 skip
13293 10:08:21.704101 arm64_za-ptrace_Set_VL_1696 pass
13294 10:08:21.704192 arm64_za-ptrace_Disabled_ZA_for_VL_1696 skip
13295 10:08:21.704488 arm64_za-ptrace_Get_and_set_data_for_VL_1696 skip
13296 10:08:21.704654 arm64_za-ptrace_Set_VL_1712 pass
13297 10:08:21.704744 arm64_za-ptrace_Disabled_ZA_for_VL_1712 skip
13298 10:08:21.704844 arm64_za-ptrace_Get_and_set_data_for_VL_1712 skip
13299 10:08:21.704928 arm64_za-ptrace_Set_VL_1728 pass
13300 10:08:21.705009 arm64_za-ptrace_Disabled_ZA_for_VL_1728 skip
13301 10:08:21.705095 arm64_za-ptrace_Get_and_set_data_for_VL_1728 skip
13302 10:08:21.705197 arm64_za-ptrace_Set_VL_1744 pass
13303 10:08:21.709201 arm64_za-ptrace_Disabled_ZA_for_VL_1744 skip
13304 10:08:21.709526 arm64_za-ptrace_Get_and_set_data_for_VL_1744 skip
13305 10:08:21.709634 arm64_za-ptrace_Set_VL_1760 pass
13306 10:08:21.709727 arm64_za-ptrace_Disabled_ZA_for_VL_1760 skip
13307 10:08:21.709957 arm64_za-ptrace_Get_and_set_data_for_VL_1760 skip
13308 10:08:21.710053 arm64_za-ptrace_Set_VL_1776 pass
13309 10:08:21.710142 arm64_za-ptrace_Disabled_ZA_for_VL_1776 skip
13310 10:08:21.710230 arm64_za-ptrace_Get_and_set_data_for_VL_1776 skip
13311 10:08:21.710330 arm64_za-ptrace_Set_VL_1792 pass
13312 10:08:21.710419 arm64_za-ptrace_Disabled_ZA_for_VL_1792 skip
13313 10:08:21.710505 arm64_za-ptrace_Get_and_set_data_for_VL_1792 skip
13314 10:08:21.710607 arm64_za-ptrace_Set_VL_1808 pass
13315 10:08:21.710694 arm64_za-ptrace_Disabled_ZA_for_VL_1808 skip
13316 10:08:21.710780 arm64_za-ptrace_Get_and_set_data_for_VL_1808 skip
13317 10:08:21.710887 arm64_za-ptrace_Set_VL_1824 pass
13318 10:08:21.710990 arm64_za-ptrace_Disabled_ZA_for_VL_1824 skip
13319 10:08:21.711076 arm64_za-ptrace_Get_and_set_data_for_VL_1824 skip
13320 10:08:21.711163 arm64_za-ptrace_Set_VL_1840 pass
13321 10:08:21.711268 arm64_za-ptrace_Disabled_ZA_for_VL_1840 skip
13322 10:08:21.711356 arm64_za-ptrace_Get_and_set_data_for_VL_1840 skip
13323 10:08:21.711445 arm64_za-ptrace_Set_VL_1856 pass
13324 10:08:21.711550 arm64_za-ptrace_Disabled_ZA_for_VL_1856 skip
13325 10:08:21.711640 arm64_za-ptrace_Get_and_set_data_for_VL_1856 skip
13326 10:08:21.711741 arm64_za-ptrace_Set_VL_1872 pass
13327 10:08:21.711826 arm64_za-ptrace_Disabled_ZA_for_VL_1872 skip
13328 10:08:21.711924 arm64_za-ptrace_Get_and_set_data_for_VL_1872 skip
13329 10:08:21.712009 arm64_za-ptrace_Set_VL_1888 pass
13330 10:08:21.712392 arm64_za-ptrace_Disabled_ZA_for_VL_1888 skip
13331 10:08:21.712501 arm64_za-ptrace_Get_and_set_data_for_VL_1888 skip
13332 10:08:21.712588 arm64_za-ptrace_Set_VL_1904 pass
13333 10:08:21.712673 arm64_za-ptrace_Disabled_ZA_for_VL_1904 skip
13334 10:08:21.712756 arm64_za-ptrace_Get_and_set_data_for_VL_1904 skip
13335 10:08:21.712857 arm64_za-ptrace_Set_VL_1920 pass
13336 10:08:21.712941 arm64_za-ptrace_Disabled_ZA_for_VL_1920 skip
13337 10:08:21.713024 arm64_za-ptrace_Get_and_set_data_for_VL_1920 skip
13338 10:08:21.713107 arm64_za-ptrace_Set_VL_1936 pass
13339 10:08:21.713204 arm64_za-ptrace_Disabled_ZA_for_VL_1936 skip
13340 10:08:21.717197 arm64_za-ptrace_Get_and_set_data_for_VL_1936 skip
13341 10:08:21.717672 arm64_za-ptrace_Set_VL_1952 pass
13342 10:08:21.717870 arm64_za-ptrace_Disabled_ZA_for_VL_1952 skip
13343 10:08:21.718049 arm64_za-ptrace_Get_and_set_data_for_VL_1952 skip
13344 10:08:21.718209 arm64_za-ptrace_Set_VL_1968 pass
13345 10:08:21.718403 arm64_za-ptrace_Disabled_ZA_for_VL_1968 skip
13346 10:08:21.718572 arm64_za-ptrace_Get_and_set_data_for_VL_1968 skip
13347 10:08:21.718738 arm64_za-ptrace_Set_VL_1984 pass
13348 10:08:21.718897 arm64_za-ptrace_Disabled_ZA_for_VL_1984 skip
13349 10:08:21.719055 arm64_za-ptrace_Get_and_set_data_for_VL_1984 skip
13350 10:08:21.719209 arm64_za-ptrace_Set_VL_2000 pass
13351 10:08:21.719364 arm64_za-ptrace_Disabled_ZA_for_VL_2000 skip
13352 10:08:21.719522 arm64_za-ptrace_Get_and_set_data_for_VL_2000 skip
13353 10:08:21.719747 arm64_za-ptrace_Set_VL_2016 pass
13354 10:08:21.719938 arm64_za-ptrace_Disabled_ZA_for_VL_2016 skip
13355 10:08:21.720095 arm64_za-ptrace_Get_and_set_data_for_VL_2016 skip
13356 10:08:21.720260 arm64_za-ptrace_Set_VL_2032 pass
13357 10:08:21.720423 arm64_za-ptrace_Disabled_ZA_for_VL_2032 skip
13358 10:08:21.720580 arm64_za-ptrace_Get_and_set_data_for_VL_2032 skip
13359 10:08:21.720736 arm64_za-ptrace_Set_VL_2048 pass
13360 10:08:21.720894 arm64_za-ptrace_Disabled_ZA_for_VL_2048 skip
13361 10:08:21.721073 arm64_za-ptrace_Get_and_set_data_for_VL_2048 skip
13362 10:08:21.721207 arm64_za-ptrace_Set_VL_2064 pass
13363 10:08:21.721323 arm64_za-ptrace_Disabled_ZA_for_VL_2064 skip
13364 10:08:21.721472 arm64_za-ptrace_Get_and_set_data_for_VL_2064 skip
13365 10:08:21.721594 arm64_za-ptrace_Set_VL_2080 pass
13366 10:08:21.721804 arm64_za-ptrace_Disabled_ZA_for_VL_2080 skip
13367 10:08:21.722001 arm64_za-ptrace_Get_and_set_data_for_VL_2080 skip
13368 10:08:21.722182 arm64_za-ptrace_Set_VL_2096 pass
13369 10:08:21.722363 arm64_za-ptrace_Disabled_ZA_for_VL_2096 skip
13370 10:08:21.722543 arm64_za-ptrace_Get_and_set_data_for_VL_2096 skip
13371 10:08:21.722718 arm64_za-ptrace_Set_VL_2112 pass
13372 10:08:21.722860 arm64_za-ptrace_Disabled_ZA_for_VL_2112 skip
13373 10:08:21.723002 arm64_za-ptrace_Get_and_set_data_for_VL_2112 skip
13374 10:08:21.723144 arm64_za-ptrace_Set_VL_2128 pass
13375 10:08:21.723286 arm64_za-ptrace_Disabled_ZA_for_VL_2128 skip
13376 10:08:21.723427 arm64_za-ptrace_Get_and_set_data_for_VL_2128 skip
13377 10:08:21.723567 arm64_za-ptrace_Set_VL_2144 pass
13378 10:08:21.725243 arm64_za-ptrace_Disabled_ZA_for_VL_2144 skip
13379 10:08:21.725356 arm64_za-ptrace_Get_and_set_data_for_VL_2144 skip
13380 10:08:21.725632 arm64_za-ptrace_Set_VL_2160 pass
13381 10:08:21.725739 arm64_za-ptrace_Disabled_ZA_for_VL_2160 skip
13382 10:08:21.725834 arm64_za-ptrace_Get_and_set_data_for_VL_2160 skip
13383 10:08:21.725912 arm64_za-ptrace_Set_VL_2176 pass
13384 10:08:21.725988 arm64_za-ptrace_Disabled_ZA_for_VL_2176 skip
13385 10:08:21.726064 arm64_za-ptrace_Get_and_set_data_for_VL_2176 skip
13386 10:08:21.726140 arm64_za-ptrace_Set_VL_2192 pass
13387 10:08:21.726231 arm64_za-ptrace_Disabled_ZA_for_VL_2192 skip
13388 10:08:21.726309 arm64_za-ptrace_Get_and_set_data_for_VL_2192 skip
13389 10:08:21.726387 arm64_za-ptrace_Set_VL_2208 pass
13390 10:08:21.726463 arm64_za-ptrace_Disabled_ZA_for_VL_2208 skip
13391 10:08:21.726539 arm64_za-ptrace_Get_and_set_data_for_VL_2208 skip
13392 10:08:21.726633 arm64_za-ptrace_Set_VL_2224 pass
13393 10:08:21.726712 arm64_za-ptrace_Disabled_ZA_for_VL_2224 skip
13394 10:08:21.726788 arm64_za-ptrace_Get_and_set_data_for_VL_2224 skip
13395 10:08:21.726864 arm64_za-ptrace_Set_VL_2240 pass
13396 10:08:21.726939 arm64_za-ptrace_Disabled_ZA_for_VL_2240 skip
13397 10:08:21.727030 arm64_za-ptrace_Get_and_set_data_for_VL_2240 skip
13398 10:08:21.727108 arm64_za-ptrace_Set_VL_2256 pass
13399 10:08:21.727184 arm64_za-ptrace_Disabled_ZA_for_VL_2256 skip
13400 10:08:21.727260 arm64_za-ptrace_Get_and_set_data_for_VL_2256 skip
13401 10:08:21.727334 arm64_za-ptrace_Set_VL_2272 pass
13402 10:08:21.727424 arm64_za-ptrace_Disabled_ZA_for_VL_2272 skip
13403 10:08:21.727501 arm64_za-ptrace_Get_and_set_data_for_VL_2272 skip
13404 10:08:21.727578 arm64_za-ptrace_Set_VL_2288 pass
13405 10:08:21.727653 arm64_za-ptrace_Disabled_ZA_for_VL_2288 skip
13406 10:08:21.727743 arm64_za-ptrace_Get_and_set_data_for_VL_2288 skip
13407 10:08:21.727821 arm64_za-ptrace_Set_VL_2304 pass
13408 10:08:21.727896 arm64_za-ptrace_Disabled_ZA_for_VL_2304 skip
13409 10:08:21.727984 arm64_za-ptrace_Get_and_set_data_for_VL_2304 skip
13410 10:08:21.728063 arm64_za-ptrace_Set_VL_2320 pass
13411 10:08:21.728152 arm64_za-ptrace_Disabled_ZA_for_VL_2320 skip
13412 10:08:21.728230 arm64_za-ptrace_Get_and_set_data_for_VL_2320 skip
13413 10:08:21.728306 arm64_za-ptrace_Set_VL_2336 pass
13414 10:08:21.728394 arm64_za-ptrace_Disabled_ZA_for_VL_2336 skip
13415 10:08:21.728472 arm64_za-ptrace_Get_and_set_data_for_VL_2336 skip
13416 10:08:21.728564 arm64_za-ptrace_Set_VL_2352 pass
13417 10:08:21.728642 arm64_za-ptrace_Disabled_ZA_for_VL_2352 skip
13418 10:08:21.728732 arm64_za-ptrace_Get_and_set_data_for_VL_2352 skip
13419 10:08:21.728810 arm64_za-ptrace_Set_VL_2368 pass
13420 10:08:21.728897 arm64_za-ptrace_Disabled_ZA_for_VL_2368 skip
13421 10:08:21.728975 arm64_za-ptrace_Get_and_set_data_for_VL_2368 skip
13422 10:08:21.729063 arm64_za-ptrace_Set_VL_2384 pass
13423 10:08:21.733620 arm64_za-ptrace_Disabled_ZA_for_VL_2384 skip
13424 10:08:21.733871 arm64_za-ptrace_Get_and_set_data_for_VL_2384 skip
13425 10:08:21.734075 arm64_za-ptrace_Set_VL_2400 pass
13426 10:08:21.734245 arm64_za-ptrace_Disabled_ZA_for_VL_2400 skip
13427 10:08:21.734413 arm64_za-ptrace_Get_and_set_data_for_VL_2400 skip
13428 10:08:21.734574 arm64_za-ptrace_Set_VL_2416 pass
13429 10:08:21.734766 arm64_za-ptrace_Disabled_ZA_for_VL_2416 skip
13430 10:08:21.734932 arm64_za-ptrace_Get_and_set_data_for_VL_2416 skip
13431 10:08:21.735095 arm64_za-ptrace_Set_VL_2432 pass
13432 10:08:21.735256 arm64_za-ptrace_Disabled_ZA_for_VL_2432 skip
13433 10:08:21.735414 arm64_za-ptrace_Get_and_set_data_for_VL_2432 skip
13434 10:08:21.735573 arm64_za-ptrace_Set_VL_2448 pass
13435 10:08:21.735734 arm64_za-ptrace_Disabled_ZA_for_VL_2448 skip
13436 10:08:21.735886 arm64_za-ptrace_Get_and_set_data_for_VL_2448 skip
13437 10:08:21.736080 arm64_za-ptrace_Set_VL_2464 pass
13438 10:08:21.736241 arm64_za-ptrace_Disabled_ZA_for_VL_2464 skip
13439 10:08:21.736397 arm64_za-ptrace_Get_and_set_data_for_VL_2464 skip
13440 10:08:21.736552 arm64_za-ptrace_Set_VL_2480 pass
13441 10:08:21.736709 arm64_za-ptrace_Disabled_ZA_for_VL_2480 skip
13442 10:08:21.736835 arm64_za-ptrace_Get_and_set_data_for_VL_2480 skip
13443 10:08:21.736953 arm64_za-ptrace_Set_VL_2496 pass
13444 10:08:21.737070 arm64_za-ptrace_Disabled_ZA_for_VL_2496 skip
13445 10:08:21.737187 arm64_za-ptrace_Get_and_set_data_for_VL_2496 skip
13446 10:08:21.737302 arm64_za-ptrace_Set_VL_2512 pass
13447 10:08:21.737416 arm64_za-ptrace_Disabled_ZA_for_VL_2512 skip
13448 10:08:21.737532 arm64_za-ptrace_Get_and_set_data_for_VL_2512 skip
13449 10:08:21.737660 arm64_za-ptrace_Set_VL_2528 pass
13450 10:08:21.737781 arm64_za-ptrace_Disabled_ZA_for_VL_2528 skip
13451 10:08:21.737923 arm64_za-ptrace_Get_and_set_data_for_VL_2528 skip
13452 10:08:21.738047 arm64_za-ptrace_Set_VL_2544 pass
13453 10:08:21.738165 arm64_za-ptrace_Disabled_ZA_for_VL_2544 skip
13454 10:08:21.738282 arm64_za-ptrace_Get_and_set_data_for_VL_2544 skip
13455 10:08:21.738400 arm64_za-ptrace_Set_VL_2560 pass
13456 10:08:21.738541 arm64_za-ptrace_Disabled_ZA_for_VL_2560 skip
13457 10:08:21.741564 arm64_za-ptrace_Get_and_set_data_for_VL_2560 skip
13458 10:08:21.756244 arm64_za-ptrace_Set_VL_2576 pass
13459 10:08:21.756449 arm64_za-ptrace_Disabled_ZA_for_VL_2576 skip
13460 10:08:21.756757 arm64_za-ptrace_Get_and_set_data_for_VL_2576 skip
13461 10:08:21.756867 arm64_za-ptrace_Set_VL_2592 pass
13462 10:08:21.756962 arm64_za-ptrace_Disabled_ZA_for_VL_2592 skip
13463 10:08:21.757052 arm64_za-ptrace_Get_and_set_data_for_VL_2592 skip
13464 10:08:21.757138 arm64_za-ptrace_Set_VL_2608 pass
13465 10:08:21.757239 arm64_za-ptrace_Disabled_ZA_for_VL_2608 skip
13466 10:08:21.757328 arm64_za-ptrace_Get_and_set_data_for_VL_2608 skip
13467 10:08:21.757427 arm64_za-ptrace_Set_VL_2624 pass
13468 10:08:21.757516 arm64_za-ptrace_Disabled_ZA_for_VL_2624 skip
13469 10:08:21.757621 arm64_za-ptrace_Get_and_set_data_for_VL_2624 skip
13470 10:08:21.757718 arm64_za-ptrace_Set_VL_2640 pass
13471 10:08:21.757822 arm64_za-ptrace_Disabled_ZA_for_VL_2640 skip
13472 10:08:21.757998 arm64_za-ptrace_Get_and_set_data_for_VL_2640 skip
13473 10:08:21.758108 arm64_za-ptrace_Set_VL_2656 pass
13474 10:08:21.758210 arm64_za-ptrace_Disabled_ZA_for_VL_2656 skip
13475 10:08:21.758309 arm64_za-ptrace_Get_and_set_data_for_VL_2656 skip
13476 10:08:21.758415 arm64_za-ptrace_Set_VL_2672 pass
13477 10:08:21.758633 arm64_za-ptrace_Disabled_ZA_for_VL_2672 skip
13478 10:08:21.758756 arm64_za-ptrace_Get_and_set_data_for_VL_2672 skip
13479 10:08:21.758860 arm64_za-ptrace_Set_VL_2688 pass
13480 10:08:21.758962 arm64_za-ptrace_Disabled_ZA_for_VL_2688 skip
13481 10:08:21.759065 arm64_za-ptrace_Get_and_set_data_for_VL_2688 skip
13482 10:08:21.759171 arm64_za-ptrace_Set_VL_2704 pass
13483 10:08:21.759274 arm64_za-ptrace_Disabled_ZA_for_VL_2704 skip
13484 10:08:21.759584 arm64_za-ptrace_Get_and_set_data_for_VL_2704 skip
13485 10:08:21.759691 arm64_za-ptrace_Set_VL_2720 pass
13486 10:08:21.759799 arm64_za-ptrace_Disabled_ZA_for_VL_2720 skip
13487 10:08:21.759895 arm64_za-ptrace_Get_and_set_data_for_VL_2720 skip
13488 10:08:21.759984 arm64_za-ptrace_Set_VL_2736 pass
13489 10:08:21.760086 arm64_za-ptrace_Disabled_ZA_for_VL_2736 skip
13490 10:08:21.760188 arm64_za-ptrace_Get_and_set_data_for_VL_2736 skip
13491 10:08:21.760274 arm64_za-ptrace_Set_VL_2752 pass
13492 10:08:21.760376 arm64_za-ptrace_Disabled_ZA_for_VL_2752 skip
13493 10:08:21.760479 arm64_za-ptrace_Get_and_set_data_for_VL_2752 skip
13494 10:08:21.760776 arm64_za-ptrace_Set_VL_2768 pass
13495 10:08:21.760879 arm64_za-ptrace_Disabled_ZA_for_VL_2768 skip
13496 10:08:21.760964 arm64_za-ptrace_Get_and_set_data_for_VL_2768 skip
13497 10:08:21.761062 arm64_za-ptrace_Set_VL_2784 pass
13498 10:08:21.761149 arm64_za-ptrace_Disabled_ZA_for_VL_2784 skip
13499 10:08:21.765260 arm64_za-ptrace_Get_and_set_data_for_VL_2784 skip
13500 10:08:21.765581 arm64_za-ptrace_Set_VL_2800 pass
13501 10:08:21.765699 arm64_za-ptrace_Disabled_ZA_for_VL_2800 skip
13502 10:08:21.765789 arm64_za-ptrace_Get_and_set_data_for_VL_2800 skip
13503 10:08:21.765875 arm64_za-ptrace_Set_VL_2816 pass
13504 10:08:21.765979 arm64_za-ptrace_Disabled_ZA_for_VL_2816 skip
13505 10:08:21.766065 arm64_za-ptrace_Get_and_set_data_for_VL_2816 skip
13506 10:08:21.766148 arm64_za-ptrace_Set_VL_2832 pass
13507 10:08:21.766231 arm64_za-ptrace_Disabled_ZA_for_VL_2832 skip
13508 10:08:21.766329 arm64_za-ptrace_Get_and_set_data_for_VL_2832 skip
13509 10:08:21.766413 arm64_za-ptrace_Set_VL_2848 pass
13510 10:08:21.766496 arm64_za-ptrace_Disabled_ZA_for_VL_2848 skip
13511 10:08:21.766582 arm64_za-ptrace_Get_and_set_data_for_VL_2848 skip
13512 10:08:21.766685 arm64_za-ptrace_Set_VL_2864 pass
13513 10:08:21.766769 arm64_za-ptrace_Disabled_ZA_for_VL_2864 skip
13514 10:08:21.766852 arm64_za-ptrace_Get_and_set_data_for_VL_2864 skip
13515 10:08:21.766938 arm64_za-ptrace_Set_VL_2880 pass
13516 10:08:21.767022 arm64_za-ptrace_Disabled_ZA_for_VL_2880 skip
13517 10:08:21.767123 arm64_za-ptrace_Get_and_set_data_for_VL_2880 skip
13518 10:08:21.767209 arm64_za-ptrace_Set_VL_2896 pass
13519 10:08:21.767295 arm64_za-ptrace_Disabled_ZA_for_VL_2896 skip
13520 10:08:21.767383 arm64_za-ptrace_Get_and_set_data_for_VL_2896 skip
13521 10:08:21.767471 arm64_za-ptrace_Set_VL_2912 pass
13522 10:08:21.767578 arm64_za-ptrace_Disabled_ZA_for_VL_2912 skip
13523 10:08:21.767674 arm64_za-ptrace_Get_and_set_data_for_VL_2912 skip
13524 10:08:21.767763 arm64_za-ptrace_Set_VL_2928 pass
13525 10:08:21.767855 arm64_za-ptrace_Disabled_ZA_for_VL_2928 skip
13526 10:08:21.767938 arm64_za-ptrace_Get_and_set_data_for_VL_2928 skip
13527 10:08:21.768038 arm64_za-ptrace_Set_VL_2944 pass
13528 10:08:21.768122 arm64_za-ptrace_Disabled_ZA_for_VL_2944 skip
13529 10:08:21.768204 arm64_za-ptrace_Get_and_set_data_for_VL_2944 skip
13530 10:08:21.768289 arm64_za-ptrace_Set_VL_2960 pass
13531 10:08:21.768388 arm64_za-ptrace_Disabled_ZA_for_VL_2960 skip
13532 10:08:21.769036 arm64_za-ptrace_Get_and_set_data_for_VL_2960 skip
13533 10:08:21.769201 arm64_za-ptrace_Set_VL_2976 pass
13534 10:08:21.769326 arm64_za-ptrace_Disabled_ZA_for_VL_2976 skip
13535 10:08:21.769445 arm64_za-ptrace_Get_and_set_data_for_VL_2976 skip
13536 10:08:21.769564 arm64_za-ptrace_Set_VL_2992 pass
13537 10:08:21.769697 arm64_za-ptrace_Disabled_ZA_for_VL_2992 skip
13538 10:08:21.769815 arm64_za-ptrace_Get_and_set_data_for_VL_2992 skip
13539 10:08:21.769932 arm64_za-ptrace_Set_VL_3008 pass
13540 10:08:21.770074 arm64_za-ptrace_Disabled_ZA_for_VL_3008 skip
13541 10:08:21.773396 arm64_za-ptrace_Get_and_set_data_for_VL_3008 skip
13542 10:08:21.773516 arm64_za-ptrace_Set_VL_3024 pass
13543 10:08:21.773624 arm64_za-ptrace_Disabled_ZA_for_VL_3024 skip
13544 10:08:21.773723 arm64_za-ptrace_Get_and_set_data_for_VL_3024 skip
13545 10:08:21.773809 arm64_za-ptrace_Set_VL_3040 pass
13546 10:08:21.773911 arm64_za-ptrace_Disabled_ZA_for_VL_3040 skip
13547 10:08:21.774012 arm64_za-ptrace_Get_and_set_data_for_VL_3040 skip
13548 10:08:21.774099 arm64_za-ptrace_Set_VL_3056 pass
13549 10:08:21.774202 arm64_za-ptrace_Disabled_ZA_for_VL_3056 skip
13550 10:08:21.774307 arm64_za-ptrace_Get_and_set_data_for_VL_3056 skip
13551 10:08:21.774396 arm64_za-ptrace_Set_VL_3072 pass
13552 10:08:21.774493 arm64_za-ptrace_Disabled_ZA_for_VL_3072 skip
13553 10:08:21.774575 arm64_za-ptrace_Get_and_set_data_for_VL_3072 skip
13554 10:08:21.774671 arm64_za-ptrace_Set_VL_3088 pass
13555 10:08:21.774764 arm64_za-ptrace_Disabled_ZA_for_VL_3088 skip
13556 10:08:21.774856 arm64_za-ptrace_Get_and_set_data_for_VL_3088 skip
13557 10:08:21.774943 arm64_za-ptrace_Set_VL_3104 pass
13558 10:08:21.775040 arm64_za-ptrace_Disabled_ZA_for_VL_3104 skip
13559 10:08:21.775490 arm64_za-ptrace_Get_and_set_data_for_VL_3104 skip
13560 10:08:21.775587 arm64_za-ptrace_Set_VL_3120 pass
13561 10:08:21.775670 arm64_za-ptrace_Disabled_ZA_for_VL_3120 skip
13562 10:08:21.775759 arm64_za-ptrace_Get_and_set_data_for_VL_3120 skip
13563 10:08:21.775844 arm64_za-ptrace_Set_VL_3136 pass
13564 10:08:21.775930 arm64_za-ptrace_Disabled_ZA_for_VL_3136 skip
13565 10:08:21.776033 arm64_za-ptrace_Get_and_set_data_for_VL_3136 skip
13566 10:08:21.776120 arm64_za-ptrace_Set_VL_3152 pass
13567 10:08:21.776204 arm64_za-ptrace_Disabled_ZA_for_VL_3152 skip
13568 10:08:21.776289 arm64_za-ptrace_Get_and_set_data_for_VL_3152 skip
13569 10:08:21.776374 arm64_za-ptrace_Set_VL_3168 pass
13570 10:08:21.776475 arm64_za-ptrace_Disabled_ZA_for_VL_3168 skip
13571 10:08:21.776562 arm64_za-ptrace_Get_and_set_data_for_VL_3168 skip
13572 10:08:21.776646 arm64_za-ptrace_Set_VL_3184 pass
13573 10:08:21.776746 arm64_za-ptrace_Disabled_ZA_for_VL_3184 skip
13574 10:08:21.776826 arm64_za-ptrace_Get_and_set_data_for_VL_3184 skip
13575 10:08:21.776908 arm64_za-ptrace_Set_VL_3200 pass
13576 10:08:21.777009 arm64_za-ptrace_Disabled_ZA_for_VL_3200 skip
13577 10:08:21.777095 arm64_za-ptrace_Get_and_set_data_for_VL_3200 skip
13578 10:08:21.777182 arm64_za-ptrace_Set_VL_3216 pass
13579 10:08:21.777263 arm64_za-ptrace_Disabled_ZA_for_VL_3216 skip
13580 10:08:21.781210 arm64_za-ptrace_Get_and_set_data_for_VL_3216 skip
13581 10:08:21.781599 arm64_za-ptrace_Set_VL_3232 pass
13582 10:08:21.781731 arm64_za-ptrace_Disabled_ZA_for_VL_3232 skip
13583 10:08:21.781884 arm64_za-ptrace_Get_and_set_data_for_VL_3232 skip
13584 10:08:21.782006 arm64_za-ptrace_Set_VL_3248 pass
13585 10:08:21.782100 arm64_za-ptrace_Disabled_ZA_for_VL_3248 skip
13586 10:08:21.782225 arm64_za-ptrace_Get_and_set_data_for_VL_3248 skip
13587 10:08:21.782354 arm64_za-ptrace_Set_VL_3264 pass
13588 10:08:21.782465 arm64_za-ptrace_Disabled_ZA_for_VL_3264 skip
13589 10:08:21.782573 arm64_za-ptrace_Get_and_set_data_for_VL_3264 skip
13590 10:08:21.782684 arm64_za-ptrace_Set_VL_3280 pass
13591 10:08:21.782817 arm64_za-ptrace_Disabled_ZA_for_VL_3280 skip
13592 10:08:21.782920 arm64_za-ptrace_Get_and_set_data_for_VL_3280 skip
13593 10:08:21.783028 arm64_za-ptrace_Set_VL_3296 pass
13594 10:08:21.783135 arm64_za-ptrace_Disabled_ZA_for_VL_3296 skip
13595 10:08:21.783268 arm64_za-ptrace_Get_and_set_data_for_VL_3296 skip
13596 10:08:21.783371 arm64_za-ptrace_Set_VL_3312 pass
13597 10:08:21.783478 arm64_za-ptrace_Disabled_ZA_for_VL_3312 skip
13598 10:08:21.783584 arm64_za-ptrace_Get_and_set_data_for_VL_3312 skip
13599 10:08:21.783696 arm64_za-ptrace_Set_VL_3328 pass
13600 10:08:21.783803 arm64_za-ptrace_Disabled_ZA_for_VL_3328 skip
13601 10:08:21.783936 arm64_za-ptrace_Get_and_set_data_for_VL_3328 skip
13602 10:08:21.784037 arm64_za-ptrace_Set_VL_3344 pass
13603 10:08:21.784143 arm64_za-ptrace_Disabled_ZA_for_VL_3344 skip
13604 10:08:21.784250 arm64_za-ptrace_Get_and_set_data_for_VL_3344 skip
13605 10:08:21.784356 arm64_za-ptrace_Set_VL_3360 pass
13606 10:08:21.784488 arm64_za-ptrace_Disabled_ZA_for_VL_3360 skip
13607 10:08:21.784590 arm64_za-ptrace_Get_and_set_data_for_VL_3360 skip
13608 10:08:21.784702 arm64_za-ptrace_Set_VL_3376 pass
13609 10:08:21.785044 arm64_za-ptrace_Disabled_ZA_for_VL_3376 skip
13610 10:08:21.785171 arm64_za-ptrace_Get_and_set_data_for_VL_3376 skip
13611 10:08:21.785301 arm64_za-ptrace_Set_VL_3392 pass
13612 10:08:21.785410 arm64_za-ptrace_Disabled_ZA_for_VL_3392 skip
13613 10:08:21.785518 arm64_za-ptrace_Get_and_set_data_for_VL_3392 skip
13614 10:08:21.785626 arm64_za-ptrace_Set_VL_3408 pass
13615 10:08:21.785744 arm64_za-ptrace_Disabled_ZA_for_VL_3408 skip
13616 10:08:21.785852 arm64_za-ptrace_Get_and_set_data_for_VL_3408 skip
13617 10:08:21.789297 arm64_za-ptrace_Set_VL_3424 pass
13618 10:08:21.789504 arm64_za-ptrace_Disabled_ZA_for_VL_3424 skip
13619 10:08:21.789885 arm64_za-ptrace_Get_and_set_data_for_VL_3424 skip
13620 10:08:21.790022 arm64_za-ptrace_Set_VL_3440 pass
13621 10:08:21.790149 arm64_za-ptrace_Disabled_ZA_for_VL_3440 skip
13622 10:08:21.790285 arm64_za-ptrace_Get_and_set_data_for_VL_3440 skip
13623 10:08:21.790410 arm64_za-ptrace_Set_VL_3456 pass
13624 10:08:21.790546 arm64_za-ptrace_Disabled_ZA_for_VL_3456 skip
13625 10:08:21.790684 arm64_za-ptrace_Get_and_set_data_for_VL_3456 skip
13626 10:08:21.790796 arm64_za-ptrace_Set_VL_3472 pass
13627 10:08:21.790896 arm64_za-ptrace_Disabled_ZA_for_VL_3472 skip
13628 10:08:21.790997 arm64_za-ptrace_Get_and_set_data_for_VL_3472 skip
13629 10:08:21.791104 arm64_za-ptrace_Set_VL_3488 pass
13630 10:08:21.791213 arm64_za-ptrace_Disabled_ZA_for_VL_3488 skip
13631 10:08:21.791317 arm64_za-ptrace_Get_and_set_data_for_VL_3488 skip
13632 10:08:21.791770 arm64_za-ptrace_Set_VL_3504 pass
13633 10:08:21.791881 arm64_za-ptrace_Disabled_ZA_for_VL_3504 skip
13634 10:08:21.791964 arm64_za-ptrace_Get_and_set_data_for_VL_3504 skip
13635 10:08:21.792041 arm64_za-ptrace_Set_VL_3520 pass
13636 10:08:21.792117 arm64_za-ptrace_Disabled_ZA_for_VL_3520 skip
13637 10:08:21.792192 arm64_za-ptrace_Get_and_set_data_for_VL_3520 skip
13638 10:08:21.792268 arm64_za-ptrace_Set_VL_3536 pass
13639 10:08:21.792343 arm64_za-ptrace_Disabled_ZA_for_VL_3536 skip
13640 10:08:21.792418 arm64_za-ptrace_Get_and_set_data_for_VL_3536 skip
13641 10:08:21.792708 arm64_za-ptrace_Set_VL_3552 pass
13642 10:08:21.792825 arm64_za-ptrace_Disabled_ZA_for_VL_3552 skip
13643 10:08:21.792966 arm64_za-ptrace_Get_and_set_data_for_VL_3552 skip
13644 10:08:21.793054 arm64_za-ptrace_Set_VL_3568 pass
13645 10:08:21.793139 arm64_za-ptrace_Disabled_ZA_for_VL_3568 skip
13646 10:08:21.793224 arm64_za-ptrace_Get_and_set_data_for_VL_3568 skip
13647 10:08:21.793310 arm64_za-ptrace_Set_VL_3584 pass
13648 10:08:21.793395 arm64_za-ptrace_Disabled_ZA_for_VL_3584 skip
13649 10:08:21.793480 arm64_za-ptrace_Get_and_set_data_for_VL_3584 skip
13650 10:08:21.813514 arm64_za-ptrace_Set_VL_3600 pass
13651 10:08:21.813746 arm64_za-ptrace_Disabled_ZA_for_VL_3600 skip
13652 10:08:21.814052 arm64_za-ptrace_Get_and_set_data_for_VL_3600 skip
13653 10:08:21.814158 arm64_za-ptrace_Set_VL_3616 pass
13654 10:08:21.814228 arm64_za-ptrace_Disabled_ZA_for_VL_3616 skip
13655 10:08:21.814290 arm64_za-ptrace_Get_and_set_data_for_VL_3616 skip
13656 10:08:21.814352 arm64_za-ptrace_Set_VL_3632 pass
13657 10:08:21.814425 arm64_za-ptrace_Disabled_ZA_for_VL_3632 skip
13658 10:08:21.814489 arm64_za-ptrace_Get_and_set_data_for_VL_3632 skip
13659 10:08:21.814575 arm64_za-ptrace_Set_VL_3648 pass
13660 10:08:21.814665 arm64_za-ptrace_Disabled_ZA_for_VL_3648 skip
13661 10:08:21.814754 arm64_za-ptrace_Get_and_set_data_for_VL_3648 skip
13662 10:08:21.815005 arm64_za-ptrace_Set_VL_3664 pass
13663 10:08:21.815075 arm64_za-ptrace_Disabled_ZA_for_VL_3664 skip
13664 10:08:21.815337 arm64_za-ptrace_Get_and_set_data_for_VL_3664 skip
13665 10:08:21.815422 arm64_za-ptrace_Set_VL_3680 pass
13666 10:08:21.815520 arm64_za-ptrace_Disabled_ZA_for_VL_3680 skip
13667 10:08:21.815589 arm64_za-ptrace_Get_and_set_data_for_VL_3680 skip
13668 10:08:21.815662 arm64_za-ptrace_Set_VL_3696 pass
13669 10:08:21.815906 arm64_za-ptrace_Disabled_ZA_for_VL_3696 skip
13670 10:08:21.815975 arm64_za-ptrace_Get_and_set_data_for_VL_3696 skip
13671 10:08:21.816048 arm64_za-ptrace_Set_VL_3712 pass
13672 10:08:21.816302 arm64_za-ptrace_Disabled_ZA_for_VL_3712 skip
13673 10:08:21.816380 arm64_za-ptrace_Get_and_set_data_for_VL_3712 skip
13674 10:08:21.816444 arm64_za-ptrace_Set_VL_3728 pass
13675 10:08:21.816526 arm64_za-ptrace_Disabled_ZA_for_VL_3728 skip
13676 10:08:21.816619 arm64_za-ptrace_Get_and_set_data_for_VL_3728 skip
13677 10:08:21.816717 arm64_za-ptrace_Set_VL_3744 pass
13678 10:08:21.816972 arm64_za-ptrace_Disabled_ZA_for_VL_3744 skip
13679 10:08:21.817061 arm64_za-ptrace_Get_and_set_data_for_VL_3744 skip
13680 10:08:21.821431 arm64_za-ptrace_Set_VL_3760 pass
13681 10:08:21.821730 arm64_za-ptrace_Disabled_ZA_for_VL_3760 skip
13682 10:08:21.821801 arm64_za-ptrace_Get_and_set_data_for_VL_3760 skip
13683 10:08:21.821875 arm64_za-ptrace_Set_VL_3776 pass
13684 10:08:21.821975 arm64_za-ptrace_Disabled_ZA_for_VL_3776 skip
13685 10:08:21.822295 arm64_za-ptrace_Get_and_set_data_for_VL_3776 skip
13686 10:08:21.822388 arm64_za-ptrace_Set_VL_3792 pass
13687 10:08:21.822495 arm64_za-ptrace_Disabled_ZA_for_VL_3792 skip
13688 10:08:21.822586 arm64_za-ptrace_Get_and_set_data_for_VL_3792 skip
13689 10:08:21.822673 arm64_za-ptrace_Set_VL_3808 pass
13690 10:08:21.822743 arm64_za-ptrace_Disabled_ZA_for_VL_3808 skip
13691 10:08:21.822995 arm64_za-ptrace_Get_and_set_data_for_VL_3808 skip
13692 10:08:21.823072 arm64_za-ptrace_Set_VL_3824 pass
13693 10:08:21.823318 arm64_za-ptrace_Disabled_ZA_for_VL_3824 skip
13694 10:08:21.823383 arm64_za-ptrace_Get_and_set_data_for_VL_3824 skip
13695 10:08:21.823457 arm64_za-ptrace_Set_VL_3840 pass
13696 10:08:21.823521 arm64_za-ptrace_Disabled_ZA_for_VL_3840 skip
13697 10:08:21.823766 arm64_za-ptrace_Get_and_set_data_for_VL_3840 skip
13698 10:08:21.823834 arm64_za-ptrace_Set_VL_3856 pass
13699 10:08:21.823908 arm64_za-ptrace_Disabled_ZA_for_VL_3856 skip
13700 10:08:21.824165 arm64_za-ptrace_Get_and_set_data_for_VL_3856 skip
13701 10:08:21.824237 arm64_za-ptrace_Set_VL_3872 pass
13702 10:08:21.824314 arm64_za-ptrace_Disabled_ZA_for_VL_3872 skip
13703 10:08:21.824567 arm64_za-ptrace_Get_and_set_data_for_VL_3872 skip
13704 10:08:21.824642 arm64_za-ptrace_Set_VL_3888 pass
13705 10:08:21.824720 arm64_za-ptrace_Disabled_ZA_for_VL_3888 skip
13706 10:08:21.824977 arm64_za-ptrace_Get_and_set_data_for_VL_3888 skip
13707 10:08:21.825044 arm64_za-ptrace_Set_VL_3904 pass
13708 10:08:21.825117 arm64_za-ptrace_Disabled_ZA_for_VL_3904 skip
13709 10:08:21.829442 arm64_za-ptrace_Get_and_set_data_for_VL_3904 skip
13710 10:08:21.829784 arm64_za-ptrace_Set_VL_3920 pass
13711 10:08:21.829881 arm64_za-ptrace_Disabled_ZA_for_VL_3920 skip
13712 10:08:21.829984 arm64_za-ptrace_Get_and_set_data_for_VL_3920 skip
13713 10:08:21.830062 arm64_za-ptrace_Set_VL_3936 pass
13714 10:08:21.830324 arm64_za-ptrace_Disabled_ZA_for_VL_3936 skip
13715 10:08:21.830439 arm64_za-ptrace_Get_and_set_data_for_VL_3936 skip
13716 10:08:21.830526 arm64_za-ptrace_Set_VL_3952 pass
13717 10:08:21.830595 arm64_za-ptrace_Disabled_ZA_for_VL_3952 skip
13718 10:08:21.830672 arm64_za-ptrace_Get_and_set_data_for_VL_3952 skip
13719 10:08:21.830756 arm64_za-ptrace_Set_VL_3968 pass
13720 10:08:21.830830 arm64_za-ptrace_Disabled_ZA_for_VL_3968 skip
13721 10:08:21.830916 arm64_za-ptrace_Get_and_set_data_for_VL_3968 skip
13722 10:08:21.830994 arm64_za-ptrace_Set_VL_3984 pass
13723 10:08:21.831089 arm64_za-ptrace_Disabled_ZA_for_VL_3984 skip
13724 10:08:21.831199 arm64_za-ptrace_Get_and_set_data_for_VL_3984 skip
13725 10:08:21.831293 arm64_za-ptrace_Set_VL_4000 pass
13726 10:08:21.831606 arm64_za-ptrace_Disabled_ZA_for_VL_4000 skip
13727 10:08:21.831843 arm64_za-ptrace_Get_and_set_data_for_VL_4000 skip
13728 10:08:21.832089 arm64_za-ptrace_Set_VL_4016 pass
13729 10:08:21.832315 arm64_za-ptrace_Disabled_ZA_for_VL_4016 skip
13730 10:08:21.832556 arm64_za-ptrace_Get_and_set_data_for_VL_4016 skip
13731 10:08:21.832761 arm64_za-ptrace_Set_VL_4032 pass
13732 10:08:21.833001 arm64_za-ptrace_Disabled_ZA_for_VL_4032 skip
13733 10:08:21.833149 arm64_za-ptrace_Get_and_set_data_for_VL_4032 skip
13734 10:08:21.833269 arm64_za-ptrace_Set_VL_4048 pass
13735 10:08:21.833385 arm64_za-ptrace_Disabled_ZA_for_VL_4048 skip
13736 10:08:21.833499 arm64_za-ptrace_Get_and_set_data_for_VL_4048 skip
13737 10:08:21.833613 arm64_za-ptrace_Set_VL_4064 pass
13738 10:08:21.833747 arm64_za-ptrace_Disabled_ZA_for_VL_4064 skip
13739 10:08:21.833862 arm64_za-ptrace_Get_and_set_data_for_VL_4064 skip
13740 10:08:21.837319 arm64_za-ptrace_Set_VL_4080 pass
13741 10:08:21.837767 arm64_za-ptrace_Disabled_ZA_for_VL_4080 skip
13742 10:08:21.837865 arm64_za-ptrace_Get_and_set_data_for_VL_4080 skip
13743 10:08:21.837943 arm64_za-ptrace_Set_VL_4096 pass
13744 10:08:21.838020 arm64_za-ptrace_Disabled_ZA_for_VL_4096 skip
13745 10:08:21.838130 arm64_za-ptrace_Get_and_set_data_for_VL_4096 skip
13746 10:08:21.838223 arm64_za-ptrace_Set_VL_4112 pass
13747 10:08:21.838299 arm64_za-ptrace_Disabled_ZA_for_VL_4112 skip
13748 10:08:21.838405 arm64_za-ptrace_Get_and_set_data_for_VL_4112 skip
13749 10:08:21.838519 arm64_za-ptrace_Set_VL_4128 pass
13750 10:08:21.838607 arm64_za-ptrace_Disabled_ZA_for_VL_4128 skip
13751 10:08:21.838691 arm64_za-ptrace_Get_and_set_data_for_VL_4128 skip
13752 10:08:21.838781 arm64_za-ptrace_Set_VL_4144 pass
13753 10:08:21.839070 arm64_za-ptrace_Disabled_ZA_for_VL_4144 skip
13754 10:08:21.839166 arm64_za-ptrace_Get_and_set_data_for_VL_4144 skip
13755 10:08:21.839246 arm64_za-ptrace_Set_VL_4160 pass
13756 10:08:21.839340 arm64_za-ptrace_Disabled_ZA_for_VL_4160 skip
13757 10:08:21.839424 arm64_za-ptrace_Get_and_set_data_for_VL_4160 skip
13758 10:08:21.839506 arm64_za-ptrace_Set_VL_4176 pass
13759 10:08:21.839936 arm64_za-ptrace_Disabled_ZA_for_VL_4176 skip
13760 10:08:21.840122 arm64_za-ptrace_Get_and_set_data_for_VL_4176 skip
13761 10:08:21.840258 arm64_za-ptrace_Set_VL_4192 pass
13762 10:08:21.840414 arm64_za-ptrace_Disabled_ZA_for_VL_4192 skip
13763 10:08:21.840572 arm64_za-ptrace_Get_and_set_data_for_VL_4192 skip
13764 10:08:21.840719 arm64_za-ptrace_Set_VL_4208 pass
13765 10:08:21.840903 arm64_za-ptrace_Disabled_ZA_for_VL_4208 skip
13766 10:08:21.841065 arm64_za-ptrace_Get_and_set_data_for_VL_4208 skip
13767 10:08:21.841186 arm64_za-ptrace_Set_VL_4224 pass
13768 10:08:21.841303 arm64_za-ptrace_Disabled_ZA_for_VL_4224 skip
13769 10:08:21.841440 arm64_za-ptrace_Get_and_set_data_for_VL_4224 skip
13770 10:08:21.845338 arm64_za-ptrace_Set_VL_4240 pass
13771 10:08:21.845768 arm64_za-ptrace_Disabled_ZA_for_VL_4240 skip
13772 10:08:21.845867 arm64_za-ptrace_Get_and_set_data_for_VL_4240 skip
13773 10:08:21.845967 arm64_za-ptrace_Set_VL_4256 pass
13774 10:08:21.846078 arm64_za-ptrace_Disabled_ZA_for_VL_4256 skip
13775 10:08:21.846183 arm64_za-ptrace_Get_and_set_data_for_VL_4256 skip
13776 10:08:21.846318 arm64_za-ptrace_Set_VL_4272 pass
13777 10:08:21.846421 arm64_za-ptrace_Disabled_ZA_for_VL_4272 skip
13778 10:08:21.846529 arm64_za-ptrace_Get_and_set_data_for_VL_4272 skip
13779 10:08:21.846648 arm64_za-ptrace_Set_VL_4288 pass
13780 10:08:21.846751 arm64_za-ptrace_Disabled_ZA_for_VL_4288 skip
13781 10:08:21.846864 arm64_za-ptrace_Get_and_set_data_for_VL_4288 skip
13782 10:08:21.846969 arm64_za-ptrace_Set_VL_4304 pass
13783 10:08:21.847093 arm64_za-ptrace_Disabled_ZA_for_VL_4304 skip
13784 10:08:21.847196 arm64_za-ptrace_Get_and_set_data_for_VL_4304 skip
13785 10:08:21.847493 arm64_za-ptrace_Set_VL_4320 pass
13786 10:08:21.847599 arm64_za-ptrace_Disabled_ZA_for_VL_4320 skip
13787 10:08:21.847713 arm64_za-ptrace_Get_and_set_data_for_VL_4320 skip
13788 10:08:21.847813 arm64_za-ptrace_Set_VL_4336 pass
13789 10:08:21.847930 arm64_za-ptrace_Disabled_ZA_for_VL_4336 skip
13790 10:08:21.848026 arm64_za-ptrace_Get_and_set_data_for_VL_4336 skip
13791 10:08:21.848127 arm64_za-ptrace_Set_VL_4352 pass
13792 10:08:21.848245 arm64_za-ptrace_Disabled_ZA_for_VL_4352 skip
13793 10:08:21.848346 arm64_za-ptrace_Get_and_set_data_for_VL_4352 skip
13794 10:08:21.848647 arm64_za-ptrace_Set_VL_4368 pass
13795 10:08:21.848783 arm64_za-ptrace_Disabled_ZA_for_VL_4368 skip
13796 10:08:21.848904 arm64_za-ptrace_Get_and_set_data_for_VL_4368 skip
13797 10:08:21.848982 arm64_za-ptrace_Set_VL_4384 pass
13798 10:08:21.849079 arm64_za-ptrace_Disabled_ZA_for_VL_4384 skip
13799 10:08:21.849149 arm64_za-ptrace_Get_and_set_data_for_VL_4384 skip
13800 10:08:21.849210 arm64_za-ptrace_Set_VL_4400 pass
13801 10:08:21.853579 arm64_za-ptrace_Disabled_ZA_for_VL_4400 skip
13802 10:08:21.853727 arm64_za-ptrace_Get_and_set_data_for_VL_4400 skip
13803 10:08:21.853844 arm64_za-ptrace_Set_VL_4416 pass
13804 10:08:21.854151 arm64_za-ptrace_Disabled_ZA_for_VL_4416 skip
13805 10:08:21.854285 arm64_za-ptrace_Get_and_set_data_for_VL_4416 skip
13806 10:08:21.854412 arm64_za-ptrace_Set_VL_4432 pass
13807 10:08:21.854510 arm64_za-ptrace_Disabled_ZA_for_VL_4432 skip
13808 10:08:21.854604 arm64_za-ptrace_Get_and_set_data_for_VL_4432 skip
13809 10:08:21.854694 arm64_za-ptrace_Set_VL_4448 pass
13810 10:08:21.854788 arm64_za-ptrace_Disabled_ZA_for_VL_4448 skip
13811 10:08:21.854887 arm64_za-ptrace_Get_and_set_data_for_VL_4448 skip
13812 10:08:21.854964 arm64_za-ptrace_Set_VL_4464 pass
13813 10:08:21.855067 arm64_za-ptrace_Disabled_ZA_for_VL_4464 skip
13814 10:08:21.855167 arm64_za-ptrace_Get_and_set_data_for_VL_4464 skip
13815 10:08:21.855251 arm64_za-ptrace_Set_VL_4480 pass
13816 10:08:21.855331 arm64_za-ptrace_Disabled_ZA_for_VL_4480 skip
13817 10:08:21.855411 arm64_za-ptrace_Get_and_set_data_for_VL_4480 skip
13818 10:08:21.855488 arm64_za-ptrace_Set_VL_4496 pass
13819 10:08:21.855607 arm64_za-ptrace_Disabled_ZA_for_VL_4496 skip
13820 10:08:21.855705 arm64_za-ptrace_Get_and_set_data_for_VL_4496 skip
13821 10:08:21.855803 arm64_za-ptrace_Set_VL_4512 pass
13822 10:08:21.855913 arm64_za-ptrace_Disabled_ZA_for_VL_4512 skip
13823 10:08:21.856038 arm64_za-ptrace_Get_and_set_data_for_VL_4512 skip
13824 10:08:21.856137 arm64_za-ptrace_Set_VL_4528 pass
13825 10:08:21.856226 arm64_za-ptrace_Disabled_ZA_for_VL_4528 skip
13826 10:08:21.856339 arm64_za-ptrace_Get_and_set_data_for_VL_4528 skip
13827 10:08:21.856432 arm64_za-ptrace_Set_VL_4544 pass
13828 10:08:21.856515 arm64_za-ptrace_Disabled_ZA_for_VL_4544 skip
13829 10:08:21.856618 arm64_za-ptrace_Get_and_set_data_for_VL_4544 skip
13830 10:08:21.856710 arm64_za-ptrace_Set_VL_4560 pass
13831 10:08:21.856821 arm64_za-ptrace_Disabled_ZA_for_VL_4560 skip
13832 10:08:21.856932 arm64_za-ptrace_Get_and_set_data_for_VL_4560 skip
13833 10:08:21.857042 arm64_za-ptrace_Set_VL_4576 pass
13834 10:08:21.861271 arm64_za-ptrace_Disabled_ZA_for_VL_4576 skip
13835 10:08:21.861857 arm64_za-ptrace_Get_and_set_data_for_VL_4576 skip
13836 10:08:21.862087 arm64_za-ptrace_Set_VL_4592 pass
13837 10:08:21.862228 arm64_za-ptrace_Disabled_ZA_for_VL_4592 skip
13838 10:08:21.862342 arm64_za-ptrace_Get_and_set_data_for_VL_4592 skip
13839 10:08:21.862456 arm64_za-ptrace_Set_VL_4608 pass
13840 10:08:21.862597 arm64_za-ptrace_Disabled_ZA_for_VL_4608 skip
13841 10:08:21.862739 arm64_za-ptrace_Get_and_set_data_for_VL_4608 skip
13842 10:08:21.862888 arm64_za-ptrace_Set_VL_4624 pass
13843 10:08:21.882150 arm64_za-ptrace_Disabled_ZA_for_VL_4624 skip
13844 10:08:21.882411 arm64_za-ptrace_Get_and_set_data_for_VL_4624 skip
13845 10:08:21.882511 arm64_za-ptrace_Set_VL_4640 pass
13846 10:08:21.882618 arm64_za-ptrace_Disabled_ZA_for_VL_4640 skip
13847 10:08:21.882713 arm64_za-ptrace_Get_and_set_data_for_VL_4640 skip
13848 10:08:21.882801 arm64_za-ptrace_Set_VL_4656 pass
13849 10:08:21.882895 arm64_za-ptrace_Disabled_ZA_for_VL_4656 skip
13850 10:08:21.882982 arm64_za-ptrace_Get_and_set_data_for_VL_4656 skip
13851 10:08:21.883075 arm64_za-ptrace_Set_VL_4672 pass
13852 10:08:21.883187 arm64_za-ptrace_Disabled_ZA_for_VL_4672 skip
13853 10:08:21.883279 arm64_za-ptrace_Get_and_set_data_for_VL_4672 skip
13854 10:08:21.883369 arm64_za-ptrace_Set_VL_4688 pass
13855 10:08:21.883458 arm64_za-ptrace_Disabled_ZA_for_VL_4688 skip
13856 10:08:21.883545 arm64_za-ptrace_Get_and_set_data_for_VL_4688 skip
13857 10:08:21.883629 arm64_za-ptrace_Set_VL_4704 pass
13858 10:08:21.883730 arm64_za-ptrace_Disabled_ZA_for_VL_4704 skip
13859 10:08:21.883816 arm64_za-ptrace_Get_and_set_data_for_VL_4704 skip
13860 10:08:21.883900 arm64_za-ptrace_Set_VL_4720 pass
13861 10:08:21.883985 arm64_za-ptrace_Disabled_ZA_for_VL_4720 skip
13862 10:08:21.884071 arm64_za-ptrace_Get_and_set_data_for_VL_4720 skip
13863 10:08:21.884175 arm64_za-ptrace_Set_VL_4736 pass
13864 10:08:21.884264 arm64_za-ptrace_Disabled_ZA_for_VL_4736 skip
13865 10:08:21.884350 arm64_za-ptrace_Get_and_set_data_for_VL_4736 skip
13866 10:08:21.884436 arm64_za-ptrace_Set_VL_4752 pass
13867 10:08:21.884519 arm64_za-ptrace_Disabled_ZA_for_VL_4752 skip
13868 10:08:21.884603 arm64_za-ptrace_Get_and_set_data_for_VL_4752 skip
13869 10:08:21.884707 arm64_za-ptrace_Set_VL_4768 pass
13870 10:08:21.884795 arm64_za-ptrace_Disabled_ZA_for_VL_4768 skip
13871 10:08:21.884884 arm64_za-ptrace_Get_and_set_data_for_VL_4768 skip
13872 10:08:21.884972 arm64_za-ptrace_Set_VL_4784 pass
13873 10:08:21.885056 arm64_za-ptrace_Disabled_ZA_for_VL_4784 skip
13874 10:08:21.885142 arm64_za-ptrace_Get_and_set_data_for_VL_4784 skip
13875 10:08:21.885229 arm64_za-ptrace_Set_VL_4800 pass
13876 10:08:21.885332 arm64_za-ptrace_Disabled_ZA_for_VL_4800 skip
13877 10:08:21.885419 arm64_za-ptrace_Get_and_set_data_for_VL_4800 skip
13878 10:08:21.885503 arm64_za-ptrace_Set_VL_4816 pass
13879 10:08:21.889140 arm64_za-ptrace_Disabled_ZA_for_VL_4816 skip
13880 10:08:21.889460 arm64_za-ptrace_Get_and_set_data_for_VL_4816 skip
13881 10:08:21.889565 arm64_za-ptrace_Set_VL_4832 pass
13882 10:08:21.889657 arm64_za-ptrace_Disabled_ZA_for_VL_4832 skip
13883 10:08:21.889757 arm64_za-ptrace_Get_and_set_data_for_VL_4832 skip
13884 10:08:21.889841 arm64_za-ptrace_Set_VL_4848 pass
13885 10:08:21.889926 arm64_za-ptrace_Disabled_ZA_for_VL_4848 skip
13886 10:08:21.890023 arm64_za-ptrace_Get_and_set_data_for_VL_4848 skip
13887 10:08:21.890110 arm64_za-ptrace_Set_VL_4864 pass
13888 10:08:21.890194 arm64_za-ptrace_Disabled_ZA_for_VL_4864 skip
13889 10:08:21.890294 arm64_za-ptrace_Get_and_set_data_for_VL_4864 skip
13890 10:08:21.890383 arm64_za-ptrace_Set_VL_4880 pass
13891 10:08:21.890470 arm64_za-ptrace_Disabled_ZA_for_VL_4880 skip
13892 10:08:21.890556 arm64_za-ptrace_Get_and_set_data_for_VL_4880 skip
13893 10:08:21.890659 arm64_za-ptrace_Set_VL_4896 pass
13894 10:08:21.890746 arm64_za-ptrace_Disabled_ZA_for_VL_4896 skip
13895 10:08:21.890829 arm64_za-ptrace_Get_and_set_data_for_VL_4896 skip
13896 10:08:21.890913 arm64_za-ptrace_Set_VL_4912 pass
13897 10:08:21.891016 arm64_za-ptrace_Disabled_ZA_for_VL_4912 skip
13898 10:08:21.891103 arm64_za-ptrace_Get_and_set_data_for_VL_4912 skip
13899 10:08:21.891187 arm64_za-ptrace_Set_VL_4928 pass
13900 10:08:21.891270 arm64_za-ptrace_Disabled_ZA_for_VL_4928 skip
13901 10:08:21.891373 arm64_za-ptrace_Get_and_set_data_for_VL_4928 skip
13902 10:08:21.891461 arm64_za-ptrace_Set_VL_4944 pass
13903 10:08:21.891543 arm64_za-ptrace_Disabled_ZA_for_VL_4944 skip
13904 10:08:21.891643 arm64_za-ptrace_Get_and_set_data_for_VL_4944 skip
13905 10:08:21.891733 arm64_za-ptrace_Set_VL_4960 pass
13906 10:08:21.891819 arm64_za-ptrace_Disabled_ZA_for_VL_4960 skip
13907 10:08:21.891929 arm64_za-ptrace_Get_and_set_data_for_VL_4960 skip
13908 10:08:21.892020 arm64_za-ptrace_Set_VL_4976 pass
13909 10:08:21.892108 arm64_za-ptrace_Disabled_ZA_for_VL_4976 skip
13910 10:08:21.892195 arm64_za-ptrace_Get_and_set_data_for_VL_4976 skip
13911 10:08:21.892294 arm64_za-ptrace_Set_VL_4992 pass
13912 10:08:21.892378 arm64_za-ptrace_Disabled_ZA_for_VL_4992 skip
13913 10:08:21.892460 arm64_za-ptrace_Get_and_set_data_for_VL_4992 skip
13914 10:08:21.892541 arm64_za-ptrace_Set_VL_5008 pass
13915 10:08:21.892641 arm64_za-ptrace_Disabled_ZA_for_VL_5008 skip
13916 10:08:21.892731 arm64_za-ptrace_Get_and_set_data_for_VL_5008 skip
13917 10:08:21.892819 arm64_za-ptrace_Set_VL_5024 pass
13918 10:08:21.892927 arm64_za-ptrace_Disabled_ZA_for_VL_5024 skip
13919 10:08:21.893016 arm64_za-ptrace_Get_and_set_data_for_VL_5024 skip
13920 10:08:21.893101 arm64_za-ptrace_Set_VL_5040 pass
13921 10:08:21.893185 arm64_za-ptrace_Disabled_ZA_for_VL_5040 skip
13922 10:08:21.897204 arm64_za-ptrace_Get_and_set_data_for_VL_5040 skip
13923 10:08:21.897547 arm64_za-ptrace_Set_VL_5056 pass
13924 10:08:21.897686 arm64_za-ptrace_Disabled_ZA_for_VL_5056 skip
13925 10:08:21.897796 arm64_za-ptrace_Get_and_set_data_for_VL_5056 skip
13926 10:08:21.897917 arm64_za-ptrace_Set_VL_5072 pass
13927 10:08:21.898008 arm64_za-ptrace_Disabled_ZA_for_VL_5072 skip
13928 10:08:21.898108 arm64_za-ptrace_Get_and_set_data_for_VL_5072 skip
13929 10:08:21.898191 arm64_za-ptrace_Set_VL_5088 pass
13930 10:08:21.898269 arm64_za-ptrace_Disabled_ZA_for_VL_5088 skip
13931 10:08:21.898349 arm64_za-ptrace_Get_and_set_data_for_VL_5088 skip
13932 10:08:21.898429 arm64_za-ptrace_Set_VL_5104 pass
13933 10:08:21.898524 arm64_za-ptrace_Disabled_ZA_for_VL_5104 skip
13934 10:08:21.898605 arm64_za-ptrace_Get_and_set_data_for_VL_5104 skip
13935 10:08:21.898685 arm64_za-ptrace_Set_VL_5120 pass
13936 10:08:21.898765 arm64_za-ptrace_Disabled_ZA_for_VL_5120 skip
13937 10:08:21.898845 arm64_za-ptrace_Get_and_set_data_for_VL_5120 skip
13938 10:08:21.898943 arm64_za-ptrace_Set_VL_5136 pass
13939 10:08:21.899023 arm64_za-ptrace_Disabled_ZA_for_VL_5136 skip
13940 10:08:21.899099 arm64_za-ptrace_Get_and_set_data_for_VL_5136 skip
13941 10:08:21.899177 arm64_za-ptrace_Set_VL_5152 pass
13942 10:08:21.899269 arm64_za-ptrace_Disabled_ZA_for_VL_5152 skip
13943 10:08:21.899342 arm64_za-ptrace_Get_and_set_data_for_VL_5152 skip
13944 10:08:21.899419 arm64_za-ptrace_Set_VL_5168 pass
13945 10:08:21.899497 arm64_za-ptrace_Disabled_ZA_for_VL_5168 skip
13946 10:08:21.899591 arm64_za-ptrace_Get_and_set_data_for_VL_5168 skip
13947 10:08:21.899669 arm64_za-ptrace_Set_VL_5184 pass
13948 10:08:21.899749 arm64_za-ptrace_Disabled_ZA_for_VL_5184 skip
13949 10:08:21.899827 arm64_za-ptrace_Get_and_set_data_for_VL_5184 skip
13950 10:08:21.899921 arm64_za-ptrace_Set_VL_5200 pass
13951 10:08:21.900000 arm64_za-ptrace_Disabled_ZA_for_VL_5200 skip
13952 10:08:21.900077 arm64_za-ptrace_Get_and_set_data_for_VL_5200 skip
13953 10:08:21.900170 arm64_za-ptrace_Set_VL_5216 pass
13954 10:08:21.900253 arm64_za-ptrace_Disabled_ZA_for_VL_5216 skip
13955 10:08:21.900348 arm64_za-ptrace_Get_and_set_data_for_VL_5216 skip
13956 10:08:21.900431 arm64_za-ptrace_Set_VL_5232 pass
13957 10:08:21.900523 arm64_za-ptrace_Disabled_ZA_for_VL_5232 skip
13958 10:08:21.900616 arm64_za-ptrace_Get_and_set_data_for_VL_5232 skip
13959 10:08:21.900696 arm64_za-ptrace_Set_VL_5248 pass
13960 10:08:21.900788 arm64_za-ptrace_Disabled_ZA_for_VL_5248 skip
13961 10:08:21.900887 arm64_za-ptrace_Get_and_set_data_for_VL_5248 skip
13962 10:08:21.900966 arm64_za-ptrace_Set_VL_5264 pass
13963 10:08:21.901040 arm64_za-ptrace_Disabled_ZA_for_VL_5264 skip
13964 10:08:21.905403 arm64_za-ptrace_Get_and_set_data_for_VL_5264 skip
13965 10:08:21.905592 arm64_za-ptrace_Set_VL_5280 pass
13966 10:08:21.905684 arm64_za-ptrace_Disabled_ZA_for_VL_5280 skip
13967 10:08:21.905779 arm64_za-ptrace_Get_and_set_data_for_VL_5280 skip
13968 10:08:21.905854 arm64_za-ptrace_Set_VL_5296 pass
13969 10:08:21.905925 arm64_za-ptrace_Disabled_ZA_for_VL_5296 skip
13970 10:08:21.906010 arm64_za-ptrace_Get_and_set_data_for_VL_5296 skip
13971 10:08:21.906088 arm64_za-ptrace_Set_VL_5312 pass
13972 10:08:21.906153 arm64_za-ptrace_Disabled_ZA_for_VL_5312 skip
13973 10:08:21.906226 arm64_za-ptrace_Get_and_set_data_for_VL_5312 skip
13974 10:08:21.906288 arm64_za-ptrace_Set_VL_5328 pass
13975 10:08:21.906349 arm64_za-ptrace_Disabled_ZA_for_VL_5328 skip
13976 10:08:21.906425 arm64_za-ptrace_Get_and_set_data_for_VL_5328 skip
13977 10:08:21.906487 arm64_za-ptrace_Set_VL_5344 pass
13978 10:08:21.906547 arm64_za-ptrace_Disabled_ZA_for_VL_5344 skip
13979 10:08:21.906618 arm64_za-ptrace_Get_and_set_data_for_VL_5344 skip
13980 10:08:21.906679 arm64_za-ptrace_Set_VL_5360 pass
13981 10:08:21.906751 arm64_za-ptrace_Disabled_ZA_for_VL_5360 skip
13982 10:08:21.906823 arm64_za-ptrace_Get_and_set_data_for_VL_5360 skip
13983 10:08:21.906885 arm64_za-ptrace_Set_VL_5376 pass
13984 10:08:21.906956 arm64_za-ptrace_Disabled_ZA_for_VL_5376 skip
13985 10:08:21.907029 arm64_za-ptrace_Get_and_set_data_for_VL_5376 skip
13986 10:08:21.907101 arm64_za-ptrace_Set_VL_5392 pass
13987 10:08:21.907345 arm64_za-ptrace_Disabled_ZA_for_VL_5392 skip
13988 10:08:21.907410 arm64_za-ptrace_Get_and_set_data_for_VL_5392 skip
13989 10:08:21.907470 arm64_za-ptrace_Set_VL_5408 pass
13990 10:08:21.907541 arm64_za-ptrace_Disabled_ZA_for_VL_5408 skip
13991 10:08:21.907782 arm64_za-ptrace_Get_and_set_data_for_VL_5408 skip
13992 10:08:21.907849 arm64_za-ptrace_Set_VL_5424 pass
13993 10:08:21.907912 arm64_za-ptrace_Disabled_ZA_for_VL_5424 skip
13994 10:08:21.907982 arm64_za-ptrace_Get_and_set_data_for_VL_5424 skip
13995 10:08:21.908044 arm64_za-ptrace_Set_VL_5440 pass
13996 10:08:21.908104 arm64_za-ptrace_Disabled_ZA_for_VL_5440 skip
13997 10:08:21.908174 arm64_za-ptrace_Get_and_set_data_for_VL_5440 skip
13998 10:08:21.908234 arm64_za-ptrace_Set_VL_5456 pass
13999 10:08:21.908305 arm64_za-ptrace_Disabled_ZA_for_VL_5456 skip
14000 10:08:21.908366 arm64_za-ptrace_Get_and_set_data_for_VL_5456 skip
14001 10:08:21.908437 arm64_za-ptrace_Set_VL_5472 pass
14002 10:08:21.908499 arm64_za-ptrace_Disabled_ZA_for_VL_5472 skip
14003 10:08:21.908570 arm64_za-ptrace_Get_and_set_data_for_VL_5472 skip
14004 10:08:21.908642 arm64_za-ptrace_Set_VL_5488 pass
14005 10:08:21.908704 arm64_za-ptrace_Disabled_ZA_for_VL_5488 skip
14006 10:08:21.908774 arm64_za-ptrace_Get_and_set_data_for_VL_5488 skip
14007 10:08:21.908848 arm64_za-ptrace_Set_VL_5504 pass
14008 10:08:21.908912 arm64_za-ptrace_Disabled_ZA_for_VL_5504 skip
14009 10:08:21.908982 arm64_za-ptrace_Get_and_set_data_for_VL_5504 skip
14010 10:08:21.913136 arm64_za-ptrace_Set_VL_5520 pass
14011 10:08:21.913407 arm64_za-ptrace_Disabled_ZA_for_VL_5520 skip
14012 10:08:21.913487 arm64_za-ptrace_Get_and_set_data_for_VL_5520 skip
14013 10:08:21.913562 arm64_za-ptrace_Set_VL_5536 pass
14014 10:08:21.913699 arm64_za-ptrace_Disabled_ZA_for_VL_5536 skip
14015 10:08:21.913825 arm64_za-ptrace_Get_and_set_data_for_VL_5536 skip
14016 10:08:21.913939 arm64_za-ptrace_Set_VL_5552 pass
14017 10:08:21.914037 arm64_za-ptrace_Disabled_ZA_for_VL_5552 skip
14018 10:08:21.914164 arm64_za-ptrace_Get_and_set_data_for_VL_5552 skip
14019 10:08:21.914260 arm64_za-ptrace_Set_VL_5568 pass
14020 10:08:21.914347 arm64_za-ptrace_Disabled_ZA_for_VL_5568 skip
14021 10:08:21.914423 arm64_za-ptrace_Get_and_set_data_for_VL_5568 skip
14022 10:08:21.914510 arm64_za-ptrace_Set_VL_5584 pass
14023 10:08:21.914579 arm64_za-ptrace_Disabled_ZA_for_VL_5584 skip
14024 10:08:21.914654 arm64_za-ptrace_Get_and_set_data_for_VL_5584 skip
14025 10:08:21.914726 arm64_za-ptrace_Set_VL_5600 pass
14026 10:08:21.914813 arm64_za-ptrace_Disabled_ZA_for_VL_5600 skip
14027 10:08:21.914887 arm64_za-ptrace_Get_and_set_data_for_VL_5600 skip
14028 10:08:21.914954 arm64_za-ptrace_Set_VL_5616 pass
14029 10:08:21.915023 arm64_za-ptrace_Disabled_ZA_for_VL_5616 skip
14030 10:08:21.915277 arm64_za-ptrace_Get_and_set_data_for_VL_5616 skip
14031 10:08:21.915352 arm64_za-ptrace_Set_VL_5632 pass
14032 10:08:21.915468 arm64_za-ptrace_Disabled_ZA_for_VL_5632 skip
14033 10:08:21.915548 arm64_za-ptrace_Get_and_set_data_for_VL_5632 skip
14034 10:08:21.915636 arm64_za-ptrace_Set_VL_5648 pass
14035 10:08:21.932474 arm64_za-ptrace_Disabled_ZA_for_VL_5648 skip
14036 10:08:21.932809 arm64_za-ptrace_Get_and_set_data_for_VL_5648 skip
14037 10:08:21.932967 arm64_za-ptrace_Set_VL_5664 pass
14038 10:08:21.933154 arm64_za-ptrace_Disabled_ZA_for_VL_5664 skip
14039 10:08:21.933334 arm64_za-ptrace_Get_and_set_data_for_VL_5664 skip
14040 10:08:21.933489 arm64_za-ptrace_Set_VL_5680 pass
14041 10:08:21.933639 arm64_za-ptrace_Disabled_ZA_for_VL_5680 skip
14042 10:08:21.933847 arm64_za-ptrace_Get_and_set_data_for_VL_5680 skip
14043 10:08:21.934050 arm64_za-ptrace_Set_VL_5696 pass
14044 10:08:21.934268 arm64_za-ptrace_Disabled_ZA_for_VL_5696 skip
14045 10:08:21.934435 arm64_za-ptrace_Get_and_set_data_for_VL_5696 skip
14046 10:08:21.934612 arm64_za-ptrace_Set_VL_5712 pass
14047 10:08:21.934862 arm64_za-ptrace_Disabled_ZA_for_VL_5712 skip
14048 10:08:21.935068 arm64_za-ptrace_Get_and_set_data_for_VL_5712 skip
14049 10:08:21.935268 arm64_za-ptrace_Set_VL_5728 pass
14050 10:08:21.935468 arm64_za-ptrace_Disabled_ZA_for_VL_5728 skip
14051 10:08:21.935640 arm64_za-ptrace_Get_and_set_data_for_VL_5728 skip
14052 10:08:21.935823 arm64_za-ptrace_Set_VL_5744 pass
14053 10:08:21.936000 arm64_za-ptrace_Disabled_ZA_for_VL_5744 skip
14054 10:08:21.936172 arm64_za-ptrace_Get_and_set_data_for_VL_5744 skip
14055 10:08:21.936323 arm64_za-ptrace_Set_VL_5760 pass
14056 10:08:21.936440 arm64_za-ptrace_Disabled_ZA_for_VL_5760 skip
14057 10:08:21.936558 arm64_za-ptrace_Get_and_set_data_for_VL_5760 skip
14058 10:08:21.936699 arm64_za-ptrace_Set_VL_5776 pass
14059 10:08:21.936880 arm64_za-ptrace_Disabled_ZA_for_VL_5776 skip
14060 10:08:21.937066 arm64_za-ptrace_Get_and_set_data_for_VL_5776 skip
14061 10:08:21.937201 arm64_za-ptrace_Set_VL_5792 pass
14062 10:08:21.937317 arm64_za-ptrace_Disabled_ZA_for_VL_5792 skip
14063 10:08:21.937429 arm64_za-ptrace_Get_and_set_data_for_VL_5792 skip
14064 10:08:21.937541 arm64_za-ptrace_Set_VL_5808 pass
14065 10:08:21.937692 arm64_za-ptrace_Disabled_ZA_for_VL_5808 skip
14066 10:08:21.937903 arm64_za-ptrace_Get_and_set_data_for_VL_5808 skip
14067 10:08:21.938098 arm64_za-ptrace_Set_VL_5824 pass
14068 10:08:21.938276 arm64_za-ptrace_Disabled_ZA_for_VL_5824 skip
14069 10:08:21.938418 arm64_za-ptrace_Get_and_set_data_for_VL_5824 skip
14070 10:08:21.938560 arm64_za-ptrace_Set_VL_5840 pass
14071 10:08:21.938701 arm64_za-ptrace_Disabled_ZA_for_VL_5840 skip
14072 10:08:21.938842 arm64_za-ptrace_Get_and_set_data_for_VL_5840 skip
14073 10:08:21.938987 arm64_za-ptrace_Set_VL_5856 pass
14074 10:08:21.939126 arm64_za-ptrace_Disabled_ZA_for_VL_5856 skip
14075 10:08:21.939267 arm64_za-ptrace_Get_and_set_data_for_VL_5856 skip
14076 10:08:21.939407 arm64_za-ptrace_Set_VL_5872 pass
14077 10:08:21.939548 arm64_za-ptrace_Disabled_ZA_for_VL_5872 skip
14078 10:08:21.939689 arm64_za-ptrace_Get_and_set_data_for_VL_5872 skip
14079 10:08:21.939830 arm64_za-ptrace_Set_VL_5888 pass
14080 10:08:21.940006 arm64_za-ptrace_Disabled_ZA_for_VL_5888 skip
14081 10:08:21.941192 arm64_za-ptrace_Get_and_set_data_for_VL_5888 skip
14082 10:08:21.941400 arm64_za-ptrace_Set_VL_5904 pass
14083 10:08:21.941845 arm64_za-ptrace_Disabled_ZA_for_VL_5904 skip
14084 10:08:21.941998 arm64_za-ptrace_Get_and_set_data_for_VL_5904 skip
14085 10:08:21.942129 arm64_za-ptrace_Set_VL_5920 pass
14086 10:08:21.942262 arm64_za-ptrace_Disabled_ZA_for_VL_5920 skip
14087 10:08:21.942379 arm64_za-ptrace_Get_and_set_data_for_VL_5920 skip
14088 10:08:21.942520 arm64_za-ptrace_Set_VL_5936 pass
14089 10:08:21.942636 arm64_za-ptrace_Disabled_ZA_for_VL_5936 skip
14090 10:08:21.942761 arm64_za-ptrace_Get_and_set_data_for_VL_5936 skip
14091 10:08:21.942881 arm64_za-ptrace_Set_VL_5952 pass
14092 10:08:21.943001 arm64_za-ptrace_Disabled_ZA_for_VL_5952 skip
14093 10:08:21.943117 arm64_za-ptrace_Get_and_set_data_for_VL_5952 skip
14094 10:08:21.943232 arm64_za-ptrace_Set_VL_5968 pass
14095 10:08:21.943348 arm64_za-ptrace_Disabled_ZA_for_VL_5968 skip
14096 10:08:21.943494 arm64_za-ptrace_Get_and_set_data_for_VL_5968 skip
14097 10:08:21.943623 arm64_za-ptrace_Set_VL_5984 pass
14098 10:08:21.943751 arm64_za-ptrace_Disabled_ZA_for_VL_5984 skip
14099 10:08:21.943893 arm64_za-ptrace_Get_and_set_data_for_VL_5984 skip
14100 10:08:21.944010 arm64_za-ptrace_Set_VL_6000 pass
14101 10:08:21.944130 arm64_za-ptrace_Disabled_ZA_for_VL_6000 skip
14102 10:08:21.944248 arm64_za-ptrace_Get_and_set_data_for_VL_6000 skip
14103 10:08:21.944360 arm64_za-ptrace_Set_VL_6016 pass
14104 10:08:21.944476 arm64_za-ptrace_Disabled_ZA_for_VL_6016 skip
14105 10:08:21.944647 arm64_za-ptrace_Get_and_set_data_for_VL_6016 skip
14106 10:08:21.944754 arm64_za-ptrace_Set_VL_6032 pass
14107 10:08:21.944880 arm64_za-ptrace_Disabled_ZA_for_VL_6032 skip
14108 10:08:21.944994 arm64_za-ptrace_Get_and_set_data_for_VL_6032 skip
14109 10:08:21.945082 arm64_za-ptrace_Set_VL_6048 pass
14110 10:08:21.945167 arm64_za-ptrace_Disabled_ZA_for_VL_6048 skip
14111 10:08:21.945251 arm64_za-ptrace_Get_and_set_data_for_VL_6048 skip
14112 10:08:21.945336 arm64_za-ptrace_Set_VL_6064 pass
14113 10:08:21.945421 arm64_za-ptrace_Disabled_ZA_for_VL_6064 skip
14114 10:08:21.945506 arm64_za-ptrace_Get_and_set_data_for_VL_6064 skip
14115 10:08:21.945589 arm64_za-ptrace_Set_VL_6080 pass
14116 10:08:21.945735 arm64_za-ptrace_Disabled_ZA_for_VL_6080 skip
14117 10:08:21.945888 arm64_za-ptrace_Get_and_set_data_for_VL_6080 skip
14118 10:08:21.945998 arm64_za-ptrace_Set_VL_6096 pass
14119 10:08:21.949158 arm64_za-ptrace_Disabled_ZA_for_VL_6096 skip
14120 10:08:21.949496 arm64_za-ptrace_Get_and_set_data_for_VL_6096 skip
14121 10:08:21.949616 arm64_za-ptrace_Set_VL_6112 pass
14122 10:08:21.949732 arm64_za-ptrace_Disabled_ZA_for_VL_6112 skip
14123 10:08:21.949860 arm64_za-ptrace_Get_and_set_data_for_VL_6112 skip
14124 10:08:21.949960 arm64_za-ptrace_Set_VL_6128 pass
14125 10:08:21.950037 arm64_za-ptrace_Disabled_ZA_for_VL_6128 skip
14126 10:08:21.950103 arm64_za-ptrace_Get_and_set_data_for_VL_6128 skip
14127 10:08:21.950192 arm64_za-ptrace_Set_VL_6144 pass
14128 10:08:21.950271 arm64_za-ptrace_Disabled_ZA_for_VL_6144 skip
14129 10:08:21.950344 arm64_za-ptrace_Get_and_set_data_for_VL_6144 skip
14130 10:08:21.950438 arm64_za-ptrace_Set_VL_6160 pass
14131 10:08:21.950521 arm64_za-ptrace_Disabled_ZA_for_VL_6160 skip
14132 10:08:21.950613 arm64_za-ptrace_Get_and_set_data_for_VL_6160 skip
14133 10:08:21.950694 arm64_za-ptrace_Set_VL_6176 pass
14134 10:08:21.950786 arm64_za-ptrace_Disabled_ZA_for_VL_6176 skip
14135 10:08:21.950867 arm64_za-ptrace_Get_and_set_data_for_VL_6176 skip
14136 10:08:21.951005 arm64_za-ptrace_Set_VL_6192 pass
14137 10:08:21.951165 arm64_za-ptrace_Disabled_ZA_for_VL_6192 skip
14138 10:08:21.951357 arm64_za-ptrace_Get_and_set_data_for_VL_6192 skip
14139 10:08:21.951573 arm64_za-ptrace_Set_VL_6208 pass
14140 10:08:21.951786 arm64_za-ptrace_Disabled_ZA_for_VL_6208 skip
14141 10:08:21.952047 arm64_za-ptrace_Get_and_set_data_for_VL_6208 skip
14142 10:08:21.952245 arm64_za-ptrace_Set_VL_6224 pass
14143 10:08:21.952463 arm64_za-ptrace_Disabled_ZA_for_VL_6224 skip
14144 10:08:21.952676 arm64_za-ptrace_Get_and_set_data_for_VL_6224 skip
14145 10:08:21.952868 arm64_za-ptrace_Set_VL_6240 pass
14146 10:08:21.953048 arm64_za-ptrace_Disabled_ZA_for_VL_6240 skip
14147 10:08:21.953216 arm64_za-ptrace_Get_and_set_data_for_VL_6240 skip
14148 10:08:21.953343 arm64_za-ptrace_Set_VL_6256 pass
14149 10:08:21.953484 arm64_za-ptrace_Disabled_ZA_for_VL_6256 skip
14150 10:08:21.953604 arm64_za-ptrace_Get_and_set_data_for_VL_6256 skip
14151 10:08:21.953813 arm64_za-ptrace_Set_VL_6272 pass
14152 10:08:21.954007 arm64_za-ptrace_Disabled_ZA_for_VL_6272 skip
14153 10:08:21.954186 arm64_za-ptrace_Get_and_set_data_for_VL_6272 skip
14154 10:08:21.954365 arm64_za-ptrace_Set_VL_6288 pass
14155 10:08:21.954545 arm64_za-ptrace_Disabled_ZA_for_VL_6288 skip
14156 10:08:21.954724 arm64_za-ptrace_Get_and_set_data_for_VL_6288 skip
14157 10:08:21.954904 arm64_za-ptrace_Set_VL_6304 pass
14158 10:08:21.955049 arm64_za-ptrace_Disabled_ZA_for_VL_6304 skip
14159 10:08:21.957157 arm64_za-ptrace_Get_and_set_data_for_VL_6304 skip
14160 10:08:21.957511 arm64_za-ptrace_Set_VL_6320 pass
14161 10:08:21.957661 arm64_za-ptrace_Disabled_ZA_for_VL_6320 skip
14162 10:08:21.957788 arm64_za-ptrace_Get_and_set_data_for_VL_6320 skip
14163 10:08:21.957902 arm64_za-ptrace_Set_VL_6336 pass
14164 10:08:21.957993 arm64_za-ptrace_Disabled_ZA_for_VL_6336 skip
14165 10:08:21.958064 arm64_za-ptrace_Get_and_set_data_for_VL_6336 skip
14166 10:08:21.958136 arm64_za-ptrace_Set_VL_6352 pass
14167 10:08:21.958225 arm64_za-ptrace_Disabled_ZA_for_VL_6352 skip
14168 10:08:21.958348 arm64_za-ptrace_Get_and_set_data_for_VL_6352 skip
14169 10:08:21.958439 arm64_za-ptrace_Set_VL_6368 pass
14170 10:08:21.958547 arm64_za-ptrace_Disabled_ZA_for_VL_6368 skip
14171 10:08:21.958652 arm64_za-ptrace_Get_and_set_data_for_VL_6368 skip
14172 10:08:21.958760 arm64_za-ptrace_Set_VL_6384 pass
14173 10:08:21.958861 arm64_za-ptrace_Disabled_ZA_for_VL_6384 skip
14174 10:08:21.958940 arm64_za-ptrace_Get_and_set_data_for_VL_6384 skip
14175 10:08:21.959043 arm64_za-ptrace_Set_VL_6400 pass
14176 10:08:21.959132 arm64_za-ptrace_Disabled_ZA_for_VL_6400 skip
14177 10:08:21.959231 arm64_za-ptrace_Get_and_set_data_for_VL_6400 skip
14178 10:08:21.959317 arm64_za-ptrace_Set_VL_6416 pass
14179 10:08:21.959397 arm64_za-ptrace_Disabled_ZA_for_VL_6416 skip
14180 10:08:21.959518 arm64_za-ptrace_Get_and_set_data_for_VL_6416 skip
14181 10:08:21.959609 arm64_za-ptrace_Set_VL_6432 pass
14182 10:08:21.959705 arm64_za-ptrace_Disabled_ZA_for_VL_6432 skip
14183 10:08:21.959810 arm64_za-ptrace_Get_and_set_data_for_VL_6432 skip
14184 10:08:21.959884 arm64_za-ptrace_Set_VL_6448 pass
14185 10:08:21.959968 arm64_za-ptrace_Disabled_ZA_for_VL_6448 skip
14186 10:08:21.960047 arm64_za-ptrace_Get_and_set_data_for_VL_6448 skip
14187 10:08:21.960135 arm64_za-ptrace_Set_VL_6464 pass
14188 10:08:21.960228 arm64_za-ptrace_Disabled_ZA_for_VL_6464 skip
14189 10:08:21.960347 arm64_za-ptrace_Get_and_set_data_for_VL_6464 skip
14190 10:08:21.960465 arm64_za-ptrace_Set_VL_6480 pass
14191 10:08:21.960581 arm64_za-ptrace_Disabled_ZA_for_VL_6480 skip
14192 10:08:21.960677 arm64_za-ptrace_Get_and_set_data_for_VL_6480 skip
14193 10:08:21.960776 arm64_za-ptrace_Set_VL_6496 pass
14194 10:08:21.960855 arm64_za-ptrace_Disabled_ZA_for_VL_6496 skip
14195 10:08:21.960940 arm64_za-ptrace_Get_and_set_data_for_VL_6496 skip
14196 10:08:21.961029 arm64_za-ptrace_Set_VL_6512 pass
14197 10:08:21.965141 arm64_za-ptrace_Disabled_ZA_for_VL_6512 skip
14198 10:08:21.965452 arm64_za-ptrace_Get_and_set_data_for_VL_6512 skip
14199 10:08:21.965557 arm64_za-ptrace_Set_VL_6528 pass
14200 10:08:21.965668 arm64_za-ptrace_Disabled_ZA_for_VL_6528 skip
14201 10:08:21.965773 arm64_za-ptrace_Get_and_set_data_for_VL_6528 skip
14202 10:08:21.965875 arm64_za-ptrace_Set_VL_6544 pass
14203 10:08:21.965966 arm64_za-ptrace_Disabled_ZA_for_VL_6544 skip
14204 10:08:21.966064 arm64_za-ptrace_Get_and_set_data_for_VL_6544 skip
14205 10:08:21.966162 arm64_za-ptrace_Set_VL_6560 pass
14206 10:08:21.966459 arm64_za-ptrace_Disabled_ZA_for_VL_6560 skip
14207 10:08:21.966560 arm64_za-ptrace_Get_and_set_data_for_VL_6560 skip
14208 10:08:21.966661 arm64_za-ptrace_Set_VL_6576 pass
14209 10:08:21.966750 arm64_za-ptrace_Disabled_ZA_for_VL_6576 skip
14210 10:08:21.966849 arm64_za-ptrace_Get_and_set_data_for_VL_6576 skip
14211 10:08:21.966947 arm64_za-ptrace_Set_VL_6592 pass
14212 10:08:21.967242 arm64_za-ptrace_Disabled_ZA_for_VL_6592 skip
14213 10:08:21.967342 arm64_za-ptrace_Get_and_set_data_for_VL_6592 skip
14214 10:08:21.967441 arm64_za-ptrace_Set_VL_6608 pass
14215 10:08:21.967543 arm64_za-ptrace_Disabled_ZA_for_VL_6608 skip
14216 10:08:21.967641 arm64_za-ptrace_Get_and_set_data_for_VL_6608 skip
14217 10:08:21.967747 arm64_za-ptrace_Set_VL_6624 pass
14218 10:08:21.968049 arm64_za-ptrace_Disabled_ZA_for_VL_6624 skip
14219 10:08:21.968150 arm64_za-ptrace_Get_and_set_data_for_VL_6624 skip
14220 10:08:21.968251 arm64_za-ptrace_Set_VL_6640 pass
14221 10:08:21.968339 arm64_za-ptrace_Disabled_ZA_for_VL_6640 skip
14222 10:08:21.968437 arm64_za-ptrace_Get_and_set_data_for_VL_6640 skip
14223 10:08:21.968796 arm64_za-ptrace_Set_VL_6656 pass
14224 10:08:21.968935 arm64_za-ptrace_Disabled_ZA_for_VL_6656 skip
14225 10:08:21.969037 arm64_za-ptrace_Get_and_set_data_for_VL_6656 skip
14226 10:08:21.969319 arm64_za-ptrace_Set_VL_6672 pass
14227 10:08:21.973448 arm64_za-ptrace_Disabled_ZA_for_VL_6672 skip
14228 10:08:21.986109 arm64_za-ptrace_Get_and_set_data_for_VL_6672 skip
14229 10:08:21.986340 arm64_za-ptrace_Set_VL_6688 pass
14230 10:08:21.986562 arm64_za-ptrace_Disabled_ZA_for_VL_6688 skip
14231 10:08:21.986755 arm64_za-ptrace_Get_and_set_data_for_VL_6688 skip
14232 10:08:21.986913 arm64_za-ptrace_Set_VL_6704 pass
14233 10:08:21.987050 arm64_za-ptrace_Disabled_ZA_for_VL_6704 skip
14234 10:08:21.987227 arm64_za-ptrace_Get_and_set_data_for_VL_6704 skip
14235 10:08:21.987390 arm64_za-ptrace_Set_VL_6720 pass
14236 10:08:21.987553 arm64_za-ptrace_Disabled_ZA_for_VL_6720 skip
14237 10:08:21.987748 arm64_za-ptrace_Get_and_set_data_for_VL_6720 skip
14238 10:08:21.987916 arm64_za-ptrace_Set_VL_6736 pass
14239 10:08:21.988081 arm64_za-ptrace_Disabled_ZA_for_VL_6736 skip
14240 10:08:21.988245 arm64_za-ptrace_Get_and_set_data_for_VL_6736 skip
14241 10:08:21.988403 arm64_za-ptrace_Set_VL_6752 pass
14242 10:08:21.988599 arm64_za-ptrace_Disabled_ZA_for_VL_6752 skip
14243 10:08:21.988761 arm64_za-ptrace_Get_and_set_data_for_VL_6752 skip
14244 10:08:21.988895 arm64_za-ptrace_Set_VL_6768 pass
14245 10:08:21.989010 arm64_za-ptrace_Disabled_ZA_for_VL_6768 skip
14246 10:08:21.989120 arm64_za-ptrace_Get_and_set_data_for_VL_6768 skip
14247 10:08:21.989230 arm64_za-ptrace_Set_VL_6784 pass
14248 10:08:21.989341 arm64_za-ptrace_Disabled_ZA_for_VL_6784 skip
14249 10:08:21.989450 arm64_za-ptrace_Get_and_set_data_for_VL_6784 skip
14250 10:08:21.989559 arm64_za-ptrace_Set_VL_6800 pass
14251 10:08:21.989689 arm64_za-ptrace_Disabled_ZA_for_VL_6800 skip
14252 10:08:21.989801 arm64_za-ptrace_Get_and_set_data_for_VL_6800 skip
14253 10:08:21.989909 arm64_za-ptrace_Set_VL_6816 pass
14254 10:08:21.990047 arm64_za-ptrace_Disabled_ZA_for_VL_6816 skip
14255 10:08:21.990161 arm64_za-ptrace_Get_and_set_data_for_VL_6816 skip
14256 10:08:21.990275 arm64_za-ptrace_Set_VL_6832 pass
14257 10:08:21.990385 arm64_za-ptrace_Disabled_ZA_for_VL_6832 skip
14258 10:08:21.993228 arm64_za-ptrace_Get_and_set_data_for_VL_6832 skip
14259 10:08:21.993404 arm64_za-ptrace_Set_VL_6848 pass
14260 10:08:21.993790 arm64_za-ptrace_Disabled_ZA_for_VL_6848 skip
14261 10:08:21.993987 arm64_za-ptrace_Get_and_set_data_for_VL_6848 skip
14262 10:08:21.994187 arm64_za-ptrace_Set_VL_6864 pass
14263 10:08:21.994329 arm64_za-ptrace_Disabled_ZA_for_VL_6864 skip
14264 10:08:21.994498 arm64_za-ptrace_Get_and_set_data_for_VL_6864 skip
14265 10:08:21.994660 arm64_za-ptrace_Set_VL_6880 pass
14266 10:08:21.994854 arm64_za-ptrace_Disabled_ZA_for_VL_6880 skip
14267 10:08:21.995025 arm64_za-ptrace_Get_and_set_data_for_VL_6880 skip
14268 10:08:21.995217 arm64_za-ptrace_Set_VL_6896 pass
14269 10:08:21.995374 arm64_za-ptrace_Disabled_ZA_for_VL_6896 skip
14270 10:08:21.995542 arm64_za-ptrace_Get_and_set_data_for_VL_6896 skip
14271 10:08:21.995748 arm64_za-ptrace_Set_VL_6912 pass
14272 10:08:21.995956 arm64_za-ptrace_Disabled_ZA_for_VL_6912 skip
14273 10:08:21.996134 arm64_za-ptrace_Get_and_set_data_for_VL_6912 skip
14274 10:08:21.996335 arm64_za-ptrace_Set_VL_6928 pass
14275 10:08:21.996524 arm64_za-ptrace_Disabled_ZA_for_VL_6928 skip
14276 10:08:21.996710 arm64_za-ptrace_Get_and_set_data_for_VL_6928 skip
14277 10:08:21.996890 arm64_za-ptrace_Set_VL_6944 pass
14278 10:08:21.997059 arm64_za-ptrace_Disabled_ZA_for_VL_6944 skip
14279 10:08:21.997245 arm64_za-ptrace_Get_and_set_data_for_VL_6944 skip
14280 10:08:21.997377 arm64_za-ptrace_Set_VL_6960 pass
14281 10:08:21.997517 arm64_za-ptrace_Disabled_ZA_for_VL_6960 skip
14282 10:08:21.997666 arm64_za-ptrace_Get_and_set_data_for_VL_6960 skip
14283 10:08:21.997806 arm64_za-ptrace_Set_VL_6976 pass
14284 10:08:21.997945 arm64_za-ptrace_Disabled_ZA_for_VL_6976 skip
14285 10:08:21.998084 arm64_za-ptrace_Get_and_set_data_for_VL_6976 skip
14286 10:08:21.998221 arm64_za-ptrace_Set_VL_6992 pass
14287 10:08:21.998359 arm64_za-ptrace_Disabled_ZA_for_VL_6992 skip
14288 10:08:21.998497 arm64_za-ptrace_Get_and_set_data_for_VL_6992 skip
14289 10:08:21.998635 arm64_za-ptrace_Set_VL_7008 pass
14290 10:08:21.998773 arm64_za-ptrace_Disabled_ZA_for_VL_7008 skip
14291 10:08:21.998911 arm64_za-ptrace_Get_and_set_data_for_VL_7008 skip
14292 10:08:21.999048 arm64_za-ptrace_Set_VL_7024 pass
14293 10:08:21.999186 arm64_za-ptrace_Disabled_ZA_for_VL_7024 skip
14294 10:08:21.999323 arm64_za-ptrace_Get_and_set_data_for_VL_7024 skip
14295 10:08:21.999461 arm64_za-ptrace_Set_VL_7040 pass
14296 10:08:21.999598 arm64_za-ptrace_Disabled_ZA_for_VL_7040 skip
14297 10:08:21.999736 arm64_za-ptrace_Get_and_set_data_for_VL_7040 skip
14298 10:08:21.999873 arm64_za-ptrace_Set_VL_7056 pass
14299 10:08:22.001249 arm64_za-ptrace_Disabled_ZA_for_VL_7056 skip
14300 10:08:22.001590 arm64_za-ptrace_Get_and_set_data_for_VL_7056 skip
14301 10:08:22.001814 arm64_za-ptrace_Set_VL_7072 pass
14302 10:08:22.002056 arm64_za-ptrace_Disabled_ZA_for_VL_7072 skip
14303 10:08:22.002234 arm64_za-ptrace_Get_and_set_data_for_VL_7072 skip
14304 10:08:22.002396 arm64_za-ptrace_Set_VL_7088 pass
14305 10:08:22.002554 arm64_za-ptrace_Disabled_ZA_for_VL_7088 skip
14306 10:08:22.002704 arm64_za-ptrace_Get_and_set_data_for_VL_7088 skip
14307 10:08:22.002852 arm64_za-ptrace_Set_VL_7104 pass
14308 10:08:22.003026 arm64_za-ptrace_Disabled_ZA_for_VL_7104 skip
14309 10:08:22.003136 arm64_za-ptrace_Get_and_set_data_for_VL_7104 skip
14310 10:08:22.003242 arm64_za-ptrace_Set_VL_7120 pass
14311 10:08:22.003339 arm64_za-ptrace_Disabled_ZA_for_VL_7120 skip
14312 10:08:22.003440 arm64_za-ptrace_Get_and_set_data_for_VL_7120 skip
14313 10:08:22.003546 arm64_za-ptrace_Set_VL_7136 pass
14314 10:08:22.003661 arm64_za-ptrace_Disabled_ZA_for_VL_7136 skip
14315 10:08:22.003784 arm64_za-ptrace_Get_and_set_data_for_VL_7136 skip
14316 10:08:22.003936 arm64_za-ptrace_Set_VL_7152 pass
14317 10:08:22.004084 arm64_za-ptrace_Disabled_ZA_for_VL_7152 skip
14318 10:08:22.004228 arm64_za-ptrace_Get_and_set_data_for_VL_7152 skip
14319 10:08:22.004343 arm64_za-ptrace_Set_VL_7168 pass
14320 10:08:22.004468 arm64_za-ptrace_Disabled_ZA_for_VL_7168 skip
14321 10:08:22.004589 arm64_za-ptrace_Get_and_set_data_for_VL_7168 skip
14322 10:08:22.004734 arm64_za-ptrace_Set_VL_7184 pass
14323 10:08:22.004895 arm64_za-ptrace_Disabled_ZA_for_VL_7184 skip
14324 10:08:22.005015 arm64_za-ptrace_Get_and_set_data_for_VL_7184 skip
14325 10:08:22.005108 arm64_za-ptrace_Set_VL_7200 pass
14326 10:08:22.005193 arm64_za-ptrace_Disabled_ZA_for_VL_7200 skip
14327 10:08:22.005300 arm64_za-ptrace_Get_and_set_data_for_VL_7200 skip
14328 10:08:22.005390 arm64_za-ptrace_Set_VL_7216 pass
14329 10:08:22.005476 arm64_za-ptrace_Disabled_ZA_for_VL_7216 skip
14330 10:08:22.005562 arm64_za-ptrace_Get_and_set_data_for_VL_7216 skip
14331 10:08:22.005671 arm64_za-ptrace_Set_VL_7232 pass
14332 10:08:22.005813 arm64_za-ptrace_Disabled_ZA_for_VL_7232 skip
14333 10:08:22.005912 arm64_za-ptrace_Get_and_set_data_for_VL_7232 skip
14334 10:08:22.006013 arm64_za-ptrace_Set_VL_7248 pass
14335 10:08:22.006091 arm64_za-ptrace_Disabled_ZA_for_VL_7248 skip
14336 10:08:22.009162 arm64_za-ptrace_Get_and_set_data_for_VL_7248 skip
14337 10:08:22.009462 arm64_za-ptrace_Set_VL_7264 pass
14338 10:08:22.009557 arm64_za-ptrace_Disabled_ZA_for_VL_7264 skip
14339 10:08:22.009632 arm64_za-ptrace_Get_and_set_data_for_VL_7264 skip
14340 10:08:22.009729 arm64_za-ptrace_Set_VL_7280 pass
14341 10:08:22.009822 arm64_za-ptrace_Disabled_ZA_for_VL_7280 skip
14342 10:08:22.009920 arm64_za-ptrace_Get_and_set_data_for_VL_7280 skip
14343 10:08:22.009995 arm64_za-ptrace_Set_VL_7296 pass
14344 10:08:22.010082 arm64_za-ptrace_Disabled_ZA_for_VL_7296 skip
14345 10:08:22.010180 arm64_za-ptrace_Get_and_set_data_for_VL_7296 skip
14346 10:08:22.010275 arm64_za-ptrace_Set_VL_7312 pass
14347 10:08:22.010366 arm64_za-ptrace_Disabled_ZA_for_VL_7312 skip
14348 10:08:22.010663 arm64_za-ptrace_Get_and_set_data_for_VL_7312 skip
14349 10:08:22.010745 arm64_za-ptrace_Set_VL_7328 pass
14350 10:08:22.010860 arm64_za-ptrace_Disabled_ZA_for_VL_7328 skip
14351 10:08:22.010955 arm64_za-ptrace_Get_and_set_data_for_VL_7328 skip
14352 10:08:22.011067 arm64_za-ptrace_Set_VL_7344 pass
14353 10:08:22.011342 arm64_za-ptrace_Disabled_ZA_for_VL_7344 skip
14354 10:08:22.011425 arm64_za-ptrace_Get_and_set_data_for_VL_7344 skip
14355 10:08:22.011528 arm64_za-ptrace_Set_VL_7360 pass
14356 10:08:22.011633 arm64_za-ptrace_Disabled_ZA_for_VL_7360 skip
14357 10:08:22.011707 arm64_za-ptrace_Get_and_set_data_for_VL_7360 skip
14358 10:08:22.011791 arm64_za-ptrace_Set_VL_7376 pass
14359 10:08:22.011880 arm64_za-ptrace_Disabled_ZA_for_VL_7376 skip
14360 10:08:22.011993 arm64_za-ptrace_Get_and_set_data_for_VL_7376 skip
14361 10:08:22.012089 arm64_za-ptrace_Set_VL_7392 pass
14362 10:08:22.012198 arm64_za-ptrace_Disabled_ZA_for_VL_7392 skip
14363 10:08:22.012297 arm64_za-ptrace_Get_and_set_data_for_VL_7392 skip
14364 10:08:22.012418 arm64_za-ptrace_Set_VL_7408 pass
14365 10:08:22.012510 arm64_za-ptrace_Disabled_ZA_for_VL_7408 skip
14366 10:08:22.012625 arm64_za-ptrace_Get_and_set_data_for_VL_7408 skip
14367 10:08:22.012749 arm64_za-ptrace_Set_VL_7424 pass
14368 10:08:22.012841 arm64_za-ptrace_Disabled_ZA_for_VL_7424 skip
14369 10:08:22.012959 arm64_za-ptrace_Get_and_set_data_for_VL_7424 skip
14370 10:08:22.013052 arm64_za-ptrace_Set_VL_7440 pass
14371 10:08:22.013136 arm64_za-ptrace_Disabled_ZA_for_VL_7440 skip
14372 10:08:22.017153 arm64_za-ptrace_Get_and_set_data_for_VL_7440 skip
14373 10:08:22.017456 arm64_za-ptrace_Set_VL_7456 pass
14374 10:08:22.017557 arm64_za-ptrace_Disabled_ZA_for_VL_7456 skip
14375 10:08:22.017670 arm64_za-ptrace_Get_and_set_data_for_VL_7456 skip
14376 10:08:22.017757 arm64_za-ptrace_Set_VL_7472 pass
14377 10:08:22.017841 arm64_za-ptrace_Disabled_ZA_for_VL_7472 skip
14378 10:08:22.017939 arm64_za-ptrace_Get_and_set_data_for_VL_7472 skip
14379 10:08:22.018023 arm64_za-ptrace_Set_VL_7488 pass
14380 10:08:22.018303 arm64_za-ptrace_Disabled_ZA_for_VL_7488 skip
14381 10:08:22.018394 arm64_za-ptrace_Get_and_set_data_for_VL_7488 skip
14382 10:08:22.018494 arm64_za-ptrace_Set_VL_7504 pass
14383 10:08:22.018580 arm64_za-ptrace_Disabled_ZA_for_VL_7504 skip
14384 10:08:22.018664 arm64_za-ptrace_Get_and_set_data_for_VL_7504 skip
14385 10:08:22.018763 arm64_za-ptrace_Set_VL_7520 pass
14386 10:08:22.018848 arm64_za-ptrace_Disabled_ZA_for_VL_7520 skip
14387 10:08:22.018947 arm64_za-ptrace_Get_and_set_data_for_VL_7520 skip
14388 10:08:22.019032 arm64_za-ptrace_Set_VL_7536 pass
14389 10:08:22.019135 arm64_za-ptrace_Disabled_ZA_for_VL_7536 skip
14390 10:08:22.019235 arm64_za-ptrace_Get_and_set_data_for_VL_7536 skip
14391 10:08:22.019321 arm64_za-ptrace_Set_VL_7552 pass
14392 10:08:22.019569 arm64_za-ptrace_Disabled_ZA_for_VL_7552 skip
14393 10:08:22.019661 arm64_za-ptrace_Get_and_set_data_for_VL_7552 skip
14394 10:08:22.019751 arm64_za-ptrace_Set_VL_7568 pass
14395 10:08:22.019837 arm64_za-ptrace_Disabled_ZA_for_VL_7568 skip
14396 10:08:22.019928 arm64_za-ptrace_Get_and_set_data_for_VL_7568 skip
14397 10:08:22.020019 arm64_za-ptrace_Set_VL_7584 pass
14398 10:08:22.020112 arm64_za-ptrace_Disabled_ZA_for_VL_7584 skip
14399 10:08:22.020208 arm64_za-ptrace_Get_and_set_data_for_VL_7584 skip
14400 10:08:22.020292 arm64_za-ptrace_Set_VL_7600 pass
14401 10:08:22.020610 arm64_za-ptrace_Disabled_ZA_for_VL_7600 skip
14402 10:08:22.020722 arm64_za-ptrace_Get_and_set_data_for_VL_7600 skip
14403 10:08:22.020804 arm64_za-ptrace_Set_VL_7616 pass
14404 10:08:22.020902 arm64_za-ptrace_Disabled_ZA_for_VL_7616 skip
14405 10:08:22.020989 arm64_za-ptrace_Get_and_set_data_for_VL_7616 skip
14406 10:08:22.025180 arm64_za-ptrace_Set_VL_7632 pass
14407 10:08:22.025479 arm64_za-ptrace_Disabled_ZA_for_VL_7632 skip
14408 10:08:22.025573 arm64_za-ptrace_Get_and_set_data_for_VL_7632 skip
14409 10:08:22.025688 arm64_za-ptrace_Set_VL_7648 pass
14410 10:08:22.025791 arm64_za-ptrace_Disabled_ZA_for_VL_7648 skip
14411 10:08:22.025895 arm64_za-ptrace_Get_and_set_data_for_VL_7648 skip
14412 10:08:22.026011 arm64_za-ptrace_Set_VL_7664 pass
14413 10:08:22.026108 arm64_za-ptrace_Disabled_ZA_for_VL_7664 skip
14414 10:08:22.026203 arm64_za-ptrace_Get_and_set_data_for_VL_7664 skip
14415 10:08:22.026313 arm64_za-ptrace_Set_VL_7680 pass
14416 10:08:22.026410 arm64_za-ptrace_Disabled_ZA_for_VL_7680 skip
14417 10:08:22.026518 arm64_za-ptrace_Get_and_set_data_for_VL_7680 skip
14418 10:08:22.026594 arm64_za-ptrace_Set_VL_7696 pass
14419 10:08:22.026667 arm64_za-ptrace_Disabled_ZA_for_VL_7696 skip
14420 10:08:22.047858 arm64_za-ptrace_Get_and_set_data_for_VL_7696 skip
14421 10:08:22.048384 arm64_za-ptrace_Set_VL_7712 pass
14422 10:08:22.048471 arm64_za-ptrace_Disabled_ZA_for_VL_7712 skip
14423 10:08:22.048563 arm64_za-ptrace_Get_and_set_data_for_VL_7712 skip
14424 10:08:22.048643 arm64_za-ptrace_Set_VL_7728 pass
14425 10:08:22.048725 arm64_za-ptrace_Disabled_ZA_for_VL_7728 skip
14426 10:08:22.048841 arm64_za-ptrace_Get_and_set_data_for_VL_7728 skip
14427 10:08:22.048925 arm64_za-ptrace_Set_VL_7744 pass
14428 10:08:22.049002 arm64_za-ptrace_Disabled_ZA_for_VL_7744 skip
14429 10:08:22.049077 arm64_za-ptrace_Get_and_set_data_for_VL_7744 skip
14430 10:08:22.049156 arm64_za-ptrace_Set_VL_7760 pass
14431 10:08:22.049247 arm64_za-ptrace_Disabled_ZA_for_VL_7760 skip
14432 10:08:22.049333 arm64_za-ptrace_Get_and_set_data_for_VL_7760 skip
14433 10:08:22.049404 arm64_za-ptrace_Set_VL_7776 pass
14434 10:08:22.049734 arm64_za-ptrace_Disabled_ZA_for_VL_7776 skip
14435 10:08:22.049881 arm64_za-ptrace_Get_and_set_data_for_VL_7776 skip
14436 10:08:22.050264 arm64_za-ptrace_Set_VL_7792 pass
14437 10:08:22.050454 arm64_za-ptrace_Disabled_ZA_for_VL_7792 skip
14438 10:08:22.050587 arm64_za-ptrace_Get_and_set_data_for_VL_7792 skip
14439 10:08:22.050685 arm64_za-ptrace_Set_VL_7808 pass
14440 10:08:22.050791 arm64_za-ptrace_Disabled_ZA_for_VL_7808 skip
14441 10:08:22.050927 arm64_za-ptrace_Get_and_set_data_for_VL_7808 skip
14442 10:08:22.051047 arm64_za-ptrace_Set_VL_7824 pass
14443 10:08:22.051161 arm64_za-ptrace_Disabled_ZA_for_VL_7824 skip
14444 10:08:22.051308 arm64_za-ptrace_Get_and_set_data_for_VL_7824 skip
14445 10:08:22.051424 arm64_za-ptrace_Set_VL_7840 pass
14446 10:08:22.051511 arm64_za-ptrace_Disabled_ZA_for_VL_7840 skip
14447 10:08:22.051628 arm64_za-ptrace_Get_and_set_data_for_VL_7840 skip
14448 10:08:22.051765 arm64_za-ptrace_Set_VL_7856 pass
14449 10:08:22.051868 arm64_za-ptrace_Disabled_ZA_for_VL_7856 skip
14450 10:08:22.051958 arm64_za-ptrace_Get_and_set_data_for_VL_7856 skip
14451 10:08:22.052043 arm64_za-ptrace_Set_VL_7872 pass
14452 10:08:22.052127 arm64_za-ptrace_Disabled_ZA_for_VL_7872 skip
14453 10:08:22.052188 arm64_za-ptrace_Get_and_set_data_for_VL_7872 skip
14454 10:08:22.052245 arm64_za-ptrace_Set_VL_7888 pass
14455 10:08:22.052303 arm64_za-ptrace_Disabled_ZA_for_VL_7888 skip
14456 10:08:22.052377 arm64_za-ptrace_Get_and_set_data_for_VL_7888 skip
14457 10:08:22.052469 arm64_za-ptrace_Set_VL_7904 pass
14458 10:08:22.052556 arm64_za-ptrace_Disabled_ZA_for_VL_7904 skip
14459 10:08:22.052639 arm64_za-ptrace_Get_and_set_data_for_VL_7904 skip
14460 10:08:22.052711 arm64_za-ptrace_Set_VL_7920 pass
14461 10:08:22.052791 arm64_za-ptrace_Disabled_ZA_for_VL_7920 skip
14462 10:08:22.052861 arm64_za-ptrace_Get_and_set_data_for_VL_7920 skip
14463 10:08:22.052924 arm64_za-ptrace_Set_VL_7936 pass
14464 10:08:22.052990 arm64_za-ptrace_Disabled_ZA_for_VL_7936 skip
14465 10:08:22.053048 arm64_za-ptrace_Get_and_set_data_for_VL_7936 skip
14466 10:08:22.053118 arm64_za-ptrace_Set_VL_7952 pass
14467 10:08:22.053182 arm64_za-ptrace_Disabled_ZA_for_VL_7952 skip
14468 10:08:22.053240 arm64_za-ptrace_Get_and_set_data_for_VL_7952 skip
14469 10:08:22.057320 arm64_za-ptrace_Set_VL_7968 pass
14470 10:08:22.057404 arm64_za-ptrace_Disabled_ZA_for_VL_7968 skip
14471 10:08:22.057490 arm64_za-ptrace_Get_and_set_data_for_VL_7968 skip
14472 10:08:22.057598 arm64_za-ptrace_Set_VL_7984 pass
14473 10:08:22.057704 arm64_za-ptrace_Disabled_ZA_for_VL_7984 skip
14474 10:08:22.057812 arm64_za-ptrace_Get_and_set_data_for_VL_7984 skip
14475 10:08:22.057891 arm64_za-ptrace_Set_VL_8000 pass
14476 10:08:22.057978 arm64_za-ptrace_Disabled_ZA_for_VL_8000 skip
14477 10:08:22.058060 arm64_za-ptrace_Get_and_set_data_for_VL_8000 skip
14478 10:08:22.058151 arm64_za-ptrace_Set_VL_8016 pass
14479 10:08:22.058279 arm64_za-ptrace_Disabled_ZA_for_VL_8016 skip
14480 10:08:22.058597 arm64_za-ptrace_Get_and_set_data_for_VL_8016 skip
14481 10:08:22.058773 arm64_za-ptrace_Set_VL_8032 pass
14482 10:08:22.058939 arm64_za-ptrace_Disabled_ZA_for_VL_8032 skip
14483 10:08:22.059094 arm64_za-ptrace_Get_and_set_data_for_VL_8032 skip
14484 10:08:22.059250 arm64_za-ptrace_Set_VL_8048 pass
14485 10:08:22.059417 arm64_za-ptrace_Disabled_ZA_for_VL_8048 skip
14486 10:08:22.059549 arm64_za-ptrace_Get_and_set_data_for_VL_8048 skip
14487 10:08:22.059697 arm64_za-ptrace_Set_VL_8064 pass
14488 10:08:22.059851 arm64_za-ptrace_Disabled_ZA_for_VL_8064 skip
14489 10:08:22.060008 arm64_za-ptrace_Get_and_set_data_for_VL_8064 skip
14490 10:08:22.060162 arm64_za-ptrace_Set_VL_8080 pass
14491 10:08:22.060282 arm64_za-ptrace_Disabled_ZA_for_VL_8080 skip
14492 10:08:22.060451 arm64_za-ptrace_Get_and_set_data_for_VL_8080 skip
14493 10:08:22.060610 arm64_za-ptrace_Set_VL_8096 pass
14494 10:08:22.060765 arm64_za-ptrace_Disabled_ZA_for_VL_8096 skip
14495 10:08:22.060910 arm64_za-ptrace_Get_and_set_data_for_VL_8096 skip
14496 10:08:22.061035 arm64_za-ptrace_Set_VL_8112 pass
14497 10:08:22.061153 arm64_za-ptrace_Disabled_ZA_for_VL_8112 skip
14498 10:08:22.061267 arm64_za-ptrace_Get_and_set_data_for_VL_8112 skip
14499 10:08:22.061381 arm64_za-ptrace_Set_VL_8128 pass
14500 10:08:22.061496 arm64_za-ptrace_Disabled_ZA_for_VL_8128 skip
14501 10:08:22.061610 arm64_za-ptrace_Get_and_set_data_for_VL_8128 skip
14502 10:08:22.061769 arm64_za-ptrace_Set_VL_8144 pass
14503 10:08:22.061891 arm64_za-ptrace_Disabled_ZA_for_VL_8144 skip
14504 10:08:22.062007 arm64_za-ptrace_Get_and_set_data_for_VL_8144 skip
14505 10:08:22.062124 arm64_za-ptrace_Set_VL_8160 pass
14506 10:08:22.062241 arm64_za-ptrace_Disabled_ZA_for_VL_8160 skip
14507 10:08:22.062354 arm64_za-ptrace_Get_and_set_data_for_VL_8160 skip
14508 10:08:22.065168 arm64_za-ptrace_Set_VL_8176 pass
14509 10:08:22.065549 arm64_za-ptrace_Disabled_ZA_for_VL_8176 skip
14510 10:08:22.065730 arm64_za-ptrace_Get_and_set_data_for_VL_8176 skip
14511 10:08:22.065874 arm64_za-ptrace_Set_VL_8192 pass
14512 10:08:22.066054 arm64_za-ptrace_Disabled_ZA_for_VL_8192 skip
14513 10:08:22.066222 arm64_za-ptrace_Get_and_set_data_for_VL_8192 skip
14514 10:08:22.066365 arm64_za-ptrace pass
14515 10:08:22.066517 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory pass
14516 10:08:22.066714 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory pass
14517 10:08:22.066868 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory pass
14518 10:08:22.067052 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory pass
14519 10:08:22.067218 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory fail
14520 10:08:22.067399 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory fail
14521 10:08:22.067543 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14522 10:08:22.067730 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory pass
14523 10:08:22.067900 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory pass
14524 10:08:22.068086 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14525 10:08:22.068249 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory fail
14526 10:08:22.068424 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory fail
14527 10:08:22.068577 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory pass
14528 10:08:22.068723 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory fail
14529 10:08:22.069108 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory fail
14530 10:08:22.073143 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory pass
14531 10:08:22.073510 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory pass
14532 10:08:22.073750 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14533 10:08:22.073953 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory pass
14534 10:08:22.074147 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14535 10:08:22.074307 arm64_check_buffer_fill fail
14536 10:08:22.074486 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14537 10:08:22.074669 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14538 10:08:22.075089 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14539 10:08:22.075315 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14540 10:08:22.075511 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14541 10:08:22.075705 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14542 10:08:22.075891 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14543 10:08:22.076314 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14544 10:08:22.076522 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14545 10:08:22.076701 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14546 10:08:22.076884 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14547 10:08:22.081188 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14548 10:08:22.081616 arm64_check_child_memory fail
14549 10:08:22.081808 arm64_check_gcr_el1_cswitch fail
14550 10:08:22.081979 arm64_check_ksm_options fail
14551 10:08:22.082176 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off pass
14552 10:08:22.082347 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14553 10:08:22.082544 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off pass
14554 10:08:22.082742 arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14555 10:08:22.082941 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14556 10:08:22.088181 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14557 10:08:22.088510 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14558 10:08:22.088652 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14559 10:08:22.088959 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14560 10:08:22.089272 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14561 10:08:22.089603 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14562 10:08:22.089906 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14563 10:08:22.090267 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14564 10:08:22.090447 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14565 10:08:22.090582 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14566 10:08:22.090734 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14567 10:08:22.090872 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14568 10:08:22.091021 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14569 10:08:22.091152 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14570 10:08:22.091307 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14571 10:08:22.091717 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory fail
14572 10:08:22.091940 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory fail
14573 10:08:22.092108 arm64_check_mmap_options fail
14574 10:08:22.092285 arm64_check_prctl_check_basic_read pass
14575 10:08:22.092410 arm64_check_prctl_NONE pass
14576 10:08:22.092528 arm64_check_prctl_SYNC pass
14577 10:08:22.092640 arm64_check_prctl_ASYNC pass
14578 10:08:22.092730 arm64_check_prctl_SYNC_ASYNC pass
14579 10:08:22.092815 arm64_check_prctl pass
14580 10:08:22.092899 arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode fail
14581 10:08:22.093008 arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode fail
14582 10:08:22.093126 arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode pass
14583 10:08:22.093217 arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode fail
14584 10:08:22.093302 arm64_check_tags_inclusion fail
14585 10:08:22.093405 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14586 10:08:22.097232 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14587 10:08:22.097339 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14588 10:08:22.097621 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14589 10:08:22.097746 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14590 10:08:22.097868 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14591 10:08:22.098170 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14592 10:08:22.098408 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14593 10:08:22.098612 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14594 10:08:22.098785 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14595 10:08:22.098976 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14596 10:08:22.099167 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14597 10:08:22.099329 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14598 10:08:22.099519 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14599 10:08:22.099713 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14600 10:08:22.099906 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14601 10:08:22.100102 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14602 10:08:22.100299 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14603 10:08:22.100467 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14604 10:08:22.100661 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14605 10:08:22.100831 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14606 10:08:22.101022 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14607 10:08:22.101191 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14608 10:08:22.105150 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14609 10:08:22.105452 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14610 10:08:22.105563 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14611 10:08:22.105854 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14612 10:08:22.105964 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14613 10:08:22.106242 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14614 10:08:22.106357 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14615 10:08:22.106492 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14616 10:08:22.106618 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14617 10:08:22.106924 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14618 10:08:22.107028 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14619 10:08:22.107168 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14620 10:08:22.107540 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14621 10:08:22.107662 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14622 10:08:22.107950 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14623 10:08:22.108062 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14624 10:08:22.108160 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14625 10:08:22.108427 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14626 10:08:22.108525 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14627 10:08:22.108929 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14628 10:08:22.109026 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14629 10:08:22.113220 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14630 10:08:22.113609 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14631 10:08:22.113868 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14632 10:08:22.114018 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14633 10:08:22.114114 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14634 10:08:22.114223 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14635 10:08:22.114320 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14636 10:08:22.114440 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14637 10:08:22.114570 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14638 10:08:22.114702 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14639 10:08:22.117729 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14640 10:08:22.117883 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14641 10:08:22.118004 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14642 10:08:22.118122 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14643 10:08:22.118238 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14644 10:08:22.118354 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14645 10:08:22.118470 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14646 10:08:22.118585 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14647 10:08:22.133057 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14648 10:08:22.133884 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14649 10:08:22.133992 arm64_check_user_mem pass
14650 10:08:22.134084 arm64_btitest_nohint_func_call_using_br_x0 pass
14651 10:08:22.134171 arm64_btitest_nohint_func_call_using_br_x16 pass
14652 10:08:22.134257 arm64_btitest_nohint_func_call_using_blr pass
14653 10:08:22.134343 arm64_btitest_bti_none_func_call_using_br_x0 pass
14654 10:08:22.134428 arm64_btitest_bti_none_func_call_using_br_x16 pass
14655 10:08:22.134713 arm64_btitest_bti_none_func_call_using_blr pass
14656 10:08:22.134811 arm64_btitest_bti_c_func_call_using_br_x0 pass
14657 10:08:22.134892 arm64_btitest_bti_c_func_call_using_br_x16 pass
14658 10:08:22.134969 arm64_btitest_bti_c_func_call_using_blr pass
14659 10:08:22.135047 arm64_btitest_bti_j_func_call_using_br_x0 pass
14660 10:08:22.135123 arm64_btitest_bti_j_func_call_using_br_x16 pass
14661 10:08:22.135198 arm64_btitest_bti_j_func_call_using_blr pass
14662 10:08:22.135288 arm64_btitest_bti_jc_func_call_using_br_x0 pass
14663 10:08:22.135366 arm64_btitest_bti_jc_func_call_using_br_x16 pass
14664 10:08:22.135450 arm64_btitest_bti_jc_func_call_using_blr pass
14665 10:08:22.135526 arm64_btitest_paciasp_func_call_using_br_x0 pass
14666 10:08:22.135616 arm64_btitest_paciasp_func_call_using_br_x16 pass
14667 10:08:22.135694 arm64_btitest_paciasp_func_call_using_blr pass
14668 10:08:22.135771 arm64_btitest pass
14669 10:08:22.135846 arm64_nobtitest_nohint_func_call_using_br_x0 pass
14670 10:08:22.135936 arm64_nobtitest_nohint_func_call_using_br_x16 pass
14671 10:08:22.136015 arm64_nobtitest_nohint_func_call_using_blr pass
14672 10:08:22.136104 arm64_nobtitest_bti_none_func_call_using_br_x0 pass
14673 10:08:22.136182 arm64_nobtitest_bti_none_func_call_using_br_x16 pass
14674 10:08:22.136271 arm64_nobtitest_bti_none_func_call_using_blr pass
14675 10:08:22.136368 arm64_nobtitest_bti_c_func_call_using_br_x0 pass
14676 10:08:22.136458 arm64_nobtitest_bti_c_func_call_using_br_x16 pass
14677 10:08:22.136744 arm64_nobtitest_bti_c_func_call_using_blr pass
14678 10:08:22.136839 arm64_nobtitest_bti_j_func_call_using_br_x0 pass
14679 10:08:22.136940 arm64_nobtitest_bti_j_func_call_using_br_x16 pass
14680 10:08:22.137018 arm64_nobtitest_bti_j_func_call_using_blr pass
14681 10:08:22.141169 arm64_nobtitest_bti_jc_func_call_using_br_x0 pass
14682 10:08:22.141516 arm64_nobtitest_bti_jc_func_call_using_br_x16 pass
14683 10:08:22.141613 arm64_nobtitest_bti_jc_func_call_using_blr pass
14684 10:08:22.141700 arm64_nobtitest_paciasp_func_call_using_br_x0 pass
14685 10:08:22.141777 arm64_nobtitest_paciasp_func_call_using_br_x16 pass
14686 10:08:22.141867 arm64_nobtitest_paciasp_func_call_using_blr pass
14687 10:08:22.141949 arm64_nobtitest pass
14688 10:08:22.142023 arm64_hwcap_cpuinfo_match_RNG pass
14689 10:08:22.142098 arm64_hwcap_sigill_RNG pass
14690 10:08:22.142188 arm64_hwcap_cpuinfo_match_SME pass
14691 10:08:22.142265 arm64_hwcap_sigill_SME pass
14692 10:08:22.142342 arm64_hwcap_cpuinfo_match_SVE pass
14693 10:08:22.142417 arm64_hwcap_sigill_SVE pass
14694 10:08:22.142505 arm64_hwcap_cpuinfo_match_SVE_2 pass
14695 10:08:22.142584 arm64_hwcap_sigill_SVE_2 pass
14696 10:08:22.142658 arm64_hwcap_cpuinfo_match_SVE_AES pass
14697 10:08:22.142732 arm64_hwcap_sigill_SVE_AES pass
14698 10:08:22.142821 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
14699 10:08:22.142897 arm64_hwcap_sigill_SVE2_PMULL pass
14700 10:08:22.142971 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
14701 10:08:22.143046 arm64_hwcap_sigill_SVE2_BITPERM pass
14702 10:08:22.143134 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
14703 10:08:22.143210 arm64_hwcap_sigill_SVE2_SHA3 pass
14704 10:08:22.143285 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
14705 10:08:22.143372 arm64_hwcap_sigill_SVE2_SM4 pass
14706 10:08:22.143468 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
14707 10:08:22.143545 arm64_hwcap_sigill_SVE2_I8MM pass
14708 10:08:22.143633 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
14709 10:08:22.143710 arm64_hwcap_sigill_SVE2_F32MM pass
14710 10:08:22.143798 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
14711 10:08:22.143875 arm64_hwcap_sigill_SVE2_F64MM pass
14712 10:08:22.143950 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
14713 10:08:22.144038 arm64_hwcap_sigill_SVE2_BF16 pass
14714 10:08:22.144114 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
14715 10:08:22.144189 arm64_hwcap_sigill_SVE2_EBF16 skip
14716 10:08:22.144277 arm64_hwcap pass
14717 10:08:22.144354 arm64_ptrace_read_tpidr_one pass
14718 10:08:22.144428 arm64_ptrace_write_tpidr_one pass
14719 10:08:22.144502 arm64_ptrace_verify_tpidr_one pass
14720 10:08:22.144590 arm64_ptrace_count_tpidrs pass
14721 10:08:22.144667 arm64_ptrace_tpidr2_write pass
14722 10:08:22.144741 arm64_ptrace_tpidr2_read pass
14723 10:08:22.144815 arm64_ptrace_write_tpidr_only pass
14724 10:08:22.144904 arm64_ptrace pass
14725 10:08:22.144980 arm64_syscall-abi_getpid_FPSIMD pass
14726 10:08:22.145055 arm64_syscall-abi_getpid_SVE_VL_256 pass
14727 10:08:22.145129 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA pass
14728 10:08:22.149143 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM pass
14729 10:08:22.149475 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA pass
14730 10:08:22.149618 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA pass
14731 10:08:22.149752 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM pass
14732 10:08:22.149898 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA pass
14733 10:08:22.150026 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA pass
14734 10:08:22.150146 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM pass
14735 10:08:22.150264 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA pass
14736 10:08:22.150416 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA pass
14737 10:08:22.150538 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM pass
14738 10:08:22.150651 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA pass
14739 10:08:22.150868 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA pass
14740 10:08:22.150992 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM pass
14741 10:08:22.151105 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA pass
14742 10:08:22.151219 arm64_syscall-abi_getpid_SVE_VL_240 pass
14743 10:08:22.151331 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA pass
14744 10:08:22.151470 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM pass
14745 10:08:22.151586 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA pass
14746 10:08:22.151698 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA pass
14747 10:08:22.151809 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM pass
14748 10:08:22.151920 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA pass
14749 10:08:22.152032 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA pass
14750 10:08:22.152143 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM pass
14751 10:08:22.152282 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA pass
14752 10:08:22.152400 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA pass
14753 10:08:22.152517 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM pass
14754 10:08:22.152634 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA pass
14755 10:08:22.152797 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA pass
14756 10:08:22.152946 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM pass
14757 10:08:22.153099 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA pass
14758 10:08:22.153210 arm64_syscall-abi_getpid_SVE_VL_224 pass
14759 10:08:22.153299 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA pass
14760 10:08:22.153384 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM pass
14761 10:08:22.153489 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA pass
14762 10:08:22.153580 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA pass
14763 10:08:22.153673 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM pass
14764 10:08:22.153955 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA pass
14765 10:08:22.154048 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA pass
14766 10:08:22.157173 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM pass
14767 10:08:22.157307 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA pass
14768 10:08:22.157659 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA pass
14769 10:08:22.157779 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM pass
14770 10:08:22.157900 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA pass
14771 10:08:22.157982 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA pass
14772 10:08:22.158076 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM pass
14773 10:08:22.158156 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA pass
14774 10:08:22.158233 arm64_syscall-abi_getpid_SVE_VL_208 pass
14775 10:08:22.158308 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA pass
14776 10:08:22.158398 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM pass
14777 10:08:22.158476 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA pass
14778 10:08:22.158551 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA pass
14779 10:08:22.158641 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM pass
14780 10:08:22.158718 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA pass
14781 10:08:22.158806 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA pass
14782 10:08:22.158895 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM pass
14783 10:08:22.159282 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA pass
14784 10:08:22.159383 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA pass
14785 10:08:22.159523 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM pass
14786 10:08:22.159606 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA pass
14787 10:08:22.159689 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA pass
14788 10:08:22.159780 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM pass
14789 10:08:22.159851 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA pass
14790 10:08:22.159963 arm64_syscall-abi_getpid_SVE_VL_192 pass
14791 10:08:22.160280 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA pass
14792 10:08:22.160407 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM pass
14793 10:08:22.160503 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA pass
14794 10:08:22.160600 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA pass
14795 10:08:22.160884 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM pass
14796 10:08:22.160983 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA pass
14797 10:08:22.161071 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA pass
14798 10:08:22.161137 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM pass
14799 10:08:22.161211 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA pass
14800 10:08:22.165143 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA pass
14801 10:08:22.165730 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM pass
14802 10:08:22.165836 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA pass
14803 10:08:22.165934 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA pass
14804 10:08:22.166039 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM pass
14805 10:08:22.166145 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA pass
14806 10:08:22.166267 arm64_syscall-abi_getpid_SVE_VL_176 pass
14807 10:08:22.166373 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA pass
14808 10:08:22.166479 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM pass
14809 10:08:22.166581 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA pass
14810 10:08:22.166696 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA pass
14811 10:08:22.166778 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM pass
14812 10:08:22.166841 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA pass
14813 10:08:22.166902 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA pass
14814 10:08:22.166974 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM pass
14815 10:08:22.167035 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA pass
14816 10:08:22.167336 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA pass
14817 10:08:22.177775 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM pass
14818 10:08:22.178074 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA pass
14819 10:08:22.178231 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA pass
14820 10:08:22.178408 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM pass
14821 10:08:22.178586 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA pass
14822 10:08:22.178747 arm64_syscall-abi_getpid_SVE_VL_160 pass
14823 10:08:22.178905 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA pass
14824 10:08:22.179064 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM pass
14825 10:08:22.179262 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA pass
14826 10:08:22.179430 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA pass
14827 10:08:22.179594 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM pass
14828 10:08:22.179767 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA pass
14829 10:08:22.179980 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA pass
14830 10:08:22.180247 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM pass
14831 10:08:22.180433 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA pass
14832 10:08:22.180585 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA pass
14833 10:08:22.180776 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM pass
14834 10:08:22.180989 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA pass
14835 10:08:22.181137 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA pass
14836 10:08:22.181257 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM pass
14837 10:08:22.181369 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA pass
14838 10:08:22.181483 arm64_syscall-abi_getpid_SVE_VL_144 pass
14839 10:08:22.181593 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA pass
14840 10:08:22.181721 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM pass
14841 10:08:22.181836 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA pass
14842 10:08:22.181986 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA pass
14843 10:08:22.182126 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM pass
14844 10:08:22.182244 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA pass
14845 10:08:22.182357 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA pass
14846 10:08:22.182496 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM pass
14847 10:08:22.185157 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA pass
14848 10:08:22.185503 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA pass
14849 10:08:22.185600 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM pass
14850 10:08:22.185685 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA pass
14851 10:08:22.185776 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA pass
14852 10:08:22.185853 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM pass
14853 10:08:22.185942 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA pass
14854 10:08:22.186020 arm64_syscall-abi_getpid_SVE_VL_128 pass
14855 10:08:22.186108 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA pass
14856 10:08:22.186185 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM pass
14857 10:08:22.186273 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA pass
14858 10:08:22.186363 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA pass
14859 10:08:22.186670 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM pass
14860 10:08:22.186769 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA pass
14861 10:08:22.187217 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA pass
14862 10:08:22.187543 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM pass
14863 10:08:22.187626 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA pass
14864 10:08:22.187702 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA pass
14865 10:08:22.187779 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM pass
14866 10:08:22.188113 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA pass
14867 10:08:22.188351 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA pass
14868 10:08:22.188526 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM pass
14869 10:08:22.188686 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA pass
14870 10:08:22.188832 arm64_syscall-abi_getpid_SVE_VL_112 pass
14871 10:08:22.189005 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA pass
14872 10:08:22.189161 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM pass
14873 10:08:22.189281 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA pass
14874 10:08:22.189398 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA pass
14875 10:08:22.189537 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM pass
14876 10:08:22.189665 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA pass
14877 10:08:22.189778 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA pass
14878 10:08:22.189887 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM pass
14879 10:08:22.190002 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA pass
14880 10:08:22.190110 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA pass
14881 10:08:22.190218 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM pass
14882 10:08:22.193186 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA pass
14883 10:08:22.193742 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA pass
14884 10:08:22.193925 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM pass
14885 10:08:22.194083 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA pass
14886 10:08:22.194459 arm64_syscall-abi_getpid_SVE_VL_96 pass
14887 10:08:22.194645 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA pass
14888 10:08:22.194802 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM pass
14889 10:08:22.194962 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA pass
14890 10:08:22.195130 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA pass
14891 10:08:22.195298 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM pass
14892 10:08:22.195468 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA pass
14893 10:08:22.195634 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA pass
14894 10:08:22.196052 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM pass
14895 10:08:22.196156 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA pass
14896 10:08:22.196244 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA pass
14897 10:08:22.196331 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM pass
14898 10:08:22.196418 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA pass
14899 10:08:22.196505 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA pass
14900 10:08:22.196590 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM pass
14901 10:08:22.196674 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA pass
14902 10:08:22.196758 arm64_syscall-abi_getpid_SVE_VL_80 pass
14903 10:08:22.196842 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA pass
14904 10:08:22.196926 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM pass
14905 10:08:22.197010 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA pass
14906 10:08:22.197094 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA pass
14907 10:08:22.197197 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM pass
14908 10:08:22.197283 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA pass
14909 10:08:22.197366 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA pass
14910 10:08:22.197451 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM pass
14911 10:08:22.197534 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA pass
14912 10:08:22.197616 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA pass
14913 10:08:22.197708 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM pass
14914 10:08:22.197792 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA pass
14915 10:08:22.201204 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA pass
14916 10:08:22.201513 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM pass
14917 10:08:22.201612 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA pass
14918 10:08:22.201706 arm64_syscall-abi_getpid_SVE_VL_64 pass
14919 10:08:22.201805 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA pass
14920 10:08:22.201889 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM pass
14921 10:08:22.201997 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA pass
14922 10:08:22.202084 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA pass
14923 10:08:22.202380 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM pass
14924 10:08:22.202485 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA pass
14925 10:08:22.202571 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA pass
14926 10:08:22.202671 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM pass
14927 10:08:22.202757 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA pass
14928 10:08:22.202855 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA pass
14929 10:08:22.202942 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM pass
14930 10:08:22.203041 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA pass
14931 10:08:22.203142 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA pass
14932 10:08:22.203444 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM pass
14933 10:08:22.203551 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA pass
14934 10:08:22.203636 arm64_syscall-abi_getpid_SVE_VL_48 pass
14935 10:08:22.203733 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA pass
14936 10:08:22.204015 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM pass
14937 10:08:22.204113 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA pass
14938 10:08:22.204193 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA pass
14939 10:08:22.204271 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM pass
14940 10:08:22.204365 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA pass
14941 10:08:22.204446 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA pass
14942 10:08:22.204528 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM pass
14943 10:08:22.204622 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA pass
14944 10:08:22.204703 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA pass
14945 10:08:22.204799 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM pass
14946 10:08:22.204883 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA pass
14947 10:08:22.204983 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA pass
14948 10:08:22.205071 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM pass
14949 10:08:22.209501 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA pass
14950 10:08:22.209675 arm64_syscall-abi_getpid_SVE_VL_32 pass
14951 10:08:22.209781 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA pass
14952 10:08:22.209868 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM pass
14953 10:08:22.209964 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA pass
14954 10:08:22.210050 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA pass
14955 10:08:22.210149 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM pass
14956 10:08:22.210249 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA pass
14957 10:08:22.210334 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA pass
14958 10:08:22.210432 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM pass
14959 10:08:22.210517 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA pass
14960 10:08:22.210609 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA pass
14961 10:08:22.210894 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM pass
14962 10:08:22.210993 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA pass
14963 10:08:22.211330 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA pass
14964 10:08:22.211439 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM pass
14965 10:08:22.211534 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA pass
14966 10:08:22.211619 arm64_syscall-abi_getpid_SVE_VL_16 pass
14967 10:08:22.211704 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA pass
14968 10:08:22.211808 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM pass
14969 10:08:22.221354 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA pass
14970 10:08:22.221737 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA pass
14971 10:08:22.221945 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM pass
14972 10:08:22.222152 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA pass
14973 10:08:22.222346 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA pass
14974 10:08:22.222518 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM pass
14975 10:08:22.222685 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA pass
14976 10:08:22.222881 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA pass
14977 10:08:22.223029 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM pass
14978 10:08:22.223198 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA pass
14979 10:08:22.223361 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA pass
14980 10:08:22.223520 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM pass
14981 10:08:22.223690 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA pass
14982 10:08:22.223814 arm64_syscall-abi_sched_yield_FPSIMD pass
14983 10:08:22.223935 arm64_syscall-abi_sched_yield_SVE_VL_256 pass
14984 10:08:22.224056 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA pass
14985 10:08:22.224172 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM pass
14986 10:08:22.224285 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA pass
14987 10:08:22.224879 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA pass
14988 10:08:22.224990 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM pass
14989 10:08:22.225078 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA pass
14990 10:08:22.225166 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA pass
14991 10:08:22.225255 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM pass
14992 10:08:22.225341 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA pass
14993 10:08:22.225430 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA pass
14994 10:08:22.225518 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM pass
14995 10:08:22.225611 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA pass
14996 10:08:22.225709 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA pass
14997 10:08:22.225798 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM pass
14998 10:08:22.225883 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA pass
14999 10:08:22.225967 arm64_syscall-abi_sched_yield_SVE_VL_240 pass
15000 10:08:22.226051 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA pass
15001 10:08:22.229160 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM pass
15002 10:08:22.229460 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA pass
15003 10:08:22.229556 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA pass
15004 10:08:22.229674 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM pass
15005 10:08:22.229766 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA pass
15006 10:08:22.230068 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA pass
15007 10:08:22.230175 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM pass
15008 10:08:22.230279 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA pass
15009 10:08:22.230583 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA pass
15010 10:08:22.230790 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM pass
15011 10:08:22.230926 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA pass
15012 10:08:22.231054 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA pass
15013 10:08:22.231206 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM pass
15014 10:08:22.231336 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA pass
15015 10:08:22.231460 arm64_syscall-abi_sched_yield_SVE_VL_224 pass
15016 10:08:22.231582 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA pass
15017 10:08:22.231730 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM pass
15018 10:08:22.231861 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA pass
15019 10:08:22.231980 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA pass
15020 10:08:22.232103 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM pass
15021 10:08:22.232219 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA pass
15022 10:08:22.232352 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA pass
15023 10:08:22.232469 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM pass
15024 10:08:22.232548 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA pass
15025 10:08:22.232627 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA pass
15026 10:08:22.232715 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM pass
15027 10:08:22.232788 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA pass
15028 10:08:22.232858 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA pass
15029 10:08:22.232945 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM pass
15030 10:08:22.233011 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA pass
15031 10:08:22.237153 arm64_syscall-abi_sched_yield_SVE_VL_208 pass
15032 10:08:22.237462 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA pass
15033 10:08:22.237568 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM pass
15034 10:08:22.237667 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA pass
15035 10:08:22.237760 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA pass
15036 10:08:22.237851 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM pass
15037 10:08:22.238177 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA pass
15038 10:08:22.238275 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA pass
15039 10:08:22.238404 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM pass
15040 10:08:22.238502 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA pass
15041 10:08:22.238600 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA pass
15042 10:08:22.238704 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM pass
15043 10:08:22.238982 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA pass
15044 10:08:22.239318 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA pass
15045 10:08:22.239517 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM pass
15046 10:08:22.239675 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA pass
15047 10:08:22.239868 arm64_syscall-abi_sched_yield_SVE_VL_192 pass
15048 10:08:22.240027 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA pass
15049 10:08:22.240189 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM pass
15050 10:08:22.240344 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA pass
15051 10:08:22.240489 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA pass
15052 10:08:22.240672 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM pass
15053 10:08:22.240815 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA pass
15054 10:08:22.240942 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA pass
15055 10:08:22.241056 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM pass
15056 10:08:22.241145 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA pass
15057 10:08:22.241252 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA pass
15058 10:08:22.241343 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM pass
15059 10:08:22.241430 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA pass
15060 10:08:22.245138 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA pass
15061 10:08:22.245496 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM pass
15062 10:08:22.245595 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA pass
15063 10:08:22.245688 arm64_syscall-abi_sched_yield_SVE_VL_176 pass
15064 10:08:22.245801 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA pass
15065 10:08:22.245912 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM pass
15066 10:08:22.246202 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA pass
15067 10:08:22.246293 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA pass
15068 10:08:22.246380 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM pass
15069 10:08:22.246476 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA pass
15070 10:08:22.246579 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA pass
15071 10:08:22.246678 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM pass
15072 10:08:22.246778 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA pass
15073 10:08:22.246874 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA pass
15074 10:08:22.246975 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM pass
15075 10:08:22.247270 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA pass
15076 10:08:22.247389 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA pass
15077 10:08:22.247499 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM pass
15078 10:08:22.247592 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA pass
15079 10:08:22.247673 arm64_syscall-abi_sched_yield_SVE_VL_160 pass
15080 10:08:22.247960 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA pass
15081 10:08:22.248060 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM pass
15082 10:08:22.248148 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA pass
15083 10:08:22.248225 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA pass
15084 10:08:22.248316 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM pass
15085 10:08:22.248413 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA pass
15086 10:08:22.248716 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA pass
15087 10:08:22.248813 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM pass
15088 10:08:22.248923 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA pass
15089 10:08:22.249206 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA pass
15090 10:08:22.253348 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM pass
15091 10:08:22.253793 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA pass
15092 10:08:22.253899 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA pass
15093 10:08:22.253995 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM pass
15094 10:08:22.254099 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA pass
15095 10:08:22.254188 arm64_syscall-abi_sched_yield_SVE_VL_144 pass
15096 10:08:22.254289 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA pass
15097 10:08:22.254389 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM pass
15098 10:08:22.254497 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA pass
15099 10:08:22.254796 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA pass
15100 10:08:22.254917 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM pass
15101 10:08:22.255220 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA pass
15102 10:08:22.255507 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA pass
15103 10:08:22.255612 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM pass
15104 10:08:22.255914 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA pass
15105 10:08:22.256021 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA pass
15106 10:08:22.256117 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM pass
15107 10:08:22.256402 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA pass
15108 10:08:22.256482 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA pass
15109 10:08:22.265734 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM pass
15110 10:08:22.266080 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA pass
15111 10:08:22.266196 arm64_syscall-abi_sched_yield_SVE_VL_128 pass
15112 10:08:22.266325 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA pass
15113 10:08:22.266445 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM pass
15114 10:08:22.266570 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA pass
15115 10:08:22.266854 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA pass
15116 10:08:22.266959 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM pass
15117 10:08:22.267056 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA pass
15118 10:08:22.267136 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA pass
15119 10:08:22.267411 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM pass
15120 10:08:22.267509 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA pass
15121 10:08:22.267632 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA pass
15122 10:08:22.267724 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM pass
15123 10:08:22.267823 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA pass
15124 10:08:22.267914 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA pass
15125 10:08:22.268033 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM pass
15126 10:08:22.268154 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA pass
15127 10:08:22.268272 arm64_syscall-abi_sched_yield_SVE_VL_112 pass
15128 10:08:22.268372 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA pass
15129 10:08:22.268492 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM pass
15130 10:08:22.268616 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA pass
15131 10:08:22.268740 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA pass
15132 10:08:22.268846 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM pass
15133 10:08:22.268965 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA pass
15134 10:08:22.273195 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA pass
15135 10:08:22.273548 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM pass
15136 10:08:22.273656 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA pass
15137 10:08:22.273738 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA pass
15138 10:08:22.273825 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM pass
15139 10:08:22.273920 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA pass
15140 10:08:22.274017 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA pass
15141 10:08:22.274326 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM pass
15142 10:08:22.274438 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA pass
15143 10:08:22.274522 arm64_syscall-abi_sched_yield_SVE_VL_96 pass
15144 10:08:22.274619 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA pass
15145 10:08:22.274745 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM pass
15146 10:08:22.274881 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA pass
15147 10:08:22.274995 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA pass
15148 10:08:22.275111 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM pass
15149 10:08:22.275211 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA pass
15150 10:08:22.275298 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA pass
15151 10:08:22.275558 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM pass
15152 10:08:22.275640 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA pass
15153 10:08:22.275716 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA pass
15154 10:08:22.275793 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM pass
15155 10:08:22.275872 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA pass
15156 10:08:22.276129 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA pass
15157 10:08:22.276203 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM pass
15158 10:08:22.276291 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA pass
15159 10:08:22.276372 arm64_syscall-abi_sched_yield_SVE_VL_80 pass
15160 10:08:22.276613 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA pass
15161 10:08:22.276717 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM pass
15162 10:08:22.276816 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA pass
15163 10:08:22.277017 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA pass
15164 10:08:22.281197 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM pass
15165 10:08:22.281525 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA pass
15166 10:08:22.281628 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA pass
15167 10:08:22.281713 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM pass
15168 10:08:22.281800 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA pass
15169 10:08:22.281918 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA pass
15170 10:08:22.282020 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM pass
15171 10:08:22.282139 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA pass
15172 10:08:22.282260 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA pass
15173 10:08:22.282378 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM pass
15174 10:08:22.282498 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA pass
15175 10:08:22.282622 arm64_syscall-abi_sched_yield_SVE_VL_64 pass
15176 10:08:22.282984 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA pass
15177 10:08:22.283093 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM pass
15178 10:08:22.283200 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA pass
15179 10:08:22.283316 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA pass
15180 10:08:22.283419 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM pass
15181 10:08:22.283539 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA pass
15182 10:08:22.283677 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA pass
15183 10:08:22.283765 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM pass
15184 10:08:22.283865 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA pass
15185 10:08:22.283959 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA pass
15186 10:08:22.284072 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM pass
15187 10:08:22.284191 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA pass
15188 10:08:22.284303 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA pass
15189 10:08:22.284412 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM pass
15190 10:08:22.284511 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA pass
15191 10:08:22.284601 arm64_syscall-abi_sched_yield_SVE_VL_48 pass
15192 10:08:22.284710 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA pass
15193 10:08:22.284795 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM pass
15194 10:08:22.284913 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA pass
15195 10:08:22.285014 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA pass
15196 10:08:22.289215 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM pass
15197 10:08:22.289553 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA pass
15198 10:08:22.289753 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA pass
15199 10:08:22.289984 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM pass
15200 10:08:22.290162 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA pass
15201 10:08:22.290332 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA pass
15202 10:08:22.290476 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM pass
15203 10:08:22.290657 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA pass
15204 10:08:22.290792 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA pass
15205 10:08:22.290935 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM pass
15206 10:08:22.291076 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA pass
15207 10:08:22.291250 arm64_syscall-abi_sched_yield_SVE_VL_32 pass
15208 10:08:22.291420 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA pass
15209 10:08:22.291605 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM pass
15210 10:08:22.291747 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA pass
15211 10:08:22.291890 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA pass
15212 10:08:22.292031 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM pass
15213 10:08:22.292173 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA pass
15214 10:08:22.292313 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA pass
15215 10:08:22.292453 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM pass
15216 10:08:22.292596 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA pass
15217 10:08:22.292781 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA pass
15218 10:08:22.292934 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM pass
15219 10:08:22.293115 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA pass
15220 10:08:22.293281 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA pass
15221 10:08:22.293407 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM pass
15222 10:08:22.293524 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA pass
15223 10:08:22.293638 arm64_syscall-abi_sched_yield_SVE_VL_16 pass
15224 10:08:22.293827 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA pass
15225 10:08:22.293951 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM pass
15226 10:08:22.294096 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA pass
15227 10:08:22.294219 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA pass
15228 10:08:22.297237 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM pass
15229 10:08:22.297692 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA pass
15230 10:08:22.297881 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA pass
15231 10:08:22.298054 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM pass
15232 10:08:22.298205 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA pass
15233 10:08:22.298394 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA pass
15234 10:08:22.298577 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM pass
15235 10:08:22.298703 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA pass
15236 10:08:22.298814 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA pass
15237 10:08:22.298901 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM pass
15238 10:08:22.299007 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA pass
15239 10:08:22.299096 arm64_syscall-abi pass
15240 10:08:22.299181 arm64_tpidr2_default_value pass
15241 10:08:22.299265 arm64_tpidr2_write_read pass
15242 10:08:22.299348 arm64_tpidr2_write_sleep_read pass
15243 10:08:22.299431 arm64_tpidr2_write_fork_read pass
15244 10:08:22.299515 arm64_tpidr2_write_clone_read pass
15245 10:08:22.299600 arm64_tpidr2 pass
15246 10:08:22.314825 + ../../utils/send-to-lava.sh ./output/result.txt
15247 10:08:22.357987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
15248 10:08:22.359003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
15250 10:08:22.390081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
15251 10:08:22.390648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
15253 10:08:22.422634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
15254 10:08:22.423080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
15256 10:08:22.454218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
15258 10:08:22.454743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
15259 10:08:22.486121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
15261 10:08:22.486704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
15262 10:08:22.518195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
15264 10:08:22.518734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
15265 10:08:22.549238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
15267 10:08:22.549804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
15268 10:08:22.582824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
15270 10:08:22.583370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
15271 10:08:22.615143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass>
15272 10:08:22.615623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass
15274 10:08:22.646615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass
15276 10:08:22.647282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass>
15277 10:08:22.681136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
15278 10:08:22.681609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
15280 10:08:22.712506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
15281 10:08:22.712975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
15283 10:08:22.743514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
15285 10:08:22.744115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
15286 10:08:22.774280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
15287 10:08:22.774741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
15289 10:08:22.805235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
15291 10:08:22.805871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
15292 10:08:22.836008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
15293 10:08:22.836468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
15295 10:08:22.867249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
15297 10:08:22.867816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
15298 10:08:22.898306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
15299 10:08:22.898760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
15301 10:08:22.930640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass
15303 10:08:22.931183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass>
15304 10:08:22.962259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
15306 10:08:22.962674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
15307 10:08:22.995256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
15309 10:08:22.995682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
15310 10:08:23.028828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=pass>
15311 10:08:23.029251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=pass
15313 10:08:23.061384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=pass
15315 10:08:23.061784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=pass>
15316 10:08:23.092996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=pass
15318 10:08:23.093301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=pass>
15319 10:08:23.123688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=pass>
15320 10:08:23.124113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=pass
15322 10:08:23.156546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=pass>
15323 10:08:23.156952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=pass
15325 10:08:23.191349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=pass
15327 10:08:23.191816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=pass>
15328 10:08:23.221854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass
15330 10:08:23.222260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass>
15331 10:08:23.253175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass
15333 10:08:23.253786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass>
15334 10:08:23.284944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass
15336 10:08:23.285524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass>
15337 10:08:23.315791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass>
15338 10:08:23.316247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass
15340 10:08:23.348912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass>
15341 10:08:23.349351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass
15343 10:08:23.388257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass>
15344 10:08:23.388680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass
15346 10:08:23.420979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass
15348 10:08:23.421282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass>
15349 10:08:23.452496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
15351 10:08:23.452771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
15352 10:08:23.484577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
15354 10:08:23.485086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
15355 10:08:23.515846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass
15357 10:08:23.516424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass>
15358 10:08:23.549734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass>
15359 10:08:23.550206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass
15361 10:08:23.584875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass
15363 10:08:23.585339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass>
15364 10:08:23.621298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass
15366 10:08:23.621762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass>
15367 10:08:23.653394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass
15369 10:08:23.653871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass>
15370 10:08:23.685521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass>
15371 10:08:23.686006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass
15373 10:08:23.717947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass>
15374 10:08:23.718402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass
15376 10:08:23.749976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass>
15377 10:08:23.750444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass
15379 10:08:23.780657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass>
15380 10:08:23.781119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass
15382 10:08:23.811785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass>
15383 10:08:23.812231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass
15385 10:08:23.842793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass
15387 10:08:23.843348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass>
15388 10:08:23.873670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass
15390 10:08:23.874250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass>
15391 10:08:23.904467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass>
15392 10:08:23.904942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass
15394 10:08:23.935676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass>
15395 10:08:23.936059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass
15397 10:08:23.966933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass
15399 10:08:23.967425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass>
15400 10:08:23.997956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass
15402 10:08:23.998503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass>
15403 10:08:24.028267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass
15405 10:08:24.028758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass>
15406 10:08:24.058473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass>
15407 10:08:24.058811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass
15409 10:08:24.088771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass
15411 10:08:24.089270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass>
15412 10:08:24.120692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass>
15413 10:08:24.121043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass
15415 10:08:24.151016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass
15417 10:08:24.151467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass>
15418 10:08:24.181419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass
15420 10:08:24.181882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass>
15421 10:08:24.212048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass>
15422 10:08:24.212331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass
15424 10:08:24.242372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass>
15425 10:08:24.242649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass
15427 10:08:24.274004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass
15429 10:08:24.274499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass>
15430 10:08:24.303961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass>
15431 10:08:24.304236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass
15433 10:08:24.334072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
15435 10:08:24.334568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
15436 10:08:24.364766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
15438 10:08:24.365349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
15439 10:08:24.398887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass
15441 10:08:24.399319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass>
15442 10:08:24.430598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
15443 10:08:24.431032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
15445 10:08:24.462760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
15447 10:08:24.463222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
15448 10:08:24.502562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass
15450 10:08:24.503033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass>
15451 10:08:24.534569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass>
15452 10:08:24.534996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass
15454 10:08:24.566422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass>
15455 10:08:24.566836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass
15457 10:08:24.598092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass>
15458 10:08:24.598491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass
15460 10:08:24.630406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass>
15461 10:08:24.630878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass
15463 10:08:24.662219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass
15465 10:08:24.662648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass>
15466 10:08:24.694109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass
15468 10:08:24.694556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass>
15469 10:08:24.726211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass>
15470 10:08:24.726619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass
15472 10:08:24.756942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass>
15473 10:08:24.757406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass
15475 10:08:24.787945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass>
15476 10:08:24.788408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass
15478 10:08:24.818821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass
15480 10:08:24.819231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass>
15481 10:08:24.849861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass>
15482 10:08:24.850304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass
15484 10:08:24.880925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass>
15485 10:08:24.881378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass
15487 10:08:24.911555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass>
15488 10:08:24.911950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass
15490 10:08:24.942456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass>
15491 10:08:24.942909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass
15493 10:08:24.973957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass>
15494 10:08:24.974416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass
15496 10:08:25.004584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass
15498 10:08:25.005197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass>
15499 10:08:25.035395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass>
15500 10:08:25.035833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass
15502 10:08:25.066330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass>
15503 10:08:25.066766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass
15505 10:08:25.097517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass
15507 10:08:25.098062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass>
15508 10:08:25.127950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass>
15509 10:08:25.128348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass
15511 10:08:25.158900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass>
15512 10:08:25.159339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass
15514 10:08:25.191841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass
15516 10:08:25.192386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass>
15517 10:08:25.223981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass
15519 10:08:25.224520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass>
15520 10:08:25.255301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass>
15521 10:08:25.255692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass
15523 10:08:25.286292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass>
15524 10:08:25.286569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass
15526 10:08:25.317407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass
15528 10:08:25.317960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass>
15529 10:08:25.347963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass>
15530 10:08:25.348396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass
15532 10:08:25.379132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass
15534 10:08:25.379659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass>
15535 10:08:25.410553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass>
15536 10:08:25.410990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass
15538 10:08:25.441971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass>
15539 10:08:25.442407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass
15541 10:08:25.474735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass
15543 10:08:25.475280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass>
15544 10:08:25.506559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass>
15545 10:08:25.506963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass
15547 10:08:25.538562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass>
15548 10:08:25.539033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass
15550 10:08:25.570350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass>
15551 10:08:25.570818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass
15553 10:08:25.602075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass>
15554 10:08:25.602530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass
15556 10:08:25.633906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass
15558 10:08:25.634454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass>
15559 10:08:25.665093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass
15561 10:08:25.665617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass>
15562 10:08:25.696594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass
15564 10:08:25.697132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass>
15565 10:08:25.728897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass
15567 10:08:25.729445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass>
15568 10:08:25.759849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass>
15569 10:08:25.760296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass
15571 10:08:25.791158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass>
15572 10:08:25.791576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass
15574 10:08:25.822580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass
15576 10:08:25.823105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass>
15577 10:08:25.853091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass
15579 10:08:25.853624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass>
15580 10:08:25.883683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass>
15581 10:08:25.884141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass
15583 10:08:25.914341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass>
15584 10:08:25.914788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass
15586 10:08:25.945009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass
15588 10:08:25.945538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass>
15589 10:08:25.976155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass>
15590 10:08:25.976587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass
15592 10:08:26.007123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass>
15593 10:08:26.007560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass
15595 10:08:26.038096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass>
15596 10:08:26.038513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass
15598 10:08:26.068563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass>
15599 10:08:26.068939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass
15601 10:08:26.099888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass>
15602 10:08:26.100250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass
15604 10:08:26.130348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass>
15605 10:08:26.130794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass
15607 10:08:26.161088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass
15609 10:08:26.161629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass>
15610 10:08:26.192062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass>
15611 10:08:26.192425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass
15613 10:08:26.223163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass>
15614 10:08:26.223607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass
15616 10:08:26.254045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass>
15617 10:08:26.254483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass
15619 10:08:26.284513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass>
15620 10:08:26.284899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass
15622 10:08:26.315038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass>
15623 10:08:26.315394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass
15625 10:08:26.345836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass>
15626 10:08:26.346189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass
15628 10:08:26.376193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass
15630 10:08:26.376734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass>
15631 10:08:26.407325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass>
15632 10:08:26.407749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass
15634 10:08:26.440283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass>
15635 10:08:26.440739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass
15637 10:08:26.472440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass>
15638 10:08:26.472876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass
15640 10:08:26.504438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass
15642 10:08:26.504974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass>
15643 10:08:26.536558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
15645 10:08:26.537098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
15646 10:08:26.567962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
15647 10:08:26.568402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
15649 10:08:26.599869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
15650 10:08:26.600300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
15652 10:08:26.631823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass>
15653 10:08:26.632274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass
15655 10:08:26.666542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
15656 10:08:26.666985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
15658 10:08:26.697853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
15659 10:08:26.698285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
15661 10:08:26.730185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
15662 10:08:26.730619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
15664 10:08:26.760843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass>
15665 10:08:26.761277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass
15667 10:08:26.791596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
15669 10:08:26.792028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
15670 10:08:26.822671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
15671 10:08:26.823109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
15673 10:08:26.853080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
15674 10:08:26.853490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
15676 10:08:26.884284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass>
15677 10:08:26.884689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass
15679 10:08:26.915896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
15681 10:08:26.916438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
15682 10:08:26.946438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
15683 10:08:26.946827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
15685 10:08:26.978177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
15686 10:08:26.978582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
15688 10:08:27.008446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass>
15689 10:08:27.008857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass
15691 10:08:27.039514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
15693 10:08:27.040113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
15694 10:08:27.070418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
15696 10:08:27.070861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
15697 10:08:27.101549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
15699 10:08:27.102124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
15700 10:08:27.131741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass>
15701 10:08:27.132093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass
15703 10:08:27.162431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
15704 10:08:27.162878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
15706 10:08:27.193151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
15707 10:08:27.193600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
15709 10:08:27.224609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
15710 10:08:27.225052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
15712 10:08:27.255300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass>
15713 10:08:27.255716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass
15715 10:08:27.286842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
15716 10:08:27.287292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
15718 10:08:27.317661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
15719 10:08:27.318101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
15721 10:08:27.348268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
15722 10:08:27.348709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
15724 10:08:27.378923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass>
15725 10:08:27.379380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass
15727 10:08:27.409793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
15729 10:08:27.410403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
15730 10:08:27.440439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
15731 10:08:27.440843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
15733 10:08:27.471708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
15735 10:08:27.472252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
15736 10:08:27.502280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass>
15737 10:08:27.502735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass
15739 10:08:27.532659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
15740 10:08:27.533096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
15742 10:08:27.563675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
15743 10:08:27.564104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
15745 10:08:27.595015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
15746 10:08:27.595464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
15748 10:08:27.626033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass
15750 10:08:27.626566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass>
15751 10:08:27.656654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
15752 10:08:27.657089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
15754 10:08:27.687397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
15755 10:08:27.687831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
15757 10:08:27.718818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
15758 10:08:27.719261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
15760 10:08:27.749356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass
15762 10:08:27.749916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass>
15763 10:08:27.780329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
15765 10:08:27.780867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
15766 10:08:27.812900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
15767 10:08:27.813353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
15769 10:08:27.844179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
15770 10:08:27.844633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
15772 10:08:27.875106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass
15774 10:08:27.875545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass>
15775 10:08:27.907088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
15776 10:08:27.907558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
15778 10:08:27.939682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
15780 10:08:27.940292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
15781 10:08:27.971608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
15783 10:08:27.972142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
15784 10:08:28.002796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass
15786 10:08:28.003326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass>
15787 10:08:28.033709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
15788 10:08:28.034124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
15790 10:08:28.064247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
15791 10:08:28.064685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
15793 10:08:28.095939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
15794 10:08:28.096399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
15796 10:08:28.126892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass
15798 10:08:28.127331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass>
15799 10:08:28.158859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
15801 10:08:28.159492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
15802 10:08:28.190463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
15803 10:08:28.190867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
15805 10:08:28.222364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
15806 10:08:28.222791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
15808 10:08:28.253153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass
15810 10:08:28.253596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass>
15811 10:08:28.284699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
15812 10:08:28.285101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
15814 10:08:28.316101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
15815 10:08:28.316478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
15817 10:08:28.346735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
15818 10:08:28.347093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
15820 10:08:28.377075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass>
15821 10:08:28.377429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass
15823 10:08:28.408175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
15825 10:08:28.408605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
15826 10:08:28.438361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
15827 10:08:28.438709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
15829 10:08:28.469623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
15830 10:08:28.469977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
15832 10:08:28.500574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass>
15833 10:08:28.500926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass
15835 10:08:28.531952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
15836 10:08:28.532300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
15838 10:08:28.562315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
15839 10:08:28.562667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
15841 10:08:28.593535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
15842 10:08:28.594006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
15844 10:08:28.624523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass
15846 10:08:28.625097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass>
15847 10:08:28.657790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
15848 10:08:28.658260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
15850 10:08:28.689809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
15851 10:08:28.690255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
15853 10:08:28.724029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
15855 10:08:28.724583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
15856 10:08:28.757717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass>
15857 10:08:28.758180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass
15859 10:08:28.791362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
15861 10:08:28.792074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
15862 10:08:28.825840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
15864 10:08:28.826390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
15865 10:08:28.859100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
15867 10:08:28.859674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
15868 10:08:28.893480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass>
15869 10:08:28.893977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass
15871 10:08:28.928313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
15872 10:08:28.928795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
15874 10:08:28.962441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
15875 10:08:28.962978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
15877 10:08:28.997173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
15878 10:08:28.997705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
15880 10:08:29.030394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass>
15881 10:08:29.030866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass
15883 10:08:29.064515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
15885 10:08:29.065160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
15886 10:08:29.102411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
15888 10:08:29.103011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
15889 10:08:29.143018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
15890 10:08:29.143488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
15892 10:08:29.177062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass
15894 10:08:29.177657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass>
15895 10:08:29.208334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
15896 10:08:29.208799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
15898 10:08:29.239398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
15899 10:08:29.239871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
15901 10:08:29.270859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
15902 10:08:29.271338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
15904 10:08:29.302114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass>
15905 10:08:29.302563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass
15907 10:08:29.332967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
15908 10:08:29.333465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
15910 10:08:29.364191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
15911 10:08:29.364645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
15913 10:08:29.395073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
15914 10:08:29.395499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
15916 10:08:29.427199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass
15918 10:08:29.427811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass>
15919 10:08:29.458135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
15920 10:08:29.458591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
15922 10:08:29.489711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
15924 10:08:29.490310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
15925 10:08:29.521005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
15926 10:08:29.521467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
15928 10:08:29.551559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass
15930 10:08:29.552155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass>
15931 10:08:29.582697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
15932 10:08:29.583150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
15934 10:08:29.614177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
15935 10:08:29.614631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
15937 10:08:29.647053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
15939 10:08:29.647684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
15940 10:08:29.679255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass
15942 10:08:29.679885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass>
15943 10:08:29.710491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
15944 10:08:29.710966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
15946 10:08:29.742192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
15948 10:08:29.742811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
15949 10:08:29.774169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
15950 10:08:29.774674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
15952 10:08:29.806060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass>
15953 10:08:29.806465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass
15955 10:08:29.836746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
15956 10:08:29.837187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
15958 10:08:29.867564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
15959 10:08:29.867995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
15961 10:08:29.898331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
15962 10:08:29.898677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
15964 10:08:29.928833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass
15966 10:08:29.929322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass>
15967 10:08:29.958899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
15968 10:08:29.959264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
15970 10:08:29.990418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
15971 10:08:29.990862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
15973 10:08:30.022461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
15974 10:08:30.022898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
15976 10:08:30.052907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass>
15977 10:08:30.053340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass
15979 10:08:30.084335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
15981 10:08:30.084863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
15982 10:08:30.115351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
15983 10:08:30.115779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
15985 10:08:30.146935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
15986 10:08:30.147386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
15988 10:08:30.177311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass
15990 10:08:30.177830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass>
15991 10:08:30.208600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
15992 10:08:30.208926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
15994 10:08:30.239804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
15995 10:08:30.240152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
15997 10:08:30.270937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
15998 10:08:30.271347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
16000 10:08:30.308392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass>
16001 10:08:30.308803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass
16003 10:08:30.341481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
16005 10:08:30.341935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
16006 10:08:30.373065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
16007 10:08:30.373470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
16009 10:08:30.404810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
16010 10:08:30.405220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
16012 10:08:30.435528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass>
16013 10:08:30.435927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass
16015 10:08:30.466485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
16017 10:08:30.466919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
16018 10:08:30.497934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
16019 10:08:30.498382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
16021 10:08:30.530021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
16022 10:08:30.530419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
16024 10:08:30.561228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass
16026 10:08:30.561689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass>
16027 10:08:30.593034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
16029 10:08:30.593683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
16030 10:08:30.624509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
16031 10:08:30.624969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
16033 10:08:30.657826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
16035 10:08:30.658454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
16036 10:08:30.689415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass
16038 10:08:30.689972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass>
16039 10:08:30.720549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
16040 10:08:30.720892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
16042 10:08:30.751042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
16043 10:08:30.751400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
16045 10:08:30.782634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
16046 10:08:30.782914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
16048 10:08:30.813492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass
16050 10:08:30.813963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass>
16051 10:08:30.844019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
16052 10:08:30.844374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
16054 10:08:30.874560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
16055 10:08:30.874911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
16057 10:08:30.906202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
16058 10:08:30.906548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
16060 10:08:30.937057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass
16062 10:08:30.937484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass>
16063 10:08:30.967482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
16064 10:08:30.967812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
16066 10:08:30.998571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
16067 10:08:30.998925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
16069 10:08:31.030515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
16070 10:08:31.030863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
16072 10:08:31.061051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass>
16073 10:08:31.061425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass
16075 10:08:31.091866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
16076 10:08:31.092235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
16078 10:08:31.122694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
16079 10:08:31.122972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
16081 10:08:31.153929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
16082 10:08:31.154290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
16084 10:08:31.186083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass>
16085 10:08:31.186462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass
16087 10:08:31.217523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
16089 10:08:31.218070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
16090 10:08:31.249060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
16092 10:08:31.249608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
16093 10:08:31.280900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
16095 10:08:31.281431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
16096 10:08:31.311380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass>
16097 10:08:31.311783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass
16099 10:08:31.343376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
16101 10:08:31.343816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
16102 10:08:31.374517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
16104 10:08:31.374956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
16105 10:08:31.406413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
16107 10:08:31.406961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
16108 10:08:31.438300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass>
16109 10:08:31.438710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass
16111 10:08:31.470424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
16112 10:08:31.470854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
16114 10:08:31.502919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
16116 10:08:31.503464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
16117 10:08:31.534797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
16118 10:08:31.535236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
16120 10:08:31.565438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass
16122 10:08:31.565978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass>
16123 10:08:31.598373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
16124 10:08:31.598912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
16126 10:08:31.632907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
16127 10:08:31.633303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
16129 10:08:31.664853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
16130 10:08:31.665156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
16132 10:08:31.695809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass>
16133 10:08:31.696068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass
16135 10:08:31.726996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
16136 10:08:31.727254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
16138 10:08:31.757848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
16139 10:08:31.758123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
16141 10:08:31.791810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
16142 10:08:31.792228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
16144 10:08:31.824880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass>
16145 10:08:31.825155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass
16147 10:08:31.856109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
16149 10:08:31.856392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
16150 10:08:31.887524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
16151 10:08:31.887800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
16153 10:08:31.918499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
16154 10:08:31.918774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
16156 10:08:31.951646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass>
16157 10:08:31.952007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass
16159 10:08:31.983315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
16160 10:08:31.983661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
16162 10:08:32.015013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
16163 10:08:32.015414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
16165 10:08:32.046216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
16166 10:08:32.046662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
16168 10:08:32.077637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass>
16169 10:08:32.078117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass
16171 10:08:32.108654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
16172 10:08:32.109102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
16174 10:08:32.139370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
16175 10:08:32.139791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
16177 10:08:32.170104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
16179 10:08:32.170632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
16180 10:08:32.200899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass>
16181 10:08:32.201280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass
16183 10:08:32.231643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
16185 10:08:32.232074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
16186 10:08:32.262173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
16188 10:08:32.262719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
16189 10:08:32.292920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
16190 10:08:32.293347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
16192 10:08:32.325427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass
16194 10:08:32.325982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass>
16195 10:08:32.356115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
16196 10:08:32.356540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
16198 10:08:32.386814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
16199 10:08:32.387263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
16201 10:08:32.418834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
16202 10:08:32.419285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
16204 10:08:32.449712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass
16206 10:08:32.450246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass>
16207 10:08:32.480089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
16209 10:08:32.480608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
16210 10:08:32.512063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
16211 10:08:32.512528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
16213 10:08:32.542923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
16214 10:08:32.543364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
16216 10:08:32.573435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass
16218 10:08:32.573981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass>
16219 10:08:32.604129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
16220 10:08:32.604506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
16222 10:08:32.634476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
16223 10:08:32.634845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
16225 10:08:32.665277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
16227 10:08:32.665559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
16228 10:08:32.696011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass>
16229 10:08:32.696286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass
16231 10:08:32.728099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
16232 10:08:32.728364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
16234 10:08:32.760481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
16236 10:08:32.760957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
16237 10:08:32.791975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
16238 10:08:32.792241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
16240 10:08:32.823928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass>
16241 10:08:32.824191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass
16243 10:08:32.854656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
16244 10:08:32.854931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
16246 10:08:32.885983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
16247 10:08:32.886353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
16249 10:08:32.917341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
16251 10:08:32.917856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
16252 10:08:32.947907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass
16254 10:08:32.948400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass>
16255 10:08:32.979039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
16256 10:08:32.979406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
16258 10:08:33.011613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
16259 10:08:33.011988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
16261 10:08:33.042558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
16262 10:08:33.042903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
16264 10:08:33.074078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass>
16265 10:08:33.074418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass
16267 10:08:33.105669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
16269 10:08:33.106094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
16270 10:08:33.136574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
16271 10:08:33.136850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
16273 10:08:33.167433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
16274 10:08:33.167801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
16276 10:08:33.198263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass
16278 10:08:33.198843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass>
16279 10:08:33.229639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
16280 10:08:33.230100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
16282 10:08:33.260688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
16283 10:08:33.261117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
16285 10:08:33.292505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
16286 10:08:33.292884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
16288 10:08:33.324646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass>
16289 10:08:33.325005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass
16291 10:08:33.355850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
16292 10:08:33.356206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
16294 10:08:33.388674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
16296 10:08:33.389079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
16297 10:08:33.421014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
16298 10:08:33.421349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
16300 10:08:33.454609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass>
16301 10:08:33.455081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass
16303 10:08:33.487174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
16304 10:08:33.487593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
16306 10:08:33.520228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
16307 10:08:33.520724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
16309 10:08:33.554647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
16311 10:08:33.555078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
16312 10:08:33.586712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass>
16313 10:08:33.587069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass
16315 10:08:33.624788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
16316 10:08:33.625092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
16318 10:08:33.660788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
16320 10:08:33.661080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
16321 10:08:33.696820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
16322 10:08:33.697170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
16324 10:08:33.732507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass
16326 10:08:33.732993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass>
16327 10:08:33.767734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
16328 10:08:33.768124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
16330 10:08:33.803423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
16331 10:08:33.803816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
16333 10:08:33.836181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
16334 10:08:33.836543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
16336 10:08:33.870052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass>
16337 10:08:33.870328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass
16339 10:08:33.903659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
16341 10:08:33.904069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
16342 10:08:33.938128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
16344 10:08:33.938428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
16345 10:08:33.970571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
16346 10:08:33.970937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
16348 10:08:34.003477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass>
16349 10:08:34.003744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass
16351 10:08:34.037788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
16352 10:08:34.038245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
16354 10:08:34.072704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
16355 10:08:34.073084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
16357 10:08:34.107360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
16358 10:08:34.107724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
16360 10:08:34.142047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass>
16361 10:08:34.142403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass
16363 10:08:34.174928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
16364 10:08:34.175208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
16366 10:08:34.209363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
16368 10:08:34.209644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
16369 10:08:34.242348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
16370 10:08:34.242716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
16372 10:08:34.276141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass>
16373 10:08:34.276499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass
16375 10:08:34.308709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
16376 10:08:34.309041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
16378 10:08:34.343525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
16379 10:08:34.343802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
16381 10:08:34.378327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
16382 10:08:34.378606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
16384 10:08:34.412272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass>
16385 10:08:34.412549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass
16387 10:08:34.445306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
16389 10:08:34.445644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
16390 10:08:34.487830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
16391 10:08:34.488177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
16393 10:08:34.520920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
16394 10:08:34.521292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
16396 10:08:34.554276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass>
16397 10:08:34.554554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass
16399 10:08:34.586912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
16400 10:08:34.587279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
16402 10:08:34.621772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
16403 10:08:34.622129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
16405 10:08:34.655619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
16406 10:08:34.656118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
16408 10:08:34.690409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass>
16409 10:08:34.690844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass
16411 10:08:34.722720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
16412 10:08:34.723083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
16414 10:08:34.755061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
16416 10:08:34.755538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
16417 10:08:34.786783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
16418 10:08:34.787131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
16420 10:08:34.818520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass
16422 10:08:34.819116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass>
16423 10:08:34.850909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
16424 10:08:34.851271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
16426 10:08:34.884030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
16427 10:08:34.884374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
16429 10:08:34.917022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
16430 10:08:34.917341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
16432 10:08:34.951554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass>
16433 10:08:34.951949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass
16435 10:08:34.985788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
16436 10:08:34.986197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
16438 10:08:35.019124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
16439 10:08:35.019587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
16441 10:08:35.052322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
16442 10:08:35.052796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
16444 10:08:35.085798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass>
16445 10:08:35.086209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass
16447 10:08:35.117512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
16449 10:08:35.117954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
16450 10:08:35.152218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
16451 10:08:35.152633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
16453 10:08:35.186164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
16454 10:08:35.186641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
16456 10:08:35.220670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass
16458 10:08:35.221293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass>
16459 10:08:35.255201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
16460 10:08:35.255586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
16462 10:08:35.289972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
16463 10:08:35.290315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
16465 10:08:35.324449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
16466 10:08:35.324798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
16468 10:08:35.359020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass>
16469 10:08:35.359369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass
16471 10:08:35.391739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
16472 10:08:35.392093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
16474 10:08:35.425997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
16475 10:08:35.426275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
16477 10:08:35.460414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
16478 10:08:35.460752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
16480 10:08:35.495521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass
16482 10:08:35.495809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass>
16483 10:08:35.530773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
16484 10:08:35.531051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
16486 10:08:35.564569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
16488 10:08:35.564836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
16489 10:08:35.597325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
16491 10:08:35.597604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
16492 10:08:35.630491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass>
16493 10:08:35.630767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass
16495 10:08:35.664435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
16497 10:08:35.664745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
16498 10:08:35.699565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
16500 10:08:35.699910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
16501 10:08:35.734306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
16502 10:08:35.734581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
16504 10:08:35.768343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass
16506 10:08:35.768622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass>
16507 10:08:35.802894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
16508 10:08:35.803174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
16510 10:08:35.837027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
16511 10:08:35.837290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
16513 10:08:35.870983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
16514 10:08:35.871242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
16516 10:08:35.904572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass
16518 10:08:35.904834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass>
16519 10:08:35.938443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
16521 10:08:35.938705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
16522 10:08:35.972083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
16523 10:08:35.972359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
16525 10:08:36.006252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
16526 10:08:36.006531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
16528 10:08:36.042002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass
16530 10:08:36.042280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass>
16531 10:08:36.075442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
16532 10:08:36.075802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
16534 10:08:36.109384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
16536 10:08:36.109840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
16537 10:08:36.143468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
16538 10:08:36.143852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
16540 10:08:36.176612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass
16542 10:08:36.176887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass>
16543 10:08:36.211059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
16544 10:08:36.211404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
16546 10:08:36.245359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
16548 10:08:36.245797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
16549 10:08:36.279135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
16551 10:08:36.279564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
16552 10:08:36.312717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass
16554 10:08:36.313233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass>
16555 10:08:36.346435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
16557 10:08:36.346955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
16558 10:08:36.379392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
16559 10:08:36.379737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
16561 10:08:36.412328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
16562 10:08:36.412701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
16564 10:08:36.446122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass>
16565 10:08:36.446499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass
16567 10:08:36.479865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
16568 10:08:36.480353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
16570 10:08:36.514647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
16571 10:08:36.515125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
16573 10:08:36.549170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
16575 10:08:36.549731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
16576 10:08:36.583380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass>
16577 10:08:36.583751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass
16579 10:08:36.617244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
16581 10:08:36.617552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
16582 10:08:36.651465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
16583 10:08:36.651812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
16585 10:08:36.686182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
16586 10:08:36.686557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
16588 10:08:36.720110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass>
16589 10:08:36.720461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass
16591 10:08:36.754730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
16592 10:08:36.755084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
16594 10:08:36.790834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
16595 10:08:36.791195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
16597 10:08:36.824461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
16598 10:08:36.824735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
16600 10:08:36.857334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass
16602 10:08:36.857609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass>
16603 10:08:36.890695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
16604 10:08:36.890969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
16606 10:08:36.923726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
16607 10:08:36.924139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
16609 10:08:36.957539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
16611 10:08:36.958111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
16612 10:08:36.990672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass
16614 10:08:36.991223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass>
16615 10:08:37.023568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
16616 10:08:37.023959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
16618 10:08:37.056789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
16619 10:08:37.057149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
16621 10:08:37.089963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
16622 10:08:37.090323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
16624 10:08:37.123252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass>
16625 10:08:37.123624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass
16627 10:08:37.156911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
16628 10:08:37.157274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
16630 10:08:37.190231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
16631 10:08:37.190583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
16633 10:08:37.222918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
16634 10:08:37.223376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
16636 10:08:37.256818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass>
16637 10:08:37.257242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass
16639 10:08:37.290518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
16640 10:08:37.290945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
16642 10:08:37.324405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
16643 10:08:37.324831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
16645 10:08:37.358256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
16646 10:08:37.358679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
16648 10:08:37.391781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass>
16649 10:08:37.392204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass
16651 10:08:37.425317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
16653 10:08:37.425808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
16654 10:08:37.461063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
16655 10:08:37.461501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
16657 10:08:37.496176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
16658 10:08:37.496598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
16660 10:08:37.531191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass>
16661 10:08:37.531613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass
16663 10:08:37.565998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
16664 10:08:37.566423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
16666 10:08:37.600435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
16667 10:08:37.600855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
16669 10:08:37.635008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
16671 10:08:37.635471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
16672 10:08:37.669902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass
16674 10:08:37.670328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass>
16675 10:08:37.703892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
16676 10:08:37.704168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
16678 10:08:37.738465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
16679 10:08:37.738891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
16681 10:08:37.774278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
16682 10:08:37.774749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
16684 10:08:37.808485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass>
16685 10:08:37.808966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass
16687 10:08:37.843110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
16688 10:08:37.843601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
16690 10:08:37.879016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
16691 10:08:37.879447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
16693 10:08:37.913994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
16695 10:08:37.914478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
16696 10:08:37.948006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass>
16697 10:08:37.948343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass
16699 10:08:37.980676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
16700 10:08:37.981030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
16702 10:08:38.015144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
16703 10:08:38.015494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
16705 10:08:38.049945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
16706 10:08:38.050349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
16708 10:08:38.084408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass>
16709 10:08:38.084824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass
16711 10:08:38.119475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
16712 10:08:38.119903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
16714 10:08:38.154608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
16715 10:08:38.154950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
16717 10:08:38.190275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
16718 10:08:38.190698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
16720 10:08:38.226062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass
16722 10:08:38.226510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass>
16723 10:08:38.261706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
16724 10:08:38.262086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
16726 10:08:38.295489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
16727 10:08:38.295869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
16729 10:08:38.328365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
16730 10:08:38.328720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
16732 10:08:38.359296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass
16734 10:08:38.359724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass>
16735 10:08:38.390400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
16736 10:08:38.390747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
16738 10:08:38.422048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
16739 10:08:38.422397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
16741 10:08:38.452835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
16742 10:08:38.453111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
16744 10:08:38.484621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass
16746 10:08:38.485051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass>
16747 10:08:38.515886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
16748 10:08:38.516160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
16750 10:08:38.549267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
16752 10:08:38.549545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
16753 10:08:38.580133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
16754 10:08:38.580480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
16756 10:08:38.613956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass>
16757 10:08:38.614229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass
16759 10:08:38.645353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
16761 10:08:38.645629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
16762 10:08:38.679168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
16763 10:08:38.679627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
16765 10:08:38.711408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
16766 10:08:38.711821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
16768 10:08:38.744722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass>
16769 10:08:38.745212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass
16771 10:08:38.776570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
16772 10:08:38.776955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
16774 10:08:38.810844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
16775 10:08:38.811121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
16777 10:08:38.842534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
16778 10:08:38.842898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
16780 10:08:38.874041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass>
16781 10:08:38.874391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass
16783 10:08:38.904558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
16784 10:08:38.904910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
16786 10:08:38.937812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
16787 10:08:38.938212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
16789 10:08:38.969550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
16791 10:08:38.970004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
16792 10:08:38.999896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass>
16793 10:08:39.000171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass
16795 10:08:39.030405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
16796 10:08:39.030815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
16798 10:08:39.060825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
16799 10:08:39.061237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
16801 10:08:39.091923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
16803 10:08:39.092419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
16804 10:08:39.122724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass>
16805 10:08:39.123123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass
16807 10:08:39.153905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
16808 10:08:39.154342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
16810 10:08:39.184069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
16811 10:08:39.184503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
16813 10:08:39.215159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
16815 10:08:39.215766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
16816 10:08:39.249084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass
16818 10:08:39.249741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass>
16819 10:08:39.282284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
16821 10:08:39.282908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
16822 10:08:39.313845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
16823 10:08:39.314267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
16825 10:08:39.346563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
16826 10:08:39.347018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
16828 10:08:39.377047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass>
16829 10:08:39.377483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass
16831 10:08:39.408287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
16832 10:08:39.408712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
16834 10:08:39.438917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
16836 10:08:39.439486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
16837 10:08:39.471732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
16838 10:08:39.472185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
16840 10:08:39.502993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass>
16841 10:08:39.503450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass
16843 10:08:39.534299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
16844 10:08:39.534749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
16846 10:08:39.566019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
16847 10:08:39.566401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
16849 10:08:39.596882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
16850 10:08:39.597291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
16852 10:08:39.628253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass>
16853 10:08:39.628655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass
16855 10:08:39.659371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
16856 10:08:39.659771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
16858 10:08:39.694109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
16859 10:08:39.694591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
16861 10:08:39.729062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
16862 10:08:39.729520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
16864 10:08:39.760921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass>
16865 10:08:39.761395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass
16867 10:08:39.792986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
16868 10:08:39.793392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
16870 10:08:39.824646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
16871 10:08:39.825001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
16873 10:08:39.856142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
16874 10:08:39.856489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
16876 10:08:39.888349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass
16878 10:08:39.888921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass>
16879 10:08:39.919178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
16880 10:08:39.919539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
16882 10:08:39.950862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
16884 10:08:39.951305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
16885 10:08:39.982367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
16886 10:08:39.982719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
16888 10:08:40.014335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass>
16889 10:08:40.014733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass
16891 10:08:40.045767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
16892 10:08:40.046123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
16894 10:08:40.076640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
16895 10:08:40.076997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
16897 10:08:40.107421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
16898 10:08:40.107701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
16900 10:08:40.138791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass>
16901 10:08:40.139234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass
16903 10:08:40.170471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
16904 10:08:40.170969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
16906 10:08:40.205503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
16908 10:08:40.206085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
16909 10:08:40.238760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
16910 10:08:40.239229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
16912 10:08:40.273078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass
16914 10:08:40.273635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass>
16915 10:08:40.307756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
16916 10:08:40.308139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
16918 10:08:40.343366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
16920 10:08:40.343818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
16921 10:08:40.378536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
16922 10:08:40.378955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
16924 10:08:40.412702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass
16926 10:08:40.413231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass>
16927 10:08:40.447226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
16929 10:08:40.447777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
16930 10:08:40.482297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
16931 10:08:40.482689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
16933 10:08:40.517106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
16934 10:08:40.517476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
16936 10:08:40.550023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass>
16937 10:08:40.550301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass
16939 10:08:40.581086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
16940 10:08:40.581362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
16942 10:08:40.612016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
16943 10:08:40.612291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
16945 10:08:40.642979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
16947 10:08:40.643257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
16948 10:08:40.673975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass>
16949 10:08:40.674250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass
16951 10:08:40.704865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
16952 10:08:40.705339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
16954 10:08:40.735532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
16955 10:08:40.735992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
16957 10:08:40.767125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
16959 10:08:40.767738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
16960 10:08:40.798958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass
16962 10:08:40.799559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass>
16963 10:08:40.829408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
16964 10:08:40.829857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
16966 10:08:40.859608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
16967 10:08:40.860053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
16969 10:08:40.890555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
16970 10:08:40.891021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
16972 10:08:40.920982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass>
16973 10:08:40.921437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass
16975 10:08:40.951478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
16976 10:08:40.951867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
16978 10:08:40.983899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
16979 10:08:40.984261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
16981 10:08:41.016249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
16982 10:08:41.016610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
16984 10:08:41.046333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass>
16985 10:08:41.046699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass
16987 10:08:41.076362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
16988 10:08:41.076736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
16990 10:08:41.106651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
16991 10:08:41.107016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
16993 10:08:41.140808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
16995 10:08:41.141367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
16996 10:08:41.171625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass
16998 10:08:41.172128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass>
16999 10:08:41.202465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
17001 10:08:41.202994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
17002 10:08:41.232962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
17003 10:08:41.233395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
17005 10:08:41.263728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
17006 10:08:41.264078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
17008 10:08:41.294820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass>
17009 10:08:41.295225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass
17011 10:08:41.326419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
17012 10:08:41.326829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
17014 10:08:41.357574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
17016 10:08:41.358131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
17017 10:08:41.391905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
17019 10:08:41.392453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
17020 10:08:41.423130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass>
17021 10:08:41.423586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass
17023 10:08:41.454897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
17025 10:08:41.455430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
17026 10:08:41.486513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
17027 10:08:41.486980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
17029 10:08:41.517795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
17031 10:08:41.518329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
17032 10:08:41.548867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass
17034 10:08:41.549438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass>
17035 10:08:41.580282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
17036 10:08:41.580690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
17038 10:08:41.611465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
17039 10:08:41.611868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
17041 10:08:41.645414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
17043 10:08:41.646144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
17044 10:08:41.679565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass
17046 10:08:41.679973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass>
17047 10:08:41.715141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
17048 10:08:41.715459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
17050 10:08:41.750461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
17051 10:08:41.750834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
17053 10:08:41.782617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
17054 10:08:41.782985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
17056 10:08:41.815034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass
17058 10:08:41.815644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass>
17059 10:08:41.846496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
17061 10:08:41.847105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
17062 10:08:41.881784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
17064 10:08:41.882409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
17065 10:08:41.912946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
17066 10:08:41.913307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
17068 10:08:41.944887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass>
17069 10:08:41.945258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass
17071 10:08:41.975779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
17072 10:08:41.976189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
17074 10:08:42.007301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
17075 10:08:42.007739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
17077 10:08:42.038075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
17078 10:08:42.038519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
17080 10:08:42.070530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass>
17081 10:08:42.071002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass
17083 10:08:42.102058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
17085 10:08:42.102596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
17086 10:08:42.132548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
17087 10:08:42.132985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
17089 10:08:42.163512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
17090 10:08:42.163953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
17092 10:08:42.194315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass
17094 10:08:42.194842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass>
17095 10:08:42.224918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
17097 10:08:42.225414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
17098 10:08:42.255424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
17099 10:08:42.255837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
17101 10:08:42.286208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
17102 10:08:42.286658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
17104 10:08:42.317164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass>
17105 10:08:42.317612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass
17107 10:08:42.348057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
17108 10:08:42.348536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
17110 10:08:42.378919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
17111 10:08:42.379381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
17113 10:08:42.409425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
17115 10:08:42.409894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
17116 10:08:42.440104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass>
17117 10:08:42.440487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass
17119 10:08:42.472081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
17121 10:08:42.472566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
17122 10:08:42.503060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
17124 10:08:42.503560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
17125 10:08:42.534458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
17126 10:08:42.534854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
17128 10:08:42.566833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass>
17129 10:08:42.567196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass
17131 10:08:42.596937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
17133 10:08:42.597369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
17134 10:08:42.627530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
17135 10:08:42.627876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
17137 10:08:42.658397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
17138 10:08:42.658764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
17140 10:08:42.690014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass
17142 10:08:42.690595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass>
17143 10:08:42.720708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
17144 10:08:42.721063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
17146 10:08:42.751784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
17147 10:08:42.752061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
17149 10:08:42.783117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
17150 10:08:42.783463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
17152 10:08:42.818065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass>
17153 10:08:42.818528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass
17155 10:08:42.852921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
17157 10:08:42.853404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
17158 10:08:42.887122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
17159 10:08:42.887475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
17161 10:08:42.918246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
17162 10:08:42.918595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
17164 10:08:42.949113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass
17166 10:08:42.949550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass>
17167 10:08:42.981166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
17169 10:08:42.981627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
17170 10:08:43.014429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
17172 10:08:43.015019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
17173 10:08:43.045810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
17174 10:08:43.046262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
17176 10:08:43.077309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass
17178 10:08:43.077960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass>
17179 10:08:43.109608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
17181 10:08:43.110242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
17182 10:08:43.140118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
17184 10:08:43.140611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
17185 10:08:43.170471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
17186 10:08:43.170751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
17188 10:08:43.201424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass
17190 10:08:43.201711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass>
17191 10:08:43.231742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
17192 10:08:43.232106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
17194 10:08:43.262210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
17195 10:08:43.262564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
17197 10:08:43.292445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
17198 10:08:43.292793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
17200 10:08:43.323446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass
17202 10:08:43.323882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass>
17203 10:08:43.354067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
17204 10:08:43.354341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
17206 10:08:43.384841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
17208 10:08:43.385378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
17209 10:08:43.415475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
17211 10:08:43.416024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
17212 10:08:43.446156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass
17214 10:08:43.446677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass>
17215 10:08:43.476445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
17217 10:08:43.476902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
17218 10:08:43.507341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
17219 10:08:43.507812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
17221 10:08:43.538479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
17222 10:08:43.538937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
17224 10:08:43.569565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass
17226 10:08:43.570127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass>
17227 10:08:43.600663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
17228 10:08:43.601122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
17230 10:08:43.631692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
17231 10:08:43.632096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
17233 10:08:43.663249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
17235 10:08:43.663866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
17236 10:08:43.694314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass>
17237 10:08:43.694754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass
17239 10:08:43.724796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
17240 10:08:43.725177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
17242 10:08:43.755260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
17243 10:08:43.755604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
17245 10:08:43.785955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
17246 10:08:43.786297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
17248 10:08:43.817776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass
17250 10:08:43.818191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass>
17251 10:08:43.848664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
17252 10:08:43.849065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
17254 10:08:43.880428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
17256 10:08:43.880849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
17257 10:08:43.911177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
17258 10:08:43.911459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
17260 10:08:43.941874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass
17262 10:08:43.942152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass>
17263 10:08:43.972443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
17264 10:08:43.972786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
17266 10:08:44.003510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
17267 10:08:44.003846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
17269 10:08:44.034376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
17270 10:08:44.034715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
17272 10:08:44.064547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass>
17273 10:08:44.064886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass
17275 10:08:44.095083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
17276 10:08:44.095431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
17278 10:08:44.126227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
17279 10:08:44.126569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
17281 10:08:44.156810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
17282 10:08:44.157148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
17284 10:08:44.187365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass
17286 10:08:44.187771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass>
17287 10:08:44.217814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
17288 10:08:44.218157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
17290 10:08:44.248530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
17292 10:08:44.248964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
17293 10:08:44.281723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
17294 10:08:44.282197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
17296 10:08:44.313453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass>
17297 10:08:44.313892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass
17299 10:08:44.344360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
17300 10:08:44.344718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
17302 10:08:44.374961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
17303 10:08:44.375308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
17305 10:08:44.406209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
17307 10:08:44.406817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
17308 10:08:44.438307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass>
17309 10:08:44.438780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass
17311 10:08:44.469251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
17313 10:08:44.469895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
17314 10:08:44.501062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
17316 10:08:44.501644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
17317 10:08:44.532166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
17319 10:08:44.532739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
17320 10:08:44.563324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass>
17321 10:08:44.563783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass
17323 10:08:44.594532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
17325 10:08:44.594964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
17326 10:08:44.625066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
17327 10:08:44.625527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
17329 10:08:44.657346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
17331 10:08:44.657934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
17332 10:08:44.688273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass>
17333 10:08:44.688679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass
17335 10:08:44.719281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
17336 10:08:44.719669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
17338 10:08:44.750234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
17339 10:08:44.750590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
17341 10:08:44.780412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
17342 10:08:44.780763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
17344 10:08:44.811541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass>
17345 10:08:44.811898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass
17347 10:08:44.842172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
17348 10:08:44.842528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
17350 10:08:44.872859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
17352 10:08:44.873398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
17353 10:08:44.903456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
17354 10:08:44.903877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
17356 10:08:44.934432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass>
17357 10:08:44.934817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass
17359 10:08:44.964764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
17360 10:08:44.965127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
17362 10:08:44.996016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
17364 10:08:44.996456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
17365 10:08:45.026379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
17366 10:08:45.026728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
17368 10:08:45.056280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass>
17369 10:08:45.056633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass
17371 10:08:45.086472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
17372 10:08:45.086827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
17374 10:08:45.117089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
17375 10:08:45.117437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
17377 10:08:45.147051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
17378 10:08:45.147392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
17380 10:08:45.178563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass>
17381 10:08:45.178903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass
17383 10:08:45.208456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
17384 10:08:45.208795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
17386 10:08:45.238349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
17387 10:08:45.238690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
17389 10:08:45.268453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
17390 10:08:45.268802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
17392 10:08:45.298866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass
17394 10:08:45.299286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass>
17395 10:08:45.328995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
17396 10:08:45.329335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
17398 10:08:45.359092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
17399 10:08:45.359431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
17401 10:08:45.389075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
17402 10:08:45.389417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
17404 10:08:45.419215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass>
17405 10:08:45.419600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass
17407 10:08:45.450527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
17409 10:08:45.450974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
17410 10:08:45.481338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
17412 10:08:45.481929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
17413 10:08:45.512343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
17414 10:08:45.512797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
17416 10:08:45.543362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass>
17417 10:08:45.543815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass
17419 10:08:45.574327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
17420 10:08:45.574763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
17422 10:08:45.604881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
17423 10:08:45.605307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
17425 10:08:45.635651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
17427 10:08:45.636090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
17428 10:08:45.666182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass>
17429 10:08:45.666628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass
17431 10:08:45.696776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
17432 10:08:45.697245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
17434 10:08:45.727500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
17435 10:08:45.727969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
17437 10:08:45.758168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
17438 10:08:45.758604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
17440 10:08:45.789244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass
17442 10:08:45.789792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass>
17443 10:08:45.819809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
17444 10:08:45.820209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
17446 10:08:45.850323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
17447 10:08:45.850643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
17449 10:08:45.880196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
17450 10:08:45.880652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
17452 10:08:45.910899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass>
17453 10:08:45.911299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass
17455 10:08:45.941849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
17456 10:08:45.942241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
17458 10:08:45.972954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
17460 10:08:45.973402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
17461 10:08:46.003935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
17462 10:08:46.004351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
17464 10:08:46.034315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass>
17465 10:08:46.034715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass
17467 10:08:46.065018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
17468 10:08:46.065444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
17470 10:08:46.095696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
17471 10:08:46.096150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
17473 10:08:46.126737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
17474 10:08:46.127174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
17476 10:08:46.157714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass
17478 10:08:46.158237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass>
17479 10:08:46.188525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
17480 10:08:46.188971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
17482 10:08:46.219411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
17483 10:08:46.219878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
17485 10:08:46.250309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
17486 10:08:46.250756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
17488 10:08:46.281135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass>
17489 10:08:46.281574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass
17491 10:08:46.312484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
17492 10:08:46.312931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
17494 10:08:46.342723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
17495 10:08:46.343160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
17497 10:08:46.372940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
17498 10:08:46.373363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
17500 10:08:46.403553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass>
17501 10:08:46.403967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass
17503 10:08:46.434650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
17505 10:08:46.435087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
17506 10:08:46.465893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
17507 10:08:46.466315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
17509 10:08:46.498923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
17510 10:08:46.499367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
17512 10:08:46.531155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass>
17513 10:08:46.531561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass
17515 10:08:46.562503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
17516 10:08:46.562923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
17518 10:08:46.594210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
17519 10:08:46.594613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
17521 10:08:46.625936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
17522 10:08:46.626418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
17524 10:08:46.656773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass
17526 10:08:46.657381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass>
17527 10:08:46.687345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
17528 10:08:46.687760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
17530 10:08:46.718954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
17531 10:08:46.719219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
17533 10:08:46.750127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
17534 10:08:46.750520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
17536 10:08:46.781371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass
17538 10:08:46.781811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass>
17539 10:08:46.812546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
17540 10:08:46.812948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
17542 10:08:46.843695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
17543 10:08:46.844094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
17545 10:08:46.874505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
17546 10:08:46.874951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
17548 10:08:46.904756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass
17550 10:08:46.905287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass>
17551 10:08:46.935596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
17553 10:08:46.936122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
17554 10:08:46.967173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
17556 10:08:46.967699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
17557 10:08:46.997947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
17559 10:08:46.998465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
17560 10:08:47.028073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass
17562 10:08:47.028600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass>
17563 10:08:47.058951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
17564 10:08:47.059371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
17566 10:08:47.089680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
17567 10:08:47.090115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
17569 10:08:47.120538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
17571 10:08:47.121067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
17572 10:08:47.151027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass>
17573 10:08:47.151450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass
17575 10:08:47.182041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
17576 10:08:47.182472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
17578 10:08:47.212505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
17579 10:08:47.212907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
17581 10:08:47.242965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
17582 10:08:47.243388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
17584 10:08:47.274210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass
17586 10:08:47.274727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass>
17587 10:08:47.304563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
17588 10:08:47.304922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
17590 10:08:47.335114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
17592 10:08:47.335550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
17593 10:08:47.365672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
17594 10:08:47.366000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
17596 10:08:47.395679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass>
17597 10:08:47.396028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass
17599 10:08:47.426008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
17600 10:08:47.426375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
17602 10:08:47.456161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
17603 10:08:47.456512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
17605 10:08:47.487231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
17607 10:08:47.487697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
17608 10:08:47.519021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass
17610 10:08:47.519452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass>
17611 10:08:47.550238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
17612 10:08:47.550585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
17614 10:08:47.580724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
17615 10:08:47.581182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
17617 10:08:47.611445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
17618 10:08:47.611882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
17620 10:08:47.642503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass
17622 10:08:47.643034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass>
17623 10:08:47.673441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
17625 10:08:47.674030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
17626 10:08:47.704295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
17627 10:08:47.704725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
17629 10:08:47.734800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
17630 10:08:47.735190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
17632 10:08:47.766181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass>
17633 10:08:47.766502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass
17635 10:08:47.796323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
17636 10:08:47.796599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
17638 10:08:47.829275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
17640 10:08:47.829622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
17641 10:08:47.866457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
17642 10:08:47.866828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
17644 10:08:47.897002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass
17646 10:08:47.897526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass>
17647 10:08:47.927367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
17648 10:08:47.927715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
17650 10:08:47.958753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
17651 10:08:47.959181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
17653 10:08:47.991574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
17654 10:08:47.991850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
17656 10:08:48.024514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass
17658 10:08:48.025016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass>
17659 10:08:48.058181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
17660 10:08:48.058576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
17662 10:08:48.093008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
17664 10:08:48.093312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
17665 10:08:48.126743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
17667 10:08:48.127203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
17668 10:08:48.160028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass
17670 10:08:48.160439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass>
17671 10:08:48.191724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
17672 10:08:48.192093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
17674 10:08:48.222447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
17675 10:08:48.222821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
17677 10:08:48.253341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
17679 10:08:48.253750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
17680 10:08:48.284393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass>
17681 10:08:48.284791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass
17683 10:08:48.314768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
17684 10:08:48.315043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
17686 10:08:48.345133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
17688 10:08:48.345657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
17689 10:08:48.375445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
17690 10:08:48.375809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
17692 10:08:48.406433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass
17694 10:08:48.406929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass>
17695 10:08:48.436942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
17697 10:08:48.437394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
17698 10:08:48.468039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
17699 10:08:48.468437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
17701 10:08:48.499092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
17702 10:08:48.499492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
17704 10:08:48.530607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass
17706 10:08:48.531157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass>
17707 10:08:48.562011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
17708 10:08:48.562450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
17710 10:08:48.593014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
17711 10:08:48.593467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
17713 10:08:48.625803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
17714 10:08:48.626280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
17716 10:08:48.656281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass>
17717 10:08:48.656721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass
17719 10:08:48.691345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
17721 10:08:48.691933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
17722 10:08:48.727257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
17723 10:08:48.727720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
17725 10:08:48.767686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
17726 10:08:48.768147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
17728 10:08:48.809127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass>
17729 10:08:48.809495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass
17731 10:08:48.848122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
17732 10:08:48.848394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
17734 10:08:48.886544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
17735 10:08:48.886983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
17737 10:08:48.930229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
17738 10:08:48.930516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
17740 10:08:48.968506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass>
17741 10:08:48.968783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass
17743 10:08:49.007987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
17745 10:08:49.008390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
17746 10:08:49.039813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
17747 10:08:49.040169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
17749 10:08:49.070530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
17750 10:08:49.070877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
17752 10:08:49.101072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass>
17753 10:08:49.101515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass
17755 10:08:49.132152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
17756 10:08:49.132556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
17758 10:08:49.163655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
17759 10:08:49.164112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
17761 10:08:49.195029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
17762 10:08:49.195456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
17764 10:08:49.225848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass>
17765 10:08:49.226278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass
17767 10:08:49.256037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
17768 10:08:49.256313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
17770 10:08:49.286232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
17771 10:08:49.286507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
17773 10:08:49.316330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
17774 10:08:49.316605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
17776 10:08:49.347430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass>
17777 10:08:49.347693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass
17779 10:08:49.378258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
17780 10:08:49.378626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
17782 10:08:49.408685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
17783 10:08:49.409046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
17785 10:08:49.439601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
17786 10:08:49.439952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
17788 10:08:49.470514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass>
17789 10:08:49.470981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass
17791 10:08:49.501529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
17793 10:08:49.502087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
17794 10:08:49.532597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
17796 10:08:49.533137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
17797 10:08:49.563418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
17798 10:08:49.563814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
17800 10:08:49.595571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass>
17801 10:08:49.596003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass
17803 10:08:49.626822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
17804 10:08:49.627293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
17806 10:08:49.658230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
17807 10:08:49.658698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
17809 10:08:49.688824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
17810 10:08:49.689258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
17812 10:08:49.719338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass>
17813 10:08:49.719789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass
17815 10:08:49.750461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
17816 10:08:49.750920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
17818 10:08:49.780899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
17820 10:08:49.781421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
17821 10:08:49.812397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
17822 10:08:49.812865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
17824 10:08:49.843536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass
17826 10:08:49.844106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass>
17827 10:08:49.874189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
17828 10:08:49.874548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
17830 10:08:49.904313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
17831 10:08:49.904680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
17833 10:08:49.934627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
17834 10:08:49.934978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
17836 10:08:49.965038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass>
17837 10:08:49.965384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass
17839 10:08:49.996159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
17840 10:08:49.996519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
17842 10:08:50.028909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
17843 10:08:50.029312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
17845 10:08:50.061800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
17846 10:08:50.062211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
17848 10:08:50.096992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass
17850 10:08:50.097544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass>
17851 10:08:50.128371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
17852 10:08:50.128774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
17854 10:08:50.159176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
17855 10:08:50.159526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
17857 10:08:50.193005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
17858 10:08:50.193390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
17860 10:08:50.226140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass
17862 10:08:50.226599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass>
17863 10:08:50.256583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
17864 10:08:50.257091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
17866 10:08:50.287290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
17867 10:08:50.287674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
17869 10:08:50.318256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
17871 10:08:50.318641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
17872 10:08:50.349838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass>
17873 10:08:50.350216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass
17875 10:08:50.386523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
17876 10:08:50.386901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
17878 10:08:50.418441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
17880 10:08:50.418855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
17881 10:08:50.450047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
17882 10:08:50.450415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
17884 10:08:50.480850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass
17886 10:08:50.481397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass>
17887 10:08:50.511493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
17888 10:08:50.511931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
17890 10:08:50.542457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
17891 10:08:50.542897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
17893 10:08:50.573377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
17895 10:08:50.573939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
17896 10:08:50.604850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass>
17897 10:08:50.605284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass
17899 10:08:50.635390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
17900 10:08:50.635733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
17902 10:08:50.666639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
17903 10:08:50.667000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
17905 10:08:50.698352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
17906 10:08:50.698696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
17908 10:08:50.729990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass>
17909 10:08:50.730383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass
17911 10:08:50.760426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
17912 10:08:50.760772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
17914 10:08:50.791037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
17915 10:08:50.791481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
17917 10:08:50.822625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
17918 10:08:50.823076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
17920 10:08:50.854323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass>
17921 10:08:50.854731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass
17923 10:08:50.885506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
17925 10:08:50.886057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
17926 10:08:50.916227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
17927 10:08:50.916634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
17929 10:08:50.946710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
17930 10:08:50.947149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
17932 10:08:50.978091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass
17934 10:08:50.978426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass>
17935 10:08:51.008421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
17937 10:08:51.009062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
17938 10:08:51.040164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
17939 10:08:51.040599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
17941 10:08:51.070880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
17943 10:08:51.071478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
17944 10:08:51.101969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass>
17945 10:08:51.102431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass
17947 10:08:51.133778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
17948 10:08:51.134256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
17950 10:08:51.164970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
17952 10:08:51.165442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
17953 10:08:51.195756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
17954 10:08:51.196098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
17956 10:08:51.226427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass>
17957 10:08:51.226770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass
17959 10:08:51.256780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
17960 10:08:51.257121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
17962 10:08:51.288819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
17963 10:08:51.289323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
17965 10:08:51.320245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
17966 10:08:51.320713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
17968 10:08:51.351581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass>
17969 10:08:51.352028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass
17971 10:08:51.382630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
17973 10:08:51.383168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
17974 10:08:51.416281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
17976 10:08:51.416865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
17977 10:08:51.448407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
17978 10:08:51.448850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
17980 10:08:51.479983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass>
17981 10:08:51.480428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass
17983 10:08:51.512804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
17985 10:08:51.513357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
17986 10:08:51.544154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
17987 10:08:51.544614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
17989 10:08:51.577080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
17990 10:08:51.577552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
17992 10:08:51.610157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass
17994 10:08:51.610736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass>
17995 10:08:51.642231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
17996 10:08:51.642735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
17998 10:08:51.673984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
17999 10:08:51.674443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
18001 10:08:51.705709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
18002 10:08:51.706259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
18004 10:08:51.738365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass
18006 10:08:51.738902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass>
18007 10:08:51.769884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
18009 10:08:51.770432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
18010 10:08:51.801423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
18012 10:08:51.802022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
18013 10:08:51.835947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
18014 10:08:51.836361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
18016 10:08:51.869357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass
18018 10:08:51.869702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass>
18019 10:08:51.904947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
18021 10:08:51.905386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
18022 10:08:51.938179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
18024 10:08:51.938628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
18025 10:08:51.971982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
18026 10:08:51.972328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
18028 10:08:52.003399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass>
18029 10:08:52.003776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass
18031 10:08:52.035386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
18032 10:08:52.035775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
18034 10:08:52.067400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
18035 10:08:52.067803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
18037 10:08:52.104886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
18038 10:08:52.105248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
18040 10:08:52.136736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass
18042 10:08:52.137010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass>
18043 10:08:52.170192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
18044 10:08:52.170644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
18046 10:08:52.200803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
18047 10:08:52.201169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
18049 10:08:52.231868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
18050 10:08:52.232224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
18052 10:08:52.262204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass>
18053 10:08:52.262554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass
18055 10:08:52.294092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
18056 10:08:52.294454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
18058 10:08:52.325098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
18059 10:08:52.325543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
18061 10:08:52.355886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
18062 10:08:52.356205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
18064 10:08:52.387266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass>
18065 10:08:52.387530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass
18067 10:08:52.419184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
18068 10:08:52.419449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
18070 10:08:52.451486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
18071 10:08:52.451762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
18073 10:08:52.483562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
18074 10:08:52.484043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
18076 10:08:52.514512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass>
18077 10:08:52.514972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass
18079 10:08:52.545542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
18081 10:08:52.546102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
18082 10:08:52.576930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
18083 10:08:52.577246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
18085 10:08:52.608176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
18086 10:08:52.608453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
18088 10:08:52.639726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass>
18089 10:08:52.640005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass
18091 10:08:52.670955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
18092 10:08:52.671230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
18094 10:08:52.701803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
18095 10:08:52.702078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
18097 10:08:52.732209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
18098 10:08:52.732484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
18100 10:08:52.763181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass
18102 10:08:52.763459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass>
18103 10:08:52.794062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
18104 10:08:52.794360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
18106 10:08:52.824283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
18107 10:08:52.824732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
18109 10:08:52.855215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
18110 10:08:52.855652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
18112 10:08:52.886664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass>
18113 10:08:52.887102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass
18115 10:08:52.917916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
18117 10:08:52.918446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
18118 10:08:52.948558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
18119 10:08:52.949025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
18121 10:08:52.979375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
18122 10:08:52.979771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
18124 10:08:53.009816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass
18126 10:08:53.010095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass>
18127 10:08:53.040232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
18128 10:08:53.040493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
18130 10:08:53.071233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
18131 10:08:53.071507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
18133 10:08:53.102355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
18134 10:08:53.102629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
18136 10:08:53.132808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass>
18137 10:08:53.133082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass
18139 10:08:53.163649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
18140 10:08:53.163999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
18142 10:08:53.194633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
18144 10:08:53.195104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
18145 10:08:53.225200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
18146 10:08:53.225666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
18148 10:08:53.256798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass
18150 10:08:53.257394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass>
18151 10:08:53.287870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
18152 10:08:53.288323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
18154 10:08:53.318477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
18155 10:08:53.318834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
18157 10:08:53.348990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
18158 10:08:53.349267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
18160 10:08:53.380716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass
18162 10:08:53.381310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass>
18163 10:08:53.412380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
18164 10:08:53.412789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
18166 10:08:53.444694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
18167 10:08:53.445120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
18169 10:08:53.477179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
18171 10:08:53.477644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
18172 10:08:53.508324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass
18174 10:08:53.508794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass>
18175 10:08:53.540296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
18176 10:08:53.540703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
18178 10:08:53.574144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
18179 10:08:53.574422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
18181 10:08:53.606050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
18183 10:08:53.606424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
18184 10:08:53.637899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass>
18185 10:08:53.638263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass
18187 10:08:53.670916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
18188 10:08:53.671286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
18190 10:08:53.702172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
18191 10:08:53.702548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
18193 10:08:53.733636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
18194 10:08:53.734063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
18196 10:08:53.765879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass>
18197 10:08:53.766289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass
18199 10:08:53.797060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
18200 10:08:53.797434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
18202 10:08:53.827985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
18203 10:08:53.828439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
18205 10:08:53.859072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
18207 10:08:53.859510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
18208 10:08:53.891607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass
18210 10:08:53.892062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass>
18211 10:08:53.923614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
18212 10:08:53.924072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
18214 10:08:53.954998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
18215 10:08:53.955439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
18217 10:08:53.986195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
18218 10:08:53.986626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
18220 10:08:54.016967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass>
18221 10:08:54.017419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass
18223 10:08:54.048201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
18225 10:08:54.048730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
18226 10:08:54.079575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
18227 10:08:54.080017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
18229 10:08:54.110755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
18230 10:08:54.111156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
18232 10:08:54.141916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass>
18233 10:08:54.142385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass
18235 10:08:54.172884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
18236 10:08:54.173321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
18238 10:08:54.203854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
18239 10:08:54.204335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
18241 10:08:54.234980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
18242 10:08:54.235449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
18244 10:08:54.265727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass>
18245 10:08:54.266179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass
18247 10:08:54.296551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
18248 10:08:54.297011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
18250 10:08:54.327591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
18251 10:08:54.328045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
18253 10:08:54.358483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
18254 10:08:54.358823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
18256 10:08:54.389931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass>
18257 10:08:54.390217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass
18259 10:08:54.420433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
18260 10:08:54.420895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
18262 10:08:54.451581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
18264 10:08:54.452194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
18265 10:08:54.482548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
18266 10:08:54.483006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
18268 10:08:54.513790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass
18270 10:08:54.514393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass>
18271 10:08:54.544957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
18272 10:08:54.545416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
18274 10:08:54.575937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
18275 10:08:54.576399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
18277 10:08:54.606807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
18278 10:08:54.607252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
18280 10:08:54.638584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass
18282 10:08:54.638965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass>
18283 10:08:54.668893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
18284 10:08:54.669182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
18286 10:08:54.699636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
18287 10:08:54.699915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
18289 10:08:54.731044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
18290 10:08:54.731323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
18292 10:08:54.764469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass>
18293 10:08:54.764744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass
18295 10:08:54.795117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
18297 10:08:54.795396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
18298 10:08:54.826235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
18299 10:08:54.826691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
18301 10:08:54.856969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
18302 10:08:54.857295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
18304 10:08:54.888092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass
18306 10:08:54.888589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass>
18307 10:08:54.918736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
18308 10:08:54.919100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
18310 10:08:54.949561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
18311 10:08:54.949941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
18313 10:08:54.979824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
18314 10:08:54.980115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
18316 10:08:55.010469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass
18318 10:08:55.010765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass>
18319 10:08:55.041636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
18320 10:08:55.041913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
18322 10:08:55.073360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
18324 10:08:55.073846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
18325 10:08:55.106423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
18326 10:08:55.106876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
18328 10:08:55.136830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass>
18329 10:08:55.137291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass
18331 10:08:55.170104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
18332 10:08:55.170557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
18334 10:08:55.200821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
18335 10:08:55.201285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
18337 10:08:55.247583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
18338 10:08:55.248037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
18340 10:08:55.278536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass>
18341 10:08:55.278973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass
18343 10:08:55.309089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
18344 10:08:55.309525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
18346 10:08:55.341721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
18347 10:08:55.342172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
18349 10:08:55.374730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
18350 10:08:55.375176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
18352 10:08:55.406692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass>
18353 10:08:55.407133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass
18355 10:08:55.438420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
18356 10:08:55.438853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
18358 10:08:55.470328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
18359 10:08:55.470854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
18361 10:08:55.506817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
18362 10:08:55.507272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
18364 10:08:55.539058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass>
18365 10:08:55.539480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass
18367 10:08:55.570697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
18368 10:08:55.571132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
18370 10:08:55.602249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
18372 10:08:55.602740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
18373 10:08:55.633496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
18375 10:08:55.634031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
18376 10:08:55.665136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass>
18377 10:08:55.665578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass
18379 10:08:55.696937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
18380 10:08:55.697338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
18382 10:08:55.729852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
18383 10:08:55.730274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
18385 10:08:55.761547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
18386 10:08:55.761841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
18388 10:08:55.792479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass>
18389 10:08:55.792760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass
18391 10:08:55.825590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
18392 10:08:55.826083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
18394 10:08:55.857054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
18395 10:08:55.857423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
18397 10:08:55.888813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
18398 10:08:55.889095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
18400 10:08:55.920443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass>
18401 10:08:55.920816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass
18403 10:08:55.951589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
18405 10:08:55.952025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
18406 10:08:55.983341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
18407 10:08:55.983763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
18409 10:08:56.015123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
18411 10:08:56.015689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
18412 10:08:56.046497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass>
18413 10:08:56.046943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass
18415 10:08:56.078072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
18416 10:08:56.078420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
18418 10:08:56.110166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
18419 10:08:56.110516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
18421 10:08:56.141065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
18422 10:08:56.141398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
18424 10:08:56.171938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass>
18425 10:08:56.172286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass
18427 10:08:56.203014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
18428 10:08:56.203361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
18430 10:08:56.234194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
18431 10:08:56.234538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
18433 10:08:56.264935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
18434 10:08:56.265256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
18436 10:08:56.294927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass
18438 10:08:56.295340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass>
18439 10:08:56.324918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
18440 10:08:56.325268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
18442 10:08:56.355778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
18443 10:08:56.356123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
18445 10:08:56.386898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
18447 10:08:56.387312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
18448 10:08:56.418087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass>
18449 10:08:56.418426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass
18451 10:08:56.448656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
18452 10:08:56.449145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
18454 10:08:56.479332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
18455 10:08:56.479788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
18457 10:08:56.510307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
18459 10:08:56.510661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
18460 10:08:56.541948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass>
18461 10:08:56.542352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass
18463 10:08:56.572517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
18464 10:08:56.572816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
18466 10:08:56.603737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
18467 10:08:56.604075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
18469 10:08:56.635478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
18470 10:08:56.635935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
18472 10:08:56.670746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass
18474 10:08:56.671289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass>
18475 10:08:56.706289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
18476 10:08:56.706693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
18478 10:08:56.739138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
18480 10:08:56.739744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
18481 10:08:56.771669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
18482 10:08:56.772037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
18484 10:08:56.802660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass>
18485 10:08:56.803063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass
18487 10:08:56.834727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
18488 10:08:56.835129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
18490 10:08:56.868159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
18492 10:08:56.868598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
18493 10:08:56.902990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
18495 10:08:56.903302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
18496 10:08:56.936075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass
18498 10:08:56.936439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass>
18499 10:08:56.966981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
18500 10:08:56.967393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
18502 10:08:56.998014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
18504 10:08:56.998562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
18505 10:08:57.029038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
18506 10:08:57.029489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
18508 10:08:57.059991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass>
18509 10:08:57.060410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass
18511 10:08:57.091308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
18512 10:08:57.091824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
18514 10:08:57.123914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
18515 10:08:57.124362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
18517 10:08:57.155041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
18518 10:08:57.155448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
18520 10:08:57.186359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass>
18521 10:08:57.186790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass
18523 10:08:57.217620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
18524 10:08:57.218052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
18526 10:08:57.248801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
18527 10:08:57.249244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
18529 10:08:57.279937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
18531 10:08:57.280366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
18532 10:08:57.310723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass>
18533 10:08:57.311005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass
18535 10:08:57.340999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
18537 10:08:57.341297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
18538 10:08:57.371458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
18539 10:08:57.371738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
18541 10:08:57.402191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
18542 10:08:57.402466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
18544 10:08:57.433060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass
18546 10:08:57.433585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass>
18547 10:08:57.465315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
18549 10:08:57.465660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
18550 10:08:57.496220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
18551 10:08:57.496522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
18553 10:08:57.527231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
18555 10:08:57.527546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
18556 10:08:57.558080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass>
18557 10:08:57.558367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass
18559 10:08:57.591443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
18561 10:08:57.591734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
18562 10:08:57.623361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
18564 10:08:57.623653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
18565 10:08:57.654653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
18567 10:08:57.655219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
18568 10:08:57.686082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass
18570 10:08:57.686616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass>
18571 10:08:57.716537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
18572 10:08:57.716994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
18574 10:08:57.747338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
18575 10:08:57.747802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
18577 10:08:57.782390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
18579 10:08:57.783059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
18580 10:08:57.814358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass
18582 10:08:57.814821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass>
18583 10:08:57.844728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
18585 10:08:57.845191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
18586 10:08:57.875661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
18588 10:08:57.876219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
18589 10:08:57.906497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
18590 10:08:57.906900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
18592 10:08:57.937383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass
18594 10:08:57.937974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass>
18595 10:08:57.968626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
18597 10:08:57.969184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
18598 10:08:58.000229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
18600 10:08:58.000685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
18601 10:08:58.031814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
18603 10:08:58.032247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
18604 10:08:58.062842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass>
18605 10:08:58.063213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass
18607 10:08:58.095804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
18608 10:08:58.096233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
18610 10:08:58.127608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
18611 10:08:58.128003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
18613 10:08:58.160598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
18614 10:08:58.160952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
18616 10:08:58.191431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass>
18617 10:08:58.191901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass
18619 10:08:58.222634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
18621 10:08:58.223204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
18622 10:08:58.255768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
18623 10:08:58.256181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
18625 10:08:58.289958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
18626 10:08:58.290318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
18628 10:08:58.321312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass
18630 10:08:58.321766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass>
18631 10:08:58.352824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
18632 10:08:58.353234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
18634 10:08:58.384119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
18635 10:08:58.384537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
18637 10:08:58.416047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
18638 10:08:58.416390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
18640 10:08:58.451065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass
18642 10:08:58.451584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass>
18643 10:08:58.483409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
18645 10:08:58.483966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
18646 10:08:58.514919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
18647 10:08:58.515371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
18649 10:08:58.546501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
18650 10:08:58.546809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
18652 10:08:58.577681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass>
18653 10:08:58.577985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass
18655 10:08:58.608909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
18657 10:08:58.609457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
18658 10:08:58.639285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
18659 10:08:58.639748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
18661 10:08:58.670088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
18662 10:08:58.670426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
18664 10:08:58.700510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass
18666 10:08:58.701072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass>
18667 10:08:58.730993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
18669 10:08:58.731619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
18670 10:08:58.761955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
18671 10:08:58.762357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
18673 10:08:58.793138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
18674 10:08:58.793549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
18676 10:08:58.824909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass
18678 10:08:58.825361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass>
18679 10:08:58.855885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
18680 10:08:58.856347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
18682 10:08:58.887433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
18683 10:08:58.887889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
18685 10:08:58.918963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
18686 10:08:58.919415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
18688 10:08:58.951001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass>
18689 10:08:58.951407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass
18691 10:08:58.982742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
18692 10:08:58.983143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
18694 10:08:59.014606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
18696 10:08:59.015148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
18697 10:08:59.046287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
18698 10:08:59.046729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
18700 10:08:59.077831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass>
18701 10:08:59.078273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass
18703 10:08:59.112163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
18704 10:08:59.112619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
18706 10:08:59.146669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
18708 10:08:59.147224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
18709 10:08:59.178562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
18710 10:08:59.179005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
18712 10:08:59.210302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass
18714 10:08:59.210734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass>
18715 10:08:59.241674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
18716 10:08:59.242010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
18718 10:08:59.273435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
18720 10:08:59.273788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
18721 10:08:59.306273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
18722 10:08:59.306666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
18724 10:08:59.338874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass>
18725 10:08:59.339331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass
18727 10:08:59.370928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
18728 10:08:59.371366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
18730 10:08:59.403391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
18731 10:08:59.403771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
18733 10:08:59.435506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
18734 10:08:59.435913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
18736 10:08:59.468040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass
18738 10:08:59.468481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass>
18739 10:08:59.499343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
18740 10:08:59.499750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
18742 10:08:59.530906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
18743 10:08:59.531309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
18745 10:08:59.562295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
18746 10:08:59.562713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
18748 10:08:59.593712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass>
18749 10:08:59.594117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass
18751 10:08:59.625092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
18752 10:08:59.625493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
18754 10:08:59.656099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
18755 10:08:59.656393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
18757 10:08:59.686706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
18758 10:08:59.686982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
18760 10:08:59.718113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass>
18761 10:08:59.718502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass
18763 10:08:59.748867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
18765 10:08:59.749455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
18766 10:08:59.780062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
18768 10:08:59.780554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
18769 10:08:59.814852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
18770 10:08:59.815126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
18772 10:08:59.850513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass>
18773 10:08:59.850788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass
18775 10:08:59.885738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
18777 10:08:59.886164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
18778 10:08:59.921983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
18779 10:08:59.922377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
18781 10:08:59.956785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
18783 10:08:59.957250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
18784 10:08:59.991951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass
18786 10:08:59.992399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass>
18787 10:09:00.027349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
18788 10:09:00.027761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
18790 10:09:00.062556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
18792 10:09:00.062999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
18793 10:09:00.097925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
18795 10:09:00.098363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
18796 10:09:00.132475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass
18798 10:09:00.132922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass>
18799 10:09:00.167801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
18800 10:09:00.168233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
18802 10:09:00.203915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
18803 10:09:00.204313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
18805 10:09:00.238858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
18807 10:09:00.239351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
18808 10:09:00.274783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass
18810 10:09:00.275267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass>
18811 10:09:00.310251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
18812 10:09:00.310622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
18814 10:09:00.376352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
18815 10:09:00.376628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
18817 10:09:00.418656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
18818 10:09:00.419005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
18820 10:09:00.452795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass
18822 10:09:00.453227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass>
18823 10:09:00.486590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
18825 10:09:00.486866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
18826 10:09:00.520343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
18827 10:09:00.520696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
18829 10:09:00.554187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
18831 10:09:00.554759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
18832 10:09:00.588415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass
18834 10:09:00.588973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass>
18835 10:09:00.622893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
18836 10:09:00.623340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
18838 10:09:00.657472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
18840 10:09:00.658042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
18841 10:09:00.692232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
18842 10:09:00.692608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
18844 10:09:00.726398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass>
18845 10:09:00.726741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass
18847 10:09:00.760632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
18848 10:09:00.760986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
18850 10:09:00.795040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
18852 10:09:00.795456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
18853 10:09:00.830212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
18854 10:09:00.830561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
18856 10:09:00.866405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass
18858 10:09:00.866831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass>
18859 10:09:00.901364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
18861 10:09:00.901842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
18862 10:09:00.936662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
18863 10:09:00.937048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
18865 10:09:00.971478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
18866 10:09:00.971751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
18868 10:09:01.006611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass
18870 10:09:01.006889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass>
18871 10:09:01.041113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
18873 10:09:01.041387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
18874 10:09:01.075808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
18875 10:09:01.076081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
18877 10:09:01.111425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
18878 10:09:01.111703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
18880 10:09:01.143860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass
18882 10:09:01.144267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass>
18883 10:09:01.174615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
18885 10:09:01.175007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
18886 10:09:01.205376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
18888 10:09:01.206012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
18889 10:09:01.236229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
18890 10:09:01.236703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
18892 10:09:01.266985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass>
18893 10:09:01.267440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass
18895 10:09:01.297882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
18896 10:09:01.298293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
18898 10:09:01.329228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
18900 10:09:01.329875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
18901 10:09:01.360306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
18902 10:09:01.360765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
18904 10:09:01.390790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass>
18905 10:09:01.391149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass
18907 10:09:01.421149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
18909 10:09:01.421473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
18910 10:09:01.451716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
18911 10:09:01.452080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
18913 10:09:01.482299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
18914 10:09:01.482653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
18916 10:09:01.512738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass>
18917 10:09:01.513021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass
18919 10:09:01.553886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
18920 10:09:01.554213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
18922 10:09:01.593827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
18923 10:09:01.594223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
18925 10:09:01.626689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
18926 10:09:01.627083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
18928 10:09:01.662614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass>
18929 10:09:01.662986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass
18931 10:09:01.698073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
18932 10:09:01.698475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
18934 10:09:01.734352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
18935 10:09:01.734730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
18937 10:09:01.768809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
18939 10:09:01.769309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
18940 10:09:01.802763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass>
18941 10:09:01.803114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass
18943 10:09:01.837052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
18944 10:09:01.837404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
18946 10:09:01.870881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
18948 10:09:01.871305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
18949 10:09:01.905335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
18951 10:09:01.905779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
18952 10:09:01.939170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass
18954 10:09:01.939583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass>
18955 10:09:01.972787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
18956 10:09:01.973202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
18958 10:09:02.006669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
18959 10:09:02.007080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
18961 10:09:02.043888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
18962 10:09:02.044262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
18964 10:09:02.079103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass>
18965 10:09:02.079562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass
18967 10:09:02.122154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
18968 10:09:02.122609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
18970 10:09:02.167938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
18971 10:09:02.168379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
18973 10:09:02.204289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
18974 10:09:02.204675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
18976 10:09:02.238917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass>
18977 10:09:02.239334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass
18979 10:09:02.272863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
18980 10:09:02.273237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
18982 10:09:02.307710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
18984 10:09:02.308164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
18985 10:09:02.342138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
18986 10:09:02.342478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
18988 10:09:02.375966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass
18990 10:09:02.376600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass>
18991 10:09:02.410417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
18993 10:09:02.410956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
18994 10:09:02.444831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
18995 10:09:02.445105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
18997 10:09:02.479594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
18998 10:09:02.479949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
19000 10:09:02.514566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass
19002 10:09:02.515028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass>
19003 10:09:02.549505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
19005 10:09:02.549979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
19006 10:09:02.586826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
19007 10:09:02.587237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
19009 10:09:02.621709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
19011 10:09:02.622163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
19012 10:09:02.654242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass>
19013 10:09:02.654653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass
19015 10:09:02.685767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
19016 10:09:02.686150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
19018 10:09:02.718420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
19020 10:09:02.718841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
19021 10:09:02.751779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
19023 10:09:02.752191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
19024 10:09:02.786417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass
19026 10:09:02.786922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass>
19027 10:09:02.820354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
19028 10:09:02.820714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
19030 10:09:02.853834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
19031 10:09:02.854335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
19033 10:09:02.888653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
19034 10:09:02.889082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
19036 10:09:02.923306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass
19038 10:09:02.923769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass>
19039 10:09:02.958306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
19041 10:09:02.958956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
19042 10:09:02.992753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
19044 10:09:02.993120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
19045 10:09:03.024429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
19046 10:09:03.024887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
19048 10:09:03.055208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass
19050 10:09:03.055638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass>
19051 10:09:03.086703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
19052 10:09:03.087049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
19054 10:09:03.120533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
19055 10:09:03.120890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
19057 10:09:03.155167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
19059 10:09:03.155708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
19060 10:09:03.191814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass>
19061 10:09:03.192299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass
19063 10:09:03.227166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
19064 10:09:03.227643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
19066 10:09:03.259348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
19067 10:09:03.259861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
19069 10:09:03.292025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
19071 10:09:03.292719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
19072 10:09:03.323589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass>
19073 10:09:03.324076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass
19075 10:09:03.355555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
19076 10:09:03.356019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
19078 10:09:03.387377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
19079 10:09:03.387786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
19081 10:09:03.420128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
19083 10:09:03.420582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
19084 10:09:03.451819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass>
19085 10:09:03.452215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass
19087 10:09:03.482620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
19089 10:09:03.483061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
19090 10:09:03.514415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
19091 10:09:03.514819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
19093 10:09:03.545929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
19094 10:09:03.546396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
19096 10:09:03.576289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass
19098 10:09:03.576708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass>
19099 10:09:03.606760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
19100 10:09:03.607081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
19102 10:09:03.638485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
19103 10:09:03.638832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
19105 10:09:03.670715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
19106 10:09:03.671125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
19108 10:09:03.702093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass
19110 10:09:03.702517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass>
19111 10:09:03.732326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
19112 10:09:03.732662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
19114 10:09:03.763067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
19115 10:09:03.763515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
19117 10:09:03.794251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
19118 10:09:03.794666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
19120 10:09:03.826293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass>
19121 10:09:03.826756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass
19123 10:09:03.856881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
19124 10:09:03.857341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
19126 10:09:03.887527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
19127 10:09:03.887965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
19129 10:09:03.917998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
19130 10:09:03.918385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
19132 10:09:03.948880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass>
19133 10:09:03.949292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass
19135 10:09:03.979815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
19136 10:09:03.980260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
19138 10:09:04.010902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
19139 10:09:04.011336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
19141 10:09:04.041873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
19142 10:09:04.042326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
19144 10:09:04.073064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass
19146 10:09:04.073507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass>
19147 10:09:04.104382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
19149 10:09:04.104812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
19150 10:09:04.136247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
19151 10:09:04.136641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
19153 10:09:04.167910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
19155 10:09:04.168412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
19156 10:09:04.198696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass>
19157 10:09:04.198974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass
19159 10:09:04.229878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
19160 10:09:04.230232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
19162 10:09:04.260739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
19164 10:09:04.261293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
19165 10:09:04.294141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
19166 10:09:04.294598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
19168 10:09:04.325566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass>
19169 10:09:04.326020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass
19171 10:09:04.356739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
19172 10:09:04.357173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
19174 10:09:04.388421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
19176 10:09:04.389097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
19177 10:09:04.420235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
19179 10:09:04.420797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
19180 10:09:04.450721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass
19182 10:09:04.451279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass>
19183 10:09:04.483963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
19184 10:09:04.484422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
19186 10:09:04.515172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
19187 10:09:04.515604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
19189 10:09:04.545862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
19190 10:09:04.546270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
19192 10:09:04.576336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass
19194 10:09:04.576875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass>
19195 10:09:04.607655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
19197 10:09:04.608182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
19198 10:09:04.642608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
19199 10:09:04.643047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
19201 10:09:04.673870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
19202 10:09:04.674216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
19204 10:09:04.703998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass
19206 10:09:04.704417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass>
19207 10:09:04.735648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
19208 10:09:04.736083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
19210 10:09:04.766492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
19211 10:09:04.766851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
19213 10:09:04.797863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
19214 10:09:04.798215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
19216 10:09:04.829305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass
19218 10:09:04.829788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass>
19219 10:09:04.860068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
19220 10:09:04.860438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
19222 10:09:04.890451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
19223 10:09:04.890812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
19225 10:09:04.921720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
19226 10:09:04.922180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
19228 10:09:04.952030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass>
19229 10:09:04.952392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass
19231 10:09:04.983647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
19232 10:09:04.984007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
19234 10:09:05.014249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
19235 10:09:05.014525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
19237 10:09:05.044660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
19238 10:09:05.045029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
19240 10:09:05.075364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass>
19241 10:09:05.075706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass
19243 10:09:05.106157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
19244 10:09:05.106601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
19246 10:09:05.136977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
19247 10:09:05.137353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
19249 10:09:05.168641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
19250 10:09:05.168988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
19252 10:09:05.199237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass>
19253 10:09:05.199567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass
19255 10:09:05.230035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
19256 10:09:05.230377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
19258 10:09:05.260680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
19259 10:09:05.261022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
19261 10:09:05.291309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
19262 10:09:05.291652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
19264 10:09:05.322732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass>
19265 10:09:05.323076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass
19267 10:09:05.353934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
19268 10:09:05.354279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
19270 10:09:05.384285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
19271 10:09:05.384734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
19273 10:09:05.415134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
19274 10:09:05.415582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
19276 10:09:05.454109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass
19278 10:09:05.454528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass>
19279 10:09:05.501714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
19280 10:09:05.502165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
19282 10:09:05.532719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
19283 10:09:05.533115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
19285 10:09:05.563271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
19286 10:09:05.563661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
19288 10:09:05.593931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass>
19289 10:09:05.594276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass
19291 10:09:05.624194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
19292 10:09:05.624533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
19294 10:09:05.655048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
19295 10:09:05.655392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
19297 10:09:05.686083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
19298 10:09:05.686428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
19300 10:09:05.716091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass>
19301 10:09:05.716430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass
19303 10:09:05.746339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
19304 10:09:05.746684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
19306 10:09:05.776599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
19307 10:09:05.776942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
19309 10:09:05.807143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
19310 10:09:05.807487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
19312 10:09:05.838823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass>
19313 10:09:05.839161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass
19315 10:09:05.869983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
19316 10:09:05.870326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
19318 10:09:05.900164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
19319 10:09:05.900510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
19321 10:09:05.930243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
19322 10:09:05.930610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
19324 10:09:05.960220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass
19326 10:09:05.960702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass>
19327 10:09:05.990490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
19328 10:09:05.990969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
19330 10:09:06.022048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
19331 10:09:06.022443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
19333 10:09:06.052055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
19334 10:09:06.052332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
19336 10:09:06.082560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass>
19337 10:09:06.082838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass
19339 10:09:06.113387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
19341 10:09:06.113838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
19342 10:09:06.144216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
19344 10:09:06.144646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
19345 10:09:06.175895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
19347 10:09:06.176357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
19348 10:09:06.206451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass>
19349 10:09:06.206797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass
19351 10:09:06.237383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
19353 10:09:06.237938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
19354 10:09:06.268715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
19355 10:09:06.269169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
19357 10:09:06.300258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
19358 10:09:06.300709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
19360 10:09:06.332137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass>
19361 10:09:06.332639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass
19363 10:09:06.364044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
19364 10:09:06.364450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
19366 10:09:06.395227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
19367 10:09:06.395621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
19369 10:09:06.426260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
19370 10:09:06.426651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
19372 10:09:06.456777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass
19374 10:09:06.457218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass>
19375 10:09:06.487481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
19377 10:09:06.487952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
19378 10:09:06.519919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
19380 10:09:06.520337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
19381 10:09:06.551924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
19383 10:09:06.552464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
19384 10:09:06.582365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass>
19385 10:09:06.582812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass
19387 10:09:06.614253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
19389 10:09:06.614992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
19390 10:09:06.645609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
19391 10:09:06.646084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
19393 10:09:06.677104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
19395 10:09:06.677408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
19396 10:09:06.708951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass
19398 10:09:06.709296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass>
19399 10:09:06.739434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
19400 10:09:06.739713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
19402 10:09:06.769961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
19403 10:09:06.770439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
19405 10:09:06.800328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
19406 10:09:06.800705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
19408 10:09:06.831122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass>
19409 10:09:06.831571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass
19411 10:09:06.862550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
19412 10:09:06.862957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
19414 10:09:06.893880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
19415 10:09:06.894270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
19417 10:09:06.924995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
19418 10:09:06.925401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
19420 10:09:06.955945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass
19422 10:09:06.956373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass>
19423 10:09:06.986758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
19424 10:09:06.987156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
19426 10:09:07.018262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
19427 10:09:07.018647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
19429 10:09:07.050083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
19430 10:09:07.050487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
19432 10:09:07.081501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass
19434 10:09:07.081941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass>
19435 10:09:07.112592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
19436 10:09:07.113029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
19438 10:09:07.143269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
19439 10:09:07.143723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
19441 10:09:07.174123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
19442 10:09:07.174579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
19444 10:09:07.205477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass
19446 10:09:07.205918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass>
19447 10:09:07.235677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
19448 10:09:07.236021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
19450 10:09:07.266423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
19451 10:09:07.266765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
19453 10:09:07.297036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
19454 10:09:07.297405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
19456 10:09:07.330621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass>
19457 10:09:07.331023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass
19459 10:09:07.362418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
19460 10:09:07.362818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
19462 10:09:07.393960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
19463 10:09:07.394361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
19465 10:09:07.424829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
19466 10:09:07.425292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
19468 10:09:07.455421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass>
19469 10:09:07.455853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass
19471 10:09:07.486012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
19472 10:09:07.486466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
19474 10:09:07.517417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
19476 10:09:07.517957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
19477 10:09:07.548833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
19478 10:09:07.549285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
19480 10:09:07.579513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass>
19481 10:09:07.579944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass
19483 10:09:07.610356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
19484 10:09:07.610786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
19486 10:09:07.640767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
19487 10:09:07.641151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
19489 10:09:07.671204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
19490 10:09:07.671484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
19492 10:09:07.702467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass
19494 10:09:07.702753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass>
19495 10:09:07.733430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
19497 10:09:07.733715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
19498 10:09:07.763812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
19499 10:09:07.764086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
19501 10:09:07.794341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
19502 10:09:07.794704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
19504 10:09:07.825511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass
19506 10:09:07.826068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass>
19507 10:09:07.857911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
19509 10:09:07.858352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
19510 10:09:07.889948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
19511 10:09:07.890412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
19513 10:09:07.920773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
19514 10:09:07.921139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
19516 10:09:07.951699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass
19518 10:09:07.952335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass>
19519 10:09:07.982406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
19520 10:09:07.982862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
19522 10:09:08.014089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
19523 10:09:08.014542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
19525 10:09:08.047451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
19526 10:09:08.047859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
19528 10:09:08.080175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass
19530 10:09:08.080731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass>
19531 10:09:08.111774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
19532 10:09:08.112226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
19534 10:09:08.143082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
19536 10:09:08.143518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
19537 10:09:08.174221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
19538 10:09:08.174669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
19540 10:09:08.204959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass
19542 10:09:08.205484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass>
19543 10:09:08.237314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
19545 10:09:08.237968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
19546 10:09:08.268798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
19547 10:09:08.269240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
19549 10:09:08.299906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
19550 10:09:08.300361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
19552 10:09:08.331064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass
19554 10:09:08.331492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass>
19555 10:09:08.362074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
19556 10:09:08.362522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
19558 10:09:08.394204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
19559 10:09:08.394703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
19561 10:09:08.425369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
19563 10:09:08.425939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
19564 10:09:08.456599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass>
19565 10:09:08.457032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass
19567 10:09:08.488024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
19568 10:09:08.488475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
19570 10:09:08.519399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
19571 10:09:08.519854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
19573 10:09:08.550290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
19574 10:09:08.550834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
19576 10:09:08.586001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass>
19577 10:09:08.586467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass
19579 10:09:08.616795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
19580 10:09:08.617248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
19582 10:09:08.647724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
19583 10:09:08.648185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
19585 10:09:08.679542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
19587 10:09:08.680250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
19588 10:09:08.719515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass>
19589 10:09:08.720047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass
19591 10:09:08.761238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
19593 10:09:08.761888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
19594 10:09:08.800743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
19595 10:09:08.801228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
19597 10:09:08.841084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
19598 10:09:08.841567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
19600 10:09:08.880373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass>
19601 10:09:08.880829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass
19603 10:09:08.917793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
19604 10:09:08.918278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
19606 10:09:08.956480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
19607 10:09:08.956780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
19609 10:09:08.999500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
19611 10:09:08.999906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
19612 10:09:09.036648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass>
19613 10:09:09.036921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass
19615 10:09:09.077353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
19617 10:09:09.077844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
19618 10:09:09.111003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
19619 10:09:09.111419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
19621 10:09:09.149127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
19622 10:09:09.149523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
19624 10:09:09.181137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass
19626 10:09:09.181768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass>
19627 10:09:09.212161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
19629 10:09:09.212779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
19630 10:09:09.242952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
19632 10:09:09.243561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
19633 10:09:09.274022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
19634 10:09:09.274481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
19636 10:09:09.304309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass>
19637 10:09:09.304770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass
19639 10:09:09.335935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
19641 10:09:09.336370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
19642 10:09:09.366535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
19643 10:09:09.366800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
19645 10:09:09.398932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
19647 10:09:09.399273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
19648 10:09:09.430062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass
19650 10:09:09.430533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass>
19651 10:09:09.462029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
19652 10:09:09.462378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
19654 10:09:09.492970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
19655 10:09:09.493415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
19657 10:09:09.523651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
19658 10:09:09.524056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
19660 10:09:09.554229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass>
19661 10:09:09.554576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass
19663 10:09:09.584628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
19664 10:09:09.584984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
19666 10:09:09.615742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
19667 10:09:09.616096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
19669 10:09:09.647346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
19670 10:09:09.647702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
19672 10:09:09.676475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass>
19673 10:09:09.676827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass
19675 10:09:09.707425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
19676 10:09:09.707783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
19678 10:09:09.737933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
19679 10:09:09.738213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
19681 10:09:09.768277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
19682 10:09:09.768551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
19684 10:09:09.798426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass>
19685 10:09:09.798699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass
19687 10:09:09.828705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
19688 10:09:09.829182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
19690 10:09:09.859524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
19691 10:09:09.859900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
19693 10:09:09.890135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
19694 10:09:09.890583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
19696 10:09:09.921980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass>
19697 10:09:09.922438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass
19699 10:09:09.952613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
19700 10:09:09.952991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
19702 10:09:09.984824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
19704 10:09:09.985314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
19705 10:09:10.016557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
19706 10:09:10.016931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
19708 10:09:10.047755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass
19710 10:09:10.048253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass>
19711 10:09:10.079443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
19712 10:09:10.079718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
19714 10:09:10.111574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
19715 10:09:10.111943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
19717 10:09:10.143477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
19718 10:09:10.143869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
19720 10:09:10.175833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass>
19721 10:09:10.176192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass
19723 10:09:10.207832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
19724 10:09:10.208180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
19726 10:09:10.239707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
19727 10:09:10.240056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
19729 10:09:10.271786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
19730 10:09:10.272138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
19732 10:09:10.304137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass>
19733 10:09:10.304612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass
19735 10:09:10.335649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
19736 10:09:10.336000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
19738 10:09:10.366793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
19739 10:09:10.367136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
19741 10:09:10.398413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
19742 10:09:10.398830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
19744 10:09:10.430788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass>
19745 10:09:10.431217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass
19747 10:09:10.465041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
19748 10:09:10.465426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
19750 10:09:10.500295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
19752 10:09:10.500643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
19753 10:09:10.532568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
19754 10:09:10.532967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
19756 10:09:10.565220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass
19758 10:09:10.569856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass>
19759 10:09:10.618184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
19760 10:09:10.618633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
19762 10:09:10.650002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
19764 10:09:10.650566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
19765 10:09:10.680563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
19767 10:09:10.681091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
19768 10:09:10.710927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass
19770 10:09:10.711421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass>
19771 10:09:10.742124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
19772 10:09:10.742545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
19774 10:09:10.772292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
19775 10:09:10.772703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
19777 10:09:10.802944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
19778 10:09:10.803383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
19780 10:09:10.833714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass>
19781 10:09:10.834177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass
19783 10:09:10.864468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
19784 10:09:10.864918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
19786 10:09:10.895763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
19788 10:09:10.896305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
19789 10:09:10.927217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
19790 10:09:10.927613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
19792 10:09:10.958734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass>
19793 10:09:10.959193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass
19795 10:09:10.989553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
19797 10:09:10.990078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
19798 10:09:11.019692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
19799 10:09:11.020154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
19801 10:09:11.050517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
19802 10:09:11.050962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
19804 10:09:11.081636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass>
19805 10:09:11.082121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass
19807 10:09:11.112891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
19808 10:09:11.113357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
19810 10:09:11.143652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
19811 10:09:11.144108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
19813 10:09:11.174423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
19814 10:09:11.174866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
19816 10:09:11.205942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass>
19817 10:09:11.206382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass
19819 10:09:11.236490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
19820 10:09:11.236888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
19822 10:09:11.267450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
19824 10:09:11.268055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
19825 10:09:11.298403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
19826 10:09:11.298842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
19828 10:09:11.328478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass>
19829 10:09:11.328939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass
19831 10:09:11.358914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
19832 10:09:11.359350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
19834 10:09:11.389449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
19836 10:09:11.389897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
19837 10:09:11.421960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
19838 10:09:11.422393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
19840 10:09:11.454333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass
19842 10:09:11.454779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass>
19843 10:09:11.485510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
19845 10:09:11.485952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
19846 10:09:11.518288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
19847 10:09:11.518678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
19849 10:09:11.548783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
19850 10:09:11.549139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
19852 10:09:11.580735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass>
19853 10:09:11.581173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass
19855 10:09:11.612214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
19857 10:09:11.612707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
19858 10:09:11.644495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
19860 10:09:11.645180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
19861 10:09:11.675772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
19862 10:09:11.676180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
19864 10:09:11.707719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass>
19865 10:09:11.708188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass
19867 10:09:11.740506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
19868 10:09:11.740953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
19870 10:09:11.772297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
19871 10:09:11.772738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
19873 10:09:11.803896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
19874 10:09:11.804351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
19876 10:09:11.835390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass>
19877 10:09:11.835844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass
19879 10:09:11.866561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
19880 10:09:11.867023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
19882 10:09:11.898255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
19884 10:09:11.898784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
19885 10:09:11.929602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
19887 10:09:11.930148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
19888 10:09:11.962074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass
19890 10:09:11.962652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass>
19891 10:09:11.994723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
19893 10:09:11.995284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
19894 10:09:12.026902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
19895 10:09:12.027302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
19897 10:09:12.063476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
19898 10:09:12.063876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
19900 10:09:12.094800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass>
19901 10:09:12.095170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass
19903 10:09:12.127386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
19904 10:09:12.127794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
19906 10:09:12.159082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
19907 10:09:12.159535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
19909 10:09:12.190424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
19911 10:09:12.190968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
19912 10:09:12.222028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass>
19913 10:09:12.222487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass
19915 10:09:12.253423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
19917 10:09:12.253871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
19918 10:09:12.284735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
19919 10:09:12.285138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
19921 10:09:12.315416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
19922 10:09:12.315862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
19924 10:09:12.346330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass>
19925 10:09:12.346810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass
19927 10:09:12.376317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
19928 10:09:12.376688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
19930 10:09:12.406400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
19931 10:09:12.406752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
19933 10:09:12.436423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
19934 10:09:12.436777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
19936 10:09:12.467596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass
19938 10:09:12.468036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass>
19939 10:09:12.498211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
19940 10:09:12.498564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
19942 10:09:12.528330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
19943 10:09:12.528684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
19945 10:09:12.559099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
19946 10:09:12.559549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
19948 10:09:12.590026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass>
19949 10:09:12.590496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass
19951 10:09:12.621024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
19952 10:09:12.621469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
19954 10:09:12.653134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
19956 10:09:12.653727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
19957 10:09:12.684857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
19959 10:09:12.685322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
19960 10:09:12.716294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass>
19961 10:09:12.716744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass
19963 10:09:12.748215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
19964 10:09:12.748668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
19966 10:09:12.779906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
19968 10:09:12.780465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
19969 10:09:12.813107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
19970 10:09:12.813537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
19972 10:09:12.846851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass>
19973 10:09:12.847251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass
19975 10:09:12.883877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
19977 10:09:12.884347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
19978 10:09:12.924496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
19979 10:09:12.924935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
19981 10:09:12.967267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
19982 10:09:12.967687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
19984 10:09:13.000137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass
19986 10:09:13.000431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass>
19987 10:09:13.032361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
19988 10:09:13.032737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
19990 10:09:13.066346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
19991 10:09:13.066736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
19993 10:09:13.102933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
19994 10:09:13.103374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
19996 10:09:13.138431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass>
19997 10:09:13.138810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass
19999 10:09:13.172209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
20000 10:09:13.172596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
20002 10:09:13.206430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
20003 10:09:13.206789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
20005 10:09:13.238779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
20006 10:09:13.239160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
20008 10:09:13.271347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass>
20009 10:09:13.271721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass
20011 10:09:13.305027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
20012 10:09:13.305377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
20014 10:09:13.338896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
20015 10:09:13.339326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
20017 10:09:13.372509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
20018 10:09:13.372985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
20020 10:09:13.405694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass>
20021 10:09:13.406134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass
20023 10:09:13.438698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
20024 10:09:13.439142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
20026 10:09:13.472184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
20027 10:09:13.472620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
20029 10:09:13.505430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
20031 10:09:13.505884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
20032 10:09:13.540265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass>
20033 10:09:13.540645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass
20035 10:09:13.574073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
20036 10:09:13.574479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
20038 10:09:13.606787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
20039 10:09:13.607256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
20041 10:09:13.640560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
20042 10:09:13.641023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
20044 10:09:13.672481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass>
20045 10:09:13.672887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass
20047 10:09:13.705872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
20048 10:09:13.706327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
20050 10:09:13.738449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
20051 10:09:13.738928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
20053 10:09:13.773393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
20055 10:09:13.774138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
20056 10:09:13.808251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass>
20057 10:09:13.808699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass
20059 10:09:13.841148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
20060 10:09:13.841615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
20062 10:09:13.872733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
20063 10:09:13.873203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
20065 10:09:13.904770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
20067 10:09:13.905221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
20068 10:09:13.936306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass
20070 10:09:13.936861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass>
20071 10:09:13.967801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
20072 10:09:13.968244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
20074 10:09:14.002223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
20075 10:09:14.002680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
20077 10:09:14.036037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
20078 10:09:14.036484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
20080 10:09:14.068736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass>
20081 10:09:14.069191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass
20083 10:09:14.101057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
20085 10:09:14.101453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
20086 10:09:14.132253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
20088 10:09:14.132538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
20089 10:09:14.162929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
20091 10:09:14.163262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
20092 10:09:14.195562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass>
20093 10:09:14.195965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass
20095 10:09:14.227423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
20096 10:09:14.227715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
20098 10:09:14.260269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
20100 10:09:14.260653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
20101 10:09:14.292800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
20102 10:09:14.293220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
20104 10:09:14.328228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass>
20105 10:09:14.328579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass
20107 10:09:14.364597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
20109 10:09:14.365029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
20110 10:09:14.397316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
20112 10:09:14.397711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
20113 10:09:14.432881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
20114 10:09:14.433273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
20116 10:09:14.466439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass>
20117 10:09:14.466745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass
20119 10:09:14.498582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
20120 10:09:14.498948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
20122 10:09:14.530415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
20123 10:09:14.530787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
20125 10:09:14.561799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
20127 10:09:14.562197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
20128 10:09:14.594459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass>
20129 10:09:14.594870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass
20131 10:09:14.625161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
20133 10:09:14.625588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
20134 10:09:14.659633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
20136 10:09:14.660027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
20137 10:09:14.692483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
20139 10:09:14.693106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
20140 10:09:14.726475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass
20142 10:09:14.727094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass>
20143 10:09:14.758983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
20144 10:09:14.759452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
20146 10:09:14.794595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
20148 10:09:14.795100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
20149 10:09:14.827280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
20150 10:09:14.827682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
20152 10:09:14.859766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass>
20153 10:09:14.860148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass
20155 10:09:14.894640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
20156 10:09:14.895046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
20158 10:09:14.926393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
20160 10:09:14.926836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
20161 10:09:14.958216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
20162 10:09:14.958672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
20164 10:09:14.989759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass
20166 10:09:14.990205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass>
20167 10:09:15.021701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
20168 10:09:15.022108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
20170 10:09:15.053057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
20171 10:09:15.053467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
20173 10:09:15.084533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
20174 10:09:15.084938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
20176 10:09:15.116480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass
20178 10:09:15.116920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass>
20179 10:09:15.147825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
20181 10:09:15.148258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
20182 10:09:15.180015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
20183 10:09:15.180441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
20185 10:09:15.210989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
20186 10:09:15.211330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
20188 10:09:15.242115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass
20190 10:09:15.242437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass>
20191 10:09:15.273287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
20193 10:09:15.273583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
20194 10:09:15.304618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
20196 10:09:15.305062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
20197 10:09:15.335931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
20198 10:09:15.336286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
20200 10:09:15.370666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass
20202 10:09:15.371011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass>
20203 10:09:15.402817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
20205 10:09:15.403364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
20206 10:09:15.435024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
20208 10:09:15.435592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
20209 10:09:15.467236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
20210 10:09:15.467679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
20212 10:09:15.499438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass
20214 10:09:15.500012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass>
20215 10:09:15.531737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
20216 10:09:15.532147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
20218 10:09:15.564019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
20219 10:09:15.564445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
20221 10:09:15.596600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
20222 10:09:15.597071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
20224 10:09:15.631981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass>
20225 10:09:15.632268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass
20227 10:09:15.664423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
20228 10:09:15.664770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
20230 10:09:15.725012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
20231 10:09:15.725379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
20233 10:09:15.756718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
20234 10:09:15.757011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
20236 10:09:15.788075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass>
20237 10:09:15.788353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass
20239 10:09:15.819878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
20240 10:09:15.820177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
20242 10:09:15.852352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
20243 10:09:15.852700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
20245 10:09:15.884238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
20247 10:09:15.884676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
20248 10:09:15.915825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass>
20249 10:09:15.916284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass
20251 10:09:15.948062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
20252 10:09:15.948471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
20254 10:09:15.980115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
20255 10:09:15.980521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
20257 10:09:16.013371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
20259 10:09:16.013955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
20260 10:09:16.044842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass
20262 10:09:16.045420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass>
20263 10:09:16.076989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
20264 10:09:16.077391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
20266 10:09:16.108703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
20267 10:09:16.109164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
20269 10:09:16.140095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
20270 10:09:16.140552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
20272 10:09:16.170844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass>
20273 10:09:16.171247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass
20275 10:09:16.203078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
20276 10:09:16.203530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
20278 10:09:16.235276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
20280 10:09:16.235649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
20281 10:09:16.266960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
20282 10:09:16.267243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
20284 10:09:16.298065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass>
20285 10:09:16.298503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass
20287 10:09:16.329106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
20288 10:09:16.329558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
20290 10:09:16.360385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
20291 10:09:16.360833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
20293 10:09:16.392134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
20294 10:09:16.392553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
20296 10:09:16.424382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass>
20297 10:09:16.424782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass
20299 10:09:16.456325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
20300 10:09:16.456728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
20302 10:09:16.488496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
20303 10:09:16.488925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
20305 10:09:16.519883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
20306 10:09:16.520329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
20308 10:09:16.552998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass>
20309 10:09:16.553479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass
20311 10:09:16.588545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
20312 10:09:16.588999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
20314 10:09:16.620800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
20315 10:09:16.621337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
20317 10:09:16.653111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
20319 10:09:16.653817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
20320 10:09:16.686205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass>
20321 10:09:16.686583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass
20323 10:09:16.718616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
20324 10:09:16.719040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
20326 10:09:16.750725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
20327 10:09:16.751144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
20329 10:09:16.783091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
20330 10:09:16.783491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
20332 10:09:16.814980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass>
20333 10:09:16.815337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass
20335 10:09:16.846796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
20336 10:09:16.847102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
20338 10:09:16.879475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
20339 10:09:16.879897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
20341 10:09:16.911593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
20342 10:09:16.911940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
20344 10:09:16.943986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass
20346 10:09:16.944328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass>
20347 10:09:16.976050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
20348 10:09:16.976445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
20350 10:09:17.007287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
20352 10:09:17.007873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
20353 10:09:17.038954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
20354 10:09:17.039350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
20356 10:09:17.070191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass>
20357 10:09:17.070579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass
20359 10:09:17.102150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
20361 10:09:17.102724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
20362 10:09:17.134946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
20363 10:09:17.135393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
20365 10:09:17.166836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
20367 10:09:17.167280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
20368 10:09:17.198551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass>
20369 10:09:17.198905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass
20371 10:09:17.230661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
20373 10:09:17.231127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
20374 10:09:17.262785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
20375 10:09:17.263212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
20377 10:09:17.294539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
20378 10:09:17.294952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
20380 10:09:17.326309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass>
20381 10:09:17.326706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass
20383 10:09:17.358192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
20384 10:09:17.358609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
20386 10:09:17.390349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
20387 10:09:17.390735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
20389 10:09:17.422396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
20390 10:09:17.422773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
20392 10:09:17.454906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass
20394 10:09:17.455288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass>
20395 10:09:17.486743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
20396 10:09:17.487109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
20398 10:09:17.518765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
20399 10:09:17.519130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
20401 10:09:17.550649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
20402 10:09:17.550923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
20404 10:09:17.582569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass>
20405 10:09:17.582946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass
20407 10:09:17.614343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
20408 10:09:17.614744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
20410 10:09:17.646322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
20411 10:09:17.646708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
20413 10:09:17.677707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
20414 10:09:17.678086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
20416 10:09:17.711606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass>
20417 10:09:17.711979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass
20419 10:09:17.744559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
20420 10:09:17.744923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
20422 10:09:17.776948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
20423 10:09:17.777353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
20425 10:09:17.809693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
20426 10:09:17.810153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
20428 10:09:17.841309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass
20430 10:09:17.841784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass>
20431 10:09:17.874928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
20433 10:09:17.875323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
20434 10:09:17.908616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
20435 10:09:17.909037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
20437 10:09:17.943529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
20438 10:09:17.943937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
20440 10:09:17.976424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass
20442 10:09:17.976838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass>
20443 10:09:18.010160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
20444 10:09:18.010545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
20446 10:09:18.044403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
20447 10:09:18.044759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
20449 10:09:18.080100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
20450 10:09:18.080504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
20452 10:09:18.113507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass>
20453 10:09:18.113947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass
20455 10:09:18.147112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
20456 10:09:18.147525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
20458 10:09:18.181476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
20460 10:09:18.181948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
20461 10:09:18.214504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
20462 10:09:18.214971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
20464 10:09:18.248689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass>
20465 10:09:18.249113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass
20467 10:09:18.283565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
20469 10:09:18.284003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
20470 10:09:18.316550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
20472 10:09:18.317006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
20473 10:09:18.350925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
20474 10:09:18.351312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
20476 10:09:18.383505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass>
20477 10:09:18.383869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass
20479 10:09:18.418271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
20480 10:09:18.418674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
20482 10:09:18.452481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
20483 10:09:18.452800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
20485 10:09:18.487612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
20486 10:09:18.487985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
20488 10:09:18.524303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass>
20489 10:09:18.524693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass
20491 10:09:18.558244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
20492 10:09:18.558713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
20494 10:09:18.590845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
20496 10:09:18.591490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
20497 10:09:18.624312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
20499 10:09:18.624935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
20500 10:09:18.656449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass
20502 10:09:18.656869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass>
20503 10:09:18.689036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
20504 10:09:18.689498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
20506 10:09:18.720960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
20508 10:09:18.721515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
20509 10:09:18.753399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
20511 10:09:18.753770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
20512 10:09:18.787933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass>
20513 10:09:18.788217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass
20515 10:09:18.821274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
20517 10:09:18.821697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
20518 10:09:18.854790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
20520 10:09:18.855219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
20521 10:09:18.887576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
20522 10:09:18.887989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
20524 10:09:18.919753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass>
20525 10:09:18.920157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass
20527 10:09:18.960302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
20528 10:09:18.960712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
20530 10:09:18.998022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
20532 10:09:18.998486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
20533 10:09:19.031841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
20535 10:09:19.032301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
20536 10:09:19.072428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass
20538 10:09:19.072890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass>
20539 10:09:19.106869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
20540 10:09:19.107281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
20542 10:09:19.143172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
20543 10:09:19.143592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
20545 10:09:19.179844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
20546 10:09:19.180263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
20548 10:09:19.213810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass
20550 10:09:19.214261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass>
20551 10:09:19.247284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
20553 10:09:19.247735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
20554 10:09:19.282142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
20555 10:09:19.282554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
20557 10:09:19.317261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
20559 10:09:19.317739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
20560 10:09:19.351146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass>
20561 10:09:19.351622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass
20563 10:09:19.385091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
20564 10:09:19.385545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
20566 10:09:19.420348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
20568 10:09:19.420898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
20569 10:09:19.454010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
20571 10:09:19.454484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
20572 10:09:19.489501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass
20574 10:09:19.490253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass>
20575 10:09:19.524571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
20577 10:09:19.525039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
20578 10:09:19.560304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
20580 10:09:19.560747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
20581 10:09:19.598197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
20582 10:09:19.598604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
20584 10:09:19.634286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass>
20585 10:09:19.634743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass
20587 10:09:19.670601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
20588 10:09:19.670966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
20590 10:09:19.707592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
20592 10:09:19.708333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
20593 10:09:19.744560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
20594 10:09:19.744965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
20596 10:09:19.780732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass
20598 10:09:19.781172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass>
20599 10:09:19.818369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
20600 10:09:19.818781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
20602 10:09:19.851019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
20604 10:09:19.851474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
20605 10:09:19.884160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
20606 10:09:19.884567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
20608 10:09:19.915845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass>
20609 10:09:19.916198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass
20611 10:09:19.946577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
20613 10:09:19.947003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
20614 10:09:19.978626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
20615 10:09:19.979026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
20617 10:09:20.008955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
20618 10:09:20.009363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
20620 10:09:20.046625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass>
20621 10:09:20.047095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass
20623 10:09:20.088949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
20625 10:09:20.089465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
20626 10:09:20.124155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
20628 10:09:20.124668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
20629 10:09:20.158387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
20630 10:09:20.158743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
20632 10:09:20.190260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass>
20633 10:09:20.190615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass
20635 10:09:20.222167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
20636 10:09:20.222537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
20638 10:09:20.254503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
20639 10:09:20.254951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
20641 10:09:20.288961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
20642 10:09:20.289324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
20644 10:09:20.321950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass>
20645 10:09:20.322229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass
20647 10:09:20.354856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
20648 10:09:20.355239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
20650 10:09:20.386695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
20651 10:09:20.386971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
20653 10:09:20.418741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
20654 10:09:20.419021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
20656 10:09:20.450614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass>
20657 10:09:20.450975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass
20659 10:09:20.482419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
20660 10:09:20.482767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
20662 10:09:20.515821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
20663 10:09:20.516169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
20665 10:09:20.549965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
20667 10:09:20.550398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
20668 10:09:20.583422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass>
20669 10:09:20.583832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass
20671 10:09:20.617252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
20673 10:09:20.617783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
20674 10:09:20.652698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
20676 10:09:20.653169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
20677 10:09:20.686929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
20678 10:09:20.687345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
20680 10:09:20.719901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass>
20681 10:09:20.720320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass
20683 10:09:20.752275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
20684 10:09:20.752682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
20686 10:09:20.785380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
20688 10:09:20.785875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
20689 10:09:20.851521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
20690 10:09:20.851893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
20692 10:09:20.895680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass>
20693 10:09:20.895956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass
20695 10:09:20.939176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
20696 10:09:20.939659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
20698 10:09:20.989050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
20699 10:09:20.989527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
20701 10:09:21.038632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
20702 10:09:21.039103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
20704 10:09:21.084778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass
20706 10:09:21.085345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass>
20707 10:09:21.119328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
20709 10:09:21.119813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
20710 10:09:21.154747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
20711 10:09:21.155050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
20713 10:09:21.190166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
20715 10:09:21.190609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
20716 10:09:21.224036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass>
20717 10:09:21.224358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass
20719 10:09:21.258978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
20720 10:09:21.259376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
20722 10:09:21.295494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
20724 10:09:21.295956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
20725 10:09:21.336026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
20727 10:09:21.336498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
20728 10:09:21.372164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass>
20729 10:09:21.372592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass
20731 10:09:21.407669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
20732 10:09:21.407971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
20734 10:09:21.443396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
20735 10:09:21.443757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
20737 10:09:21.478977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
20738 10:09:21.479255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
20740 10:09:21.514403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass>
20741 10:09:21.514747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass
20743 10:09:21.548959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
20745 10:09:21.549584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
20746 10:09:21.583627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
20747 10:09:21.584036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
20749 10:09:21.618540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
20750 10:09:21.619107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
20752 10:09:21.654113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass>
20753 10:09:21.654524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass
20755 10:09:21.689529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
20757 10:09:21.690221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
20758 10:09:21.725438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
20760 10:09:21.726020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
20761 10:09:21.761857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
20763 10:09:21.762376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
20764 10:09:21.795824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass>
20765 10:09:21.796171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass
20767 10:09:21.829876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
20768 10:09:21.830298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
20770 10:09:21.863448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
20772 10:09:21.863931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
20773 10:09:21.896855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
20775 10:09:21.897341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
20776 10:09:21.931085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass>
20777 10:09:21.931566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass
20779 10:09:21.965911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
20781 10:09:21.966542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
20782 10:09:22.000768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
20784 10:09:22.001323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
20785 10:09:22.035673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
20786 10:09:22.036089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
20788 10:09:22.070186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass>
20789 10:09:22.070535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass
20791 10:09:22.104834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
20793 10:09:22.105317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
20794 10:09:22.139048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
20796 10:09:22.139512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
20797 10:09:22.174581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
20798 10:09:22.175001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
20800 10:09:22.210260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass>
20801 10:09:22.210733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass
20803 10:09:22.245270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
20805 10:09:22.245848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
20806 10:09:22.280068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
20808 10:09:22.280645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
20809 10:09:22.314950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
20810 10:09:22.315342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
20812 10:09:22.350784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass
20814 10:09:22.351232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass>
20815 10:09:22.386312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
20817 10:09:22.386792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
20818 10:09:22.422159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
20819 10:09:22.422444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
20821 10:09:22.457502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
20823 10:09:22.457894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
20824 10:09:22.492780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass
20826 10:09:22.493272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass>
20827 10:09:22.527679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
20829 10:09:22.528117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
20830 10:09:22.562494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
20831 10:09:22.562768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
20833 10:09:22.598199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
20835 10:09:22.598477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
20836 10:09:22.632730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass
20838 10:09:22.633177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass>
20839 10:09:22.667263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
20841 10:09:22.667708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
20842 10:09:22.702488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
20843 10:09:22.702882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
20845 10:09:22.736864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
20846 10:09:22.737211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
20848 10:09:22.770581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass
20850 10:09:22.770998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass>
20851 10:09:22.803864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
20852 10:09:22.804273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
20854 10:09:22.838406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
20855 10:09:22.838785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
20857 10:09:22.873970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
20859 10:09:22.874605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
20860 10:09:22.907941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass>
20861 10:09:22.908421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass
20863 10:09:22.942805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
20865 10:09:22.943437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
20866 10:09:22.975800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
20867 10:09:22.976220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
20869 10:09:23.010845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
20870 10:09:23.011317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
20872 10:09:23.045710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass
20874 10:09:23.046248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass>
20875 10:09:23.078775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
20876 10:09:23.079170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
20878 10:09:23.112572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
20880 10:09:23.113024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
20881 10:09:23.145489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
20883 10:09:23.145951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
20884 10:09:23.180753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass>
20885 10:09:23.181171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass
20887 10:09:23.214689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
20888 10:09:23.215108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
20890 10:09:23.248777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
20891 10:09:23.249194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
20893 10:09:23.284184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
20894 10:09:23.284560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
20896 10:09:23.319735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass
20898 10:09:23.320202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass>
20899 10:09:23.353221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
20901 10:09:23.353684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
20902 10:09:23.387384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
20904 10:09:23.387998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
20905 10:09:23.421430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
20907 10:09:23.422034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
20908 10:09:23.455388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass>
20909 10:09:23.455858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass
20911 10:09:23.490189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
20913 10:09:23.490625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
20914 10:09:23.525208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
20916 10:09:23.525730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
20917 10:09:23.559727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
20918 10:09:23.560066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
20920 10:09:23.594465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass>
20921 10:09:23.594808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass
20923 10:09:23.629511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
20925 10:09:23.629947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
20926 10:09:23.664284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
20927 10:09:23.664628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
20929 10:09:23.699901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
20930 10:09:23.700270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
20932 10:09:23.733099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass>
20933 10:09:23.733457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass
20935 10:09:23.763965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
20936 10:09:23.764308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
20938 10:09:23.796282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
20940 10:09:23.796708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
20941 10:09:23.827614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
20942 10:09:23.827967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
20944 10:09:23.858588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass
20946 10:09:23.859215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass>
20947 10:09:23.891739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
20948 10:09:23.892280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
20950 10:09:23.926034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
20952 10:09:23.926602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
20953 10:09:23.960391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
20955 10:09:23.960969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
20956 10:09:23.994959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass
20958 10:09:23.995515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass>
20959 10:09:24.035678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
20960 10:09:24.036161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
20962 10:09:24.070592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
20964 10:09:24.071073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
20965 10:09:24.105993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
20967 10:09:24.106449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
20968 10:09:24.141187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass
20970 10:09:24.141664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass>
20971 10:09:24.175399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
20972 10:09:24.175859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
20974 10:09:24.206380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
20975 10:09:24.206815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
20977 10:09:24.240163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
20978 10:09:24.240601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
20980 10:09:24.274174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass>
20981 10:09:24.274615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass
20983 10:09:24.309025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
20984 10:09:24.309490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
20986 10:09:24.351302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
20988 10:09:24.351869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
20989 10:09:24.387805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
20991 10:09:24.388351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
20992 10:09:24.419729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass>
20993 10:09:24.420124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass
20995 10:09:24.450704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
20996 10:09:24.451103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
20998 10:09:24.482275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
20999 10:09:24.482729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
21001 10:09:24.512900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
21003 10:09:24.513506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
21004 10:09:24.543644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass
21006 10:09:24.544256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass>
21007 10:09:24.574820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
21008 10:09:24.575275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
21010 10:09:24.606320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
21011 10:09:24.606766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
21013 10:09:24.638560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
21015 10:09:24.639010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
21016 10:09:24.670384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass
21018 10:09:24.670939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass>
21019 10:09:24.700977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
21021 10:09:24.701517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
21022 10:09:24.731808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
21023 10:09:24.732260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
21025 10:09:24.763252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
21026 10:09:24.763715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
21028 10:09:24.795491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass>
21029 10:09:24.795923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass
21031 10:09:24.827388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
21033 10:09:24.827940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
21034 10:09:24.858545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
21035 10:09:24.858993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
21037 10:09:24.888876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
21038 10:09:24.889257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
21040 10:09:24.919479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass>
21041 10:09:24.919935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass
21043 10:09:24.951332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
21045 10:09:24.951958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
21046 10:09:24.982806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
21048 10:09:24.983341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
21049 10:09:25.014050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
21051 10:09:25.014576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
21052 10:09:25.044428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass
21054 10:09:25.044850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass>
21055 10:09:25.075419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
21056 10:09:25.075811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
21058 10:09:25.107939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
21059 10:09:25.108381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
21061 10:09:25.138594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
21062 10:09:25.138951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
21064 10:09:25.169722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass
21066 10:09:25.170265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass>
21067 10:09:25.200574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
21069 10:09:25.201004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
21070 10:09:25.231780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
21071 10:09:25.232181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
21073 10:09:25.263096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
21074 10:09:25.263548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
21076 10:09:25.295448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass>
21077 10:09:25.295919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass
21079 10:09:25.326799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
21080 10:09:25.327194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
21082 10:09:25.358219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
21083 10:09:25.358677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
21085 10:09:25.389190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
21087 10:09:25.389644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
21088 10:09:25.420920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass
21090 10:09:25.421371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass>
21091 10:09:25.452035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
21093 10:09:25.452579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
21094 10:09:25.482835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
21095 10:09:25.483265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
21097 10:09:25.514016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
21098 10:09:25.514455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
21100 10:09:25.544287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass>
21101 10:09:25.544679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass
21103 10:09:25.575825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
21104 10:09:25.576266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
21106 10:09:25.607951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
21107 10:09:25.608494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
21109 10:09:25.642940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
21111 10:09:25.643562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
21112 10:09:25.675008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass>
21113 10:09:25.675485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass
21115 10:09:25.706247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
21116 10:09:25.706702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
21118 10:09:25.736997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
21120 10:09:25.737491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
21121 10:09:25.768491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
21122 10:09:25.768852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
21124 10:09:25.799087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass
21126 10:09:25.799624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass>
21127 10:09:25.830614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
21128 10:09:25.831006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
21130 10:09:25.865113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
21132 10:09:25.865550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
21133 10:09:25.896582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
21134 10:09:25.896940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
21136 10:09:25.934705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass
21138 10:09:25.935214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass>
21139 10:09:25.983791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
21140 10:09:25.984260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
21142 10:09:26.014514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
21143 10:09:26.014907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
21145 10:09:26.044947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
21146 10:09:26.045299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
21148 10:09:26.075515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass>
21149 10:09:26.075873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass
21151 10:09:26.106000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
21152 10:09:26.106364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
21154 10:09:26.139124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
21155 10:09:26.139576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
21157 10:09:26.170277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
21159 10:09:26.170830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
21160 10:09:26.202048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass>
21161 10:09:26.202437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass
21163 10:09:26.232526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
21164 10:09:26.232976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
21166 10:09:26.263363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
21167 10:09:26.263811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
21169 10:09:26.294426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
21171 10:09:26.294963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
21172 10:09:26.324966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass
21174 10:09:26.325421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass>
21175 10:09:26.356063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
21176 10:09:26.356506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
21178 10:09:26.386793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
21180 10:09:26.387378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
21181 10:09:26.417717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
21182 10:09:26.418168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
21184 10:09:26.448918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass>
21185 10:09:26.449366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass
21187 10:09:26.479791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
21188 10:09:26.480228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
21190 10:09:26.510712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
21191 10:09:26.511124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
21193 10:09:26.542236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
21194 10:09:26.542607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
21196 10:09:26.572265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass>
21197 10:09:26.572628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass
21199 10:09:26.604937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
21200 10:09:26.605239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
21202 10:09:26.638286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
21203 10:09:26.638592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
21205 10:09:26.670330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
21206 10:09:26.670699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
21208 10:09:26.702960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass
21210 10:09:26.703383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass>
21211 10:09:26.736040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
21212 10:09:26.736391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
21214 10:09:26.769246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
21216 10:09:26.769686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
21217 10:09:26.804395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
21218 10:09:26.804780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
21220 10:09:26.834983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass>
21221 10:09:26.835265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass
21223 10:09:26.865809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
21224 10:09:26.866086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
21226 10:09:26.896189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
21227 10:09:26.896537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
21229 10:09:26.926397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
21230 10:09:26.926761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
21232 10:09:26.957089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass
21234 10:09:26.957515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass>
21235 10:09:26.987706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
21236 10:09:26.988048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
21238 10:09:27.018340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
21239 10:09:27.018704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
21241 10:09:27.048843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
21242 10:09:27.049294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
21244 10:09:27.079694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass
21246 10:09:27.080225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass>
21247 10:09:27.110554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
21248 10:09:27.110987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
21250 10:09:27.141760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
21251 10:09:27.142193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
21253 10:09:27.172630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
21254 10:09:27.173066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
21256 10:09:27.203975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass
21258 10:09:27.204513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass>
21259 10:09:27.234578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
21260 10:09:27.234974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
21262 10:09:27.265882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
21263 10:09:27.266271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
21265 10:09:27.296439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
21266 10:09:27.296783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
21268 10:09:27.326607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass>
21269 10:09:27.326959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass
21271 10:09:27.357493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
21273 10:09:27.358091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
21274 10:09:27.388602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
21275 10:09:27.388950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
21277 10:09:27.419541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
21278 10:09:27.419883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
21280 10:09:27.450822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass>
21281 10:09:27.451140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass
21283 10:09:27.481435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
21285 10:09:27.481873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
21286 10:09:27.512184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
21288 10:09:27.512606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
21289 10:09:27.542645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
21290 10:09:27.542992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
21292 10:09:27.573506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass
21294 10:09:27.574059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass>
21295 10:09:27.604219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
21296 10:09:27.604669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
21298 10:09:27.635770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
21299 10:09:27.636228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
21301 10:09:27.667105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
21302 10:09:27.667569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
21304 10:09:27.698376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass>
21305 10:09:27.698780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass
21307 10:09:27.729013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
21308 10:09:27.729457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
21310 10:09:27.760339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
21311 10:09:27.760772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
21313 10:09:27.792236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
21314 10:09:27.792676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
21316 10:09:27.823152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass>
21317 10:09:27.823580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass
21319 10:09:27.855726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
21320 10:09:27.856177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
21322 10:09:27.889446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
21324 10:09:27.889901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
21325 10:09:27.922770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
21326 10:09:27.923247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
21328 10:09:27.955225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass>
21329 10:09:27.955609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass
21331 10:09:27.987160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
21333 10:09:27.987427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
21334 10:09:28.026187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
21335 10:09:28.026553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
21337 10:09:28.062075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
21338 10:09:28.062445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
21340 10:09:28.096369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass
21342 10:09:28.096725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass>
21343 10:09:28.131720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
21344 10:09:28.132184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
21346 10:09:28.165841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
21347 10:09:28.166252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
21349 10:09:28.196913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
21351 10:09:28.197235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
21352 10:09:28.231264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass>
21353 10:09:28.231659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass
21355 10:09:28.261959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
21356 10:09:28.262322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
21358 10:09:28.293015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
21359 10:09:28.293376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
21361 10:09:28.324061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
21363 10:09:28.324617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
21364 10:09:28.355204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass>
21365 10:09:28.355602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass
21367 10:09:28.387339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
21368 10:09:28.387826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
21370 10:09:28.419052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
21371 10:09:28.419511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
21373 10:09:28.450134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
21374 10:09:28.450600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
21376 10:09:28.481607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass>
21377 10:09:28.482086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass
21379 10:09:28.512604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
21381 10:09:28.513155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
21382 10:09:28.543395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
21384 10:09:28.543969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
21385 10:09:28.574098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
21386 10:09:28.574468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
21388 10:09:28.605199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass
21390 10:09:28.605706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass>
21391 10:09:28.636524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
21392 10:09:28.636803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
21394 10:09:28.667790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
21395 10:09:28.668067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
21397 10:09:28.699087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
21399 10:09:28.699563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
21400 10:09:28.731965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass
21402 10:09:28.732399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass>
21403 10:09:28.765870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
21404 10:09:28.766145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
21406 10:09:28.799418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
21407 10:09:28.799693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
21409 10:09:28.834231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
21410 10:09:28.834679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
21412 10:09:28.867910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass
21414 10:09:28.868472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass>
21415 10:09:28.902121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
21416 10:09:28.902688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
21418 10:09:28.936195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
21419 10:09:28.936653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
21421 10:09:28.970589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
21422 10:09:28.971052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
21424 10:09:29.004773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass>
21425 10:09:29.005117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass
21427 10:09:29.042167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
21428 10:09:29.042439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
21430 10:09:29.073499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
21432 10:09:29.074040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
21433 10:09:29.106584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
21434 10:09:29.107041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
21436 10:09:29.138368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass>
21437 10:09:29.138823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass
21439 10:09:29.170076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
21440 10:09:29.170447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
21442 10:09:29.202105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
21443 10:09:29.202347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
21445 10:09:29.232969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
21446 10:09:29.233414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
21448 10:09:29.264638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass>
21449 10:09:29.265087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass
21451 10:09:29.295479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
21453 10:09:29.296046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
21454 10:09:29.326867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
21456 10:09:29.327610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
21457 10:09:29.359485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
21458 10:09:29.359895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
21460 10:09:29.391304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass
21462 10:09:29.391729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass>
21463 10:09:29.422709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
21464 10:09:29.423117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
21466 10:09:29.454238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
21468 10:09:29.454809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
21469 10:09:29.484694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
21470 10:09:29.485094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
21472 10:09:29.517866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass
21474 10:09:29.518238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass>
21475 10:09:29.551001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
21477 10:09:29.551376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
21478 10:09:29.582582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
21479 10:09:29.582843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
21481 10:09:29.614216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
21482 10:09:29.614661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
21484 10:09:29.645423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass
21486 10:09:29.646053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass>
21487 10:09:29.677795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
21488 10:09:29.678264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
21490 10:09:29.709974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
21491 10:09:29.710433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
21493 10:09:29.740896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
21494 10:09:29.741295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
21496 10:09:29.771271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass>
21497 10:09:29.771552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass
21499 10:09:29.802010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
21500 10:09:29.802461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
21502 10:09:29.832862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
21503 10:09:29.833306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
21505 10:09:29.864735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
21506 10:09:29.865203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
21508 10:09:29.896068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass>
21509 10:09:29.896528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass
21511 10:09:29.929086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
21513 10:09:29.929420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
21514 10:09:29.959427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
21515 10:09:29.959702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
21517 10:09:29.990215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
21518 10:09:29.990567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
21520 10:09:30.021066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass
21522 10:09:30.021590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass>
21523 10:09:30.052468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
21524 10:09:30.052837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
21526 10:09:30.082896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
21527 10:09:30.083372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
21529 10:09:30.114090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
21531 10:09:30.114705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
21532 10:09:30.144564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass>
21533 10:09:30.145020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass
21535 10:09:30.176001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
21536 10:09:30.176461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
21538 10:09:30.207037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
21539 10:09:30.207495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
21541 10:09:30.238311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
21542 10:09:30.238751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
21544 10:09:30.269661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass>
21545 10:09:30.270041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass
21547 10:09:30.300062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
21549 10:09:30.300601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
21550 10:09:30.330991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
21551 10:09:30.331307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
21553 10:09:30.361224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
21555 10:09:30.361495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
21556 10:09:30.392103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass>
21557 10:09:30.392451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass
21559 10:09:30.423025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
21560 10:09:30.423377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
21562 10:09:30.453828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
21563 10:09:30.454175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
21565 10:09:30.484598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
21566 10:09:30.484873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
21568 10:09:30.515939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass
21570 10:09:30.516216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass>
21571 10:09:30.546754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
21572 10:09:30.547027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
21574 10:09:30.577136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
21575 10:09:30.577573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
21577 10:09:30.608024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
21578 10:09:30.608485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
21580 10:09:30.640814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass
21582 10:09:30.641271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass>
21583 10:09:30.672025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
21584 10:09:30.672470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
21586 10:09:30.703398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
21588 10:09:30.703939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
21589 10:09:30.734180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
21590 10:09:30.734631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
21592 10:09:30.765325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
21593 10:09:30.765866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
21595 10:09:30.797546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass
21597 10:09:30.798097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass>
21598 10:09:30.828327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
21599 10:09:30.828670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
21601 10:09:30.859415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
21603 10:09:30.859860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
21604 10:09:30.890603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass
21606 10:09:30.891033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass>
21607 10:09:30.926319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass>
21608 10:09:30.926697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass
21610 10:09:30.957846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass>
21611 10:09:30.958258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass
21613 10:09:30.988996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass>
21614 10:09:30.989341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass
21616 10:09:31.019583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass
21618 10:09:31.020010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass>
21619 10:09:31.063586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass>
21620 10:09:31.063987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass
21622 10:09:31.112519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass
21624 10:09:31.113177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass>
21625 10:09:31.144597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass
21627 10:09:31.145189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass>
21628 10:09:31.178681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass
21630 10:09:31.179126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass>
21631 10:09:31.209937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip
21633 10:09:31.210446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip>
21634 10:09:31.240823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip
21636 10:09:31.241257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip>
21637 10:09:31.271431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip>
21638 10:09:31.271883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip
21640 10:09:31.302917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass>
21641 10:09:31.303285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass
21643 10:09:31.333684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass>
21644 10:09:31.333960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass
21646 10:09:31.365060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass
21648 10:09:31.365552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass>
21649 10:09:31.396494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass>
21650 10:09:31.396901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass
21652 10:09:31.427464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass>
21653 10:09:31.427918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass
21655 10:09:31.458279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip>
21656 10:09:31.458742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip
21658 10:09:31.488982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip>
21659 10:09:31.489423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip
21661 10:09:31.519874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip>
21662 10:09:31.520286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip
21664 10:09:31.550484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass
21666 10:09:31.550948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass>
21667 10:09:31.580521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip>
21668 10:09:31.580879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip
21670 10:09:31.610981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip>
21671 10:09:31.611434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip
21673 10:09:31.644087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip>
21674 10:09:31.644551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip
21676 10:09:31.675647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass
21678 10:09:31.676221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass>
21679 10:09:31.708148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip
21681 10:09:31.708597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip>
21682 10:09:31.740485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip
21684 10:09:31.740932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip>
21685 10:09:31.771883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip>
21686 10:09:31.772307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip
21688 10:09:31.803308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass>
21689 10:09:31.803767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass
21691 10:09:31.836859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass>
21692 10:09:31.837310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass
21694 10:09:31.867505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass>
21695 10:09:31.867953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass
21697 10:09:31.902418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass
21699 10:09:31.902845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass>
21700 10:09:31.933352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass
21702 10:09:31.933813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass>
21703 10:09:31.963701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip>
21704 10:09:31.964137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip
21706 10:09:31.994463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip>
21707 10:09:31.994814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip
21709 10:09:32.024526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip>
21710 10:09:32.024881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip
21712 10:09:32.056612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass
21714 10:09:32.057175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass>
21715 10:09:32.088104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip>
21716 10:09:32.088408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip
21718 10:09:32.120688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip>
21719 10:09:32.121032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip
21721 10:09:32.155852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip
21723 10:09:32.156203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip>
21724 10:09:32.190220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass
21726 10:09:32.190772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass>
21727 10:09:32.222026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip
21729 10:09:32.222472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip>
21730 10:09:32.254666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip>
21731 10:09:32.255078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip
21733 10:09:32.286938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip>
21734 10:09:32.287349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip
21736 10:09:32.320828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass>
21737 10:09:32.321254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass
21739 10:09:32.353894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip>
21740 10:09:32.354381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip
21742 10:09:32.385524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip
21744 10:09:32.386044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip>
21745 10:09:32.419032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip>
21746 10:09:32.419422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip
21748 10:09:32.451593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass
21750 10:09:32.452159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass>
21751 10:09:32.488597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip>
21752 10:09:32.489015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip
21754 10:09:32.526396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip>
21755 10:09:32.526830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip
21757 10:09:32.563363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip>
21758 10:09:32.563740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip
21760 10:09:32.596848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass>
21761 10:09:32.597313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass
21763 10:09:32.630385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip>
21764 10:09:32.630794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip
21766 10:09:32.664676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip>
21767 10:09:32.665161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip
21769 10:09:32.700399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip
21771 10:09:32.700988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip>
21772 10:09:32.734519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass
21774 10:09:32.735088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass>
21775 10:09:32.767079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip>
21776 10:09:32.767495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip
21778 10:09:32.802167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip>
21779 10:09:32.802562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip
21781 10:09:32.834432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip>
21782 10:09:32.834848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip
21784 10:09:32.867321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass>
21785 10:09:32.867756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass
21787 10:09:32.900186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass>
21788 10:09:32.900668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass
21790 10:09:32.932557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass>
21791 10:09:32.933038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass
21793 10:09:32.967131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass>
21794 10:09:32.967594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass
21796 10:09:33.000408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass
21798 10:09:33.000874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass>
21799 10:09:33.036522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
21800 10:09:33.036931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
21802 10:09:33.068835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
21803 10:09:33.069306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
21805 10:09:33.101012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
21806 10:09:33.101491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
21808 10:09:33.133805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass>
21809 10:09:33.134151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass
21811 10:09:33.166787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
21812 10:09:33.167138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
21814 10:09:33.198545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
21815 10:09:33.198901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
21817 10:09:33.230884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
21818 10:09:33.231240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
21820 10:09:33.262859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass>
21821 10:09:33.263199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass
21823 10:09:33.294891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
21825 10:09:33.295325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
21826 10:09:33.330242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
21827 10:09:33.330708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
21829 10:09:33.365067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
21830 10:09:33.365484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
21832 10:09:33.398554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass
21834 10:09:33.399159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass>
21835 10:09:33.430786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
21836 10:09:33.431239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
21838 10:09:33.465870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
21839 10:09:33.466336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
21841 10:09:33.499115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
21842 10:09:33.499587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
21844 10:09:33.533675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass>
21845 10:09:33.534081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass
21847 10:09:33.566201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
21848 10:09:33.566466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
21850 10:09:33.607825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
21851 10:09:33.608184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
21853 10:09:33.640121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
21854 10:09:33.640477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
21856 10:09:33.672389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass
21858 10:09:33.672822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass>
21859 10:09:33.704988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
21860 10:09:33.705442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
21862 10:09:33.738085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
21863 10:09:33.738494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
21865 10:09:33.770206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
21866 10:09:33.770617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
21868 10:09:33.802047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass>
21869 10:09:33.802684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass
21871 10:09:33.838675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
21872 10:09:33.839128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
21874 10:09:33.870965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
21875 10:09:33.871313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
21877 10:09:33.903057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
21878 10:09:33.903423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
21880 10:09:33.934737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass
21882 10:09:33.935036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass>
21883 10:09:33.966363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
21884 10:09:33.966756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
21886 10:09:33.997841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
21887 10:09:33.998180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
21889 10:09:34.029998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
21890 10:09:34.030276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
21892 10:09:34.061514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass
21894 10:09:34.062032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass>
21895 10:09:34.094438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
21896 10:09:34.094892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
21898 10:09:34.131558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
21899 10:09:34.131971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
21901 10:09:34.164465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
21902 10:09:34.164889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
21904 10:09:34.196175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass
21906 10:09:34.196687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass>
21907 10:09:34.227510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
21909 10:09:34.227943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
21910 10:09:34.260454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
21911 10:09:34.260895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
21913 10:09:34.292177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
21914 10:09:34.292445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
21916 10:09:34.324910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass>
21917 10:09:34.325347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass
21919 10:09:34.364962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
21920 10:09:34.365547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
21922 10:09:34.400723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
21923 10:09:34.401010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
21925 10:09:34.434941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
21926 10:09:34.435223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
21928 10:09:34.469722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass
21930 10:09:34.470267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass>
21931 10:09:34.502808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
21932 10:09:34.503230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
21934 10:09:34.535246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
21935 10:09:34.535661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
21937 10:09:34.567943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
21938 10:09:34.568379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
21940 10:09:34.601074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass>
21941 10:09:34.601502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass
21943 10:09:34.634138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
21944 10:09:34.634562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
21946 10:09:34.666616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
21948 10:09:34.667177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
21949 10:09:34.699112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
21950 10:09:34.699559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
21952 10:09:34.732291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass
21954 10:09:34.732846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass>
21955 10:09:34.764685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
21956 10:09:34.765161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
21958 10:09:34.797448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
21960 10:09:34.798008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
21961 10:09:34.830066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
21962 10:09:34.830517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
21964 10:09:34.863576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass
21966 10:09:34.864023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass>
21967 10:09:34.895573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
21968 10:09:34.896046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
21970 10:09:34.927951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
21971 10:09:34.928420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
21973 10:09:34.962612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
21974 10:09:34.963066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
21976 10:09:35.006121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass
21978 10:09:35.006797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass>
21979 10:09:35.040703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
21980 10:09:35.041179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
21982 10:09:35.074804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
21983 10:09:35.075217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
21985 10:09:35.108111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
21986 10:09:35.108521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
21988 10:09:35.139882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass>
21989 10:09:35.140285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass
21991 10:09:35.171337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
21992 10:09:35.171819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
21994 10:09:35.204512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
21995 10:09:35.204974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
21997 10:09:35.236403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
21998 10:09:35.236695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
22000 10:09:35.268110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass
22002 10:09:35.268408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass>
22003 10:09:35.299175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
22004 10:09:35.299524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
22006 10:09:35.330608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
22007 10:09:35.330982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
22009 10:09:35.362008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
22010 10:09:35.362373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
22012 10:09:35.392815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass
22014 10:09:35.393307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass>
22015 10:09:35.425358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
22017 10:09:35.425691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
22018 10:09:35.456565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
22019 10:09:35.456932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
22021 10:09:35.487622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
22022 10:09:35.487903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
22024 10:09:35.519963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass
22026 10:09:35.520516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass>
22027 10:09:35.551332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
22028 10:09:35.551734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
22030 10:09:35.582830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
22031 10:09:35.583237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
22033 10:09:35.616946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
22034 10:09:35.617334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
22036 10:09:35.650823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass>
22037 10:09:35.651111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass
22039 10:09:35.687071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
22040 10:09:35.687453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
22042 10:09:35.723441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
22043 10:09:35.723737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
22045 10:09:35.760522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
22046 10:09:35.760804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
22048 10:09:35.798477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass
22050 10:09:35.798900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass>
22051 10:09:35.831436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
22052 10:09:35.831911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
22054 10:09:35.864313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
22055 10:09:35.864784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
22057 10:09:35.896917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
22058 10:09:35.897415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
22060 10:09:35.929690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass>
22061 10:09:35.930017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass
22063 10:09:35.962498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
22064 10:09:35.962781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
22066 10:09:35.995549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
22067 10:09:35.995914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
22069 10:09:36.027996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
22070 10:09:36.028276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
22072 10:09:36.060734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass>
22073 10:09:36.061086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass
22075 10:09:36.093845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
22077 10:09:36.094269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
22078 10:09:36.126370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
22080 10:09:36.126791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
22081 10:09:36.159380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
22083 10:09:36.159675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
22084 10:09:36.224830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass
22086 10:09:36.225114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass>
22087 10:09:36.259421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
22088 10:09:36.259831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
22090 10:09:36.293320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
22092 10:09:36.293818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
22093 10:09:36.325899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
22094 10:09:36.326318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
22096 10:09:36.359712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass>
22097 10:09:36.360116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass
22099 10:09:36.394130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
22101 10:09:36.394604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
22102 10:09:36.426735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
22103 10:09:36.427092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
22105 10:09:36.458928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
22106 10:09:36.459274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
22108 10:09:36.494347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass
22110 10:09:36.494930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass>
22111 10:09:36.526532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
22112 10:09:36.526903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
22114 10:09:36.558906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
22115 10:09:36.559271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
22117 10:09:36.591715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
22119 10:09:36.592000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
22120 10:09:36.627459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass>
22121 10:09:36.627954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass
22123 10:09:36.666254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
22124 10:09:36.666695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
22126 10:09:36.704356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
22127 10:09:36.704750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
22129 10:09:36.739978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
22130 10:09:36.740450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
22132 10:09:36.774398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass
22134 10:09:36.774859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass>
22135 10:09:36.811450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
22137 10:09:36.811889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
22138 10:09:36.847485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
22139 10:09:36.847972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
22141 10:09:36.883964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
22142 10:09:36.884434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
22144 10:09:36.919013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass>
22145 10:09:36.919453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass
22147 10:09:36.953389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
22149 10:09:36.953824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
22150 10:09:36.985158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
22151 10:09:36.985563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
22153 10:09:37.017631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
22154 10:09:37.018034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
22156 10:09:37.048761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass
22158 10:09:37.049399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass>
22159 10:09:37.080089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
22160 10:09:37.080451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
22162 10:09:37.111889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
22163 10:09:37.112238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
22165 10:09:37.146901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
22166 10:09:37.147422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
22168 10:09:37.182401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass
22170 10:09:37.182907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass>
22171 10:09:37.218426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
22172 10:09:37.218702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
22174 10:09:37.254902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
22175 10:09:37.255176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
22177 10:09:37.292337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
22179 10:09:37.292634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
22180 10:09:37.328689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass>
22181 10:09:37.329110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass
22183 10:09:37.365934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
22184 10:09:37.366342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
22186 10:09:37.402137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
22187 10:09:37.402534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
22189 10:09:37.437424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
22191 10:09:37.438014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
22192 10:09:37.472183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass
22194 10:09:37.472630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass>
22195 10:09:37.506561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
22196 10:09:37.506995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
22198 10:09:37.540616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
22200 10:09:37.541175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
22201 10:09:37.572871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
22203 10:09:37.573411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
22204 10:09:37.604803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass>
22205 10:09:37.605218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass
22207 10:09:37.636983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
22208 10:09:37.637391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
22210 10:09:37.669817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
22211 10:09:37.670230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
22213 10:09:37.701476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
22215 10:09:37.701913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
22216 10:09:37.742974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass>
22217 10:09:37.743418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass
22219 10:09:37.778061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
22220 10:09:37.778495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
22222 10:09:37.815570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
22224 10:09:37.816007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
22225 10:09:37.850219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
22226 10:09:37.850635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
22228 10:09:37.886227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass>
22229 10:09:37.886686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass
22231 10:09:37.922819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
22232 10:09:37.923249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
22234 10:09:37.958998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
22235 10:09:37.959464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
22237 10:09:37.994673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
22238 10:09:37.995140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
22240 10:09:38.030095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass
22242 10:09:38.030706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass>
22243 10:09:38.064868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
22245 10:09:38.065400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
22246 10:09:38.099393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
22247 10:09:38.099860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
22249 10:09:38.134414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
22250 10:09:38.134871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
22252 10:09:38.169431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass
22254 10:09:38.169999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass>
22255 10:09:38.203960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
22256 10:09:38.204330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
22258 10:09:38.239112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
22259 10:09:38.239467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
22261 10:09:38.274386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
22262 10:09:38.274731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
22264 10:09:38.309351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass
22266 10:09:38.309840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass>
22267 10:09:38.343261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
22269 10:09:38.343772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
22270 10:09:38.378366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
22271 10:09:38.378839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
22273 10:09:38.414440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
22275 10:09:38.414849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
22276 10:09:38.448823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass>
22277 10:09:38.449139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass
22279 10:09:38.483617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
22280 10:09:38.483926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
22282 10:09:38.519473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
22284 10:09:38.519948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
22285 10:09:38.555961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
22286 10:09:38.556365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
22288 10:09:38.591891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass>
22289 10:09:38.592266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass
22291 10:09:38.627378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
22292 10:09:38.627785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
22294 10:09:38.662950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
22295 10:09:38.663381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
22297 10:09:38.700406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
22299 10:09:38.700875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
22300 10:09:38.738878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass
22302 10:09:38.739318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass>
22303 10:09:38.775125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
22304 10:09:38.775509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
22306 10:09:38.810940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
22307 10:09:38.811334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
22309 10:09:38.846611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
22310 10:09:38.847024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
22312 10:09:38.883057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass>
22313 10:09:38.883499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass
22315 10:09:38.918604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
22316 10:09:38.919075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
22318 10:09:38.954157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
22319 10:09:38.954624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
22321 10:09:38.990416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
22323 10:09:38.990846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
22324 10:09:39.028269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass>
22325 10:09:39.028637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass
22327 10:09:39.067235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
22329 10:09:39.067808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
22330 10:09:39.102576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
22331 10:09:39.102994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
22333 10:09:39.138862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
22334 10:09:39.139275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
22336 10:09:39.175276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass>
22337 10:09:39.175713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass
22339 10:09:39.211072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
22341 10:09:39.211527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
22342 10:09:39.246537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
22343 10:09:39.246906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
22345 10:09:39.278587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
22346 10:09:39.279028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
22348 10:09:39.311328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass>
22349 10:09:39.311783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass
22351 10:09:39.343232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
22352 10:09:39.343690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
22354 10:09:39.378052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
22355 10:09:39.378504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
22357 10:09:39.411683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
22358 10:09:39.412142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
22360 10:09:39.444094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass>
22361 10:09:39.444548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass
22363 10:09:39.475420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
22364 10:09:39.475871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
22366 10:09:39.509941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
22367 10:09:39.510384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
22369 10:09:39.542086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
22370 10:09:39.542492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
22372 10:09:39.574531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass>
22373 10:09:39.574825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass
22375 10:09:39.606601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
22376 10:09:39.606960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
22378 10:09:39.640601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
22379 10:09:39.641047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
22381 10:09:39.674235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
22382 10:09:39.674688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
22384 10:09:39.705521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass
22386 10:09:39.705980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass>
22387 10:09:39.738609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
22388 10:09:39.739080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
22390 10:09:39.771995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
22391 10:09:39.772441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
22393 10:09:39.806149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
22394 10:09:39.806613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
22396 10:09:39.837965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass>
22397 10:09:39.838440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass
22399 10:09:39.869766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
22400 10:09:39.870213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
22402 10:09:39.903278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
22403 10:09:39.903725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
22405 10:09:39.935749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
22406 10:09:39.936217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
22408 10:09:39.972337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass>
22409 10:09:39.972795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass
22411 10:09:40.005406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
22413 10:09:40.005964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
22414 10:09:40.037382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
22416 10:09:40.037930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
22417 10:09:40.070591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
22419 10:09:40.071143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
22420 10:09:40.102912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass
22422 10:09:40.103473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass>
22423 10:09:40.138387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
22425 10:09:40.138838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
22426 10:09:40.174468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
22427 10:09:40.174957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
22429 10:09:40.211970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
22431 10:09:40.212451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
22432 10:09:40.249706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass>
22433 10:09:40.250085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass
22435 10:09:40.284942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
22437 10:09:40.285308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
22438 10:09:40.322665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
22439 10:09:40.323048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
22441 10:09:40.359421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
22442 10:09:40.359804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
22444 10:09:40.394651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass>
22445 10:09:40.395085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass
22447 10:09:40.430456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
22448 10:09:40.430823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
22450 10:09:40.462875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
22451 10:09:40.463350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
22453 10:09:40.495740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
22455 10:09:40.496192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
22456 10:09:40.529204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass
22458 10:09:40.529678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass>
22459 10:09:40.561397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
22461 10:09:40.562009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
22462 10:09:40.594724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
22463 10:09:40.595180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
22465 10:09:40.628518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
22466 10:09:40.628919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
22468 10:09:40.662221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass>
22469 10:09:40.662638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass
22471 10:09:40.696242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
22473 10:09:40.696801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
22474 10:09:40.728694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
22476 10:09:40.729448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
22477 10:09:40.762193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
22478 10:09:40.762607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
22480 10:09:40.794847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass
22482 10:09:40.795280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass>
22483 10:09:40.826807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
22484 10:09:40.827197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
22486 10:09:40.860191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
22487 10:09:40.860669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
22489 10:09:40.892287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
22491 10:09:40.892742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
22492 10:09:40.923556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass>
22493 10:09:40.924066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass
22495 10:09:40.956164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
22497 10:09:40.956716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
22498 10:09:40.990685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
22499 10:09:40.991162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
22501 10:09:41.022142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
22503 10:09:41.022761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
22504 10:09:41.054711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass
22506 10:09:41.055258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass>
22507 10:09:41.087539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
22508 10:09:41.087997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
22510 10:09:41.119025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
22511 10:09:41.119476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
22513 10:09:41.163202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
22515 10:09:41.163752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
22516 10:09:41.197874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass>
22517 10:09:41.198345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass
22519 10:09:41.234305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
22521 10:09:41.234792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
22522 10:09:41.271471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
22523 10:09:41.271931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
22525 10:09:41.331309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
22526 10:09:41.331718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
22528 10:09:41.368609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass>
22529 10:09:41.369026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass
22531 10:09:41.406966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
22533 10:09:41.407415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
22534 10:09:41.442174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
22536 10:09:41.442817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
22537 10:09:41.473401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
22539 10:09:41.473912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
22540 10:09:41.506891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass
22542 10:09:41.507341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass>
22543 10:09:41.539308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
22545 10:09:41.539776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
22546 10:09:41.571299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
22548 10:09:41.571762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
22549 10:09:41.602507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
22550 10:09:41.602909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
22552 10:09:41.633790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass>
22553 10:09:41.634279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass
22555 10:09:41.667981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
22556 10:09:41.668468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
22558 10:09:41.701274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
22560 10:09:41.701858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
22561 10:09:41.735930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
22563 10:09:41.736455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
22564 10:09:41.770047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass
22566 10:09:41.770582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass>
22567 10:09:41.803855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
22569 10:09:41.804380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
22570 10:09:41.836425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
22571 10:09:41.836842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
22573 10:09:41.868117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
22574 10:09:41.868519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
22576 10:09:41.901473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass
22578 10:09:41.902023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass>
22579 10:09:41.932440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
22580 10:09:41.932832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
22582 10:09:41.963896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
22583 10:09:41.964247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
22585 10:09:41.994474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
22586 10:09:41.994840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
22588 10:09:42.026819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass>
22589 10:09:42.027177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass
22591 10:09:42.059058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
22592 10:09:42.059414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
22594 10:09:42.090095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
22595 10:09:42.090507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
22597 10:09:42.120607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
22598 10:09:42.120956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
22600 10:09:42.153291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass
22602 10:09:42.153735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass>
22603 10:09:42.186290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
22604 10:09:42.186632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
22606 10:09:42.218450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
22607 10:09:42.218795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
22609 10:09:42.250426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
22611 10:09:42.250994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
22612 10:09:42.282461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass
22614 10:09:42.283087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass>
22615 10:09:42.314827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
22616 10:09:42.315302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
22618 10:09:42.347272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
22620 10:09:42.347888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
22621 10:09:42.380333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
22622 10:09:42.380807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
22624 10:09:42.414032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass
22626 10:09:42.414660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass>
22627 10:09:42.445414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
22629 10:09:42.446088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
22630 10:09:42.477771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
22631 10:09:42.478183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
22633 10:09:42.510417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
22635 10:09:42.510985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
22636 10:09:42.544243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass
22638 10:09:42.544992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass>
22639 10:09:42.577091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
22640 10:09:42.577569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
22642 10:09:42.610626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
22644 10:09:42.611200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
22645 10:09:42.644639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
22646 10:09:42.645107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
22648 10:09:42.676249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass>
22649 10:09:42.676727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass
22651 10:09:42.711612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
22652 10:09:42.712155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
22654 10:09:42.746392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
22655 10:09:42.746942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
22657 10:09:42.781518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
22659 10:09:42.782058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
22660 10:09:42.814642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass>
22661 10:09:42.815066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass
22663 10:09:42.847479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
22664 10:09:42.847931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
22666 10:09:42.879963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
22668 10:09:42.880395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
22669 10:09:42.912569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
22670 10:09:42.913070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
22672 10:09:42.944979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass>
22673 10:09:42.945459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass
22675 10:09:42.977219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
22677 10:09:42.977711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
22678 10:09:43.011918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
22679 10:09:43.012321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
22681 10:09:43.043046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
22682 10:09:43.043432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
22684 10:09:43.073842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass
22686 10:09:43.074156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass>
22687 10:09:43.104533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
22688 10:09:43.104874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
22690 10:09:43.135505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
22691 10:09:43.135848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
22693 10:09:43.166236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
22694 10:09:43.166617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
22696 10:09:43.198352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass
22698 10:09:43.198875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass>
22699 10:09:43.229232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
22701 10:09:43.229869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
22702 10:09:43.260554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
22703 10:09:43.261003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
22705 10:09:43.291594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
22707 10:09:43.292157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
22708 10:09:43.322281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass>
22709 10:09:43.322625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass
22711 10:09:43.354395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
22712 10:09:43.354676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
22714 10:09:43.385950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
22715 10:09:43.386402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
22717 10:09:43.418060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
22718 10:09:43.418492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
22720 10:09:43.450131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass
22722 10:09:43.450750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass>
22723 10:09:43.480607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
22724 10:09:43.481076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
22726 10:09:43.511850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
22728 10:09:43.512471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
22729 10:09:43.542879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
22730 10:09:43.543324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
22732 10:09:43.573780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass>
22733 10:09:43.574178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass
22735 10:09:43.605052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
22736 10:09:43.605457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
22738 10:09:43.637879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
22739 10:09:43.638290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
22741 10:09:43.670463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
22742 10:09:43.670925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
22744 10:09:43.706671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass>
22745 10:09:43.707143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass
22747 10:09:43.740040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
22749 10:09:43.740595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
22750 10:09:43.772527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
22751 10:09:43.772927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
22753 10:09:43.804407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
22754 10:09:43.804783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
22756 10:09:43.838151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass>
22757 10:09:43.838629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass
22759 10:09:43.880339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
22760 10:09:43.880828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
22762 10:09:43.914593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
22763 10:09:43.915077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
22765 10:09:43.946087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
22766 10:09:43.946555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
22768 10:09:43.977223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass
22770 10:09:43.977808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass>
22771 10:09:44.008486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
22773 10:09:44.008930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
22774 10:09:44.040848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
22775 10:09:44.041298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
22777 10:09:44.072793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
22779 10:09:44.073249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
22780 10:09:44.107889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass
22782 10:09:44.108335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass>
22783 10:09:44.140267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
22784 10:09:44.140717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
22786 10:09:44.173028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
22787 10:09:44.173515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
22789 10:09:44.206237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
22790 10:09:44.206677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
22792 10:09:44.240261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass
22794 10:09:44.240843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass>
22795 10:09:44.272618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
22796 10:09:44.273064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
22798 10:09:44.303942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
22799 10:09:44.304355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
22801 10:09:44.337891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
22802 10:09:44.338356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
22804 10:09:44.368873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass>
22805 10:09:44.369229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass
22807 10:09:44.399751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
22808 10:09:44.400191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
22810 10:09:44.431386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
22812 10:09:44.431950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
22813 10:09:44.462446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
22814 10:09:44.462879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
22816 10:09:44.494366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass>
22817 10:09:44.494754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass
22819 10:09:44.525719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
22820 10:09:44.526121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
22822 10:09:44.556452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
22824 10:09:44.556991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
22825 10:09:44.588295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
22826 10:09:44.588674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
22828 10:09:44.619400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass
22830 10:09:44.619847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass>
22831 10:09:44.651036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
22833 10:09:44.651468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
22834 10:09:44.684482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
22835 10:09:44.684857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
22837 10:09:44.719865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
22838 10:09:44.720143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
22840 10:09:44.750528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass>
22841 10:09:44.750891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass
22843 10:09:44.781609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
22844 10:09:44.781975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
22846 10:09:44.812359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
22847 10:09:44.812720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
22849 10:09:44.843886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
22850 10:09:44.844249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
22852 10:09:44.874517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass
22854 10:09:44.874938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass>
22855 10:09:44.904896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
22856 10:09:44.905173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
22858 10:09:44.935850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
22859 10:09:44.936205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
22861 10:09:44.966821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
22862 10:09:44.967095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
22864 10:09:44.998022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass
22866 10:09:44.998499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass>
22867 10:09:45.028813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
22868 10:09:45.029195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
22870 10:09:45.060199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
22871 10:09:45.060479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
22873 10:09:45.091580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
22874 10:09:45.091929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
22876 10:09:45.122809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass>
22877 10:09:45.123153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass
22879 10:09:45.153396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
22881 10:09:45.153837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
22882 10:09:45.184834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
22883 10:09:45.185160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
22885 10:09:45.216108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
22887 10:09:45.216665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
22888 10:09:45.247625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass>
22889 10:09:45.248093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass
22891 10:09:45.279349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
22892 10:09:45.279801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
22894 10:09:45.310698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
22896 10:09:45.311245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
22897 10:09:45.341791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
22898 10:09:45.342231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
22900 10:09:45.372450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass>
22901 10:09:45.372881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass
22903 10:09:45.404216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
22905 10:09:45.404849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
22906 10:09:45.436716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
22908 10:09:45.437276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
22909 10:09:45.467572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
22910 10:09:45.467917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
22912 10:09:45.499111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass>
22913 10:09:45.499548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass
22915 10:09:45.531812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
22916 10:09:45.532276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
22918 10:09:45.563561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
22919 10:09:45.564002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
22921 10:09:45.596121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
22922 10:09:45.596609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
22924 10:09:45.628229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass>
22925 10:09:45.628691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass
22927 10:09:45.659992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
22928 10:09:45.660518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
22930 10:09:45.692722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
22931 10:09:45.693193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
22933 10:09:45.724835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
22934 10:09:45.725276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
22936 10:09:45.756518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass
22938 10:09:45.756964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass>
22939 10:09:45.788593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
22940 10:09:45.788983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
22942 10:09:45.820202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
22943 10:09:45.820478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
22945 10:09:45.852922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
22947 10:09:45.853301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
22948 10:09:45.884982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass
22950 10:09:45.885543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass>
22951 10:09:45.916212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
22952 10:09:45.916560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
22954 10:09:45.948761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
22955 10:09:45.949109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
22957 10:09:45.980051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
22958 10:09:45.980395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
22960 10:09:46.011455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass>
22961 10:09:46.011731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass
22963 10:09:46.042919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
22964 10:09:46.043194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
22966 10:09:46.074417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
22967 10:09:46.074692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
22969 10:09:46.106413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
22970 10:09:46.106689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
22972 10:09:46.138517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass
22974 10:09:46.138793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass>
22975 10:09:46.170199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
22976 10:09:46.170473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
22978 10:09:46.200973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
22979 10:09:46.201249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
22981 10:09:46.232478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
22982 10:09:46.232853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
22984 10:09:46.264448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass>
22985 10:09:46.264722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass
22987 10:09:46.297395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
22989 10:09:46.297919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
22990 10:09:46.328801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
22991 10:09:46.329171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
22993 10:09:46.360107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
22994 10:09:46.360478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
22996 10:09:46.390841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass>
22997 10:09:46.391212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass
22999 10:09:46.450277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
23000 10:09:46.450639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
23002 10:09:46.482498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
23003 10:09:46.482855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
23005 10:09:46.513295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
23007 10:09:46.513796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
23008 10:09:46.544834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass>
23009 10:09:46.545201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass
23011 10:09:46.576029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
23012 10:09:46.576395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
23014 10:09:46.606908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
23015 10:09:46.607273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
23017 10:09:46.640108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
23018 10:09:46.640476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
23020 10:09:46.672616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass>
23021 10:09:46.673166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass
23023 10:09:46.704098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
23024 10:09:46.704458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
23026 10:09:46.736397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
23027 10:09:46.736773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
23029 10:09:46.768271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
23030 10:09:46.768625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
23032 10:09:46.800622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass>
23033 10:09:46.800980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass
23035 10:09:46.833309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
23037 10:09:46.833611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
23038 10:09:46.865691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
23039 10:09:46.866054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
23041 10:09:46.896732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
23042 10:09:46.897076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
23044 10:09:46.927321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass>
23045 10:09:46.927764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass
23047 10:09:46.959549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
23048 10:09:46.959905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
23050 10:09:46.991300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
23052 10:09:46.991729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
23053 10:09:47.022066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
23054 10:09:47.022413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
23056 10:09:47.052148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass
23058 10:09:47.052572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass>
23059 10:09:47.082714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
23060 10:09:47.083073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
23062 10:09:47.113685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
23063 10:09:47.114041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
23065 10:09:47.146147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
23066 10:09:47.146546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
23068 10:09:47.177042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass>
23069 10:09:47.177391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass
23071 10:09:47.207424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
23072 10:09:47.207781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
23074 10:09:47.238441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
23075 10:09:47.238787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
23077 10:09:47.269697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
23078 10:09:47.270050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
23080 10:09:47.301931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass>
23081 10:09:47.302278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass
23083 10:09:47.333692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
23084 10:09:47.334023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
23086 10:09:47.364683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
23087 10:09:47.365028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
23089 10:09:47.395360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
23090 10:09:47.395717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
23092 10:09:47.426196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass>
23093 10:09:47.426549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass
23095 10:09:47.456705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
23096 10:09:47.457112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
23098 10:09:47.488942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
23099 10:09:47.489342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
23101 10:09:47.521311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
23103 10:09:47.521768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
23104 10:09:47.553452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass
23106 10:09:47.553981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass>
23107 10:09:47.584250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
23109 10:09:47.584673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
23110 10:09:47.615305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
23111 10:09:47.615651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
23113 10:09:47.646144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
23114 10:09:47.646495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
23116 10:09:47.678257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass
23118 10:09:47.678691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass>
23119 10:09:47.709434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
23121 10:09:47.709902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
23122 10:09:47.740751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
23123 10:09:47.741119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
23125 10:09:47.771439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
23126 10:09:47.771781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
23128 10:09:47.802354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass
23130 10:09:47.802989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass>
23131 10:09:47.834971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
23132 10:09:47.835418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
23134 10:09:47.869698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
23136 10:09:47.870383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
23137 10:09:47.902365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
23138 10:09:47.902799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
23140 10:09:47.932898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass>
23141 10:09:47.933250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass
23143 10:09:47.964682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
23144 10:09:47.965149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
23146 10:09:47.997703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
23147 10:09:47.998097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
23149 10:09:48.029525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
23151 10:09:48.030155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
23152 10:09:48.061411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass
23154 10:09:48.061860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass>
23155 10:09:48.092523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
23156 10:09:48.092918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
23158 10:09:48.123704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
23159 10:09:48.124095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
23161 10:09:48.159860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
23162 10:09:48.160228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
23164 10:09:48.192072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass>
23165 10:09:48.192454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass
23167 10:09:48.224009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
23168 10:09:48.224455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
23170 10:09:48.254894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
23171 10:09:48.255282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
23173 10:09:48.285670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
23174 10:09:48.286061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
23176 10:09:48.317382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass
23178 10:09:48.317896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass>
23179 10:09:48.351194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
23180 10:09:48.351448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
23182 10:09:48.383135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
23183 10:09:48.383548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
23185 10:09:48.414889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
23186 10:09:48.415231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
23188 10:09:48.446387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass>
23189 10:09:48.446828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass
23191 10:09:48.477735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
23193 10:09:48.478465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
23194 10:09:48.508774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
23196 10:09:48.509314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
23197 10:09:48.539880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
23198 10:09:48.540340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
23200 10:09:48.572008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass
23202 10:09:48.572529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass>
23203 10:09:48.602759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
23204 10:09:48.603119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
23206 10:09:48.634581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
23207 10:09:48.635024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
23209 10:09:48.665847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
23210 10:09:48.666244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
23212 10:09:48.700755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass>
23213 10:09:48.701167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass
23215 10:09:48.737983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
23216 10:09:48.738343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
23218 10:09:48.781979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
23219 10:09:48.782330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
23221 10:09:48.819881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
23223 10:09:48.820303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
23224 10:09:48.859393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass
23226 10:09:48.859824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass>
23227 10:09:48.897788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
23228 10:09:48.898153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
23230 10:09:48.940784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
23231 10:09:48.941246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
23233 10:09:48.979030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
23235 10:09:48.979475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
23236 10:09:49.010522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass
23238 10:09:49.010855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass>
23239 10:09:49.041929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
23240 10:09:49.042344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
23242 10:09:49.073712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
23243 10:09:49.074115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
23245 10:09:49.104980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
23246 10:09:49.105389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
23248 10:09:49.135931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass>
23249 10:09:49.136373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass
23251 10:09:49.167140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
23253 10:09:49.167731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
23254 10:09:49.199651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
23255 10:09:49.200058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
23257 10:09:49.233404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
23259 10:09:49.233697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
23260 10:09:49.266301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass
23262 10:09:49.266649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass>
23263 10:09:49.299342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
23264 10:09:49.299621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
23266 10:09:49.331461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
23267 10:09:49.331921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
23269 10:09:49.363024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
23270 10:09:49.363458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
23272 10:09:49.395531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass>
23273 10:09:49.395994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass
23275 10:09:49.427541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
23276 10:09:49.427991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
23278 10:09:49.459357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
23279 10:09:49.459832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
23281 10:09:49.490882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
23282 10:09:49.491435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
23284 10:09:49.523795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass
23286 10:09:49.524164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass>
23287 10:09:49.555045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
23288 10:09:49.555378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
23290 10:09:49.586326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
23291 10:09:49.586596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
23293 10:09:49.617758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
23294 10:09:49.618028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
23296 10:09:49.649731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass
23298 10:09:49.650050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass>
23299 10:09:49.683278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
23300 10:09:49.683652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
23302 10:09:49.714589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
23303 10:09:49.714983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
23305 10:09:49.746991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
23306 10:09:49.747393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
23308 10:09:49.779003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass>
23309 10:09:49.779428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass
23311 10:09:49.809998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
23312 10:09:49.810274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
23314 10:09:49.840972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
23315 10:09:49.841247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
23317 10:09:49.871765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
23318 10:09:49.872118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
23320 10:09:49.902273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass>
23321 10:09:49.902623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass
23323 10:09:49.932730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
23324 10:09:49.933098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
23326 10:09:49.963939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
23327 10:09:49.964350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
23329 10:09:49.996180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
23330 10:09:49.996532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
23332 10:09:50.027510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass>
23333 10:09:50.027856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass
23335 10:09:50.058472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
23336 10:09:50.058822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
23338 10:09:50.090100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
23339 10:09:50.090560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
23341 10:09:50.120836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
23342 10:09:50.121238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
23344 10:09:50.151826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass>
23345 10:09:50.152227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass
23347 10:09:50.182894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
23348 10:09:50.183352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
23350 10:09:50.214247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
23351 10:09:50.214690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
23353 10:09:50.245931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
23354 10:09:50.246330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
23356 10:09:50.277398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass
23358 10:09:50.277874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass>
23359 10:09:50.308332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
23360 10:09:50.308680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
23362 10:09:50.339156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
23363 10:09:50.339500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
23365 10:09:50.370249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
23366 10:09:50.370618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
23368 10:09:50.401805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass
23370 10:09:50.402229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass>
23371 10:09:50.435406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
23373 10:09:50.435966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
23374 10:09:50.468230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
23376 10:09:50.468833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
23377 10:09:50.500462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
23378 10:09:50.500935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
23380 10:09:50.533980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass
23382 10:09:50.534425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass>
23383 10:09:50.566824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
23385 10:09:50.567276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
23386 10:09:50.598528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
23388 10:09:50.599087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
23389 10:09:50.631872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
23391 10:09:50.632431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
23392 10:09:50.664193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass
23394 10:09:50.664743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass>
23395 10:09:50.698527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
23396 10:09:50.698929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
23398 10:09:50.730244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
23399 10:09:50.730708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
23401 10:09:50.761787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
23402 10:09:50.762257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
23404 10:09:50.793100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass>
23405 10:09:50.793563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass
23407 10:09:50.824465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
23408 10:09:50.824920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
23410 10:09:50.855932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
23411 10:09:50.856331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
23413 10:09:50.887333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
23414 10:09:50.887734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
23416 10:09:50.918580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass>
23417 10:09:50.919042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass
23419 10:09:50.951584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
23421 10:09:50.952029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
23422 10:09:50.984040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
23423 10:09:50.984448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
23425 10:09:51.016666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
23427 10:09:51.017242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
23428 10:09:51.048024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass>
23429 10:09:51.048417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass
23431 10:09:51.080129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
23432 10:09:51.080593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
23434 10:09:51.112074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
23435 10:09:51.112547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
23437 10:09:51.143867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
23438 10:09:51.144255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
23440 10:09:51.174876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass>
23441 10:09:51.175331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass
23443 10:09:51.206782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
23444 10:09:51.207229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
23446 10:09:51.238755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
23448 10:09:51.239305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
23449 10:09:51.270565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
23451 10:09:51.271136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
23452 10:09:51.303300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass>
23453 10:09:51.303763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass
23455 10:09:51.335702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
23456 10:09:51.336165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
23458 10:09:51.369831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
23459 10:09:51.370306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
23461 10:09:51.403419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
23463 10:09:51.403887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
23464 10:09:51.436685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass>
23465 10:09:51.436992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass
23467 10:09:51.468288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
23468 10:09:51.468600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
23470 10:09:51.499530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
23471 10:09:51.499894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
23473 10:09:51.546681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
23474 10:09:51.547034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
23476 10:09:51.585917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass
23478 10:09:51.586348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass>
23479 10:09:51.616652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
23480 10:09:51.617000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
23482 10:09:51.647593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
23483 10:09:51.647872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
23485 10:09:51.679374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
23487 10:09:51.679793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
23488 10:09:51.710910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass>
23489 10:09:51.711349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass
23491 10:09:51.743231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
23493 10:09:51.743728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
23494 10:09:51.775226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
23495 10:09:51.775634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
23497 10:09:51.808100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
23498 10:09:51.808468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
23500 10:09:51.842211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass>
23501 10:09:51.842615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass
23503 10:09:51.874757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
23504 10:09:51.875189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
23506 10:09:51.907779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
23508 10:09:51.908202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
23509 10:09:51.939711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
23511 10:09:51.940142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
23512 10:09:51.971818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass>
23513 10:09:51.972182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass
23515 10:09:52.005373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
23517 10:09:52.005852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
23518 10:09:52.039316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
23519 10:09:52.039774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
23521 10:09:52.071949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
23522 10:09:52.072466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
23524 10:09:52.103094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass>
23525 10:09:52.103535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass
23527 10:09:52.134471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
23528 10:09:52.134914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
23530 10:09:52.165729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
23531 10:09:52.166176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
23533 10:09:52.196785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
23534 10:09:52.197270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
23536 10:09:52.228038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass>
23537 10:09:52.228487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass
23539 10:09:52.259733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
23540 10:09:52.260196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
23542 10:09:52.291940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
23543 10:09:52.292401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
23545 10:09:52.323398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
23546 10:09:52.323807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
23548 10:09:52.355377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass>
23549 10:09:52.355831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass
23551 10:09:52.387787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
23552 10:09:52.388331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
23554 10:09:52.420767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
23555 10:09:52.421141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
23557 10:09:52.452114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
23558 10:09:52.452486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
23560 10:09:52.483638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass>
23561 10:09:52.484002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass
23563 10:09:52.514761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
23564 10:09:52.515124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
23566 10:09:52.545703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
23567 10:09:52.545998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
23569 10:09:52.577057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
23570 10:09:52.577415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
23572 10:09:52.607770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass>
23573 10:09:52.608057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass
23575 10:09:52.638527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
23576 10:09:52.638934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
23578 10:09:52.672815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
23579 10:09:52.673210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
23581 10:09:52.705021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
23582 10:09:52.705408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
23584 10:09:52.736729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass>
23585 10:09:52.737201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass
23587 10:09:52.767874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
23588 10:09:52.768339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
23590 10:09:52.799316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
23592 10:09:52.799929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
23593 10:09:52.830790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
23594 10:09:52.831191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
23596 10:09:52.862179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass>
23597 10:09:52.862574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass
23599 10:09:52.893326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
23601 10:09:52.893736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
23602 10:09:52.925690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
23603 10:09:52.926072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
23605 10:09:52.958035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
23606 10:09:52.958506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
23608 10:09:52.989779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass>
23609 10:09:52.990172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass
23611 10:09:53.020627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
23612 10:09:53.021001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
23614 10:09:53.051663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
23615 10:09:53.052047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
23617 10:09:53.083779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
23618 10:09:53.084259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
23620 10:09:53.114899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass>
23621 10:09:53.115257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass
23623 10:09:53.145638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
23624 10:09:53.146019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
23626 10:09:53.176174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
23627 10:09:53.176537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
23629 10:09:53.206881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
23630 10:09:53.207227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
23632 10:09:53.238037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass>
23633 10:09:53.238418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass
23635 10:09:53.268892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
23636 10:09:53.269352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
23638 10:09:53.300315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
23639 10:09:53.300773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
23641 10:09:53.331501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
23642 10:09:53.331949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
23644 10:09:53.362117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass>
23645 10:09:53.362464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass
23647 10:09:53.392833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
23648 10:09:53.393178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
23650 10:09:53.423970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
23651 10:09:53.424350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
23653 10:09:53.458801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
23654 10:09:53.459196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
23656 10:09:53.493613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass>
23657 10:09:53.494030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass
23659 10:09:53.525674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
23660 10:09:53.526145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
23662 10:09:53.559448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
23663 10:09:53.559935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
23665 10:09:53.592807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
23667 10:09:53.593157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
23668 10:09:53.624626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass>
23669 10:09:53.625005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass
23671 10:09:53.655974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
23672 10:09:53.656358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
23674 10:09:53.687446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
23675 10:09:53.687831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
23677 10:09:53.718973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
23678 10:09:53.719329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
23680 10:09:53.750559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass>
23681 10:09:53.750914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass
23683 10:09:53.781889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
23684 10:09:53.782247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
23686 10:09:53.812607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
23687 10:09:53.813071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
23689 10:09:53.843563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
23690 10:09:53.844106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
23692 10:09:53.875862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass
23694 10:09:53.876303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass>
23695 10:09:53.907116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
23696 10:09:53.907510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
23698 10:09:53.939244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
23699 10:09:53.939715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
23701 10:09:53.970501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
23702 10:09:53.970907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
23704 10:09:54.001098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass>
23705 10:09:54.001453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass
23707 10:09:54.032380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
23708 10:09:54.032823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
23710 10:09:54.068240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
23711 10:09:54.068706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
23713 10:09:54.103006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
23714 10:09:54.103380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
23716 10:09:54.134694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass>
23717 10:09:54.135129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass
23719 10:09:54.166704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
23721 10:09:54.167154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
23722 10:09:54.197792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
23723 10:09:54.198143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
23725 10:09:54.228574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
23726 10:09:54.228919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
23728 10:09:54.259645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass>
23729 10:09:54.259992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass
23731 10:09:54.290468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
23732 10:09:54.290839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
23734 10:09:54.321305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
23736 10:09:54.321637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
23737 10:09:54.352158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
23738 10:09:54.352512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
23740 10:09:54.382781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass>
23741 10:09:54.383124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass
23743 10:09:54.413446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
23745 10:09:54.413884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
23746 10:09:54.444275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
23747 10:09:54.444641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
23749 10:09:54.475505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
23751 10:09:54.475931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
23752 10:09:54.506653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass>
23753 10:09:54.506999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass
23755 10:09:54.541817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
23756 10:09:54.542289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
23758 10:09:54.575832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
23759 10:09:54.576200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
23761 10:09:54.608113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
23762 10:09:54.608479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
23764 10:09:54.639647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass
23766 10:09:54.640100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass>
23767 10:09:54.674665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
23769 10:09:54.675207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
23770 10:09:54.706140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
23771 10:09:54.706532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
23773 10:09:54.737371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
23775 10:09:54.737837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
23776 10:09:54.769034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass>
23777 10:09:54.769384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass
23779 10:09:54.800684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
23780 10:09:54.801034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
23782 10:09:54.831460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
23783 10:09:54.831805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
23785 10:09:54.862588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
23786 10:09:54.862985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
23788 10:09:54.894123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass>
23789 10:09:54.894519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass
23791 10:09:54.924821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
23792 10:09:54.925221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
23794 10:09:54.956960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
23795 10:09:54.957363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
23797 10:09:54.988665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
23798 10:09:54.989075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
23800 10:09:55.020214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass>
23801 10:09:55.020611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass
23803 10:09:55.051502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
23804 10:09:55.051901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
23806 10:09:55.083426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
23808 10:09:55.084055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
23809 10:09:55.115069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
23810 10:09:55.115465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
23812 10:09:55.146816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass>
23813 10:09:55.147314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass
23815 10:09:55.178172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
23816 10:09:55.178635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
23818 10:09:55.210798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
23819 10:09:55.211302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
23821 10:09:55.220662 <47>[ 229.894382] systemd-journald[109]: Sent WATCHDOG=1 notification.
23822 10:09:55.247903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
23823 10:09:55.248312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
23825 10:09:55.280227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass>
23826 10:09:55.280644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass
23828 10:09:55.312808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
23829 10:09:55.313217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
23831 10:09:55.346273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
23832 10:09:55.346649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
23834 10:09:55.380737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
23836 10:09:55.381282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
23837 10:09:55.416082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass>
23838 10:09:55.416514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass
23840 10:09:55.450114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
23842 10:09:55.450702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
23843 10:09:55.483495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
23844 10:09:55.483906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
23846 10:09:55.514997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
23847 10:09:55.515398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
23849 10:09:55.547054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass
23851 10:09:55.547671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass>
23852 10:09:55.578693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
23853 10:09:55.579089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
23855 10:09:55.610113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
23856 10:09:55.610504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
23858 10:09:55.643587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
23859 10:09:55.643997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
23861 10:09:55.675467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass>
23862 10:09:55.675901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass
23864 10:09:55.707005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
23865 10:09:55.707412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
23867 10:09:55.739137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
23868 10:09:55.739539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
23870 10:09:55.770426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
23871 10:09:55.770830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
23873 10:09:55.802282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass>
23874 10:09:55.802727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass
23876 10:09:55.833697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
23877 10:09:55.834138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
23879 10:09:55.864750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
23880 10:09:55.865185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
23882 10:09:55.895816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
23883 10:09:55.896255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
23885 10:09:55.927154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass
23887 10:09:55.927693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass>
23888 10:09:55.958371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
23889 10:09:55.958822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
23891 10:09:55.992412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
23892 10:09:55.992861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
23894 10:09:56.025067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
23895 10:09:56.025520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
23897 10:09:56.056999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass
23899 10:09:56.057430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass>
23900 10:09:56.088429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
23901 10:09:56.088823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
23903 10:09:56.120049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
23904 10:09:56.120438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
23906 10:09:56.151990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
23907 10:09:56.152381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
23909 10:09:56.183228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass>
23910 10:09:56.183665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass
23912 10:09:56.214698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
23913 10:09:56.215093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
23915 10:09:56.246585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
23916 10:09:56.246958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
23918 10:09:56.279303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
23919 10:09:56.279685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
23921 10:09:56.312867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass>
23922 10:09:56.313273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass
23924 10:09:56.347088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
23925 10:09:56.347622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
23927 10:09:56.379124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
23928 10:09:56.379526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
23930 10:09:56.410264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
23931 10:09:56.410653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
23933 10:09:56.441320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass
23935 10:09:56.441760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass>
23936 10:09:56.473836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
23937 10:09:56.474210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
23939 10:09:56.505949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
23940 10:09:56.506342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
23942 10:09:56.538356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
23944 10:09:56.538969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
23945 10:09:56.570493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass>
23946 10:09:56.570937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass
23948 10:09:56.602820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
23949 10:09:56.603331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
23951 10:09:56.634889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
23952 10:09:56.635339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
23954 10:09:56.700301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
23955 10:09:56.700771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
23957 10:09:56.734616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass>
23958 10:09:56.735085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass
23960 10:09:56.767113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
23962 10:09:56.767670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
23963 10:09:56.798855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
23964 10:09:56.799317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
23966 10:09:56.830638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
23968 10:09:56.831215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
23969 10:09:56.862608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass
23971 10:09:56.863034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass>
23972 10:09:56.894080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
23974 10:09:56.894668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
23975 10:09:56.926328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
23976 10:09:56.926734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
23978 10:09:56.959743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
23979 10:09:56.960135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
23981 10:09:56.992074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass
23983 10:09:56.992669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass>
23984 10:09:57.023604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
23985 10:09:57.024064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
23987 10:09:57.056143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
23988 10:09:57.056591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
23990 10:09:57.087922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
23991 10:09:57.088411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
23993 10:09:57.119221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass
23995 10:09:57.119810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass>
23996 10:09:57.151299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
23998 10:09:57.151884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
23999 10:09:57.183245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
24001 10:09:57.183836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
24002 10:09:57.215364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
24003 10:09:57.215757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
24005 10:09:57.247522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass>
24006 10:09:57.247915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass
24008 10:09:57.279234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
24009 10:09:57.279626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
24011 10:09:57.310977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
24012 10:09:57.311360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
24014 10:09:57.342662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
24015 10:09:57.343051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
24017 10:09:57.374607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass>
24018 10:09:57.374994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass
24020 10:09:57.407006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
24021 10:09:57.407460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
24023 10:09:57.438483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
24024 10:09:57.438893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
24026 10:09:57.470323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
24027 10:09:57.470723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
24029 10:09:57.502187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass
24031 10:09:57.502833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass>
24032 10:09:57.533800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
24033 10:09:57.534267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
24035 10:09:57.565172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
24036 10:09:57.565570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
24038 10:09:57.596647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
24039 10:09:57.597070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
24041 10:09:57.627988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass>
24042 10:09:57.628303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass
24044 10:09:57.658898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
24045 10:09:57.659279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
24047 10:09:57.690442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
24048 10:09:57.690812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
24050 10:09:57.722420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
24051 10:09:57.722798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
24053 10:09:57.753880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass>
24054 10:09:57.754252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass
24056 10:09:57.785443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
24058 10:09:57.785936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
24059 10:09:57.817002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
24060 10:09:57.817462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
24062 10:09:57.847974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
24064 10:09:57.848540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
24065 10:09:57.879691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass>
24066 10:09:57.880101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass
24068 10:09:57.911647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
24069 10:09:57.912013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
24071 10:09:57.943331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
24072 10:09:57.943722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
24074 10:09:57.975344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
24075 10:09:57.975782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
24077 10:09:58.006221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass>
24078 10:09:58.006653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass
24080 10:09:58.037705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
24082 10:09:58.038236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
24083 10:09:58.069026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
24084 10:09:58.069441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
24086 10:09:58.100282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
24087 10:09:58.100702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
24089 10:09:58.130933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass>
24090 10:09:58.131366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass
24092 10:09:58.162078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
24094 10:09:58.162536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
24095 10:09:58.193287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
24097 10:09:58.193768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
24098 10:09:58.224564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
24099 10:09:58.224970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
24101 10:09:58.255647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass>
24102 10:09:58.256060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass
24104 10:09:58.286986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
24106 10:09:58.287466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
24107 10:09:58.318666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
24109 10:09:58.319133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
24110 10:09:58.350258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
24111 10:09:58.350688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
24113 10:09:58.381278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass
24115 10:09:58.381772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass>
24116 10:09:58.412643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
24117 10:09:58.413040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
24119 10:09:58.443630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
24120 10:09:58.443948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
24122 10:09:58.475692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
24123 10:09:58.476024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
24125 10:09:58.507566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass
24127 10:09:58.508188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass>
24128 10:09:58.539998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
24130 10:09:58.540636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
24131 10:09:58.571253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
24132 10:09:58.571722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
24134 10:09:58.609615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
24136 10:09:58.610263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
24137 10:09:58.642206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass>
24138 10:09:58.642701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass
24140 10:09:58.673469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
24142 10:09:58.674131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
24143 10:09:58.705434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
24145 10:09:58.705867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
24146 10:09:58.737083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
24147 10:09:58.737545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
24149 10:09:58.767951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass
24151 10:09:58.768616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass>
24152 10:09:58.799398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
24153 10:09:58.799866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
24155 10:09:58.831210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
24156 10:09:58.831609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
24158 10:09:58.862457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
24159 10:09:58.862830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
24161 10:09:58.894882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass>
24162 10:09:58.895244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass
24164 10:09:58.926611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
24166 10:09:58.927114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
24167 10:09:58.957917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
24168 10:09:58.958362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
24170 10:09:58.989856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
24171 10:09:58.990254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
24173 10:09:59.020934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass>
24174 10:09:59.021350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass
24176 10:09:59.053727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
24177 10:09:59.054168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
24179 10:09:59.085272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
24181 10:09:59.085735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
24182 10:09:59.118445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
24184 10:09:59.119001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
24185 10:09:59.150190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass
24187 10:09:59.150742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass>
24188 10:09:59.181056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
24189 10:09:59.181477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
24191 10:09:59.213665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
24192 10:09:59.214015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
24194 10:09:59.246058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
24195 10:09:59.246523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
24197 10:09:59.277766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass
24199 10:09:59.278275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass>
24200 10:09:59.308319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
24201 10:09:59.308692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
24203 10:09:59.340111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
24204 10:09:59.340455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
24206 10:09:59.371276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
24207 10:09:59.371632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
24209 10:09:59.402235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass>
24210 10:09:59.402580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass
24212 10:09:59.435148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
24213 10:09:59.435586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
24215 10:09:59.466569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
24216 10:09:59.466921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
24218 10:09:59.500213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
24219 10:09:59.500647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
24221 10:09:59.535380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass>
24222 10:09:59.535727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass
24224 10:09:59.566359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
24225 10:09:59.566700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
24227 10:09:59.599132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
24229 10:09:59.599743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
24230 10:09:59.633461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
24232 10:09:59.634244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
24233 10:09:59.669144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass
24235 10:09:59.669610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass>
24236 10:09:59.704901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
24237 10:09:59.705327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
24239 10:09:59.742374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
24240 10:09:59.742846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
24242 10:09:59.778352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
24243 10:09:59.778767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
24245 10:09:59.813473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass
24247 10:09:59.814120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass>
24248 10:09:59.850255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
24250 10:09:59.850962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
24251 10:09:59.886305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
24252 10:09:59.886768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
24254 10:09:59.919404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
24255 10:09:59.919813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
24257 10:09:59.952116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass>
24258 10:09:59.952560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass
24260 10:09:59.985341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
24262 10:09:59.985919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
24263 10:10:00.018469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
24264 10:10:00.018922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
24266 10:10:00.050400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
24267 10:10:00.050861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
24269 10:10:00.084900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass>
24270 10:10:00.085386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass
24272 10:10:00.118628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
24273 10:10:00.119078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
24275 10:10:00.151818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
24276 10:10:00.152235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
24278 10:10:00.184705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
24279 10:10:00.185116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
24281 10:10:00.216364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass>
24282 10:10:00.216826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass
24284 10:10:00.247728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
24285 10:10:00.248085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
24287 10:10:00.280231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
24288 10:10:00.280512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
24290 10:10:00.314479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
24291 10:10:00.314757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
24293 10:10:00.346415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass>
24294 10:10:00.346690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass
24296 10:10:00.378392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
24297 10:10:00.378666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
24299 10:10:00.410319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
24300 10:10:00.410774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
24302 10:10:00.442390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
24303 10:10:00.442843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
24305 10:10:00.474270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass>
24306 10:10:00.474741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass
24308 10:10:00.505339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
24310 10:10:00.505951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
24311 10:10:00.536953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
24313 10:10:00.537520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
24314 10:10:00.568316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
24315 10:10:00.568713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
24317 10:10:00.599880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass
24319 10:10:00.600312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass>
24320 10:10:00.630833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
24322 10:10:00.631417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
24323 10:10:00.661713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
24324 10:10:00.662102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
24326 10:10:00.694235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
24328 10:10:00.694650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
24329 10:10:00.727966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass>
24330 10:10:00.728368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass
24332 10:10:00.760508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
24333 10:10:00.760956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
24335 10:10:00.792865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
24336 10:10:00.793261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
24338 10:10:00.825500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
24340 10:10:00.826058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
24341 10:10:00.857758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass>
24342 10:10:00.858223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass
24344 10:10:00.890589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
24345 10:10:00.891068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
24347 10:10:00.923164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
24348 10:10:00.923629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
24350 10:10:00.955113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
24351 10:10:00.955571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
24353 10:10:00.986608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass>
24354 10:10:00.987061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass
24356 10:10:01.017882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
24357 10:10:01.018232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
24359 10:10:01.048294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
24360 10:10:01.048662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
24362 10:10:01.078878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
24363 10:10:01.079155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
24365 10:10:01.110368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass>
24366 10:10:01.110643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass
24368 10:10:01.141852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
24369 10:10:01.142133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
24371 10:10:01.172963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
24372 10:10:01.173235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
24374 10:10:01.204333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
24375 10:10:01.204679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
24377 10:10:01.234992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass>
24378 10:10:01.235325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass
24380 10:10:01.265902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
24381 10:10:01.266251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
24383 10:10:01.296871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
24384 10:10:01.297244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
24386 10:10:01.329330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
24388 10:10:01.329853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
24389 10:10:01.359841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass>
24390 10:10:01.360209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass
24392 10:10:01.390670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
24393 10:10:01.391028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
24395 10:10:01.422042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
24397 10:10:01.422537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
24398 10:10:01.453276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
24400 10:10:01.453793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
24401 10:10:01.484024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass
24403 10:10:01.484513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass>
24404 10:10:01.515107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
24406 10:10:01.515599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
24407 10:10:01.546460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
24408 10:10:01.546793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
24410 10:10:01.577391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
24412 10:10:01.577855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
24413 10:10:01.608297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass>
24414 10:10:01.608733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass
24416 10:10:01.639211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
24417 10:10:01.639598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
24419 10:10:01.670114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
24420 10:10:01.670469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
24422 10:10:01.700750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
24423 10:10:01.701204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
24425 10:10:01.734245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass
24427 10:10:01.734802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass>
24428 10:10:01.765358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
24430 10:10:01.770004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
24431 10:10:01.822890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
24432 10:10:01.823297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
24434 10:10:01.854355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
24435 10:10:01.854795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
24437 10:10:01.885622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass
24439 10:10:01.886157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass>
24440 10:10:01.916885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
24441 10:10:01.917326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
24443 10:10:01.948647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
24444 10:10:01.949039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
24446 10:10:01.980840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
24447 10:10:01.981321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
24449 10:10:02.013797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass
24451 10:10:02.014376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass>
24452 10:10:02.045619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
24454 10:10:02.046231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
24455 10:10:02.080448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
24457 10:10:02.080826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
24458 10:10:02.117428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
24460 10:10:02.117831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
24461 10:10:02.150730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass
24463 10:10:02.151289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass>
24464 10:10:02.182415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
24465 10:10:02.182865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
24467 10:10:02.214623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
24468 10:10:02.215072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
24470 10:10:02.246258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
24471 10:10:02.246725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
24473 10:10:02.277465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass
24475 10:10:02.278014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass>
24476 10:10:02.309103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
24477 10:10:02.309553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
24479 10:10:02.340444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
24480 10:10:02.340848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
24482 10:10:02.372803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
24483 10:10:02.373220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
24485 10:10:02.404327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass>
24486 10:10:02.404734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass
24488 10:10:02.436933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
24489 10:10:02.437353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
24491 10:10:02.469332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
24493 10:10:02.469781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
24494 10:10:02.501551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
24496 10:10:02.502010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
24497 10:10:02.533792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass>
24498 10:10:02.534221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass
24500 10:10:02.565143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
24502 10:10:02.565602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
24503 10:10:02.596871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
24505 10:10:02.597358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
24506 10:10:02.629025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
24508 10:10:02.629475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
24509 10:10:02.660855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass>
24510 10:10:02.661272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass
24512 10:10:02.694113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
24513 10:10:02.694525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
24515 10:10:02.724920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
24516 10:10:02.725327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
24518 10:10:02.756601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
24519 10:10:02.757011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
24521 10:10:02.788122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass>
24522 10:10:02.788547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass
24524 10:10:02.821124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
24526 10:10:02.821584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
24527 10:10:02.856099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
24528 10:10:02.856479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
24530 10:10:02.890265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
24531 10:10:02.890659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
24533 10:10:02.926143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass>
24534 10:10:02.926455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass
24536 10:10:02.958292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
24537 10:10:02.958572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
24539 10:10:02.990445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
24540 10:10:02.990794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
24542 10:10:03.021867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
24544 10:10:03.022147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
24545 10:10:03.054476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass>
24546 10:10:03.054753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass
24548 10:10:03.086877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
24549 10:10:03.087346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
24551 10:10:03.122462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
24552 10:10:03.122933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
24554 10:10:03.158999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
24555 10:10:03.159396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
24557 10:10:03.196310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass>
24558 10:10:03.196609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass
24560 10:10:03.234518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
24562 10:10:03.234802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
24563 10:10:03.271800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
24564 10:10:03.272251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
24566 10:10:03.303337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
24568 10:10:03.303772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
24569 10:10:03.334092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass>
24570 10:10:03.334442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass
24572 10:10:03.364753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
24574 10:10:03.365199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
24575 10:10:03.395305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
24576 10:10:03.395663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
24578 10:10:03.427338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
24579 10:10:03.427633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
24581 10:10:03.461149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass
24583 10:10:03.461671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass>
24584 10:10:03.492667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
24585 10:10:03.493028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
24587 10:10:03.523568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
24589 10:10:03.524057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
24590 10:10:03.554492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
24591 10:10:03.554843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
24593 10:10:03.585677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass>
24594 10:10:03.585951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass
24596 10:10:03.617052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
24597 10:10:03.617399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
24599 10:10:03.648192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
24600 10:10:03.648535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
24602 10:10:03.679361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
24603 10:10:03.679713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
24605 10:10:03.711538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass>
24606 10:10:03.711971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass
24608 10:10:03.746973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
24609 10:10:03.747362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
24611 10:10:03.781962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
24612 10:10:03.782317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
24614 10:10:03.814566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
24615 10:10:03.814841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
24617 10:10:03.846861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass>
24618 10:10:03.847137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass
24620 10:10:03.878484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
24621 10:10:03.878834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
24623 10:10:03.910417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
24624 10:10:03.910762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
24626 10:10:03.942049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
24627 10:10:03.942414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
24629 10:10:03.974421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass>
24630 10:10:03.974773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass
24632 10:10:04.007620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
24634 10:10:04.008038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
24635 10:10:04.039320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
24636 10:10:04.039663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
24638 10:10:04.070488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
24639 10:10:04.070857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
24641 10:10:04.102731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass>
24642 10:10:04.103098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass
24644 10:10:04.134849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
24645 10:10:04.135196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
24647 10:10:04.166591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
24648 10:10:04.167079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
24650 10:10:04.200201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
24651 10:10:04.200616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
24653 10:10:04.231855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass
24655 10:10:04.232399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass>
24656 10:10:04.263778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
24657 10:10:04.264186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
24659 10:10:04.296357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
24661 10:10:04.296825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
24662 10:10:04.329370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
24664 10:10:04.330157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
24665 10:10:04.363410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass>
24666 10:10:04.363890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass
24668 10:10:04.394484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
24669 10:10:04.394945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
24671 10:10:04.426012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
24673 10:10:04.426343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
24674 10:10:04.457327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
24676 10:10:04.457895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
24677 10:10:04.489051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass>
24678 10:10:04.489488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass
24680 10:10:04.522557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
24681 10:10:04.522975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
24683 10:10:04.554769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
24684 10:10:04.555253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
24686 10:10:04.586401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
24688 10:10:04.586940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
24689 10:10:04.618868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass
24691 10:10:04.619385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass>
24692 10:10:04.650297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
24693 10:10:04.650560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
24695 10:10:04.681421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
24697 10:10:04.681825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
24698 10:10:04.712825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
24699 10:10:04.713154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
24701 10:10:04.744112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass>
24702 10:10:04.744388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass
24704 10:10:04.775288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
24705 10:10:04.775564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
24707 10:10:04.806163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
24708 10:10:04.806511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
24710 10:10:04.837004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
24712 10:10:04.837278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
24713 10:10:04.868593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass
24715 10:10:04.868865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass>
24716 10:10:04.899383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
24717 10:10:04.899839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
24719 10:10:04.930775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
24721 10:10:04.931250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
24722 10:10:04.962046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
24723 10:10:04.962455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
24725 10:10:04.993057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass>
24726 10:10:04.993450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass
24728 10:10:05.023900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
24729 10:10:05.024264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
24731 10:10:05.054810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
24732 10:10:05.055169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
24734 10:10:05.085822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
24735 10:10:05.086164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
24737 10:10:05.117093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass>
24738 10:10:05.117440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass
24740 10:10:05.148003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
24741 10:10:05.148349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
24743 10:10:05.178805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
24745 10:10:05.179351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
24746 10:10:05.210220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
24747 10:10:05.210667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
24749 10:10:05.249887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass>
24750 10:10:05.250283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass
24752 10:10:05.281441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
24754 10:10:05.281913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
24755 10:10:05.312694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
24756 10:10:05.313185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
24758 10:10:05.343906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
24759 10:10:05.344282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
24761 10:10:05.374989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass
24763 10:10:05.375426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass>
24764 10:10:05.405816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
24765 10:10:05.406165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
24767 10:10:05.442168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
24769 10:10:05.442657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
24770 10:10:05.475596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
24771 10:10:05.476067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
24773 10:10:05.507546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass>
24774 10:10:05.507949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass
24776 10:10:05.539142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
24777 10:10:05.539515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
24779 10:10:05.570725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
24780 10:10:05.571092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
24782 10:10:05.602370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
24783 10:10:05.602723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
24785 10:10:05.633313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass
24787 10:10:05.633824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass>
24788 10:10:05.664963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
24789 10:10:05.665324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
24791 10:10:05.696652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
24792 10:10:05.697016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
24794 10:10:05.728801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
24795 10:10:05.729147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
24797 10:10:05.760148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass>
24798 10:10:05.760621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass
24800 10:10:05.792364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
24801 10:10:05.792823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
24803 10:10:05.823874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
24804 10:10:05.824308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
24806 10:10:05.855275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
24807 10:10:05.855593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
24809 10:10:05.887401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass
24811 10:10:05.887682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass>
24812 10:10:05.918776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
24813 10:10:05.919051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
24815 10:10:05.950324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
24816 10:10:05.950598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
24818 10:10:05.982202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
24819 10:10:05.982481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
24821 10:10:06.014104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass>
24822 10:10:06.014576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass
24824 10:10:06.045634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
24825 10:10:06.046093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
24827 10:10:06.077050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
24828 10:10:06.077437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
24830 10:10:06.108690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
24831 10:10:06.109044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
24833 10:10:06.140496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass>
24834 10:10:06.140852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass
24836 10:10:06.171837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
24837 10:10:06.172195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
24839 10:10:06.203035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
24840 10:10:06.203394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
24842 10:10:06.234763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
24843 10:10:06.235165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
24845 10:10:06.266614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass
24847 10:10:06.267152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass>
24848 10:10:06.298370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
24849 10:10:06.298768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
24851 10:10:06.331243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
24853 10:10:06.331744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
24854 10:10:06.363338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
24855 10:10:06.363717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
24857 10:10:06.396156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass>
24858 10:10:06.396618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass
24860 10:10:06.428365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
24861 10:10:06.428819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
24863 10:10:06.460325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
24864 10:10:06.460752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
24866 10:10:06.492957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
24867 10:10:06.493368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
24869 10:10:06.524343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass>
24870 10:10:06.524708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass
24872 10:10:06.555815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
24873 10:10:06.556167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
24875 10:10:06.587243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
24876 10:10:06.587585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
24878 10:10:06.619404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
24879 10:10:06.619744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
24881 10:10:06.650537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass>
24882 10:10:06.650877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass
24884 10:10:06.681960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
24886 10:10:06.682461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
24887 10:10:06.713126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
24888 10:10:06.713540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
24890 10:10:06.746781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
24892 10:10:06.747223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
24893 10:10:06.778244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass
24895 10:10:06.778796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass>
24896 10:10:06.809767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
24897 10:10:06.810205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
24899 10:10:06.843987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
24900 10:10:06.844447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
24902 10:10:06.875897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
24903 10:10:06.876326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
24905 10:10:06.930683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass>
24906 10:10:06.931180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass
24908 10:10:06.962482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
24910 10:10:06.963010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
24911 10:10:06.993822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
24912 10:10:06.994198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
24914 10:10:07.024965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
24915 10:10:07.025309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
24917 10:10:07.056390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass>
24918 10:10:07.056760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass
24920 10:10:07.087631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
24921 10:10:07.088029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
24923 10:10:07.120646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
24924 10:10:07.121057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
24926 10:10:07.152663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
24927 10:10:07.153092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
24929 10:10:07.184486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass>
24930 10:10:07.184934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass
24932 10:10:07.216294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
24933 10:10:07.216750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
24935 10:10:07.247606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
24936 10:10:07.247934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
24938 10:10:07.278764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
24939 10:10:07.279039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
24941 10:10:07.310095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass>
24942 10:10:07.310369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass
24944 10:10:07.341362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
24946 10:10:07.341624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
24947 10:10:07.373757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
24948 10:10:07.374034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
24950 10:10:07.404936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
24951 10:10:07.405392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
24953 10:10:07.436834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass
24955 10:10:07.437359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass>
24956 10:10:07.468197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
24957 10:10:07.468666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
24959 10:10:07.499608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
24960 10:10:07.499995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
24962 10:10:07.531020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
24963 10:10:07.531363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
24965 10:10:07.562314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass
24967 10:10:07.562937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass>
24968 10:10:07.593355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
24970 10:10:07.593907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
24971 10:10:07.624615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
24972 10:10:07.625041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
24974 10:10:07.655778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
24975 10:10:07.656248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
24977 10:10:07.687013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass
24979 10:10:07.687537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass>
24980 10:10:07.721538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
24982 10:10:07.722101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
24983 10:10:07.753125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
24984 10:10:07.753597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
24986 10:10:07.784414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
24988 10:10:07.784970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
24989 10:10:07.815439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass
24991 10:10:07.815966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass>
24992 10:10:07.846344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
24993 10:10:07.846735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
24995 10:10:07.878907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
24997 10:10:07.879408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
24998 10:10:07.910133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
24999 10:10:07.910508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
25001 10:10:07.942187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass>
25002 10:10:07.942561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass
25004 10:10:07.973418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
25006 10:10:07.973989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
25007 10:10:08.018606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
25008 10:10:08.019013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
25010 10:10:08.063099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
25011 10:10:08.063484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
25013 10:10:08.095696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass
25015 10:10:08.096024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass>
25016 10:10:08.128792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
25017 10:10:08.129153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
25019 10:10:08.161987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
25020 10:10:08.162262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
25022 10:10:08.196126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
25023 10:10:08.196505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
25025 10:10:08.232017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass
25027 10:10:08.232443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass>
25028 10:10:08.266817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
25029 10:10:08.267217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
25031 10:10:08.302379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
25032 10:10:08.302813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
25034 10:10:08.335859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
25035 10:10:08.336319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
25037 10:10:08.368001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass>
25038 10:10:08.368385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass
25040 10:10:08.398924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
25042 10:10:08.399201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
25043 10:10:08.431032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
25045 10:10:08.431309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
25046 10:10:08.464075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
25047 10:10:08.464366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
25049 10:10:08.495474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass>
25050 10:10:08.495746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass
25052 10:10:08.526743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
25053 10:10:08.527114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
25055 10:10:08.558239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
25056 10:10:08.558609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
25058 10:10:08.590197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
25059 10:10:08.590562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
25061 10:10:08.621305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass
25063 10:10:08.621833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass>
25064 10:10:08.652426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
25065 10:10:08.652780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
25067 10:10:08.683808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
25068 10:10:08.684164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
25070 10:10:08.715229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
25071 10:10:08.715669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
25073 10:10:08.746714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass>
25074 10:10:08.747175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass
25076 10:10:08.778229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
25077 10:10:08.778706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
25079 10:10:08.810678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
25080 10:10:08.811161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
25082 10:10:08.845258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
25083 10:10:08.845752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
25085 10:10:08.878123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass
25087 10:10:08.878735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass>
25088 10:10:08.910287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
25089 10:10:08.910738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
25091 10:10:08.942317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
25092 10:10:08.942886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
25094 10:10:08.974542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
25096 10:10:08.975201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
25097 10:10:09.010274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass>
25098 10:10:09.010699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass
25100 10:10:09.042576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
25101 10:10:09.042854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
25103 10:10:09.074858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
25104 10:10:09.075322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
25106 10:10:09.106776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
25107 10:10:09.107123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
25109 10:10:09.138636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass
25111 10:10:09.139059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass>
25112 10:10:09.170132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
25113 10:10:09.170570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
25115 10:10:09.202043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
25116 10:10:09.202485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
25118 10:10:09.234027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
25119 10:10:09.234478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
25121 10:10:09.266256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass>
25122 10:10:09.266659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass
25124 10:10:09.298299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
25125 10:10:09.298695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
25127 10:10:09.329968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
25128 10:10:09.330420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
25130 10:10:09.361883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
25131 10:10:09.362327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
25133 10:10:09.393409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass
25135 10:10:09.394023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass>
25136 10:10:09.425760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
25137 10:10:09.426187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
25139 10:10:09.458602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
25141 10:10:09.459045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
25142 10:10:09.490551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
25143 10:10:09.490944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
25145 10:10:09.522079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass>
25146 10:10:09.522423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass
25148 10:10:09.553795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
25149 10:10:09.554141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
25151 10:10:09.585321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
25153 10:10:09.585607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
25154 10:10:09.618349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
25156 10:10:09.618634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
25157 10:10:09.650954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass
25159 10:10:09.651512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass>
25160 10:10:09.682889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
25161 10:10:09.683392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
25163 10:10:09.714977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
25164 10:10:09.715297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
25166 10:10:09.746883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
25167 10:10:09.747350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
25169 10:10:09.778395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass>
25170 10:10:09.778765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass
25172 10:10:09.809990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
25173 10:10:09.810349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
25175 10:10:09.841352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
25177 10:10:09.841630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
25178 10:10:09.872945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
25179 10:10:09.873290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
25181 10:10:09.903916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass>
25182 10:10:09.904192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass
25184 10:10:09.935294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
25185 10:10:09.935644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
25187 10:10:09.966943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
25188 10:10:09.967398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
25190 10:10:09.998500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
25191 10:10:09.998897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
25193 10:10:10.031015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass>
25194 10:10:10.031418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass
25196 10:10:10.063393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
25197 10:10:10.063797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
25199 10:10:10.096489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
25200 10:10:10.096893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
25202 10:10:10.128798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
25203 10:10:10.129216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
25205 10:10:10.160764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass>
25206 10:10:10.161176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass
25208 10:10:10.193148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
25209 10:10:10.193570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
25211 10:10:10.224801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
25212 10:10:10.225247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
25214 10:10:10.257060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
25216 10:10:10.257712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
25217 10:10:10.293824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass
25219 10:10:10.294232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass>
25220 10:10:10.326552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
25221 10:10:10.327000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
25223 10:10:10.357768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
25224 10:10:10.358039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
25226 10:10:10.388815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
25227 10:10:10.389189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
25229 10:10:10.420468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass>
25230 10:10:10.420844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass
25232 10:10:10.452598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
25233 10:10:10.453006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
25235 10:10:10.486941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
25236 10:10:10.487320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
25238 10:10:10.518902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
25239 10:10:10.519252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
25241 10:10:10.550812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass>
25242 10:10:10.551168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass
25244 10:10:10.584117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
25245 10:10:10.584478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
25247 10:10:10.615952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
25248 10:10:10.616391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
25250 10:10:10.648174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
25251 10:10:10.648571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
25253 10:10:10.679508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass
25255 10:10:10.679998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass>
25256 10:10:10.710802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
25257 10:10:10.711166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
25259 10:10:10.742208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
25260 10:10:10.742560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
25262 10:10:10.774146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
25263 10:10:10.774560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
25265 10:10:10.805181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass>
25266 10:10:10.805580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass
25268 10:10:10.836984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
25269 10:10:10.837333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
25271 10:10:10.869032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
25273 10:10:10.869609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
25274 10:10:10.901519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
25276 10:10:10.901967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
25277 10:10:10.932910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass
25279 10:10:10.933381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass>
25280 10:10:10.963989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
25281 10:10:10.964332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
25283 10:10:10.996088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
25284 10:10:10.996451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
25286 10:10:11.027483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
25287 10:10:11.027833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
25289 10:10:11.059340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass>
25290 10:10:11.059616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass
25292 10:10:11.091003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
25293 10:10:11.091347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
25295 10:10:11.122421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
25296 10:10:11.122887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
25298 10:10:11.154468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
25299 10:10:11.154855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
25301 10:10:11.186414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass>
25302 10:10:11.186762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass
25304 10:10:11.218081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
25306 10:10:11.218497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
25307 10:10:11.249691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
25308 10:10:11.250026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
25310 10:10:11.280972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
25311 10:10:11.281313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
25313 10:10:11.312948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass>
25314 10:10:11.313295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass
25316 10:10:11.345163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
25318 10:10:11.345878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
25319 10:10:11.376546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
25320 10:10:11.376969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
25322 10:10:11.409920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
25323 10:10:11.410332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
25325 10:10:11.442512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass>
25326 10:10:11.442969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass
25328 10:10:11.477141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
25329 10:10:11.477629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
25331 10:10:11.510903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
25333 10:10:11.511455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
25334 10:10:11.543059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
25335 10:10:11.543538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
25337 10:10:11.574839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass>
25338 10:10:11.575305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass
25340 10:10:11.606788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
25341 10:10:11.607136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
25343 10:10:11.638407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
25344 10:10:11.638753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
25346 10:10:11.671557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
25347 10:10:11.671938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
25349 10:10:11.705015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass
25351 10:10:11.705425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass>
25352 10:10:11.736100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
25353 10:10:11.736433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
25355 10:10:11.769146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
25357 10:10:11.769583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
25358 10:10:11.805963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
25360 10:10:11.806358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
25361 10:10:11.842225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass>
25362 10:10:11.842506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass
25364 10:10:11.877108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
25365 10:10:11.877456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
25367 10:10:11.911116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
25368 10:10:11.911468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
25370 10:10:11.946677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
25372 10:10:11.947126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
25373 10:10:11.980565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass>
25374 10:10:11.980962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass
25376 10:10:12.050651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
25377 10:10:12.051032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
25379 10:10:12.082388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
25380 10:10:12.082668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
25382 10:10:12.114925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
25383 10:10:12.115368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
25385 10:10:12.147744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass
25387 10:10:12.148321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass>
25388 10:10:12.179821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
25389 10:10:12.180279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
25391 10:10:12.214966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
25392 10:10:12.215337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
25394 10:10:12.246669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
25395 10:10:12.246943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
25397 10:10:12.279945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass
25399 10:10:12.280323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass>
25400 10:10:12.312080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
25401 10:10:12.312519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
25403 10:10:12.343911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
25404 10:10:12.344197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
25406 10:10:12.376102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
25407 10:10:12.376388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
25409 10:10:12.408164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass
25411 10:10:12.408606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass>
25412 10:10:12.440021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
25413 10:10:12.440369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
25415 10:10:12.471438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
25416 10:10:12.471801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
25418 10:10:12.503122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
25419 10:10:12.503468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
25421 10:10:12.534561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass
25423 10:10:12.535000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass>
25424 10:10:12.565923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
25425 10:10:12.566270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
25427 10:10:12.597682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
25428 10:10:12.598026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
25430 10:10:12.628549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
25431 10:10:12.628897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
25433 10:10:12.660011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass>
25434 10:10:12.660357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass
25436 10:10:12.692412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
25437 10:10:12.692780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
25439 10:10:12.723937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
25440 10:10:12.724284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
25442 10:10:12.756094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
25443 10:10:12.756461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
25445 10:10:12.786867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass>
25446 10:10:12.787229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass
25448 10:10:12.821925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
25449 10:10:12.822288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
25451 10:10:12.852688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
25452 10:10:12.853055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
25454 10:10:12.883548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
25455 10:10:12.883921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
25457 10:10:12.914479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass
25459 10:10:12.914978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass>
25460 10:10:12.946038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
25461 10:10:12.946385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
25463 10:10:12.977723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
25464 10:10:12.978166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
25466 10:10:13.009529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
25468 10:10:13.010111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
25469 10:10:13.042075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass>
25470 10:10:13.042530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass
25472 10:10:13.073578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
25474 10:10:13.074217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
25475 10:10:13.104885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
25476 10:10:13.105355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
25478 10:10:13.136012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
25479 10:10:13.136474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
25481 10:10:13.168073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass>
25482 10:10:13.168451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass
25484 10:10:13.199217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
25486 10:10:13.199655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
25487 10:10:13.231086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
25488 10:10:13.231455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
25490 10:10:13.262904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
25491 10:10:13.263255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
25493 10:10:13.294168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass>
25494 10:10:13.294535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass
25496 10:10:13.325103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
25497 10:10:13.325569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
25499 10:10:13.358124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
25501 10:10:13.358708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
25502 10:10:13.390455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
25504 10:10:13.391068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
25505 10:10:13.422025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass>
25506 10:10:13.422306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass
25508 10:10:13.453018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
25509 10:10:13.453295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
25511 10:10:13.487279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
25513 10:10:13.487840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
25514 10:10:13.519726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
25516 10:10:13.520256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
25517 10:10:13.551095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass>
25518 10:10:13.551442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass
25520 10:10:13.585399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
25522 10:10:13.585848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
25523 10:10:13.618668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
25524 10:10:13.619215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
25526 10:10:13.651910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
25528 10:10:13.652404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
25529 10:10:13.685803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass>
25530 10:10:13.686196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass
25532 10:10:13.718030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
25533 10:10:13.718398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
25535 10:10:13.749887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
25536 10:10:13.750337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
25538 10:10:13.782575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
25539 10:10:13.783052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
25541 10:10:13.814210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass>
25542 10:10:13.814673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass
25544 10:10:13.845921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
25545 10:10:13.846321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
25547 10:10:13.878393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
25548 10:10:13.878980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
25550 10:10:13.912137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
25552 10:10:13.912593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
25553 10:10:13.951123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass
25555 10:10:13.951578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass>
25556 10:10:13.983501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
25557 10:10:13.983956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
25559 10:10:14.015464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
25560 10:10:14.015869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
25562 10:10:14.047613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
25563 10:10:14.048047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
25565 10:10:14.079608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass>
25566 10:10:14.080051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass
25568 10:10:14.111581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
25569 10:10:14.111986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
25571 10:10:14.143069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
25572 10:10:14.143350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
25574 10:10:14.174548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
25575 10:10:14.174923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
25577 10:10:14.206639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass>
25578 10:10:14.206919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass
25580 10:10:14.238876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
25581 10:10:14.239245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
25583 10:10:14.274056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
25585 10:10:14.274591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
25586 10:10:14.306233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
25588 10:10:14.306778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
25589 10:10:14.338917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass
25591 10:10:14.339454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass>
25592 10:10:14.383327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
25593 10:10:14.383792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
25595 10:10:14.418173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
25596 10:10:14.418622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
25598 10:10:14.450453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
25599 10:10:14.450861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
25601 10:10:14.482951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass>
25602 10:10:14.483369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass
25604 10:10:14.515003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
25605 10:10:14.515443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
25607 10:10:14.547181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
25608 10:10:14.547630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
25610 10:10:14.579133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
25611 10:10:14.579596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
25613 10:10:14.610926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass>
25614 10:10:14.611369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass
25616 10:10:14.643237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
25617 10:10:14.643676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
25619 10:10:14.675823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
25620 10:10:14.676262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
25622 10:10:14.707999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
25623 10:10:14.708436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
25625 10:10:14.740151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass>
25626 10:10:14.740591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass
25628 10:10:14.772112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
25630 10:10:14.772548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
25631 10:10:14.804356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
25633 10:10:14.804771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
25634 10:10:14.836738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
25636 10:10:14.837039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
25637 10:10:14.868365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass>
25638 10:10:14.868734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass
25640 10:10:14.899665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
25641 10:10:14.900015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
25643 10:10:14.931596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
25644 10:10:14.931942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
25646 10:10:14.963329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
25647 10:10:14.963669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
25649 10:10:14.994799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass>
25650 10:10:14.995078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass
25652 10:10:15.026752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
25653 10:10:15.027028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
25655 10:10:15.058764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
25656 10:10:15.059036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
25658 10:10:15.091098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
25659 10:10:15.091453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
25661 10:10:15.124976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass>
25662 10:10:15.125253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass
25664 10:10:15.156767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
25665 10:10:15.157043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
25667 10:10:15.188184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
25668 10:10:15.188461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
25670 10:10:15.219732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
25671 10:10:15.220189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
25673 10:10:15.252385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass>
25674 10:10:15.252826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass
25676 10:10:15.283913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
25678 10:10:15.284492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
25679 10:10:15.315563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
25680 10:10:15.316031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
25682 10:10:15.347230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
25684 10:10:15.347771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
25685 10:10:15.378471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass>
25686 10:10:15.378808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass
25688 10:10:15.410343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
25689 10:10:15.410710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
25691 10:10:15.442300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
25692 10:10:15.442665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
25694 10:10:15.477146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
25695 10:10:15.477510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
25697 10:10:15.510042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass
25699 10:10:15.510512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass>
25700 10:10:15.541782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
25701 10:10:15.542058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
25703 10:10:15.573345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
25705 10:10:15.573881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
25706 10:10:15.606760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
25707 10:10:15.607124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
25709 10:10:15.638047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass>
25710 10:10:15.638412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass
25712 10:10:15.669667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
25713 10:10:15.670013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
25715 10:10:15.702255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
25716 10:10:15.702600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
25718 10:10:15.734021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
25719 10:10:15.734372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
25721 10:10:15.765728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass>
25722 10:10:15.766008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass
25724 10:10:15.797276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
25726 10:10:15.797745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
25727 10:10:15.830497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
25728 10:10:15.830957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
25730 10:10:15.862954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
25732 10:10:15.863516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
25733 10:10:15.894294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass>
25734 10:10:15.894693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass
25736 10:10:15.925825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
25737 10:10:15.926219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
25739 10:10:15.958779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
25740 10:10:15.959193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
25742 10:10:15.991304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
25743 10:10:15.991779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
25745 10:10:16.022524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass
25747 10:10:16.023061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass>
25748 10:10:16.053615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
25749 10:10:16.054077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
25751 10:10:16.084859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
25752 10:10:16.085317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
25754 10:10:16.116290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
25755 10:10:16.116742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
25757 10:10:16.147297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass>
25758 10:10:16.147726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass
25760 10:10:16.178564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
25762 10:10:16.179006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
25763 10:10:16.210364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
25765 10:10:16.210799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
25766 10:10:16.241875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
25768 10:10:16.242309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
25769 10:10:16.274115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass
25771 10:10:16.274555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass>
25772 10:10:16.305720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
25773 10:10:16.306162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
25775 10:10:16.336904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
25777 10:10:16.337469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
25778 10:10:16.368113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
25779 10:10:16.368565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
25781 10:10:16.399114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass>
25782 10:10:16.399559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass
25784 10:10:16.430448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
25785 10:10:16.430921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
25787 10:10:16.468019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
25788 10:10:16.468305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
25790 10:10:16.500096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
25791 10:10:16.500373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
25793 10:10:16.532342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass>
25794 10:10:16.532709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass
25796 10:10:16.563142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
25797 10:10:16.563581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
25799 10:10:16.594984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
25800 10:10:16.595478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
25802 10:10:16.630151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
25803 10:10:16.630612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
25805 10:10:16.662392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass>
25806 10:10:16.662842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass
25808 10:10:16.693726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
25809 10:10:16.694162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
25811 10:10:16.726222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
25812 10:10:16.726640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
25814 10:10:16.757985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
25815 10:10:16.758428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
25817 10:10:16.791247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass>
25818 10:10:16.791697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass
25820 10:10:16.823564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
25821 10:10:16.824023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
25823 10:10:16.855981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
25824 10:10:16.856427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
25826 10:10:16.889396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
25828 10:10:16.889869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
25829 10:10:16.922445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass>
25830 10:10:16.922805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass
25832 10:10:16.955155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
25834 10:10:16.955499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
25835 10:10:16.987634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
25836 10:10:16.987924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
25838 10:10:17.022138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
25839 10:10:17.022488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
25841 10:10:17.053413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass
25843 10:10:17.054002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass>
25844 10:10:17.085003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
25845 10:10:17.085450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
25847 10:10:17.116575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
25849 10:10:17.117004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
25850 10:10:17.171825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
25852 10:10:17.172263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
25853 10:10:17.203465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass
25855 10:10:17.203805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass>
25856 10:10:17.235680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
25857 10:10:17.236096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
25859 10:10:17.268260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
25861 10:10:17.268693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
25862 10:10:17.300579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
25863 10:10:17.300994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
25865 10:10:17.334135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass>
25866 10:10:17.334566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass
25868 10:10:17.366490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
25869 10:10:17.366964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
25871 10:10:17.397953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
25872 10:10:17.398343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
25874 10:10:17.429590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
25876 10:10:17.430150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
25877 10:10:17.461136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass
25879 10:10:17.461761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass>
25880 10:10:17.492562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
25882 10:10:17.493188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
25883 10:10:17.524712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
25885 10:10:17.525173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
25886 10:10:17.556013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
25887 10:10:17.556299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
25889 10:10:17.587785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass>
25890 10:10:17.588064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass
25892 10:10:17.618830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
25894 10:10:17.619116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
25895 10:10:17.650339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
25896 10:10:17.650627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
25898 10:10:17.682065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
25899 10:10:17.682447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
25901 10:10:17.712957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass
25903 10:10:17.713222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass>
25904 10:10:17.744312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
25905 10:10:17.744576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
25907 10:10:17.776623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
25908 10:10:17.776886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
25910 10:10:17.807904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
25911 10:10:17.808212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
25913 10:10:17.841868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass
25915 10:10:17.842152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass>
25916 10:10:17.873328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
25918 10:10:17.873594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
25919 10:10:17.904714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
25920 10:10:17.904998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
25922 10:10:17.936684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
25923 10:10:17.937099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
25925 10:10:17.967974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass>
25926 10:10:17.968277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass
25928 10:10:17.999040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
25930 10:10:17.999384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
25931 10:10:18.030267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
25932 10:10:18.030604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
25934 10:10:18.062005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
25935 10:10:18.062449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
25937 10:10:18.093363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass
25939 10:10:18.093981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass>
25940 10:10:18.124312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
25941 10:10:18.124759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
25943 10:10:18.155528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
25944 10:10:18.155891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
25946 10:10:18.187065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
25947 10:10:18.187467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
25949 10:10:18.218149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass>
25950 10:10:18.218517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass
25952 10:10:18.249383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
25954 10:10:18.249958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
25955 10:10:18.280690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
25956 10:10:18.281107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
25958 10:10:18.311816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
25959 10:10:18.312172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
25961 10:10:18.343449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass>
25962 10:10:18.343825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass
25964 10:10:18.375031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
25965 10:10:18.375414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
25967 10:10:18.406227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
25968 10:10:18.406667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
25970 10:10:18.438745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
25972 10:10:18.439334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
25973 10:10:18.470754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass
25975 10:10:18.471201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass>
25976 10:10:18.502381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
25977 10:10:18.502833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
25979 10:10:18.539707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
25980 10:10:18.540182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
25982 10:10:18.576687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
25983 10:10:18.577159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
25985 10:10:18.608746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass>
25986 10:10:18.609215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass
25988 10:10:18.640228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
25990 10:10:18.640773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
25991 10:10:18.671214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
25992 10:10:18.671670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
25994 10:10:18.702772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
25995 10:10:18.703230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
25997 10:10:18.734056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass>
25998 10:10:18.734495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass
26000 10:10:18.765678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
26001 10:10:18.766119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
26003 10:10:18.798179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
26004 10:10:18.798624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
26006 10:10:18.829142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
26007 10:10:18.829546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
26009 10:10:18.860059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass>
26010 10:10:18.860498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass
26012 10:10:18.891221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
26013 10:10:18.891604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
26015 10:10:18.922107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
26016 10:10:18.922383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
26018 10:10:18.953817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
26019 10:10:18.954092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
26021 10:10:18.984594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass>
26022 10:10:18.984904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass
26024 10:10:19.015832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
26025 10:10:19.016219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
26027 10:10:19.046653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
26028 10:10:19.047011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
26030 10:10:19.077924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
26031 10:10:19.078251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
26033 10:10:19.108770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass>
26034 10:10:19.109100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass
26036 10:10:19.139791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
26037 10:10:19.140153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
26039 10:10:19.171074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
26040 10:10:19.171589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
26042 10:10:19.203657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
26043 10:10:19.204146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
26045 10:10:19.234964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass
26047 10:10:19.235289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass>
26048 10:10:19.266313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
26049 10:10:19.266756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
26051 10:10:19.297973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
26052 10:10:19.298457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
26054 10:10:19.329717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
26055 10:10:19.330130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
26057 10:10:19.361020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass
26059 10:10:19.361576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass>
26060 10:10:19.395279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
26061 10:10:19.395610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
26063 10:10:19.428073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
26064 10:10:19.428425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
26066 10:10:19.459605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
26067 10:10:19.459992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
26069 10:10:19.491194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass>
26070 10:10:19.491548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass
26072 10:10:19.522556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
26073 10:10:19.523008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
26075 10:10:19.566678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
26076 10:10:19.567057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
26078 10:10:19.607141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
26079 10:10:19.607484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
26081 10:10:19.639279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass
26083 10:10:19.639844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass>
26084 10:10:19.671096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
26086 10:10:19.671652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
26087 10:10:19.702833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
26088 10:10:19.703234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
26090 10:10:19.734317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
26091 10:10:19.734784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
26093 10:10:19.765994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass>
26094 10:10:19.766453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass
26096 10:10:19.797262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
26098 10:10:19.797565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
26099 10:10:19.829508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
26101 10:10:19.829958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
26102 10:10:19.862218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
26103 10:10:19.862622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
26105 10:10:19.894172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass>
26106 10:10:19.894592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass
26108 10:10:19.927105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
26109 10:10:19.927555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
26111 10:10:19.959403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
26112 10:10:19.959841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
26114 10:10:19.993968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
26115 10:10:19.994460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
26117 10:10:20.028707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass
26119 10:10:20.029250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass>
26120 10:10:20.074283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
26121 10:10:20.074724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
26123 10:10:20.109788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
26124 10:10:20.110073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
26126 10:10:20.146772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
26127 10:10:20.147246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
26129 10:10:20.183397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass>
26130 10:10:20.183871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass
26132 10:10:20.219573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
26134 10:10:20.220207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
26135 10:10:20.255853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
26136 10:10:20.256176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
26138 10:10:20.292708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
26140 10:10:20.292991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
26141 10:10:20.329934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass>
26142 10:10:20.330211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass
26144 10:10:20.367751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
26145 10:10:20.368118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
26147 10:10:20.403807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
26148 10:10:20.404160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
26150 10:10:20.440585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
26152 10:10:20.441199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
26153 10:10:20.476447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass>
26154 10:10:20.476770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass
26156 10:10:20.512466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
26157 10:10:20.512743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
26159 10:10:20.549051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
26160 10:10:20.549529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
26162 10:10:20.585885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
26163 10:10:20.586339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
26165 10:10:20.622449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass>
26166 10:10:20.622915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass
26168 10:10:20.658999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
26169 10:10:20.659451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
26171 10:10:20.693936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
26172 10:10:20.694405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
26174 10:10:20.728504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
26175 10:10:20.728986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
26177 10:10:20.764083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass
26179 10:10:20.764710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass>
26180 10:10:20.798919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
26181 10:10:20.799393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
26183 10:10:20.834809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
26184 10:10:20.835231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
26186 10:10:20.871374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
26187 10:10:20.871789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
26189 10:10:20.907411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass>
26190 10:10:20.907817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass
26192 10:10:20.943337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
26193 10:10:20.943747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
26195 10:10:20.980037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
26196 10:10:20.980447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
26198 10:10:21.015989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
26199 10:10:21.016441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
26201 10:10:21.052217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass>
26202 10:10:21.052663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass
26204 10:10:21.089036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
26205 10:10:21.089450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
26207 10:10:21.127104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
26209 10:10:21.127575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
26210 10:10:21.164371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
26211 10:10:21.164797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
26213 10:10:21.201415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass
26215 10:10:21.201963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass>
26216 10:10:21.238495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
26217 10:10:21.238913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
26219 10:10:21.275175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
26220 10:10:21.275593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
26222 10:10:21.312356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
26223 10:10:21.312827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
26225 10:10:21.347898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass>
26226 10:10:21.348351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass
26228 10:10:21.382759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
26229 10:10:21.383078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
26231 10:10:21.418192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
26232 10:10:21.418470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
26234 10:10:21.453972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
26235 10:10:21.454347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
26237 10:10:21.489142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass>
26238 10:10:21.489589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass
26240 10:10:21.524051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
26241 10:10:21.524493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
26243 10:10:21.558826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
26245 10:10:21.559290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
26246 10:10:21.594468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
26247 10:10:21.594819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
26249 10:10:21.630513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass>
26250 10:10:21.630882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass
26252 10:10:21.663457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
26253 10:10:21.663832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
26255 10:10:21.697108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
26256 10:10:21.697584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
26258 10:10:21.730743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
26259 10:10:21.731200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
26261 10:10:21.764096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass>
26262 10:10:21.764564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass
26264 10:10:21.802756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
26265 10:10:21.803299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
26267 10:10:21.836790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
26268 10:10:21.837353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
26270 10:10:21.871300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
26271 10:10:21.871737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
26273 10:10:21.908082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass>
26274 10:10:21.908522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass
26276 10:10:21.943468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
26278 10:10:21.943933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
26279 10:10:21.983058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
26280 10:10:21.983437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
26282 10:10:22.017099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
26283 10:10:22.017486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
26285 10:10:22.054583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass>
26286 10:10:22.054929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass
26288 10:10:22.090109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
26289 10:10:22.090465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
26291 10:10:22.125054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
26292 10:10:22.125333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
26294 10:10:22.160773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
26296 10:10:22.161148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
26297 10:10:22.195588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass>
26298 10:10:22.195972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass
26300 10:10:22.233638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
26301 10:10:22.233994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
26303 10:10:22.300626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
26304 10:10:22.300982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
26306 10:10:22.338085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
26307 10:10:22.338439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
26309 10:10:22.373544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass
26311 10:10:22.374005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass>
26312 10:10:22.408232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
26313 10:10:22.408655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
26315 10:10:22.443234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
26316 10:10:22.443648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
26318 10:10:22.479300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
26319 10:10:22.479727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
26321 10:10:22.514949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass
26323 10:10:22.515420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass>
26324 10:10:22.550824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
26325 10:10:22.551226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
26327 10:10:22.586673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
26328 10:10:22.587164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
26330 10:10:22.622739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
26331 10:10:22.623211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
26333 10:10:22.658803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass>
26334 10:10:22.659240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass
26336 10:10:22.694725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
26337 10:10:22.695129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
26339 10:10:22.731815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
26340 10:10:22.732296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
26342 10:10:22.767244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
26343 10:10:22.767638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
26345 10:10:22.799838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass>
26346 10:10:22.800288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass
26348 10:10:22.834160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
26349 10:10:22.834569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
26351 10:10:22.866477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
26353 10:10:22.867032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
26354 10:10:22.899794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
26356 10:10:22.900519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
26357 10:10:22.934877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass>
26358 10:10:22.935428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass
26360 10:10:22.970354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
26362 10:10:22.970816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
26363 10:10:23.006431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
26364 10:10:23.006850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
26366 10:10:23.040643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
26367 10:10:23.041037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
26369 10:10:23.075630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass>
26370 10:10:23.076105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass
26372 10:10:23.110924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
26373 10:10:23.111367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
26375 10:10:23.146668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
26376 10:10:23.147120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
26378 10:10:23.182442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
26379 10:10:23.182863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
26381 10:10:23.215152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass>
26382 10:10:23.215542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass
26384 10:10:23.248140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
26385 10:10:23.248576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
26387 10:10:23.283336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
26388 10:10:23.283746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
26390 10:10:23.317924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
26391 10:10:23.318335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
26393 10:10:23.353452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass
26395 10:10:23.353906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass>
26396 10:10:23.389716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
26397 10:10:23.390136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
26399 10:10:23.421580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
26400 10:10:23.422012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
26402 10:10:23.455576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
26403 10:10:23.456007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
26405 10:10:23.488420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass
26407 10:10:23.488980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass>
26408 10:10:23.520553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
26410 10:10:23.520982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
26411 10:10:23.551638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
26412 10:10:23.552003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
26414 10:10:23.583481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
26415 10:10:23.583826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
26417 10:10:23.614459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass>
26418 10:10:23.614738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass
26420 10:10:23.645976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
26421 10:10:23.646317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
26423 10:10:23.677286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
26425 10:10:23.677943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
26426 10:10:23.709047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
26427 10:10:23.709390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
26429 10:10:23.740127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass>
26430 10:10:23.740496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass
26432 10:10:23.772371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
26433 10:10:23.772742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
26435 10:10:23.805458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
26437 10:10:23.806021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
26438 10:10:23.838613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
26439 10:10:23.838974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
26441 10:10:23.870847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass>
26442 10:10:23.871203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass
26444 10:10:23.903382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
26446 10:10:23.903868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
26447 10:10:23.935095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
26448 10:10:23.935459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
26450 10:10:23.966871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
26451 10:10:23.967223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
26453 10:10:23.998466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass>
26454 10:10:23.998744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass
26456 10:10:24.030287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
26457 10:10:24.030630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
26459 10:10:24.061348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
26461 10:10:24.061861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
26462 10:10:24.092930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
26464 10:10:24.093212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
26465 10:10:24.125115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass>
26466 10:10:24.125497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass
26468 10:10:24.157077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
26469 10:10:24.157435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
26471 10:10:24.187944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
26472 10:10:24.188223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
26474 10:10:24.219323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
26476 10:10:24.219751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
26477 10:10:24.251388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass>
26478 10:10:24.251668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass
26480 10:10:24.283099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
26481 10:10:24.283445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
26483 10:10:24.315346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
26484 10:10:24.315745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
26486 10:10:24.349963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
26487 10:10:24.350424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
26489 10:10:24.382897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass
26491 10:10:24.383450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass>
26492 10:10:24.415397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
26493 10:10:24.415855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
26495 10:10:24.448606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
26497 10:10:24.449154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
26498 10:10:24.480362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
26499 10:10:24.480704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
26501 10:10:24.511612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass>
26502 10:10:24.511952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass
26504 10:10:24.543184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
26505 10:10:24.543536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
26507 10:10:24.574170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
26508 10:10:24.574512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
26510 10:10:24.606469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
26511 10:10:24.606925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
26513 10:10:24.637952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass>
26514 10:10:24.638417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass
26516 10:10:24.669105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
26517 10:10:24.669565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
26519 10:10:24.700693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
26520 10:10:24.701158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
26522 10:10:24.731790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
26523 10:10:24.732261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
26525 10:10:24.762768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass>
26526 10:10:24.763090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass
26528 10:10:24.794752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
26530 10:10:24.795380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
26531 10:10:24.826101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
26532 10:10:24.826508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
26534 10:10:24.857653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
26535 10:10:24.858057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
26537 10:10:24.890431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass>
26538 10:10:24.890838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass
26540 10:10:24.922332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
26541 10:10:24.922731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
26543 10:10:24.954577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
26544 10:10:24.955051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
26546 10:10:24.986012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
26547 10:10:24.986476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
26549 10:10:25.018101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass
26551 10:10:25.018552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass>
26552 10:10:25.049901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
26553 10:10:25.050352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
26555 10:10:25.080752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
26556 10:10:25.081191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
26558 10:10:25.116481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
26559 10:10:25.116917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
26561 10:10:25.150982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass
26563 10:10:25.151403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass>
26564 10:10:25.182170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
26566 10:10:25.182669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
26567 10:10:25.212657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
26568 10:10:25.213021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
26570 10:10:25.244186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
26571 10:10:25.244531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
26573 10:10:25.275244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass>
26574 10:10:25.275596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass
26576 10:10:25.307697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
26577 10:10:25.308040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
26579 10:10:25.339561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
26580 10:10:25.339925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
26582 10:10:25.370458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
26583 10:10:25.370737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
26585 10:10:25.400984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass>
26586 10:10:25.401341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass
26588 10:10:25.432091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
26589 10:10:25.432461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
26591 10:10:25.464275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
26592 10:10:25.464621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
26594 10:10:25.495833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
26595 10:10:25.496117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
26597 10:10:25.526634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass>
26598 10:10:25.526973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass
26600 10:10:25.557301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
26602 10:10:25.557736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
26603 10:10:25.588349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
26604 10:10:25.588691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
26606 10:10:25.619997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
26607 10:10:25.620339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
26609 10:10:25.652152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass>
26610 10:10:25.652490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass
26612 10:10:25.683216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
26614 10:10:25.683742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
26615 10:10:25.714967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
26616 10:10:25.715395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
26618 10:10:25.746286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
26619 10:10:25.746643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
26621 10:10:25.777478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass
26623 10:10:25.777987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass>
26624 10:10:25.808993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
26625 10:10:25.809438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
26627 10:10:25.840934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
26628 10:10:25.841401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
26630 10:10:25.872245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
26631 10:10:25.872695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
26633 10:10:25.903423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass>
26634 10:10:25.903798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass
26636 10:10:25.934351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
26637 10:10:25.934628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
26639 10:10:25.965080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
26640 10:10:25.965426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
26642 10:10:25.997489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
26644 10:10:25.998096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
26645 10:10:26.028460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass>
26646 10:10:26.028918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass
26648 10:10:26.059617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
26649 10:10:26.060074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
26651 10:10:26.090750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
26652 10:10:26.091175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
26654 10:10:26.121777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
26655 10:10:26.122215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
26657 10:10:26.155042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass
26659 10:10:26.155587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass>
26660 10:10:26.187371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
26662 10:10:26.187998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
26663 10:10:26.220551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
26664 10:10:26.221017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
26666 10:10:26.252110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
26667 10:10:26.252571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
26669 10:10:26.283583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass
26671 10:10:26.284152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass>
26672 10:10:26.315645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
26673 10:10:26.316085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
26675 10:10:26.347398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
26676 10:10:26.347820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
26678 10:10:26.378324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
26679 10:10:26.378680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
26681 10:10:26.408831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass
26683 10:10:26.409279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass>
26684 10:10:26.439359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
26685 10:10:26.439716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
26687 10:10:26.470620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
26688 10:10:26.470979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
26690 10:10:26.502410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
26692 10:10:26.502859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
26693 10:10:26.532895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass
26695 10:10:26.533341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass>
26696 10:10:26.564929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
26697 10:10:26.565284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
26699 10:10:26.595394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
26700 10:10:26.595764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
26702 10:10:26.628663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
26703 10:10:26.629031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
26705 10:10:26.663730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass>
26706 10:10:26.664097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass
26708 10:10:26.694792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
26709 10:10:26.695071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
26711 10:10:26.726252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
26713 10:10:26.726518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
26714 10:10:26.756713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
26715 10:10:26.757085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
26717 10:10:26.788444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass>
26718 10:10:26.788966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass
26720 10:10:26.822630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
26722 10:10:26.822993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
26723 10:10:26.854797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
26724 10:10:26.855151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
26726 10:10:26.886882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
26727 10:10:26.887246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
26729 10:10:26.918811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass>
26730 10:10:26.919174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass
26732 10:10:26.950236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
26733 10:10:26.950604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
26735 10:10:26.982420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
26736 10:10:26.982814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
26738 10:10:27.014370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
26739 10:10:27.014714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
26741 10:10:27.044607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass>
26742 10:10:27.044889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass
26744 10:10:27.075755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
26746 10:10:27.076030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
26747 10:10:27.106609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
26748 10:10:27.107020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
26750 10:10:27.138094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
26751 10:10:27.138468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
26753 10:10:27.169991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass
26755 10:10:27.170399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass>
26756 10:10:27.200636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
26757 10:10:27.200913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
26759 10:10:27.232069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
26760 10:10:27.232416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
26762 10:10:27.262704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
26763 10:10:27.263068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
26765 10:10:27.293754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass
26767 10:10:27.294219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass>
26768 10:10:27.325277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
26770 10:10:27.325757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
26771 10:10:27.357578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
26773 10:10:27.358172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
26774 10:10:27.410790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
26775 10:10:27.411249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
26777 10:10:27.442676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass
26779 10:10:27.443271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass>
26780 10:10:27.473644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
26781 10:10:27.473928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
26783 10:10:27.505769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
26784 10:10:27.506048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
26786 10:10:27.537357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
26788 10:10:27.537631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
26789 10:10:27.568189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass
26791 10:10:27.568453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass>
26792 10:10:27.598783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
26793 10:10:27.599047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
26795 10:10:27.630250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
26796 10:10:27.630524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
26798 10:10:27.661067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
26799 10:10:27.661342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
26801 10:10:27.694119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass>
26802 10:10:27.694391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass
26804 10:10:27.725880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
26805 10:10:27.726151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
26807 10:10:27.757281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
26809 10:10:27.757758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
26810 10:10:27.788122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
26811 10:10:27.788467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
26813 10:10:27.818737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass>
26814 10:10:27.819085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass
26816 10:10:27.849769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
26817 10:10:27.850223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
26819 10:10:27.881312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
26821 10:10:27.881997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
26822 10:10:27.916602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
26823 10:10:27.917074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
26825 10:10:27.949525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass
26827 10:10:27.949983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass>
26828 10:10:27.982586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
26829 10:10:27.983048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
26831 10:10:28.015125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
26832 10:10:28.015535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
26834 10:10:28.049005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
26835 10:10:28.049434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
26837 10:10:28.084125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass>
26838 10:10:28.084613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass
26840 10:10:28.122311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
26842 10:10:28.122737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
26843 10:10:28.156965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
26845 10:10:28.157490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
26846 10:10:28.191081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
26847 10:10:28.191535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
26849 10:10:28.226015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass>
26850 10:10:28.226402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass
26852 10:10:28.259426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
26853 10:10:28.259830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
26855 10:10:28.291261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
26856 10:10:28.291529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
26858 10:10:28.322559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
26860 10:10:28.322821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
26861 10:10:28.353955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass
26863 10:10:28.354218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass>
26864 10:10:28.384954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
26865 10:10:28.385213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
26867 10:10:28.417670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
26868 10:10:28.417930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
26870 10:10:28.448781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
26871 10:10:28.449040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
26873 10:10:28.480122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass
26875 10:10:28.480376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass>
26876 10:10:28.511083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
26877 10:10:28.511438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
26879 10:10:28.542373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
26880 10:10:28.542765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
26882 10:10:28.574938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
26884 10:10:28.575488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
26885 10:10:28.606254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass>
26886 10:10:28.606687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass
26888 10:10:28.637428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
26890 10:10:28.637997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
26891 10:10:28.669434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
26893 10:10:28.669887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
26894 10:10:28.700947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
26895 10:10:28.701332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
26897 10:10:28.732716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass>
26898 10:10:28.733063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass
26900 10:10:28.764575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
26902 10:10:28.765048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
26903 10:10:28.795809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
26904 10:10:28.796276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
26906 10:10:28.827314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
26907 10:10:28.827787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
26909 10:10:28.858534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass>
26910 10:10:28.858983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass
26912 10:10:28.890245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
26913 10:10:28.890716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
26915 10:10:28.924050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
26916 10:10:28.924455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
26918 10:10:28.955180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
26919 10:10:28.955455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
26921 10:10:28.986573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass>
26922 10:10:28.986855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass
26924 10:10:29.017992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
26926 10:10:29.018280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
26927 10:10:29.048462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
26928 10:10:29.048760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
26930 10:10:29.080382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
26931 10:10:29.080787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
26933 10:10:29.112433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass>
26934 10:10:29.112870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass
26936 10:10:29.144433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
26938 10:10:29.144991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
26939 10:10:29.175954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
26940 10:10:29.176404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
26942 10:10:29.208005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
26944 10:10:29.208450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
26945 10:10:29.240631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass>
26946 10:10:29.241065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass
26948 10:10:29.274085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
26950 10:10:29.274530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
26951 10:10:29.306179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
26953 10:10:29.306619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
26954 10:10:29.337221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
26956 10:10:29.337832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
26957 10:10:29.369894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass>
26958 10:10:29.370367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass
26960 10:10:29.404766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
26961 10:10:29.405242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
26963 10:10:29.439833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
26965 10:10:29.440443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
26966 10:10:29.471647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
26967 10:10:29.472190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
26969 10:10:29.506033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass>
26970 10:10:29.506486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass
26972 10:10:29.537964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
26973 10:10:29.538416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
26975 10:10:29.568753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
26976 10:10:29.569157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
26978 10:10:29.601106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
26980 10:10:29.601755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
26981 10:10:29.633065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass
26983 10:10:29.633733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass>
26984 10:10:29.664786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
26985 10:10:29.665277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
26987 10:10:29.698067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
26988 10:10:29.698464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
26990 10:10:29.731141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
26991 10:10:29.731526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
26993 10:10:29.764187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass>
26994 10:10:29.764476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass
26996 10:10:29.796741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
26997 10:10:29.797071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
26999 10:10:29.833375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
27001 10:10:29.833863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
27002 10:10:29.867921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
27003 10:10:29.868297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
27005 10:10:29.902358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass>
27006 10:10:29.902752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass
27008 10:10:29.938376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
27009 10:10:29.938758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
27011 10:10:29.970343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
27013 10:10:29.970765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
27014 10:10:30.001961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
27016 10:10:30.002553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
27017 10:10:30.034620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass>
27018 10:10:30.035074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass
27020 10:10:30.066387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
27022 10:10:30.066966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
27023 10:10:30.098161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
27024 10:10:30.098623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
27026 10:10:30.130700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
27027 10:10:30.131156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
27029 10:10:30.162923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass>
27030 10:10:30.163349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass
27032 10:10:30.194859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
27033 10:10:30.195371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
27035 10:10:30.227778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
27037 10:10:30.228342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
27038 10:10:30.259617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
27039 10:10:30.260085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
27041 10:10:30.292061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass
27043 10:10:30.292622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass>
27044 10:10:30.328525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
27045 10:10:30.328951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
27047 10:10:30.362979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
27048 10:10:30.363361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
27050 10:10:30.396853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
27051 10:10:30.397248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
27053 10:10:30.429478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass
27055 10:10:30.430012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass>
27056 10:10:30.461861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
27057 10:10:30.462237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
27059 10:10:30.499617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
27060 10:10:30.500013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
27062 10:10:30.531470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
27064 10:10:30.531777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
27065 10:10:30.563157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass
27067 10:10:30.563472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass>
27068 10:10:30.594332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
27070 10:10:30.594897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
27071 10:10:30.625176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
27073 10:10:30.625757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
27074 10:10:30.656709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
27076 10:10:30.657155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
27077 10:10:30.687621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass
27079 10:10:30.688210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass>
27080 10:10:30.718664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
27081 10:10:30.718991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
27083 10:10:30.750892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
27084 10:10:30.751382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
27086 10:10:30.782408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
27087 10:10:30.782849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
27089 10:10:30.813355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass
27091 10:10:30.814037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass>
27092 10:10:30.848533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
27093 10:10:30.849209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
27095 10:10:30.883250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
27096 10:10:30.883609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
27098 10:10:30.915796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
27099 10:10:30.916164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
27101 10:10:30.947006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass
27103 10:10:30.947370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass>
27104 10:10:30.979120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
27105 10:10:30.979532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
27107 10:10:31.011197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
27108 10:10:31.011573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
27110 10:10:31.043376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
27112 10:10:31.044001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
27113 10:10:31.075951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass>
27114 10:10:31.076297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass
27116 10:10:31.107401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
27117 10:10:31.107745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
27119 10:10:31.139239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
27120 10:10:31.139601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
27122 10:10:31.170570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
27123 10:10:31.170931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
27125 10:10:31.201329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass
27127 10:10:31.201845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass>
27128 10:10:31.232621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
27129 10:10:31.233081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
27131 10:10:31.264744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
27132 10:10:31.265195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
27134 10:10:31.296227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
27135 10:10:31.296680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
27137 10:10:31.328631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass
27139 10:10:31.329292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass>
27140 10:10:31.362688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
27141 10:10:31.363186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
27143 10:10:31.395897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
27144 10:10:31.396307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
27146 10:10:31.428391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
27147 10:10:31.428915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
27149 10:10:31.460188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass>
27150 10:10:31.460670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass
27152 10:10:31.492583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
27153 10:10:31.493030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
27155 10:10:31.525116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
27157 10:10:31.525612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
27158 10:10:31.556597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
27159 10:10:31.556959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
27161 10:10:31.588069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass
27163 10:10:31.588564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass>
27164 10:10:31.619449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
27165 10:10:31.619809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
27167 10:10:31.652040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
27169 10:10:31.652533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
27170 10:10:31.684385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
27171 10:10:31.684737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
27173 10:10:31.716662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass>
27174 10:10:31.716943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass
27176 10:10:31.751217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
27177 10:10:31.751505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
27179 10:10:31.784598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
27180 10:10:31.784967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
27182 10:10:31.822508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
27183 10:10:31.822920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
27185 10:10:31.866685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass>
27186 10:10:31.867080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass
27188 10:10:31.898492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
27190 10:10:31.898932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
27191 10:10:31.930583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
27192 10:10:31.930992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
27194 10:10:31.963427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
27195 10:10:31.963809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
27197 10:10:31.998482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass
27199 10:10:31.998903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass>
27200 10:10:32.038621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
27201 10:10:32.039086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
27203 10:10:32.074534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
27204 10:10:32.074908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
27206 10:10:32.108340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
27207 10:10:32.108746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
27209 10:10:32.143333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass>
27210 10:10:32.143711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass
27212 10:10:32.178461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
27213 10:10:32.178858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
27215 10:10:32.214450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
27217 10:10:32.214872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
27218 10:10:32.248318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
27219 10:10:32.248729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
27221 10:10:32.280209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass>
27222 10:10:32.280692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass
27224 10:10:32.312679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
27225 10:10:32.313160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
27227 10:10:32.345009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
27229 10:10:32.345666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
27230 10:10:32.376517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
27231 10:10:32.376812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
27233 10:10:32.410000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass>
27234 10:10:32.410332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass
27236 10:10:32.441879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
27238 10:10:32.442323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
27239 10:10:32.475007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
27240 10:10:32.475349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
27242 10:10:32.532381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
27243 10:10:32.532824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
27245 10:10:32.563962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass
27247 10:10:32.564406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass>
27248 10:10:32.595397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
27249 10:10:32.595793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
27251 10:10:32.630023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
27252 10:10:32.630458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
27254 10:10:32.662270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
27256 10:10:32.662831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
27257 10:10:32.694301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass>
27258 10:10:32.694768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass
27260 10:10:32.726256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
27261 10:10:32.726688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
27263 10:10:32.758448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
27264 10:10:32.758901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
27266 10:10:32.792613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
27267 10:10:32.793085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
27269 10:10:32.826160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass>
27270 10:10:32.826592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass
27272 10:10:32.858484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
27274 10:10:32.859030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
27275 10:10:32.890021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
27276 10:10:32.890460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
27278 10:10:32.922057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
27279 10:10:32.922471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
27281 10:10:32.953623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass>
27282 10:10:32.954072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass
27284 10:10:32.984669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
27285 10:10:32.985110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
27287 10:10:33.016955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
27288 10:10:33.017374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
27290 10:10:33.050571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
27291 10:10:33.050975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
27293 10:10:33.084176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass>
27294 10:10:33.084635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass
27296 10:10:33.118288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
27297 10:10:33.118774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
27299 10:10:33.154558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
27300 10:10:33.155037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
27302 10:10:33.186378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
27303 10:10:33.186778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
27305 10:10:33.218539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass>
27306 10:10:33.218920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass
27308 10:10:33.259565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
27309 10:10:33.260021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
27311 10:10:33.293347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
27313 10:10:33.293784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
27314 10:10:33.326970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
27315 10:10:33.327374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
27317 10:10:33.358643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass>
27318 10:10:33.359066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass
27320 10:10:33.391431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
27321 10:10:33.391838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
27323 10:10:33.423744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
27324 10:10:33.424192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
27326 10:10:33.455244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
27328 10:10:33.455797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
27329 10:10:33.487805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass>
27330 10:10:33.488268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass
27332 10:10:33.520856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
27333 10:10:33.521327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
27335 10:10:33.552936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
27337 10:10:33.553574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
27338 10:10:33.586699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
27340 10:10:33.587326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
27341 10:10:33.619932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass
27343 10:10:33.620583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass>
27344 10:10:33.652610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
27345 10:10:33.653098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
27347 10:10:33.685276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
27349 10:10:33.685923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
27350 10:10:33.718231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
27351 10:10:33.718673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
27353 10:10:33.750435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass>
27354 10:10:33.750885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass
27356 10:10:33.783042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
27358 10:10:33.783668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
27359 10:10:33.814925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
27360 10:10:33.815386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
27362 10:10:33.848205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
27364 10:10:33.848802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
27365 10:10:33.879772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass
27367 10:10:33.880307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass>
27368 10:10:33.911857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
27369 10:10:33.912315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
27371 10:10:33.943342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
27372 10:10:33.943736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
27374 10:10:33.974826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
27375 10:10:33.975218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
27377 10:10:34.006245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass
27379 10:10:34.006777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass>
27380 10:10:34.038151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
27382 10:10:34.038680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
27383 10:10:34.070177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
27384 10:10:34.070551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
27386 10:10:34.102484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
27387 10:10:34.102875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
27389 10:10:34.134871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass>
27390 10:10:34.135252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass
27392 10:10:34.169879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
27394 10:10:34.170333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
27395 10:10:34.204650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
27396 10:10:34.205009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
27398 10:10:34.239685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
27399 10:10:34.240044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
27401 10:10:34.275432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass>
27402 10:10:34.275795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass
27404 10:10:34.310691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
27405 10:10:34.310980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
27407 10:10:34.346621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
27408 10:10:34.346914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
27410 10:10:34.381900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
27411 10:10:34.382248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
27413 10:10:34.415925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass>
27414 10:10:34.416336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass
27416 10:10:34.450725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
27417 10:10:34.451102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
27419 10:10:34.487935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
27421 10:10:34.488501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
27422 10:10:34.522491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
27423 10:10:34.522858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
27425 10:10:34.557810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass
27427 10:10:34.558161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass>
27428 10:10:34.592554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
27429 10:10:34.593041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
27431 10:10:34.630404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
27432 10:10:34.630859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
27434 10:10:34.667265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
27435 10:10:34.667773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
27437 10:10:34.702867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass>
27438 10:10:34.703291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass
27440 10:10:34.737706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
27441 10:10:34.738065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
27443 10:10:34.775071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
27444 10:10:34.775384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
27446 10:10:34.811285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
27447 10:10:34.811548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
27449 10:10:34.847076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass>
27450 10:10:34.847440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass
27452 10:10:34.884220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
27453 10:10:34.884635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
27455 10:10:34.920867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
27456 10:10:34.921239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
27458 10:10:34.959047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
27459 10:10:34.959422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
27461 10:10:34.994702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass
27463 10:10:34.995198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass>
27464 10:10:35.030158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
27465 10:10:35.030558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
27467 10:10:35.066214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
27468 10:10:35.066623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
27470 10:10:35.102719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
27471 10:10:35.103068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
27473 10:10:35.139045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass
27475 10:10:35.139782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass>
27476 10:10:35.174862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
27477 10:10:35.175218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
27479 10:10:35.211035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
27480 10:10:35.211432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
27482 10:10:35.249474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
27484 10:10:35.249897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
27485 10:10:35.299255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass>
27486 10:10:35.299684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass
27488 10:10:35.335677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
27489 10:10:35.336141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
27491 10:10:35.371261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
27492 10:10:35.371725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
27494 10:10:35.410756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
27495 10:10:35.411192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
27497 10:10:35.448204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass>
27498 10:10:35.448565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass
27500 10:10:35.484293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
27501 10:10:35.484938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
27503 10:10:35.538062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
27504 10:10:35.538515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
27506 10:10:35.583969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
27508 10:10:35.584278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
27509 10:10:35.619026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass
27511 10:10:35.619467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass>
27512 10:10:35.652319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
27513 10:10:35.652679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
27515 10:10:35.683485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
27516 10:10:35.683885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
27518 10:10:35.715984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
27519 10:10:35.716360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
27521 10:10:35.748186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass
27523 10:10:35.748625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass>
27524 10:10:35.779617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
27525 10:10:35.780011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
27527 10:10:35.812026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
27528 10:10:35.812418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
27530 10:10:35.843904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
27532 10:10:35.844503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
27533 10:10:35.875199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass>
27534 10:10:35.875602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass
27536 10:10:35.908184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
27537 10:10:35.908566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
27539 10:10:35.940717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
27540 10:10:35.941193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
27542 10:10:35.975415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
27543 10:10:35.975870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
27545 10:10:36.007586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass>
27546 10:10:36.007966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass
27548 10:10:36.042554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
27549 10:10:36.043032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
27551 10:10:36.075596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
27552 10:10:36.076072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
27554 10:10:36.107908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
27555 10:10:36.108217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
27557 10:10:36.142418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass>
27558 10:10:36.142714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass
27560 10:10:36.175572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
27562 10:10:36.175801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
27563 10:10:36.209495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
27565 10:10:36.210134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
27566 10:10:36.241516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
27568 10:10:36.241989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
27569 10:10:36.273803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass>
27570 10:10:36.274234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass
27572 10:10:36.306116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
27573 10:10:36.306589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
27575 10:10:36.337948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
27576 10:10:36.338342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
27578 10:10:36.370270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
27579 10:10:36.370621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
27581 10:10:36.401780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass>
27582 10:10:36.402237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass
27584 10:10:36.434111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
27585 10:10:36.434498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
27587 10:10:36.466768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
27589 10:10:36.467229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
27590 10:10:36.498710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
27591 10:10:36.499102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
27593 10:10:36.530896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass>
27594 10:10:36.531380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass
27596 10:10:36.562325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
27597 10:10:36.562744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
27599 10:10:36.594500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
27600 10:10:36.594972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
27602 10:10:36.626501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
27603 10:10:36.626947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
27605 10:10:36.658570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass>
27606 10:10:36.659051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass
27608 10:10:36.690675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
27610 10:10:36.691244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
27611 10:10:36.722501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
27612 10:10:36.723026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
27614 10:10:36.757506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
27616 10:10:36.758151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
27617 10:10:36.790960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass>
27618 10:10:36.791422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass
27620 10:10:36.823327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
27621 10:10:36.823803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
27623 10:10:36.857426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
27625 10:10:36.858050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
27626 10:10:36.890545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
27627 10:10:36.890947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
27629 10:10:36.923649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass>
27630 10:10:36.924063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass
27632 10:10:36.957370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
27634 10:10:36.957815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
27635 10:10:36.990885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
27636 10:10:36.991346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
27638 10:10:37.024815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
27639 10:10:37.025208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
27641 10:10:37.058219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass>
27642 10:10:37.058479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass
27644 10:10:37.090532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
27645 10:10:37.090937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
27647 10:10:37.123496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
27649 10:10:37.123961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
27650 10:10:37.156464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
27652 10:10:37.156921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
27653 10:10:37.188244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass>
27654 10:10:37.188654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass
27656 10:10:37.220659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
27657 10:10:37.221124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
27659 10:10:37.252707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
27660 10:10:37.253083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
27662 10:10:37.284288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
27663 10:10:37.284648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
27665 10:10:37.315642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass>
27666 10:10:37.315995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass
27668 10:10:37.347322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
27669 10:10:37.347605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
27671 10:10:37.379005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
27672 10:10:37.379373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
27674 10:10:37.411018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
27675 10:10:37.411418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
27677 10:10:37.443051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass>
27678 10:10:37.443456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass
27680 10:10:37.477015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
27681 10:10:37.477409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
27683 10:10:37.510123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
27684 10:10:37.510525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
27686 10:10:37.541553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
27688 10:10:37.541997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
27689 10:10:37.573662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass>
27690 10:10:37.574081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass
27692 10:10:37.610320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
27693 10:10:37.610708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
27695 10:10:37.659892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
27696 10:10:37.660302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
27698 10:10:37.692399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
27699 10:10:37.692805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
27701 10:10:37.725015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass
27703 10:10:37.725470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass>
27704 10:10:37.756922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
27705 10:10:37.757330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
27707 10:10:37.789400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
27709 10:10:37.789852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
27710 10:10:37.824985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
27711 10:10:37.825409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
27713 10:10:37.861707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass
27715 10:10:37.862116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass>
27716 10:10:37.893385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
27718 10:10:37.893765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
27719 10:10:37.924927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
27720 10:10:37.925279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
27722 10:10:37.956182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
27724 10:10:37.956471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
27725 10:10:37.987259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass
27727 10:10:37.987763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass>
27728 10:10:38.018725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
27729 10:10:38.019089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
27731 10:10:38.050568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
27732 10:10:38.050935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
27734 10:10:38.082259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
27735 10:10:38.082608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
27737 10:10:38.113446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass
27739 10:10:38.114063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass>
27740 10:10:38.146003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
27741 10:10:38.146468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
27743 10:10:38.178261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
27744 10:10:38.178664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
27746 10:10:38.210638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
27747 10:10:38.211036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
27749 10:10:38.242146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=pass
27751 10:10:38.242614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=pass>
27752 10:10:38.273742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass
27754 10:10:38.274173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass>
27755 10:10:38.304708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass>
27756 10:10:38.304986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass
27758 10:10:38.336053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass
27760 10:10:38.336332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass>
27761 10:10:38.366990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass>
27762 10:10:38.367445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass
27764 10:10:38.398329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass>
27765 10:10:38.398706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass
27767 10:10:38.430095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass>
27768 10:10:38.430503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass
27770 10:10:38.461719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass>
27771 10:10:38.462098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass
27773 10:10:38.492890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass>
27774 10:10:38.493232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass
27776 10:10:38.524124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass
27778 10:10:38.524678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass>
27779 10:10:38.555438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass>
27780 10:10:38.555833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass
27782 10:10:38.586616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass>
27783 10:10:38.586992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass
27785 10:10:38.620263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass>
27786 10:10:38.620679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass
27788 10:10:38.653339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass
27790 10:10:38.653850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass>
27791 10:10:38.684759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass>
27792 10:10:38.685178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass
27794 10:10:38.717219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass>
27795 10:10:38.717631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass
27797 10:10:38.749948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass
27799 10:10:38.750588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass>
27800 10:10:38.782270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass
27802 10:10:38.782873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass>
27803 10:10:38.814113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass>
27804 10:10:38.814508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass
27806 10:10:38.846503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass>
27807 10:10:38.846919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass
27809 10:10:38.879471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass
27811 10:10:38.880010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass>
27812 10:10:38.910778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass>
27813 10:10:38.911132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass
27815 10:10:38.941823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass>
27816 10:10:38.942169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass
27818 10:10:38.973975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass>
27819 10:10:38.974316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass
27821 10:10:39.005395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
27823 10:10:39.005835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
27824 10:10:39.037965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass
27826 10:10:39.038578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass>
27827 10:10:39.071029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
27829 10:10:39.071584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
27830 10:10:39.104233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass>
27831 10:10:39.104749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass
27833 10:10:39.136708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass
27835 10:10:39.137000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass>
27836 10:10:39.168682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass
27838 10:10:39.169245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass>
27839 10:10:39.200344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass>
27840 10:10:39.200807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass
27842 10:10:39.232700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass>
27843 10:10:39.233088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass
27845 10:10:39.266553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass>
27846 10:10:39.266907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass
27848 10:10:39.302632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass
27850 10:10:39.303080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass>
27851 10:10:39.335431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip>
27852 10:10:39.335883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip
27854 10:10:39.367016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip
27856 10:10:39.367679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip>
27857 10:10:39.398218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass>
27858 10:10:39.398497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass
27860 10:10:39.429233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass
27862 10:10:39.429519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass>
27863 10:10:39.460483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass>
27864 10:10:39.460873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass
27866 10:10:39.494119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass
27868 10:10:39.494571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass>
27869 10:10:39.526087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip
27871 10:10:39.526648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip>
27872 10:10:39.557727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip>
27873 10:10:39.558159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip
27875 10:10:39.588647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass
27877 10:10:39.589143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass>
27878 10:10:39.619849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip>
27879 10:10:39.620253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip
27881 10:10:39.652497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip
27883 10:10:39.653062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip>
27884 10:10:39.683936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass
27886 10:10:39.684386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass>
27887 10:10:39.715376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip>
27888 10:10:39.715772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip
27890 10:10:39.746874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip
27892 10:10:39.747372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip>
27893 10:10:39.778462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass>
27894 10:10:39.778862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass
27896 10:10:39.810591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass
27898 10:10:39.811178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass>
27899 10:10:39.842167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass
27901 10:10:39.842731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass>
27902 10:10:39.873800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass>
27903 10:10:39.874264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass
27905 10:10:39.906028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip>
27906 10:10:39.906482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip
27908 10:10:39.937231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip
27910 10:10:39.937809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip>
27911 10:10:39.968278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass
27913 10:10:39.968846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass>
27914 10:10:39.998789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip>
27915 10:10:39.999133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip
27917 10:10:40.030320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip>
27918 10:10:40.030666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip
27920 10:10:40.060724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass
27922 10:10:40.061147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass>
27923 10:10:40.092306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip>
27924 10:10:40.092662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip
27926 10:10:40.123776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip>
27927 10:10:40.124124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip
27929 10:10:40.154629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass>
27930 10:10:40.154978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass
27932 10:10:40.186575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip
27934 10:10:40.187003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip>
27935 10:10:40.218405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip>
27936 10:10:40.218857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip
27938 10:10:40.250136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass>
27939 10:10:40.250529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass
27941 10:10:40.281449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip
27943 10:10:40.281778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip>
27944 10:10:40.312454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip>
27945 10:10:40.312730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip
27947 10:10:40.343299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass>
27948 10:10:40.343574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass
27950 10:10:40.374727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip>
27951 10:10:40.375001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip
27953 10:10:40.406721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip>
27954 10:10:40.407074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip
27956 10:10:40.437673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass>
27957 10:10:40.438028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass
27959 10:10:40.468411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip>
27960 10:10:40.468823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip
27962 10:10:40.500228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip
27964 10:10:40.500660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip>
27965 10:10:40.532373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass
27967 10:10:40.532803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass>
27968 10:10:40.563999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass>
27969 10:10:40.564420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass
27971 10:10:40.595732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass
27973 10:10:40.596248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass>
27974 10:10:40.626964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass>
27975 10:10:40.627280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass
27977 10:10:40.658991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip>
27978 10:10:40.659411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip
27980 10:10:40.690906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip
27982 10:10:40.691458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip>
27983 10:10:40.721973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass
27985 10:10:40.722441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass>
27986 10:10:40.752859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip>
27987 10:10:40.753204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip
27989 10:10:40.783770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip>
27990 10:10:40.784112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip
27992 10:10:40.814832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass>
27993 10:10:40.815107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass
27995 10:10:40.846143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip>
27996 10:10:40.846491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip
27998 10:10:40.876557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip
28000 10:10:40.876981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip>
28001 10:10:40.908311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass>
28002 10:10:40.908652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass
28004 10:10:40.939030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip>
28005 10:10:40.939395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip
28007 10:10:40.970068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip>
28008 10:10:40.970428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip
28010 10:10:41.000613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass
28012 10:10:41.001035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass>
28013 10:10:41.031565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip>
28014 10:10:41.031918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip
28016 10:10:41.062798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip>
28017 10:10:41.063192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip
28019 10:10:41.095159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass
28021 10:10:41.095703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass>
28022 10:10:41.126331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip>
28023 10:10:41.126720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip
28025 10:10:41.157857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip>
28026 10:10:41.158201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip
28028 10:10:41.190265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass>
28029 10:10:41.190730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass
28031 10:10:41.221980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip
28033 10:10:41.222459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip>
28034 10:10:41.253758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip>
28035 10:10:41.254101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip
28037 10:10:41.284792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass
28039 10:10:41.285206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass>
28040 10:10:41.315792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip>
28041 10:10:41.316149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip
28043 10:10:41.346897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip>
28044 10:10:41.347349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip
28046 10:10:41.378016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass>
28047 10:10:41.378453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass
28049 10:10:41.408855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip>
28050 10:10:41.409289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip
28052 10:10:41.440044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip>
28053 10:10:41.440505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip
28055 10:10:41.471136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass>
28056 10:10:41.471456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass
28058 10:10:41.502426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip>
28059 10:10:41.502704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip
28061 10:10:41.533584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip>
28062 10:10:41.533970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip
28064 10:10:41.564014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass
28066 10:10:41.564520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass>
28067 10:10:41.594976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip
28069 10:10:41.595259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip>
28070 10:10:41.625565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip>
28071 10:10:41.625844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip
28073 10:10:41.657025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass
28075 10:10:41.657576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass>
28076 10:10:41.687906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip
28078 10:10:41.688431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip>
28079 10:10:41.719917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip
28081 10:10:41.720454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip>
28082 10:10:41.750892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass
28084 10:10:41.751311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass>
28085 10:10:41.781815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip>
28086 10:10:41.782198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip
28088 10:10:41.812962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip>
28089 10:10:41.813360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip
28091 10:10:41.843952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass
28093 10:10:41.844513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass>
28094 10:10:41.874889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip>
28095 10:10:41.875323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip
28097 10:10:41.907064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip>
28098 10:10:41.907614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip
28100 10:10:41.938009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass
28102 10:10:41.938477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass>
28103 10:10:41.968896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip
28105 10:10:41.969369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip>
28106 10:10:41.999552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip>
28107 10:10:41.999918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip
28109 10:10:42.030541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass
28111 10:10:42.031012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass>
28112 10:10:42.061680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip>
28113 10:10:42.062068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip
28115 10:10:42.093043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip
28117 10:10:42.093486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip>
28118 10:10:42.124042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass>
28119 10:10:42.124418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass
28121 10:10:42.155097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip>
28122 10:10:42.155503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip
28124 10:10:42.186709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip>
28125 10:10:42.187090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip
28127 10:10:42.217512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass
28129 10:10:42.218072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass>
28130 10:10:42.250130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip
28132 10:10:42.250748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip>
28133 10:10:42.281148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip>
28134 10:10:42.281625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip
28136 10:10:42.311790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass
28138 10:10:42.312317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass>
28139 10:10:42.342984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip>
28140 10:10:42.343437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip
28142 10:10:42.374408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip>
28143 10:10:42.374847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip
28145 10:10:42.405035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass>
28146 10:10:42.405423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass
28148 10:10:42.436634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip
28150 10:10:42.437180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip>
28151 10:10:42.467677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip>
28152 10:10:42.468100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip
28154 10:10:42.499141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass
28156 10:10:42.499585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass>
28157 10:10:42.530367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip>
28158 10:10:42.530770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip
28160 10:10:42.561739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip>
28161 10:10:42.562203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip
28163 10:10:42.593058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass
28165 10:10:42.593517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass>
28166 10:10:42.624233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip
28168 10:10:42.624787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip>
28169 10:10:42.655567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip>
28170 10:10:42.655913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip
28172 10:10:42.686532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass>
28173 10:10:42.686873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass
28175 10:10:42.717868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip>
28176 10:10:42.718215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip
28178 10:10:42.769046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip>
28179 10:10:42.769508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip
28181 10:10:42.800156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass>
28182 10:10:42.800537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass
28184 10:10:42.831253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip>
28185 10:10:42.831712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip
28187 10:10:42.862899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip>
28188 10:10:42.863359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip
28190 10:10:42.894261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass>
28191 10:10:42.894661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass
28193 10:10:42.926414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip
28195 10:10:42.926839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip>
28196 10:10:42.958213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip>
28197 10:10:42.958599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip
28199 10:10:42.989215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass
28201 10:10:42.989632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass>
28202 10:10:43.019807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip>
28203 10:10:43.020084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip
28205 10:10:43.050632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip>
28206 10:10:43.050909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip
28208 10:10:43.082107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass>
28209 10:10:43.082475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass
28211 10:10:43.113509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip
28213 10:10:43.114010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip>
28214 10:10:43.144175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip>
28215 10:10:43.144528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip
28217 10:10:43.174997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass>
28218 10:10:43.175358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass
28220 10:10:43.205843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip
28222 10:10:43.206321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip>
28223 10:10:43.236394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip>
28224 10:10:43.236757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip
28226 10:10:43.267781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass
28228 10:10:43.268058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass>
28229 10:10:43.298852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip>
28230 10:10:43.299208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip
28232 10:10:43.330055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip
28234 10:10:43.330661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip>
28235 10:10:43.360921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass>
28236 10:10:43.361337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass
28238 10:10:43.392324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip>
28239 10:10:43.392702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip
28241 10:10:43.423245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip>
28242 10:10:43.423587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip
28244 10:10:43.454176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass>
28245 10:10:43.454624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass
28247 10:10:43.485486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip
28249 10:10:43.486050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip>
28250 10:10:43.516108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip>
28251 10:10:43.516454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip
28253 10:10:43.547290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass>
28254 10:10:43.547645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass
28256 10:10:43.578491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip>
28257 10:10:43.578879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip
28259 10:10:43.609719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip
28261 10:10:43.610259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip>
28262 10:10:43.640893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass>
28263 10:10:43.641329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass
28265 10:10:43.672873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip>
28266 10:10:43.673281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip
28268 10:10:43.704191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip
28270 10:10:43.704607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip>
28271 10:10:43.735814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass
28273 10:10:43.736234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass>
28274 10:10:43.767829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip>
28275 10:10:43.768283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip
28277 10:10:43.799294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip>
28278 10:10:43.799635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip
28280 10:10:43.831158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass
28282 10:10:43.831438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass>
28283 10:10:43.862103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip
28285 10:10:43.862384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip>
28286 10:10:43.893295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip
28288 10:10:43.893561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip>
28289 10:10:43.924393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass>
28290 10:10:43.924739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass
28292 10:10:43.955555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip>
28293 10:10:43.955951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip
28295 10:10:43.987351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip>
28296 10:10:43.987669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip
28298 10:10:44.018666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass>
28299 10:10:44.019024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass
28301 10:10:44.050142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip>
28302 10:10:44.050491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip
28304 10:10:44.080653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip>
28305 10:10:44.081000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip
28307 10:10:44.112106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass
28309 10:10:44.112523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass>
28310 10:10:44.144207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip>
28311 10:10:44.144582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip
28313 10:10:44.175311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip>
28314 10:10:44.175586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip
28316 10:10:44.206156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass
28318 10:10:44.206745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass>
28319 10:10:44.237655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip
28321 10:10:44.238186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip>
28322 10:10:44.269963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip>
28323 10:10:44.270306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip
28325 10:10:44.301544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass>
28326 10:10:44.301895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass
28328 10:10:44.332263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip>
28329 10:10:44.332599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip
28331 10:10:44.364202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip>
28332 10:10:44.364666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip
28334 10:10:44.395572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass
28336 10:10:44.395924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass>
28337 10:10:44.427091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip>
28338 10:10:44.427443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip
28340 10:10:44.458626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip>
28341 10:10:44.459088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip
28343 10:10:44.490741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass>
28344 10:10:44.491203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass
28346 10:10:44.522394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip>
28347 10:10:44.522833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip
28349 10:10:44.554193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip>
28350 10:10:44.554594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip
28352 10:10:44.586325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass>
28353 10:10:44.586769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass
28355 10:10:44.618391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip
28357 10:10:44.619020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip>
28358 10:10:44.650417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip>
28359 10:10:44.650874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip
28361 10:10:44.683005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass
28363 10:10:44.683443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass>
28364 10:10:44.714861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip>
28365 10:10:44.715257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip
28367 10:10:44.746318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip>
28368 10:10:44.746775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip
28370 10:10:44.777472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass
28372 10:10:44.778085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass>
28373 10:10:44.808651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip
28375 10:10:44.809092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip>
28376 10:10:44.840154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip>
28377 10:10:44.840543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip
28379 10:10:44.873083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass
28381 10:10:44.873610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass>
28382 10:10:44.906076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip>
28383 10:10:44.906496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip
28385 10:10:44.938469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip>
28386 10:10:44.938912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip
28388 10:10:44.969866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass>
28389 10:10:44.970334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass
28391 10:10:45.000656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip
28393 10:10:45.001280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip>
28394 10:10:45.033818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip>
28395 10:10:45.034282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip
28397 10:10:45.065908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass
28399 10:10:45.066446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass>
28400 10:10:45.099020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip
28402 10:10:45.099412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip>
28403 10:10:45.130598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip
28405 10:10:45.131159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip>
28406 10:10:45.162971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass>
28407 10:10:45.163247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass
28409 10:10:45.195252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip
28411 10:10:45.195535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip>
28412 10:10:45.226753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip
28414 10:10:45.227250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip>
28415 10:10:45.259229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass>
28416 10:10:45.259577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass
28418 10:10:45.292299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip>
28419 10:10:45.292647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip
28421 10:10:45.323560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip>
28422 10:10:45.323914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip
28424 10:10:45.354760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass>
28425 10:10:45.355108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass
28427 10:10:45.385911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip>
28428 10:10:45.386260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip
28430 10:10:45.416613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip>
28431 10:10:45.416970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip
28433 10:10:45.447755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass>
28434 10:10:45.448107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass
28436 10:10:45.478675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip
28438 10:10:45.479096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip>
28439 10:10:45.510148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip>
28440 10:10:45.510490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip
28442 10:10:45.541131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass>
28443 10:10:45.541493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass
28445 10:10:45.572668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip>
28446 10:10:45.573028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip
28448 10:10:45.604061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip>
28449 10:10:45.604410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip
28451 10:10:45.634890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass>
28452 10:10:45.635236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass
28454 10:10:45.666269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip
28456 10:10:45.666551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip>
28457 10:10:45.698097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip>
28458 10:10:45.698445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip
28460 10:10:45.729169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass>
28461 10:10:45.729570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass
28463 10:10:45.761541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip
28465 10:10:45.762175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip>
28466 10:10:45.793696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip
28468 10:10:45.794244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip>
28469 10:10:45.825057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass>
28470 10:10:45.825499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass
28472 10:10:45.856148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip>
28473 10:10:45.856500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip
28475 10:10:45.887340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip>
28476 10:10:45.887788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip
28478 10:10:45.919136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass>
28479 10:10:45.919586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass
28481 10:10:45.951975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip
28483 10:10:45.952656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip>
28484 10:10:45.983985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip
28486 10:10:45.984411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip>
28487 10:10:46.015027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass>
28488 10:10:46.015411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass
28490 10:10:46.046233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip>
28491 10:10:46.046601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip
28493 10:10:46.077501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip
28495 10:10:46.078046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip>
28496 10:10:46.109151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass
28498 10:10:46.109588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass>
28499 10:10:46.141507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip
28501 10:10:46.141948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip>
28502 10:10:46.172883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip>
28503 10:10:46.173284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip
28505 10:10:46.204041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass>
28506 10:10:46.204456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass
28508 10:10:46.235853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip>
28509 10:10:46.236275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip
28511 10:10:46.267606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip>
28512 10:10:46.267983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip
28514 10:10:46.299174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass
28516 10:10:46.299684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass>
28517 10:10:46.330428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip>
28518 10:10:46.330902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip
28520 10:10:46.362273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip>
28521 10:10:46.362635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip
28523 10:10:46.393926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass>
28524 10:10:46.394288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass
28526 10:10:46.425383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip
28528 10:10:46.425889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip>
28529 10:10:46.456307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip>
28530 10:10:46.456674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip
28532 10:10:46.487061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass>
28533 10:10:46.487423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass
28535 10:10:46.518348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip>
28536 10:10:46.518712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip
28538 10:10:46.549353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip
28540 10:10:46.549839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip>
28541 10:10:46.580432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass
28543 10:10:46.580996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass>
28544 10:10:46.611825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip
28546 10:10:46.612271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip>
28547 10:10:46.643529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip>
28548 10:10:46.643937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip
28550 10:10:46.674859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass
28552 10:10:46.675393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass>
28553 10:10:46.706583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip>
28554 10:10:46.706955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip
28556 10:10:46.737838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip>
28557 10:10:46.738116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip
28559 10:10:46.768553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass>
28560 10:10:46.768925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass
28562 10:10:46.799407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip>
28563 10:10:46.799764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip
28565 10:10:46.830391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip
28567 10:10:46.830856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip>
28568 10:10:46.861676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass
28570 10:10:46.862253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass>
28571 10:10:46.892896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip
28573 10:10:46.893320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip>
28574 10:10:46.924069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip>
28575 10:10:46.924345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip
28577 10:10:46.955801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass>
28578 10:10:46.956116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass
28580 10:10:46.987297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip>
28581 10:10:46.987581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip
28583 10:10:47.018533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip>
28584 10:10:47.018809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip
28586 10:10:47.050549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass
28588 10:10:47.050967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass>
28589 10:10:47.082321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip>
28590 10:10:47.082738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip
28592 10:10:47.114521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip>
28593 10:10:47.114879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip
28595 10:10:47.146330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass
28597 10:10:47.146762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass>
28598 10:10:47.178084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip
28600 10:10:47.178518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip>
28601 10:10:47.209351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip
28603 10:10:47.209818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip>
28604 10:10:47.240960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass>
28605 10:10:47.241359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass
28607 10:10:47.272160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip>
28608 10:10:47.272510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip
28610 10:10:47.304177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip
28612 10:10:47.304755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip>
28613 10:10:47.336003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass
28615 10:10:47.336462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass>
28616 10:10:47.367210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip>
28617 10:10:47.367556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip
28619 10:10:47.398392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip>
28620 10:10:47.398857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip
28622 10:10:47.429936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass>
28623 10:10:47.430336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass
28625 10:10:47.460927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip>
28626 10:10:47.461378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip
28628 10:10:47.492513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip
28630 10:10:47.493057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip>
28631 10:10:47.524122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass
28633 10:10:47.524548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass>
28634 10:10:47.555587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip>
28635 10:10:47.555989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip
28637 10:10:47.587577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip
28639 10:10:47.588006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip>
28640 10:10:47.618954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass
28642 10:10:47.619491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass>
28643 10:10:47.650563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip>
28644 10:10:47.651001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip
28646 10:10:47.682330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip
28648 10:10:47.682862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip>
28649 10:10:47.714078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass
28651 10:10:47.714612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass>
28652 10:10:47.745344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip
28654 10:10:47.745750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip>
28655 10:10:47.778319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip>
28656 10:10:47.778695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip
28658 10:10:47.810128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass
28660 10:10:47.810755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass>
28661 10:10:47.841878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip>
28662 10:10:47.842241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip
28664 10:10:47.895558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip>
28665 10:10:47.896029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip
28667 10:10:47.928433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass>
28668 10:10:47.928934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass
28670 10:10:47.960049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip
28672 10:10:47.960358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip>
28673 10:10:47.991875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip>
28674 10:10:47.992183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip
28676 10:10:48.024396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass>
28677 10:10:48.024811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass
28679 10:10:48.056513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip>
28680 10:10:48.056961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip
28682 10:10:48.088656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip
28684 10:10:48.089221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip>
28685 10:10:48.120377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass
28687 10:10:48.120786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass>
28688 10:10:48.151998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip
28690 10:10:48.152554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip>
28691 10:10:48.184255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip>
28692 10:10:48.184677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip
28694 10:10:48.217995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass
28696 10:10:48.218589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass>
28697 10:10:48.250128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip
28699 10:10:48.250748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip>
28700 10:10:48.281750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip>
28701 10:10:48.282162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip
28703 10:10:48.314373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass>
28704 10:10:48.314853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass
28706 10:10:48.347134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip
28708 10:10:48.347762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip>
28709 10:10:48.379853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip
28711 10:10:48.380482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip>
28712 10:10:48.411985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass>
28713 10:10:48.412445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass
28715 10:10:48.445148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip
28717 10:10:48.445750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip>
28718 10:10:48.478409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip>
28719 10:10:48.478817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip
28721 10:10:48.510877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass>
28722 10:10:48.511252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass
28724 10:10:48.542757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip>
28725 10:10:48.543107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip
28727 10:10:48.574126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip>
28728 10:10:48.574409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip
28730 10:10:48.605176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass
28732 10:10:48.605461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass>
28733 10:10:48.637980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip
28735 10:10:48.638260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip>
28736 10:10:48.669686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip>
28737 10:10:48.669962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip
28739 10:10:48.701843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass>
28740 10:10:48.702192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass
28742 10:10:48.733395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip
28744 10:10:48.733715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip>
28745 10:10:48.765477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip
28747 10:10:48.766034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip>
28748 10:10:48.797773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass
28750 10:10:48.798403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass>
28751 10:10:48.830339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip
28753 10:10:48.830980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip>
28754 10:10:48.863239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip>
28755 10:10:48.863723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip
28757 10:10:48.897086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass>
28758 10:10:48.897637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass
28760 10:10:48.931083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip>
28761 10:10:48.931546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip
28763 10:10:48.964246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip>
28764 10:10:48.964670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip
28766 10:10:48.996215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass
28768 10:10:48.996897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass>
28769 10:10:49.028056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip>
28770 10:10:49.028477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip
28772 10:10:49.059783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip>
28773 10:10:49.060106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip
28775 10:10:49.090723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass>
28776 10:10:49.091057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass
28778 10:10:49.122271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip>
28779 10:10:49.122613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip
28781 10:10:49.154026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip
28783 10:10:49.154470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip>
28784 10:10:49.186525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass>
28785 10:10:49.186918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass
28787 10:10:49.218893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip
28789 10:10:49.219431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip>
28790 10:10:49.250183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip>
28791 10:10:49.250533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip
28793 10:10:49.281623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass>
28794 10:10:49.281982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass
28796 10:10:49.315395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip
28798 10:10:49.315841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip>
28799 10:10:49.349641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip
28801 10:10:49.350071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip>
28802 10:10:49.383424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass>
28803 10:10:49.383770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass
28805 10:10:49.416594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip
28807 10:10:49.417123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip>
28808 10:10:49.449362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip
28810 10:10:49.449659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip>
28811 10:10:49.483323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass>
28812 10:10:49.483601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass
28814 10:10:49.516972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip>
28815 10:10:49.517338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip
28817 10:10:49.549436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip
28819 10:10:49.549730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip>
28820 10:10:49.581701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass>
28821 10:10:49.582057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass
28823 10:10:49.615262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip>
28824 10:10:49.615613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip
28826 10:10:49.649501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip
28828 10:10:49.649973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip>
28829 10:10:49.683111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass>
28830 10:10:49.683389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass
28832 10:10:49.716758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip>
28833 10:10:49.717034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip
28835 10:10:49.750323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip>
28836 10:10:49.750598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip
28838 10:10:49.783943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass
28840 10:10:49.784208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass>
28841 10:10:49.817132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip
28843 10:10:49.817773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip>
28844 10:10:49.850145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip>
28845 10:10:49.850611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip
28847 10:10:49.881428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass
28849 10:10:49.882012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass>
28850 10:10:49.914499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip>
28851 10:10:49.914914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip
28853 10:10:49.948209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip>
28854 10:10:49.948618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip
28856 10:10:49.980798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass>
28857 10:10:49.981221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass
28859 10:10:50.014358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip>
28860 10:10:50.014769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip
28862 10:10:50.047822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip
28864 10:10:50.048389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip>
28865 10:10:50.083114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass>
28866 10:10:50.083467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass
28868 10:10:50.116945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip>
28869 10:10:50.117224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip
28871 10:10:50.150391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip
28873 10:10:50.150670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip>
28874 10:10:50.182874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass>
28875 10:10:50.183302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass
28877 10:10:50.218483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip>
28878 10:10:50.218852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip
28880 10:10:50.250230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip
28882 10:10:50.250665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip>
28883 10:10:50.282056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass
28885 10:10:50.282459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass>
28886 10:10:50.313435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip
28888 10:10:50.313828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip>
28889 10:10:50.347260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip>
28890 10:10:50.347636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip
28892 10:10:50.381920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass>
28893 10:10:50.382334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass
28895 10:10:50.416714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip>
28896 10:10:50.417187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip
28898 10:10:50.451825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip>
28899 10:10:50.452233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip
28901 10:10:50.486756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass>
28902 10:10:50.487191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass
28904 10:10:50.520204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip>
28905 10:10:50.520672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip
28907 10:10:50.552855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip>
28908 10:10:50.553330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip
28910 10:10:50.586131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass
28912 10:10:50.586764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass>
28913 10:10:50.618522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip>
28914 10:10:50.618944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip
28916 10:10:50.651195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip>
28917 10:10:50.651669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip
28919 10:10:50.684532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass
28921 10:10:50.685167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass>
28922 10:10:50.717229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip
28924 10:10:50.717869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip>
28925 10:10:50.750124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip>
28926 10:10:50.750584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip
28928 10:10:50.782335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass>
28929 10:10:50.782773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass
28931 10:10:50.814817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip
28933 10:10:50.815265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip>
28934 10:10:50.848671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip>
28935 10:10:50.849111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip
28937 10:10:50.884018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass
28939 10:10:50.884496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass>
28940 10:10:50.919101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip>
28941 10:10:50.919517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip
28943 10:10:50.954251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip
28945 10:10:50.954684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip>
28946 10:10:50.988973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass
28948 10:10:50.989258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass>
28949 10:10:51.023151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip
28951 10:10:51.023527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip>
28952 10:10:51.055713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip
28954 10:10:51.056013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip>
28955 10:10:51.087520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass
28957 10:10:51.088158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass>
28958 10:10:51.119679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip
28960 10:10:51.120122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip>
28961 10:10:51.153034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip
28963 10:10:51.153492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip>
28964 10:10:51.186309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass
28966 10:10:51.186705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass>
28967 10:10:51.218589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip>
28968 10:10:51.218903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip
28970 10:10:51.250873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip>
28971 10:10:51.251175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip
28973 10:10:51.284526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass
28975 10:10:51.284982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass>
28976 10:10:51.318129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip>
28977 10:10:51.318494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip
28979 10:10:51.352986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip
28981 10:10:51.353428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip>
28982 10:10:51.387428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass
28984 10:10:51.387715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass>
28985 10:10:51.421762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip
28987 10:10:51.422040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip>
28988 10:10:51.457671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip>
28989 10:10:51.458077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip
28991 10:10:51.491140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass
28993 10:10:51.491427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass>
28994 10:10:51.527082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip
28996 10:10:51.527593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip>
28997 10:10:51.561687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip
28999 10:10:51.562183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip>
29000 10:10:51.595300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass
29002 10:10:51.595733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass>
29003 10:10:51.631788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip
29005 10:10:51.632299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip>
29006 10:10:51.667020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip>
29007 10:10:51.667373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip
29009 10:10:51.702365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass
29011 10:10:51.702644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass>
29012 10:10:51.736740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip
29014 10:10:51.737290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip>
29015 10:10:51.772362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip>
29016 10:10:51.772712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip
29018 10:10:51.806694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass>
29019 10:10:51.807053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass
29021 10:10:51.841869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip
29023 10:10:51.842288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip>
29024 10:10:51.875439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip>
29025 10:10:51.875799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip
29027 10:10:51.911683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass
29029 10:10:51.912116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass>
29030 10:10:51.948634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip
29032 10:10:51.949073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip>
29033 10:10:51.988566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip>
29034 10:10:51.988994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip
29036 10:10:52.027585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass>
29037 10:10:52.028033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass
29039 10:10:52.066994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip>
29040 10:10:52.067476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip
29042 10:10:52.104007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip
29044 10:10:52.104509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip>
29045 10:10:52.139782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass>
29046 10:10:52.140208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass
29048 10:10:52.176020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip>
29049 10:10:52.176396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip
29051 10:10:52.210383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip>
29052 10:10:52.210642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip
29054 10:10:52.243890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass>
29055 10:10:52.244284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass
29057 10:10:52.280157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip
29059 10:10:52.280605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip>
29060 10:10:52.318185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip
29062 10:10:52.318533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip>
29063 10:10:52.354020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass>
29064 10:10:52.354412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass
29066 10:10:52.391915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip>
29067 10:10:52.392343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip
29069 10:10:52.426927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip
29071 10:10:52.427361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip>
29072 10:10:52.461940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass>
29073 10:10:52.462407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass
29075 10:10:52.498610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip>
29076 10:10:52.498993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip
29078 10:10:52.534073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip
29080 10:10:52.534570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip>
29081 10:10:52.569073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass
29083 10:10:52.569569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass>
29084 10:10:52.605006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip>
29085 10:10:52.605373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip
29087 10:10:52.640253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip>
29088 10:10:52.640609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip
29090 10:10:52.676431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass>
29091 10:10:52.676789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass
29093 10:10:52.711859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip>
29094 10:10:52.712204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip
29096 10:10:52.746805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip>
29097 10:10:52.747155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip
29099 10:10:52.782732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass>
29100 10:10:52.783085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass
29102 10:10:52.819143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip
29104 10:10:52.819791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip>
29105 10:10:52.855410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip>
29106 10:10:52.855867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip
29108 10:10:52.891259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass>
29109 10:10:52.891715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass
29111 10:10:52.925997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip>
29112 10:10:52.926447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip
29114 10:10:52.960889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip
29116 10:10:52.961426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip>
29117 10:10:53.021167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass
29119 10:10:53.021637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass>
29120 10:10:53.058482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip
29122 10:10:53.059124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip>
29123 10:10:53.095357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip>
29124 10:10:53.095824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip
29126 10:10:53.128336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass
29128 10:10:53.128780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass>
29129 10:10:53.160608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip
29131 10:10:53.161050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip>
29132 10:10:53.194605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip
29134 10:10:53.195152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip>
29135 10:10:53.227923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass>
29136 10:10:53.228276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass
29138 10:10:53.262814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip>
29139 10:10:53.263192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip
29141 10:10:53.298234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip>
29142 10:10:53.298650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip
29144 10:10:53.333032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass
29146 10:10:53.333604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass>
29147 10:10:53.367712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip>
29148 10:10:53.368167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip
29150 10:10:53.402337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip
29152 10:10:53.402847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip>
29153 10:10:53.437788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass>
29154 10:10:53.438252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass
29156 10:10:53.471964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip>
29157 10:10:53.472386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip
29159 10:10:53.507377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip>
29160 10:10:53.507814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip
29162 10:10:53.540505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass>
29163 10:10:53.540987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass
29165 10:10:53.575670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip>
29166 10:10:53.576080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip
29168 10:10:53.616551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip>
29169 10:10:53.616964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip
29171 10:10:53.651262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass>
29172 10:10:53.651571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass
29174 10:10:53.686563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip>
29175 10:10:53.687040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip
29177 10:10:53.722797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip>
29178 10:10:53.723258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip
29180 10:10:53.756708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass>
29181 10:10:53.757138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass
29183 10:10:53.790912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip>
29184 10:10:53.791338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip
29186 10:10:53.827013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip
29188 10:10:53.827587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip>
29189 10:10:53.860408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass>
29190 10:10:53.860841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass
29192 10:10:53.895555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip
29194 10:10:53.895970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip>
29195 10:10:53.930510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip>
29196 10:10:53.930908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip
29198 10:10:53.964611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass
29200 10:10:53.965109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass>
29201 10:10:53.998883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip
29203 10:10:53.999493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip>
29204 10:10:54.034407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip>
29205 10:10:54.034848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip
29207 10:10:54.068615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass>
29208 10:10:54.069078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass
29210 10:10:54.103998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip>
29211 10:10:54.104420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip
29213 10:10:54.138642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip
29215 10:10:54.139003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip>
29216 10:10:54.170187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass>
29217 10:10:54.170632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass
29219 10:10:54.202578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip>
29220 10:10:54.203007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip
29222 10:10:54.234906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip>
29223 10:10:54.235367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip
29225 10:10:54.267443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass
29227 10:10:54.267884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass>
29228 10:10:54.300971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip>
29229 10:10:54.301421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip
29231 10:10:54.335162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip
29233 10:10:54.335593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip>
29234 10:10:54.370189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass>
29235 10:10:54.370624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass
29237 10:10:54.404606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip
29239 10:10:54.404979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip>
29240 10:10:54.436445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip
29242 10:10:54.436846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip>
29243 10:10:54.467974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass
29245 10:10:54.468508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass>
29246 10:10:54.499396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip
29248 10:10:54.499929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip>
29249 10:10:54.532342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip>
29250 10:10:54.532756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip
29252 10:10:54.563164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass
29254 10:10:54.563719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass>
29255 10:10:54.594857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip>
29256 10:10:54.595334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip
29258 10:10:54.626696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip>
29259 10:10:54.627160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip
29261 10:10:54.658291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass>
29262 10:10:54.658716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass
29264 10:10:54.690426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip
29266 10:10:54.690981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip>
29267 10:10:54.722839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip>
29268 10:10:54.723293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip
29270 10:10:54.754367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass
29272 10:10:54.754989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass>
29273 10:10:54.785719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip>
29274 10:10:54.786132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip
29276 10:10:54.817279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip
29278 10:10:54.817744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip>
29279 10:10:54.848790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass>
29280 10:10:54.849219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass
29282 10:10:54.880863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip>
29283 10:10:54.881333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip
29285 10:10:54.912393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip
29287 10:10:54.912940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip>
29288 10:10:54.944204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass
29290 10:10:54.944634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass>
29291 10:10:54.975324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip>
29292 10:10:54.975749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip
29294 10:10:55.007157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip
29296 10:10:55.007595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip>
29297 10:10:55.038470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass>
29298 10:10:55.038895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass
29300 10:10:55.070151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip
29302 10:10:55.070714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip>
29303 10:10:55.101717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip>
29304 10:10:55.102180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip
29306 10:10:55.147635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass>
29307 10:10:55.148053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass
29309 10:10:55.181828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip
29311 10:10:55.182259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip>
29312 10:10:55.215094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip>
29313 10:10:55.215505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip
29315 10:10:55.248542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass
29317 10:10:55.248924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass>
29318 10:10:55.282124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip
29320 10:10:55.282736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip>
29321 10:10:55.316559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip
29323 10:10:55.316989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip>
29324 10:10:55.350464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass
29326 10:10:55.350897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass>
29327 10:10:55.383554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip>
29328 10:10:55.384037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip
29330 10:10:55.416520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip>
29331 10:10:55.416961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip
29333 10:10:55.451121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass>
29334 10:10:55.451580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass
29336 10:10:55.484794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip
29338 10:10:55.485378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip>
29339 10:10:55.518899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip>
29340 10:10:55.519374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip
29342 10:10:55.553425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass
29344 10:10:55.554073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass>
29345 10:10:55.588610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip
29347 10:10:55.589228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip>
29348 10:10:55.622883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip
29350 10:10:55.623340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip>
29351 10:10:55.658476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass>
29352 10:10:55.658951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass
29354 10:10:55.693044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip>
29355 10:10:55.693522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip
29357 10:10:55.727885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip
29359 10:10:55.728361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip>
29360 10:10:55.762094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass
29362 10:10:55.762543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass>
29363 10:10:55.795767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip>
29364 10:10:55.796242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip
29366 10:10:55.828712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip>
29367 10:10:55.829140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip
29369 10:10:55.861933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass>
29370 10:10:55.862420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass
29372 10:10:55.895107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip>
29373 10:10:55.895510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip
29375 10:10:55.928436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip>
29376 10:10:55.928913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip
29378 10:10:55.962157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass>
29379 10:10:55.962619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass
29381 10:10:55.995249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip>
29382 10:10:55.995721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip
29384 10:10:56.028535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip>
29385 10:10:56.028965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip
29387 10:10:56.062414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass
29389 10:10:56.062865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass>
29390 10:10:56.095593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip
29392 10:10:56.096048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip>
29393 10:10:56.128709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip>
29394 10:10:56.129195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip
29396 10:10:56.162464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass
29398 10:10:56.163092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass>
29399 10:10:56.196037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip>
29400 10:10:56.196513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip
29402 10:10:56.228783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip>
29403 10:10:56.229220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip
29405 10:10:56.261346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass
29407 10:10:56.261819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass>
29408 10:10:56.294669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip>
29409 10:10:56.295084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip
29411 10:10:56.328637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip>
29412 10:10:56.329049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip
29414 10:10:56.361424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass
29416 10:10:56.361896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass>
29417 10:10:56.394957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip>
29418 10:10:56.395440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip
29420 10:10:56.428804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip>
29421 10:10:56.429285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip
29423 10:10:56.463176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass>
29424 10:10:56.463659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass
29426 10:10:56.497459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip
29428 10:10:56.497901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip>
29429 10:10:56.530846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip>
29430 10:10:56.531255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip
29432 10:10:56.564722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass
29434 10:10:56.565179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass>
29435 10:10:56.598719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip>
29436 10:10:56.599219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip
29438 10:10:56.633038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip
29440 10:10:56.633617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip>
29441 10:10:56.668492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass>
29442 10:10:56.668934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass
29444 10:10:56.703065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip>
29445 10:10:56.703500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip
29447 10:10:56.738226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip
29449 10:10:56.738822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip>
29450 10:10:56.771333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass>
29451 10:10:56.771760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass
29453 10:10:56.805062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip
29455 10:10:56.805518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip>
29456 10:10:56.838837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip>
29457 10:10:56.839267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip
29459 10:10:56.872730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass
29461 10:10:56.873179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass>
29462 10:10:56.906403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip>
29463 10:10:56.906814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip
29465 10:10:56.940456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip>
29466 10:10:56.940899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip
29468 10:10:56.975761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass>
29469 10:10:56.976203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass
29471 10:10:57.015024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip>
29472 10:10:57.015542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip
29474 10:10:57.056811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip>
29475 10:10:57.057481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip
29477 10:10:57.094475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass>
29478 10:10:57.094901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass
29480 10:10:57.130043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip
29482 10:10:57.130739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip>
29483 10:10:57.164799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip
29485 10:10:57.165449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip>
29486 10:10:57.199280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass>
29487 10:10:57.199721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass
29489 10:10:57.233140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip>
29490 10:10:57.233582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip
29492 10:10:57.267491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip>
29493 10:10:57.267914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip
29495 10:10:57.302161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass>
29496 10:10:57.302596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass
29498 10:10:57.336567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip
29500 10:10:57.337188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip>
29501 10:10:57.370584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip
29503 10:10:57.371064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip>
29504 10:10:57.405077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass>
29505 10:10:57.405523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass
29507 10:10:57.440671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip>
29508 10:10:57.441110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip
29510 10:10:57.475936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip
29512 10:10:57.476409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip>
29513 10:10:57.513033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass
29515 10:10:57.513716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass>
29516 10:10:57.550501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip>
29517 10:10:57.550908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip
29519 10:10:57.585982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip
29521 10:10:57.586549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip>
29522 10:10:57.619203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass
29524 10:10:57.619627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass>
29525 10:10:57.653518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip
29527 10:10:57.653958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip>
29528 10:10:57.688233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip
29530 10:10:57.688624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip>
29531 10:10:57.722983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass>
29532 10:10:57.723259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass
29534 10:10:57.757990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip>
29535 10:10:57.758308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip
29537 10:10:57.796364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip>
29538 10:10:57.796733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip
29540 10:10:57.834303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass>
29541 10:10:57.834623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass
29543 10:10:57.870660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip
29545 10:10:57.871336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip>
29546 10:10:57.906248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip>
29547 10:10:57.906714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip
29549 10:10:57.941170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass>
29550 10:10:57.941634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass
29552 10:10:57.976148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip>
29553 10:10:57.976514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip
29555 10:10:58.011352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip>
29556 10:10:58.011707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip
29558 10:10:58.046456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass>
29559 10:10:58.046800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass
29561 10:10:58.082002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip
29563 10:10:58.082432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip>
29564 10:10:58.139826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip
29566 10:10:58.140279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip>
29567 10:10:58.174908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass>
29568 10:10:58.175371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass
29570 10:10:58.210768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip>
29571 10:10:58.211167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip
29573 10:10:58.245840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip>
29574 10:10:58.246121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip
29576 10:10:58.280543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass>
29577 10:10:58.280945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass
29579 10:10:58.315236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip>
29580 10:10:58.315658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip
29582 10:10:58.350103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip>
29583 10:10:58.350529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip
29585 10:10:58.384660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass>
29586 10:10:58.385083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass
29588 10:10:58.420294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip>
29589 10:10:58.420719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip
29591 10:10:58.454799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip>
29592 10:10:58.455217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip
29594 10:10:58.489941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass
29596 10:10:58.490333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass>
29597 10:10:58.526254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip>
29598 10:10:58.526532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip
29600 10:10:58.560918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip>
29601 10:10:58.561355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip
29603 10:10:58.594921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass>
29604 10:10:58.595361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass
29606 10:10:58.629253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip
29608 10:10:58.629732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip>
29609 10:10:58.664260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip>
29610 10:10:58.664673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip
29612 10:10:58.697882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass
29614 10:10:58.698342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass>
29615 10:10:58.731378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip>
29616 10:10:58.731793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip
29618 10:10:58.764673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip>
29619 10:10:58.765116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip
29621 10:10:58.798775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass>
29622 10:10:58.799205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass
29624 10:10:58.833774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip>
29625 10:10:58.834053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip
29627 10:10:58.868932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip
29629 10:10:58.869426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip>
29630 10:10:58.903119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass
29632 10:10:58.903545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass>
29633 10:10:58.938651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip
29635 10:10:58.939105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip>
29636 10:10:58.973613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip>
29637 10:10:58.974101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip
29639 10:10:59.008169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass
29641 10:10:59.008814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass>
29642 10:10:59.045056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip
29644 10:10:59.045520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip>
29645 10:10:59.081829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip>
29646 10:10:59.082270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip
29648 10:10:59.116452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass>
29649 10:10:59.116937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass
29651 10:10:59.150423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip>
29652 10:10:59.150876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip
29654 10:10:59.182243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip>
29655 10:10:59.182681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip
29657 10:10:59.214013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass
29659 10:10:59.214575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass>
29660 10:10:59.244897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip>
29661 10:10:59.245299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip
29663 10:10:59.276573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip>
29664 10:10:59.277001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip
29666 10:10:59.308501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass>
29667 10:10:59.308973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass
29669 10:10:59.340308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip>
29670 10:10:59.340750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip
29672 10:10:59.371529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip
29674 10:10:59.372088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip>
29675 10:10:59.402610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass>
29676 10:10:59.402989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass
29678 10:10:59.434184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip>
29679 10:10:59.434544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip
29681 10:10:59.465339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip
29683 10:10:59.465967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip>
29684 10:10:59.510895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass>
29685 10:10:59.511238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass
29687 10:10:59.542713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip
29689 10:10:59.543259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip>
29690 10:10:59.574901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip>
29691 10:10:59.575366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip
29693 10:10:59.606665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass>
29694 10:10:59.607127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass
29696 10:10:59.638189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip>
29697 10:10:59.638648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip
29699 10:10:59.670590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip>
29700 10:10:59.671034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip
29702 10:10:59.703290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass>
29703 10:10:59.703843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass
29705 10:10:59.736666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip
29707 10:10:59.737113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip>
29708 10:10:59.770100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip>
29709 10:10:59.770512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip
29711 10:10:59.803519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass>
29712 10:10:59.803950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass
29714 10:10:59.839094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip>
29715 10:10:59.839505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip
29717 10:10:59.874809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip>
29718 10:10:59.875213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip
29720 10:10:59.908560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass>
29721 10:10:59.908978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass
29723 10:10:59.940081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip
29725 10:10:59.940508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip>
29726 10:10:59.971228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip>
29727 10:10:59.971622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip
29729 10:11:00.006306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass
29731 10:11:00.006747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass>
29732 10:11:00.038536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip>
29733 10:11:00.038993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip
29735 10:11:00.070164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip>
29736 10:11:00.070613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip
29738 10:11:00.100701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass
29740 10:11:00.101134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass>
29741 10:11:00.132385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip>
29742 10:11:00.132786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip
29744 10:11:00.163830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip>
29745 10:11:00.164234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip
29747 10:11:00.199165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass
29749 10:11:00.199618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass>
29750 10:11:00.231747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip>
29751 10:11:00.232150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip
29753 10:11:00.271023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip>
29754 10:11:00.271380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip
29756 10:11:00.302440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass>
29757 10:11:00.302784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass
29759 10:11:00.332945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip
29761 10:11:00.333393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip>
29762 10:11:00.366017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip>
29763 10:11:00.366383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip
29765 10:11:00.397440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass
29767 10:11:00.397738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass>
29768 10:11:00.428044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip>
29769 10:11:00.428446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip
29771 10:11:00.459075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip>
29772 10:11:00.459479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip
29774 10:11:00.490254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass>
29775 10:11:00.490669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass
29777 10:11:00.522045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip>
29778 10:11:00.522426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip
29780 10:11:00.553117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip>
29781 10:11:00.553464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip
29783 10:11:00.584040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass
29785 10:11:00.584457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass>
29786 10:11:00.615319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip>
29787 10:11:00.615682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip
29789 10:11:00.646422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip>
29790 10:11:00.646876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip
29792 10:11:00.677915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass
29794 10:11:00.678454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass>
29795 10:11:00.709048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip>
29796 10:11:00.709452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip
29798 10:11:00.740590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip
29800 10:11:00.741212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip>
29801 10:11:00.772312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass
29803 10:11:00.772857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass>
29804 10:11:00.803436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip>
29805 10:11:00.803893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip
29807 10:11:00.834891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip>
29808 10:11:00.835322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip
29810 10:11:00.866337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass>
29811 10:11:00.866778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass
29813 10:11:00.897902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip
29815 10:11:00.898433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip>
29816 10:11:00.928747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip>
29817 10:11:00.929179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip
29819 10:11:00.960216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass
29821 10:11:00.960734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass>
29822 10:11:00.991459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip
29824 10:11:00.991987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip>
29825 10:11:01.023333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip>
29826 10:11:01.023769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip
29828 10:11:01.054930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass
29830 10:11:01.055562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass>
29831 10:11:01.086121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip
29833 10:11:01.086639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip>
29834 10:11:01.117478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip
29836 10:11:01.118012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip>
29837 10:11:01.148794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass
29839 10:11:01.149329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass>
29840 10:11:01.179940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip>
29841 10:11:01.180344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip
29843 10:11:01.211846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip
29845 10:11:01.212382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip>
29846 10:11:01.243102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass>
29847 10:11:01.243481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass
29849 10:11:01.274036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip>
29850 10:11:01.274387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip
29852 10:11:01.306005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip>
29853 10:11:01.306370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip
29855 10:11:01.336712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass>
29856 10:11:01.337075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass
29858 10:11:01.368720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip>
29859 10:11:01.369007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip
29861 10:11:01.400009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip>
29862 10:11:01.400359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip
29864 10:11:01.431199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass
29866 10:11:01.431705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass>
29867 10:11:01.462494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip>
29868 10:11:01.462864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip
29870 10:11:01.495219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip>
29871 10:11:01.495568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip
29873 10:11:01.526276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass
29875 10:11:01.526700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass>
29876 10:11:01.556886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip>
29877 10:11:01.557241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip
29879 10:11:01.588059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip>
29880 10:11:01.588408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip
29882 10:11:01.619189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass>
29883 10:11:01.619538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass
29885 10:11:01.650496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip>
29886 10:11:01.650852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip
29888 10:11:01.682236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip>
29889 10:11:01.682521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip
29891 10:11:01.714067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass>
29892 10:11:01.714490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass
29894 10:11:01.745274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip
29896 10:11:01.745558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip>
29897 10:11:01.777367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip
29899 10:11:01.777827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip>
29900 10:11:01.807967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass
29902 10:11:01.808388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass>
29903 10:11:01.839955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip>
29904 10:11:01.840324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip
29906 10:11:01.870873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip>
29907 10:11:01.871149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip
29909 10:11:01.901739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass>
29910 10:11:01.902006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass
29912 10:11:01.933469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip
29914 10:11:01.933889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip>
29915 10:11:01.965200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip
29917 10:11:01.965644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip>
29918 10:11:01.997318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass
29920 10:11:01.997936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass>
29921 10:11:02.030576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip>
29922 10:11:02.030870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip
29924 10:11:02.062188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip>
29925 10:11:02.062580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip
29927 10:11:02.092951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass>
29928 10:11:02.093356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass
29930 10:11:02.124090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip>
29931 10:11:02.124482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip
29933 10:11:02.155541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip>
29934 10:11:02.155925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip
29936 10:11:02.187559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass
29938 10:11:02.188022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass>
29939 10:11:02.219069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip>
29940 10:11:02.219346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip
29942 10:11:02.251326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip
29944 10:11:02.251606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip>
29945 10:11:02.282634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass>
29946 10:11:02.282911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass
29948 10:11:02.313886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip>
29949 10:11:02.314345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip
29951 10:11:02.346513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip>
29952 10:11:02.346984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip
29954 10:11:02.378092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass>
29955 10:11:02.378490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass
29957 10:11:02.409481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip
29959 10:11:02.409898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip>
29960 10:11:02.441714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip>
29961 10:11:02.442179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip
29963 10:11:02.474448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass
29965 10:11:02.475000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass>
29966 10:11:02.506456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip>
29967 10:11:02.506805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip
29969 10:11:02.537603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip>
29970 10:11:02.537969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip
29972 10:11:02.568780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass>
29973 10:11:02.569152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass
29975 10:11:02.600048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip
29977 10:11:02.600540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip>
29978 10:11:02.630966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip>
29979 10:11:02.631321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip
29981 10:11:02.662004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass>
29982 10:11:02.662352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass
29984 10:11:02.694058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip>
29985 10:11:02.694401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip
29987 10:11:02.725075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip
29989 10:11:02.725574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip>
29990 10:11:02.756326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass
29992 10:11:02.757064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass>
29993 10:11:02.787951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip
29995 10:11:02.788454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip>
29996 10:11:02.819213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip>
29997 10:11:02.819490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip
29999 10:11:02.851290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass
30001 10:11:02.851733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass>
30002 10:11:02.882421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip
30004 10:11:02.882845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip>
30005 10:11:02.913718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip>
30006 10:11:02.914133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip
30008 10:11:02.944345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass>
30009 10:11:02.944820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass
30011 10:11:02.976310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip
30013 10:11:02.976733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip>
30014 10:11:03.007994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip>
30015 10:11:03.008379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip
30017 10:11:03.040156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass>
30018 10:11:03.040625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass
30020 10:11:03.071641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip
30022 10:11:03.072081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip>
30023 10:11:03.103328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip>
30024 10:11:03.103721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip
30026 10:11:03.134062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass>
30027 10:11:03.134410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass
30029 10:11:03.165000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip>
30030 10:11:03.165348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip
30032 10:11:03.197414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip
30034 10:11:03.197922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip>
30035 10:11:03.268730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass
30037 10:11:03.269294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass>
30038 10:11:03.303175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip
30040 10:11:03.303592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip>
30041 10:11:03.334424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip>
30042 10:11:03.334847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip
30044 10:11:03.365190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass
30046 10:11:03.365656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass>
30047 10:11:03.396360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip>
30048 10:11:03.396731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip
30050 10:11:03.428318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip>
30051 10:11:03.428665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip
30053 10:11:03.459982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass>
30054 10:11:03.460326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass
30056 10:11:03.493860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip>
30057 10:11:03.494226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip
30059 10:11:03.530417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip>
30060 10:11:03.530794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip
30062 10:11:03.561995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass>
30063 10:11:03.562361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass
30065 10:11:03.593033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip
30067 10:11:03.593447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip>
30068 10:11:03.624720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip
30070 10:11:03.625146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip>
30071 10:11:03.662415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass
30073 10:11:03.662847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass>
30074 10:11:03.696541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip>
30075 10:11:03.696944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip
30077 10:11:03.729119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip
30079 10:11:03.729550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip>
30080 10:11:03.761368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass
30082 10:11:03.761811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass>
30083 10:11:03.793991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip>
30084 10:11:03.794353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip
30086 10:11:03.826040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip>
30087 10:11:03.826394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip
30089 10:11:03.858519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass>
30090 10:11:03.858803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass
30092 10:11:03.890508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip
30094 10:11:03.890944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip>
30095 10:11:03.922538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip>
30096 10:11:03.922894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip
30098 10:11:03.954410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass>
30099 10:11:03.954811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass
30101 10:11:03.986627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip>
30102 10:11:03.987003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip
30104 10:11:04.018626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip
30106 10:11:04.019054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip>
30107 10:11:04.050514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass>
30108 10:11:04.050902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass
30110 10:11:04.082757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip>
30111 10:11:04.083134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip
30113 10:11:04.115592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip>
30114 10:11:04.116056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip
30116 10:11:04.147556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass>
30117 10:11:04.148016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass
30119 10:11:04.179612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip>
30120 10:11:04.180071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip
30122 10:11:04.211896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip>
30123 10:11:04.212361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip
30125 10:11:04.243611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass
30127 10:11:04.244121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass>
30128 10:11:04.275167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip>
30129 10:11:04.275513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip
30131 10:11:04.307502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip>
30132 10:11:04.307792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip
30134 10:11:04.339619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass
30136 10:11:04.339916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass>
30137 10:11:04.372386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip>
30138 10:11:04.372844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip
30140 10:11:04.404296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip>
30141 10:11:04.404686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip
30143 10:11:04.436249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass>
30144 10:11:04.436640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass
30146 10:11:04.468906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip
30148 10:11:04.469315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip>
30149 10:11:04.500993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip
30151 10:11:04.501414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip>
30152 10:11:04.532888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass>
30153 10:11:04.533305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass
30155 10:11:04.565804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip
30157 10:11:04.566250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip>
30158 10:11:04.597984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip>
30159 10:11:04.598454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip
30161 10:11:04.629699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass
30163 10:11:04.630132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass>
30164 10:11:04.661078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip>
30165 10:11:04.661425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip
30167 10:11:04.692623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip>
30168 10:11:04.693072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip
30170 10:11:04.724154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass>
30171 10:11:04.724590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass
30173 10:11:04.756117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip>
30174 10:11:04.756577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip
30176 10:11:04.787997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip
30178 10:11:04.788362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip>
30179 10:11:04.819381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass
30181 10:11:04.819677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass>
30182 10:11:04.851242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip>
30183 10:11:04.851590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip
30185 10:11:04.884007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip>
30186 10:11:04.884453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip
30188 10:11:04.916680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass>
30189 10:11:04.917148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass
30191 10:11:04.948593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip>
30192 10:11:04.949054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip
30194 10:11:04.981107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip
30196 10:11:04.981673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip>
30197 10:11:05.013541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass
30199 10:11:05.014090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass>
30200 10:11:05.045044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip
30202 10:11:05.045497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip>
30203 10:11:05.077691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip
30205 10:11:05.078136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip>
30206 10:11:05.109513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass
30208 10:11:05.109968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass>
30209 10:11:05.141959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip>
30210 10:11:05.142363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip
30212 10:11:05.173918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip>
30213 10:11:05.174369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip
30215 10:11:05.204856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass>
30216 10:11:05.205195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass
30218 10:11:05.220487 <47>[ 299.894387] systemd-journald[109]: Sent WATCHDOG=1 notification.
30219 10:11:05.241913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip
30221 10:11:05.242465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip>
30222 10:11:05.274303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip>
30223 10:11:05.274750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip
30225 10:11:05.306140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass>
30226 10:11:05.306581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass
30228 10:11:05.338328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip>
30229 10:11:05.338764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip
30231 10:11:05.370389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip>
30232 10:11:05.370844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip
30234 10:11:05.402471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass>
30235 10:11:05.402896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass
30237 10:11:05.434521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip
30239 10:11:05.435058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip>
30240 10:11:05.466334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip>
30241 10:11:05.466773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip
30243 10:11:05.498813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass>
30244 10:11:05.499258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass
30246 10:11:05.530032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip
30248 10:11:05.530605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip>
30249 10:11:05.561397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip
30251 10:11:05.561963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip>
30252 10:11:05.592527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass>
30253 10:11:05.592924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass
30255 10:11:05.624390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip>
30256 10:11:05.624798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip
30258 10:11:05.656256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip>
30259 10:11:05.656660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip
30261 10:11:05.688230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass>
30262 10:11:05.688638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass
30264 10:11:05.720942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip
30266 10:11:05.721495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip>
30267 10:11:05.753606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip>
30268 10:11:05.754078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip
30270 10:11:05.785109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass
30272 10:11:05.785637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass>
30273 10:11:05.816051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip>
30274 10:11:05.816519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip
30276 10:11:05.848138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip>
30277 10:11:05.848561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip
30279 10:11:05.879631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass
30281 10:11:05.880219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass>
30282 10:11:05.912919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip
30284 10:11:05.913479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip>
30285 10:11:05.944180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip>
30286 10:11:05.944646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip
30288 10:11:05.975522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass>
30289 10:11:05.975931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass
30291 10:11:06.007670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip>
30292 10:11:06.008121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip
30294 10:11:06.039534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip>
30295 10:11:06.039970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip
30297 10:11:06.071623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass>
30298 10:11:06.072020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass
30300 10:11:06.103806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip>
30301 10:11:06.104197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip
30303 10:11:06.135265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip>
30304 10:11:06.135658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip
30306 10:11:06.167121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass
30308 10:11:06.167536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass>
30309 10:11:06.198696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip
30311 10:11:06.199141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip>
30312 10:11:06.230432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip>
30313 10:11:06.230829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip
30315 10:11:06.262661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass>
30316 10:11:06.263059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass
30318 10:11:06.295375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip>
30319 10:11:06.295780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip
30321 10:11:06.327540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip>
30322 10:11:06.327989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip
30324 10:11:06.359930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass>
30325 10:11:06.360279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass
30327 10:11:06.390932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip>
30328 10:11:06.391304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip
30330 10:11:06.423064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip>
30331 10:11:06.423421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip
30333 10:11:06.454633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass>
30334 10:11:06.454973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass
30336 10:11:06.485942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip>
30337 10:11:06.486237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip
30339 10:11:06.518118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip>
30340 10:11:06.518493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip
30342 10:11:06.549802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass>
30343 10:11:06.550160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass
30345 10:11:06.581356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip
30347 10:11:06.581792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip>
30348 10:11:06.612692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip>
30349 10:11:06.613087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip
30351 10:11:06.644080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass>
30352 10:11:06.644464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass
30354 10:11:06.675914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip
30356 10:11:06.676502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip>
30357 10:11:06.707287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip
30359 10:11:06.707739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip>
30360 10:11:06.739318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass
30362 10:11:06.739761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass>
30363 10:11:06.771224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip>
30364 10:11:06.771671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip
30366 10:11:06.802171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip>
30367 10:11:06.802646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip
30369 10:11:06.834098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass>
30370 10:11:06.834584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass
30372 10:11:06.865901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip>
30373 10:11:06.866258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip
30375 10:11:06.897551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip
30377 10:11:06.898018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip>
30378 10:11:06.929351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass
30380 10:11:06.929825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass>
30381 10:11:06.960989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip
30383 10:11:06.961421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip>
30384 10:11:06.993088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip
30386 10:11:06.993880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip>
30387 10:11:07.023926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass
30389 10:11:07.024588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass>
30390 10:11:07.055429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip>
30391 10:11:07.055909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip
30393 10:11:07.087799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip
30395 10:11:07.088372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip>
30396 10:11:07.119640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass
30398 10:11:07.120059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass>
30399 10:11:07.151597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip>
30400 10:11:07.152017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip
30402 10:11:07.184470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip
30404 10:11:07.184893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip>
30405 10:11:07.216107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass>
30406 10:11:07.216547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass
30408 10:11:07.248390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip>
30409 10:11:07.248788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip
30411 10:11:07.280547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip
30413 10:11:07.281211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip>
30414 10:11:07.312419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass>
30415 10:11:07.312816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass
30417 10:11:07.343819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip
30419 10:11:07.344253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip>
30420 10:11:07.376235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip>
30421 10:11:07.376699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip
30423 10:11:07.408042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass>
30424 10:11:07.408436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass
30426 10:11:07.440399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip
30428 10:11:07.440835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip>
30429 10:11:07.472317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip>
30430 10:11:07.472749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip
30432 10:11:07.504143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass
30434 10:11:07.504563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass>
30435 10:11:07.535785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip>
30436 10:11:07.536189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip
30438 10:11:07.567493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip
30440 10:11:07.567938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip>
30441 10:11:07.598746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass>
30442 10:11:07.599160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass
30444 10:11:07.630308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip>
30445 10:11:07.630726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip
30447 10:11:07.662315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip
30449 10:11:07.662762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip>
30450 10:11:07.694052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass
30452 10:11:07.694492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass>
30453 10:11:07.725793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip>
30454 10:11:07.726249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip
30456 10:11:07.758251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip
30458 10:11:07.758821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip>
30459 10:11:07.790355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass
30461 10:11:07.790871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass>
30462 10:11:07.823608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip
30464 10:11:07.824000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip>
30465 10:11:07.855263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip>
30466 10:11:07.855652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip
30468 10:11:07.886710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass>
30469 10:11:07.887112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass
30471 10:11:07.924092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip>
30472 10:11:07.924484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip
30474 10:11:07.963825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip>
30475 10:11:07.964218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip
30477 10:11:07.998591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass>
30478 10:11:07.998948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass
30480 10:11:08.030303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip>
30481 10:11:08.030649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip
30483 10:11:08.062062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip>
30484 10:11:08.062411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip
30486 10:11:08.093152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass>
30487 10:11:08.093533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass
30489 10:11:08.124786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip>
30490 10:11:08.125070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip
30492 10:11:08.155507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip
30494 10:11:08.155958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip>
30495 10:11:08.186848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass
30497 10:11:08.187401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass>
30498 10:11:08.218864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip>
30499 10:11:08.219289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip
30501 10:11:08.250321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip>
30502 10:11:08.250741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip
30504 10:11:08.282049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass>
30505 10:11:08.282451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass
30507 10:11:08.313156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip>
30508 10:11:08.313542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip
30510 10:11:08.374743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip>
30511 10:11:08.375099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip
30513 10:11:08.406269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass>
30514 10:11:08.406640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass
30516 10:11:08.439212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip>
30517 10:11:08.439620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip
30519 10:11:08.474415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip>
30520 10:11:08.474874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip
30522 10:11:08.505806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass
30524 10:11:08.506279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass>
30525 10:11:08.536927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip
30527 10:11:08.537361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip>
30528 10:11:08.567536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip
30530 10:11:08.568157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip>
30531 10:11:08.599559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass
30533 10:11:08.600183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass>
30534 10:11:08.631453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip
30536 10:11:08.632079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip>
30537 10:11:08.663248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip>
30538 10:11:08.663642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip
30540 10:11:08.694469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass
30542 10:11:08.694909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass>
30543 10:11:08.725897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip
30545 10:11:08.726330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip>
30546 10:11:08.756876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip>
30547 10:11:08.757254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip
30549 10:11:08.788978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass>
30550 10:11:08.789384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass
30552 10:11:08.822776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip>
30553 10:11:08.823191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip
30555 10:11:08.858000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip
30557 10:11:08.858455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip>
30558 10:11:08.892473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass>
30559 10:11:08.892908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass
30561 10:11:08.929291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip
30563 10:11:08.929908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip>
30564 10:11:08.962013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip>
30565 10:11:08.962458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip
30567 10:11:08.993914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass>
30568 10:11:08.994337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass
30570 10:11:09.026781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip>
30571 10:11:09.027271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip
30573 10:11:09.058324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip
30575 10:11:09.058766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip>
30576 10:11:09.090173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass
30578 10:11:09.090834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass>
30579 10:11:09.122356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip
30581 10:11:09.122890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip>
30582 10:11:09.154565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip>
30583 10:11:09.154914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip
30585 10:11:09.186154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass>
30586 10:11:09.186521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass
30588 10:11:09.218299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip
30590 10:11:09.218725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip>
30591 10:11:09.250326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip>
30592 10:11:09.250728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip
30594 10:11:09.282826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass
30596 10:11:09.283264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass>
30597 10:11:09.315958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip>
30598 10:11:09.316335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip
30600 10:11:09.347519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip>
30601 10:11:09.347866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip
30603 10:11:09.379631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass>
30604 10:11:09.379976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass
30606 10:11:09.411254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip>
30607 10:11:09.411597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip
30609 10:11:09.443228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip
30611 10:11:09.443726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip>
30612 10:11:09.475508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass>
30613 10:11:09.475982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass
30615 10:11:09.508506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip>
30616 10:11:09.508915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip
30618 10:11:09.540471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip>
30619 10:11:09.540877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip
30621 10:11:09.572165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass
30623 10:11:09.572586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass>
30624 10:11:09.604072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip
30626 10:11:09.604515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip>
30627 10:11:09.636779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip>
30628 10:11:09.637175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip
30630 10:11:09.669013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass>
30631 10:11:09.669397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass
30633 10:11:09.700863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip
30635 10:11:09.701293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip>
30636 10:11:09.732196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip>
30637 10:11:09.732538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip
30639 10:11:09.763180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass
30641 10:11:09.763604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass>
30642 10:11:09.795053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip
30644 10:11:09.795477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip>
30645 10:11:09.827702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip
30647 10:11:09.828122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip>
30648 10:11:09.859564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass>
30649 10:11:09.859958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass
30651 10:11:09.891205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip>
30652 10:11:09.891611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip
30654 10:11:09.923190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip>
30655 10:11:09.923565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip
30657 10:11:09.955670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass
30659 10:11:09.956105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass>
30660 10:11:09.989454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip
30662 10:11:09.990032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip>
30663 10:11:10.022267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip>
30664 10:11:10.022720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip
30666 10:11:10.055189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass>
30667 10:11:10.055613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass
30669 10:11:10.087396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip
30671 10:11:10.087939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip>
30672 10:11:10.120686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip
30674 10:11:10.121142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip>
30675 10:11:10.153439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass
30677 10:11:10.153992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass>
30678 10:11:10.185346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip
30680 10:11:10.185792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip>
30681 10:11:10.217326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip
30683 10:11:10.217811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip>
30684 10:11:10.249922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass
30686 10:11:10.250216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass>
30687 10:11:10.282822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip
30689 10:11:10.283241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip>
30690 10:11:10.316461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip
30692 10:11:10.316797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip>
30693 10:11:10.349291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass
30695 10:11:10.349860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass>
30696 10:11:10.380558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip>
30697 10:11:10.380907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip
30699 10:11:10.412652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip
30701 10:11:10.413162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip>
30702 10:11:10.444225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass
30704 10:11:10.444662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass>
30705 10:11:10.476504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip>
30706 10:11:10.476854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip
30708 10:11:10.510263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip>
30709 10:11:10.510603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip
30711 10:11:10.541874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass>
30712 10:11:10.542229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass
30714 10:11:10.574463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip
30716 10:11:10.575068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip>
30717 10:11:10.606485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip
30719 10:11:10.606947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip>
30720 10:11:10.638131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass
30722 10:11:10.638557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass>
30723 10:11:10.671638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip
30725 10:11:10.672229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip>
30726 10:11:10.703052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip>
30727 10:11:10.703463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip
30729 10:11:10.734736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass>
30730 10:11:10.735103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass
30732 10:11:10.767378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip>
30733 10:11:10.767721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip
30735 10:11:10.799519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip>
30736 10:11:10.799860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip
30738 10:11:10.835135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass>
30739 10:11:10.835581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass
30741 10:11:10.866936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip>
30742 10:11:10.867335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip
30744 10:11:10.899272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip>
30745 10:11:10.899715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip
30747 10:11:10.933047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass>
30748 10:11:10.933461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass
30750 10:11:10.966710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip>
30751 10:11:10.967126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip
30753 10:11:11.001711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip>
30754 10:11:11.002136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip
30756 10:11:11.035132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass
30758 10:11:11.035590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass>
30759 10:11:11.068931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip>
30760 10:11:11.069342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip
30762 10:11:11.104555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip
30764 10:11:11.105123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip>
30765 10:11:11.138994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass>
30766 10:11:11.139462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass
30768 10:11:11.176578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip
30770 10:11:11.177138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip>
30771 10:11:11.209550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip
30773 10:11:11.210100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip>
30774 10:11:11.242847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass
30776 10:11:11.243387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass>
30777 10:11:11.277424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip
30779 10:11:11.277985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip>
30780 10:11:11.312192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip>
30781 10:11:11.312543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip
30783 10:11:11.349862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass
30785 10:11:11.350295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass>
30786 10:11:11.387682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip>
30787 10:11:11.388049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip
30789 10:11:11.420029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip>
30790 10:11:11.420469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip
30792 10:11:11.452706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass>
30793 10:11:11.453034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass
30795 10:11:11.484961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip>
30796 10:11:11.485246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip
30798 10:11:11.518079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip>
30799 10:11:11.518357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip
30801 10:11:11.554695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass>
30802 10:11:11.555135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass
30804 10:11:11.586542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip
30806 10:11:11.586987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip>
30807 10:11:11.617821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip>
30808 10:11:11.618170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip
30810 10:11:11.648566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass
30812 10:11:11.649071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass>
30813 10:11:11.679570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip>
30814 10:11:11.680054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip
30816 10:11:11.711265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip>
30817 10:11:11.711714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip
30819 10:11:11.743254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass>
30820 10:11:11.743670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass
30822 10:11:11.775073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip
30824 10:11:11.775698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip>
30825 10:11:11.806227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip>
30826 10:11:11.806702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip
30828 10:11:11.837191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass
30830 10:11:11.837825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass>
30831 10:11:11.868735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip>
30832 10:11:11.869191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip
30834 10:11:11.904823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip
30836 10:11:11.905373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip>
30837 10:11:11.936014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass
30839 10:11:11.936558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass>
30840 10:11:11.967008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip>
30841 10:11:11.967456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip
30843 10:11:12.003830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip>
30844 10:11:12.004353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip
30846 10:11:12.038290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass>
30847 10:11:12.038784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass
30849 10:11:12.072210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip>
30850 10:11:12.072620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip
30852 10:11:12.106864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip>
30853 10:11:12.107276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip
30855 10:11:12.139961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass
30857 10:11:12.140513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass>
30858 10:11:12.172834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip
30860 10:11:12.173405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip>
30861 10:11:12.206440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip>
30862 10:11:12.206900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip
30864 10:11:12.239420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass>
30865 10:11:12.239889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass
30867 10:11:12.272332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip>
30868 10:11:12.272798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip
30870 10:11:12.306095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip>
30871 10:11:12.306549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip
30873 10:11:12.338950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass>
30874 10:11:12.339317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass
30876 10:11:12.372167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip>
30877 10:11:12.372518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip
30879 10:11:12.407014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip>
30880 10:11:12.407367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip
30882 10:11:12.440820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass
30884 10:11:12.441326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass>
30885 10:11:12.473014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip>
30886 10:11:12.473380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip
30888 10:11:12.506442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip>
30889 10:11:12.506809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip
30891 10:11:12.540400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass>
30892 10:11:12.540745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass
30894 10:11:12.573325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip
30896 10:11:12.573845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip>
30897 10:11:12.606855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip
30899 10:11:12.607280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip>
30900 10:11:12.640703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass>
30901 10:11:12.641059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass
30903 10:11:12.673873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip
30905 10:11:12.674379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip>
30906 10:11:12.706502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip>
30907 10:11:12.706863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip
30909 10:11:12.739699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass>
30910 10:11:12.740056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass
30912 10:11:12.774975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip>
30913 10:11:12.775323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip
30915 10:11:12.808818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip>
30916 10:11:12.809169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip
30918 10:11:12.842689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass
30920 10:11:12.843113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass>
30921 10:11:12.878543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip
30923 10:11:12.878986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip>
30924 10:11:12.910516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip>
30925 10:11:12.910873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip
30927 10:11:12.943250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass>
30928 10:11:12.943617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass
30930 10:11:12.980339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip
30932 10:11:12.980959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip>
30933 10:11:13.012175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip>
30934 10:11:13.012643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip
30936 10:11:13.043906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass>
30937 10:11:13.044387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass
30939 10:11:13.075875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip>
30940 10:11:13.076335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip
30942 10:11:13.108077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip
30944 10:11:13.108690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip>
30945 10:11:13.139540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass>
30946 10:11:13.140015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass
30948 10:11:13.171083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip>
30949 10:11:13.171558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip
30951 10:11:13.203302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip>
30952 10:11:13.203760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip
30954 10:11:13.235394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass>
30955 10:11:13.235873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass
30957 10:11:13.266778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip>
30958 10:11:13.267234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip
30960 10:11:13.298040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip
30962 10:11:13.298595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip>
30963 10:11:13.328891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass
30965 10:11:13.329442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass>
30966 10:11:13.359873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip
30968 10:11:13.360589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip>
30969 10:11:13.390804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip>
30970 10:11:13.391268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip
30972 10:11:13.423668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass
30974 10:11:13.424232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass>
30975 10:11:13.483732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip>
30976 10:11:13.484139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip
30978 10:11:13.522325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip>
30979 10:11:13.522747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip
30981 10:11:13.554219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass>
30982 10:11:13.554695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass
30984 10:11:13.586417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip
30986 10:11:13.586988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip>
30987 10:11:13.618623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip>
30988 10:11:13.619066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip
30990 10:11:13.650422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass
30992 10:11:13.650956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass>
30993 10:11:13.682496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip
30995 10:11:13.683047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip>
30996 10:11:13.716605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip>
30997 10:11:13.717072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip
30999 10:11:13.748440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass
31001 10:11:13.748800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass>
31002 10:11:13.779941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip
31004 10:11:13.780499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip>
31005 10:11:13.811633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip>
31006 10:11:13.812040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip
31008 10:11:13.843347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass
31010 10:11:13.843796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass>
31011 10:11:13.876571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip>
31012 10:11:13.876989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip
31014 10:11:13.908354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip>
31015 10:11:13.908754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip
31017 10:11:13.941427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass
31019 10:11:13.942080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass>
31020 10:11:13.973797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip
31022 10:11:13.974223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip>
31023 10:11:14.005881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip>
31024 10:11:14.006282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip
31026 10:11:14.037904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass>
31027 10:11:14.038309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass
31029 10:11:14.070122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip
31031 10:11:14.070545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip>
31032 10:11:14.102111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip
31034 10:11:14.102548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip>
31035 10:11:14.134281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass>
31036 10:11:14.134692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass
31038 10:11:14.166265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip>
31039 10:11:14.166738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip
31041 10:11:14.198406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip
31043 10:11:14.198866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip>
31044 10:11:14.230200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass>
31045 10:11:14.230625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass
31047 10:11:14.262233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip
31049 10:11:14.262690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip>
31050 10:11:14.294466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip>
31051 10:11:14.294901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip
31053 10:11:14.326828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass
31055 10:11:14.327445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass>
31056 10:11:14.358596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip>
31057 10:11:14.358992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip
31059 10:11:14.390565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip>
31060 10:11:14.391015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip
31062 10:11:14.422369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass>
31063 10:11:14.422814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass
31065 10:11:14.454664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip>
31066 10:11:14.455054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip
31068 10:11:14.486992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip>
31069 10:11:14.487377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip
31071 10:11:14.519001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass
31073 10:11:14.519417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass>
31074 10:11:14.551273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip>
31075 10:11:14.551693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip
31077 10:11:14.583735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip>
31078 10:11:14.584245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip
31080 10:11:14.615641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass
31082 10:11:14.616064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass>
31083 10:11:14.647836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip>
31084 10:11:14.648233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip
31086 10:11:14.679930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip>
31087 10:11:14.680321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip
31089 10:11:14.712695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass>
31090 10:11:14.713140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass
31092 10:11:14.746551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip>
31093 10:11:14.746957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip
31095 10:11:14.778678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip>
31096 10:11:14.779151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip
31098 10:11:14.810510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass
31100 10:11:14.810922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass>
31101 10:11:14.842421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip>
31102 10:11:14.842816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip
31104 10:11:14.874450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip
31106 10:11:14.874863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip>
31107 10:11:14.906813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass
31109 10:11:14.907213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass>
31110 10:11:14.938383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip>
31111 10:11:14.938776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip
31113 10:11:14.970872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip>
31114 10:11:14.971272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip
31116 10:11:15.002198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass>
31117 10:11:15.002595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass
31119 10:11:15.034144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip
31121 10:11:15.034548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip>
31122 10:11:15.066078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip>
31123 10:11:15.066471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip
31125 10:11:15.098238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass
31127 10:11:15.098644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass>
31128 10:11:15.130230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip
31130 10:11:15.130633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip>
31131 10:11:15.162005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip
31133 10:11:15.162410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip>
31134 10:11:15.193704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass
31136 10:11:15.194112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass>
31137 10:11:15.225635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip
31139 10:11:15.226043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip>
31140 10:11:15.257465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip
31142 10:11:15.257878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip>
31143 10:11:15.288965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass>
31144 10:11:15.289429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass
31146 10:11:15.320459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip
31148 10:11:15.321094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip>
31149 10:11:15.352123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip
31151 10:11:15.352745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip>
31152 10:11:15.383694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass>
31153 10:11:15.384128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass
31155 10:11:15.415550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip>
31156 10:11:15.416051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip
31158 10:11:15.447453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip
31160 10:11:15.447935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip>
31161 10:11:15.478790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass>
31162 10:11:15.479221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass
31164 10:11:15.510455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip>
31165 10:11:15.510882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip
31167 10:11:15.542525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip
31169 10:11:15.543170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip>
31170 10:11:15.574514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass>
31171 10:11:15.574992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass
31173 10:11:15.607566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip>
31174 10:11:15.608031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip
31176 10:11:15.640175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip
31178 10:11:15.640646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip>
31179 10:11:15.671678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass>
31180 10:11:15.672077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass
31182 10:11:15.707894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip>
31183 10:11:15.708246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip
31185 10:11:15.741983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip
31187 10:11:15.742429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip>
31188 10:11:15.775051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass>
31189 10:11:15.775460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass
31191 10:11:15.807272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip
31193 10:11:15.807721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip>
31194 10:11:15.842685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip>
31195 10:11:15.843171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip
31197 10:11:15.878521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass>
31198 10:11:15.879005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass
31200 10:11:15.914978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip
31202 10:11:15.915666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip>
31203 10:11:15.951077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip>
31204 10:11:15.951529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip
31206 10:11:16.000802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass>
31207 10:11:16.001273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass
31209 10:11:16.035205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip>
31210 10:11:16.035609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip
31212 10:11:16.068532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip>
31213 10:11:16.068943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip
31215 10:11:16.101362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass
31217 10:11:16.101696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass>
31218 10:11:16.134277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip
31220 10:11:16.134557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip>
31221 10:11:16.167449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip>
31222 10:11:16.168498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip
31224 10:11:16.199963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass>
31225 10:11:16.200230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass
31227 10:11:16.233041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip
31229 10:11:16.233315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip>
31230 10:11:16.267219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip>
31231 10:11:16.267562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip
31233 10:11:16.299668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass>
31234 10:11:16.300123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass
31236 10:11:16.332989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip
31238 10:11:16.333533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip>
31239 10:11:16.366710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip>
31240 10:11:16.367128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip
31242 10:11:16.399662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass>
31243 10:11:16.400015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass
31245 10:11:16.432229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip
31247 10:11:16.432671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip>
31248 10:11:16.464984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip>
31249 10:11:16.465309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip
31251 10:11:16.497318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass
31253 10:11:16.497794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass>
31254 10:11:16.530486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip>
31255 10:11:16.530832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip
31257 10:11:16.563474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip>
31258 10:11:16.563819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip
31260 10:11:16.597976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass>
31261 10:11:16.598391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass
31263 10:11:16.631562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip
31265 10:11:16.632192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip>
31266 10:11:16.665763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip>
31267 10:11:16.666246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip
31269 10:11:16.698939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass>
31270 10:11:16.699395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass
31272 10:11:16.732641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip
31274 10:11:16.733140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip>
31275 10:11:16.776869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip>
31276 10:11:16.777234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip
31278 10:11:16.812413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass
31280 10:11:16.812860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass>
31281 10:11:16.848826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip>
31282 10:11:16.849185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip
31284 10:11:16.887473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip>
31285 10:11:16.887877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip
31287 10:11:16.920919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass>
31288 10:11:16.921428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass
31290 10:11:16.954690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip>
31291 10:11:16.955010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip
31293 10:11:16.989123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip>
31294 10:11:16.989523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip
31296 10:11:17.036343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass>
31297 10:11:17.036762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass
31299 10:11:17.080625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip>
31300 10:11:17.081031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip
31302 10:11:17.119372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip
31304 10:11:17.119817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip>
31305 10:11:17.153198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass
31307 10:11:17.153780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass>
31308 10:11:17.186470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip
31310 10:11:17.187025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip>
31311 10:11:17.219475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip>
31312 10:11:17.219959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip
31314 10:11:17.256343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass>
31315 10:11:17.256821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass
31317 10:11:17.289704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip>
31318 10:11:17.290100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip
31320 10:11:17.323424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip>
31321 10:11:17.323838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip
31323 10:11:17.357978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass>
31324 10:11:17.358449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass
31326 10:11:17.395107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip
31328 10:11:17.395561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip>
31329 10:11:17.430023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip
31331 10:11:17.430497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip>
31332 10:11:17.463084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass
31334 10:11:17.463720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass>
31335 10:11:17.496748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip>
31336 10:11:17.497160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip
31338 10:11:17.531255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip>
31339 10:11:17.531668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip
31341 10:11:17.564299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass>
31342 10:11:17.564741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass
31344 10:11:17.598863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip
31346 10:11:17.599511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip>
31347 10:11:17.632431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip
31349 10:11:17.632885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip>
31350 10:11:17.666022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass
31352 10:11:17.666660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass>
31353 10:11:17.699194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip
31355 10:11:17.699827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip>
31356 10:11:17.732113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip
31358 10:11:17.732700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip>
31359 10:11:17.765793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass>
31360 10:11:17.766224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass
31362 10:11:17.799206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip>
31363 10:11:17.799683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip
31365 10:11:17.832656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip>
31366 10:11:17.833151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip
31368 10:11:17.867012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass>
31369 10:11:17.867444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass
31371 10:11:17.900497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip
31373 10:11:17.900951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip>
31374 10:11:17.934138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip
31376 10:11:17.934747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip>
31377 10:11:17.968702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass>
31378 10:11:17.969190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass
31380 10:11:18.002733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip
31382 10:11:18.003305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip>
31383 10:11:18.037028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip>
31384 10:11:18.037512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip
31386 10:11:18.071954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass>
31387 10:11:18.072396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass
31389 10:11:18.109009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip>
31390 10:11:18.109432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip
31392 10:11:18.145459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip
31394 10:11:18.145926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip>
31395 10:11:18.180361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass
31397 10:11:18.180705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass>
31398 10:11:18.214752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip>
31399 10:11:18.215118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip
31401 10:11:18.248797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip>
31402 10:11:18.249163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip
31404 10:11:18.282760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass>
31405 10:11:18.283115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass
31407 10:11:18.317072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip>
31408 10:11:18.317447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip
31410 10:11:18.350486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip>
31411 10:11:18.350821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip
31413 10:11:18.383387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass>
31414 10:11:18.383721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass
31416 10:11:18.416703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip>
31417 10:11:18.417140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip
31419 10:11:18.450488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip>
31420 10:11:18.450924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip
31422 10:11:18.484030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass>
31423 10:11:18.484536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass
31425 10:11:18.518309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip>
31426 10:11:18.518763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip
31428 10:11:18.554464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip
31430 10:11:18.555118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip>
31431 10:11:18.612854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass>
31432 10:11:18.613359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass
31434 10:11:18.648278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip
31436 10:11:18.648908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip>
31437 10:11:18.684861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip>
31438 10:11:18.685326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip
31440 10:11:18.718582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass>
31441 10:11:18.719062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass
31443 10:11:18.752639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip>
31444 10:11:18.753119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip
31446 10:11:18.786293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip>
31447 10:11:18.786785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip
31449 10:11:18.819965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass>
31450 10:11:18.820411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass
31452 10:11:18.853673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip>
31453 10:11:18.854105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip
31455 10:11:18.887494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip
31457 10:11:18.887944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip>
31458 10:11:18.922922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass
31460 10:11:18.923372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass>
31461 10:11:18.956622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip>
31462 10:11:18.957051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip
31464 10:11:18.991254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip
31466 10:11:18.991933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip>
31467 10:11:19.025296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass
31469 10:11:19.025901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass>
31470 10:11:19.059566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip>
31471 10:11:19.060040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip
31473 10:11:19.093125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip
31475 10:11:19.093608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip>
31476 10:11:19.127431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass>
31477 10:11:19.127847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass
31479 10:11:19.160726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip
31481 10:11:19.161186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip>
31482 10:11:19.194816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip>
31483 10:11:19.195229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip
31485 10:11:19.229510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass
31487 10:11:19.230160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass>
31488 10:11:19.263046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip>
31489 10:11:19.263518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip
31491 10:11:19.298408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip
31493 10:11:19.299005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip>
31494 10:11:19.332295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass>
31495 10:11:19.332725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass
31497 10:11:19.366816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip
31499 10:11:19.367265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip>
31500 10:11:19.400908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip
31502 10:11:19.401381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip>
31503 10:11:19.434510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass
31505 10:11:19.434974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass>
31506 10:11:19.468274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip
31508 10:11:19.468751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip>
31509 10:11:19.502091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip>
31510 10:11:19.502529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip
31512 10:11:19.534884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass>
31513 10:11:19.535319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass
31515 10:11:19.569413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip
31517 10:11:19.569887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip>
31518 10:11:19.604205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip>
31519 10:11:19.604916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip
31521 10:11:19.638823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass
31523 10:11:19.639464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass>
31524 10:11:19.673954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip>
31525 10:11:19.674429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip
31527 10:11:19.707738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip>
31528 10:11:19.708229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip
31530 10:11:19.742060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass
31532 10:11:19.742625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass>
31533 10:11:19.775316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip>
31534 10:11:19.775773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip
31536 10:11:19.809076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip>
31537 10:11:19.809402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip
31539 10:11:19.842718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass>
31540 10:11:19.842997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass
31542 10:11:19.875463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip>
31543 10:11:19.875943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip
31545 10:11:19.908907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip>
31546 10:11:19.909377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip
31548 10:11:19.942340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass
31550 10:11:19.942958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass>
31551 10:11:19.979128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip>
31552 10:11:19.979552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip
31554 10:11:20.014661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip>
31555 10:11:20.015055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip
31557 10:11:20.051094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass>
31558 10:11:20.051497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass
31560 10:11:20.087096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip>
31561 10:11:20.087548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip
31563 10:11:20.122516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip>
31564 10:11:20.122997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip
31566 10:11:20.155939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass
31568 10:11:20.156693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass>
31569 10:11:20.189058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip>
31570 10:11:20.189467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip
31572 10:11:20.225117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip
31574 10:11:20.225565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip>
31575 10:11:20.263704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass>
31576 10:11:20.264201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass
31578 10:11:20.300911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip>
31579 10:11:20.301294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip
31581 10:11:20.338436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip>
31582 10:11:20.338788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip
31584 10:11:20.373076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass>
31585 10:11:20.373475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass
31587 10:11:20.413097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip>
31588 10:11:20.413563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip
31590 10:11:20.448228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip>
31591 10:11:20.448663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip
31593 10:11:20.483824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass>
31594 10:11:20.484318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass
31596 10:11:20.523434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip>
31597 10:11:20.523983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip
31599 10:11:20.562447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip>
31600 10:11:20.562891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip
31602 10:11:20.594869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass>
31603 10:11:20.595321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass
31605 10:11:20.627448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip>
31606 10:11:20.627920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip
31608 10:11:20.660842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip>
31609 10:11:20.661228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip
31611 10:11:20.694613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass
31613 10:11:20.695156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass>
31614 10:11:20.727428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip>
31615 10:11:20.727860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip
31617 10:11:20.761867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip>
31618 10:11:20.762344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip
31620 10:11:20.792923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass>
31621 10:11:20.793308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass
31623 10:11:20.827105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip
31625 10:11:20.827697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip>
31626 10:11:20.859344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip>
31627 10:11:20.859642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip
31629 10:11:20.893715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass
31631 10:11:20.894275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass>
31632 10:11:20.926855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip>
31633 10:11:20.927304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip
31635 10:11:20.960349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip
31637 10:11:20.960780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip>
31638 10:11:20.994768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass
31640 10:11:20.995187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass>
31641 10:11:21.027990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip
31643 10:11:21.028321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip>
31644 10:11:21.060734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip>
31645 10:11:21.061130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip
31647 10:11:21.093781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass
31649 10:11:21.094336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass>
31650 10:11:21.129283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip
31652 10:11:21.129904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip>
31653 10:11:21.167279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip>
31654 10:11:21.167629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip
31656 10:11:21.203519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass>
31657 10:11:21.203910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass
31659 10:11:21.238703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip>
31660 10:11:21.239146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip
31662 10:11:21.274748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip
31664 10:11:21.275206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip>
31665 10:11:21.307571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass>
31666 10:11:21.307896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass
31668 10:11:21.339276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip>
31669 10:11:21.339649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip
31671 10:11:21.370520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip
31673 10:11:21.370856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip>
31674 10:11:21.402005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass>
31675 10:11:21.402289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass
31677 10:11:21.432975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip>
31678 10:11:21.433383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip
31680 10:11:21.464659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip>
31681 10:11:21.465061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip
31683 10:11:21.496778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass
31685 10:11:21.497330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass>
31686 10:11:21.527743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip>
31687 10:11:21.528185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip
31689 10:11:21.558848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip>
31690 10:11:21.559297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip
31692 10:11:21.589711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass>
31693 10:11:21.590175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass
31695 10:11:21.620716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip>
31696 10:11:21.621182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip
31698 10:11:21.653002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip
31700 10:11:21.653554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip>
31701 10:11:21.683742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass>
31702 10:11:21.684166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass
31704 10:11:21.715131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip>
31705 10:11:21.715572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip
31707 10:11:21.746570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip>
31708 10:11:21.746977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip
31710 10:11:21.778148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass>
31711 10:11:21.778592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass
31713 10:11:21.810189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip>
31714 10:11:21.810638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip
31716 10:11:21.842102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip>
31717 10:11:21.842562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip
31719 10:11:21.873611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass>
31720 10:11:21.874072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass
31722 10:11:21.906172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip>
31723 10:11:21.906611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip
31725 10:11:21.937784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip
31727 10:11:21.938405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip>
31728 10:11:21.969315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass
31730 10:11:21.969903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass>
31731 10:11:22.000761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip
31733 10:11:22.001330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip>
31734 10:11:22.034482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip
31736 10:11:22.034947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip>
31737 10:11:22.066637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass
31739 10:11:22.067198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass>
31740 10:11:22.101071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip>
31741 10:11:22.101496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip
31743 10:11:22.135868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip
31745 10:11:22.136431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip>
31746 10:11:22.171101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass>
31747 10:11:22.171472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass
31749 10:11:22.204479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip>
31750 10:11:22.204974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip
31752 10:11:22.236586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip>
31753 10:11:22.236909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip
31755 10:11:22.268185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass>
31756 10:11:22.268478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass
31758 10:11:22.301931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip
31760 10:11:22.302476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip>
31761 10:11:22.333914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip>
31762 10:11:22.334359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip
31764 10:11:22.366404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass
31766 10:11:22.366945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass>
31767 10:11:22.398147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip
31769 10:11:22.398598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip>
31770 10:11:22.429091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip>
31771 10:11:22.429465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip
31773 10:11:22.460731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass
31775 10:11:22.461176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass>
31776 10:11:22.491531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip>
31777 10:11:22.491880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip
31779 10:11:22.523541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip
31781 10:11:22.523965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip>
31782 10:11:22.554357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass>
31783 10:11:22.554657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass
31785 10:11:22.585071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip>
31786 10:11:22.585521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip
31788 10:11:22.617422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip
31790 10:11:22.618047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip>
31791 10:11:22.649093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass>
31792 10:11:22.649557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass
31794 10:11:22.680663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip>
31795 10:11:22.681129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip
31797 10:11:22.711556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip
31799 10:11:22.712167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip>
31800 10:11:22.742904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass
31802 10:11:22.743494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass>
31803 10:11:22.774349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip
31805 10:11:22.774911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip>
31806 10:11:22.806365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip>
31807 10:11:22.806820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip
31809 10:11:22.837870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass
31811 10:11:22.838336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass>
31812 10:11:22.868313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip>
31813 10:11:22.868604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip
31815 10:11:22.899837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip>
31816 10:11:22.900129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip
31818 10:11:22.931590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass
31820 10:11:22.931895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass>
31821 10:11:22.963179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip
31823 10:11:22.963493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip>
31824 10:11:22.995898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip>
31825 10:11:22.996190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip
31827 10:11:23.026877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass
31829 10:11:23.027323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass>
31830 10:11:23.058318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip>
31831 10:11:23.058739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip
31833 10:11:23.089549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip>
31834 10:11:23.090033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip
31836 10:11:23.120469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass>
31837 10:11:23.120914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass
31839 10:11:23.152772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip>
31840 10:11:23.153212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip
31842 10:11:23.184841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip
31844 10:11:23.185377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip>
31845 10:11:23.215996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass>
31846 10:11:23.216438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass
31848 10:11:23.247279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip
31850 10:11:23.247810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip>
31851 10:11:23.279623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip>
31852 10:11:23.280052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip
31854 10:11:23.311548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass>
31855 10:11:23.311978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass
31857 10:11:23.343412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip
31859 10:11:23.343845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip>
31860 10:11:23.375128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip>
31861 10:11:23.375530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip
31863 10:11:23.406558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass
31865 10:11:23.406993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass>
31866 10:11:23.439658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip
31868 10:11:23.440107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip>
31869 10:11:23.471575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip
31871 10:11:23.472247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip>
31872 10:11:23.510151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass>
31873 10:11:23.510621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass
31875 10:11:23.542667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip
31877 10:11:23.543201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip>
31878 10:11:23.575054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip>
31879 10:11:23.575507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip
31881 10:11:23.606822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass>
31882 10:11:23.607289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass
31884 10:11:23.638856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip>
31885 10:11:23.639426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip
31887 10:11:23.672913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip>
31888 10:11:23.673330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip
31890 10:11:23.728065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass>
31891 10:11:23.728445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass
31893 10:11:23.760017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip>
31894 10:11:23.760325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip
31896 10:11:23.791405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip>
31897 10:11:23.791790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip
31899 10:11:23.824647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass>
31900 10:11:23.825051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass
31902 10:11:23.857949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip
31904 10:11:23.858381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip>
31905 10:11:23.889806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip>
31906 10:11:23.890089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip
31908 10:11:23.921067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass>
31909 10:11:23.921437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass
31911 10:11:23.952488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip>
31912 10:11:23.952930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip
31914 10:11:23.985118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip>
31915 10:11:23.985639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip
31917 10:11:24.017336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass
31919 10:11:24.017931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass>
31920 10:11:24.048378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip>
31921 10:11:24.048735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip
31923 10:11:24.079358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip
31925 10:11:24.079913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip>
31926 10:11:24.110574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass>
31927 10:11:24.111037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass
31929 10:11:24.141930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip>
31930 10:11:24.142327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip
31932 10:11:24.174473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip>
31933 10:11:24.174872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip
31935 10:11:24.206801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass
31937 10:11:24.207251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass>
31938 10:11:24.239154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip
31940 10:11:24.239599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip>
31941 10:11:24.270450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip
31943 10:11:24.270888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip>
31944 10:11:24.302078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass>
31945 10:11:24.302481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass
31947 10:11:24.333865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip>
31948 10:11:24.334270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip
31950 10:11:24.366282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip>
31951 10:11:24.366704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip
31953 10:11:24.398577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass>
31954 10:11:24.399005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass
31956 10:11:24.431059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip>
31957 10:11:24.431474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip
31959 10:11:24.462653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip>
31960 10:11:24.463051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip
31962 10:11:24.494307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass>
31963 10:11:24.494706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass
31965 10:11:24.526480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip>
31966 10:11:24.526902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip
31968 10:11:24.558418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip>
31969 10:11:24.558815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip
31971 10:11:24.590334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass
31973 10:11:24.590776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass>
31974 10:11:24.621861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip>
31975 10:11:24.622314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip
31977 10:11:24.652897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip>
31978 10:11:24.653367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip
31980 10:11:24.683858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass
31982 10:11:24.684378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass>
31983 10:11:24.715800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip>
31984 10:11:24.716178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip
31986 10:11:24.747171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip>
31987 10:11:24.747543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip
31989 10:11:24.778150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass>
31990 10:11:24.778523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass
31992 10:11:24.809072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip
31994 10:11:24.809513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip>
31995 10:11:24.840053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip>
31996 10:11:24.840411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip
31998 10:11:24.871973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass>
31999 10:11:24.872346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass
32001 10:11:24.903415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip
32003 10:11:24.903916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip>
32004 10:11:24.934606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip>
32005 10:11:24.935005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip
32007 10:11:24.966072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass>
32008 10:11:24.966513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass
32010 10:11:24.998076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip>
32011 10:11:24.998516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip
32013 10:11:25.030303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip
32015 10:11:25.030888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip>
32016 10:11:25.064757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass>
32017 10:11:25.065224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass
32019 10:11:25.095776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip>
32020 10:11:25.096227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip
32022 10:11:25.127445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip>
32023 10:11:25.127883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip
32025 10:11:25.158892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass
32027 10:11:25.159386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass>
32028 10:11:25.190986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip>
32029 10:11:25.191389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip
32031 10:11:25.224554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip
32033 10:11:25.225130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip>
32034 10:11:25.256637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass>
32035 10:11:25.257009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass
32037 10:11:25.288114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip>
32038 10:11:25.288490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip
32040 10:11:25.319589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip>
32041 10:11:25.319950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip
32043 10:11:25.351030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass>
32044 10:11:25.351421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass
32046 10:11:25.384032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip>
32047 10:11:25.384440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip
32049 10:11:25.415769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip>
32050 10:11:25.416174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip
32052 10:11:25.447875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass
32054 10:11:25.448458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass>
32055 10:11:25.478580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip>
32056 10:11:25.478932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip
32058 10:11:25.509206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip>
32059 10:11:25.509564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip
32061 10:11:25.540756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass>
32062 10:11:25.541143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass
32064 10:11:25.572527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip>
32065 10:11:25.572892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip
32067 10:11:25.604161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip>
32068 10:11:25.604466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip
32070 10:11:25.635849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass>
32071 10:11:25.636139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass
32073 10:11:25.667627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip>
32074 10:11:25.667999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip
32076 10:11:25.698868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip>
32077 10:11:25.699221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip
32079 10:11:25.731667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass>
32080 10:11:25.732052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass
32082 10:11:25.763854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip>
32083 10:11:25.764268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip
32085 10:11:25.795528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip>
32086 10:11:25.795912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip
32088 10:11:25.827355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass
32090 10:11:25.827757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass>
32091 10:11:25.859333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip
32093 10:11:25.859902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip>
32094 10:11:25.891695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip>
32095 10:11:25.892174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip
32097 10:11:25.924448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass>
32098 10:11:25.924858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass
32100 10:11:25.956430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip>
32101 10:11:25.956833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip
32103 10:11:25.988430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip>
32104 10:11:25.988848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip
32106 10:11:26.020539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass>
32107 10:11:26.020960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass
32109 10:11:26.054096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip
32111 10:11:26.054537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip>
32112 10:11:26.087263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip>
32113 10:11:26.087687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip
32115 10:11:26.118575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass
32117 10:11:26.119143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass>
32118 10:11:26.149681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip>
32119 10:11:26.150119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip
32121 10:11:26.182837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip>
32122 10:11:26.183222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip
32124 10:11:26.215543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass>
32125 10:11:26.216003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass
32127 10:11:26.248917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip>
32128 10:11:26.249354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip
32130 10:11:26.281848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip>
32131 10:11:26.282310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip
32133 10:11:26.313461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass
32135 10:11:26.314001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass>
32136 10:11:26.344724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip
32138 10:11:26.345180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip>
32139 10:11:26.376579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip
32141 10:11:26.377164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip>
32142 10:11:26.410759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass
32144 10:11:26.411382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass>
32145 10:11:26.442486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip
32147 10:11:26.443012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip>
32148 10:11:26.474552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip
32150 10:11:26.474987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip>
32151 10:11:26.507083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass
32153 10:11:26.507618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass>
32154 10:11:26.539332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip
32156 10:11:26.539868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip>
32157 10:11:26.573690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip>
32158 10:11:26.574149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip
32160 10:11:26.606077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass>
32161 10:11:26.606528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass
32163 10:11:26.638292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip>
32164 10:11:26.638671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip
32166 10:11:26.669688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip>
32167 10:11:26.670004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip
32169 10:11:26.700686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass
32171 10:11:26.701155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass>
32172 10:11:26.732198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip>
32173 10:11:26.732553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip
32175 10:11:26.764698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip
32177 10:11:26.765127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip>
32178 10:11:26.796837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass>
32179 10:11:26.797271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass
32181 10:11:26.830418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip>
32182 10:11:26.830887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip
32184 10:11:26.863063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip
32186 10:11:26.863824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip>
32187 10:11:26.917778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass>
32188 10:11:26.918294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass
32190 10:11:26.958700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip
32192 10:11:26.959137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip>
32193 10:11:26.990928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip>
32194 10:11:26.991334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip
32196 10:11:27.022847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass
32198 10:11:27.023280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass>
32199 10:11:27.055451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip>
32200 10:11:27.055870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip
32202 10:11:27.089629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip>
32203 10:11:27.090060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip
32205 10:11:27.121831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass>
32206 10:11:27.122246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass
32208 10:11:27.153986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip>
32209 10:11:27.154403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip
32211 10:11:27.186441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip
32213 10:11:27.186875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip>
32214 10:11:27.218633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass
32216 10:11:27.219279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass>
32217 10:11:27.251499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip
32219 10:11:27.252205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip>
32220 10:11:27.284273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip>
32221 10:11:27.284728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip
32223 10:11:27.316425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass>
32224 10:11:27.316883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass
32226 10:11:27.349685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip>
32227 10:11:27.350094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip
32229 10:11:27.383127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip>
32230 10:11:27.383574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip
32232 10:11:27.428354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass
32234 10:11:27.428793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass>
32235 10:11:27.460404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip>
32236 10:11:27.460855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip
32238 10:11:27.492270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip
32240 10:11:27.492817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip>
32241 10:11:27.524171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass>
32242 10:11:27.524598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass
32244 10:11:27.556736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip>
32245 10:11:27.557173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip
32247 10:11:27.589908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip
32249 10:11:27.590352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip>
32250 10:11:27.622320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass>
32251 10:11:27.622695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass
32253 10:11:27.654516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip
32255 10:11:27.655063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip>
32256 10:11:27.686422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip
32258 10:11:27.686970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip>
32259 10:11:27.719026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass
32261 10:11:27.719551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass>
32262 10:11:27.751074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip>
32263 10:11:27.751534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip
32265 10:11:27.784286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip
32267 10:11:27.784906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip>
32268 10:11:27.816512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass
32270 10:11:27.817072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass>
32271 10:11:27.848616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip
32273 10:11:27.849190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip>
32274 10:11:27.880968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip>
32275 10:11:27.881403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip
32277 10:11:27.913551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass
32279 10:11:27.914301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass>
32280 10:11:27.946882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip>
32281 10:11:27.947412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip
32283 10:11:27.980601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip
32285 10:11:27.981168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip>
32286 10:11:28.013062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass>
32287 10:11:28.013604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass
32289 10:11:28.046509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip>
32290 10:11:28.046964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip
32292 10:11:28.079737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip>
32293 10:11:28.080202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip
32295 10:11:28.114124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass>
32296 10:11:28.114569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass
32298 10:11:28.147949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip>
32299 10:11:28.148371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip
32301 10:11:28.182395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip
32303 10:11:28.182949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip>
32304 10:11:28.214544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass
32306 10:11:28.215145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass>
32307 10:11:28.248720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip
32309 10:11:28.249267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip>
32310 10:11:28.285384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip
32312 10:11:28.285938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip>
32313 10:11:28.319843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass>
32314 10:11:28.320346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass
32316 10:11:28.352316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip>
32317 10:11:28.352775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip
32319 10:11:28.383953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip>
32320 10:11:28.384406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip
32322 10:11:28.415171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass
32324 10:11:28.415708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass>
32325 10:11:28.449325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip
32327 10:11:28.449901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip>
32328 10:11:28.481018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip>
32329 10:11:28.481494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip
32331 10:11:28.513439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass
32333 10:11:28.514065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass>
32334 10:11:28.546510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip
32336 10:11:28.547089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip>
32337 10:11:28.577941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip>
32338 10:11:28.578401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip
32340 10:11:28.610799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass
32342 10:11:28.611357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass>
32343 10:11:28.643226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip
32345 10:11:28.643728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip>
32346 10:11:28.675487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip
32348 10:11:28.676039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip>
32349 10:11:28.706978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass
32351 10:11:28.707506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass>
32352 10:11:28.738360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip>
32353 10:11:28.738830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip
32355 10:11:28.771455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip
32357 10:11:28.772168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip>
32358 10:11:28.804450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass
32360 10:11:28.804999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass>
32361 10:11:28.857981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip>
32362 10:11:28.858450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip
32364 10:11:28.890505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip>
32365 10:11:28.890929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip
32367 10:11:28.923797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass>
32368 10:11:28.924225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass
32370 10:11:28.963531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip>
32371 10:11:28.964009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip
32373 10:11:28.995877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip
32375 10:11:28.996464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip>
32376 10:11:29.027885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass
32378 10:11:29.028437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass>
32379 10:11:29.059900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip
32381 10:11:29.060345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip>
32382 10:11:29.093023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip
32384 10:11:29.093847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip>
32385 10:11:29.126424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass>
32386 10:11:29.126869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass
32388 10:11:29.160329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip
32390 10:11:29.160884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip>
32391 10:11:29.193449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip
32393 10:11:29.194035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip>
32394 10:11:29.226583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass
32396 10:11:29.227004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass>
32397 10:11:29.259351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip
32399 10:11:29.259830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip>
32400 10:11:29.294245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip
32402 10:11:29.294828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip>
32403 10:11:29.326804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass>
32404 10:11:29.327250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass
32406 10:11:29.360279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip
32408 10:11:29.360842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip>
32409 10:11:29.393457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip
32411 10:11:29.394058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip>
32412 10:11:29.425930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass>
32413 10:11:29.426404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass
32415 10:11:29.463254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip
32417 10:11:29.463823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip>
32418 10:11:29.496656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip>
32419 10:11:29.497067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip
32421 10:11:29.528612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass
32423 10:11:29.529162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass>
32424 10:11:29.560208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip>
32425 10:11:29.560620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip
32427 10:11:29.591681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip>
32428 10:11:29.592072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip
32430 10:11:29.624432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass>
32431 10:11:29.624858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass
32433 10:11:29.657423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip
32435 10:11:29.657870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip>
32436 10:11:29.692384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip
32438 10:11:29.692820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip>
32439 10:11:29.723835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=pass>
32440 10:11:29.724304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=pass
32442 10:11:29.755475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass>
32443 10:11:29.755901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass
32445 10:11:29.787860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass>
32446 10:11:29.788271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass
32448 10:11:29.820536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass>
32449 10:11:29.820931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass
32451 10:11:29.854040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass>
32452 10:11:29.854424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass
32454 10:11:29.886019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32455 10:11:29.886383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32457 10:11:29.918492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32459 10:11:29.918962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32460 10:11:29.951058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32461 10:11:29.951520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32463 10:11:29.984470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass>
32464 10:11:29.984914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass
32466 10:11:30.017451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass
32468 10:11:30.018010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass>
32469 10:11:30.050067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32470 10:11:30.050510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32472 10:11:30.082700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32474 10:11:30.083264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32475 10:11:30.115320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32476 10:11:30.115807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32478 10:11:30.148486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass>
32479 10:11:30.148959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass
32481 10:11:30.181886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail>
32482 10:11:30.182325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail
32484 10:11:30.214313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail>
32485 10:11:30.214730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail
32487 10:11:30.247865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass
32489 10:11:30.248325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass>
32490 10:11:30.280357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32491 10:11:30.280754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32493 10:11:30.320377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32494 10:11:30.320829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32496 10:11:30.354307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32498 10:11:30.354851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32499 10:11:30.394470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32500 10:11:30.394855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32502 10:11:30.427865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail
32504 10:11:30.428324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail>
32505 10:11:30.461317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32507 10:11:30.461698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32508 10:11:30.495746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32509 10:11:30.496220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32511 10:11:30.528405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32512 10:11:30.528919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32514 10:11:30.560270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32515 10:11:30.560681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32517 10:11:30.593760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32518 10:11:30.594163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32520 10:11:30.627574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32521 10:11:30.628034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32523 10:11:30.660434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32524 10:11:30.660908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32526 10:11:30.692255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32527 10:11:30.692648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32529 10:11:30.724376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32530 10:11:30.724775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32532 10:11:30.756430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32533 10:11:30.756827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32535 10:11:30.788773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32536 10:11:30.789210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32538 10:11:30.822606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32539 10:11:30.823076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32541 10:11:30.855334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=fail
32543 10:11:30.855835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=fail>
32544 10:11:30.886304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail>
32545 10:11:30.886708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail
32547 10:11:30.916951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=fail>
32548 10:11:30.917354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=fail
32550 10:11:30.948708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32551 10:11:30.949118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32553 10:11:30.981474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32555 10:11:30.982067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32556 10:11:31.014516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32557 10:11:31.014948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32559 10:11:31.046594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32560 10:11:31.047075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32562 10:11:31.078676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32563 10:11:31.079129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32565 10:11:31.110544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32566 10:11:31.110962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32568 10:11:31.143134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32569 10:11:31.143558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32571 10:11:31.176455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32572 10:11:31.176930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32574 10:11:31.208502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32575 10:11:31.208908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32577 10:11:31.240621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32578 10:11:31.241018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32580 10:11:31.273088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32581 10:11:31.273490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32583 10:11:31.305382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32585 10:11:31.305849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32586 10:11:31.338809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32587 10:11:31.339217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32589 10:11:31.372209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32590 10:11:31.372605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32592 10:11:31.404110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32594 10:11:31.404525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32595 10:11:31.435977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32596 10:11:31.436369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32598 10:11:31.468279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32599 10:11:31.468688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32601 10:11:31.501054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32602 10:11:31.501473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32604 10:11:31.534400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32605 10:11:31.534876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32607 10:11:31.566648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32608 10:11:31.567108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32610 10:11:31.599947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail>
32611 10:11:31.600368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail
32613 10:11:31.634486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail>
32614 10:11:31.635025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail
32616 10:11:31.668420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=fail>
32617 10:11:31.668870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=fail
32619 10:11:31.700398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
32620 10:11:31.700892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
32622 10:11:31.731975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
32624 10:11:31.732596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
32625 10:11:31.763595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass
32627 10:11:31.764214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass>
32628 10:11:31.795366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass>
32629 10:11:31.795859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass
32631 10:11:31.828060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass
32633 10:11:31.828533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass>
32634 10:11:31.862121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
32636 10:11:31.862570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
32637 10:11:31.898520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail>
32638 10:11:31.898937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail
32640 10:11:31.931309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail>
32641 10:11:31.931723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail
32643 10:11:31.963763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass>
32644 10:11:31.964170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass
32646 10:11:31.997374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail
32648 10:11:31.997837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail>
32649 10:11:32.030082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail>
32650 10:11:32.030543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail
32652 10:11:32.062485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32653 10:11:32.063051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32655 10:11:32.094019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32656 10:11:32.094581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32658 10:11:32.126094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32660 10:11:32.126656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32661 10:11:32.158853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32662 10:11:32.159365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32664 10:11:32.192249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32665 10:11:32.192677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32667 10:11:32.226139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32669 10:11:32.226705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32670 10:11:32.258462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32671 10:11:32.258910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32673 10:11:32.290450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32674 10:11:32.290930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32676 10:11:32.324545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32678 10:11:32.324941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32679 10:11:32.357980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32680 10:11:32.358342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32682 10:11:32.391368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32683 10:11:32.391796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32685 10:11:32.427919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32686 10:11:32.428348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32688 10:11:32.461264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32690 10:11:32.461662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32691 10:11:32.494852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32692 10:11:32.495225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32694 10:11:32.528699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32695 10:11:32.529059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32697 10:11:32.561844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32698 10:11:32.562256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32700 10:11:32.596744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32701 10:11:32.597170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32703 10:11:32.632563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32704 10:11:32.632975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32706 10:11:32.667586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32707 10:11:32.668008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32709 10:11:32.706425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32710 10:11:32.706786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32712 10:11:32.740080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32714 10:11:32.740676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32715 10:11:32.771592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32716 10:11:32.772035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32718 10:11:32.803099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32719 10:11:32.803595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32721 10:11:32.836455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32723 10:11:32.837062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32724 10:11:32.875218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32725 10:11:32.875658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32727 10:11:32.907610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32728 10:11:32.908083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32730 10:11:32.939130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32731 10:11:32.939529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32733 10:11:32.983201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32734 10:11:32.983675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32736 10:11:33.015666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32737 10:11:33.016226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32739 10:11:33.048744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32741 10:11:33.049382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32742 10:11:33.080871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32743 10:11:33.081285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32745 10:11:33.112984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32746 10:11:33.113398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32748 10:11:33.146792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32749 10:11:33.147210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32751 10:11:33.180778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32752 10:11:33.181192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32754 10:11:33.214284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32755 10:11:33.214751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32757 10:11:33.246713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32758 10:11:33.247197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32760 10:11:33.279028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32761 10:11:33.279485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32763 10:11:33.311119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32764 10:11:33.311532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32766 10:11:33.344737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32768 10:11:33.345389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32769 10:11:33.378109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32770 10:11:33.378584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32772 10:11:33.410553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32773 10:11:33.410979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32775 10:11:33.442864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32776 10:11:33.443288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32778 10:11:33.475123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32779 10:11:33.475598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32781 10:11:33.508652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32782 10:11:33.509071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32784 10:11:33.542620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32785 10:11:33.543082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32787 10:11:33.576823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32788 10:11:33.577298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32790 10:11:33.609940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32791 10:11:33.610369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32793 10:11:33.643337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32794 10:11:33.643765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32796 10:11:33.676548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32797 10:11:33.677003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32799 10:11:33.713645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32801 10:11:33.714246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32802 10:11:33.746197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32803 10:11:33.746599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32805 10:11:33.778248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32806 10:11:33.778666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32808 10:11:33.810534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32809 10:11:33.810984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32811 10:11:33.843323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32813 10:11:33.843789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32814 10:11:33.876917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32815 10:11:33.877332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32817 10:11:33.909028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32819 10:11:33.909617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32820 10:11:33.967183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32822 10:11:33.967760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32823 10:11:33.999684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32824 10:11:34.000130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32826 10:11:34.032512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32827 10:11:34.032982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32829 10:11:34.068681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32830 10:11:34.069118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32832 10:11:34.102438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32833 10:11:34.102824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32835 10:11:34.134531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32836 10:11:34.134895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32838 10:11:34.166416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32839 10:11:34.166903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32841 10:11:34.198676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32842 10:11:34.199096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32844 10:11:34.230905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=pass>
32845 10:11:34.231328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=pass
32847 10:11:34.263475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass>
32848 10:11:34.263919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass
32850 10:11:34.294582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass
32852 10:11:34.295052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass>
32853 10:11:34.325789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass>
32854 10:11:34.326210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass
32856 10:11:34.358063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass
32858 10:11:34.358625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass>
32859 10:11:34.389167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass
32861 10:11:34.389643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass>
32862 10:11:34.420064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass>
32863 10:11:34.420479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass
32865 10:11:34.451217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass>
32866 10:11:34.451677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass
32868 10:11:34.482880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass
32870 10:11:34.483419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass>
32871 10:11:34.516126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass>
32872 10:11:34.516566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass
32874 10:11:34.548831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass
32876 10:11:34.549483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass>
32877 10:11:34.580554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass
32879 10:11:34.581178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass>
32880 10:11:34.612338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass>
32881 10:11:34.612809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass
32883 10:11:34.643237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32884 10:11:34.643704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass
32886 10:11:34.675950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass
32888 10:11:34.676409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32889 10:11:34.709818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass>
32890 10:11:34.710191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass
32892 10:11:34.746620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass>
32893 10:11:34.746990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass
32895 10:11:34.784752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass>
32896 10:11:34.785148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass
32898 10:11:34.816826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass
32900 10:11:34.817212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass>
32901 10:11:34.849098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
32902 10:11:34.849540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
32904 10:11:34.886941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass>
32905 10:11:34.887335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass
32907 10:11:34.922566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass>
32908 10:11:34.923029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass
32910 10:11:34.962124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass>
32911 10:11:34.962591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass
32913 10:11:34.996108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass
32915 10:11:34.996526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass>
32916 10:11:35.031903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass>
32917 10:11:35.032247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass
32919 10:11:35.066782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass
32921 10:11:35.067198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass>
32922 10:11:35.102204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass>
32923 10:11:35.102544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass
32925 10:11:35.139522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass>
32926 10:11:35.139886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass
32928 10:11:35.174955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass
32930 10:11:35.175368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass>
32931 10:11:35.209735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass>
32932 10:11:35.210200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass
32934 10:11:35.242543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass>
32935 10:11:35.243013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass
32937 10:11:35.274444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass>
32938 10:11:35.274880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass
32940 10:11:35.308292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32941 10:11:35.308751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass
32943 10:11:35.340076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32944 10:11:35.340492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass
32946 10:11:35.371830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass>
32947 10:11:35.372281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass
32949 10:11:35.404515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass>
32950 10:11:35.404989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass
32952 10:11:35.436885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass>
32953 10:11:35.437351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass
32955 10:11:35.468398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass
32957 10:11:35.469021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass>
32958 10:11:35.500608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
32960 10:11:35.501228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
32961 10:11:35.532272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
32962 10:11:35.532701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
32964 10:11:35.563419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass>
32965 10:11:35.563891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass
32967 10:11:35.594945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
32969 10:11:35.595595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
32970 10:11:35.626666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
32971 10:11:35.627135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
32973 10:11:35.659074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
32974 10:11:35.659540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
32976 10:11:35.690724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
32977 10:11:35.691198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
32979 10:11:35.722301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
32980 10:11:35.722707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
32982 10:11:35.754252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass>
32983 10:11:35.754701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass
32985 10:11:35.786644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
32987 10:11:35.787220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
32988 10:11:35.818736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass
32990 10:11:35.819353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass>
32991 10:11:35.850814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
32993 10:11:35.851470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
32994 10:11:35.888472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass>
32995 10:11:35.888954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass
32997 10:11:35.920663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
32999 10:11:35.921237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
33000 10:11:35.954299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass>
33001 10:11:35.954766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass
33003 10:11:35.986526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
33004 10:11:35.987009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
33006 10:11:36.018694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass>
33007 10:11:36.019170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass
33009 10:11:36.050627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
33010 10:11:36.051095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
33012 10:11:36.090171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass
33014 10:11:36.090524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass>
33015 10:11:36.122625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
33017 10:11:36.122993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
33018 10:11:36.154943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass
33020 10:11:36.155295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass>
33021 10:11:36.187796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
33023 10:11:36.188154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
33024 10:11:36.220302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass
33026 10:11:36.220716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass>
33027 10:11:36.259569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
33029 10:11:36.260017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
33030 10:11:36.292260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass>
33031 10:11:36.292577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass
33033 10:11:36.323520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
33034 10:11:36.323899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
33036 10:11:36.356559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass
33038 10:11:36.356870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass>
33039 10:11:36.389129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
33040 10:11:36.389444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
33042 10:11:36.423608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
33044 10:11:36.423976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
33045 10:11:36.454797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
33047 10:11:36.455333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
33048 10:11:36.486502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
33049 10:11:36.486975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
33051 10:11:36.518070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
33053 10:11:36.518624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
33054 10:11:36.549712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
33055 10:11:36.550085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
33057 10:11:36.580850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
33058 10:11:36.581323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
33060 10:11:36.612458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
33061 10:11:36.612939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
33063 10:11:36.644182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
33064 10:11:36.644652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
33066 10:11:36.676453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
33067 10:11:36.676889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
33069 10:11:36.711912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
33070 10:11:36.712375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
33072 10:11:36.743291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
33073 10:11:36.743749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
33075 10:11:36.775539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass>
33076 10:11:36.775999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass
33078 10:11:36.807088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33080 10:11:36.807643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33081 10:11:36.838472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass
33083 10:11:36.838914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33084 10:11:36.870599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33086 10:11:36.871145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33087 10:11:36.902786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33089 10:11:36.903343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33090 10:11:36.936821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33091 10:11:36.937248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass
33093 10:11:36.971672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33094 10:11:36.972063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33096 10:11:37.004286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33098 10:11:37.004876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33099 10:11:37.035393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33100 10:11:37.035898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass
33102 10:11:37.076377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33104 10:11:37.076937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33105 10:11:37.117551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33107 10:11:37.118004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33108 10:11:37.152539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass
33110 10:11:37.153039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33111 10:11:37.187580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33112 10:11:37.187978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33114 10:11:37.222454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33115 10:11:37.222833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33117 10:11:37.257417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass
33119 10:11:37.257957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33120 10:11:37.289453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33122 10:11:37.289957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33123 10:11:37.322040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass>
33124 10:11:37.322457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass
33126 10:11:37.354429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33127 10:11:37.354877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33129 10:11:37.386328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33130 10:11:37.386757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass
33132 10:11:37.422318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33133 10:11:37.422778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33135 10:11:37.455354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33137 10:11:37.456115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33138 10:11:37.490853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33139 10:11:37.491310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass
33141 10:11:37.524296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33142 10:11:37.524761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33144 10:11:37.556947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33146 10:11:37.557416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33147 10:11:37.589522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass
33149 10:11:37.590001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33150 10:11:37.624969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33152 10:11:37.625449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33153 10:11:37.658592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33155 10:11:37.658958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33156 10:11:37.706860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33157 10:11:37.707341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass
33159 10:11:37.754955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33161 10:11:37.755481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33162 10:11:37.792732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33163 10:11:37.793214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33165 10:11:37.827763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33166 10:11:37.828241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass
33168 10:11:37.864680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33170 10:11:37.865143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33171 10:11:37.915008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass>
33172 10:11:37.915443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass
33174 10:11:37.965472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33176 10:11:37.965897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33177 10:11:38.016276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33178 10:11:38.016831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass
33180 10:11:38.063855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33181 10:11:38.064241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33183 10:11:38.112281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33184 10:11:38.112713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33186 10:11:38.159507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33187 10:11:38.159913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass
33189 10:11:38.196376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33190 10:11:38.196790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33192 10:11:38.232786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33193 10:11:38.233186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33195 10:11:38.272865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33196 10:11:38.273249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass
33198 10:11:38.310921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33199 10:11:38.311336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33201 10:11:38.347102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33202 10:11:38.347474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33204 10:11:38.388041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33205 10:11:38.388925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass
33207 10:11:38.423860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33208 10:11:38.424369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33210 10:11:38.458069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33211 10:11:38.458630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33213 10:11:38.501940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33214 10:11:38.502370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass
33216 10:11:38.544356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33218 10:11:38.544849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33219 10:11:38.596081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass
33221 10:11:38.596670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass>
33222 10:11:38.643518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33223 10:11:38.643953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33225 10:11:38.682227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33226 10:11:38.682611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass
33228 10:11:38.718646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33229 10:11:38.719072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33231 10:11:38.751354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33233 10:11:38.751843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33234 10:11:38.786032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass
33236 10:11:38.786488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33237 10:11:38.820344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33238 10:11:38.820646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33240 10:11:38.855790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33241 10:11:38.856110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33243 10:11:38.890773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33244 10:11:38.891100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass
33246 10:11:38.926106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33247 10:11:38.926403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33249 10:11:38.962042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33251 10:11:38.962366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33252 10:11:38.997408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass
33254 10:11:38.997731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33255 10:11:39.042441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33256 10:11:39.042763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33258 10:11:39.118802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
33260 10:11:39.119173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
33261 10:11:39.156792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass>
33262 10:11:39.157217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass
33264 10:11:39.193153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass
33266 10:11:39.193625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
33267 10:11:39.230788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass>
33268 10:11:39.231170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass
33270 10:11:39.267361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
33272 10:11:39.267825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
33273 10:11:39.304010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass>
33274 10:11:39.304433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass
33276 10:11:39.339994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
33277 10:11:39.340500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass
33279 10:11:39.376042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
33280 10:11:39.376459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
33282 10:11:39.412964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass>
33283 10:11:39.413272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass
33285 10:11:39.450132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
33286 10:11:39.450464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass
33288 10:11:39.487432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
33290 10:11:39.487798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
33291 10:11:39.523399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass
33293 10:11:39.523760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass>
33294 10:11:39.559671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
33295 10:11:39.559973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass
33297 10:11:39.597082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
33299 10:11:39.597535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
33300 10:11:39.633804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass>
33301 10:11:39.634126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass
33303 10:11:39.670493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
33304 10:11:39.670899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass
33306 10:11:39.706918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
33307 10:11:39.707270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
33309 10:11:39.743902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass>
33310 10:11:39.744237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass
33312 10:11:39.779297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
33313 10:11:39.779639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass
33315 10:11:39.815298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass>
33316 10:11:39.815592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass
33318 10:11:39.851044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
33319 10:11:39.851359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
33321 10:11:39.887132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass>
33322 10:11:39.887432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass
33324 10:11:39.924672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass
33326 10:11:39.925286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
33327 10:11:39.961104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
33328 10:11:39.961535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
33330 10:11:39.998127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass>
33331 10:11:39.998587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass
33333 10:11:40.034301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
33334 10:11:40.034725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass
33336 10:11:40.070784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
33337 10:11:40.071258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
33339 10:11:40.107364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass>
33340 10:11:40.107841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass
33342 10:11:40.143730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass
33344 10:11:40.144156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
33345 10:11:40.179621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
33346 10:11:40.179910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
33348 10:11:40.215221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass>
33349 10:11:40.215526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass
33351 10:11:40.250694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
33352 10:11:40.250985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass
33354 10:11:40.287165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
33355 10:11:40.287464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
33357 10:11:40.323386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass>
33358 10:11:40.323680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass
33360 10:11:40.359460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
33361 10:11:40.359753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass
33363 10:11:40.394728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass>
33364 10:11:40.395131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass
33366 10:11:40.430861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
33367 10:11:40.431284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
33369 10:11:40.466608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass>
33370 10:11:40.467031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass
33372 10:11:40.502861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
33373 10:11:40.503281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass
33375 10:11:40.538834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
33376 10:11:40.539278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
33378 10:11:40.574649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass>
33379 10:11:40.575153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass
33381 10:11:40.611213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass
33383 10:11:40.611855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
33384 10:11:40.648218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
33385 10:11:40.648641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
33387 10:11:40.684278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass>
33388 10:11:40.684683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass
33390 10:11:40.720764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass
33392 10:11:40.721072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
33393 10:11:40.757293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
33395 10:11:40.757598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
33396 10:11:40.794740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass>
33397 10:11:40.795038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass
33399 10:11:40.831733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
33400 10:11:40.832019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass
33402 10:11:40.868166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
33403 10:11:40.868590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
33405 10:11:40.906268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass>
33406 10:11:40.906693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass
33408 10:11:40.943124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
33409 10:11:40.943549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass
33411 10:11:40.979887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass
33413 10:11:40.980356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass>
33414 10:11:41.016579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
33415 10:11:41.017001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
33417 10:11:41.052729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass
33419 10:11:41.053191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass>
33420 10:11:41.089975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
33421 10:11:41.090415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass
33423 10:11:41.126943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
33424 10:11:41.127330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
33426 10:11:41.164101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass
33428 10:11:41.164706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass>
33429 10:11:41.202126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
33430 10:11:41.202536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass
33432 10:11:41.238418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
33434 10:11:41.239000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
33435 10:11:41.275054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass
33437 10:11:41.275624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass>
33438 10:11:41.311264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
33439 10:11:41.311683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass
33441 10:11:41.347565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
33443 10:11:41.348000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
33444 10:11:41.384866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass>
33445 10:11:41.385290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass
33447 10:11:41.422386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass
33449 10:11:41.422954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
33450 10:11:41.459122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
33451 10:11:41.459578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
33453 10:11:41.496138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass>
33454 10:11:41.496550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass
33456 10:11:41.532444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
33457 10:11:41.532926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass
33459 10:11:41.568911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass>
33460 10:11:41.569336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass
33462 10:11:41.606133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
33463 10:11:41.606559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
33465 10:11:41.643747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass>
33466 10:11:41.644229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass
33468 10:11:41.680525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
33469 10:11:41.681018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass
33471 10:11:41.717418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
33473 10:11:41.718072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
33474 10:11:41.754408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass>
33475 10:11:41.754884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass
33477 10:11:41.791471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
33478 10:11:41.791987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass
33480 10:11:41.828096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
33482 10:11:41.828647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
33483 10:11:41.864530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass
33485 10:11:41.864978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass>
33486 10:11:41.900671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
33487 10:11:41.901003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass
33489 10:11:41.936720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
33490 10:11:41.937015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
33492 10:11:41.971534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass>
33493 10:11:41.971842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass
33495 10:11:42.006003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
33496 10:11:42.006302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass
33498 10:11:42.039198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
33499 10:11:42.039680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
33501 10:11:42.075501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass
33503 10:11:42.075881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass>
33504 10:11:42.108716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
33505 10:11:42.109149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass
33507 10:11:42.142156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass
33509 10:11:42.142595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass>
33510 10:11:42.178744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
33511 10:11:42.179224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
33513 10:11:42.214854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass
33515 10:11:42.215300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass>
33516 10:11:42.250795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
33517 10:11:42.251260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass
33519 10:11:42.284749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
33520 10:11:42.285230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
33522 10:11:42.321003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass>
33523 10:11:42.321495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass
33525 10:11:42.357001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass
33527 10:11:42.357571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
33528 10:11:42.394251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
33529 10:11:42.394710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
33531 10:11:42.427668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass>
33532 10:11:42.428080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass
33534 10:11:42.460879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass
33536 10:11:42.461520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
33537 10:11:42.498160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
33538 10:11:42.498582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
33540 10:11:42.534534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass>
33541 10:11:42.534940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass
33543 10:11:42.568701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
33544 10:11:42.569122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass
33546 10:11:42.601969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
33547 10:11:42.602445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
33549 10:11:42.636258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass>
33550 10:11:42.636721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass
33552 10:11:42.671819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
33553 10:11:42.672284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass
33555 10:11:42.706606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass>
33556 10:11:42.707062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass
33558 10:11:42.741493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
33560 10:11:42.741949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
33561 10:11:42.778282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass>
33562 10:11:42.778758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass
33564 10:11:42.814177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
33565 10:11:42.814646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass
33567 10:11:42.849168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
33569 10:11:42.849833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
33570 10:11:42.884444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass
33572 10:11:42.885122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass>
33573 10:11:42.920687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
33574 10:11:42.921145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass
33576 10:11:42.959749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
33577 10:11:42.960178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
33579 10:11:42.994476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass
33581 10:11:42.994964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass>
33582 10:11:43.030070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
33583 10:11:43.030426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass
33585 10:11:43.067400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
33586 10:11:43.067826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
33588 10:11:43.102106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass>
33589 10:11:43.102528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass
33591 10:11:43.139874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
33592 10:11:43.140355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass
33594 10:11:43.179192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
33596 10:11:43.179660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
33597 10:11:43.218646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass>
33598 10:11:43.219073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass
33600 10:11:43.256766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass
33602 10:11:43.257427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
33603 10:11:43.293414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass
33605 10:11:43.293885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass>
33606 10:11:43.331093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
33607 10:11:43.331529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
33609 10:11:43.370920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass>
33610 10:11:43.371301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass
33612 10:11:43.408917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
33613 10:11:43.409368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass
33615 10:11:43.446724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
33616 10:11:43.447146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
33618 10:11:43.483760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass>
33619 10:11:43.484261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass
33621 10:11:43.523225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
33622 10:11:43.523734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass
33624 10:11:43.558812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
33626 10:11:43.559400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
33627 10:11:43.592392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass>
33628 10:11:43.592767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass
33630 10:11:43.624282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass
33632 10:11:43.624689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
33633 10:11:43.656436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
33635 10:11:43.656881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
33636 10:11:43.692878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass
33638 10:11:43.693327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass>
33639 10:11:43.729438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass
33641 10:11:43.729901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
33642 10:11:43.763442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
33644 10:11:43.764024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
33645 10:11:43.797672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass
33647 10:11:43.798262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass>
33648 10:11:43.830502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
33649 10:11:43.830941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass
33651 10:11:43.864034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass>
33652 10:11:43.864431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass
33654 10:11:43.897792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
33656 10:11:43.898244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
33657 10:11:43.931416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass
33659 10:11:43.931874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass>
33660 10:11:43.964677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass
33662 10:11:43.965323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
33663 10:11:43.998306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
33665 10:11:43.998934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
33666 10:11:44.031997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass
33668 10:11:44.032620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass>
33669 10:11:44.067612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
33670 10:11:44.068095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass
33672 10:11:44.102457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
33673 10:11:44.102925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
33675 10:11:44.135796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass
33677 10:11:44.136351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass>
33678 10:11:44.179091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
33679 10:11:44.179440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass
33681 10:11:44.235542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
33682 10:11:44.235827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
33684 10:11:44.268445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass
33686 10:11:44.268726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass>
33687 10:11:44.301601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
33688 10:11:44.301883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass
33690 10:11:44.334375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
33691 10:11:44.334652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
33693 10:11:44.368509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass>
33694 10:11:44.368982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass
33696 10:11:44.403756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
33697 10:11:44.404218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass
33699 10:11:44.437431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass
33701 10:11:44.437730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass>
33702 10:11:44.470958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
33703 10:11:44.471311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
33705 10:11:44.504722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass>
33706 10:11:44.505075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass
33708 10:11:44.539141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
33709 10:11:44.539428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass
33711 10:11:44.574409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
33712 10:11:44.574768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
33714 10:11:44.610559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass
33716 10:11:44.610859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass>
33717 10:11:44.645446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass
33719 10:11:44.645892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
33720 10:11:44.679741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
33721 10:11:44.680158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
33723 10:11:44.714015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass>
33724 10:11:44.714431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass
33726 10:11:44.749826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
33727 10:11:44.750242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass
33729 10:11:44.783372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
33730 10:11:44.783810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
33732 10:11:44.817591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass>
33733 10:11:44.817923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass
33735 10:11:44.850933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
33736 10:11:44.851300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass
33738 10:11:44.884131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
33740 10:11:44.884841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
33741 10:11:44.923999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass
33743 10:11:44.924636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass>
33744 10:11:44.958432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
33745 10:11:44.958906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass
33747 10:11:44.992130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass>
33748 10:11:44.992597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass
33750 10:11:45.026537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
33751 10:11:45.026954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
33753 10:11:45.061345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass
33755 10:11:45.061817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass>
33756 10:11:45.098432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
33757 10:11:45.098843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass
33759 10:11:45.134009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
33760 10:11:45.134419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
33762 10:11:45.168083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass>
33763 10:11:45.168496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass
33765 10:11:45.202580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass
33767 10:11:45.203033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
33768 10:11:45.238720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
33770 10:11:45.239480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
33771 10:11:45.275246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass>
33772 10:11:45.275814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass
33774 10:11:45.311267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
33775 10:11:45.311693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass
33777 10:11:45.348227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
33779 10:11:45.348683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
33780 10:11:45.385399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass
33782 10:11:45.385764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass>
33783 10:11:45.422515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
33784 10:11:45.422793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass
33786 10:11:45.470040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
33787 10:11:45.470318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
33789 10:11:45.507804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass>
33790 10:11:45.508080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass
33792 10:11:45.545090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
33793 10:11:45.545513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass
33795 10:11:45.582226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass>
33796 10:11:45.582606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass
33798 10:11:45.618636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
33799 10:11:45.618986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
33801 10:11:45.655549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass
33803 10:11:45.655987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass>
33804 10:11:45.692575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
33805 10:11:45.692851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass
33807 10:11:45.729080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
33808 10:11:45.729460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
33810 10:11:45.765005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass>
33811 10:11:45.765388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass
33813 10:11:45.801315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass
33815 10:11:45.801835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
33816 10:11:45.838429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
33817 10:11:45.838779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
33819 10:11:45.874853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass>
33820 10:11:45.875137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass
33822 10:11:45.914860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
33823 10:11:45.915211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass
33825 10:11:45.955343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
33826 10:11:45.955682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
33828 10:11:45.991165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass>
33829 10:11:45.991512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass
33831 10:11:46.035998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
33832 10:11:46.036344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass
33834 10:11:46.071464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
33835 10:11:46.071746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
33837 10:11:46.107406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass>
33838 10:11:46.107683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass
33840 10:11:46.143682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
33841 10:11:46.144028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass
33843 10:11:46.180313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
33844 10:11:46.180658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
33846 10:11:46.216745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass>
33847 10:11:46.217215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass
33849 10:11:46.254188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33850 10:11:46.254538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33852 10:11:46.290647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33853 10:11:46.290928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass
33855 10:11:46.326546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33856 10:11:46.326828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33858 10:11:46.362946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33859 10:11:46.363225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33861 10:11:46.399253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33862 10:11:46.399531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass
33864 10:11:46.436674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33865 10:11:46.436958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33867 10:11:46.474343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33868 10:11:46.474693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33870 10:11:46.510272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass
33872 10:11:46.510740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33873 10:11:46.546873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33874 10:11:46.547237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33876 10:11:46.584576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33877 10:11:46.584858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33879 10:11:46.624341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33880 10:11:46.624622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass
33882 10:11:46.663868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33883 10:11:46.664234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33885 10:11:46.703047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33886 10:11:46.703409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33888 10:11:46.741421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass
33890 10:11:46.741956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33891 10:11:46.780712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33892 10:11:46.781060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33894 10:11:46.820447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass>
33895 10:11:46.820726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass
33897 10:11:46.868521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33898 10:11:46.868799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33900 10:11:46.907742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33901 10:11:46.908054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass
33903 10:11:46.948749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33904 10:11:46.949027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33906 10:11:47.002122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33908 10:11:47.002408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33909 10:11:47.048744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33910 10:11:47.049099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass
33912 10:11:47.087151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33913 10:11:47.087518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33915 10:11:47.128073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33917 10:11:47.128525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33918 10:11:47.167178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33919 10:11:47.167631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass
33921 10:11:47.205983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33923 10:11:47.206452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33924 10:11:47.245612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33926 10:11:47.246086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33927 10:11:47.284913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33928 10:11:47.285324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass
33930 10:11:47.320347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33931 10:11:47.320755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33933 10:11:47.371285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33934 10:11:47.371849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33936 10:11:47.426635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33937 10:11:47.427082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass
33939 10:11:47.482910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33940 10:11:47.483309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33942 10:11:47.524397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass
33944 10:11:47.524862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass>
33945 10:11:47.561856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33946 10:11:47.562272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33948 10:11:47.598501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass
33950 10:11:47.598985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33951 10:11:47.637992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33952 10:11:47.638416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33954 10:11:47.685575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33956 10:11:47.686014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33957 10:11:47.740869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33958 10:11:47.741415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass
33960 10:11:47.791171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33962 10:11:47.791632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33963 10:11:47.827268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33964 10:11:47.827708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33966 10:11:47.864089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass
33968 10:11:47.864549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33969 10:11:47.900189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33971 10:11:47.900649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33972 10:11:47.938046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33973 10:11:47.938474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33975 10:11:47.974993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass
33977 10:11:47.975648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33978 10:11:48.011591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33979 10:11:48.011957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33981 10:11:48.048412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33982 10:11:48.048823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33984 10:11:48.084094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33985 10:11:48.084550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass
33987 10:11:48.119712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33988 10:11:48.120140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33990 10:11:48.154967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass>
33991 10:11:48.155389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass
33993 10:11:48.190662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33994 10:11:48.191084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33996 10:11:48.226589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33997 10:11:48.227009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass
33999 10:11:48.262506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass
34001 10:11:48.262972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
34002 10:11:48.298047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
34004 10:11:48.298513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
34005 10:11:48.333805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass>
34006 10:11:48.334225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass
34008 10:11:48.372264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass
34010 10:11:48.372721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
34011 10:11:48.410379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
34012 10:11:48.410800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
34014 10:11:48.448899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass
34016 10:11:48.449374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass>
34017 10:11:48.485370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass
34019 10:11:48.485847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
34020 10:11:48.521362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
34022 10:11:48.521849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
34023 10:11:48.557086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass>
34024 10:11:48.557509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass
34026 10:11:48.593601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass
34028 10:11:48.594074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
34029 10:11:48.631863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
34030 10:11:48.632284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
34032 10:11:48.668197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass
34034 10:11:48.668656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass>
34035 10:11:48.704881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
34036 10:11:48.705333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass
34038 10:11:48.755163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass
34040 10:11:48.755815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass>
34041 10:11:48.806312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
34043 10:11:48.806767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
34044 10:11:48.850820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass>
34045 10:11:48.851301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass
34047 10:11:48.890963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
34048 10:11:48.891393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass
34050 10:11:48.931034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
34051 10:11:48.931429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
34053 10:11:48.971569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass>
34054 10:11:48.972033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass
34056 10:11:49.024093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
34057 10:11:49.024526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass
34059 10:11:49.068336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
34061 10:11:49.068797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
34062 10:11:49.112392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass
34064 10:11:49.112853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass>
34065 10:11:49.156191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
34066 10:11:49.156580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass
34068 10:11:49.210902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
34070 10:11:49.211380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
34071 10:11:49.256524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass
34073 10:11:49.257092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass>
34074 10:11:49.349318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass
34076 10:11:49.349817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
34077 10:11:49.410801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
34078 10:11:49.411230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
34080 10:11:49.467940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass>
34081 10:11:49.468389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass
34083 10:11:49.525451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass
34085 10:11:49.525941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
34086 10:11:49.583622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass>
34087 10:11:49.584045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass
34089 10:11:49.631016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
34091 10:11:49.631481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
34092 10:11:49.670367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass>
34093 10:11:49.670817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass
34095 10:11:49.707872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass
34097 10:11:49.708343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
34098 10:11:49.745125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
34099 10:11:49.745553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
34101 10:11:49.784080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass>
34102 10:11:49.784509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass
34104 10:11:49.834766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
34105 10:11:49.835201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass
34107 10:11:49.874247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
34108 10:11:49.874701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
34110 10:11:49.911785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass>
34111 10:11:49.912216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass
34113 10:11:49.972083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass
34115 10:11:49.972559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
34116 10:11:50.023630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
34117 10:11:50.024085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
34119 10:11:50.072827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass
34121 10:11:50.073505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass>
34122 10:11:50.113375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass
34124 10:11:50.113962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
34125 10:11:50.163056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
34126 10:11:50.163483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
34128 10:11:50.206759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass>
34129 10:11:50.207182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass
34131 10:11:50.245222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass
34133 10:11:50.245842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
34134 10:11:50.289913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass>
34135 10:11:50.290328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass
34137 10:11:50.325541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
34139 10:11:50.326026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
34140 10:11:50.367021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass>
34141 10:11:50.367533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass
34143 10:11:50.412979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
34144 10:11:50.413380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass
34146 10:11:50.468269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
34147 10:11:50.468679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
34149 10:11:50.520447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass>
34150 10:11:50.520841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass
34152 10:11:50.565501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass
34154 10:11:50.565978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
34155 10:11:50.599037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
34157 10:11:50.599525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
34158 10:11:50.651437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass>
34159 10:11:50.651933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass
34161 10:11:50.689127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass
34163 10:11:50.689604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
34164 10:11:50.726080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
34165 10:11:50.726502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
34167 10:11:50.762542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass>
34168 10:11:50.762967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass
34170 10:11:50.797062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
34171 10:11:50.797490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass
34173 10:11:50.852438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
34174 10:11:50.852872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
34176 10:11:50.905076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass>
34177 10:11:50.905503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass
34179 10:11:50.943239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
34180 10:11:50.943674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass
34182 10:11:50.978195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass
34184 10:11:50.978668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass>
34185 10:11:51.013202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
34187 10:11:51.013695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
34188 10:11:51.049015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass
34190 10:11:51.049378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass>
34191 10:11:51.090526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
34192 10:11:51.090991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass
34194 10:11:51.132278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
34195 10:11:51.132931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
34197 10:11:51.186658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass>
34198 10:11:51.187117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass
34200 10:11:51.236579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass
34202 10:11:51.237114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
34203 10:11:51.278750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
34205 10:11:51.279218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
34206 10:11:51.314871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass>
34207 10:11:51.315323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass
34209 10:11:51.352094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
34210 10:11:51.352543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass
34212 10:11:51.389215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
34214 10:11:51.389732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
34215 10:11:51.438817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass>
34216 10:11:51.439282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass
34218 10:11:51.475138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
34219 10:11:51.475593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass
34221 10:11:51.511025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
34222 10:11:51.511468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
34224 10:11:51.546268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass
34226 10:11:51.546753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass>
34227 10:11:51.581135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass
34229 10:11:51.581608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
34230 10:11:51.615962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass
34232 10:11:51.616393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass>
34233 10:11:51.651809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
34235 10:11:51.652282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
34236 10:11:51.687163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass>
34237 10:11:51.687601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass
34239 10:11:51.723754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
34240 10:11:51.724181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass
34242 10:11:51.761792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
34243 10:11:51.762231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
34245 10:11:51.798836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass
34247 10:11:51.799318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass>
34248 10:11:51.844547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass
34250 10:11:51.845024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
34251 10:11:51.898448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
34252 10:11:51.898886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
34254 10:11:51.952464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass>
34255 10:11:51.952924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass
34257 10:11:52.002278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass
34259 10:11:52.002757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
34260 10:11:52.042440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
34261 10:11:52.042870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
34263 10:11:52.084254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass>
34264 10:11:52.084680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass
34266 10:11:52.126077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
34267 10:11:52.126534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass
34269 10:11:52.166125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
34270 10:11:52.166586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
34272 10:11:52.215686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass>
34273 10:11:52.216111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass
34275 10:11:52.252735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
34276 10:11:52.253103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass
34278 10:11:52.290056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass
34280 10:11:52.290518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass>
34281 10:11:52.324814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
34282 10:11:52.325232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
34284 10:11:52.358909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass
34286 10:11:52.359360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass>
34287 10:11:52.394477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
34288 10:11:52.394964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass
34290 10:11:52.428689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
34292 10:11:52.429269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
34293 10:11:52.462290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass>
34294 10:11:52.462711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass
34296 10:11:52.496145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
34297 10:11:52.496572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass
34299 10:11:52.530589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
34300 10:11:52.530999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
34302 10:11:52.564545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass
34304 10:11:52.565068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass>
34305 10:11:52.599511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass
34307 10:11:52.599991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
34308 10:11:52.634445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
34309 10:11:52.634903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
34311 10:11:52.670216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass>
34312 10:11:52.670675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass
34314 10:11:52.704000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass
34316 10:11:52.704571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
34317 10:11:52.738071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
34318 10:11:52.738514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
34320 10:11:52.770783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass>
34321 10:11:52.771210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass
34323 10:11:52.803352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
34324 10:11:52.803754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass
34326 10:11:52.834738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass>
34327 10:11:52.835145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass
34329 10:11:52.866448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
34331 10:11:52.866871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
34332 10:11:52.898181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass>
34333 10:11:52.898580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass
34335 10:11:52.932244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
34336 10:11:52.932625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass
34338 10:11:52.967204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
34340 10:11:52.967637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
34341 10:11:53.000752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass
34343 10:11:53.001211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass>
34344 10:11:53.034897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
34345 10:11:53.035320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass
34347 10:11:53.067712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
34349 10:11:53.068148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
34350 10:11:53.100747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass>
34351 10:11:53.101148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass
34353 10:11:53.134368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass
34355 10:11:53.134798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
34356 10:11:53.166891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
34357 10:11:53.167317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
34359 10:11:53.201633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass>
34360 10:11:53.202065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass
34362 10:11:53.233980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
34363 10:11:53.234376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass
34365 10:11:53.266377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
34367 10:11:53.267022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
34368 10:11:53.299970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass>
34369 10:11:53.300447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass
34371 10:11:53.333517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass
34373 10:11:53.334160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
34374 10:11:53.368120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass
34376 10:11:53.368580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass>
34377 10:11:53.404290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
34378 10:11:53.404734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
34380 10:11:53.444715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass
34382 10:11:53.445222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass>
34383 10:11:53.494952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass
34385 10:11:53.495408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
34386 10:11:53.539507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
34388 10:11:53.539990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
34389 10:11:53.590693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass
34391 10:11:53.591153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass>
34392 10:11:53.645662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass
34394 10:11:53.646124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
34395 10:11:53.700468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
34396 10:11:53.700904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
34398 10:11:53.738307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass
34400 10:11:53.738760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass>
34401 10:11:53.788389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
34402 10:11:53.788814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass
34404 10:11:53.831234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
34405 10:11:53.831687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
34407 10:11:53.871931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass
34409 10:11:53.872404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass>
34410 10:11:53.923239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
34411 10:11:53.923698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass
34413 10:11:53.970263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
34414 10:11:53.970644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
34416 10:11:54.009980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass
34418 10:11:54.010649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass>
34419 10:11:54.048482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
34420 10:11:54.048925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass
34422 10:11:54.084904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass
34424 10:11:54.085353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass>
34425 10:11:54.139757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
34426 10:11:54.140111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
34428 10:11:54.192790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass>
34429 10:11:54.193355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass
34431 10:11:54.245052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
34432 10:11:54.245689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass
34434 10:11:54.284233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
34435 10:11:54.284641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
34437 10:11:54.325473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass
34439 10:11:54.325872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass>
34440 10:11:54.365933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass
34442 10:11:54.366405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
34443 10:11:54.415704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
34444 10:11:54.416159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
34446 10:11:54.490444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass
34448 10:11:54.491198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass>
34449 10:11:54.546346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
34450 10:11:54.546808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass
34452 10:11:54.601682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
34454 10:11:54.602385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
34455 10:11:54.650584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass
34457 10:11:54.651063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass>
34458 10:11:54.699152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass
34460 10:11:54.699627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
34461 10:11:54.741509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
34463 10:11:54.742044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
34464 10:11:54.784869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass>
34465 10:11:54.785305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass
34467 10:11:54.839613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
34468 10:11:54.840046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass
34470 10:11:54.893142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass>
34471 10:11:54.893599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass
34473 10:11:54.936792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
34475 10:11:54.937272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
34476 10:11:54.981061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass>
34477 10:11:54.981479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass
34479 10:11:55.026290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
34480 10:11:55.026721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass
34482 10:11:55.068792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
34483 10:11:55.069220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
34485 10:11:55.107226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass
34487 10:11:55.107711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass>
34488 10:11:55.145517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass
34490 10:11:55.145982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
34491 10:11:55.195661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
34492 10:11:55.196109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
34494 10:11:55.236963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass>
34495 10:11:55.237421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass
34497 10:11:55.280584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass
34499 10:11:55.281060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
34500 10:11:55.322602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
34501 10:11:55.323029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
34503 10:11:55.370419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass>
34504 10:11:55.370844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass
34506 10:11:55.412684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
34507 10:11:55.413117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass
34509 10:11:55.463141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
34510 10:11:55.463587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
34512 10:11:55.510798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass
34514 10:11:55.511266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass>
34515 10:11:55.550857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
34516 10:11:55.551289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass
34518 10:11:55.590393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass>
34519 10:11:55.590848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass
34521 10:11:55.633364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
34523 10:11:55.633811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
34524 10:11:55.683924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass>
34525 10:11:55.684351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass
34527 10:11:55.728503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
34528 10:11:55.728921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass
34530 10:11:55.770676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
34531 10:11:55.771166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
34533 10:11:55.807395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass>
34534 10:11:55.807887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass
34536 10:11:55.847330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
34537 10:11:55.847764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass
34539 10:11:55.903847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
34540 10:11:55.904282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
34542 10:11:55.964599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass>
34543 10:11:55.965041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass
34545 10:11:56.024678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
34546 10:11:56.025109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass
34548 10:11:56.084135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
34549 10:11:56.084568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
34551 10:11:56.124809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass
34553 10:11:56.125499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass>
34554 10:11:56.166802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass
34556 10:11:56.167534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
34557 10:11:56.209030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
34558 10:11:56.209519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
34560 10:11:56.248682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass>
34561 10:11:56.249183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass
34563 10:11:56.288183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
34564 10:11:56.288757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass
34566 10:11:56.331846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass>
34567 10:11:56.332292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass
34569 10:11:56.376737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
34570 10:11:56.377181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
34572 10:11:56.420500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass>
34573 10:11:56.420934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass
34575 10:11:56.460554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass
34577 10:11:56.461026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
34578 10:11:56.500171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
34580 10:11:56.500846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
34581 10:11:56.540584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass
34583 10:11:56.541258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass>
34584 10:11:56.587073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
34585 10:11:56.587500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass
34587 10:11:56.632011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
34588 10:11:56.632462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
34590 10:11:56.673776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass>
34591 10:11:56.674236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass
34593 10:11:56.716268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass
34595 10:11:56.716753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
34596 10:11:56.756609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
34597 10:11:56.757105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
34599 10:11:56.797182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass
34601 10:11:56.797965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass>
34602 10:11:56.839480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
34603 10:11:56.839882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass
34605 10:11:56.894423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
34607 10:11:56.895073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
34608 10:11:56.952200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass>
34609 10:11:56.952615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass
34611 10:11:57.012784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
34612 10:11:57.013361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass
34614 10:11:57.053739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
34615 10:11:57.054191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
34617 10:11:57.105316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass
34619 10:11:57.109763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass>
34620 10:11:57.166041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass>
34621 10:11:57.166474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass
34623 10:11:57.225899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass>
34624 10:11:57.226354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass
34626 10:11:57.282788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass>
34627 10:11:57.283184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass
34629 10:11:57.327792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass
34631 10:11:57.328238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass>
34632 10:11:57.386094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
34633 10:11:57.386542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
34635 10:11:57.390759 + set +x
34636 10:11:57.391001 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64_qemu 592431_1.1.3.5>
34637 10:11:57.391339 Received signal: <ENDRUN> 1_kselftest-arm64_qemu 592431_1.1.3.5
34638 10:11:57.391511 Ending use of test pattern.
34639 10:11:57.391679 Ending test lava.1_kselftest-arm64_qemu (592431_1.1.3.5), duration 328.45
34641 10:11:57.396967 <LAVA_TEST_RUNNER EXIT>
34642 10:11:57.397414 ok: lava_test_shell seems to have completed
34643 10:11:57.475542 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: pass
arm64_btitest_bti_c_func_call_using_br_x0: pass
arm64_btitest_bti_c_func_call_using_br_x16: pass
arm64_btitest_bti_j_func_call_using_blr: pass
arm64_btitest_bti_j_func_call_using_br_x0: pass
arm64_btitest_bti_j_func_call_using_br_x16: pass
arm64_btitest_bti_jc_func_call_using_blr: pass
arm64_btitest_bti_jc_func_call_using_br_x0: pass
arm64_btitest_bti_jc_func_call_using_br_x16: pass
arm64_btitest_bti_none_func_call_using_blr: pass
arm64_btitest_bti_none_func_call_using_br_x0: pass
arm64_btitest_bti_none_func_call_using_br_x16: pass
arm64_btitest_nohint_func_call_using_blr: pass
arm64_btitest_nohint_func_call_using_br_x0: pass
arm64_btitest_nohint_func_call_using_br_x16: pass
arm64_btitest_paciasp_func_call_using_blr: pass
arm64_btitest_paciasp_func_call_using_br_x0: pass
arm64_btitest_paciasp_func_call_using_br_x16: pass
arm64_check_buffer_fill: fail
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_child_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_gcr_el1_cswitch: fail
arm64_check_ksm_options: fail
arm64_check_mmap_options: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: pass
arm64_check_prctl_SYNC_ASYNC: pass
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: fail
arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode: pass
arm64_check_user_mem: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: pass
arm64_fake_sigreturn_sve_change_vl: pass
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_SSVE-VL-128-0: pass
arm64_fp-stress_SSVE-VL-16-0: pass
arm64_fp-stress_SSVE-VL-256-0: pass
arm64_fp-stress_SSVE-VL-32-0: pass
arm64_fp-stress_SSVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-112-0: pass
arm64_fp-stress_SVE-VL-128-0: pass
arm64_fp-stress_SVE-VL-144-0: pass
arm64_fp-stress_SVE-VL-16-0: pass
arm64_fp-stress_SVE-VL-160-0: pass
arm64_fp-stress_SVE-VL-176-0: pass
arm64_fp-stress_SVE-VL-192-0: pass
arm64_fp-stress_SVE-VL-208-0: pass
arm64_fp-stress_SVE-VL-224-0: pass
arm64_fp-stress_SVE-VL-240-0: pass
arm64_fp-stress_SVE-VL-256-0: pass
arm64_fp-stress_SVE-VL-32-0: pass
arm64_fp-stress_SVE-VL-48-0: pass
arm64_fp-stress_SVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-80-0: pass
arm64_fp-stress_SVE-VL-96-0: pass
arm64_fp-stress_ZA-VL-128-0: pass
arm64_fp-stress_ZA-VL-16-0: pass
arm64_fp-stress_ZA-VL-256-0: pass
arm64_fp-stress_ZA-VL-32-0: pass
arm64_fp-stress_ZA-VL-64-0: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SM4: pass
arm64_hwcap_sigill_SVE_2: pass
arm64_hwcap_sigill_SVE_AES: pass
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: pass
arm64_nobtitest_bti_c_func_call_using_br_x0: pass
arm64_nobtitest_bti_c_func_call_using_br_x16: pass
arm64_nobtitest_bti_j_func_call_using_blr: pass
arm64_nobtitest_bti_j_func_call_using_br_x0: pass
arm64_nobtitest_bti_j_func_call_using_br_x16: pass
arm64_nobtitest_bti_jc_func_call_using_blr: pass
arm64_nobtitest_bti_jc_func_call_using_br_x0: pass
arm64_nobtitest_bti_jc_func_call_using_br_x16: pass
arm64_nobtitest_bti_none_func_call_using_blr: pass
arm64_nobtitest_bti_none_func_call_using_br_x0: pass
arm64_nobtitest_bti_none_func_call_using_br_x16: pass
arm64_nobtitest_nohint_func_call_using_blr: pass
arm64_nobtitest_nohint_func_call_using_br_x0: pass
arm64_nobtitest_nohint_func_call_using_br_x16: pass
arm64_nobtitest_paciasp_func_call_using_blr: pass
arm64_nobtitest_paciasp_func_call_using_br_x0: pass
arm64_nobtitest_paciasp_func_call_using_br_x16: pass
arm64_pac: pass
arm64_pac_global_context_switch_keep_keys: pass
arm64_pac_global_context_switch_keep_keys_generic: pass
arm64_pac_global_corrupt_pac: pass
arm64_pac_global_exec_changed_keys: pass
arm64_pac_global_pac_instructions_not_nop: pass
arm64_pac_global_pac_instructions_not_nop_generic: pass
arm64_pac_global_single_thread_different_keys: pass
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: pass
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: pass
arm64_ssve_regs: pass
arm64_sve-probe-vls: pass
arm64_sve-probe-vls_All_vector_lengths_valid: pass
arm64_sve-probe-vls_Enumerated_16_vector_lengths: pass
arm64_sve-ptrace: pass
arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_1008: pass
arm64_sve-ptrace_Set_SVE_VL_1024: pass
arm64_sve-ptrace_Set_SVE_VL_1040: pass
arm64_sve-ptrace_Set_SVE_VL_1056: pass
arm64_sve-ptrace_Set_SVE_VL_1072: pass
arm64_sve-ptrace_Set_SVE_VL_1088: pass
arm64_sve-ptrace_Set_SVE_VL_1104: pass
arm64_sve-ptrace_Set_SVE_VL_112: pass
arm64_sve-ptrace_Set_SVE_VL_1120: pass
arm64_sve-ptrace_Set_SVE_VL_1136: pass
arm64_sve-ptrace_Set_SVE_VL_1152: pass
arm64_sve-ptrace_Set_SVE_VL_1168: pass
arm64_sve-ptrace_Set_SVE_VL_1184: pass
arm64_sve-ptrace_Set_SVE_VL_1200: pass
arm64_sve-ptrace_Set_SVE_VL_1216: pass
arm64_sve-ptrace_Set_SVE_VL_1232: pass
arm64_sve-ptrace_Set_SVE_VL_1248: pass
arm64_sve-ptrace_Set_SVE_VL_1264: pass
arm64_sve-ptrace_Set_SVE_VL_128: pass
arm64_sve-ptrace_Set_SVE_VL_1280: pass
arm64_sve-ptrace_Set_SVE_VL_1296: pass
arm64_sve-ptrace_Set_SVE_VL_1312: pass
arm64_sve-ptrace_Set_SVE_VL_1328: pass
arm64_sve-ptrace_Set_SVE_VL_1344: pass
arm64_sve-ptrace_Set_SVE_VL_1360: pass
arm64_sve-ptrace_Set_SVE_VL_1376: pass
arm64_sve-ptrace_Set_SVE_VL_1392: pass
arm64_sve-ptrace_Set_SVE_VL_1408: pass
arm64_sve-ptrace_Set_SVE_VL_1424: pass
arm64_sve-ptrace_Set_SVE_VL_144: pass
arm64_sve-ptrace_Set_SVE_VL_1440: pass
arm64_sve-ptrace_Set_SVE_VL_1456: pass
arm64_sve-ptrace_Set_SVE_VL_1472: pass
arm64_sve-ptrace_Set_SVE_VL_1488: pass
arm64_sve-ptrace_Set_SVE_VL_1504: pass
arm64_sve-ptrace_Set_SVE_VL_1520: pass
arm64_sve-ptrace_Set_SVE_VL_1536: pass
arm64_sve-ptrace_Set_SVE_VL_1552: pass
arm64_sve-ptrace_Set_SVE_VL_1568: pass
arm64_sve-ptrace_Set_SVE_VL_1584: pass
arm64_sve-ptrace_Set_SVE_VL_16: pass
arm64_sve-ptrace_Set_SVE_VL_160: pass
arm64_sve-ptrace_Set_SVE_VL_1600: pass
arm64_sve-ptrace_Set_SVE_VL_1616: pass
arm64_sve-ptrace_Set_SVE_VL_1632: pass
arm64_sve-ptrace_Set_SVE_VL_1648: pass
arm64_sve-ptrace_Set_SVE_VL_1664: pass
arm64_sve-ptrace_Set_SVE_VL_1680: pass
arm64_sve-ptrace_Set_SVE_VL_1696: pass
arm64_sve-ptrace_Set_SVE_VL_1712: pass
arm64_sve-ptrace_Set_SVE_VL_1728: pass
arm64_sve-ptrace_Set_SVE_VL_1744: pass
arm64_sve-ptrace_Set_SVE_VL_176: pass
arm64_sve-ptrace_Set_SVE_VL_1760: pass
arm64_sve-ptrace_Set_SVE_VL_1776: pass
arm64_sve-ptrace_Set_SVE_VL_1792: pass
arm64_sve-ptrace_Set_SVE_VL_1808: pass
arm64_sve-ptrace_Set_SVE_VL_1824: pass
arm64_sve-ptrace_Set_SVE_VL_1840: pass
arm64_sve-ptrace_Set_SVE_VL_1856: pass
arm64_sve-ptrace_Set_SVE_VL_1872: pass
arm64_sve-ptrace_Set_SVE_VL_1888: pass
arm64_sve-ptrace_Set_SVE_VL_1904: pass
arm64_sve-ptrace_Set_SVE_VL_192: pass
arm64_sve-ptrace_Set_SVE_VL_1920: pass
arm64_sve-ptrace_Set_SVE_VL_1936: pass
arm64_sve-ptrace_Set_SVE_VL_1952: pass
arm64_sve-ptrace_Set_SVE_VL_1968: pass
arm64_sve-ptrace_Set_SVE_VL_1984: pass
arm64_sve-ptrace_Set_SVE_VL_2000: pass
arm64_sve-ptrace_Set_SVE_VL_2016: pass
arm64_sve-ptrace_Set_SVE_VL_2032: pass
arm64_sve-ptrace_Set_SVE_VL_2048: pass
arm64_sve-ptrace_Set_SVE_VL_2064: pass
arm64_sve-ptrace_Set_SVE_VL_208: pass
arm64_sve-ptrace_Set_SVE_VL_2080: pass
arm64_sve-ptrace_Set_SVE_VL_2096: pass
arm64_sve-ptrace_Set_SVE_VL_2112: pass
arm64_sve-ptrace_Set_SVE_VL_2128: pass
arm64_sve-ptrace_Set_SVE_VL_2144: pass
arm64_sve-ptrace_Set_SVE_VL_2160: pass
arm64_sve-ptrace_Set_SVE_VL_2176: pass
arm64_sve-ptrace_Set_SVE_VL_2192: pass
arm64_sve-ptrace_Set_SVE_VL_2208: pass
arm64_sve-ptrace_Set_SVE_VL_2224: pass
arm64_sve-ptrace_Set_SVE_VL_224: pass
arm64_sve-ptrace_Set_SVE_VL_2240: pass
arm64_sve-ptrace_Set_SVE_VL_2256: pass
arm64_sve-ptrace_Set_SVE_VL_2272: pass
arm64_sve-ptrace_Set_SVE_VL_2288: pass
arm64_sve-ptrace_Set_SVE_VL_2304: pass
arm64_sve-ptrace_Set_SVE_VL_2320: pass
arm64_sve-ptrace_Set_SVE_VL_2336: pass
arm64_sve-ptrace_Set_SVE_VL_2352: pass
arm64_sve-ptrace_Set_SVE_VL_2368: pass
arm64_sve-ptrace_Set_SVE_VL_2384: pass
arm64_sve-ptrace_Set_SVE_VL_240: pass
arm64_sve-ptrace_Set_SVE_VL_2400: pass
arm64_sve-ptrace_Set_SVE_VL_2416: pass
arm64_sve-ptrace_Set_SVE_VL_2432: pass
arm64_sve-ptrace_Set_SVE_VL_2448: pass
arm64_sve-ptrace_Set_SVE_VL_2464: pass
arm64_sve-ptrace_Set_SVE_VL_2480: pass
arm64_sve-ptrace_Set_SVE_VL_2496: pass
arm64_sve-ptrace_Set_SVE_VL_2512: pass
arm64_sve-ptrace_Set_SVE_VL_2528: pass
arm64_sve-ptrace_Set_SVE_VL_2544: pass
arm64_sve-ptrace_Set_SVE_VL_256: pass
arm64_sve-ptrace_Set_SVE_VL_2560: pass
arm64_sve-ptrace_Set_SVE_VL_2576: pass
arm64_sve-ptrace_Set_SVE_VL_2592: pass
arm64_sve-ptrace_Set_SVE_VL_2608: pass
arm64_sve-ptrace_Set_SVE_VL_2624: pass
arm64_sve-ptrace_Set_SVE_VL_2640: pass
arm64_sve-ptrace_Set_SVE_VL_2656: pass
arm64_sve-ptrace_Set_SVE_VL_2672: pass
arm64_sve-ptrace_Set_SVE_VL_2688: pass
arm64_sve-ptrace_Set_SVE_VL_2704: pass
arm64_sve-ptrace_Set_SVE_VL_272: pass
arm64_sve-ptrace_Set_SVE_VL_2720: pass
arm64_sve-ptrace_Set_SVE_VL_2736: pass
arm64_sve-ptrace_Set_SVE_VL_2752: pass
arm64_sve-ptrace_Set_SVE_VL_2768: pass
arm64_sve-ptrace_Set_SVE_VL_2784: pass
arm64_sve-ptrace_Set_SVE_VL_2800: pass
arm64_sve-ptrace_Set_SVE_VL_2816: pass
arm64_sve-ptrace_Set_SVE_VL_2832: pass
arm64_sve-ptrace_Set_SVE_VL_2848: pass
arm64_sve-ptrace_Set_SVE_VL_2864: pass
arm64_sve-ptrace_Set_SVE_VL_288: pass
arm64_sve-ptrace_Set_SVE_VL_2880: pass
arm64_sve-ptrace_Set_SVE_VL_2896: pass
arm64_sve-ptrace_Set_SVE_VL_2912: pass
arm64_sve-ptrace_Set_SVE_VL_2928: pass
arm64_sve-ptrace_Set_SVE_VL_2944: pass
arm64_sve-ptrace_Set_SVE_VL_2960: pass
arm64_sve-ptrace_Set_SVE_VL_2976: pass
arm64_sve-ptrace_Set_SVE_VL_2992: pass
arm64_sve-ptrace_Set_SVE_VL_3008: pass
arm64_sve-ptrace_Set_SVE_VL_3024: pass
arm64_sve-ptrace_Set_SVE_VL_304: pass
arm64_sve-ptrace_Set_SVE_VL_3040: pass
arm64_sve-ptrace_Set_SVE_VL_3056: pass
arm64_sve-ptrace_Set_SVE_VL_3072: pass
arm64_sve-ptrace_Set_SVE_VL_3088: pass
arm64_sve-ptrace_Set_SVE_VL_3104: pass
arm64_sve-ptrace_Set_SVE_VL_3120: pass
arm64_sve-ptrace_Set_SVE_VL_3136: pass
arm64_sve-ptrace_Set_SVE_VL_3152: pass
arm64_sve-ptrace_Set_SVE_VL_3168: pass
arm64_sve-ptrace_Set_SVE_VL_3184: pass
arm64_sve-ptrace_Set_SVE_VL_32: pass
arm64_sve-ptrace_Set_SVE_VL_320: pass
arm64_sve-ptrace_Set_SVE_VL_3200: pass
arm64_sve-ptrace_Set_SVE_VL_3216: pass
arm64_sve-ptrace_Set_SVE_VL_3232: pass
arm64_sve-ptrace_Set_SVE_VL_3248: pass
arm64_sve-ptrace_Set_SVE_VL_3264: pass
arm64_sve-ptrace_Set_SVE_VL_3280: pass
arm64_sve-ptrace_Set_SVE_VL_3296: pass
arm64_sve-ptrace_Set_SVE_VL_3312: pass
arm64_sve-ptrace_Set_SVE_VL_3328: pass
arm64_sve-ptrace_Set_SVE_VL_3344: pass
arm64_sve-ptrace_Set_SVE_VL_336: pass
arm64_sve-ptrace_Set_SVE_VL_3360: pass
arm64_sve-ptrace_Set_SVE_VL_3376: pass
arm64_sve-ptrace_Set_SVE_VL_3392: pass
arm64_sve-ptrace_Set_SVE_VL_3408: pass
arm64_sve-ptrace_Set_SVE_VL_3424: pass
arm64_sve-ptrace_Set_SVE_VL_3440: pass
arm64_sve-ptrace_Set_SVE_VL_3456: pass
arm64_sve-ptrace_Set_SVE_VL_3472: pass
arm64_sve-ptrace_Set_SVE_VL_3488: pass
arm64_sve-ptrace_Set_SVE_VL_3504: pass
arm64_sve-ptrace_Set_SVE_VL_352: pass
arm64_sve-ptrace_Set_SVE_VL_3520: pass
arm64_sve-ptrace_Set_SVE_VL_3536: pass
arm64_sve-ptrace_Set_SVE_VL_3552: pass
arm64_sve-ptrace_Set_SVE_VL_3568: pass
arm64_sve-ptrace_Set_SVE_VL_3584: pass
arm64_sve-ptrace_Set_SVE_VL_3600: pass
arm64_sve-ptrace_Set_SVE_VL_3616: pass
arm64_sve-ptrace_Set_SVE_VL_3632: pass
arm64_sve-ptrace_Set_SVE_VL_3648: pass
arm64_sve-ptrace_Set_SVE_VL_3664: pass
arm64_sve-ptrace_Set_SVE_VL_368: pass
arm64_sve-ptrace_Set_SVE_VL_3680: pass
arm64_sve-ptrace_Set_SVE_VL_3696: pass
arm64_sve-ptrace_Set_SVE_VL_3712: pass
arm64_sve-ptrace_Set_SVE_VL_3728: pass
arm64_sve-ptrace_Set_SVE_VL_3744: pass
arm64_sve-ptrace_Set_SVE_VL_3760: pass
arm64_sve-ptrace_Set_SVE_VL_3776: pass
arm64_sve-ptrace_Set_SVE_VL_3792: pass
arm64_sve-ptrace_Set_SVE_VL_3808: pass
arm64_sve-ptrace_Set_SVE_VL_3824: pass
arm64_sve-ptrace_Set_SVE_VL_384: pass
arm64_sve-ptrace_Set_SVE_VL_3840: pass
arm64_sve-ptrace_Set_SVE_VL_3856: pass
arm64_sve-ptrace_Set_SVE_VL_3872: pass
arm64_sve-ptrace_Set_SVE_VL_3888: pass
arm64_sve-ptrace_Set_SVE_VL_3904: pass
arm64_sve-ptrace_Set_SVE_VL_3920: pass
arm64_sve-ptrace_Set_SVE_VL_3936: pass
arm64_sve-ptrace_Set_SVE_VL_3952: pass
arm64_sve-ptrace_Set_SVE_VL_3968: pass
arm64_sve-ptrace_Set_SVE_VL_3984: pass
arm64_sve-ptrace_Set_SVE_VL_400: pass
arm64_sve-ptrace_Set_SVE_VL_4000: pass
arm64_sve-ptrace_Set_SVE_VL_4016: pass
arm64_sve-ptrace_Set_SVE_VL_4032: pass
arm64_sve-ptrace_Set_SVE_VL_4048: pass
arm64_sve-ptrace_Set_SVE_VL_4064: pass
arm64_sve-ptrace_Set_SVE_VL_4080: pass
arm64_sve-ptrace_Set_SVE_VL_4096: pass
arm64_sve-ptrace_Set_SVE_VL_4112: pass
arm64_sve-ptrace_Set_SVE_VL_4128: pass
arm64_sve-ptrace_Set_SVE_VL_4144: pass
arm64_sve-ptrace_Set_SVE_VL_416: pass
arm64_sve-ptrace_Set_SVE_VL_4160: pass
arm64_sve-ptrace_Set_SVE_VL_4176: pass
arm64_sve-ptrace_Set_SVE_VL_4192: pass
arm64_sve-ptrace_Set_SVE_VL_4208: pass
arm64_sve-ptrace_Set_SVE_VL_4224: pass
arm64_sve-ptrace_Set_SVE_VL_4240: pass
arm64_sve-ptrace_Set_SVE_VL_4256: pass
arm64_sve-ptrace_Set_SVE_VL_4272: pass
arm64_sve-ptrace_Set_SVE_VL_4288: pass
arm64_sve-ptrace_Set_SVE_VL_4304: pass
arm64_sve-ptrace_Set_SVE_VL_432: pass
arm64_sve-ptrace_Set_SVE_VL_4320: pass
arm64_sve-ptrace_Set_SVE_VL_4336: pass
arm64_sve-ptrace_Set_SVE_VL_4352: pass
arm64_sve-ptrace_Set_SVE_VL_4368: pass
arm64_sve-ptrace_Set_SVE_VL_4384: pass
arm64_sve-ptrace_Set_SVE_VL_4400: pass
arm64_sve-ptrace_Set_SVE_VL_4416: pass
arm64_sve-ptrace_Set_SVE_VL_4432: pass
arm64_sve-ptrace_Set_SVE_VL_4448: pass
arm64_sve-ptrace_Set_SVE_VL_4464: pass
arm64_sve-ptrace_Set_SVE_VL_448: pass
arm64_sve-ptrace_Set_SVE_VL_4480: pass
arm64_sve-ptrace_Set_SVE_VL_4496: pass
arm64_sve-ptrace_Set_SVE_VL_4512: pass
arm64_sve-ptrace_Set_SVE_VL_4528: pass
arm64_sve-ptrace_Set_SVE_VL_4544: pass
arm64_sve-ptrace_Set_SVE_VL_4560: pass
arm64_sve-ptrace_Set_SVE_VL_4576: pass
arm64_sve-ptrace_Set_SVE_VL_4592: pass
arm64_sve-ptrace_Set_SVE_VL_4608: pass
arm64_sve-ptrace_Set_SVE_VL_4624: pass
arm64_sve-ptrace_Set_SVE_VL_464: pass
arm64_sve-ptrace_Set_SVE_VL_4640: pass
arm64_sve-ptrace_Set_SVE_VL_4656: pass
arm64_sve-ptrace_Set_SVE_VL_4672: pass
arm64_sve-ptrace_Set_SVE_VL_4688: pass
arm64_sve-ptrace_Set_SVE_VL_4704: pass
arm64_sve-ptrace_Set_SVE_VL_4720: pass
arm64_sve-ptrace_Set_SVE_VL_4736: pass
arm64_sve-ptrace_Set_SVE_VL_4752: pass
arm64_sve-ptrace_Set_SVE_VL_4768: pass
arm64_sve-ptrace_Set_SVE_VL_4784: pass
arm64_sve-ptrace_Set_SVE_VL_48: pass
arm64_sve-ptrace_Set_SVE_VL_480: pass
arm64_sve-ptrace_Set_SVE_VL_4800: pass
arm64_sve-ptrace_Set_SVE_VL_4816: pass
arm64_sve-ptrace_Set_SVE_VL_4832: pass
arm64_sve-ptrace_Set_SVE_VL_4848: pass
arm64_sve-ptrace_Set_SVE_VL_4864: pass
arm64_sve-ptrace_Set_SVE_VL_4880: pass
arm64_sve-ptrace_Set_SVE_VL_4896: pass
arm64_sve-ptrace_Set_SVE_VL_4912: pass
arm64_sve-ptrace_Set_SVE_VL_4928: pass
arm64_sve-ptrace_Set_SVE_VL_4944: pass
arm64_sve-ptrace_Set_SVE_VL_496: pass
arm64_sve-ptrace_Set_SVE_VL_4960: pass
arm64_sve-ptrace_Set_SVE_VL_4976: pass
arm64_sve-ptrace_Set_SVE_VL_4992: pass
arm64_sve-ptrace_Set_SVE_VL_5008: pass
arm64_sve-ptrace_Set_SVE_VL_5024: pass
arm64_sve-ptrace_Set_SVE_VL_5040: pass
arm64_sve-ptrace_Set_SVE_VL_5056: pass
arm64_sve-ptrace_Set_SVE_VL_5072: pass
arm64_sve-ptrace_Set_SVE_VL_5088: pass
arm64_sve-ptrace_Set_SVE_VL_5104: pass
arm64_sve-ptrace_Set_SVE_VL_512: pass
arm64_sve-ptrace_Set_SVE_VL_5120: pass
arm64_sve-ptrace_Set_SVE_VL_5136: pass
arm64_sve-ptrace_Set_SVE_VL_5152: pass
arm64_sve-ptrace_Set_SVE_VL_5168: pass
arm64_sve-ptrace_Set_SVE_VL_5184: pass
arm64_sve-ptrace_Set_SVE_VL_5200: pass
arm64_sve-ptrace_Set_SVE_VL_5216: pass
arm64_sve-ptrace_Set_SVE_VL_5232: pass
arm64_sve-ptrace_Set_SVE_VL_5248: pass
arm64_sve-ptrace_Set_SVE_VL_5264: pass
arm64_sve-ptrace_Set_SVE_VL_528: pass
arm64_sve-ptrace_Set_SVE_VL_5280: pass
arm64_sve-ptrace_Set_SVE_VL_5296: pass
arm64_sve-ptrace_Set_SVE_VL_5312: pass
arm64_sve-ptrace_Set_SVE_VL_5328: pass
arm64_sve-ptrace_Set_SVE_VL_5344: pass
arm64_sve-ptrace_Set_SVE_VL_5360: pass
arm64_sve-ptrace_Set_SVE_VL_5376: pass
arm64_sve-ptrace_Set_SVE_VL_5392: pass
arm64_sve-ptrace_Set_SVE_VL_5408: pass
arm64_sve-ptrace_Set_SVE_VL_5424: pass
arm64_sve-ptrace_Set_SVE_VL_544: pass
arm64_sve-ptrace_Set_SVE_VL_5440: pass
arm64_sve-ptrace_Set_SVE_VL_5456: pass
arm64_sve-ptrace_Set_SVE_VL_5472: pass
arm64_sve-ptrace_Set_SVE_VL_5488: pass
arm64_sve-ptrace_Set_SVE_VL_5504: pass
arm64_sve-ptrace_Set_SVE_VL_5520: pass
arm64_sve-ptrace_Set_SVE_VL_5536: pass
arm64_sve-ptrace_Set_SVE_VL_5552: pass
arm64_sve-ptrace_Set_SVE_VL_5568: pass
arm64_sve-ptrace_Set_SVE_VL_5584: pass
arm64_sve-ptrace_Set_SVE_VL_560: pass
arm64_sve-ptrace_Set_SVE_VL_5600: pass
arm64_sve-ptrace_Set_SVE_VL_5616: pass
arm64_sve-ptrace_Set_SVE_VL_5632: pass
arm64_sve-ptrace_Set_SVE_VL_5648: pass
arm64_sve-ptrace_Set_SVE_VL_5664: pass
arm64_sve-ptrace_Set_SVE_VL_5680: pass
arm64_sve-ptrace_Set_SVE_VL_5696: pass
arm64_sve-ptrace_Set_SVE_VL_5712: pass
arm64_sve-ptrace_Set_SVE_VL_5728: pass
arm64_sve-ptrace_Set_SVE_VL_5744: pass
arm64_sve-ptrace_Set_SVE_VL_576: pass
arm64_sve-ptrace_Set_SVE_VL_5760: pass
arm64_sve-ptrace_Set_SVE_VL_5776: pass
arm64_sve-ptrace_Set_SVE_VL_5792: pass
arm64_sve-ptrace_Set_SVE_VL_5808: pass
arm64_sve-ptrace_Set_SVE_VL_5824: pass
arm64_sve-ptrace_Set_SVE_VL_5840: pass
arm64_sve-ptrace_Set_SVE_VL_5856: pass
arm64_sve-ptrace_Set_SVE_VL_5872: pass
arm64_sve-ptrace_Set_SVE_VL_5888: pass
arm64_sve-ptrace_Set_SVE_VL_5904: pass
arm64_sve-ptrace_Set_SVE_VL_592: pass
arm64_sve-ptrace_Set_SVE_VL_5920: pass
arm64_sve-ptrace_Set_SVE_VL_5936: pass
arm64_sve-ptrace_Set_SVE_VL_5952: pass
arm64_sve-ptrace_Set_SVE_VL_5968: pass
arm64_sve-ptrace_Set_SVE_VL_5984: pass
arm64_sve-ptrace_Set_SVE_VL_6000: pass
arm64_sve-ptrace_Set_SVE_VL_6016: pass
arm64_sve-ptrace_Set_SVE_VL_6032: pass
arm64_sve-ptrace_Set_SVE_VL_6048: pass
arm64_sve-ptrace_Set_SVE_VL_6064: pass
arm64_sve-ptrace_Set_SVE_VL_608: pass
arm64_sve-ptrace_Set_SVE_VL_6080: pass
arm64_sve-ptrace_Set_SVE_VL_6096: pass
arm64_sve-ptrace_Set_SVE_VL_6112: pass
arm64_sve-ptrace_Set_SVE_VL_6128: pass
arm64_sve-ptrace_Set_SVE_VL_6144: pass
arm64_sve-ptrace_Set_SVE_VL_6160: pass
arm64_sve-ptrace_Set_SVE_VL_6176: pass
arm64_sve-ptrace_Set_SVE_VL_6192: pass
arm64_sve-ptrace_Set_SVE_VL_6208: pass
arm64_sve-ptrace_Set_SVE_VL_6224: pass
arm64_sve-ptrace_Set_SVE_VL_624: pass
arm64_sve-ptrace_Set_SVE_VL_6240: pass
arm64_sve-ptrace_Set_SVE_VL_6256: pass
arm64_sve-ptrace_Set_SVE_VL_6272: pass
arm64_sve-ptrace_Set_SVE_VL_6288: pass
arm64_sve-ptrace_Set_SVE_VL_6304: pass
arm64_sve-ptrace_Set_SVE_VL_6320: pass
arm64_sve-ptrace_Set_SVE_VL_6336: pass
arm64_sve-ptrace_Set_SVE_VL_6352: pass
arm64_sve-ptrace_Set_SVE_VL_6368: pass
arm64_sve-ptrace_Set_SVE_VL_6384: pass
arm64_sve-ptrace_Set_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_640: pass
arm64_sve-ptrace_Set_SVE_VL_6400: pass
arm64_sve-ptrace_Set_SVE_VL_6416: pass
arm64_sve-ptrace_Set_SVE_VL_6432: pass
arm64_sve-ptrace_Set_SVE_VL_6448: pass
arm64_sve-ptrace_Set_SVE_VL_6464: pass
arm64_sve-ptrace_Set_SVE_VL_6480: pass
arm64_sve-ptrace_Set_SVE_VL_6496: pass
arm64_sve-ptrace_Set_SVE_VL_6512: pass
arm64_sve-ptrace_Set_SVE_VL_6528: pass
arm64_sve-ptrace_Set_SVE_VL_6544: pass
arm64_sve-ptrace_Set_SVE_VL_656: pass
arm64_sve-ptrace_Set_SVE_VL_6560: pass
arm64_sve-ptrace_Set_SVE_VL_6576: pass
arm64_sve-ptrace_Set_SVE_VL_6592: pass
arm64_sve-ptrace_Set_SVE_VL_6608: pass
arm64_sve-ptrace_Set_SVE_VL_6624: pass
arm64_sve-ptrace_Set_SVE_VL_6640: pass
arm64_sve-ptrace_Set_SVE_VL_6656: pass
arm64_sve-ptrace_Set_SVE_VL_6672: pass
arm64_sve-ptrace_Set_SVE_VL_6688: pass
arm64_sve-ptrace_Set_SVE_VL_6704: pass
arm64_sve-ptrace_Set_SVE_VL_672: pass
arm64_sve-ptrace_Set_SVE_VL_6720: pass
arm64_sve-ptrace_Set_SVE_VL_6736: pass
arm64_sve-ptrace_Set_SVE_VL_6752: pass
arm64_sve-ptrace_Set_SVE_VL_6768: pass
arm64_sve-ptrace_Set_SVE_VL_6784: pass
arm64_sve-ptrace_Set_SVE_VL_6800: pass
arm64_sve-ptrace_Set_SVE_VL_6816: pass
arm64_sve-ptrace_Set_SVE_VL_6832: pass
arm64_sve-ptrace_Set_SVE_VL_6848: pass
arm64_sve-ptrace_Set_SVE_VL_6864: pass
arm64_sve-ptrace_Set_SVE_VL_688: pass
arm64_sve-ptrace_Set_SVE_VL_6880: pass
arm64_sve-ptrace_Set_SVE_VL_6896: pass
arm64_sve-ptrace_Set_SVE_VL_6912: pass
arm64_sve-ptrace_Set_SVE_VL_6928: pass
arm64_sve-ptrace_Set_SVE_VL_6944: pass
arm64_sve-ptrace_Set_SVE_VL_6960: pass
arm64_sve-ptrace_Set_SVE_VL_6976: pass
arm64_sve-ptrace_Set_SVE_VL_6992: pass
arm64_sve-ptrace_Set_SVE_VL_7008: pass
arm64_sve-ptrace_Set_SVE_VL_7024: pass
arm64_sve-ptrace_Set_SVE_VL_704: pass
arm64_sve-ptrace_Set_SVE_VL_7040: pass
arm64_sve-ptrace_Set_SVE_VL_7056: pass
arm64_sve-ptrace_Set_SVE_VL_7072: pass
arm64_sve-ptrace_Set_SVE_VL_7088: pass
arm64_sve-ptrace_Set_SVE_VL_7104: pass
arm64_sve-ptrace_Set_SVE_VL_7120: pass
arm64_sve-ptrace_Set_SVE_VL_7136: pass
arm64_sve-ptrace_Set_SVE_VL_7152: pass
arm64_sve-ptrace_Set_SVE_VL_7168: pass
arm64_sve-ptrace_Set_SVE_VL_7184: pass
arm64_sve-ptrace_Set_SVE_VL_720: pass
arm64_sve-ptrace_Set_SVE_VL_7200: pass
arm64_sve-ptrace_Set_SVE_VL_7216: pass
arm64_sve-ptrace_Set_SVE_VL_7232: pass
arm64_sve-ptrace_Set_SVE_VL_7248: pass
arm64_sve-ptrace_Set_SVE_VL_7264: pass
arm64_sve-ptrace_Set_SVE_VL_7280: pass
arm64_sve-ptrace_Set_SVE_VL_7296: pass
arm64_sve-ptrace_Set_SVE_VL_7312: pass
arm64_sve-ptrace_Set_SVE_VL_7328: pass
arm64_sve-ptrace_Set_SVE_VL_7344: pass
arm64_sve-ptrace_Set_SVE_VL_736: pass
arm64_sve-ptrace_Set_SVE_VL_7360: pass
arm64_sve-ptrace_Set_SVE_VL_7376: pass
arm64_sve-ptrace_Set_SVE_VL_7392: pass
arm64_sve-ptrace_Set_SVE_VL_7408: pass
arm64_sve-ptrace_Set_SVE_VL_7424: pass
arm64_sve-ptrace_Set_SVE_VL_7440: pass
arm64_sve-ptrace_Set_SVE_VL_7456: pass
arm64_sve-ptrace_Set_SVE_VL_7472: pass
arm64_sve-ptrace_Set_SVE_VL_7488: pass
arm64_sve-ptrace_Set_SVE_VL_7504: pass
arm64_sve-ptrace_Set_SVE_VL_752: pass
arm64_sve-ptrace_Set_SVE_VL_7520: pass
arm64_sve-ptrace_Set_SVE_VL_7536: pass
arm64_sve-ptrace_Set_SVE_VL_7552: pass
arm64_sve-ptrace_Set_SVE_VL_7568: pass
arm64_sve-ptrace_Set_SVE_VL_7584: pass
arm64_sve-ptrace_Set_SVE_VL_7600: pass
arm64_sve-ptrace_Set_SVE_VL_7616: pass
arm64_sve-ptrace_Set_SVE_VL_7632: pass
arm64_sve-ptrace_Set_SVE_VL_7648: pass
arm64_sve-ptrace_Set_SVE_VL_7664: pass
arm64_sve-ptrace_Set_SVE_VL_768: pass
arm64_sve-ptrace_Set_SVE_VL_7680: pass
arm64_sve-ptrace_Set_SVE_VL_7696: pass
arm64_sve-ptrace_Set_SVE_VL_7712: pass
arm64_sve-ptrace_Set_SVE_VL_7728: pass
arm64_sve-ptrace_Set_SVE_VL_7744: pass
arm64_sve-ptrace_Set_SVE_VL_7760: pass
arm64_sve-ptrace_Set_SVE_VL_7776: pass
arm64_sve-ptrace_Set_SVE_VL_7792: pass
arm64_sve-ptrace_Set_SVE_VL_7808: pass
arm64_sve-ptrace_Set_SVE_VL_7824: pass
arm64_sve-ptrace_Set_SVE_VL_784: pass
arm64_sve-ptrace_Set_SVE_VL_7840: pass
arm64_sve-ptrace_Set_SVE_VL_7856: pass
arm64_sve-ptrace_Set_SVE_VL_7872: pass
arm64_sve-ptrace_Set_SVE_VL_7888: pass
arm64_sve-ptrace_Set_SVE_VL_7904: pass
arm64_sve-ptrace_Set_SVE_VL_7920: pass
arm64_sve-ptrace_Set_SVE_VL_7936: pass
arm64_sve-ptrace_Set_SVE_VL_7952: pass
arm64_sve-ptrace_Set_SVE_VL_7968: pass
arm64_sve-ptrace_Set_SVE_VL_7984: pass
arm64_sve-ptrace_Set_SVE_VL_80: pass
arm64_sve-ptrace_Set_SVE_VL_800: pass
arm64_sve-ptrace_Set_SVE_VL_8000: pass
arm64_sve-ptrace_Set_SVE_VL_8016: pass
arm64_sve-ptrace_Set_SVE_VL_8032: pass
arm64_sve-ptrace_Set_SVE_VL_8048: pass
arm64_sve-ptrace_Set_SVE_VL_8064: pass
arm64_sve-ptrace_Set_SVE_VL_8080: pass
arm64_sve-ptrace_Set_SVE_VL_8096: pass
arm64_sve-ptrace_Set_SVE_VL_8112: pass
arm64_sve-ptrace_Set_SVE_VL_8128: pass
arm64_sve-ptrace_Set_SVE_VL_8144: pass
arm64_sve-ptrace_Set_SVE_VL_816: pass
arm64_sve-ptrace_Set_SVE_VL_8160: pass
arm64_sve-ptrace_Set_SVE_VL_8176: pass
arm64_sve-ptrace_Set_SVE_VL_8192: pass
arm64_sve-ptrace_Set_SVE_VL_832: pass
arm64_sve-ptrace_Set_SVE_VL_848: pass
arm64_sve-ptrace_Set_SVE_VL_864: pass
arm64_sve-ptrace_Set_SVE_VL_880: pass
arm64_sve-ptrace_Set_SVE_VL_896: pass
arm64_sve-ptrace_Set_SVE_VL_912: pass
arm64_sve-ptrace_Set_SVE_VL_928: pass
arm64_sve-ptrace_Set_SVE_VL_944: pass
arm64_sve-ptrace_Set_SVE_VL_96: pass
arm64_sve-ptrace_Set_SVE_VL_960: pass
arm64_sve-ptrace_Set_SVE_VL_976: pass
arm64_sve-ptrace_Set_SVE_VL_992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_48: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_80: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_96: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_992: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve_regs: pass
arm64_sve_vl: pass
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_getpid_SVE_VL_112: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16: pass
arm64_syscall-abi_getpid_SVE_VL_160: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi_sched_yield_SVE_VL_112: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16: pass
arm64_syscall-abi_sched_yield_SVE_VL_160: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_default_value: pass
arm64_tpidr2_write_clone_read: pass
arm64_tpidr2_write_fork_read: pass
arm64_tpidr2_write_read: pass
arm64_tpidr2_write_sleep_read: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_current_VL_is_32: pass
arm64_vec-syscfg_SME_default_vector_length_32: pass
arm64_vec-syscfg_SME_maximum_vector_length_256: pass
arm64_vec-syscfg_SME_minimum_vector_length_16: pass
arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SME_prctl_set_min_max: pass
arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32: pass
arm64_vec-syscfg_SME_vector_length_set_on_exec: pass
arm64_vec-syscfg_SME_vector_length_used_default: pass
arm64_vec-syscfg_SME_vector_length_was_inherited: pass
arm64_vec-syscfg_SVE_current_VL_is_64: pass
arm64_vec-syscfg_SVE_default_vector_length_64: pass
arm64_vec-syscfg_SVE_maximum_vector_length_256: pass
arm64_vec-syscfg_SVE_minimum_vector_length_16: pass
arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SVE_prctl_set_min_max: pass
arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64: pass
arm64_vec-syscfg_SVE_vector_length_set_on_exec: pass
arm64_vec-syscfg_SVE_vector_length_used_default: pass
arm64_vec-syscfg_SVE_vector_length_was_inherited: pass
arm64_za-fork: pass
arm64_za-fork_fork_test: pass
arm64_za-ptrace: pass
arm64_za-ptrace_Data_match_for_VL_128: pass
arm64_za-ptrace_Data_match_for_VL_16: pass
arm64_za-ptrace_Data_match_for_VL_256: pass
arm64_za-ptrace_Data_match_for_VL_32: pass
arm64_za-ptrace_Data_match_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_128: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_16: pass
arm64_za-ptrace_Disabled_ZA_for_VL_160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_256: pass
arm64_za-ptrace_Disabled_ZA_for_VL_2560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_32: pass
arm64_za-ptrace_Disabled_ZA_for_VL_320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_48: skip
arm64_za-ptrace_Disabled_ZA_for_VL_480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_80: skip
arm64_za-ptrace_Disabled_ZA_for_VL_800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_96: skip
arm64_za-ptrace_Disabled_ZA_for_VL_960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_48: skip
arm64_za-ptrace_Get_and_set_data_for_VL_480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_80: skip
arm64_za-ptrace_Get_and_set_data_for_VL_800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_96: skip
arm64_za-ptrace_Get_and_set_data_for_VL_960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_992: skip
arm64_za-ptrace_Set_VL_1008: pass
arm64_za-ptrace_Set_VL_1024: pass
arm64_za-ptrace_Set_VL_1040: pass
arm64_za-ptrace_Set_VL_1056: pass
arm64_za-ptrace_Set_VL_1072: pass
arm64_za-ptrace_Set_VL_1088: pass
arm64_za-ptrace_Set_VL_1104: pass
arm64_za-ptrace_Set_VL_112: pass
arm64_za-ptrace_Set_VL_1120: pass
arm64_za-ptrace_Set_VL_1136: pass
arm64_za-ptrace_Set_VL_1152: pass
arm64_za-ptrace_Set_VL_1168: pass
arm64_za-ptrace_Set_VL_1184: pass
arm64_za-ptrace_Set_VL_1200: pass
arm64_za-ptrace_Set_VL_1216: pass
arm64_za-ptrace_Set_VL_1232: pass
arm64_za-ptrace_Set_VL_1248: pass
arm64_za-ptrace_Set_VL_1264: pass
arm64_za-ptrace_Set_VL_128: pass
arm64_za-ptrace_Set_VL_1280: pass
arm64_za-ptrace_Set_VL_1296: pass
arm64_za-ptrace_Set_VL_1312: pass
arm64_za-ptrace_Set_VL_1328: pass
arm64_za-ptrace_Set_VL_1344: pass
arm64_za-ptrace_Set_VL_1360: pass
arm64_za-ptrace_Set_VL_1376: pass
arm64_za-ptrace_Set_VL_1392: pass
arm64_za-ptrace_Set_VL_1408: pass
arm64_za-ptrace_Set_VL_1424: pass
arm64_za-ptrace_Set_VL_144: pass
arm64_za-ptrace_Set_VL_1440: pass
arm64_za-ptrace_Set_VL_1456: pass
arm64_za-ptrace_Set_VL_1472: pass
arm64_za-ptrace_Set_VL_1488: pass
arm64_za-ptrace_Set_VL_1504: pass
arm64_za-ptrace_Set_VL_1520: pass
arm64_za-ptrace_Set_VL_1536: pass
arm64_za-ptrace_Set_VL_1552: pass
arm64_za-ptrace_Set_VL_1568: pass
arm64_za-ptrace_Set_VL_1584: pass
arm64_za-ptrace_Set_VL_16: pass
arm64_za-ptrace_Set_VL_160: pass
arm64_za-ptrace_Set_VL_1600: pass
arm64_za-ptrace_Set_VL_1616: pass
arm64_za-ptrace_Set_VL_1632: pass
arm64_za-ptrace_Set_VL_1648: pass
arm64_za-ptrace_Set_VL_1664: pass
arm64_za-ptrace_Set_VL_1680: pass
arm64_za-ptrace_Set_VL_1696: pass
arm64_za-ptrace_Set_VL_1712: pass
arm64_za-ptrace_Set_VL_1728: pass
arm64_za-ptrace_Set_VL_1744: pass
arm64_za-ptrace_Set_VL_176: pass
arm64_za-ptrace_Set_VL_1760: pass
arm64_za-ptrace_Set_VL_1776: pass
arm64_za-ptrace_Set_VL_1792: pass
arm64_za-ptrace_Set_VL_1808: pass
arm64_za-ptrace_Set_VL_1824: pass
arm64_za-ptrace_Set_VL_1840: pass
arm64_za-ptrace_Set_VL_1856: pass
arm64_za-ptrace_Set_VL_1872: pass
arm64_za-ptrace_Set_VL_1888: pass
arm64_za-ptrace_Set_VL_1904: pass
arm64_za-ptrace_Set_VL_192: pass
arm64_za-ptrace_Set_VL_1920: pass
arm64_za-ptrace_Set_VL_1936: pass
arm64_za-ptrace_Set_VL_1952: pass
arm64_za-ptrace_Set_VL_1968: pass
arm64_za-ptrace_Set_VL_1984: pass
arm64_za-ptrace_Set_VL_2000: pass
arm64_za-ptrace_Set_VL_2016: pass
arm64_za-ptrace_Set_VL_2032: pass
arm64_za-ptrace_Set_VL_2048: pass
arm64_za-ptrace_Set_VL_2064: pass
arm64_za-ptrace_Set_VL_208: pass
arm64_za-ptrace_Set_VL_2080: pass
arm64_za-ptrace_Set_VL_2096: pass
arm64_za-ptrace_Set_VL_2112: pass
arm64_za-ptrace_Set_VL_2128: pass
arm64_za-ptrace_Set_VL_2144: pass
arm64_za-ptrace_Set_VL_2160: pass
arm64_za-ptrace_Set_VL_2176: pass
arm64_za-ptrace_Set_VL_2192: pass
arm64_za-ptrace_Set_VL_2208: pass
arm64_za-ptrace_Set_VL_2224: pass
arm64_za-ptrace_Set_VL_224: pass
arm64_za-ptrace_Set_VL_2240: pass
arm64_za-ptrace_Set_VL_2256: pass
arm64_za-ptrace_Set_VL_2272: pass
arm64_za-ptrace_Set_VL_2288: pass
arm64_za-ptrace_Set_VL_2304: pass
arm64_za-ptrace_Set_VL_2320: pass
arm64_za-ptrace_Set_VL_2336: pass
arm64_za-ptrace_Set_VL_2352: pass
arm64_za-ptrace_Set_VL_2368: pass
arm64_za-ptrace_Set_VL_2384: pass
arm64_za-ptrace_Set_VL_240: pass
arm64_za-ptrace_Set_VL_2400: pass
arm64_za-ptrace_Set_VL_2416: pass
arm64_za-ptrace_Set_VL_2432: pass
arm64_za-ptrace_Set_VL_2448: pass
arm64_za-ptrace_Set_VL_2464: pass
arm64_za-ptrace_Set_VL_2480: pass
arm64_za-ptrace_Set_VL_2496: pass
arm64_za-ptrace_Set_VL_2512: pass
arm64_za-ptrace_Set_VL_2528: pass
arm64_za-ptrace_Set_VL_2544: pass
arm64_za-ptrace_Set_VL_256: pass
arm64_za-ptrace_Set_VL_2560: pass
arm64_za-ptrace_Set_VL_2576: pass
arm64_za-ptrace_Set_VL_2592: pass
arm64_za-ptrace_Set_VL_2608: pass
arm64_za-ptrace_Set_VL_2624: pass
arm64_za-ptrace_Set_VL_2640: pass
arm64_za-ptrace_Set_VL_2656: pass
arm64_za-ptrace_Set_VL_2672: pass
arm64_za-ptrace_Set_VL_2688: pass
arm64_za-ptrace_Set_VL_2704: pass
arm64_za-ptrace_Set_VL_272: pass
arm64_za-ptrace_Set_VL_2720: pass
arm64_za-ptrace_Set_VL_2736: pass
arm64_za-ptrace_Set_VL_2752: pass
arm64_za-ptrace_Set_VL_2768: pass
arm64_za-ptrace_Set_VL_2784: pass
arm64_za-ptrace_Set_VL_2800: pass
arm64_za-ptrace_Set_VL_2816: pass
arm64_za-ptrace_Set_VL_2832: pass
arm64_za-ptrace_Set_VL_2848: pass
arm64_za-ptrace_Set_VL_2864: pass
arm64_za-ptrace_Set_VL_288: pass
arm64_za-ptrace_Set_VL_2880: pass
arm64_za-ptrace_Set_VL_2896: pass
arm64_za-ptrace_Set_VL_2912: pass
arm64_za-ptrace_Set_VL_2928: pass
arm64_za-ptrace_Set_VL_2944: pass
arm64_za-ptrace_Set_VL_2960: pass
arm64_za-ptrace_Set_VL_2976: pass
arm64_za-ptrace_Set_VL_2992: pass
arm64_za-ptrace_Set_VL_3008: pass
arm64_za-ptrace_Set_VL_3024: pass
arm64_za-ptrace_Set_VL_304: pass
arm64_za-ptrace_Set_VL_3040: pass
arm64_za-ptrace_Set_VL_3056: pass
arm64_za-ptrace_Set_VL_3072: pass
arm64_za-ptrace_Set_VL_3088: pass
arm64_za-ptrace_Set_VL_3104: pass
arm64_za-ptrace_Set_VL_3120: pass
arm64_za-ptrace_Set_VL_3136: pass
arm64_za-ptrace_Set_VL_3152: pass
arm64_za-ptrace_Set_VL_3168: pass
arm64_za-ptrace_Set_VL_3184: pass
arm64_za-ptrace_Set_VL_32: pass
arm64_za-ptrace_Set_VL_320: pass
arm64_za-ptrace_Set_VL_3200: pass
arm64_za-ptrace_Set_VL_3216: pass
arm64_za-ptrace_Set_VL_3232: pass
arm64_za-ptrace_Set_VL_3248: pass
arm64_za-ptrace_Set_VL_3264: pass
arm64_za-ptrace_Set_VL_3280: pass
arm64_za-ptrace_Set_VL_3296: pass
arm64_za-ptrace_Set_VL_3312: pass
arm64_za-ptrace_Set_VL_3328: pass
arm64_za-ptrace_Set_VL_3344: pass
arm64_za-ptrace_Set_VL_336: pass
arm64_za-ptrace_Set_VL_3360: pass
arm64_za-ptrace_Set_VL_3376: pass
arm64_za-ptrace_Set_VL_3392: pass
arm64_za-ptrace_Set_VL_3408: pass
arm64_za-ptrace_Set_VL_3424: pass
arm64_za-ptrace_Set_VL_3440: pass
arm64_za-ptrace_Set_VL_3456: pass
arm64_za-ptrace_Set_VL_3472: pass
arm64_za-ptrace_Set_VL_3488: pass
arm64_za-ptrace_Set_VL_3504: pass
arm64_za-ptrace_Set_VL_352: pass
arm64_za-ptrace_Set_VL_3520: pass
arm64_za-ptrace_Set_VL_3536: pass
arm64_za-ptrace_Set_VL_3552: pass
arm64_za-ptrace_Set_VL_3568: pass
arm64_za-ptrace_Set_VL_3584: pass
arm64_za-ptrace_Set_VL_3600: pass
arm64_za-ptrace_Set_VL_3616: pass
arm64_za-ptrace_Set_VL_3632: pass
arm64_za-ptrace_Set_VL_3648: pass
arm64_za-ptrace_Set_VL_3664: pass
arm64_za-ptrace_Set_VL_368: pass
arm64_za-ptrace_Set_VL_3680: pass
arm64_za-ptrace_Set_VL_3696: pass
arm64_za-ptrace_Set_VL_3712: pass
arm64_za-ptrace_Set_VL_3728: pass
arm64_za-ptrace_Set_VL_3744: pass
arm64_za-ptrace_Set_VL_3760: pass
arm64_za-ptrace_Set_VL_3776: pass
arm64_za-ptrace_Set_VL_3792: pass
arm64_za-ptrace_Set_VL_3808: pass
arm64_za-ptrace_Set_VL_3824: pass
arm64_za-ptrace_Set_VL_384: pass
arm64_za-ptrace_Set_VL_3840: pass
arm64_za-ptrace_Set_VL_3856: pass
arm64_za-ptrace_Set_VL_3872: pass
arm64_za-ptrace_Set_VL_3888: pass
arm64_za-ptrace_Set_VL_3904: pass
arm64_za-ptrace_Set_VL_3920: pass
arm64_za-ptrace_Set_VL_3936: pass
arm64_za-ptrace_Set_VL_3952: pass
arm64_za-ptrace_Set_VL_3968: pass
arm64_za-ptrace_Set_VL_3984: pass
arm64_za-ptrace_Set_VL_400: pass
arm64_za-ptrace_Set_VL_4000: pass
arm64_za-ptrace_Set_VL_4016: pass
arm64_za-ptrace_Set_VL_4032: pass
arm64_za-ptrace_Set_VL_4048: pass
arm64_za-ptrace_Set_VL_4064: pass
arm64_za-ptrace_Set_VL_4080: pass
arm64_za-ptrace_Set_VL_4096: pass
arm64_za-ptrace_Set_VL_4112: pass
arm64_za-ptrace_Set_VL_4128: pass
arm64_za-ptrace_Set_VL_4144: pass
arm64_za-ptrace_Set_VL_416: pass
arm64_za-ptrace_Set_VL_4160: pass
arm64_za-ptrace_Set_VL_4176: pass
arm64_za-ptrace_Set_VL_4192: pass
arm64_za-ptrace_Set_VL_4208: pass
arm64_za-ptrace_Set_VL_4224: pass
arm64_za-ptrace_Set_VL_4240: pass
arm64_za-ptrace_Set_VL_4256: pass
arm64_za-ptrace_Set_VL_4272: pass
arm64_za-ptrace_Set_VL_4288: pass
arm64_za-ptrace_Set_VL_4304: pass
arm64_za-ptrace_Set_VL_432: pass
arm64_za-ptrace_Set_VL_4320: pass
arm64_za-ptrace_Set_VL_4336: pass
arm64_za-ptrace_Set_VL_4352: pass
arm64_za-ptrace_Set_VL_4368: pass
arm64_za-ptrace_Set_VL_4384: pass
arm64_za-ptrace_Set_VL_4400: pass
arm64_za-ptrace_Set_VL_4416: pass
arm64_za-ptrace_Set_VL_4432: pass
arm64_za-ptrace_Set_VL_4448: pass
arm64_za-ptrace_Set_VL_4464: pass
arm64_za-ptrace_Set_VL_448: pass
arm64_za-ptrace_Set_VL_4480: pass
arm64_za-ptrace_Set_VL_4496: pass
arm64_za-ptrace_Set_VL_4512: pass
arm64_za-ptrace_Set_VL_4528: pass
arm64_za-ptrace_Set_VL_4544: pass
arm64_za-ptrace_Set_VL_4560: pass
arm64_za-ptrace_Set_VL_4576: pass
arm64_za-ptrace_Set_VL_4592: pass
arm64_za-ptrace_Set_VL_4608: pass
arm64_za-ptrace_Set_VL_4624: pass
arm64_za-ptrace_Set_VL_464: pass
arm64_za-ptrace_Set_VL_4640: pass
arm64_za-ptrace_Set_VL_4656: pass
arm64_za-ptrace_Set_VL_4672: pass
arm64_za-ptrace_Set_VL_4688: pass
arm64_za-ptrace_Set_VL_4704: pass
arm64_za-ptrace_Set_VL_4720: pass
arm64_za-ptrace_Set_VL_4736: pass
arm64_za-ptrace_Set_VL_4752: pass
arm64_za-ptrace_Set_VL_4768: pass
arm64_za-ptrace_Set_VL_4784: pass
arm64_za-ptrace_Set_VL_48: pass
arm64_za-ptrace_Set_VL_480: pass
arm64_za-ptrace_Set_VL_4800: pass
arm64_za-ptrace_Set_VL_4816: pass
arm64_za-ptrace_Set_VL_4832: pass
arm64_za-ptrace_Set_VL_4848: pass
arm64_za-ptrace_Set_VL_4864: pass
arm64_za-ptrace_Set_VL_4880: pass
arm64_za-ptrace_Set_VL_4896: pass
arm64_za-ptrace_Set_VL_4912: pass
arm64_za-ptrace_Set_VL_4928: pass
arm64_za-ptrace_Set_VL_4944: pass
arm64_za-ptrace_Set_VL_496: pass
arm64_za-ptrace_Set_VL_4960: pass
arm64_za-ptrace_Set_VL_4976: pass
arm64_za-ptrace_Set_VL_4992: pass
arm64_za-ptrace_Set_VL_5008: pass
arm64_za-ptrace_Set_VL_5024: pass
arm64_za-ptrace_Set_VL_5040: pass
arm64_za-ptrace_Set_VL_5056: pass
arm64_za-ptrace_Set_VL_5072: pass
arm64_za-ptrace_Set_VL_5088: pass
arm64_za-ptrace_Set_VL_5104: pass
arm64_za-ptrace_Set_VL_512: pass
arm64_za-ptrace_Set_VL_5120: pass
arm64_za-ptrace_Set_VL_5136: pass
arm64_za-ptrace_Set_VL_5152: pass
arm64_za-ptrace_Set_VL_5168: pass
arm64_za-ptrace_Set_VL_5184: pass
arm64_za-ptrace_Set_VL_5200: pass
arm64_za-ptrace_Set_VL_5216: pass
arm64_za-ptrace_Set_VL_5232: pass
arm64_za-ptrace_Set_VL_5248: pass
arm64_za-ptrace_Set_VL_5264: pass
arm64_za-ptrace_Set_VL_528: pass
arm64_za-ptrace_Set_VL_5280: pass
arm64_za-ptrace_Set_VL_5296: pass
arm64_za-ptrace_Set_VL_5312: pass
arm64_za-ptrace_Set_VL_5328: pass
arm64_za-ptrace_Set_VL_5344: pass
arm64_za-ptrace_Set_VL_5360: pass
arm64_za-ptrace_Set_VL_5376: pass
arm64_za-ptrace_Set_VL_5392: pass
arm64_za-ptrace_Set_VL_5408: pass
arm64_za-ptrace_Set_VL_5424: pass
arm64_za-ptrace_Set_VL_544: pass
arm64_za-ptrace_Set_VL_5440: pass
arm64_za-ptrace_Set_VL_5456: pass
arm64_za-ptrace_Set_VL_5472: pass
arm64_za-ptrace_Set_VL_5488: pass
arm64_za-ptrace_Set_VL_5504: pass
arm64_za-ptrace_Set_VL_5520: pass
arm64_za-ptrace_Set_VL_5536: pass
arm64_za-ptrace_Set_VL_5552: pass
arm64_za-ptrace_Set_VL_5568: pass
arm64_za-ptrace_Set_VL_5584: pass
arm64_za-ptrace_Set_VL_560: pass
arm64_za-ptrace_Set_VL_5600: pass
arm64_za-ptrace_Set_VL_5616: pass
arm64_za-ptrace_Set_VL_5632: pass
arm64_za-ptrace_Set_VL_5648: pass
arm64_za-ptrace_Set_VL_5664: pass
arm64_za-ptrace_Set_VL_5680: pass
arm64_za-ptrace_Set_VL_5696: pass
arm64_za-ptrace_Set_VL_5712: pass
arm64_za-ptrace_Set_VL_5728: pass
arm64_za-ptrace_Set_VL_5744: pass
arm64_za-ptrace_Set_VL_576: pass
arm64_za-ptrace_Set_VL_5760: pass
arm64_za-ptrace_Set_VL_5776: pass
arm64_za-ptrace_Set_VL_5792: pass
arm64_za-ptrace_Set_VL_5808: pass
arm64_za-ptrace_Set_VL_5824: pass
arm64_za-ptrace_Set_VL_5840: pass
arm64_za-ptrace_Set_VL_5856: pass
arm64_za-ptrace_Set_VL_5872: pass
arm64_za-ptrace_Set_VL_5888: pass
arm64_za-ptrace_Set_VL_5904: pass
arm64_za-ptrace_Set_VL_592: pass
arm64_za-ptrace_Set_VL_5920: pass
arm64_za-ptrace_Set_VL_5936: pass
arm64_za-ptrace_Set_VL_5952: pass
arm64_za-ptrace_Set_VL_5968: pass
arm64_za-ptrace_Set_VL_5984: pass
arm64_za-ptrace_Set_VL_6000: pass
arm64_za-ptrace_Set_VL_6016: pass
arm64_za-ptrace_Set_VL_6032: pass
arm64_za-ptrace_Set_VL_6048: pass
arm64_za-ptrace_Set_VL_6064: pass
arm64_za-ptrace_Set_VL_608: pass
arm64_za-ptrace_Set_VL_6080: pass
arm64_za-ptrace_Set_VL_6096: pass
arm64_za-ptrace_Set_VL_6112: pass
arm64_za-ptrace_Set_VL_6128: pass
arm64_za-ptrace_Set_VL_6144: pass
arm64_za-ptrace_Set_VL_6160: pass
arm64_za-ptrace_Set_VL_6176: pass
arm64_za-ptrace_Set_VL_6192: pass
arm64_za-ptrace_Set_VL_6208: pass
arm64_za-ptrace_Set_VL_6224: pass
arm64_za-ptrace_Set_VL_624: pass
arm64_za-ptrace_Set_VL_6240: pass
arm64_za-ptrace_Set_VL_6256: pass
arm64_za-ptrace_Set_VL_6272: pass
arm64_za-ptrace_Set_VL_6288: pass
arm64_za-ptrace_Set_VL_6304: pass
arm64_za-ptrace_Set_VL_6320: pass
arm64_za-ptrace_Set_VL_6336: pass
arm64_za-ptrace_Set_VL_6352: pass
arm64_za-ptrace_Set_VL_6368: pass
arm64_za-ptrace_Set_VL_6384: pass
arm64_za-ptrace_Set_VL_64: pass
arm64_za-ptrace_Set_VL_640: pass
arm64_za-ptrace_Set_VL_6400: pass
arm64_za-ptrace_Set_VL_6416: pass
arm64_za-ptrace_Set_VL_6432: pass
arm64_za-ptrace_Set_VL_6448: pass
arm64_za-ptrace_Set_VL_6464: pass
arm64_za-ptrace_Set_VL_6480: pass
arm64_za-ptrace_Set_VL_6496: pass
arm64_za-ptrace_Set_VL_6512: pass
arm64_za-ptrace_Set_VL_6528: pass
arm64_za-ptrace_Set_VL_6544: pass
arm64_za-ptrace_Set_VL_656: pass
arm64_za-ptrace_Set_VL_6560: pass
arm64_za-ptrace_Set_VL_6576: pass
arm64_za-ptrace_Set_VL_6592: pass
arm64_za-ptrace_Set_VL_6608: pass
arm64_za-ptrace_Set_VL_6624: pass
arm64_za-ptrace_Set_VL_6640: pass
arm64_za-ptrace_Set_VL_6656: pass
arm64_za-ptrace_Set_VL_6672: pass
arm64_za-ptrace_Set_VL_6688: pass
arm64_za-ptrace_Set_VL_6704: pass
arm64_za-ptrace_Set_VL_672: pass
arm64_za-ptrace_Set_VL_6720: pass
arm64_za-ptrace_Set_VL_6736: pass
arm64_za-ptrace_Set_VL_6752: pass
arm64_za-ptrace_Set_VL_6768: pass
arm64_za-ptrace_Set_VL_6784: pass
arm64_za-ptrace_Set_VL_6800: pass
arm64_za-ptrace_Set_VL_6816: pass
arm64_za-ptrace_Set_VL_6832: pass
arm64_za-ptrace_Set_VL_6848: pass
arm64_za-ptrace_Set_VL_6864: pass
arm64_za-ptrace_Set_VL_688: pass
arm64_za-ptrace_Set_VL_6880: pass
arm64_za-ptrace_Set_VL_6896: pass
arm64_za-ptrace_Set_VL_6912: pass
arm64_za-ptrace_Set_VL_6928: pass
arm64_za-ptrace_Set_VL_6944: pass
arm64_za-ptrace_Set_VL_6960: pass
arm64_za-ptrace_Set_VL_6976: pass
arm64_za-ptrace_Set_VL_6992: pass
arm64_za-ptrace_Set_VL_7008: pass
arm64_za-ptrace_Set_VL_7024: pass
arm64_za-ptrace_Set_VL_704: pass
arm64_za-ptrace_Set_VL_7040: pass
arm64_za-ptrace_Set_VL_7056: pass
arm64_za-ptrace_Set_VL_7072: pass
arm64_za-ptrace_Set_VL_7088: pass
arm64_za-ptrace_Set_VL_7104: pass
arm64_za-ptrace_Set_VL_7120: pass
arm64_za-ptrace_Set_VL_7136: pass
arm64_za-ptrace_Set_VL_7152: pass
arm64_za-ptrace_Set_VL_7168: pass
arm64_za-ptrace_Set_VL_7184: pass
arm64_za-ptrace_Set_VL_720: pass
arm64_za-ptrace_Set_VL_7200: pass
arm64_za-ptrace_Set_VL_7216: pass
arm64_za-ptrace_Set_VL_7232: pass
arm64_za-ptrace_Set_VL_7248: pass
arm64_za-ptrace_Set_VL_7264: pass
arm64_za-ptrace_Set_VL_7280: pass
arm64_za-ptrace_Set_VL_7296: pass
arm64_za-ptrace_Set_VL_7312: pass
arm64_za-ptrace_Set_VL_7328: pass
arm64_za-ptrace_Set_VL_7344: pass
arm64_za-ptrace_Set_VL_736: pass
arm64_za-ptrace_Set_VL_7360: pass
arm64_za-ptrace_Set_VL_7376: pass
arm64_za-ptrace_Set_VL_7392: pass
arm64_za-ptrace_Set_VL_7408: pass
arm64_za-ptrace_Set_VL_7424: pass
arm64_za-ptrace_Set_VL_7440: pass
arm64_za-ptrace_Set_VL_7456: pass
arm64_za-ptrace_Set_VL_7472: pass
arm64_za-ptrace_Set_VL_7488: pass
arm64_za-ptrace_Set_VL_7504: pass
arm64_za-ptrace_Set_VL_752: pass
arm64_za-ptrace_Set_VL_7520: pass
arm64_za-ptrace_Set_VL_7536: pass
arm64_za-ptrace_Set_VL_7552: pass
arm64_za-ptrace_Set_VL_7568: pass
arm64_za-ptrace_Set_VL_7584: pass
arm64_za-ptrace_Set_VL_7600: pass
arm64_za-ptrace_Set_VL_7616: pass
arm64_za-ptrace_Set_VL_7632: pass
arm64_za-ptrace_Set_VL_7648: pass
arm64_za-ptrace_Set_VL_7664: pass
arm64_za-ptrace_Set_VL_768: pass
arm64_za-ptrace_Set_VL_7680: pass
arm64_za-ptrace_Set_VL_7696: pass
arm64_za-ptrace_Set_VL_7712: pass
arm64_za-ptrace_Set_VL_7728: pass
arm64_za-ptrace_Set_VL_7744: pass
arm64_za-ptrace_Set_VL_7760: pass
arm64_za-ptrace_Set_VL_7776: pass
arm64_za-ptrace_Set_VL_7792: pass
arm64_za-ptrace_Set_VL_7808: pass
arm64_za-ptrace_Set_VL_7824: pass
arm64_za-ptrace_Set_VL_784: pass
arm64_za-ptrace_Set_VL_7840: pass
arm64_za-ptrace_Set_VL_7856: pass
arm64_za-ptrace_Set_VL_7872: pass
arm64_za-ptrace_Set_VL_7888: pass
arm64_za-ptrace_Set_VL_7904: pass
arm64_za-ptrace_Set_VL_7920: pass
arm64_za-ptrace_Set_VL_7936: pass
arm64_za-ptrace_Set_VL_7952: pass
arm64_za-ptrace_Set_VL_7968: pass
arm64_za-ptrace_Set_VL_7984: pass
arm64_za-ptrace_Set_VL_80: pass
arm64_za-ptrace_Set_VL_800: pass
arm64_za-ptrace_Set_VL_8000: pass
arm64_za-ptrace_Set_VL_8016: pass
arm64_za-ptrace_Set_VL_8032: pass
arm64_za-ptrace_Set_VL_8048: pass
arm64_za-ptrace_Set_VL_8064: pass
arm64_za-ptrace_Set_VL_8080: pass
arm64_za-ptrace_Set_VL_8096: pass
arm64_za-ptrace_Set_VL_8112: pass
arm64_za-ptrace_Set_VL_8128: pass
arm64_za-ptrace_Set_VL_8144: pass
arm64_za-ptrace_Set_VL_816: pass
arm64_za-ptrace_Set_VL_8160: pass
arm64_za-ptrace_Set_VL_8176: pass
arm64_za-ptrace_Set_VL_8192: pass
arm64_za-ptrace_Set_VL_832: pass
arm64_za-ptrace_Set_VL_848: pass
arm64_za-ptrace_Set_VL_864: pass
arm64_za-ptrace_Set_VL_880: pass
arm64_za-ptrace_Set_VL_896: pass
arm64_za-ptrace_Set_VL_912: pass
arm64_za-ptrace_Set_VL_928: pass
arm64_za-ptrace_Set_VL_944: pass
arm64_za-ptrace_Set_VL_96: pass
arm64_za-ptrace_Set_VL_960: pass
arm64_za-ptrace_Set_VL_976: pass
arm64_za-ptrace_Set_VL_992: pass
arm64_za_no_regs: pass
arm64_za_regs: pass
34644 10:11:57.480867 end: 3.1 lava-test-shell (duration 00:05:30) [common]
34645 10:11:57.481043 end: 3 lava-test-retry (duration 00:05:30) [common]
34646 10:11:57.481169 start: 4 finalize (timeout 00:03:17) [common]
34647 10:11:57.481290 start: 4.1 power-off (timeout 00:00:30) [common]
34648 10:11:57.481402 end: 4.1 power-off (duration 00:00:00) [common]
34649 10:11:57.481513 start: 4.2 read-feedback (timeout 00:03:17) [common]
34650 10:11:57.481754 Listened to connection for namespace 'common' for up to 1s
34651 10:11:57.482066 Listened to connection for namespace 'common' for up to 1s
34652 10:11:58.485753 Finalising connection for namespace 'common'
34654 10:11:58.586851 / # poweroff
34655 10:11:58.587395 Already disconnected
34656 10:11:58.587524 poweroff
34657 10:11:58.688328 end: 4.2 read-feedback (duration 00:00:01) [common]
34658 10:11:58.688575 Already disconnected
34659 10:11:58.688709 end: 4 finalize (duration 00:00:01) [common]
34660 10:11:58.688847 Cleaning after the job
34661 10:11:58.688998 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/592431/deployimages-1es6uzg4/kernel
34662 10:11:58.696677 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/592431/deployimages-1es6uzg4/ramdisk
34663 10:11:58.709241 Stopping the qemu container lava-docker-qemu-592431-2.1.1-tl53m9t735
34664 10:12:01.859396 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/592431
34665 10:12:01.931093 Job finished correctly