Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 31
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
1 10:04:50.910294 lava-dispatcher, installed at version: 2023.05.1
2 10:04:50.910517 start: 0 validate
3 10:04:50.910653 Start time: 2023-06-10 10:04:50.910646+00:00 (UTC)
4 10:04:50.910783 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:04:50.910915 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 10:04:51.187281 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:04:51.187467 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:04:51.445509 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:04:51.445693 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:04:51.712025 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:04:51.712314 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:04:51.971800 validate duration: 1.06
14 10:04:51.972118 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:04:51.972221 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:04:51.972306 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:04:51.972432 Not decompressing ramdisk as can be used compressed.
18 10:04:51.972514 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230527.0/arm64/rootfs.cpio.gz
19 10:04:51.972577 saving as /var/lib/lava/dispatcher/tmp/10670700/tftp-deploy-0exqgs1y/ramdisk/rootfs.cpio.gz
20 10:04:51.972638 total size: 43394293 (41MB)
21 10:04:51.973716 progress 0% (0MB)
22 10:04:51.984909 progress 5% (2MB)
23 10:04:51.996111 progress 10% (4MB)
24 10:04:52.007043 progress 15% (6MB)
25 10:04:52.017884 progress 20% (8MB)
26 10:04:52.028814 progress 25% (10MB)
27 10:04:52.039869 progress 30% (12MB)
28 10:04:52.051019 progress 35% (14MB)
29 10:04:52.061932 progress 40% (16MB)
30 10:04:52.072947 progress 45% (18MB)
31 10:04:52.084178 progress 50% (20MB)
32 10:04:52.095264 progress 55% (22MB)
33 10:04:52.106275 progress 60% (24MB)
34 10:04:52.117126 progress 65% (26MB)
35 10:04:52.128181 progress 70% (29MB)
36 10:04:52.139155 progress 75% (31MB)
37 10:04:52.150322 progress 80% (33MB)
38 10:04:52.161236 progress 85% (35MB)
39 10:04:52.172132 progress 90% (37MB)
40 10:04:52.183261 progress 95% (39MB)
41 10:04:52.194166 progress 100% (41MB)
42 10:04:52.194379 41MB downloaded in 0.22s (186.64MB/s)
43 10:04:52.194552 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:04:52.194792 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:04:52.194877 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:04:52.194958 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:04:52.195093 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:04:52.195166 saving as /var/lib/lava/dispatcher/tmp/10670700/tftp-deploy-0exqgs1y/kernel/Image
50 10:04:52.195227 total size: 45746688 (43MB)
51 10:04:52.195287 No compression specified
52 10:04:52.196507 progress 0% (0MB)
53 10:04:52.208118 progress 5% (2MB)
54 10:04:52.219714 progress 10% (4MB)
55 10:04:52.231313 progress 15% (6MB)
56 10:04:52.242920 progress 20% (8MB)
57 10:04:52.254644 progress 25% (10MB)
58 10:04:52.266019 progress 30% (13MB)
59 10:04:52.277592 progress 35% (15MB)
60 10:04:52.289275 progress 40% (17MB)
61 10:04:52.300914 progress 45% (19MB)
62 10:04:52.312657 progress 50% (21MB)
63 10:04:52.323925 progress 55% (24MB)
64 10:04:52.335536 progress 60% (26MB)
65 10:04:52.347058 progress 65% (28MB)
66 10:04:52.358638 progress 70% (30MB)
67 10:04:52.370162 progress 75% (32MB)
68 10:04:52.381526 progress 80% (34MB)
69 10:04:52.393028 progress 85% (37MB)
70 10:04:52.404560 progress 90% (39MB)
71 10:04:52.415869 progress 95% (41MB)
72 10:04:52.427277 progress 100% (43MB)
73 10:04:52.427459 43MB downloaded in 0.23s (187.87MB/s)
74 10:04:52.427611 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:04:52.427837 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:04:52.427923 start: 1.3 download-retry (timeout 00:10:00) [common]
78 10:04:52.428007 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 10:04:52.428169 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:04:52.428247 saving as /var/lib/lava/dispatcher/tmp/10670700/tftp-deploy-0exqgs1y/dtb/mt8192-asurada-spherion-r0.dtb
81 10:04:52.428309 total size: 46924 (0MB)
82 10:04:52.428368 No compression specified
83 10:04:52.429485 progress 69% (0MB)
84 10:04:52.429752 progress 100% (0MB)
85 10:04:52.429902 0MB downloaded in 0.00s (28.13MB/s)
86 10:04:52.430024 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:04:52.430242 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:04:52.430324 start: 1.4 download-retry (timeout 00:10:00) [common]
90 10:04:52.430404 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 10:04:52.430516 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:04:52.430586 saving as /var/lib/lava/dispatcher/tmp/10670700/tftp-deploy-0exqgs1y/modules/modules.tar
93 10:04:52.430647 total size: 8540248 (8MB)
94 10:04:52.430706 Using unxz to decompress xz
95 10:04:52.434208 progress 0% (0MB)
96 10:04:52.456687 progress 5% (0MB)
97 10:04:52.481282 progress 10% (0MB)
98 10:04:52.505820 progress 15% (1MB)
99 10:04:52.531206 progress 20% (1MB)
100 10:04:52.555922 progress 25% (2MB)
101 10:04:52.578772 progress 30% (2MB)
102 10:04:52.604194 progress 35% (2MB)
103 10:04:52.629318 progress 40% (3MB)
104 10:04:52.653610 progress 45% (3MB)
105 10:04:52.680799 progress 50% (4MB)
106 10:04:52.705847 progress 55% (4MB)
107 10:04:52.731775 progress 60% (4MB)
108 10:04:52.758437 progress 65% (5MB)
109 10:04:52.783554 progress 70% (5MB)
110 10:04:52.807660 progress 75% (6MB)
111 10:04:52.831277 progress 80% (6MB)
112 10:04:52.855758 progress 85% (6MB)
113 10:04:52.884630 progress 90% (7MB)
114 10:04:52.909983 progress 95% (7MB)
115 10:04:52.934963 progress 100% (8MB)
116 10:04:52.940270 8MB downloaded in 0.51s (15.98MB/s)
117 10:04:52.940594 end: 1.4.1 http-download (duration 00:00:01) [common]
119 10:04:52.940882 end: 1.4 download-retry (duration 00:00:01) [common]
120 10:04:52.940987 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 10:04:52.941097 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 10:04:52.941195 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:04:52.941300 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 10:04:52.941548 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49
125 10:04:52.941728 makedir: /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin
126 10:04:52.941873 makedir: /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/tests
127 10:04:52.942016 makedir: /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/results
128 10:04:52.942149 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-add-keys
129 10:04:52.942306 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-add-sources
130 10:04:52.942448 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-background-process-start
131 10:04:52.942593 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-background-process-stop
132 10:04:52.942734 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-common-functions
133 10:04:52.942897 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-echo-ipv4
134 10:04:52.943060 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-install-packages
135 10:04:52.943227 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-installed-packages
136 10:04:52.943396 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-os-build
137 10:04:52.943561 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-probe-channel
138 10:04:52.943725 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-probe-ip
139 10:04:52.943893 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-target-ip
140 10:04:52.944092 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-target-mac
141 10:04:52.944228 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-target-storage
142 10:04:52.944371 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-test-case
143 10:04:52.944533 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-test-event
144 10:04:52.944672 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-test-feedback
145 10:04:52.944834 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-test-raise
146 10:04:52.944971 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-test-reference
147 10:04:52.945110 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-test-runner
148 10:04:52.945274 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-test-set
149 10:04:52.945439 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-test-shell
150 10:04:52.945608 Updating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-install-packages (oe)
151 10:04:52.945801 Updating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/bin/lava-installed-packages (oe)
152 10:04:52.945961 Creating /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/environment
153 10:04:52.946097 LAVA metadata
154 10:04:52.946203 - LAVA_JOB_ID=10670700
155 10:04:52.946305 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:04:52.946461 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 10:04:52.946559 skipped lava-vland-overlay
158 10:04:52.946677 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:04:52.946801 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 10:04:52.946894 skipped lava-multinode-overlay
161 10:04:52.947018 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:04:52.947151 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 10:04:52.947288 Loading test definitions
164 10:04:52.947438 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 10:04:52.947549 Using /lava-10670700 at stage 0
166 10:04:52.947988 uuid=10670700_1.5.2.3.1 testdef=None
167 10:04:52.948150 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 10:04:52.948276 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 10:04:52.948999 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 10:04:52.949362 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 10:04:52.950245 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 10:04:52.950632 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 10:04:52.951490 runner path: /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/0/tests/0_igt-gpu-panfrost test_uuid 10670700_1.5.2.3.1
176 10:04:52.951686 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 10:04:52.952040 Creating lava-test-runner.conf files
179 10:04:52.952152 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10670700/lava-overlay-9tsjqb49/lava-10670700/0 for stage 0
180 10:04:52.952263 - 0_igt-gpu-panfrost
181 10:04:52.952374 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 10:04:52.952471 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 10:04:52.959063 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 10:04:52.959205 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 10:04:52.959316 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 10:04:52.959444 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 10:04:52.959578 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 10:04:54.326825 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 10:04:54.327213 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 10:04:54.327353 extracting modules file /var/lib/lava/dispatcher/tmp/10670700/tftp-deploy-0exqgs1y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670700/extract-overlay-ramdisk-7xmwg90w/ramdisk
191 10:04:54.549730 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 10:04:54.549918 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 10:04:54.550061 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670700/compress-overlay-426tte1f/overlay-1.5.2.4.tar.gz to ramdisk
194 10:04:54.550165 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670700/compress-overlay-426tte1f/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10670700/extract-overlay-ramdisk-7xmwg90w/ramdisk
195 10:04:54.558223 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 10:04:54.558425 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 10:04:54.558560 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 10:04:54.558685 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 10:04:54.558772 Building ramdisk /var/lib/lava/dispatcher/tmp/10670700/extract-overlay-ramdisk-7xmwg90w/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10670700/extract-overlay-ramdisk-7xmwg90w/ramdisk
200 10:04:55.436209 >> 369044 blocks
201 10:05:01.249611 rename /var/lib/lava/dispatcher/tmp/10670700/extract-overlay-ramdisk-7xmwg90w/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10670700/tftp-deploy-0exqgs1y/ramdisk/ramdisk.cpio.gz
202 10:05:01.250061 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 10:05:01.250207 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 10:05:01.250325 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 10:05:01.250456 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10670700/tftp-deploy-0exqgs1y/kernel/Image'
206 10:05:13.122597 Returned 0 in 11 seconds
207 10:05:13.223538 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10670700/tftp-deploy-0exqgs1y/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10670700/tftp-deploy-0exqgs1y/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10670700/tftp-deploy-0exqgs1y/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10670700/tftp-deploy-0exqgs1y/kernel/image.itb
208 10:05:14.056830 output: FIT description: Kernel Image image with one or more FDT blobs
209 10:05:14.057175 output: Created: Sat Jun 10 11:05:13 2023
210 10:05:14.057246 output: Image 0 (kernel-1)
211 10:05:14.057309 output: Description:
212 10:05:14.057368 output: Created: Sat Jun 10 11:05:13 2023
213 10:05:14.057431 output: Type: Kernel Image
214 10:05:14.057490 output: Compression: lzma compressed
215 10:05:14.057548 output: Data Size: 10087317 Bytes = 9850.90 KiB = 9.62 MiB
216 10:05:14.057608 output: Architecture: AArch64
217 10:05:14.057664 output: OS: Linux
218 10:05:14.057718 output: Load Address: 0x00000000
219 10:05:14.057773 output: Entry Point: 0x00000000
220 10:05:14.057855 output: Hash algo: crc32
221 10:05:14.057921 output: Hash value: c9e456fd
222 10:05:14.057972 output: Image 1 (fdt-1)
223 10:05:14.058023 output: Description: mt8192-asurada-spherion-r0
224 10:05:14.058074 output: Created: Sat Jun 10 11:05:13 2023
225 10:05:14.058125 output: Type: Flat Device Tree
226 10:05:14.058176 output: Compression: uncompressed
227 10:05:14.058226 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 10:05:14.058277 output: Architecture: AArch64
229 10:05:14.058328 output: Hash algo: crc32
230 10:05:14.058378 output: Hash value: 1df858fa
231 10:05:14.058429 output: Image 2 (ramdisk-1)
232 10:05:14.058480 output: Description: unavailable
233 10:05:14.058530 output: Created: Sat Jun 10 11:05:13 2023
234 10:05:14.058582 output: Type: RAMDisk Image
235 10:05:14.058633 output: Compression: Unknown Compression
236 10:05:14.058684 output: Data Size: 56374129 Bytes = 55052.86 KiB = 53.76 MiB
237 10:05:14.058735 output: Architecture: AArch64
238 10:05:14.058785 output: OS: Linux
239 10:05:14.058836 output: Load Address: unavailable
240 10:05:14.058887 output: Entry Point: unavailable
241 10:05:14.058937 output: Hash algo: crc32
242 10:05:14.058988 output: Hash value: 419072f1
243 10:05:14.059039 output: Default Configuration: 'conf-1'
244 10:05:14.059090 output: Configuration 0 (conf-1)
245 10:05:14.059141 output: Description: mt8192-asurada-spherion-r0
246 10:05:14.059192 output: Kernel: kernel-1
247 10:05:14.059243 output: Init Ramdisk: ramdisk-1
248 10:05:14.059294 output: FDT: fdt-1
249 10:05:14.059345 output: Loadables: kernel-1
250 10:05:14.059395 output:
251 10:05:14.059581 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 10:05:14.059676 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 10:05:14.059797 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 10:05:14.059901 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 10:05:14.059976 No LXC device requested
256 10:05:14.060079 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 10:05:14.060179 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 10:05:14.060255 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 10:05:14.060324 Checking files for TFTP limit of 4294967296 bytes.
260 10:05:14.060784 end: 1 tftp-deploy (duration 00:00:22) [common]
261 10:05:14.060885 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 10:05:14.060975 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 10:05:14.061097 substitutions:
264 10:05:14.061160 - {DTB}: 10670700/tftp-deploy-0exqgs1y/dtb/mt8192-asurada-spherion-r0.dtb
265 10:05:14.061224 - {INITRD}: 10670700/tftp-deploy-0exqgs1y/ramdisk/ramdisk.cpio.gz
266 10:05:14.061282 - {KERNEL}: 10670700/tftp-deploy-0exqgs1y/kernel/Image
267 10:05:14.061338 - {LAVA_MAC}: None
268 10:05:14.061393 - {PRESEED_CONFIG}: None
269 10:05:14.061447 - {PRESEED_LOCAL}: None
270 10:05:14.061501 - {RAMDISK}: 10670700/tftp-deploy-0exqgs1y/ramdisk/ramdisk.cpio.gz
271 10:05:14.061555 - {ROOT_PART}: None
272 10:05:14.061607 - {ROOT}: None
273 10:05:14.061660 - {SERVER_IP}: 192.168.201.1
274 10:05:14.061711 - {TEE}: None
275 10:05:14.061763 Parsed boot commands:
276 10:05:14.061872 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 10:05:14.062037 Parsed boot commands: tftpboot 192.168.201.1 10670700/tftp-deploy-0exqgs1y/kernel/image.itb 10670700/tftp-deploy-0exqgs1y/kernel/cmdline
278 10:05:14.062124 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 10:05:14.062207 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 10:05:14.062295 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 10:05:14.062376 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 10:05:14.062445 Not connected, no need to disconnect.
283 10:05:14.062516 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 10:05:14.062594 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 10:05:14.062657 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
286 10:05:14.065989 Setting prompt string to ['lava-test: # ']
287 10:05:14.066357 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 10:05:14.066473 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 10:05:14.066567 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 10:05:14.066659 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 10:05:14.066851 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
292 10:05:19.429690 >> Command sent successfully.
293 10:05:19.435457 Returned 0 in 5 seconds
294 10:05:19.536009 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 10:05:19.536596 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 10:05:19.536696 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 10:05:19.536786 Setting prompt string to 'Starting depthcharge on Spherion...'
299 10:05:19.536851 Changing prompt to 'Starting depthcharge on Spherion...'
300 10:05:19.536918 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 10:05:19.537176 [Enter `^Ec?' for help]
302 10:05:19.707914
303 10:05:19.708096
304 10:05:19.708172 F0: 102B 0000
305 10:05:19.708235
306 10:05:19.708296 F3: 1001 0000 [0200]
307 10:05:19.711811
308 10:05:19.711898 F3: 1001 0000
309 10:05:19.711965
310 10:05:19.712027 F7: 102D 0000
311 10:05:19.712126
312 10:05:19.715112 F1: 0000 0000
313 10:05:19.715197
314 10:05:19.715263 V0: 0000 0000 [0001]
315 10:05:19.715324
316 10:05:19.717995 00: 0007 8000
317 10:05:19.718080
318 10:05:19.718146 01: 0000 0000
319 10:05:19.718209
320 10:05:19.721385 BP: 0C00 0209 [0000]
321 10:05:19.721483
322 10:05:19.721550 G0: 1182 0000
323 10:05:19.721611
324 10:05:19.725376 EC: 0000 0021 [4000]
325 10:05:19.725534
326 10:05:19.725619 S7: 0000 0000 [0000]
327 10:05:19.725693
328 10:05:19.728796 CC: 0000 0000 [0001]
329 10:05:19.728926
330 10:05:19.728992 T0: 0000 0040 [010F]
331 10:05:19.729054
332 10:05:19.729113 Jump to BL
333 10:05:19.729170
334 10:05:19.755089
335 10:05:19.755219
336 10:05:19.755298
337 10:05:19.762522 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 10:05:19.765503 ARM64: Exception handlers installed.
339 10:05:19.768955 ARM64: Testing exception
340 10:05:19.772402 ARM64: Done test exception
341 10:05:19.779195 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 10:05:19.789291 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 10:05:19.795744 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 10:05:19.806321 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 10:05:19.812712 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 10:05:19.822753 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 10:05:19.833513 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 10:05:19.839918 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 10:05:19.858380 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 10:05:19.862035 WDT: Last reset was cold boot
351 10:05:19.864884 SPI1(PAD0) initialized at 2873684 Hz
352 10:05:19.868209 SPI5(PAD0) initialized at 992727 Hz
353 10:05:19.871313 VBOOT: Loading verstage.
354 10:05:19.878124 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 10:05:19.881580 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 10:05:19.884566 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 10:05:19.888019 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 10:05:19.895419 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 10:05:19.902882 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 10:05:20.188465 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 10:05:20.189006
362 10:05:20.189400
363 10:05:20.189728 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 10:05:20.190048 ARM64: Exception handlers installed.
365 10:05:20.190354 ARM64: Testing exception
366 10:05:20.190655 ARM64: Done test exception
367 10:05:20.190997 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 10:05:20.191307 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 10:05:20.191605 Probing TPM: . done!
370 10:05:20.191940 TPM ready after 0 ms
371 10:05:20.192319 Connected to device vid:did:rid of 1ae0:0028:00
372 10:05:20.192616 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 10:05:20.192913 Initialized TPM device CR50 revision 0
374 10:05:20.193205 tlcl_send_startup: Startup return code is 0
375 10:05:20.193520 TPM: setup succeeded
376 10:05:20.193579 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 10:05:20.193634 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 10:05:20.193690 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 10:05:20.193745 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 10:05:20.193801 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 10:05:20.193899 in-header: 03 07 00 00 08 00 00 00
382 10:05:20.193954 in-data: aa e4 47 04 13 02 00 00
383 10:05:20.194013 Chrome EC: UHEPI supported
384 10:05:20.194076 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 10:05:20.194133 in-header: 03 95 00 00 08 00 00 00
386 10:05:20.194188 in-data: 18 20 20 08 00 00 00 00
387 10:05:20.194259 Phase 1
388 10:05:20.194329 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 10:05:20.194385 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 10:05:20.194441 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 10:05:20.194496 Recovery requested (1009000e)
392 10:05:20.194551 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 10:05:20.194606 tlcl_extend: response is 0
394 10:05:20.194662 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 10:05:20.194734 tlcl_extend: response is 0
396 10:05:20.194791 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 10:05:20.194862 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
398 10:05:20.194953 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 10:05:20.195034
400 10:05:20.195089
401 10:05:20.200818 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 10:05:20.203755 ARM64: Exception handlers installed.
403 10:05:20.207043 ARM64: Testing exception
404 10:05:20.207127 ARM64: Done test exception
405 10:05:20.229795 pmic_efuse_setting: Set efuses in 11 msecs
406 10:05:20.233189 pmwrap_interface_init: Select PMIF_VLD_RDY
407 10:05:20.239564 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 10:05:20.242767 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 10:05:20.250024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 10:05:20.253608 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 10:05:20.256680 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 10:05:20.263801 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 10:05:20.267207 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 10:05:20.274415 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 10:05:20.278228 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 10:05:20.282241 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 10:05:20.285617 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 10:05:20.293249 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 10:05:20.296661 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 10:05:20.300475 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 10:05:20.307806 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 10:05:20.314901 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 10:05:20.318629 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 10:05:20.324900 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 10:05:20.329250 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 10:05:20.337152 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 10:05:20.340412 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 10:05:20.346508 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 10:05:20.354245 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 10:05:20.358007 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 10:05:20.364851 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 10:05:20.368664 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 10:05:20.375927 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 10:05:20.379930 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 10:05:20.383758 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 10:05:20.386878 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 10:05:20.394502 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 10:05:20.398454 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 10:05:20.404728 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 10:05:20.408365 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 10:05:20.411958 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 10:05:20.419476 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 10:05:20.423820 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 10:05:20.427037 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 10:05:20.434665 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 10:05:20.438659 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 10:05:20.442226 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 10:05:20.445551 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 10:05:20.452655 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 10:05:20.456420 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 10:05:20.460358 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 10:05:20.463661 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 10:05:20.467512 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 10:05:20.471297 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 10:05:20.478623 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 10:05:20.482199 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 10:05:20.486118 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 10:05:20.493623 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 10:05:20.500907 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 10:05:20.504310 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 10:05:20.515133 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 10:05:20.522484 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 10:05:20.526296 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 10:05:20.529796 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 10:05:20.537333 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 10:05:20.545219 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x4
467 10:05:20.548256 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 10:05:20.552176 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 10:05:20.555681 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 10:05:20.566992 [RTC]rtc_get_frequency_meter,154: input=15, output=851
471 10:05:20.576581 [RTC]rtc_get_frequency_meter,154: input=7, output=724
472 10:05:20.586293 [RTC]rtc_get_frequency_meter,154: input=11, output=789
473 10:05:20.595351 [RTC]rtc_get_frequency_meter,154: input=13, output=821
474 10:05:20.605308 [RTC]rtc_get_frequency_meter,154: input=12, output=805
475 10:05:20.614762 [RTC]rtc_get_frequency_meter,154: input=11, output=788
476 10:05:20.624281 [RTC]rtc_get_frequency_meter,154: input=12, output=805
477 10:05:20.628052 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 10:05:20.635595 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 10:05:20.638811 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 10:05:20.642581 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 10:05:20.646550 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 10:05:20.649836 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 10:05:20.653231 ADC[4]: Raw value=904064 ID=7
484 10:05:20.657391 ADC[3]: Raw value=213916 ID=1
485 10:05:20.657475 RAM Code: 0x71
486 10:05:20.660670 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 10:05:20.668250 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 10:05:20.675646 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 10:05:20.682976 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 10:05:20.686415 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 10:05:20.689781 in-header: 03 07 00 00 08 00 00 00
492 10:05:20.693732 in-data: aa e4 47 04 13 02 00 00
493 10:05:20.693841 Chrome EC: UHEPI supported
494 10:05:20.701066 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 10:05:20.705013 in-header: 03 95 00 00 08 00 00 00
496 10:05:20.708508 in-data: 18 20 20 08 00 00 00 00
497 10:05:20.712284 MRC: failed to locate region type 0.
498 10:05:20.718988 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 10:05:20.723227 DRAM-K: Running full calibration
500 10:05:20.726644 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 10:05:20.729927 header.status = 0x0
502 10:05:20.733406 header.version = 0x6 (expected: 0x6)
503 10:05:20.737387 header.size = 0xd00 (expected: 0xd00)
504 10:05:20.737469 header.flags = 0x0
505 10:05:20.744219 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 10:05:20.762606 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 10:05:20.770082 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 10:05:20.770168 dram_init: ddr_geometry: 2
509 10:05:20.774335 [EMI] MDL number = 2
510 10:05:20.777172 [EMI] Get MDL freq = 0
511 10:05:20.777267 dram_init: ddr_type: 0
512 10:05:20.781003 is_discrete_lpddr4: 1
513 10:05:20.784617 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 10:05:20.784699
515 10:05:20.784764
516 10:05:20.784824 [Bian_co] ETT version 0.0.0.1
517 10:05:20.791899 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 10:05:20.792007
519 10:05:20.795267 dramc_set_vcore_voltage set vcore to 650000
520 10:05:20.795349 Read voltage for 800, 4
521 10:05:20.799126 Vio18 = 0
522 10:05:20.799208 Vcore = 650000
523 10:05:20.799273 Vdram = 0
524 10:05:20.803331 Vddq = 0
525 10:05:20.803413 Vmddr = 0
526 10:05:20.803478 dram_init: config_dvfs: 1
527 10:05:20.809785 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 10:05:20.813385 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 10:05:20.816713 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 10:05:20.823396 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 10:05:20.826664 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 10:05:20.830144 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 10:05:20.833629 MEM_TYPE=3, freq_sel=18
534 10:05:20.833727 sv_algorithm_assistance_LP4_1600
535 10:05:20.837467 ============ PULL DRAM RESETB DOWN ============
536 10:05:20.845090 ========== PULL DRAM RESETB DOWN end =========
537 10:05:20.848767 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 10:05:20.851740 ===================================
539 10:05:20.854831 LPDDR4 DRAM CONFIGURATION
540 10:05:20.858439 ===================================
541 10:05:20.858525 EX_ROW_EN[0] = 0x0
542 10:05:20.861632 EX_ROW_EN[1] = 0x0
543 10:05:20.861715 LP4Y_EN = 0x0
544 10:05:20.865189 WORK_FSP = 0x0
545 10:05:20.865272 WL = 0x2
546 10:05:20.868599 RL = 0x2
547 10:05:20.868746 BL = 0x2
548 10:05:20.871648 RPST = 0x0
549 10:05:20.871732 RD_PRE = 0x0
550 10:05:20.874832 WR_PRE = 0x1
551 10:05:20.874931 WR_PST = 0x0
552 10:05:20.878381 DBI_WR = 0x0
553 10:05:20.878496 DBI_RD = 0x0
554 10:05:20.881492 OTF = 0x1
555 10:05:20.884766 ===================================
556 10:05:20.888011 ===================================
557 10:05:20.888174 ANA top config
558 10:05:20.891193 ===================================
559 10:05:20.894638 DLL_ASYNC_EN = 0
560 10:05:20.897879 ALL_SLAVE_EN = 1
561 10:05:20.901573 NEW_RANK_MODE = 1
562 10:05:20.901678 DLL_IDLE_MODE = 1
563 10:05:20.904904 LP45_APHY_COMB_EN = 1
564 10:05:20.908352 TX_ODT_DIS = 1
565 10:05:20.911579 NEW_8X_MODE = 1
566 10:05:20.915212 ===================================
567 10:05:20.918493 ===================================
568 10:05:20.921124 data_rate = 1600
569 10:05:20.924815 CKR = 1
570 10:05:20.924919 DQ_P2S_RATIO = 8
571 10:05:20.927869 ===================================
572 10:05:20.931158 CA_P2S_RATIO = 8
573 10:05:20.934620 DQ_CA_OPEN = 0
574 10:05:20.938358 DQ_SEMI_OPEN = 0
575 10:05:20.942190 CA_SEMI_OPEN = 0
576 10:05:20.942428 CA_FULL_RATE = 0
577 10:05:20.945504 DQ_CKDIV4_EN = 1
578 10:05:20.948427 CA_CKDIV4_EN = 1
579 10:05:20.951809 CA_PREDIV_EN = 0
580 10:05:20.955304 PH8_DLY = 0
581 10:05:20.955513 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 10:05:20.958430 DQ_AAMCK_DIV = 4
583 10:05:20.961652 CA_AAMCK_DIV = 4
584 10:05:20.965076 CA_ADMCK_DIV = 4
585 10:05:20.968664 DQ_TRACK_CA_EN = 0
586 10:05:20.971672 CA_PICK = 800
587 10:05:20.975343 CA_MCKIO = 800
588 10:05:20.975774 MCKIO_SEMI = 0
589 10:05:20.978962 PLL_FREQ = 3068
590 10:05:20.982613 DQ_UI_PI_RATIO = 32
591 10:05:20.985753 CA_UI_PI_RATIO = 0
592 10:05:20.989491 ===================================
593 10:05:20.993479 ===================================
594 10:05:20.993910 memory_type:LPDDR4
595 10:05:20.997447 GP_NUM : 10
596 10:05:20.997876 SRAM_EN : 1
597 10:05:21.001065 MD32_EN : 0
598 10:05:21.004718 ===================================
599 10:05:21.005145 [ANA_INIT] >>>>>>>>>>>>>>
600 10:05:21.008764 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 10:05:21.011916 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 10:05:21.015277 ===================================
603 10:05:21.018373 data_rate = 1600,PCW = 0X7600
604 10:05:21.021828 ===================================
605 10:05:21.025268 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 10:05:21.031936 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 10:05:21.035215 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 10:05:21.042311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 10:05:21.045574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 10:05:21.048661 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 10:05:21.049200 [ANA_INIT] flow start
612 10:05:21.052406 [ANA_INIT] PLL >>>>>>>>
613 10:05:21.055394 [ANA_INIT] PLL <<<<<<<<
614 10:05:21.055934 [ANA_INIT] MIDPI >>>>>>>>
615 10:05:21.058442 [ANA_INIT] MIDPI <<<<<<<<
616 10:05:21.061922 [ANA_INIT] DLL >>>>>>>>
617 10:05:21.062511 [ANA_INIT] flow end
618 10:05:21.068405 ============ LP4 DIFF to SE enter ============
619 10:05:21.072007 ============ LP4 DIFF to SE exit ============
620 10:05:21.075165 [ANA_INIT] <<<<<<<<<<<<<
621 10:05:21.078666 [Flow] Enable top DCM control >>>>>
622 10:05:21.083083 [Flow] Enable top DCM control <<<<<
623 10:05:21.083522 Enable DLL master slave shuffle
624 10:05:21.088092 ==============================================================
625 10:05:21.091805 Gating Mode config
626 10:05:21.094643 ==============================================================
627 10:05:21.098154 Config description:
628 10:05:21.107936 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 10:05:21.114681 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 10:05:21.118052 SELPH_MODE 0: By rank 1: By Phase
631 10:05:21.154737 ==============================================================
632 10:05:21.155281 GAT_TRACK_EN = 1
633 10:05:21.155635 RX_GATING_MODE = 2
634 10:05:21.155960 RX_GATING_TRACK_MODE = 2
635 10:05:21.156349 SELPH_MODE = 1
636 10:05:21.156662 PICG_EARLY_EN = 1
637 10:05:21.156962 VALID_LAT_VALUE = 1
638 10:05:21.157256 ==============================================================
639 10:05:21.157557 Enter into Gating configuration >>>>
640 10:05:21.158298 Exit from Gating configuration <<<<
641 10:05:21.158632 Enter into DVFS_PRE_config >>>>>
642 10:05:21.168306 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 10:05:21.171905 Exit from DVFS_PRE_config <<<<<
644 10:05:21.174754 Enter into PICG configuration >>>>
645 10:05:21.177664 Exit from PICG configuration <<<<
646 10:05:21.181117 [RX_INPUT] configuration >>>>>
647 10:05:21.184812 [RX_INPUT] configuration <<<<<
648 10:05:21.187806 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 10:05:21.194529 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 10:05:21.201150 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 10:05:21.207895 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 10:05:21.214468 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 10:05:21.217578 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 10:05:21.224907 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 10:05:21.227649 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 10:05:21.230705 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 10:05:21.234077 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 10:05:21.240468 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 10:05:21.244702 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 10:05:21.247548 ===================================
661 10:05:21.250763 LPDDR4 DRAM CONFIGURATION
662 10:05:21.254079 ===================================
663 10:05:21.254215 EX_ROW_EN[0] = 0x0
664 10:05:21.257380 EX_ROW_EN[1] = 0x0
665 10:05:21.257512 LP4Y_EN = 0x0
666 10:05:21.260806 WORK_FSP = 0x0
667 10:05:21.260937 WL = 0x2
668 10:05:21.264124 RL = 0x2
669 10:05:21.264291 BL = 0x2
670 10:05:21.267229 RPST = 0x0
671 10:05:21.267423 RD_PRE = 0x0
672 10:05:21.270468 WR_PRE = 0x1
673 10:05:21.274069 WR_PST = 0x0
674 10:05:21.274152 DBI_WR = 0x0
675 10:05:21.277042 DBI_RD = 0x0
676 10:05:21.277114 OTF = 0x1
677 10:05:21.280353 ===================================
678 10:05:21.283925 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 10:05:21.286859 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 10:05:21.294091 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 10:05:21.296897 ===================================
682 10:05:21.300546 LPDDR4 DRAM CONFIGURATION
683 10:05:21.303471 ===================================
684 10:05:21.303582 EX_ROW_EN[0] = 0x10
685 10:05:21.307249 EX_ROW_EN[1] = 0x0
686 10:05:21.307379 LP4Y_EN = 0x0
687 10:05:21.310117 WORK_FSP = 0x0
688 10:05:21.310245 WL = 0x2
689 10:05:21.313796 RL = 0x2
690 10:05:21.313943 BL = 0x2
691 10:05:21.316985 RPST = 0x0
692 10:05:21.317096 RD_PRE = 0x0
693 10:05:21.320581 WR_PRE = 0x1
694 10:05:21.320687 WR_PST = 0x0
695 10:05:21.323473 DBI_WR = 0x0
696 10:05:21.323592 DBI_RD = 0x0
697 10:05:21.326710 OTF = 0x1
698 10:05:21.330040 ===================================
699 10:05:21.337112 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 10:05:21.340428 nWR fixed to 40
701 10:05:21.343635 [ModeRegInit_LP4] CH0 RK0
702 10:05:21.343787 [ModeRegInit_LP4] CH0 RK1
703 10:05:21.346981 [ModeRegInit_LP4] CH1 RK0
704 10:05:21.349919 [ModeRegInit_LP4] CH1 RK1
705 10:05:21.350032 match AC timing 13
706 10:05:21.356437 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 10:05:21.359854 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 10:05:21.363358 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 10:05:21.370272 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 10:05:21.373108 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 10:05:21.376835 [EMI DOE] emi_dcm 0
712 10:05:21.379656 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 10:05:21.379741 ==
714 10:05:21.383055 Dram Type= 6, Freq= 0, CH_0, rank 0
715 10:05:21.386312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 10:05:21.386405 ==
717 10:05:21.393209 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 10:05:21.399463 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 10:05:21.408149 [CA 0] Center 37 (7~68) winsize 62
720 10:05:21.411444 [CA 1] Center 37 (7~68) winsize 62
721 10:05:21.414309 [CA 2] Center 34 (4~65) winsize 62
722 10:05:21.417758 [CA 3] Center 35 (4~66) winsize 63
723 10:05:21.421234 [CA 4] Center 33 (3~64) winsize 62
724 10:05:21.424475 [CA 5] Center 33 (3~64) winsize 62
725 10:05:21.424662
726 10:05:21.427578 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 10:05:21.427796
728 10:05:21.431532 [CATrainingPosCal] consider 1 rank data
729 10:05:21.434918 u2DelayCellTimex100 = 270/100 ps
730 10:05:21.438213 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 10:05:21.444547 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 10:05:21.447902 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 10:05:21.451351 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
734 10:05:21.454803 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 10:05:21.457590 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 10:05:21.458037
737 10:05:21.461039 CA PerBit enable=1, Macro0, CA PI delay=33
738 10:05:21.461471
739 10:05:21.464325 [CBTSetCACLKResult] CA Dly = 33
740 10:05:21.464752 CS Dly: 6 (0~37)
741 10:05:21.467623 ==
742 10:05:21.470774 Dram Type= 6, Freq= 0, CH_0, rank 1
743 10:05:21.473969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 10:05:21.474054 ==
745 10:05:21.477481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 10:05:21.483757 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 10:05:21.493967 [CA 0] Center 38 (7~69) winsize 63
748 10:05:21.497533 [CA 1] Center 37 (7~68) winsize 62
749 10:05:21.500895 [CA 2] Center 35 (4~66) winsize 63
750 10:05:21.504185 [CA 3] Center 35 (4~66) winsize 63
751 10:05:21.507565 [CA 4] Center 34 (3~65) winsize 63
752 10:05:21.510441 [CA 5] Center 33 (3~64) winsize 62
753 10:05:21.510602
754 10:05:21.513846 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 10:05:21.513952
756 10:05:21.517210 [CATrainingPosCal] consider 2 rank data
757 10:05:21.520407 u2DelayCellTimex100 = 270/100 ps
758 10:05:21.524018 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 10:05:21.526871 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 10:05:21.534079 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 10:05:21.538012 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
762 10:05:21.540526 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 10:05:21.544156 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 10:05:21.544301
765 10:05:21.547266 CA PerBit enable=1, Macro0, CA PI delay=33
766 10:05:21.547367
767 10:05:21.550593 [CBTSetCACLKResult] CA Dly = 33
768 10:05:21.550747 CS Dly: 6 (0~38)
769 10:05:21.554011
770 10:05:21.557588 ----->DramcWriteLeveling(PI) begin...
771 10:05:21.557737 ==
772 10:05:21.561229 Dram Type= 6, Freq= 0, CH_0, rank 0
773 10:05:21.564797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 10:05:21.564961 ==
775 10:05:21.568416 Write leveling (Byte 0): 30 => 30
776 10:05:21.568582 Write leveling (Byte 1): 27 => 27
777 10:05:21.571987 DramcWriteLeveling(PI) end<-----
778 10:05:21.572147
779 10:05:21.572253 ==
780 10:05:21.575325 Dram Type= 6, Freq= 0, CH_0, rank 0
781 10:05:21.581502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 10:05:21.581667 ==
783 10:05:21.581745 [Gating] SW mode calibration
784 10:05:21.592306 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 10:05:21.595822 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 10:05:21.599202 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 10:05:21.605523 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 10:05:21.609275 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 10:05:21.612542 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 10:05:21.619154 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 10:05:21.622322 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 10:05:21.625617 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 10:05:21.631991 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 10:05:21.635322 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 10:05:21.639113 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 10:05:21.642404 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 10:05:21.649102 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 10:05:21.652463 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 10:05:21.655288 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 10:05:21.662716 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 10:05:21.665716 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 10:05:21.668921 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 10:05:21.675917 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 10:05:21.678786 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 10:05:21.682313 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 10:05:21.689281 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 10:05:21.692198 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 10:05:21.695288 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 10:05:21.702573 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 10:05:21.705273 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 10:05:21.708667 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 10:05:21.715875 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
813 10:05:21.719262 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
814 10:05:21.722340 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 10:05:21.729283 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 10:05:21.732137 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 10:05:21.735722 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 10:05:21.742006 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 10:05:21.745356 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
820 10:05:21.748872 0 10 8 | B1->B0 | 3232 2424 | 0 0 | (1 0) (0 0)
821 10:05:21.755651 0 10 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
822 10:05:21.758577 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 10:05:21.761777 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 10:05:21.768842 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 10:05:21.771920 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 10:05:21.775417 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 10:05:21.781943 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
828 10:05:21.785025 0 11 8 | B1->B0 | 2e2e 4545 | 1 1 | (0 0) (0 0)
829 10:05:21.788470 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
830 10:05:21.795454 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 10:05:21.798960 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 10:05:21.801973 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 10:05:21.805329 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 10:05:21.812440 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 10:05:21.815583 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 10:05:21.818610 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 10:05:21.825261 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 10:05:21.828659 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 10:05:21.832142 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 10:05:21.838537 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 10:05:21.841813 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 10:05:21.845141 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 10:05:21.852257 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 10:05:21.855323 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 10:05:21.858974 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 10:05:21.865400 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 10:05:21.868382 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 10:05:21.872165 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 10:05:21.878818 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 10:05:21.881472 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 10:05:21.885247 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 10:05:21.892143 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 10:05:21.892578 Total UI for P1: 0, mck2ui 16
854 10:05:21.898467 best dqsien dly found for B0: ( 0, 14, 2)
855 10:05:21.901472 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 10:05:21.905034 Total UI for P1: 0, mck2ui 16
857 10:05:21.908453 best dqsien dly found for B1: ( 0, 14, 8)
858 10:05:21.911705 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
859 10:05:21.914656 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 10:05:21.914960
861 10:05:21.918608 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
862 10:05:21.921212 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 10:05:21.924484 [Gating] SW calibration Done
864 10:05:21.924669 ==
865 10:05:21.927716 Dram Type= 6, Freq= 0, CH_0, rank 0
866 10:05:21.931217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 10:05:21.931359 ==
868 10:05:21.934644 RX Vref Scan: 0
869 10:05:21.934855
870 10:05:21.938959 RX Vref 0 -> 0, step: 1
871 10:05:21.939089
872 10:05:21.939213 RX Delay -130 -> 252, step: 16
873 10:05:21.942067 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
874 10:05:21.949055 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 10:05:21.952316 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 10:05:21.955474 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 10:05:21.959072 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 10:05:21.962576 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 10:05:21.965745 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 10:05:21.972292 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 10:05:21.975532 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 10:05:21.979211 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
883 10:05:21.982344 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 10:05:21.985926 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 10:05:21.992407 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 10:05:21.995550 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 10:05:21.999387 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 10:05:22.003024 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 10:05:22.003455 ==
890 10:05:22.006207 Dram Type= 6, Freq= 0, CH_0, rank 0
891 10:05:22.012665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 10:05:22.013242 ==
893 10:05:22.013619 DQS Delay:
894 10:05:22.015745 DQS0 = 0, DQS1 = 0
895 10:05:22.016390 DQM Delay:
896 10:05:22.019174 DQM0 = 90, DQM1 = 76
897 10:05:22.019678 DQ Delay:
898 10:05:22.022406 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
899 10:05:22.026109 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
900 10:05:22.029051 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
901 10:05:22.032727 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 10:05:22.033290
903 10:05:22.033666
904 10:05:22.034011 ==
905 10:05:22.035441 Dram Type= 6, Freq= 0, CH_0, rank 0
906 10:05:22.039475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 10:05:22.040149 ==
908 10:05:22.040543
909 10:05:22.040896
910 10:05:22.042282 TX Vref Scan disable
911 10:05:22.045577 == TX Byte 0 ==
912 10:05:22.049006 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 10:05:22.052424 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 10:05:22.055427 == TX Byte 1 ==
915 10:05:22.059110 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
916 10:05:22.062413 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
917 10:05:22.062954 ==
918 10:05:22.065364 Dram Type= 6, Freq= 0, CH_0, rank 0
919 10:05:22.068792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 10:05:22.072078 ==
921 10:05:22.083568 TX Vref=22, minBit 1, minWin=27, winSum=440
922 10:05:22.086914 TX Vref=24, minBit 0, minWin=27, winSum=439
923 10:05:22.090708 TX Vref=26, minBit 0, minWin=27, winSum=444
924 10:05:22.093538 TX Vref=28, minBit 3, minWin=27, winSum=447
925 10:05:22.096624 TX Vref=30, minBit 2, minWin=27, winSum=450
926 10:05:22.103557 TX Vref=32, minBit 0, minWin=28, winSum=451
927 10:05:22.106823 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
928 10:05:22.107351
929 10:05:22.110280 Final TX Range 1 Vref 32
930 10:05:22.110807
931 10:05:22.111151 ==
932 10:05:22.112969 Dram Type= 6, Freq= 0, CH_0, rank 0
933 10:05:22.119846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 10:05:22.120502 ==
935 10:05:22.120872
936 10:05:22.121198
937 10:05:22.121504 TX Vref Scan disable
938 10:05:22.124281 == TX Byte 0 ==
939 10:05:22.127104 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 10:05:22.133836 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 10:05:22.134411 == TX Byte 1 ==
942 10:05:22.137146 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
943 10:05:22.143742 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
944 10:05:22.144378
945 10:05:22.144860 [DATLAT]
946 10:05:22.145397 Freq=800, CH0 RK0
947 10:05:22.146011
948 10:05:22.146948 DATLAT Default: 0xa
949 10:05:22.147557 0, 0xFFFF, sum = 0
950 10:05:22.150199 1, 0xFFFF, sum = 0
951 10:05:22.153378 2, 0xFFFF, sum = 0
952 10:05:22.153811 3, 0xFFFF, sum = 0
953 10:05:22.156971 4, 0xFFFF, sum = 0
954 10:05:22.157405 5, 0xFFFF, sum = 0
955 10:05:22.160340 6, 0xFFFF, sum = 0
956 10:05:22.160776 7, 0xFFFF, sum = 0
957 10:05:22.163370 8, 0xFFFF, sum = 0
958 10:05:22.163971 9, 0x0, sum = 1
959 10:05:22.167148 10, 0x0, sum = 2
960 10:05:22.167718 11, 0x0, sum = 3
961 10:05:22.168143 12, 0x0, sum = 4
962 10:05:22.169988 best_step = 10
963 10:05:22.170434
964 10:05:22.170779 ==
965 10:05:22.172998 Dram Type= 6, Freq= 0, CH_0, rank 0
966 10:05:22.176292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 10:05:22.176727 ==
968 10:05:22.179723 RX Vref Scan: 1
969 10:05:22.180215
970 10:05:22.183265 Set Vref Range= 32 -> 127
971 10:05:22.183841
972 10:05:22.184287 RX Vref 32 -> 127, step: 1
973 10:05:22.184624
974 10:05:22.186362 RX Delay -111 -> 252, step: 8
975 10:05:22.186789
976 10:05:22.189843 Set Vref, RX VrefLevel [Byte0]: 32
977 10:05:22.192669 [Byte1]: 32
978 10:05:22.196315
979 10:05:22.196886 Set Vref, RX VrefLevel [Byte0]: 33
980 10:05:22.199517 [Byte1]: 33
981 10:05:22.204681
982 10:05:22.205205 Set Vref, RX VrefLevel [Byte0]: 34
983 10:05:22.207533 [Byte1]: 34
984 10:05:22.211943
985 10:05:22.212570 Set Vref, RX VrefLevel [Byte0]: 35
986 10:05:22.215188 [Byte1]: 35
987 10:05:22.219137
988 10:05:22.219556 Set Vref, RX VrefLevel [Byte0]: 36
989 10:05:22.222437 [Byte1]: 36
990 10:05:22.226844
991 10:05:22.227383 Set Vref, RX VrefLevel [Byte0]: 37
992 10:05:22.230308 [Byte1]: 37
993 10:05:22.235316
994 10:05:22.235905 Set Vref, RX VrefLevel [Byte0]: 38
995 10:05:22.238479 [Byte1]: 38
996 10:05:22.242012
997 10:05:22.245573 Set Vref, RX VrefLevel [Byte0]: 39
998 10:05:22.246059 [Byte1]: 39
999 10:05:22.250064
1000 10:05:22.250542 Set Vref, RX VrefLevel [Byte0]: 40
1001 10:05:22.253279 [Byte1]: 40
1002 10:05:22.257993
1003 10:05:22.258513 Set Vref, RX VrefLevel [Byte0]: 41
1004 10:05:22.261323 [Byte1]: 41
1005 10:05:22.265179
1006 10:05:22.265608 Set Vref, RX VrefLevel [Byte0]: 42
1007 10:05:22.268813 [Byte1]: 42
1008 10:05:22.272740
1009 10:05:22.273170 Set Vref, RX VrefLevel [Byte0]: 43
1010 10:05:22.276429 [Byte1]: 43
1011 10:05:22.280260
1012 10:05:22.280689 Set Vref, RX VrefLevel [Byte0]: 44
1013 10:05:22.284167 [Byte1]: 44
1014 10:05:22.288173
1015 10:05:22.288600 Set Vref, RX VrefLevel [Byte0]: 45
1016 10:05:22.291134 [Byte1]: 45
1017 10:05:22.295986
1018 10:05:22.296656 Set Vref, RX VrefLevel [Byte0]: 46
1019 10:05:22.298891 [Byte1]: 46
1020 10:05:22.303510
1021 10:05:22.303939 Set Vref, RX VrefLevel [Byte0]: 47
1022 10:05:22.306643 [Byte1]: 47
1023 10:05:22.311208
1024 10:05:22.311728 Set Vref, RX VrefLevel [Byte0]: 48
1025 10:05:22.314277 [Byte1]: 48
1026 10:05:22.319033
1027 10:05:22.319448 Set Vref, RX VrefLevel [Byte0]: 49
1028 10:05:22.322188 [Byte1]: 49
1029 10:05:22.326742
1030 10:05:22.327255 Set Vref, RX VrefLevel [Byte0]: 50
1031 10:05:22.329775 [Byte1]: 50
1032 10:05:22.334198
1033 10:05:22.334710 Set Vref, RX VrefLevel [Byte0]: 51
1034 10:05:22.337248 [Byte1]: 51
1035 10:05:22.341992
1036 10:05:22.342505 Set Vref, RX VrefLevel [Byte0]: 52
1037 10:05:22.344740 [Byte1]: 52
1038 10:05:22.349266
1039 10:05:22.349744 Set Vref, RX VrefLevel [Byte0]: 53
1040 10:05:22.352252 [Byte1]: 53
1041 10:05:22.356836
1042 10:05:22.357249 Set Vref, RX VrefLevel [Byte0]: 54
1043 10:05:22.359819 [Byte1]: 54
1044 10:05:22.364457
1045 10:05:22.364871 Set Vref, RX VrefLevel [Byte0]: 55
1046 10:05:22.367708 [Byte1]: 55
1047 10:05:22.372216
1048 10:05:22.372629 Set Vref, RX VrefLevel [Byte0]: 56
1049 10:05:22.375280 [Byte1]: 56
1050 10:05:22.379647
1051 10:05:22.380094 Set Vref, RX VrefLevel [Byte0]: 57
1052 10:05:22.383304 [Byte1]: 57
1053 10:05:22.387880
1054 10:05:22.388429 Set Vref, RX VrefLevel [Byte0]: 58
1055 10:05:22.390941 [Byte1]: 58
1056 10:05:22.394905
1057 10:05:22.395322 Set Vref, RX VrefLevel [Byte0]: 59
1058 10:05:22.398498 [Byte1]: 59
1059 10:05:22.403033
1060 10:05:22.403545 Set Vref, RX VrefLevel [Byte0]: 60
1061 10:05:22.406721 [Byte1]: 60
1062 10:05:22.411130
1063 10:05:22.411649 Set Vref, RX VrefLevel [Byte0]: 61
1064 10:05:22.413731 [Byte1]: 61
1065 10:05:22.418129
1066 10:05:22.418569 Set Vref, RX VrefLevel [Byte0]: 62
1067 10:05:22.421316 [Byte1]: 62
1068 10:05:22.425660
1069 10:05:22.426071 Set Vref, RX VrefLevel [Byte0]: 63
1070 10:05:22.428676 [Byte1]: 63
1071 10:05:22.433247
1072 10:05:22.433760 Set Vref, RX VrefLevel [Byte0]: 64
1073 10:05:22.436566 [Byte1]: 64
1074 10:05:22.440927
1075 10:05:22.441340 Set Vref, RX VrefLevel [Byte0]: 65
1076 10:05:22.444249 [Byte1]: 65
1077 10:05:22.449310
1078 10:05:22.449833 Set Vref, RX VrefLevel [Byte0]: 66
1079 10:05:22.452297 [Byte1]: 66
1080 10:05:22.456768
1081 10:05:22.457279 Set Vref, RX VrefLevel [Byte0]: 67
1082 10:05:22.460201 [Byte1]: 67
1083 10:05:22.464265
1084 10:05:22.464777 Set Vref, RX VrefLevel [Byte0]: 68
1085 10:05:22.467681 [Byte1]: 68
1086 10:05:22.471508
1087 10:05:22.472099 Set Vref, RX VrefLevel [Byte0]: 69
1088 10:05:22.475073 [Byte1]: 69
1089 10:05:22.479631
1090 10:05:22.480271 Set Vref, RX VrefLevel [Byte0]: 70
1091 10:05:22.482444 [Byte1]: 70
1092 10:05:22.486974
1093 10:05:22.487503 Set Vref, RX VrefLevel [Byte0]: 71
1094 10:05:22.490250 [Byte1]: 71
1095 10:05:22.494959
1096 10:05:22.495474 Set Vref, RX VrefLevel [Byte0]: 72
1097 10:05:22.497514 [Byte1]: 72
1098 10:05:22.502444
1099 10:05:22.502968 Set Vref, RX VrefLevel [Byte0]: 73
1100 10:05:22.505909 [Byte1]: 73
1101 10:05:22.509907
1102 10:05:22.510327 Set Vref, RX VrefLevel [Byte0]: 74
1103 10:05:22.513221 [Byte1]: 74
1104 10:05:22.517592
1105 10:05:22.518108 Final RX Vref Byte 0 = 56 to rank0
1106 10:05:22.520929 Final RX Vref Byte 1 = 60 to rank0
1107 10:05:22.523996 Final RX Vref Byte 0 = 56 to rank1
1108 10:05:22.527347 Final RX Vref Byte 1 = 60 to rank1==
1109 10:05:22.530748 Dram Type= 6, Freq= 0, CH_0, rank 0
1110 10:05:22.537090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1111 10:05:22.537604 ==
1112 10:05:22.537945 DQS Delay:
1113 10:05:22.540886 DQS0 = 0, DQS1 = 0
1114 10:05:22.541413 DQM Delay:
1115 10:05:22.541865 DQM0 = 88, DQM1 = 76
1116 10:05:22.544500 DQ Delay:
1117 10:05:22.547313 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1118 10:05:22.550751 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1119 10:05:22.554108 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1120 10:05:22.557161 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1121 10:05:22.557679
1122 10:05:22.558014
1123 10:05:22.564264 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
1124 10:05:22.567664 CH0 RK0: MR19=606, MR18=2D26
1125 10:05:22.574497 CH0_RK0: MR19=0x606, MR18=0x2D26, DQSOSC=398, MR23=63, INC=93, DEC=62
1126 10:05:22.575059
1127 10:05:22.576961 ----->DramcWriteLeveling(PI) begin...
1128 10:05:22.577425 ==
1129 10:05:22.580778 Dram Type= 6, Freq= 0, CH_0, rank 1
1130 10:05:22.583712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1131 10:05:22.584213 ==
1132 10:05:22.587600 Write leveling (Byte 0): 32 => 32
1133 10:05:22.590658 Write leveling (Byte 1): 28 => 28
1134 10:05:22.593844 DramcWriteLeveling(PI) end<-----
1135 10:05:22.594568
1136 10:05:22.594949 ==
1137 10:05:22.597155 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 10:05:22.600481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 10:05:22.601003 ==
1140 10:05:22.603963 [Gating] SW mode calibration
1141 10:05:22.610134 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1142 10:05:22.616833 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1143 10:05:22.620404 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1144 10:05:22.664445 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1145 10:05:22.665012 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1146 10:05:22.665387 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 10:05:22.666079 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 10:05:22.666440 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 10:05:22.666772 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 10:05:22.667089 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 10:05:22.667398 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 10:05:22.667708 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 10:05:22.668019 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 10:05:22.708243 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 10:05:22.708805 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 10:05:22.709499 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 10:05:22.709870 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 10:05:22.710265 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 10:05:22.710659 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1160 10:05:22.711378 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1161 10:05:22.711795 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1162 10:05:22.712163 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 10:05:22.712541 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 10:05:22.728762 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 10:05:22.729671 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 10:05:22.730066 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 10:05:22.730416 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 10:05:22.732209 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1169 10:05:22.735325 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
1170 10:05:22.738793 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 10:05:22.745127 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 10:05:22.748703 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 10:05:22.752144 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 10:05:22.758501 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 10:05:22.762108 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 10:05:22.765602 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1177 10:05:22.771820 0 10 8 | B1->B0 | 3131 2626 | 1 0 | (1 0) (1 0)
1178 10:05:22.774900 0 10 12 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
1179 10:05:22.779014 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 10:05:22.785069 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 10:05:22.788593 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 10:05:22.791751 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 10:05:22.798098 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 10:05:22.802243 0 11 4 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
1185 10:05:22.805077 0 11 8 | B1->B0 | 3434 4545 | 0 0 | (0 0) (0 0)
1186 10:05:22.809042 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1187 10:05:22.816348 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 10:05:22.819543 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 10:05:22.822968 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 10:05:22.826211 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 10:05:22.833184 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 10:05:22.837030 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1193 10:05:22.839912 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1194 10:05:22.842809 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 10:05:22.849546 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 10:05:22.852764 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 10:05:22.856427 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 10:05:22.863079 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 10:05:22.866710 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 10:05:22.869845 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 10:05:22.876105 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 10:05:22.879545 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 10:05:22.882939 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 10:05:22.889631 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 10:05:22.893200 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 10:05:22.896010 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 10:05:22.903278 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 10:05:22.906219 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1209 10:05:22.909863 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1210 10:05:22.913287 Total UI for P1: 0, mck2ui 16
1211 10:05:22.916134 best dqsien dly found for B0: ( 0, 14, 4)
1212 10:05:22.923009 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 10:05:22.923431 Total UI for P1: 0, mck2ui 16
1214 10:05:22.929907 best dqsien dly found for B1: ( 0, 14, 8)
1215 10:05:22.932909 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1216 10:05:22.936201 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1217 10:05:22.936622
1218 10:05:22.939893 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1219 10:05:22.942572 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1220 10:05:22.946203 [Gating] SW calibration Done
1221 10:05:22.946659 ==
1222 10:05:22.949362 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 10:05:22.952489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1224 10:05:22.953044 ==
1225 10:05:22.955903 RX Vref Scan: 0
1226 10:05:22.956395
1227 10:05:22.956732 RX Vref 0 -> 0, step: 1
1228 10:05:22.957042
1229 10:05:22.959560 RX Delay -130 -> 252, step: 16
1230 10:05:22.962544 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1231 10:05:22.969339 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1232 10:05:22.972331 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1233 10:05:22.975913 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1234 10:05:22.979613 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1235 10:05:22.982817 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1236 10:05:22.989244 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1237 10:05:22.992307 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1238 10:05:22.995929 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1239 10:05:22.999493 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1240 10:05:23.002410 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1241 10:05:23.009207 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1242 10:05:23.012609 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1243 10:05:23.015801 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1244 10:05:23.018967 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1245 10:05:23.026095 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1246 10:05:23.026617 ==
1247 10:05:23.029112 Dram Type= 6, Freq= 0, CH_0, rank 1
1248 10:05:23.032160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1249 10:05:23.032588 ==
1250 10:05:23.032929 DQS Delay:
1251 10:05:23.035791 DQS0 = 0, DQS1 = 0
1252 10:05:23.036363 DQM Delay:
1253 10:05:23.039132 DQM0 = 86, DQM1 = 74
1254 10:05:23.039649 DQ Delay:
1255 10:05:23.042233 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1256 10:05:23.045304 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1257 10:05:23.048962 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
1258 10:05:23.052560 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1259 10:05:23.053115
1260 10:05:23.053451
1261 10:05:23.053764 ==
1262 10:05:23.055666 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 10:05:23.058639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 10:05:23.059100 ==
1265 10:05:23.061640
1266 10:05:23.062111
1267 10:05:23.062451 TX Vref Scan disable
1268 10:05:23.065411 == TX Byte 0 ==
1269 10:05:23.068491 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1270 10:05:23.071915 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1271 10:05:23.075316 == TX Byte 1 ==
1272 10:05:23.078860 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1273 10:05:23.081811 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1274 10:05:23.082242 ==
1275 10:05:23.085228 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 10:05:23.091925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 10:05:23.092533 ==
1278 10:05:23.104671 TX Vref=22, minBit 2, minWin=27, winSum=442
1279 10:05:23.107689 TX Vref=24, minBit 1, minWin=27, winSum=447
1280 10:05:23.111500 TX Vref=26, minBit 1, minWin=27, winSum=446
1281 10:05:23.113976 TX Vref=28, minBit 1, minWin=27, winSum=449
1282 10:05:23.117499 TX Vref=30, minBit 0, minWin=28, winSum=452
1283 10:05:23.120741 TX Vref=32, minBit 1, minWin=27, winSum=448
1284 10:05:23.127177 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 30
1285 10:05:23.127596
1286 10:05:23.130922 Final TX Range 1 Vref 30
1287 10:05:23.131444
1288 10:05:23.131776 ==
1289 10:05:23.133753 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 10:05:23.137460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 10:05:23.137980 ==
1292 10:05:23.140550
1293 10:05:23.140954
1294 10:05:23.141269 TX Vref Scan disable
1295 10:05:23.143892 == TX Byte 0 ==
1296 10:05:23.147048 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1297 10:05:23.153823 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1298 10:05:23.154230 == TX Byte 1 ==
1299 10:05:23.157308 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1300 10:05:23.163976 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1301 10:05:23.164414
1302 10:05:23.164734 [DATLAT]
1303 10:05:23.165029 Freq=800, CH0 RK1
1304 10:05:23.165314
1305 10:05:23.167659 DATLAT Default: 0xa
1306 10:05:23.168387 0, 0xFFFF, sum = 0
1307 10:05:23.170896 1, 0xFFFF, sum = 0
1308 10:05:23.171409 2, 0xFFFF, sum = 0
1309 10:05:23.173812 3, 0xFFFF, sum = 0
1310 10:05:23.177071 4, 0xFFFF, sum = 0
1311 10:05:23.177486 5, 0xFFFF, sum = 0
1312 10:05:23.181049 6, 0xFFFF, sum = 0
1313 10:05:23.181463 7, 0xFFFF, sum = 0
1314 10:05:23.183791 8, 0xFFFF, sum = 0
1315 10:05:23.184233 9, 0x0, sum = 1
1316 10:05:23.186803 10, 0x0, sum = 2
1317 10:05:23.187219 11, 0x0, sum = 3
1318 10:05:23.187548 12, 0x0, sum = 4
1319 10:05:23.190476 best_step = 10
1320 10:05:23.191040
1321 10:05:23.191369 ==
1322 10:05:23.194246 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 10:05:23.196928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 10:05:23.197344 ==
1325 10:05:23.200332 RX Vref Scan: 0
1326 10:05:23.200740
1327 10:05:23.201059 RX Vref 0 -> 0, step: 1
1328 10:05:23.204181
1329 10:05:23.204687 RX Delay -111 -> 252, step: 8
1330 10:05:23.210689 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1331 10:05:23.214443 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1332 10:05:23.217505 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1333 10:05:23.220777 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1334 10:05:23.223949 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1335 10:05:23.230906 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1336 10:05:23.234013 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1337 10:05:23.237389 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1338 10:05:23.240675 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1339 10:05:23.244132 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1340 10:05:23.250621 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1341 10:05:23.254366 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1342 10:05:23.256981 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1343 10:05:23.260993 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1344 10:05:23.267593 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1345 10:05:23.270813 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1346 10:05:23.271337 ==
1347 10:05:23.273572 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 10:05:23.277525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 10:05:23.278037 ==
1350 10:05:23.278360 DQS Delay:
1351 10:05:23.280557 DQS0 = 0, DQS1 = 0
1352 10:05:23.281015 DQM Delay:
1353 10:05:23.283569 DQM0 = 86, DQM1 = 77
1354 10:05:23.283974 DQ Delay:
1355 10:05:23.286833 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1356 10:05:23.290642 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1357 10:05:23.294026 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1358 10:05:23.297063 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1359 10:05:23.297571
1360 10:05:23.297894
1361 10:05:23.307242 [DQSOSCAuto] RK1, (LSB)MR18= 0x2421, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1362 10:05:23.307753 CH0 RK1: MR19=606, MR18=2421
1363 10:05:23.313527 CH0_RK1: MR19=0x606, MR18=0x2421, DQSOSC=400, MR23=63, INC=92, DEC=61
1364 10:05:23.317396 [RxdqsGatingPostProcess] freq 800
1365 10:05:23.323471 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1366 10:05:23.327081 Pre-setting of DQS Precalculation
1367 10:05:23.330482 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1368 10:05:23.330990 ==
1369 10:05:23.333442 Dram Type= 6, Freq= 0, CH_1, rank 0
1370 10:05:23.339728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 10:05:23.340274 ==
1372 10:05:23.343238 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1373 10:05:23.349919 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1374 10:05:23.359228 [CA 0] Center 36 (6~67) winsize 62
1375 10:05:23.362384 [CA 1] Center 37 (6~68) winsize 63
1376 10:05:23.366061 [CA 2] Center 35 (5~65) winsize 61
1377 10:05:23.369319 [CA 3] Center 34 (4~65) winsize 62
1378 10:05:23.372647 [CA 4] Center 34 (4~65) winsize 62
1379 10:05:23.375401 [CA 5] Center 33 (3~64) winsize 62
1380 10:05:23.375802
1381 10:05:23.379382 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1382 10:05:23.379884
1383 10:05:23.382128 [CATrainingPosCal] consider 1 rank data
1384 10:05:23.385664 u2DelayCellTimex100 = 270/100 ps
1385 10:05:23.388987 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1386 10:05:23.395557 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1387 10:05:23.398602 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1388 10:05:23.402363 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1389 10:05:23.406024 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1390 10:05:23.409325 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1391 10:05:23.409846
1392 10:05:23.412620 CA PerBit enable=1, Macro0, CA PI delay=33
1393 10:05:23.413136
1394 10:05:23.415775 [CBTSetCACLKResult] CA Dly = 33
1395 10:05:23.416348 CS Dly: 4 (0~35)
1396 10:05:23.418673 ==
1397 10:05:23.422117 Dram Type= 6, Freq= 0, CH_1, rank 1
1398 10:05:23.425437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 10:05:23.425858 ==
1400 10:05:23.428712 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1401 10:05:23.435502 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1402 10:05:23.445924 [CA 0] Center 36 (6~67) winsize 62
1403 10:05:23.449167 [CA 1] Center 36 (6~67) winsize 62
1404 10:05:23.452687 [CA 2] Center 34 (4~65) winsize 62
1405 10:05:23.455402 [CA 3] Center 34 (3~65) winsize 63
1406 10:05:23.458729 [CA 4] Center 34 (4~65) winsize 62
1407 10:05:23.461936 [CA 5] Center 33 (3~64) winsize 62
1408 10:05:23.462351
1409 10:05:23.465674 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1410 10:05:23.466202
1411 10:05:23.468740 [CATrainingPosCal] consider 2 rank data
1412 10:05:23.472418 u2DelayCellTimex100 = 270/100 ps
1413 10:05:23.476008 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1414 10:05:23.479840 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1415 10:05:23.483117 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1416 10:05:23.486583 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1417 10:05:23.490251 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1418 10:05:23.493763 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1419 10:05:23.494179
1420 10:05:23.497466 CA PerBit enable=1, Macro0, CA PI delay=33
1421 10:05:23.497879
1422 10:05:23.501625 [CBTSetCACLKResult] CA Dly = 33
1423 10:05:23.505238 CS Dly: 5 (0~38)
1424 10:05:23.505675
1425 10:05:23.506006 ----->DramcWriteLeveling(PI) begin...
1426 10:05:23.509009 ==
1427 10:05:23.512408 Dram Type= 6, Freq= 0, CH_1, rank 0
1428 10:05:23.515555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 10:05:23.516101 ==
1430 10:05:23.519155 Write leveling (Byte 0): 26 => 26
1431 10:05:23.521907 Write leveling (Byte 1): 28 => 28
1432 10:05:23.525430 DramcWriteLeveling(PI) end<-----
1433 10:05:23.525847
1434 10:05:23.526173 ==
1435 10:05:23.528407 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 10:05:23.532162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 10:05:23.532583 ==
1438 10:05:23.535361 [Gating] SW mode calibration
1439 10:05:23.542559 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1440 10:05:23.545092 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1441 10:05:23.552471 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1442 10:05:23.555327 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1443 10:05:23.559196 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1444 10:05:23.565533 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 10:05:23.568722 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 10:05:23.571764 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 10:05:23.578701 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 10:05:23.581639 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 10:05:23.585538 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 10:05:23.591886 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 10:05:23.595253 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 10:05:23.598723 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 10:05:23.604998 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 10:05:23.608512 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 10:05:23.611587 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 10:05:23.618525 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 10:05:23.621450 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 10:05:23.624610 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1459 10:05:23.631687 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 10:05:23.634772 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 10:05:23.638403 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 10:05:23.644998 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 10:05:23.648257 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 10:05:23.651296 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 10:05:23.658493 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 10:05:23.661908 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 10:05:23.664970 0 9 8 | B1->B0 | 2f2f 3333 | 0 0 | (0 0) (0 0)
1468 10:05:23.671519 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 10:05:23.675189 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 10:05:23.678430 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 10:05:23.684695 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 10:05:23.687842 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 10:05:23.691182 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 10:05:23.697417 0 10 4 | B1->B0 | 3333 2f2f | 1 1 | (1 0) (1 0)
1475 10:05:23.700906 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
1476 10:05:23.704634 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 10:05:23.711042 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 10:05:23.714195 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 10:05:23.717441 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 10:05:23.721014 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 10:05:23.727378 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 10:05:23.730772 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1483 10:05:23.734124 0 11 8 | B1->B0 | 3e3e 4242 | 0 0 | (0 0) (0 0)
1484 10:05:23.740794 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 10:05:23.744176 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 10:05:23.747626 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 10:05:23.754138 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 10:05:23.757475 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 10:05:23.760970 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 10:05:23.767827 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 10:05:23.770749 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 10:05:23.773788 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 10:05:23.780891 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 10:05:23.784142 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 10:05:23.787259 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 10:05:23.794090 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 10:05:23.797456 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 10:05:23.800251 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 10:05:23.807070 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 10:05:23.810031 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 10:05:23.813630 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 10:05:23.820097 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 10:05:23.823142 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 10:05:23.827117 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 10:05:23.833931 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 10:05:23.836860 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1507 10:05:23.839900 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 10:05:23.843323 Total UI for P1: 0, mck2ui 16
1509 10:05:23.846420 best dqsien dly found for B0: ( 0, 14, 4)
1510 10:05:23.850124 Total UI for P1: 0, mck2ui 16
1511 10:05:23.853252 best dqsien dly found for B1: ( 0, 14, 4)
1512 10:05:23.856650 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1513 10:05:23.860204 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1514 10:05:23.860723
1515 10:05:23.866349 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1516 10:05:23.870073 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1517 10:05:23.870588 [Gating] SW calibration Done
1518 10:05:23.872833 ==
1519 10:05:23.876646 Dram Type= 6, Freq= 0, CH_1, rank 0
1520 10:05:23.879809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1521 10:05:23.880365 ==
1522 10:05:23.880701 RX Vref Scan: 0
1523 10:05:23.881009
1524 10:05:23.883072 RX Vref 0 -> 0, step: 1
1525 10:05:23.883489
1526 10:05:23.886220 RX Delay -130 -> 252, step: 16
1527 10:05:23.889995 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1528 10:05:23.892872 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1529 10:05:23.899465 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1530 10:05:23.903167 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1531 10:05:23.906362 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1532 10:05:23.909666 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1533 10:05:23.912848 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1534 10:05:23.919734 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1535 10:05:23.922848 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1536 10:05:23.926136 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1537 10:05:23.929340 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1538 10:05:23.932719 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1539 10:05:23.939203 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1540 10:05:23.942751 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1541 10:05:23.946128 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1542 10:05:23.949519 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1543 10:05:23.950050 ==
1544 10:05:23.952525 Dram Type= 6, Freq= 0, CH_1, rank 0
1545 10:05:23.959528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1546 10:05:23.960100 ==
1547 10:05:23.960487 DQS Delay:
1548 10:05:23.963325 DQS0 = 0, DQS1 = 0
1549 10:05:23.963842 DQM Delay:
1550 10:05:23.964221 DQM0 = 86, DQM1 = 82
1551 10:05:23.965998 DQ Delay:
1552 10:05:23.969536 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1553 10:05:23.973222 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =77
1554 10:05:23.975762 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1555 10:05:23.978900 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1556 10:05:23.979323
1557 10:05:23.979652
1558 10:05:23.979959 ==
1559 10:05:23.982291 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 10:05:23.985699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 10:05:23.986119 ==
1562 10:05:23.986472
1563 10:05:23.986780
1564 10:05:23.989131 TX Vref Scan disable
1565 10:05:23.992515 == TX Byte 0 ==
1566 10:05:23.996390 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1567 10:05:23.998938 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1568 10:05:24.002379 == TX Byte 1 ==
1569 10:05:24.005600 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1570 10:05:24.008964 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1571 10:05:24.009489 ==
1572 10:05:24.012395 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 10:05:24.016103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 10:05:24.018750 ==
1575 10:05:24.030000 TX Vref=22, minBit 0, minWin=27, winSum=440
1576 10:05:24.033845 TX Vref=24, minBit 2, minWin=27, winSum=446
1577 10:05:24.037155 TX Vref=26, minBit 5, minWin=27, winSum=454
1578 10:05:24.040305 TX Vref=28, minBit 3, minWin=27, winSum=453
1579 10:05:24.043652 TX Vref=30, minBit 6, minWin=27, winSum=457
1580 10:05:24.049506 TX Vref=32, minBit 0, minWin=27, winSum=453
1581 10:05:24.053689 [TxChooseVref] Worse bit 6, Min win 27, Win sum 457, Final Vref 30
1582 10:05:24.054221
1583 10:05:24.056994 Final TX Range 1 Vref 30
1584 10:05:24.057415
1585 10:05:24.057746 ==
1586 10:05:24.060349 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 10:05:24.064160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 10:05:24.064690 ==
1589 10:05:24.065029
1590 10:05:24.065416
1591 10:05:24.067240 TX Vref Scan disable
1592 10:05:24.070989 == TX Byte 0 ==
1593 10:05:24.074143 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1594 10:05:24.076936 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1595 10:05:24.080699 == TX Byte 1 ==
1596 10:05:24.083657 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1597 10:05:24.086666 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1598 10:05:24.087105
1599 10:05:24.090527 [DATLAT]
1600 10:05:24.090944 Freq=800, CH1 RK0
1601 10:05:24.091275
1602 10:05:24.093712 DATLAT Default: 0xa
1603 10:05:24.094230 0, 0xFFFF, sum = 0
1604 10:05:24.096889 1, 0xFFFF, sum = 0
1605 10:05:24.097420 2, 0xFFFF, sum = 0
1606 10:05:24.100358 3, 0xFFFF, sum = 0
1607 10:05:24.100889 4, 0xFFFF, sum = 0
1608 10:05:24.103766 5, 0xFFFF, sum = 0
1609 10:05:24.104330 6, 0xFFFF, sum = 0
1610 10:05:24.107186 7, 0xFFFF, sum = 0
1611 10:05:24.110410 8, 0xFFFF, sum = 0
1612 10:05:24.110943 9, 0x0, sum = 1
1613 10:05:24.111288 10, 0x0, sum = 2
1614 10:05:24.113812 11, 0x0, sum = 3
1615 10:05:24.114346 12, 0x0, sum = 4
1616 10:05:24.116681 best_step = 10
1617 10:05:24.117203
1618 10:05:24.117538 ==
1619 10:05:24.120587 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 10:05:24.123083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 10:05:24.123510 ==
1622 10:05:24.126739 RX Vref Scan: 1
1623 10:05:24.127159
1624 10:05:24.127488 Set Vref Range= 32 -> 127
1625 10:05:24.127797
1626 10:05:24.129835 RX Vref 32 -> 127, step: 1
1627 10:05:24.130433
1628 10:05:24.133197 RX Delay -95 -> 252, step: 8
1629 10:05:24.133615
1630 10:05:24.136375 Set Vref, RX VrefLevel [Byte0]: 32
1631 10:05:24.139977 [Byte1]: 32
1632 10:05:24.140531
1633 10:05:24.143444 Set Vref, RX VrefLevel [Byte0]: 33
1634 10:05:24.146941 [Byte1]: 33
1635 10:05:24.150495
1636 10:05:24.151018 Set Vref, RX VrefLevel [Byte0]: 34
1637 10:05:24.153575 [Byte1]: 34
1638 10:05:24.157560
1639 10:05:24.157977 Set Vref, RX VrefLevel [Byte0]: 35
1640 10:05:24.161166 [Byte1]: 35
1641 10:05:24.165815
1642 10:05:24.166232 Set Vref, RX VrefLevel [Byte0]: 36
1643 10:05:24.168486 [Byte1]: 36
1644 10:05:24.173272
1645 10:05:24.173792 Set Vref, RX VrefLevel [Byte0]: 37
1646 10:05:24.176701 [Byte1]: 37
1647 10:05:24.180641
1648 10:05:24.181171 Set Vref, RX VrefLevel [Byte0]: 38
1649 10:05:24.184311 [Byte1]: 38
1650 10:05:24.188172
1651 10:05:24.188591 Set Vref, RX VrefLevel [Byte0]: 39
1652 10:05:24.191312 [Byte1]: 39
1653 10:05:24.195783
1654 10:05:24.196352 Set Vref, RX VrefLevel [Byte0]: 40
1655 10:05:24.199534 [Byte1]: 40
1656 10:05:24.203517
1657 10:05:24.204095 Set Vref, RX VrefLevel [Byte0]: 41
1658 10:05:24.207152 [Byte1]: 41
1659 10:05:24.211249
1660 10:05:24.211842 Set Vref, RX VrefLevel [Byte0]: 42
1661 10:05:24.214514 [Byte1]: 42
1662 10:05:24.218970
1663 10:05:24.219497 Set Vref, RX VrefLevel [Byte0]: 43
1664 10:05:24.221624 [Byte1]: 43
1665 10:05:24.226268
1666 10:05:24.226687 Set Vref, RX VrefLevel [Byte0]: 44
1667 10:05:24.229435 [Byte1]: 44
1668 10:05:24.234210
1669 10:05:24.234733 Set Vref, RX VrefLevel [Byte0]: 45
1670 10:05:24.236888 [Byte1]: 45
1671 10:05:24.241868
1672 10:05:24.242392 Set Vref, RX VrefLevel [Byte0]: 46
1673 10:05:24.244495 [Byte1]: 46
1674 10:05:24.248931
1675 10:05:24.249351 Set Vref, RX VrefLevel [Byte0]: 47
1676 10:05:24.252401 [Byte1]: 47
1677 10:05:24.256410
1678 10:05:24.256831 Set Vref, RX VrefLevel [Byte0]: 48
1679 10:05:24.259753 [Byte1]: 48
1680 10:05:24.264196
1681 10:05:24.264707 Set Vref, RX VrefLevel [Byte0]: 49
1682 10:05:24.267486 [Byte1]: 49
1683 10:05:24.272273
1684 10:05:24.272791 Set Vref, RX VrefLevel [Byte0]: 50
1685 10:05:24.275209 [Byte1]: 50
1686 10:05:24.279642
1687 10:05:24.280190 Set Vref, RX VrefLevel [Byte0]: 51
1688 10:05:24.283229 [Byte1]: 51
1689 10:05:24.286799
1690 10:05:24.287241 Set Vref, RX VrefLevel [Byte0]: 52
1691 10:05:24.290010 [Byte1]: 52
1692 10:05:24.295188
1693 10:05:24.295945 Set Vref, RX VrefLevel [Byte0]: 53
1694 10:05:24.297911 [Byte1]: 53
1695 10:05:24.302362
1696 10:05:24.302787 Set Vref, RX VrefLevel [Byte0]: 54
1697 10:05:24.305605 [Byte1]: 54
1698 10:05:24.309803
1699 10:05:24.310341 Set Vref, RX VrefLevel [Byte0]: 55
1700 10:05:24.313661 [Byte1]: 55
1701 10:05:24.317219
1702 10:05:24.317643 Set Vref, RX VrefLevel [Byte0]: 56
1703 10:05:24.320730 [Byte1]: 56
1704 10:05:24.325506
1705 10:05:24.325935 Set Vref, RX VrefLevel [Byte0]: 57
1706 10:05:24.328081 [Byte1]: 57
1707 10:05:24.332727
1708 10:05:24.333148 Set Vref, RX VrefLevel [Byte0]: 58
1709 10:05:24.335989 [Byte1]: 58
1710 10:05:24.339957
1711 10:05:24.340460 Set Vref, RX VrefLevel [Byte0]: 59
1712 10:05:24.343239 [Byte1]: 59
1713 10:05:24.347973
1714 10:05:24.348483 Set Vref, RX VrefLevel [Byte0]: 60
1715 10:05:24.351744 [Byte1]: 60
1716 10:05:24.355196
1717 10:05:24.355633 Set Vref, RX VrefLevel [Byte0]: 61
1718 10:05:24.358640 [Byte1]: 61
1719 10:05:24.363103
1720 10:05:24.363723 Set Vref, RX VrefLevel [Byte0]: 62
1721 10:05:24.366664 [Byte1]: 62
1722 10:05:24.370417
1723 10:05:24.370847 Set Vref, RX VrefLevel [Byte0]: 63
1724 10:05:24.373649 [Byte1]: 63
1725 10:05:24.378016
1726 10:05:24.378482 Set Vref, RX VrefLevel [Byte0]: 64
1727 10:05:24.381622 [Byte1]: 64
1728 10:05:24.386243
1729 10:05:24.386664 Set Vref, RX VrefLevel [Byte0]: 65
1730 10:05:24.389014 [Byte1]: 65
1731 10:05:24.393356
1732 10:05:24.393848 Set Vref, RX VrefLevel [Byte0]: 66
1733 10:05:24.396385 [Byte1]: 66
1734 10:05:24.401153
1735 10:05:24.401570 Set Vref, RX VrefLevel [Byte0]: 67
1736 10:05:24.404352 [Byte1]: 67
1737 10:05:24.408361
1738 10:05:24.408775 Set Vref, RX VrefLevel [Byte0]: 68
1739 10:05:24.411659 [Byte1]: 68
1740 10:05:24.416143
1741 10:05:24.416552 Set Vref, RX VrefLevel [Byte0]: 69
1742 10:05:24.419668 [Byte1]: 69
1743 10:05:24.423678
1744 10:05:24.424126 Set Vref, RX VrefLevel [Byte0]: 70
1745 10:05:24.427043 [Byte1]: 70
1746 10:05:24.431296
1747 10:05:24.431776 Set Vref, RX VrefLevel [Byte0]: 71
1748 10:05:24.434343 [Byte1]: 71
1749 10:05:24.438790
1750 10:05:24.439268 Set Vref, RX VrefLevel [Byte0]: 72
1751 10:05:24.442408 [Byte1]: 72
1752 10:05:24.446855
1753 10:05:24.447343 Set Vref, RX VrefLevel [Byte0]: 73
1754 10:05:24.449804 [Byte1]: 73
1755 10:05:24.453869
1756 10:05:24.454276 Set Vref, RX VrefLevel [Byte0]: 74
1757 10:05:24.457687 [Byte1]: 74
1758 10:05:24.461514
1759 10:05:24.461995 Set Vref, RX VrefLevel [Byte0]: 75
1760 10:05:24.464934 [Byte1]: 75
1761 10:05:24.468899
1762 10:05:24.469423 Final RX Vref Byte 0 = 55 to rank0
1763 10:05:24.472244 Final RX Vref Byte 1 = 56 to rank0
1764 10:05:24.475720 Final RX Vref Byte 0 = 55 to rank1
1765 10:05:24.479444 Final RX Vref Byte 1 = 56 to rank1==
1766 10:05:24.482798 Dram Type= 6, Freq= 0, CH_1, rank 0
1767 10:05:24.489499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1768 10:05:24.489933 ==
1769 10:05:24.490268 DQS Delay:
1770 10:05:24.492722 DQS0 = 0, DQS1 = 0
1771 10:05:24.493135 DQM Delay:
1772 10:05:24.493466 DQM0 = 84, DQM1 = 80
1773 10:05:24.495657 DQ Delay:
1774 10:05:24.498865 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1775 10:05:24.502367 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1776 10:05:24.505795 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1777 10:05:24.508902 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1778 10:05:24.509325
1779 10:05:24.509655
1780 10:05:24.515906 [DQSOSCAuto] RK0, (LSB)MR18= 0x172a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1781 10:05:24.518848 CH1 RK0: MR19=606, MR18=172A
1782 10:05:24.525545 CH1_RK0: MR19=0x606, MR18=0x172A, DQSOSC=399, MR23=63, INC=92, DEC=61
1783 10:05:24.526027
1784 10:05:24.529037 ----->DramcWriteLeveling(PI) begin...
1785 10:05:24.529678 ==
1786 10:05:24.532293 Dram Type= 6, Freq= 0, CH_1, rank 1
1787 10:05:24.535426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 10:05:24.535850 ==
1789 10:05:24.538877 Write leveling (Byte 0): 25 => 25
1790 10:05:24.542192 Write leveling (Byte 1): 31 => 31
1791 10:05:24.545654 DramcWriteLeveling(PI) end<-----
1792 10:05:24.546103
1793 10:05:24.546439 ==
1794 10:05:24.548762 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 10:05:24.552443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 10:05:24.553007 ==
1797 10:05:24.555293 [Gating] SW mode calibration
1798 10:05:24.562244 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1799 10:05:24.568880 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1800 10:05:24.572271 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1801 10:05:24.575596 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1802 10:05:24.582134 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 10:05:24.585311 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 10:05:24.588741 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 10:05:24.595100 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 10:05:24.598883 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 10:05:24.602132 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 10:05:24.608607 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 10:05:24.612089 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 10:05:24.615153 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 10:05:24.621860 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 10:05:24.625345 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 10:05:24.628321 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 10:05:24.634871 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 10:05:24.638333 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 10:05:24.641820 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1817 10:05:24.648443 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1818 10:05:24.651186 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1819 10:05:24.654966 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 10:05:24.661657 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 10:05:24.664632 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 10:05:24.668051 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 10:05:24.674600 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 10:05:24.677622 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 10:05:24.681147 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1826 10:05:24.687881 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1827 10:05:24.691525 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 10:05:24.694946 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 10:05:24.701280 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 10:05:24.704720 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 10:05:24.707678 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 10:05:24.714496 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1833 10:05:24.717518 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
1834 10:05:24.720871 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 10:05:24.727836 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 10:05:24.730937 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 10:05:24.734815 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 10:05:24.741232 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 10:05:24.744573 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 10:05:24.748010 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 10:05:24.751494 0 11 4 | B1->B0 | 2525 3736 | 0 1 | (0 0) (0 0)
1842 10:05:24.757576 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1843 10:05:24.761426 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 10:05:24.764377 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 10:05:24.771144 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 10:05:24.774039 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 10:05:24.777798 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 10:05:24.784427 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1849 10:05:24.787676 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1850 10:05:24.790882 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1851 10:05:24.797282 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 10:05:24.800967 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 10:05:24.804173 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 10:05:24.810946 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 10:05:24.813932 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 10:05:24.817561 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 10:05:24.823927 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 10:05:24.827391 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 10:05:24.830708 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 10:05:24.837353 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 10:05:24.840468 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 10:05:24.844522 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 10:05:24.850356 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 10:05:24.853686 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1865 10:05:24.856942 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1866 10:05:24.860498 Total UI for P1: 0, mck2ui 16
1867 10:05:24.863741 best dqsien dly found for B0: ( 0, 14, 0)
1868 10:05:24.870482 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1869 10:05:24.873469 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 10:05:24.877085 Total UI for P1: 0, mck2ui 16
1871 10:05:24.880663 best dqsien dly found for B1: ( 0, 14, 6)
1872 10:05:24.883469 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1873 10:05:24.887270 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1874 10:05:24.887792
1875 10:05:24.890510 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1876 10:05:24.893406 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1877 10:05:24.897058 [Gating] SW calibration Done
1878 10:05:24.897474 ==
1879 10:05:24.900105 Dram Type= 6, Freq= 0, CH_1, rank 1
1880 10:05:24.903644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1881 10:05:24.904108 ==
1882 10:05:24.907242 RX Vref Scan: 0
1883 10:05:24.907662
1884 10:05:24.910173 RX Vref 0 -> 0, step: 1
1885 10:05:24.910596
1886 10:05:24.913599 RX Delay -130 -> 252, step: 16
1887 10:05:24.917130 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1888 10:05:24.920162 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1889 10:05:24.923328 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1890 10:05:24.926950 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1891 10:05:24.933076 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1892 10:05:24.936433 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1893 10:05:24.939988 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1894 10:05:24.943193 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1895 10:05:24.946563 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1896 10:05:24.953573 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1897 10:05:24.956185 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1898 10:05:24.959513 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1899 10:05:24.962971 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1900 10:05:24.966188 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1901 10:05:24.973351 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1902 10:05:24.976651 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1903 10:05:24.977069 ==
1904 10:05:24.979427 Dram Type= 6, Freq= 0, CH_1, rank 1
1905 10:05:24.983023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1906 10:05:24.983443 ==
1907 10:05:24.986794 DQS Delay:
1908 10:05:24.987246 DQS0 = 0, DQS1 = 0
1909 10:05:24.987584 DQM Delay:
1910 10:05:24.989418 DQM0 = 80, DQM1 = 80
1911 10:05:24.989834 DQ Delay:
1912 10:05:24.993255 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1913 10:05:24.996175 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1914 10:05:24.999791 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1915 10:05:25.003498 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =93
1916 10:05:25.003915
1917 10:05:25.004295
1918 10:05:25.004632 ==
1919 10:05:25.006459 Dram Type= 6, Freq= 0, CH_1, rank 1
1920 10:05:25.012991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1921 10:05:25.013415 ==
1922 10:05:25.013747
1923 10:05:25.014050
1924 10:05:25.014342 TX Vref Scan disable
1925 10:05:25.017097 == TX Byte 0 ==
1926 10:05:25.020117 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1927 10:05:25.026667 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1928 10:05:25.027139 == TX Byte 1 ==
1929 10:05:25.029339 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1930 10:05:25.036198 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1931 10:05:25.036619 ==
1932 10:05:25.039303 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 10:05:25.042573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 10:05:25.042943 ==
1935 10:05:25.055790 TX Vref=22, minBit 0, minWin=27, winSum=446
1936 10:05:25.059151 TX Vref=24, minBit 1, minWin=27, winSum=447
1937 10:05:25.062756 TX Vref=26, minBit 1, minWin=28, winSum=453
1938 10:05:25.065908 TX Vref=28, minBit 6, minWin=27, winSum=452
1939 10:05:25.069183 TX Vref=30, minBit 1, minWin=28, winSum=459
1940 10:05:25.075824 TX Vref=32, minBit 2, minWin=27, winSum=449
1941 10:05:25.079141 [TxChooseVref] Worse bit 1, Min win 28, Win sum 459, Final Vref 30
1942 10:05:25.079541
1943 10:05:25.082658 Final TX Range 1 Vref 30
1944 10:05:25.083052
1945 10:05:25.083382 ==
1946 10:05:25.085913 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 10:05:25.089118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 10:05:25.089558 ==
1949 10:05:25.092539
1950 10:05:25.093000
1951 10:05:25.093336 TX Vref Scan disable
1952 10:05:25.095997 == TX Byte 0 ==
1953 10:05:25.099484 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1954 10:05:25.106123 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1955 10:05:25.106687 == TX Byte 1 ==
1956 10:05:25.109502 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1957 10:05:25.116122 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1958 10:05:25.116546
1959 10:05:25.116877 [DATLAT]
1960 10:05:25.117188 Freq=800, CH1 RK1
1961 10:05:25.117487
1962 10:05:25.119213 DATLAT Default: 0xa
1963 10:05:25.119649 0, 0xFFFF, sum = 0
1964 10:05:25.122671 1, 0xFFFF, sum = 0
1965 10:05:25.125775 2, 0xFFFF, sum = 0
1966 10:05:25.126260 3, 0xFFFF, sum = 0
1967 10:05:25.129235 4, 0xFFFF, sum = 0
1968 10:05:25.129678 5, 0xFFFF, sum = 0
1969 10:05:25.132209 6, 0xFFFF, sum = 0
1970 10:05:25.132681 7, 0xFFFF, sum = 0
1971 10:05:25.135841 8, 0xFFFF, sum = 0
1972 10:05:25.136298 9, 0x0, sum = 1
1973 10:05:25.138720 10, 0x0, sum = 2
1974 10:05:25.139152 11, 0x0, sum = 3
1975 10:05:25.142467 12, 0x0, sum = 4
1976 10:05:25.142845 best_step = 10
1977 10:05:25.143205
1978 10:05:25.143528 ==
1979 10:05:25.145878 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 10:05:25.148826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 10:05:25.149233 ==
1982 10:05:25.152373 RX Vref Scan: 0
1983 10:05:25.152757
1984 10:05:25.155535 RX Vref 0 -> 0, step: 1
1985 10:05:25.155939
1986 10:05:25.156356 RX Delay -95 -> 252, step: 8
1987 10:05:25.162784 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1988 10:05:25.165854 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1989 10:05:25.169188 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1990 10:05:25.172467 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1991 10:05:25.175937 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1992 10:05:25.182571 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1993 10:05:25.186209 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1994 10:05:25.189522 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1995 10:05:25.192373 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1996 10:05:25.195733 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1997 10:05:25.202781 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
1998 10:05:25.205432 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1999 10:05:25.208826 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2000 10:05:25.212138 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2001 10:05:25.218954 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2002 10:05:25.222009 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2003 10:05:25.222434 ==
2004 10:05:25.225636 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 10:05:25.228752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 10:05:25.229135 ==
2007 10:05:25.232261 DQS Delay:
2008 10:05:25.232671 DQS0 = 0, DQS1 = 0
2009 10:05:25.233010 DQM Delay:
2010 10:05:25.237246 DQM0 = 86, DQM1 = 82
2011 10:05:25.237679 DQ Delay:
2012 10:05:25.238876 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2013 10:05:25.242007 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2014 10:05:25.245408 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =76
2015 10:05:25.249039 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2016 10:05:25.249432
2017 10:05:25.249792
2018 10:05:25.259160 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a35, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
2019 10:05:25.259727 CH1 RK1: MR19=606, MR18=1A35
2020 10:05:25.265492 CH1_RK1: MR19=0x606, MR18=0x1A35, DQSOSC=396, MR23=63, INC=94, DEC=62
2021 10:05:25.268881 [RxdqsGatingPostProcess] freq 800
2022 10:05:25.275906 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2023 10:05:25.278860 Pre-setting of DQS Precalculation
2024 10:05:25.282551 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2025 10:05:25.288661 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2026 10:05:25.298995 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2027 10:05:25.299468
2028 10:05:25.299807
2029 10:05:25.301724 [Calibration Summary] 1600 Mbps
2030 10:05:25.302245 CH 0, Rank 0
2031 10:05:25.305587 SW Impedance : PASS
2032 10:05:25.306020 DUTY Scan : NO K
2033 10:05:25.308489 ZQ Calibration : PASS
2034 10:05:25.312568 Jitter Meter : NO K
2035 10:05:25.313150 CBT Training : PASS
2036 10:05:25.314901 Write leveling : PASS
2037 10:05:25.315371 RX DQS gating : PASS
2038 10:05:25.318644 RX DQ/DQS(RDDQC) : PASS
2039 10:05:25.321755 TX DQ/DQS : PASS
2040 10:05:25.322224 RX DATLAT : PASS
2041 10:05:25.324945 RX DQ/DQS(Engine): PASS
2042 10:05:25.328439 TX OE : NO K
2043 10:05:25.328870 All Pass.
2044 10:05:25.329204
2045 10:05:25.329519 CH 0, Rank 1
2046 10:05:25.331760 SW Impedance : PASS
2047 10:05:25.334901 DUTY Scan : NO K
2048 10:05:25.335322 ZQ Calibration : PASS
2049 10:05:25.338347 Jitter Meter : NO K
2050 10:05:25.342036 CBT Training : PASS
2051 10:05:25.342458 Write leveling : PASS
2052 10:05:25.344951 RX DQS gating : PASS
2053 10:05:25.348771 RX DQ/DQS(RDDQC) : PASS
2054 10:05:25.349195 TX DQ/DQS : PASS
2055 10:05:25.351425 RX DATLAT : PASS
2056 10:05:25.354833 RX DQ/DQS(Engine): PASS
2057 10:05:25.355253 TX OE : NO K
2058 10:05:25.358481 All Pass.
2059 10:05:25.358904
2060 10:05:25.359236 CH 1, Rank 0
2061 10:05:25.361611 SW Impedance : PASS
2062 10:05:25.362034 DUTY Scan : NO K
2063 10:05:25.364943 ZQ Calibration : PASS
2064 10:05:25.368333 Jitter Meter : NO K
2065 10:05:25.368756 CBT Training : PASS
2066 10:05:25.371787 Write leveling : PASS
2067 10:05:25.372245 RX DQS gating : PASS
2068 10:05:25.375112 RX DQ/DQS(RDDQC) : PASS
2069 10:05:25.378012 TX DQ/DQS : PASS
2070 10:05:25.378438 RX DATLAT : PASS
2071 10:05:25.381381 RX DQ/DQS(Engine): PASS
2072 10:05:25.384701 TX OE : NO K
2073 10:05:25.385209 All Pass.
2074 10:05:25.385550
2075 10:05:25.385863 CH 1, Rank 1
2076 10:05:25.387916 SW Impedance : PASS
2077 10:05:25.391364 DUTY Scan : NO K
2078 10:05:25.391786 ZQ Calibration : PASS
2079 10:05:25.394536 Jitter Meter : NO K
2080 10:05:25.397887 CBT Training : PASS
2081 10:05:25.398451 Write leveling : PASS
2082 10:05:25.401309 RX DQS gating : PASS
2083 10:05:25.404408 RX DQ/DQS(RDDQC) : PASS
2084 10:05:25.404830 TX DQ/DQS : PASS
2085 10:05:25.407895 RX DATLAT : PASS
2086 10:05:25.411309 RX DQ/DQS(Engine): PASS
2087 10:05:25.411729 TX OE : NO K
2088 10:05:25.414261 All Pass.
2089 10:05:25.414700
2090 10:05:25.415033 DramC Write-DBI off
2091 10:05:25.417676 PER_BANK_REFRESH: Hybrid Mode
2092 10:05:25.418097 TX_TRACKING: ON
2093 10:05:25.421816 [GetDramInforAfterCalByMRR] Vendor 6.
2094 10:05:25.427286 [GetDramInforAfterCalByMRR] Revision 606.
2095 10:05:25.430808 [GetDramInforAfterCalByMRR] Revision 2 0.
2096 10:05:25.431420 MR0 0x3b3b
2097 10:05:25.431953 MR8 0x5151
2098 10:05:25.434289 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2099 10:05:25.437460
2100 10:05:25.437880 MR0 0x3b3b
2101 10:05:25.438212 MR8 0x5151
2102 10:05:25.440809 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2103 10:05:25.441281
2104 10:05:25.450561 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2105 10:05:25.453874 [FAST_K] Save calibration result to emmc
2106 10:05:25.457685 [FAST_K] Save calibration result to emmc
2107 10:05:25.460644 dram_init: config_dvfs: 1
2108 10:05:25.463821 dramc_set_vcore_voltage set vcore to 662500
2109 10:05:25.467415 Read voltage for 1200, 2
2110 10:05:25.467846 Vio18 = 0
2111 10:05:25.468308 Vcore = 662500
2112 10:05:25.470780 Vdram = 0
2113 10:05:25.471237 Vddq = 0
2114 10:05:25.471579 Vmddr = 0
2115 10:05:25.477571 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2116 10:05:25.480459 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2117 10:05:25.484109 MEM_TYPE=3, freq_sel=15
2118 10:05:25.487479 sv_algorithm_assistance_LP4_1600
2119 10:05:25.490490 ============ PULL DRAM RESETB DOWN ============
2120 10:05:25.494434 ========== PULL DRAM RESETB DOWN end =========
2121 10:05:25.500649 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2122 10:05:25.503928 ===================================
2123 10:05:25.507084 LPDDR4 DRAM CONFIGURATION
2124 10:05:25.510373 ===================================
2125 10:05:25.510861 EX_ROW_EN[0] = 0x0
2126 10:05:25.513490 EX_ROW_EN[1] = 0x0
2127 10:05:25.513953 LP4Y_EN = 0x0
2128 10:05:25.517032 WORK_FSP = 0x0
2129 10:05:25.517461 WL = 0x4
2130 10:05:25.520271 RL = 0x4
2131 10:05:25.520689 BL = 0x2
2132 10:05:25.523749 RPST = 0x0
2133 10:05:25.524192 RD_PRE = 0x0
2134 10:05:25.527205 WR_PRE = 0x1
2135 10:05:25.527620 WR_PST = 0x0
2136 10:05:25.530420 DBI_WR = 0x0
2137 10:05:25.530837 DBI_RD = 0x0
2138 10:05:25.533724 OTF = 0x1
2139 10:05:25.536610 ===================================
2140 10:05:25.539986 ===================================
2141 10:05:25.540438 ANA top config
2142 10:05:25.543412 ===================================
2143 10:05:25.547471 DLL_ASYNC_EN = 0
2144 10:05:25.550473 ALL_SLAVE_EN = 0
2145 10:05:25.553601 NEW_RANK_MODE = 1
2146 10:05:25.556420 DLL_IDLE_MODE = 1
2147 10:05:25.556832 LP45_APHY_COMB_EN = 1
2148 10:05:25.559833 TX_ODT_DIS = 1
2149 10:05:25.563696 NEW_8X_MODE = 1
2150 10:05:25.566212 ===================================
2151 10:05:25.569668 ===================================
2152 10:05:25.573110 data_rate = 2400
2153 10:05:25.576434 CKR = 1
2154 10:05:25.576856 DQ_P2S_RATIO = 8
2155 10:05:25.580194 ===================================
2156 10:05:25.583589 CA_P2S_RATIO = 8
2157 10:05:25.586452 DQ_CA_OPEN = 0
2158 10:05:25.590022 DQ_SEMI_OPEN = 0
2159 10:05:25.593165 CA_SEMI_OPEN = 0
2160 10:05:25.596410 CA_FULL_RATE = 0
2161 10:05:25.596830 DQ_CKDIV4_EN = 0
2162 10:05:25.599897 CA_CKDIV4_EN = 0
2163 10:05:25.603279 CA_PREDIV_EN = 0
2164 10:05:25.606589 PH8_DLY = 17
2165 10:05:25.610085 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2166 10:05:25.613162 DQ_AAMCK_DIV = 4
2167 10:05:25.613581 CA_AAMCK_DIV = 4
2168 10:05:25.616171 CA_ADMCK_DIV = 4
2169 10:05:25.619582 DQ_TRACK_CA_EN = 0
2170 10:05:25.623146 CA_PICK = 1200
2171 10:05:25.626131 CA_MCKIO = 1200
2172 10:05:25.629451 MCKIO_SEMI = 0
2173 10:05:25.632613 PLL_FREQ = 2366
2174 10:05:25.636103 DQ_UI_PI_RATIO = 32
2175 10:05:25.636543 CA_UI_PI_RATIO = 0
2176 10:05:25.639418 ===================================
2177 10:05:25.642879 ===================================
2178 10:05:25.646365 memory_type:LPDDR4
2179 10:05:25.649496 GP_NUM : 10
2180 10:05:25.649917 SRAM_EN : 1
2181 10:05:25.652748 MD32_EN : 0
2182 10:05:25.656157 ===================================
2183 10:05:25.659672 [ANA_INIT] >>>>>>>>>>>>>>
2184 10:05:25.660133 <<<<<< [CONFIGURE PHASE]: ANA_TX
2185 10:05:25.662463 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2186 10:05:25.666056 ===================================
2187 10:05:25.669169 data_rate = 2400,PCW = 0X5b00
2188 10:05:25.672598 ===================================
2189 10:05:25.675605 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2190 10:05:25.682766 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2191 10:05:25.689373 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2192 10:05:25.692715 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2193 10:05:25.696165 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2194 10:05:25.699855 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2195 10:05:25.702478 [ANA_INIT] flow start
2196 10:05:25.702949 [ANA_INIT] PLL >>>>>>>>
2197 10:05:25.705897 [ANA_INIT] PLL <<<<<<<<
2198 10:05:25.709563 [ANA_INIT] MIDPI >>>>>>>>
2199 10:05:25.709985 [ANA_INIT] MIDPI <<<<<<<<
2200 10:05:25.712615 [ANA_INIT] DLL >>>>>>>>
2201 10:05:25.716278 [ANA_INIT] DLL <<<<<<<<
2202 10:05:25.716699 [ANA_INIT] flow end
2203 10:05:25.722653 ============ LP4 DIFF to SE enter ============
2204 10:05:25.725834 ============ LP4 DIFF to SE exit ============
2205 10:05:25.729172 [ANA_INIT] <<<<<<<<<<<<<
2206 10:05:25.732509 [Flow] Enable top DCM control >>>>>
2207 10:05:25.736074 [Flow] Enable top DCM control <<<<<
2208 10:05:25.736499 Enable DLL master slave shuffle
2209 10:05:25.742477 ==============================================================
2210 10:05:25.745649 Gating Mode config
2211 10:05:25.749231 ==============================================================
2212 10:05:25.752663 Config description:
2213 10:05:25.762654 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2214 10:05:25.768688 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2215 10:05:25.772492 SELPH_MODE 0: By rank 1: By Phase
2216 10:05:25.778983 ==============================================================
2217 10:05:25.782130 GAT_TRACK_EN = 1
2218 10:05:25.785719 RX_GATING_MODE = 2
2219 10:05:25.788704 RX_GATING_TRACK_MODE = 2
2220 10:05:25.791901 SELPH_MODE = 1
2221 10:05:25.795578 PICG_EARLY_EN = 1
2222 10:05:25.795997 VALID_LAT_VALUE = 1
2223 10:05:25.801861 ==============================================================
2224 10:05:25.805368 Enter into Gating configuration >>>>
2225 10:05:25.808515 Exit from Gating configuration <<<<
2226 10:05:25.811811 Enter into DVFS_PRE_config >>>>>
2227 10:05:25.821814 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2228 10:05:25.825536 Exit from DVFS_PRE_config <<<<<
2229 10:05:25.829039 Enter into PICG configuration >>>>
2230 10:05:25.832179 Exit from PICG configuration <<<<
2231 10:05:25.835336 [RX_INPUT] configuration >>>>>
2232 10:05:25.839212 [RX_INPUT] configuration <<<<<
2233 10:05:25.841974 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2234 10:05:25.848593 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2235 10:05:25.854957 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2236 10:05:25.862076 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2237 10:05:25.868470 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2238 10:05:25.874986 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2239 10:05:25.878012 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2240 10:05:25.881531 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2241 10:05:25.885018 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2242 10:05:25.891505 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2243 10:05:25.895023 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2244 10:05:25.898249 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2245 10:05:25.901621 ===================================
2246 10:05:25.905081 LPDDR4 DRAM CONFIGURATION
2247 10:05:25.908133 ===================================
2248 10:05:25.908514 EX_ROW_EN[0] = 0x0
2249 10:05:25.911461 EX_ROW_EN[1] = 0x0
2250 10:05:25.911987 LP4Y_EN = 0x0
2251 10:05:25.914581 WORK_FSP = 0x0
2252 10:05:25.918255 WL = 0x4
2253 10:05:25.918760 RL = 0x4
2254 10:05:25.921618 BL = 0x2
2255 10:05:25.922182 RPST = 0x0
2256 10:05:25.924994 RD_PRE = 0x0
2257 10:05:25.925418 WR_PRE = 0x1
2258 10:05:25.928022 WR_PST = 0x0
2259 10:05:25.928516 DBI_WR = 0x0
2260 10:05:25.931558 DBI_RD = 0x0
2261 10:05:25.932172 OTF = 0x1
2262 10:05:25.934483 ===================================
2263 10:05:25.937880 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2264 10:05:25.944422 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2265 10:05:25.947826 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2266 10:05:25.951232 ===================================
2267 10:05:25.954686 LPDDR4 DRAM CONFIGURATION
2268 10:05:25.957999 ===================================
2269 10:05:25.958555 EX_ROW_EN[0] = 0x10
2270 10:05:25.960876 EX_ROW_EN[1] = 0x0
2271 10:05:25.961312 LP4Y_EN = 0x0
2272 10:05:25.964590 WORK_FSP = 0x0
2273 10:05:25.965017 WL = 0x4
2274 10:05:25.967531 RL = 0x4
2275 10:05:25.970767 BL = 0x2
2276 10:05:25.971189 RPST = 0x0
2277 10:05:25.974469 RD_PRE = 0x0
2278 10:05:25.975026 WR_PRE = 0x1
2279 10:05:25.977426 WR_PST = 0x0
2280 10:05:25.977850 DBI_WR = 0x0
2281 10:05:25.980795 DBI_RD = 0x0
2282 10:05:25.981219 OTF = 0x1
2283 10:05:25.984248 ===================================
2284 10:05:25.990811 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2285 10:05:25.991238 ==
2286 10:05:25.994104 Dram Type= 6, Freq= 0, CH_0, rank 0
2287 10:05:25.997403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2288 10:05:25.997828 ==
2289 10:05:26.000780 [Duty_Offset_Calibration]
2290 10:05:26.003995 B0:2 B1:0 CA:4
2291 10:05:26.004454
2292 10:05:26.007053 [DutyScan_Calibration_Flow] k_type=0
2293 10:05:26.014414
2294 10:05:26.014821 ==CLK 0==
2295 10:05:26.017677 Final CLK duty delay cell = -4
2296 10:05:26.021073 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2297 10:05:26.024866 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2298 10:05:26.028201 [-4] AVG Duty = 4953%(X100)
2299 10:05:26.028525
2300 10:05:26.031302 CH0 CLK Duty spec in!! Max-Min= 218%
2301 10:05:26.034498 [DutyScan_Calibration_Flow] ====Done====
2302 10:05:26.034788
2303 10:05:26.037646 [DutyScan_Calibration_Flow] k_type=1
2304 10:05:26.053203
2305 10:05:26.053492 ==DQS 0 ==
2306 10:05:26.056577 Final DQS duty delay cell = -4
2307 10:05:26.060358 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2308 10:05:26.063726 [-4] MIN Duty = 4876%(X100), DQS PI = 2
2309 10:05:26.067006 [-4] AVG Duty = 4922%(X100)
2310 10:05:26.067655
2311 10:05:26.067987 ==DQS 1 ==
2312 10:05:26.070313 Final DQS duty delay cell = 0
2313 10:05:26.073449 [0] MAX Duty = 5125%(X100), DQS PI = 50
2314 10:05:26.076949 [0] MIN Duty = 4969%(X100), DQS PI = 62
2315 10:05:26.080372 [0] AVG Duty = 5047%(X100)
2316 10:05:26.080775
2317 10:05:26.083113 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2318 10:05:26.083519
2319 10:05:26.086525 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2320 10:05:26.089746 [DutyScan_Calibration_Flow] ====Done====
2321 10:05:26.090148
2322 10:05:26.093019 [DutyScan_Calibration_Flow] k_type=3
2323 10:05:26.110470
2324 10:05:26.110871 ==DQM 0 ==
2325 10:05:26.113428 Final DQM duty delay cell = 0
2326 10:05:26.117174 [0] MAX Duty = 5125%(X100), DQS PI = 20
2327 10:05:26.120328 [0] MIN Duty = 4844%(X100), DQS PI = 52
2328 10:05:26.123534 [0] AVG Duty = 4984%(X100)
2329 10:05:26.123933
2330 10:05:26.124287 ==DQM 1 ==
2331 10:05:26.126701 Final DQM duty delay cell = 0
2332 10:05:26.130243 [0] MAX Duty = 4969%(X100), DQS PI = 2
2333 10:05:26.133400 [0] MIN Duty = 4876%(X100), DQS PI = 28
2334 10:05:26.136899 [0] AVG Duty = 4922%(X100)
2335 10:05:26.137312
2336 10:05:26.140111 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2337 10:05:26.140515
2338 10:05:26.143292 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2339 10:05:26.146900 [DutyScan_Calibration_Flow] ====Done====
2340 10:05:26.147301
2341 10:05:26.150285 [DutyScan_Calibration_Flow] k_type=2
2342 10:05:26.166644
2343 10:05:26.167045 ==DQ 0 ==
2344 10:05:26.170415 Final DQ duty delay cell = 0
2345 10:05:26.173616 [0] MAX Duty = 5125%(X100), DQS PI = 18
2346 10:05:26.176712 [0] MIN Duty = 4969%(X100), DQS PI = 50
2347 10:05:26.177125 [0] AVG Duty = 5047%(X100)
2348 10:05:26.180142
2349 10:05:26.180554 ==DQ 1 ==
2350 10:05:26.183366 Final DQ duty delay cell = 0
2351 10:05:26.186561 [0] MAX Duty = 5156%(X100), DQS PI = 4
2352 10:05:26.189729 [0] MIN Duty = 4938%(X100), DQS PI = 16
2353 10:05:26.190205 [0] AVG Duty = 5047%(X100)
2354 10:05:26.190535
2355 10:05:26.193231 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2356 10:05:26.196420
2357 10:05:26.199878 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2358 10:05:26.202968 [DutyScan_Calibration_Flow] ====Done====
2359 10:05:26.203378 ==
2360 10:05:26.206432 Dram Type= 6, Freq= 0, CH_1, rank 0
2361 10:05:26.210014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2362 10:05:26.210517 ==
2363 10:05:26.213294 [Duty_Offset_Calibration]
2364 10:05:26.213742 B0:0 B1:-1 CA:3
2365 10:05:26.214081
2366 10:05:26.216548 [DutyScan_Calibration_Flow] k_type=0
2367 10:05:26.226027
2368 10:05:26.226437 ==CLK 0==
2369 10:05:26.228992 Final CLK duty delay cell = -4
2370 10:05:26.232499 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2371 10:05:26.235839 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2372 10:05:26.239434 [-4] AVG Duty = 4938%(X100)
2373 10:05:26.239862
2374 10:05:26.242886 CH1 CLK Duty spec in!! Max-Min= 124%
2375 10:05:26.246188 [DutyScan_Calibration_Flow] ====Done====
2376 10:05:26.246597
2377 10:05:26.248817 [DutyScan_Calibration_Flow] k_type=1
2378 10:05:26.265790
2379 10:05:26.266313 ==DQS 0 ==
2380 10:05:26.268517 Final DQS duty delay cell = 0
2381 10:05:26.272348 [0] MAX Duty = 5187%(X100), DQS PI = 18
2382 10:05:26.275312 [0] MIN Duty = 4907%(X100), DQS PI = 38
2383 10:05:26.278581 [0] AVG Duty = 5047%(X100)
2384 10:05:26.278995
2385 10:05:26.279323 ==DQS 1 ==
2386 10:05:26.282227 Final DQS duty delay cell = 0
2387 10:05:26.285396 [0] MAX Duty = 5156%(X100), DQS PI = 6
2388 10:05:26.288413 [0] MIN Duty = 5000%(X100), DQS PI = 26
2389 10:05:26.291839 [0] AVG Duty = 5078%(X100)
2390 10:05:26.292289
2391 10:05:26.295027 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2392 10:05:26.295441
2393 10:05:26.298672 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2394 10:05:26.302025 [DutyScan_Calibration_Flow] ====Done====
2395 10:05:26.302440
2396 10:05:26.305141 [DutyScan_Calibration_Flow] k_type=3
2397 10:05:26.321856
2398 10:05:26.322266 ==DQM 0 ==
2399 10:05:26.325299 Final DQM duty delay cell = 0
2400 10:05:26.328748 [0] MAX Duty = 5031%(X100), DQS PI = 26
2401 10:05:26.331948 [0] MIN Duty = 4782%(X100), DQS PI = 38
2402 10:05:26.334879 [0] AVG Duty = 4906%(X100)
2403 10:05:26.335290
2404 10:05:26.335615 ==DQM 1 ==
2405 10:05:26.338282 Final DQM duty delay cell = 0
2406 10:05:26.341470 [0] MAX Duty = 4969%(X100), DQS PI = 32
2407 10:05:26.345132 [0] MIN Duty = 4844%(X100), DQS PI = 0
2408 10:05:26.348645 [0] AVG Duty = 4906%(X100)
2409 10:05:26.349063
2410 10:05:26.351820 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2411 10:05:26.352258
2412 10:05:26.355348 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2413 10:05:26.358253 [DutyScan_Calibration_Flow] ====Done====
2414 10:05:26.358671
2415 10:05:26.361505 [DutyScan_Calibration_Flow] k_type=2
2416 10:05:26.377611
2417 10:05:26.378020 ==DQ 0 ==
2418 10:05:26.381065 Final DQ duty delay cell = -4
2419 10:05:26.384391 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2420 10:05:26.387755 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2421 10:05:26.390812 [-4] AVG Duty = 4922%(X100)
2422 10:05:26.391228
2423 10:05:26.391558 ==DQ 1 ==
2424 10:05:26.393938 Final DQ duty delay cell = 0
2425 10:05:26.397279 [0] MAX Duty = 5031%(X100), DQS PI = 34
2426 10:05:26.400467 [0] MIN Duty = 4844%(X100), DQS PI = 62
2427 10:05:26.404078 [0] AVG Duty = 4937%(X100)
2428 10:05:26.404503
2429 10:05:26.406979 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2430 10:05:26.407393
2431 10:05:26.410225 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2432 10:05:26.413586 [DutyScan_Calibration_Flow] ====Done====
2433 10:05:26.417211 nWR fixed to 30
2434 10:05:26.420174 [ModeRegInit_LP4] CH0 RK0
2435 10:05:26.420594 [ModeRegInit_LP4] CH0 RK1
2436 10:05:26.423846 [ModeRegInit_LP4] CH1 RK0
2437 10:05:26.426757 [ModeRegInit_LP4] CH1 RK1
2438 10:05:26.427172 match AC timing 7
2439 10:05:26.433636 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2440 10:05:26.436557 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2441 10:05:26.439940 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2442 10:05:26.446661 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2443 10:05:26.449990 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2444 10:05:26.450550 ==
2445 10:05:26.453252 Dram Type= 6, Freq= 0, CH_0, rank 0
2446 10:05:26.456672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2447 10:05:26.457097 ==
2448 10:05:26.463284 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2449 10:05:26.469658 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2450 10:05:26.477838 [CA 0] Center 39 (9~70) winsize 62
2451 10:05:26.481082 [CA 1] Center 39 (9~69) winsize 61
2452 10:05:26.484407 [CA 2] Center 35 (5~66) winsize 62
2453 10:05:26.488091 [CA 3] Center 35 (5~66) winsize 62
2454 10:05:26.490812 [CA 4] Center 33 (3~64) winsize 62
2455 10:05:26.494086 [CA 5] Center 33 (3~63) winsize 61
2456 10:05:26.494577
2457 10:05:26.497635 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2458 10:05:26.498054
2459 10:05:26.501059 [CATrainingPosCal] consider 1 rank data
2460 10:05:26.504198 u2DelayCellTimex100 = 270/100 ps
2461 10:05:26.507732 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2462 10:05:26.514458 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2463 10:05:26.517920 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2464 10:05:26.520627 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2465 10:05:26.524567 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2466 10:05:26.527203 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2467 10:05:26.527626
2468 10:05:26.530778 CA PerBit enable=1, Macro0, CA PI delay=33
2469 10:05:26.531364
2470 10:05:26.534034 [CBTSetCACLKResult] CA Dly = 33
2471 10:05:26.534501 CS Dly: 7 (0~38)
2472 10:05:26.537269 ==
2473 10:05:26.540848 Dram Type= 6, Freq= 0, CH_0, rank 1
2474 10:05:26.544121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2475 10:05:26.544583 ==
2476 10:05:26.550374 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2477 10:05:26.553625 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2478 10:05:26.563811 [CA 0] Center 39 (9~70) winsize 62
2479 10:05:26.567497 [CA 1] Center 39 (9~70) winsize 62
2480 10:05:26.570250 [CA 2] Center 35 (5~66) winsize 62
2481 10:05:26.573228 [CA 3] Center 35 (5~66) winsize 62
2482 10:05:26.576888 [CA 4] Center 34 (4~65) winsize 62
2483 10:05:26.580320 [CA 5] Center 33 (3~64) winsize 62
2484 10:05:26.580623
2485 10:05:26.583118 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2486 10:05:26.583432
2487 10:05:26.586417 [CATrainingPosCal] consider 2 rank data
2488 10:05:26.589845 u2DelayCellTimex100 = 270/100 ps
2489 10:05:26.593479 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2490 10:05:26.599860 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2491 10:05:26.603284 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2492 10:05:26.606636 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2493 10:05:26.609837 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2494 10:05:26.613254 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2495 10:05:26.613560
2496 10:05:26.616692 CA PerBit enable=1, Macro0, CA PI delay=33
2497 10:05:26.616985
2498 10:05:26.619328 [CBTSetCACLKResult] CA Dly = 33
2499 10:05:26.619620 CS Dly: 8 (0~41)
2500 10:05:26.622886
2501 10:05:26.626051 ----->DramcWriteLeveling(PI) begin...
2502 10:05:26.626361 ==
2503 10:05:26.629492 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 10:05:26.632632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 10:05:26.633024 ==
2506 10:05:26.636264 Write leveling (Byte 0): 33 => 33
2507 10:05:26.639705 Write leveling (Byte 1): 26 => 26
2508 10:05:26.643262 DramcWriteLeveling(PI) end<-----
2509 10:05:26.643558
2510 10:05:26.643868 ==
2511 10:05:26.646146 Dram Type= 6, Freq= 0, CH_0, rank 0
2512 10:05:26.650154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 10:05:26.650607 ==
2514 10:05:26.653466 [Gating] SW mode calibration
2515 10:05:26.659729 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2516 10:05:26.665965 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2517 10:05:26.669510 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2518 10:05:26.672725 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2519 10:05:26.679540 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 10:05:26.682995 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 10:05:26.686218 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 10:05:26.692532 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 10:05:26.696015 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2524 10:05:26.699174 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
2525 10:05:26.705949 1 0 0 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
2526 10:05:26.709377 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2527 10:05:26.712528 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 10:05:26.719255 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 10:05:26.722565 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 10:05:26.725880 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 10:05:26.732665 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2532 10:05:26.735597 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2533 10:05:26.739114 1 1 0 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2534 10:05:26.742510 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2535 10:05:26.749256 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 10:05:26.752172 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 10:05:26.755788 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 10:05:26.762489 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 10:05:26.765734 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 10:05:26.769119 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2541 10:05:26.775749 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2542 10:05:26.778874 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2543 10:05:26.782347 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 10:05:26.789254 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 10:05:26.792019 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 10:05:26.795077 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 10:05:26.802068 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 10:05:26.805370 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 10:05:26.808588 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 10:05:26.814952 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 10:05:26.818661 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 10:05:26.821686 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 10:05:26.828137 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 10:05:26.832168 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 10:05:26.834881 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2556 10:05:26.841389 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2557 10:05:26.845245 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2558 10:05:26.848114 Total UI for P1: 0, mck2ui 16
2559 10:05:26.851168 best dqsien dly found for B0: ( 1, 3, 26)
2560 10:05:26.854951 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 10:05:26.858249 Total UI for P1: 0, mck2ui 16
2562 10:05:26.861357 best dqsien dly found for B1: ( 1, 4, 0)
2563 10:05:26.864801 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2564 10:05:26.867985 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2565 10:05:26.868622
2566 10:05:26.875369 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2567 10:05:26.877851 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2568 10:05:26.878397 [Gating] SW calibration Done
2569 10:05:26.881244 ==
2570 10:05:26.884357 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 10:05:26.887926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 10:05:26.888422 ==
2573 10:05:26.888789 RX Vref Scan: 0
2574 10:05:26.889164
2575 10:05:26.891230 RX Vref 0 -> 0, step: 1
2576 10:05:26.891882
2577 10:05:26.894535 RX Delay -40 -> 252, step: 8
2578 10:05:26.897672 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2579 10:05:26.901400 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2580 10:05:26.907909 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2581 10:05:26.911147 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2582 10:05:26.914708 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2583 10:05:26.918041 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2584 10:05:26.920842 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2585 10:05:26.927420 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2586 10:05:26.930894 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2587 10:05:26.934226 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2588 10:05:26.937456 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2589 10:05:26.941062 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2590 10:05:26.947729 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2591 10:05:26.951105 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2592 10:05:26.954007 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2593 10:05:26.957515 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2594 10:05:26.957945 ==
2595 10:05:26.960938 Dram Type= 6, Freq= 0, CH_0, rank 0
2596 10:05:26.964441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2597 10:05:26.967573 ==
2598 10:05:26.967986 DQS Delay:
2599 10:05:26.968370 DQS0 = 0, DQS1 = 0
2600 10:05:26.970561 DQM Delay:
2601 10:05:26.970972 DQM0 = 117, DQM1 = 108
2602 10:05:26.974565 DQ Delay:
2603 10:05:26.977711 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2604 10:05:26.980784 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2605 10:05:26.984296 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2606 10:05:26.987531 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
2607 10:05:26.988015
2608 10:05:26.988514
2609 10:05:26.988843 ==
2610 10:05:26.990683 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 10:05:26.993943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 10:05:26.994521 ==
2613 10:05:26.997348
2614 10:05:26.997936
2615 10:05:26.998366 TX Vref Scan disable
2616 10:05:27.000474 == TX Byte 0 ==
2617 10:05:27.003955 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2618 10:05:27.007068 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2619 10:05:27.010767 == TX Byte 1 ==
2620 10:05:27.013822 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2621 10:05:27.017268 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2622 10:05:27.017748 ==
2623 10:05:27.020089 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 10:05:27.027166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 10:05:27.027728 ==
2626 10:05:27.038470 TX Vref=22, minBit 5, minWin=24, winSum=409
2627 10:05:27.042042 TX Vref=24, minBit 1, minWin=25, winSum=418
2628 10:05:27.044996 TX Vref=26, minBit 0, minWin=26, winSum=424
2629 10:05:27.048467 TX Vref=28, minBit 4, minWin=26, winSum=427
2630 10:05:27.051727 TX Vref=30, minBit 8, minWin=26, winSum=431
2631 10:05:27.055302 TX Vref=32, minBit 4, minWin=26, winSum=427
2632 10:05:27.061737 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 30
2633 10:05:27.062195
2634 10:05:27.065074 Final TX Range 1 Vref 30
2635 10:05:27.065545
2636 10:05:27.065977 ==
2637 10:05:27.068401 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 10:05:27.071654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 10:05:27.072106 ==
2640 10:05:27.074456
2641 10:05:27.074867
2642 10:05:27.075193 TX Vref Scan disable
2643 10:05:27.078098 == TX Byte 0 ==
2644 10:05:27.081517 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2645 10:05:27.087667 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2646 10:05:27.087779 == TX Byte 1 ==
2647 10:05:27.091068 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2648 10:05:27.097977 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2649 10:05:27.098058
2650 10:05:27.098122 [DATLAT]
2651 10:05:27.098193 Freq=1200, CH0 RK0
2652 10:05:27.098255
2653 10:05:27.100699 DATLAT Default: 0xd
2654 10:05:27.104713 0, 0xFFFF, sum = 0
2655 10:05:27.104823 1, 0xFFFF, sum = 0
2656 10:05:27.107211 2, 0xFFFF, sum = 0
2657 10:05:27.107292 3, 0xFFFF, sum = 0
2658 10:05:27.110664 4, 0xFFFF, sum = 0
2659 10:05:27.110755 5, 0xFFFF, sum = 0
2660 10:05:27.113985 6, 0xFFFF, sum = 0
2661 10:05:27.114058 7, 0xFFFF, sum = 0
2662 10:05:27.117369 8, 0xFFFF, sum = 0
2663 10:05:27.117438 9, 0xFFFF, sum = 0
2664 10:05:27.121156 10, 0xFFFF, sum = 0
2665 10:05:27.121225 11, 0xFFFF, sum = 0
2666 10:05:27.124216 12, 0x0, sum = 1
2667 10:05:27.124297 13, 0x0, sum = 2
2668 10:05:27.127511 14, 0x0, sum = 3
2669 10:05:27.127602 15, 0x0, sum = 4
2670 10:05:27.130801 best_step = 13
2671 10:05:27.130886
2672 10:05:27.130949 ==
2673 10:05:27.134202 Dram Type= 6, Freq= 0, CH_0, rank 0
2674 10:05:27.137464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2675 10:05:27.137545 ==
2676 10:05:27.140415 RX Vref Scan: 1
2677 10:05:27.140495
2678 10:05:27.140561 Set Vref Range= 32 -> 127
2679 10:05:27.140632
2680 10:05:27.143807 RX Vref 32 -> 127, step: 1
2681 10:05:27.143915
2682 10:05:27.146986 RX Delay -21 -> 252, step: 4
2683 10:05:27.147086
2684 10:05:27.150580 Set Vref, RX VrefLevel [Byte0]: 32
2685 10:05:27.153688 [Byte1]: 32
2686 10:05:27.153768
2687 10:05:27.157245 Set Vref, RX VrefLevel [Byte0]: 33
2688 10:05:27.160225 [Byte1]: 33
2689 10:05:27.164306
2690 10:05:27.164399 Set Vref, RX VrefLevel [Byte0]: 34
2691 10:05:27.167511 [Byte1]: 34
2692 10:05:27.172512
2693 10:05:27.172592 Set Vref, RX VrefLevel [Byte0]: 35
2694 10:05:27.175490 [Byte1]: 35
2695 10:05:27.179935
2696 10:05:27.180017 Set Vref, RX VrefLevel [Byte0]: 36
2697 10:05:27.183177 [Byte1]: 36
2698 10:05:27.188408
2699 10:05:27.188487 Set Vref, RX VrefLevel [Byte0]: 37
2700 10:05:27.191428 [Byte1]: 37
2701 10:05:27.196244
2702 10:05:27.196324 Set Vref, RX VrefLevel [Byte0]: 38
2703 10:05:27.199139 [Byte1]: 38
2704 10:05:27.204366
2705 10:05:27.204455 Set Vref, RX VrefLevel [Byte0]: 39
2706 10:05:27.207202 [Byte1]: 39
2707 10:05:27.212214
2708 10:05:27.212310 Set Vref, RX VrefLevel [Byte0]: 40
2709 10:05:27.215126 [Byte1]: 40
2710 10:05:27.219759
2711 10:05:27.219868 Set Vref, RX VrefLevel [Byte0]: 41
2712 10:05:27.222927 [Byte1]: 41
2713 10:05:27.227652
2714 10:05:27.227731 Set Vref, RX VrefLevel [Byte0]: 42
2715 10:05:27.231072 [Byte1]: 42
2716 10:05:27.235974
2717 10:05:27.236102 Set Vref, RX VrefLevel [Byte0]: 43
2718 10:05:27.239479 [Byte1]: 43
2719 10:05:27.243419
2720 10:05:27.243499 Set Vref, RX VrefLevel [Byte0]: 44
2721 10:05:27.247216 [Byte1]: 44
2722 10:05:27.251544
2723 10:05:27.251623 Set Vref, RX VrefLevel [Byte0]: 45
2724 10:05:27.254888 [Byte1]: 45
2725 10:05:27.259554
2726 10:05:27.259634 Set Vref, RX VrefLevel [Byte0]: 46
2727 10:05:27.262922 [Byte1]: 46
2728 10:05:27.267622
2729 10:05:27.267701 Set Vref, RX VrefLevel [Byte0]: 47
2730 10:05:27.271095 [Byte1]: 47
2731 10:05:27.275289
2732 10:05:27.275369 Set Vref, RX VrefLevel [Byte0]: 48
2733 10:05:27.278589 [Byte1]: 48
2734 10:05:27.283438
2735 10:05:27.283517 Set Vref, RX VrefLevel [Byte0]: 49
2736 10:05:27.286399 [Byte1]: 49
2737 10:05:27.291188
2738 10:05:27.291286 Set Vref, RX VrefLevel [Byte0]: 50
2739 10:05:27.294421 [Byte1]: 50
2740 10:05:27.299600
2741 10:05:27.299746 Set Vref, RX VrefLevel [Byte0]: 51
2742 10:05:27.302531 [Byte1]: 51
2743 10:05:27.307531
2744 10:05:27.307611 Set Vref, RX VrefLevel [Byte0]: 52
2745 10:05:27.310452 [Byte1]: 52
2746 10:05:27.314784
2747 10:05:27.314863 Set Vref, RX VrefLevel [Byte0]: 53
2748 10:05:27.318467 [Byte1]: 53
2749 10:05:27.323213
2750 10:05:27.323292 Set Vref, RX VrefLevel [Byte0]: 54
2751 10:05:27.326061 [Byte1]: 54
2752 10:05:27.330983
2753 10:05:27.331062 Set Vref, RX VrefLevel [Byte0]: 55
2754 10:05:27.333844 [Byte1]: 55
2755 10:05:27.338972
2756 10:05:27.339051 Set Vref, RX VrefLevel [Byte0]: 56
2757 10:05:27.341745 [Byte1]: 56
2758 10:05:27.346450
2759 10:05:27.346529 Set Vref, RX VrefLevel [Byte0]: 57
2760 10:05:27.349680 [Byte1]: 57
2761 10:05:27.354597
2762 10:05:27.354678 Set Vref, RX VrefLevel [Byte0]: 58
2763 10:05:27.358000 [Byte1]: 58
2764 10:05:27.362629
2765 10:05:27.362709 Set Vref, RX VrefLevel [Byte0]: 59
2766 10:05:27.366075 [Byte1]: 59
2767 10:05:27.370590
2768 10:05:27.370710 Set Vref, RX VrefLevel [Byte0]: 60
2769 10:05:27.373543 [Byte1]: 60
2770 10:05:27.378161
2771 10:05:27.378252 Set Vref, RX VrefLevel [Byte0]: 61
2772 10:05:27.381953 [Byte1]: 61
2773 10:05:27.386191
2774 10:05:27.386282 Set Vref, RX VrefLevel [Byte0]: 62
2775 10:05:27.389575 [Byte1]: 62
2776 10:05:27.393951
2777 10:05:27.394041 Set Vref, RX VrefLevel [Byte0]: 63
2778 10:05:27.397303 [Byte1]: 63
2779 10:05:27.401987
2780 10:05:27.402066 Set Vref, RX VrefLevel [Byte0]: 64
2781 10:05:27.405218 [Byte1]: 64
2782 10:05:27.410230
2783 10:05:27.410309 Set Vref, RX VrefLevel [Byte0]: 65
2784 10:05:27.413522 [Byte1]: 65
2785 10:05:27.417648
2786 10:05:27.417728 Set Vref, RX VrefLevel [Byte0]: 66
2787 10:05:27.421418 [Byte1]: 66
2788 10:05:27.426086
2789 10:05:27.426166 Set Vref, RX VrefLevel [Byte0]: 67
2790 10:05:27.429278 [Byte1]: 67
2791 10:05:27.433854
2792 10:05:27.433934 Set Vref, RX VrefLevel [Byte0]: 68
2793 10:05:27.437071 [Byte1]: 68
2794 10:05:27.441729
2795 10:05:27.441809 Final RX Vref Byte 0 = 53 to rank0
2796 10:05:27.444851 Final RX Vref Byte 1 = 44 to rank0
2797 10:05:27.448366 Final RX Vref Byte 0 = 53 to rank1
2798 10:05:27.451922 Final RX Vref Byte 1 = 44 to rank1==
2799 10:05:27.454855 Dram Type= 6, Freq= 0, CH_0, rank 0
2800 10:05:27.461467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2801 10:05:27.461636 ==
2802 10:05:27.461701 DQS Delay:
2803 10:05:27.461793 DQS0 = 0, DQS1 = 0
2804 10:05:27.464949 DQM Delay:
2805 10:05:27.465028 DQM0 = 117, DQM1 = 102
2806 10:05:27.468843 DQ Delay:
2807 10:05:27.471605 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2808 10:05:27.475106 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2809 10:05:27.478070 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2810 10:05:27.481278 DQ12 =110, DQ13 =106, DQ14 =112, DQ15 =110
2811 10:05:27.481358
2812 10:05:27.481421
2813 10:05:27.491231 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdf9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
2814 10:05:27.491313 CH0 RK0: MR19=303, MR18=FDF9
2815 10:05:27.498338 CH0_RK0: MR19=0x303, MR18=0xFDF9, DQSOSC=411, MR23=63, INC=38, DEC=25
2816 10:05:27.498418
2817 10:05:27.501354 ----->DramcWriteLeveling(PI) begin...
2818 10:05:27.501435 ==
2819 10:05:27.504977 Dram Type= 6, Freq= 0, CH_0, rank 1
2820 10:05:27.508089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2821 10:05:27.511192 ==
2822 10:05:27.515008 Write leveling (Byte 0): 33 => 33
2823 10:05:27.515088 Write leveling (Byte 1): 25 => 25
2824 10:05:27.518140 DramcWriteLeveling(PI) end<-----
2825 10:05:27.518220
2826 10:05:27.518288 ==
2827 10:05:27.521478 Dram Type= 6, Freq= 0, CH_0, rank 1
2828 10:05:27.527793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2829 10:05:27.527873 ==
2830 10:05:27.531043 [Gating] SW mode calibration
2831 10:05:27.538122 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2832 10:05:27.540885 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2833 10:05:27.548145 0 15 0 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
2834 10:05:27.551018 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2835 10:05:27.554381 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 10:05:27.560919 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 10:05:27.564402 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 10:05:27.567906 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 10:05:27.574346 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2840 10:05:27.577510 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
2841 10:05:27.581195 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2842 10:05:27.587679 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 10:05:27.590921 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 10:05:27.594439 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 10:05:27.600839 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 10:05:27.604669 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 10:05:27.607975 1 0 24 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
2848 10:05:27.611286 1 0 28 | B1->B0 | 2a2a 4545 | 0 1 | (0 0) (0 0)
2849 10:05:27.618161 1 1 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2850 10:05:27.621264 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 10:05:27.624417 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 10:05:27.631233 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 10:05:27.634397 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 10:05:27.637581 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 10:05:27.644339 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2856 10:05:27.647602 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2857 10:05:27.650600 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2858 10:05:27.657431 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 10:05:27.660453 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 10:05:27.664185 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 10:05:27.670576 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 10:05:27.673959 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 10:05:27.677268 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 10:05:27.683843 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 10:05:27.687001 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 10:05:27.690294 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 10:05:27.697227 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 10:05:27.700527 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 10:05:27.703863 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 10:05:27.710241 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 10:05:27.713364 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2872 10:05:27.716885 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2873 10:05:27.720124 Total UI for P1: 0, mck2ui 16
2874 10:05:27.723365 best dqsien dly found for B0: ( 1, 3, 24)
2875 10:05:27.730064 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2876 10:05:27.733277 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 10:05:27.737018 Total UI for P1: 0, mck2ui 16
2878 10:05:27.740151 best dqsien dly found for B1: ( 1, 4, 0)
2879 10:05:27.743297 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2880 10:05:27.746524 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2881 10:05:27.746940
2882 10:05:27.750020 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2883 10:05:27.753354 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2884 10:05:27.756696 [Gating] SW calibration Done
2885 10:05:27.757217 ==
2886 10:05:27.760085 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 10:05:27.763599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 10:05:27.766635 ==
2889 10:05:27.767051 RX Vref Scan: 0
2890 10:05:27.767380
2891 10:05:27.770054 RX Vref 0 -> 0, step: 1
2892 10:05:27.770470
2893 10:05:27.770797 RX Delay -40 -> 252, step: 8
2894 10:05:27.776843 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2895 10:05:27.780162 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2896 10:05:27.783464 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2897 10:05:27.786790 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2898 10:05:27.790395 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2899 10:05:27.796979 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2900 10:05:27.800356 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2901 10:05:27.803338 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2902 10:05:27.806715 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2903 10:05:27.809877 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2904 10:05:27.816485 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2905 10:05:27.819976 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2906 10:05:27.823543 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2907 10:05:27.827147 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2908 10:05:27.829846 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2909 10:05:27.836508 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2910 10:05:27.836927 ==
2911 10:05:27.840221 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 10:05:27.843214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 10:05:27.843645 ==
2914 10:05:27.843988 DQS Delay:
2915 10:05:27.846413 DQS0 = 0, DQS1 = 0
2916 10:05:27.846830 DQM Delay:
2917 10:05:27.850521 DQM0 = 116, DQM1 = 105
2918 10:05:27.850938 DQ Delay:
2919 10:05:27.853649 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2920 10:05:27.856440 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2921 10:05:27.859825 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2922 10:05:27.862984 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =111
2923 10:05:27.863645
2924 10:05:27.864275
2925 10:05:27.866483 ==
2926 10:05:27.869520 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 10:05:27.873033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 10:05:27.873450 ==
2929 10:05:27.873791
2930 10:05:27.874210
2931 10:05:27.876300 TX Vref Scan disable
2932 10:05:27.876752 == TX Byte 0 ==
2933 10:05:27.883077 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2934 10:05:27.885763 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2935 10:05:27.886310 == TX Byte 1 ==
2936 10:05:27.892358 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2937 10:05:27.896366 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2938 10:05:27.896783 ==
2939 10:05:27.898976 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 10:05:27.902283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 10:05:27.902841 ==
2942 10:05:27.915858 TX Vref=22, minBit 14, minWin=25, winSum=420
2943 10:05:27.919536 TX Vref=24, minBit 1, minWin=26, winSum=421
2944 10:05:27.922468 TX Vref=26, minBit 2, minWin=26, winSum=429
2945 10:05:27.925504 TX Vref=28, minBit 5, minWin=26, winSum=427
2946 10:05:27.928913 TX Vref=30, minBit 10, minWin=26, winSum=432
2947 10:05:27.935605 TX Vref=32, minBit 7, minWin=26, winSum=428
2948 10:05:27.938962 [TxChooseVref] Worse bit 10, Min win 26, Win sum 432, Final Vref 30
2949 10:05:27.939579
2950 10:05:27.942046 Final TX Range 1 Vref 30
2951 10:05:27.942623
2952 10:05:27.943234 ==
2953 10:05:27.945485 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 10:05:27.949333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 10:05:27.952135 ==
2956 10:05:27.952569
2957 10:05:27.952905
2958 10:05:27.953218 TX Vref Scan disable
2959 10:05:27.955874 == TX Byte 0 ==
2960 10:05:27.959167 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2961 10:05:27.965811 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2962 10:05:27.966235 == TX Byte 1 ==
2963 10:05:27.969048 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2964 10:05:27.975730 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2965 10:05:27.976319
2966 10:05:27.976799 [DATLAT]
2967 10:05:27.977257 Freq=1200, CH0 RK1
2968 10:05:27.977705
2969 10:05:27.979317 DATLAT Default: 0xd
2970 10:05:27.982485 0, 0xFFFF, sum = 0
2971 10:05:27.982915 1, 0xFFFF, sum = 0
2972 10:05:27.985862 2, 0xFFFF, sum = 0
2973 10:05:27.986289 3, 0xFFFF, sum = 0
2974 10:05:27.989180 4, 0xFFFF, sum = 0
2975 10:05:27.989608 5, 0xFFFF, sum = 0
2976 10:05:27.991945 6, 0xFFFF, sum = 0
2977 10:05:27.992425 7, 0xFFFF, sum = 0
2978 10:05:27.995367 8, 0xFFFF, sum = 0
2979 10:05:27.995794 9, 0xFFFF, sum = 0
2980 10:05:27.998602 10, 0xFFFF, sum = 0
2981 10:05:27.999028 11, 0xFFFF, sum = 0
2982 10:05:28.002087 12, 0x0, sum = 1
2983 10:05:28.002513 13, 0x0, sum = 2
2984 10:05:28.005380 14, 0x0, sum = 3
2985 10:05:28.005808 15, 0x0, sum = 4
2986 10:05:28.008459 best_step = 13
2987 10:05:28.008878
2988 10:05:28.009207 ==
2989 10:05:28.012001 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 10:05:28.015444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 10:05:28.015867 ==
2992 10:05:28.018855 RX Vref Scan: 0
2993 10:05:28.019275
2994 10:05:28.019608 RX Vref 0 -> 0, step: 1
2995 10:05:28.019921
2996 10:05:28.021884 RX Delay -21 -> 252, step: 4
2997 10:05:28.028366 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
2998 10:05:28.031745 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
2999 10:05:28.034800 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3000 10:05:28.038452 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3001 10:05:28.041653 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3002 10:05:28.048817 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3003 10:05:28.052094 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3004 10:05:28.055029 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3005 10:05:28.058238 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3006 10:05:28.061577 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3007 10:05:28.068387 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3008 10:05:28.071336 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3009 10:05:28.074747 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3010 10:05:28.078551 iDelay=195, Bit 13, Center 108 (43 ~ 174) 132
3011 10:05:28.081812 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3012 10:05:28.088541 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3013 10:05:28.088964 ==
3014 10:05:28.091498 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 10:05:28.094811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 10:05:28.095305 ==
3017 10:05:28.095653 DQS Delay:
3018 10:05:28.098486 DQS0 = 0, DQS1 = 0
3019 10:05:28.098905 DQM Delay:
3020 10:05:28.101649 DQM0 = 116, DQM1 = 104
3021 10:05:28.102069 DQ Delay:
3022 10:05:28.104981 DQ0 =114, DQ1 =116, DQ2 =112, DQ3 =112
3023 10:05:28.107836 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
3024 10:05:28.111584 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =96
3025 10:05:28.114598 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =110
3026 10:05:28.115019
3027 10:05:28.115349
3028 10:05:28.124560 [DQSOSCAuto] RK1, (LSB)MR18= 0xfbf9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
3029 10:05:28.128089 CH0 RK1: MR19=303, MR18=FBF9
3030 10:05:28.131237 CH0_RK1: MR19=0x303, MR18=0xFBF9, DQSOSC=412, MR23=63, INC=38, DEC=25
3031 10:05:28.134847 [RxdqsGatingPostProcess] freq 1200
3032 10:05:28.141395 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3033 10:05:28.144286 best DQS0 dly(2T, 0.5T) = (0, 11)
3034 10:05:28.147907 best DQS1 dly(2T, 0.5T) = (0, 12)
3035 10:05:28.151237 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3036 10:05:28.154324 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3037 10:05:28.158036 best DQS0 dly(2T, 0.5T) = (0, 11)
3038 10:05:28.161919 best DQS1 dly(2T, 0.5T) = (0, 12)
3039 10:05:28.164444 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3040 10:05:28.167804 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3041 10:05:28.170938 Pre-setting of DQS Precalculation
3042 10:05:28.174436 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3043 10:05:28.174888 ==
3044 10:05:28.177632 Dram Type= 6, Freq= 0, CH_1, rank 0
3045 10:05:28.181288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 10:05:28.181701 ==
3047 10:05:28.187837 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3048 10:05:28.194559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3049 10:05:28.202090 [CA 0] Center 38 (8~68) winsize 61
3050 10:05:28.205455 [CA 1] Center 38 (8~68) winsize 61
3051 10:05:28.209293 [CA 2] Center 35 (6~65) winsize 60
3052 10:05:28.212296 [CA 3] Center 34 (5~64) winsize 60
3053 10:05:28.215168 [CA 4] Center 35 (5~65) winsize 61
3054 10:05:28.219158 [CA 5] Center 33 (3~64) winsize 62
3055 10:05:28.219576
3056 10:05:28.222514 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3057 10:05:28.222922
3058 10:05:28.225172 [CATrainingPosCal] consider 1 rank data
3059 10:05:28.229044 u2DelayCellTimex100 = 270/100 ps
3060 10:05:28.231852 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3061 10:05:28.238795 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3062 10:05:28.241926 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3063 10:05:28.245029 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3064 10:05:28.248449 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3065 10:05:28.251883 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3066 10:05:28.252325
3067 10:05:28.254986 CA PerBit enable=1, Macro0, CA PI delay=33
3068 10:05:28.255536
3069 10:05:28.258664 [CBTSetCACLKResult] CA Dly = 33
3070 10:05:28.259078 CS Dly: 5 (0~36)
3071 10:05:28.261592 ==
3072 10:05:28.265032 Dram Type= 6, Freq= 0, CH_1, rank 1
3073 10:05:28.268189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 10:05:28.268621 ==
3075 10:05:28.271951 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3076 10:05:28.278169 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3077 10:05:28.288073 [CA 0] Center 37 (7~68) winsize 62
3078 10:05:28.291220 [CA 1] Center 38 (8~68) winsize 61
3079 10:05:28.294613 [CA 2] Center 35 (5~65) winsize 61
3080 10:05:28.297575 [CA 3] Center 33 (3~64) winsize 62
3081 10:05:28.301387 [CA 4] Center 33 (3~64) winsize 62
3082 10:05:28.304352 [CA 5] Center 33 (3~64) winsize 62
3083 10:05:28.304769
3084 10:05:28.307439 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3085 10:05:28.307857
3086 10:05:28.310869 [CATrainingPosCal] consider 2 rank data
3087 10:05:28.314350 u2DelayCellTimex100 = 270/100 ps
3088 10:05:28.317494 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3089 10:05:28.321224 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3090 10:05:28.327505 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3091 10:05:28.330858 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3092 10:05:28.333962 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3093 10:05:28.337662 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3094 10:05:28.338080
3095 10:05:28.340929 CA PerBit enable=1, Macro0, CA PI delay=33
3096 10:05:28.341345
3097 10:05:28.344211 [CBTSetCACLKResult] CA Dly = 33
3098 10:05:28.344628 CS Dly: 6 (0~38)
3099 10:05:28.344979
3100 10:05:28.347637 ----->DramcWriteLeveling(PI) begin...
3101 10:05:28.350771 ==
3102 10:05:28.354234 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 10:05:28.357635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 10:05:28.358053 ==
3105 10:05:28.360999 Write leveling (Byte 0): 27 => 27
3106 10:05:28.364209 Write leveling (Byte 1): 27 => 27
3107 10:05:28.367387 DramcWriteLeveling(PI) end<-----
3108 10:05:28.367804
3109 10:05:28.368169 ==
3110 10:05:28.370887 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 10:05:28.374275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 10:05:28.374722 ==
3113 10:05:28.377572 [Gating] SW mode calibration
3114 10:05:28.383944 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3115 10:05:28.390745 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3116 10:05:28.394016 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3117 10:05:28.397185 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 10:05:28.404007 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 10:05:28.407407 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 10:05:28.410360 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 10:05:28.417068 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 10:05:28.420614 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
3123 10:05:28.423740 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
3124 10:05:28.427471 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 10:05:28.433637 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 10:05:28.437208 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 10:05:28.440496 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 10:05:28.447170 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 10:05:28.450737 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 10:05:28.453599 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
3131 10:05:28.460845 1 0 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
3132 10:05:28.464173 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 10:05:28.467054 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 10:05:28.473897 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 10:05:28.477307 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 10:05:28.480999 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 10:05:28.486945 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 10:05:28.490460 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3139 10:05:28.493455 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3140 10:05:28.500275 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 10:05:28.503260 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 10:05:28.507006 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 10:05:28.513423 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 10:05:28.517079 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 10:05:28.520140 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 10:05:28.526470 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 10:05:28.530140 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 10:05:28.533479 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 10:05:28.540169 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 10:05:28.543132 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 10:05:28.546573 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 10:05:28.553333 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 10:05:28.556456 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 10:05:28.559969 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3155 10:05:28.566603 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3156 10:05:28.567025 Total UI for P1: 0, mck2ui 16
3157 10:05:28.573078 best dqsien dly found for B0: ( 1, 3, 24)
3158 10:05:28.576614 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 10:05:28.579467 Total UI for P1: 0, mck2ui 16
3160 10:05:28.583325 best dqsien dly found for B1: ( 1, 3, 28)
3161 10:05:28.586162 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3162 10:05:28.589307 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3163 10:05:28.589855
3164 10:05:28.593106 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3165 10:05:28.596548 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3166 10:05:28.599359 [Gating] SW calibration Done
3167 10:05:28.599881 ==
3168 10:05:28.602958 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 10:05:28.606031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 10:05:28.606451 ==
3171 10:05:28.609460 RX Vref Scan: 0
3172 10:05:28.609894
3173 10:05:28.612528 RX Vref 0 -> 0, step: 1
3174 10:05:28.612950
3175 10:05:28.613280 RX Delay -40 -> 252, step: 8
3176 10:05:28.619427 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3177 10:05:28.622432 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3178 10:05:28.626010 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3179 10:05:28.629267 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3180 10:05:28.632800 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3181 10:05:28.639423 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3182 10:05:28.642609 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3183 10:05:28.645762 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3184 10:05:28.649567 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3185 10:05:28.652632 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3186 10:05:28.659496 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3187 10:05:28.662771 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3188 10:05:28.665678 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3189 10:05:28.669086 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3190 10:05:28.676086 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3191 10:05:28.679595 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3192 10:05:28.680177 ==
3193 10:05:28.682440 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 10:05:28.685589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 10:05:28.686178 ==
3196 10:05:28.686710 DQS Delay:
3197 10:05:28.689371 DQS0 = 0, DQS1 = 0
3198 10:05:28.689797 DQM Delay:
3199 10:05:28.692610 DQM0 = 115, DQM1 = 113
3200 10:05:28.693025 DQ Delay:
3201 10:05:28.695716 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3202 10:05:28.699264 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3203 10:05:28.702635 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3204 10:05:28.705597 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3205 10:05:28.706029
3206 10:05:28.709068
3207 10:05:28.709479 ==
3208 10:05:28.712181 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 10:05:28.715723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 10:05:28.716179 ==
3211 10:05:28.716516
3212 10:05:28.716822
3213 10:05:28.719715 TX Vref Scan disable
3214 10:05:28.720157 == TX Byte 0 ==
3215 10:05:28.725377 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3216 10:05:28.728837 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3217 10:05:28.729286 == TX Byte 1 ==
3218 10:05:28.735531 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3219 10:05:28.738727 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3220 10:05:28.739408 ==
3221 10:05:28.742339 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 10:05:28.745666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 10:05:28.746257 ==
3224 10:05:28.757818 TX Vref=22, minBit 9, minWin=24, winSum=408
3225 10:05:28.761087 TX Vref=24, minBit 3, minWin=25, winSum=414
3226 10:05:28.764342 TX Vref=26, minBit 9, minWin=24, winSum=417
3227 10:05:28.767781 TX Vref=28, minBit 9, minWin=25, winSum=423
3228 10:05:28.770950 TX Vref=30, minBit 0, minWin=26, winSum=425
3229 10:05:28.777192 TX Vref=32, minBit 9, minWin=25, winSum=423
3230 10:05:28.780566 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 30
3231 10:05:28.781024
3232 10:05:28.783973 Final TX Range 1 Vref 30
3233 10:05:28.784092
3234 10:05:28.784220 ==
3235 10:05:28.787175 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 10:05:28.790426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 10:05:28.793583 ==
3238 10:05:28.793668
3239 10:05:28.793732
3240 10:05:28.793790 TX Vref Scan disable
3241 10:05:28.797015 == TX Byte 0 ==
3242 10:05:28.800321 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3243 10:05:28.807092 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3244 10:05:28.807173 == TX Byte 1 ==
3245 10:05:28.810153 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3246 10:05:28.816686 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3247 10:05:28.816768
3248 10:05:28.816831 [DATLAT]
3249 10:05:28.816891 Freq=1200, CH1 RK0
3250 10:05:28.816948
3251 10:05:28.819870 DATLAT Default: 0xd
3252 10:05:28.819950 0, 0xFFFF, sum = 0
3253 10:05:28.823421 1, 0xFFFF, sum = 0
3254 10:05:28.827121 2, 0xFFFF, sum = 0
3255 10:05:28.827208 3, 0xFFFF, sum = 0
3256 10:05:28.829801 4, 0xFFFF, sum = 0
3257 10:05:28.829882 5, 0xFFFF, sum = 0
3258 10:05:28.833311 6, 0xFFFF, sum = 0
3259 10:05:28.833394 7, 0xFFFF, sum = 0
3260 10:05:28.836591 8, 0xFFFF, sum = 0
3261 10:05:28.836682 9, 0xFFFF, sum = 0
3262 10:05:28.840058 10, 0xFFFF, sum = 0
3263 10:05:28.840153 11, 0xFFFF, sum = 0
3264 10:05:28.843632 12, 0x0, sum = 1
3265 10:05:28.843747 13, 0x0, sum = 2
3266 10:05:28.846802 14, 0x0, sum = 3
3267 10:05:28.846915 15, 0x0, sum = 4
3268 10:05:28.850010 best_step = 13
3269 10:05:28.850089
3270 10:05:28.850161 ==
3271 10:05:28.853378 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 10:05:28.856771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 10:05:28.856853 ==
3274 10:05:28.856915 RX Vref Scan: 1
3275 10:05:28.860009
3276 10:05:28.860131 Set Vref Range= 32 -> 127
3277 10:05:28.860196
3278 10:05:28.862944 RX Vref 32 -> 127, step: 1
3279 10:05:28.863025
3280 10:05:28.866220 RX Delay -13 -> 252, step: 4
3281 10:05:28.866300
3282 10:05:28.870115 Set Vref, RX VrefLevel [Byte0]: 32
3283 10:05:28.872998 [Byte1]: 32
3284 10:05:28.873080
3285 10:05:28.876336 Set Vref, RX VrefLevel [Byte0]: 33
3286 10:05:28.879797 [Byte1]: 33
3287 10:05:28.883092
3288 10:05:28.883173 Set Vref, RX VrefLevel [Byte0]: 34
3289 10:05:28.886618 [Byte1]: 34
3290 10:05:28.892097
3291 10:05:28.892179 Set Vref, RX VrefLevel [Byte0]: 35
3292 10:05:28.894315 [Byte1]: 35
3293 10:05:28.899074
3294 10:05:28.899156 Set Vref, RX VrefLevel [Byte0]: 36
3295 10:05:28.902167 [Byte1]: 36
3296 10:05:28.907126
3297 10:05:28.907207 Set Vref, RX VrefLevel [Byte0]: 37
3298 10:05:28.910281 [Byte1]: 37
3299 10:05:28.914984
3300 10:05:28.915063 Set Vref, RX VrefLevel [Byte0]: 38
3301 10:05:28.918080 [Byte1]: 38
3302 10:05:28.922732
3303 10:05:28.922812 Set Vref, RX VrefLevel [Byte0]: 39
3304 10:05:28.926446 [Byte1]: 39
3305 10:05:28.930714
3306 10:05:28.930794 Set Vref, RX VrefLevel [Byte0]: 40
3307 10:05:28.933897 [Byte1]: 40
3308 10:05:28.938529
3309 10:05:28.938609 Set Vref, RX VrefLevel [Byte0]: 41
3310 10:05:28.941700 [Byte1]: 41
3311 10:05:28.946253
3312 10:05:28.946333 Set Vref, RX VrefLevel [Byte0]: 42
3313 10:05:28.949689 [Byte1]: 42
3314 10:05:28.954117
3315 10:05:28.954197 Set Vref, RX VrefLevel [Byte0]: 43
3316 10:05:28.957325 [Byte1]: 43
3317 10:05:28.962139
3318 10:05:28.962219 Set Vref, RX VrefLevel [Byte0]: 44
3319 10:05:28.965147 [Byte1]: 44
3320 10:05:28.969906
3321 10:05:28.969985 Set Vref, RX VrefLevel [Byte0]: 45
3322 10:05:28.973053 [Byte1]: 45
3323 10:05:28.977916
3324 10:05:28.977995 Set Vref, RX VrefLevel [Byte0]: 46
3325 10:05:28.980915 [Byte1]: 46
3326 10:05:28.986068
3327 10:05:28.986147 Set Vref, RX VrefLevel [Byte0]: 47
3328 10:05:28.988935 [Byte1]: 47
3329 10:05:28.993720
3330 10:05:28.993800 Set Vref, RX VrefLevel [Byte0]: 48
3331 10:05:28.997128 [Byte1]: 48
3332 10:05:29.001374
3333 10:05:29.001454 Set Vref, RX VrefLevel [Byte0]: 49
3334 10:05:29.004848 [Byte1]: 49
3335 10:05:29.009367
3336 10:05:29.009448 Set Vref, RX VrefLevel [Byte0]: 50
3337 10:05:29.012671 [Byte1]: 50
3338 10:05:29.017471
3339 10:05:29.017551 Set Vref, RX VrefLevel [Byte0]: 51
3340 10:05:29.020365 [Byte1]: 51
3341 10:05:29.025001
3342 10:05:29.025106 Set Vref, RX VrefLevel [Byte0]: 52
3343 10:05:29.029187 [Byte1]: 52
3344 10:05:29.033093
3345 10:05:29.033172 Set Vref, RX VrefLevel [Byte0]: 53
3346 10:05:29.036174 [Byte1]: 53
3347 10:05:29.040963
3348 10:05:29.041043 Set Vref, RX VrefLevel [Byte0]: 54
3349 10:05:29.044013 [Byte1]: 54
3350 10:05:29.049061
3351 10:05:29.049139 Set Vref, RX VrefLevel [Byte0]: 55
3352 10:05:29.052265 [Byte1]: 55
3353 10:05:29.056596
3354 10:05:29.056670 Set Vref, RX VrefLevel [Byte0]: 56
3355 10:05:29.059966 [Byte1]: 56
3356 10:05:29.064563
3357 10:05:29.064639 Set Vref, RX VrefLevel [Byte0]: 57
3358 10:05:29.068010 [Byte1]: 57
3359 10:05:29.072931
3360 10:05:29.073003 Set Vref, RX VrefLevel [Byte0]: 58
3361 10:05:29.075925 [Byte1]: 58
3362 10:05:29.080267
3363 10:05:29.080337 Set Vref, RX VrefLevel [Byte0]: 59
3364 10:05:29.083537 [Byte1]: 59
3365 10:05:29.087968
3366 10:05:29.088103 Set Vref, RX VrefLevel [Byte0]: 60
3367 10:05:29.091542 [Byte1]: 60
3368 10:05:29.096080
3369 10:05:29.096162 Set Vref, RX VrefLevel [Byte0]: 61
3370 10:05:29.099387 [Byte1]: 61
3371 10:05:29.103823
3372 10:05:29.103904 Set Vref, RX VrefLevel [Byte0]: 62
3373 10:05:29.106966 [Byte1]: 62
3374 10:05:29.111696
3375 10:05:29.111783 Set Vref, RX VrefLevel [Byte0]: 63
3376 10:05:29.115242 [Byte1]: 63
3377 10:05:29.120121
3378 10:05:29.120202 Set Vref, RX VrefLevel [Byte0]: 64
3379 10:05:29.123026 [Byte1]: 64
3380 10:05:29.127473
3381 10:05:29.127553 Set Vref, RX VrefLevel [Byte0]: 65
3382 10:05:29.130661 [Byte1]: 65
3383 10:05:29.135595
3384 10:05:29.135677 Final RX Vref Byte 0 = 54 to rank0
3385 10:05:29.138717 Final RX Vref Byte 1 = 52 to rank0
3386 10:05:29.142369 Final RX Vref Byte 0 = 54 to rank1
3387 10:05:29.145498 Final RX Vref Byte 1 = 52 to rank1==
3388 10:05:29.148916 Dram Type= 6, Freq= 0, CH_1, rank 0
3389 10:05:29.155501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3390 10:05:29.155583 ==
3391 10:05:29.155648 DQS Delay:
3392 10:05:29.155708 DQS0 = 0, DQS1 = 0
3393 10:05:29.158563 DQM Delay:
3394 10:05:29.158643 DQM0 = 115, DQM1 = 113
3395 10:05:29.161800 DQ Delay:
3396 10:05:29.165057 DQ0 =122, DQ1 =112, DQ2 =106, DQ3 =114
3397 10:05:29.168571 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3398 10:05:29.172252 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3399 10:05:29.175585 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =122
3400 10:05:29.175665
3401 10:05:29.175729
3402 10:05:29.185110 [DQSOSCAuto] RK0, (LSB)MR18= 0xf501, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 414 ps
3403 10:05:29.185191 CH1 RK0: MR19=304, MR18=F501
3404 10:05:29.192385 CH1_RK0: MR19=0x304, MR18=0xF501, DQSOSC=409, MR23=63, INC=39, DEC=26
3405 10:05:29.192466
3406 10:05:29.195141 ----->DramcWriteLeveling(PI) begin...
3407 10:05:29.195212 ==
3408 10:05:29.198578 Dram Type= 6, Freq= 0, CH_1, rank 1
3409 10:05:29.201878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3410 10:05:29.205363 ==
3411 10:05:29.208715 Write leveling (Byte 0): 25 => 25
3412 10:05:29.208797 Write leveling (Byte 1): 29 => 29
3413 10:05:29.212245 DramcWriteLeveling(PI) end<-----
3414 10:05:29.212326
3415 10:05:29.212389 ==
3416 10:05:29.215284 Dram Type= 6, Freq= 0, CH_1, rank 1
3417 10:05:29.221629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3418 10:05:29.221711 ==
3419 10:05:29.224996 [Gating] SW mode calibration
3420 10:05:29.231931 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3421 10:05:29.235000 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3422 10:05:29.241508 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3423 10:05:29.244798 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3424 10:05:29.247989 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3425 10:05:29.254856 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3426 10:05:29.257908 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3427 10:05:29.261576 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3428 10:05:29.268152 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
3429 10:05:29.271241 0 15 28 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
3430 10:05:29.274816 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3431 10:05:29.281674 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3432 10:05:29.284777 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3433 10:05:29.287574 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3434 10:05:29.294222 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3435 10:05:29.297970 1 0 20 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
3436 10:05:29.301027 1 0 24 | B1->B0 | 2424 4646 | 1 0 | (0 0) (0 0)
3437 10:05:29.307800 1 0 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
3438 10:05:29.311406 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3439 10:05:29.314017 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3440 10:05:29.321110 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3441 10:05:29.324011 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3442 10:05:29.327411 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 10:05:29.333946 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 10:05:29.337329 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3445 10:05:29.340554 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3446 10:05:29.347575 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 10:05:29.350543 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 10:05:29.353569 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 10:05:29.359932 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 10:05:29.363651 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 10:05:29.366644 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 10:05:29.373546 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 10:05:29.376871 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 10:05:29.380381 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 10:05:29.386275 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 10:05:29.389547 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 10:05:29.392819 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 10:05:29.399626 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 10:05:29.402609 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3460 10:05:29.406396 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3461 10:05:29.413014 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3462 10:05:29.416238 Total UI for P1: 0, mck2ui 16
3463 10:05:29.419659 best dqsien dly found for B0: ( 1, 3, 22)
3464 10:05:29.422534 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 10:05:29.426461 Total UI for P1: 0, mck2ui 16
3466 10:05:29.429581 best dqsien dly found for B1: ( 1, 3, 28)
3467 10:05:29.432760 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3468 10:05:29.436548 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3469 10:05:29.436628
3470 10:05:29.439031 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3471 10:05:29.442676 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3472 10:05:29.446033 [Gating] SW calibration Done
3473 10:05:29.446113 ==
3474 10:05:29.448898 Dram Type= 6, Freq= 0, CH_1, rank 1
3475 10:05:29.455741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3476 10:05:29.455822 ==
3477 10:05:29.455886 RX Vref Scan: 0
3478 10:05:29.455945
3479 10:05:29.458726 RX Vref 0 -> 0, step: 1
3480 10:05:29.458819
3481 10:05:29.461803 RX Delay -40 -> 252, step: 8
3482 10:05:29.465437 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3483 10:05:29.468776 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3484 10:05:29.471692 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3485 10:05:29.478840 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3486 10:05:29.481624 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3487 10:05:29.485028 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3488 10:05:29.488715 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3489 10:05:29.491851 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3490 10:05:29.497998 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3491 10:05:29.501457 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3492 10:05:29.504678 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3493 10:05:29.508294 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3494 10:05:29.511606 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3495 10:05:29.517866 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3496 10:05:29.521103 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3497 10:05:29.524384 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3498 10:05:29.524465 ==
3499 10:05:29.527881 Dram Type= 6, Freq= 0, CH_1, rank 1
3500 10:05:29.531098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3501 10:05:29.534375 ==
3502 10:05:29.534455 DQS Delay:
3503 10:05:29.534531 DQS0 = 0, DQS1 = 0
3504 10:05:29.537668 DQM Delay:
3505 10:05:29.537752 DQM0 = 115, DQM1 = 111
3506 10:05:29.541368 DQ Delay:
3507 10:05:29.544635 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3508 10:05:29.548016 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3509 10:05:29.550880 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3510 10:05:29.554201 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3511 10:05:29.554283
3512 10:05:29.554347
3513 10:05:29.554406 ==
3514 10:05:29.557760 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 10:05:29.560650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 10:05:29.560733 ==
3517 10:05:29.564025
3518 10:05:29.564143
3519 10:05:29.564207 TX Vref Scan disable
3520 10:05:29.567289 == TX Byte 0 ==
3521 10:05:29.570991 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3522 10:05:29.574096 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3523 10:05:29.577036 == TX Byte 1 ==
3524 10:05:29.580999 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3525 10:05:29.583796 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3526 10:05:29.587332 ==
3527 10:05:29.587413 Dram Type= 6, Freq= 0, CH_1, rank 1
3528 10:05:29.593526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3529 10:05:29.593609 ==
3530 10:05:29.604580 TX Vref=22, minBit 2, minWin=25, winSum=423
3531 10:05:29.607969 TX Vref=24, minBit 9, minWin=25, winSum=427
3532 10:05:29.611555 TX Vref=26, minBit 1, minWin=26, winSum=429
3533 10:05:29.615099 TX Vref=28, minBit 1, minWin=26, winSum=431
3534 10:05:29.618398 TX Vref=30, minBit 9, minWin=26, winSum=434
3535 10:05:29.624864 TX Vref=32, minBit 2, minWin=26, winSum=432
3536 10:05:29.627924 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3537 10:05:29.628089
3538 10:05:29.631405 Final TX Range 1 Vref 30
3539 10:05:29.631578
3540 10:05:29.631715 ==
3541 10:05:29.634814 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 10:05:29.637998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 10:05:29.641421 ==
3544 10:05:29.641662
3545 10:05:29.641853
3546 10:05:29.642029 TX Vref Scan disable
3547 10:05:29.644877 == TX Byte 0 ==
3548 10:05:29.648361 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3549 10:05:29.651964 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3550 10:05:29.655115 == TX Byte 1 ==
3551 10:05:29.658714 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3552 10:05:29.664555 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3553 10:05:29.665130
3554 10:05:29.665598 [DATLAT]
3555 10:05:29.665926 Freq=1200, CH1 RK1
3556 10:05:29.666236
3557 10:05:29.668178 DATLAT Default: 0xd
3558 10:05:29.668625 0, 0xFFFF, sum = 0
3559 10:05:29.671471 1, 0xFFFF, sum = 0
3560 10:05:29.674552 2, 0xFFFF, sum = 0
3561 10:05:29.675183 3, 0xFFFF, sum = 0
3562 10:05:29.678030 4, 0xFFFF, sum = 0
3563 10:05:29.678419 5, 0xFFFF, sum = 0
3564 10:05:29.681253 6, 0xFFFF, sum = 0
3565 10:05:29.681726 7, 0xFFFF, sum = 0
3566 10:05:29.684127 8, 0xFFFF, sum = 0
3567 10:05:29.684565 9, 0xFFFF, sum = 0
3568 10:05:29.687553 10, 0xFFFF, sum = 0
3569 10:05:29.688013 11, 0xFFFF, sum = 0
3570 10:05:29.690790 12, 0x0, sum = 1
3571 10:05:29.691199 13, 0x0, sum = 2
3572 10:05:29.693921 14, 0x0, sum = 3
3573 10:05:29.694297 15, 0x0, sum = 4
3574 10:05:29.697372 best_step = 13
3575 10:05:29.697813
3576 10:05:29.698126 ==
3577 10:05:29.700883 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 10:05:29.704243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 10:05:29.704625 ==
3580 10:05:29.707399 RX Vref Scan: 0
3581 10:05:29.707795
3582 10:05:29.708193 RX Vref 0 -> 0, step: 1
3583 10:05:29.708513
3584 10:05:29.710459 RX Delay -13 -> 252, step: 4
3585 10:05:29.717167 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3586 10:05:29.720630 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3587 10:05:29.723873 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3588 10:05:29.726886 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3589 10:05:29.730709 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3590 10:05:29.737186 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3591 10:05:29.740630 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3592 10:05:29.743500 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3593 10:05:29.746902 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3594 10:05:29.750129 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3595 10:05:29.756998 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3596 10:05:29.760465 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3597 10:05:29.763129 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3598 10:05:29.766922 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3599 10:05:29.773168 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3600 10:05:29.776922 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3601 10:05:29.777355 ==
3602 10:05:29.779966 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 10:05:29.783135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 10:05:29.783554 ==
3605 10:05:29.786193 DQS Delay:
3606 10:05:29.786630 DQS0 = 0, DQS1 = 0
3607 10:05:29.786959 DQM Delay:
3608 10:05:29.789849 DQM0 = 115, DQM1 = 112
3609 10:05:29.790266 DQ Delay:
3610 10:05:29.792776 DQ0 =116, DQ1 =112, DQ2 =108, DQ3 =112
3611 10:05:29.796131 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3612 10:05:29.803049 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3613 10:05:29.805845 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =120
3614 10:05:29.806265
3615 10:05:29.806597
3616 10:05:29.812570 [DQSOSCAuto] RK1, (LSB)MR18= 0xf80a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3617 10:05:29.816162 CH1 RK1: MR19=304, MR18=F80A
3618 10:05:29.822695 CH1_RK1: MR19=0x304, MR18=0xF80A, DQSOSC=406, MR23=63, INC=39, DEC=26
3619 10:05:29.825843 [RxdqsGatingPostProcess] freq 1200
3620 10:05:29.832479 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3621 10:05:29.833140 best DQS0 dly(2T, 0.5T) = (0, 11)
3622 10:05:29.835551 best DQS1 dly(2T, 0.5T) = (0, 11)
3623 10:05:29.839507 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3624 10:05:29.842333 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3625 10:05:29.845597 best DQS0 dly(2T, 0.5T) = (0, 11)
3626 10:05:29.848972 best DQS1 dly(2T, 0.5T) = (0, 11)
3627 10:05:29.852065 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3628 10:05:29.855661 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3629 10:05:29.858870 Pre-setting of DQS Precalculation
3630 10:05:29.865238 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3631 10:05:29.872308 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3632 10:05:29.878726 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3633 10:05:29.879141
3634 10:05:29.879471
3635 10:05:29.881874 [Calibration Summary] 2400 Mbps
3636 10:05:29.882292 CH 0, Rank 0
3637 10:05:29.885137 SW Impedance : PASS
3638 10:05:29.888410 DUTY Scan : NO K
3639 10:05:29.888829 ZQ Calibration : PASS
3640 10:05:29.892002 Jitter Meter : NO K
3641 10:05:29.895201 CBT Training : PASS
3642 10:05:29.895616 Write leveling : PASS
3643 10:05:29.898330 RX DQS gating : PASS
3644 10:05:29.901432 RX DQ/DQS(RDDQC) : PASS
3645 10:05:29.901854 TX DQ/DQS : PASS
3646 10:05:29.904985 RX DATLAT : PASS
3647 10:05:29.907851 RX DQ/DQS(Engine): PASS
3648 10:05:29.908522 TX OE : NO K
3649 10:05:29.911344 All Pass.
3650 10:05:29.911853
3651 10:05:29.912373 CH 0, Rank 1
3652 10:05:29.914410 SW Impedance : PASS
3653 10:05:29.914826 DUTY Scan : NO K
3654 10:05:29.917871 ZQ Calibration : PASS
3655 10:05:29.921858 Jitter Meter : NO K
3656 10:05:29.922273 CBT Training : PASS
3657 10:05:29.924428 Write leveling : PASS
3658 10:05:29.927393 RX DQS gating : PASS
3659 10:05:29.927811 RX DQ/DQS(RDDQC) : PASS
3660 10:05:29.930868 TX DQ/DQS : PASS
3661 10:05:29.934161 RX DATLAT : PASS
3662 10:05:29.934577 RX DQ/DQS(Engine): PASS
3663 10:05:29.937580 TX OE : NO K
3664 10:05:29.937999 All Pass.
3665 10:05:29.938328
3666 10:05:29.940794 CH 1, Rank 0
3667 10:05:29.941210 SW Impedance : PASS
3668 10:05:29.944265 DUTY Scan : NO K
3669 10:05:29.947489 ZQ Calibration : PASS
3670 10:05:29.947903 Jitter Meter : NO K
3671 10:05:29.950635 CBT Training : PASS
3672 10:05:29.951052 Write leveling : PASS
3673 10:05:29.953781 RX DQS gating : PASS
3674 10:05:29.957461 RX DQ/DQS(RDDQC) : PASS
3675 10:05:29.957875 TX DQ/DQS : PASS
3676 10:05:29.960476 RX DATLAT : PASS
3677 10:05:29.963495 RX DQ/DQS(Engine): PASS
3678 10:05:29.963910 TX OE : NO K
3679 10:05:29.966901 All Pass.
3680 10:05:29.967314
3681 10:05:29.967641 CH 1, Rank 1
3682 10:05:29.970464 SW Impedance : PASS
3683 10:05:29.970877 DUTY Scan : NO K
3684 10:05:29.973647 ZQ Calibration : PASS
3685 10:05:29.977169 Jitter Meter : NO K
3686 10:05:29.977585 CBT Training : PASS
3687 10:05:29.980166 Write leveling : PASS
3688 10:05:29.983210 RX DQS gating : PASS
3689 10:05:29.983851 RX DQ/DQS(RDDQC) : PASS
3690 10:05:29.987147 TX DQ/DQS : PASS
3691 10:05:29.990376 RX DATLAT : PASS
3692 10:05:29.990818 RX DQ/DQS(Engine): PASS
3693 10:05:29.993422 TX OE : NO K
3694 10:05:29.993504 All Pass.
3695 10:05:29.993569
3696 10:05:29.996186 DramC Write-DBI off
3697 10:05:29.999563 PER_BANK_REFRESH: Hybrid Mode
3698 10:05:29.999643 TX_TRACKING: ON
3699 10:05:30.009252 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3700 10:05:30.012933 [FAST_K] Save calibration result to emmc
3701 10:05:30.016098 dramc_set_vcore_voltage set vcore to 650000
3702 10:05:30.019501 Read voltage for 600, 5
3703 10:05:30.019601 Vio18 = 0
3704 10:05:30.019682 Vcore = 650000
3705 10:05:30.022532 Vdram = 0
3706 10:05:30.022632 Vddq = 0
3707 10:05:30.022712 Vmddr = 0
3708 10:05:30.029333 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3709 10:05:30.032721 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3710 10:05:30.036021 MEM_TYPE=3, freq_sel=19
3711 10:05:30.039537 sv_algorithm_assistance_LP4_1600
3712 10:05:30.042527 ============ PULL DRAM RESETB DOWN ============
3713 10:05:30.049543 ========== PULL DRAM RESETB DOWN end =========
3714 10:05:30.052076 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3715 10:05:30.055543 ===================================
3716 10:05:30.059375 LPDDR4 DRAM CONFIGURATION
3717 10:05:30.062181 ===================================
3718 10:05:30.062554 EX_ROW_EN[0] = 0x0
3719 10:05:30.065766 EX_ROW_EN[1] = 0x0
3720 10:05:30.066146 LP4Y_EN = 0x0
3721 10:05:30.068945 WORK_FSP = 0x0
3722 10:05:30.069356 WL = 0x2
3723 10:05:30.072282 RL = 0x2
3724 10:05:30.075416 BL = 0x2
3725 10:05:30.075829 RPST = 0x0
3726 10:05:30.079439 RD_PRE = 0x0
3727 10:05:30.079850 WR_PRE = 0x1
3728 10:05:30.082071 WR_PST = 0x0
3729 10:05:30.082497 DBI_WR = 0x0
3730 10:05:30.085591 DBI_RD = 0x0
3731 10:05:30.086006 OTF = 0x1
3732 10:05:30.089229 ===================================
3733 10:05:30.092508 ===================================
3734 10:05:30.095436 ANA top config
3735 10:05:30.099356 ===================================
3736 10:05:30.099775 DLL_ASYNC_EN = 0
3737 10:05:30.102191 ALL_SLAVE_EN = 1
3738 10:05:30.105204 NEW_RANK_MODE = 1
3739 10:05:30.108289 DLL_IDLE_MODE = 1
3740 10:05:30.111730 LP45_APHY_COMB_EN = 1
3741 10:05:30.112177 TX_ODT_DIS = 1
3742 10:05:30.114810 NEW_8X_MODE = 1
3743 10:05:30.118351 ===================================
3744 10:05:30.121566 ===================================
3745 10:05:30.124637 data_rate = 1200
3746 10:05:30.128319 CKR = 1
3747 10:05:30.131752 DQ_P2S_RATIO = 8
3748 10:05:30.134512 ===================================
3749 10:05:30.137692 CA_P2S_RATIO = 8
3750 10:05:30.138109 DQ_CA_OPEN = 0
3751 10:05:30.141203 DQ_SEMI_OPEN = 0
3752 10:05:30.144274 CA_SEMI_OPEN = 0
3753 10:05:30.147797 CA_FULL_RATE = 0
3754 10:05:30.151336 DQ_CKDIV4_EN = 1
3755 10:05:30.154344 CA_CKDIV4_EN = 1
3756 10:05:30.154760 CA_PREDIV_EN = 0
3757 10:05:30.157520 PH8_DLY = 0
3758 10:05:30.161388 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3759 10:05:30.164197 DQ_AAMCK_DIV = 4
3760 10:05:30.167580 CA_AAMCK_DIV = 4
3761 10:05:30.170993 CA_ADMCK_DIV = 4
3762 10:05:30.171411 DQ_TRACK_CA_EN = 0
3763 10:05:30.174515 CA_PICK = 600
3764 10:05:30.177500 CA_MCKIO = 600
3765 10:05:30.180993 MCKIO_SEMI = 0
3766 10:05:30.184644 PLL_FREQ = 2288
3767 10:05:30.187226 DQ_UI_PI_RATIO = 32
3768 10:05:30.190610 CA_UI_PI_RATIO = 0
3769 10:05:30.194083 ===================================
3770 10:05:30.197878 ===================================
3771 10:05:30.198292 memory_type:LPDDR4
3772 10:05:30.200513 GP_NUM : 10
3773 10:05:30.203851 SRAM_EN : 1
3774 10:05:30.204309 MD32_EN : 0
3775 10:05:30.207007 ===================================
3776 10:05:30.210407 [ANA_INIT] >>>>>>>>>>>>>>
3777 10:05:30.213842 <<<<<< [CONFIGURE PHASE]: ANA_TX
3778 10:05:30.217014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3779 10:05:30.220669 ===================================
3780 10:05:30.223653 data_rate = 1200,PCW = 0X5800
3781 10:05:30.226683 ===================================
3782 10:05:30.229889 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3783 10:05:30.236362 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3784 10:05:30.239545 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3785 10:05:30.246424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3786 10:05:30.249388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3787 10:05:30.253054 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3788 10:05:30.253492 [ANA_INIT] flow start
3789 10:05:30.256350 [ANA_INIT] PLL >>>>>>>>
3790 10:05:30.259087 [ANA_INIT] PLL <<<<<<<<
3791 10:05:30.259504 [ANA_INIT] MIDPI >>>>>>>>
3792 10:05:30.262810 [ANA_INIT] MIDPI <<<<<<<<
3793 10:05:30.266089 [ANA_INIT] DLL >>>>>>>>
3794 10:05:30.266504 [ANA_INIT] flow end
3795 10:05:30.272823 ============ LP4 DIFF to SE enter ============
3796 10:05:30.275786 ============ LP4 DIFF to SE exit ============
3797 10:05:30.278902 [ANA_INIT] <<<<<<<<<<<<<
3798 10:05:30.282843 [Flow] Enable top DCM control >>>>>
3799 10:05:30.285710 [Flow] Enable top DCM control <<<<<
3800 10:05:30.289117 Enable DLL master slave shuffle
3801 10:05:30.292611 ==============================================================
3802 10:05:30.296262 Gating Mode config
3803 10:05:30.299270 ==============================================================
3804 10:05:30.302407 Config description:
3805 10:05:30.312146 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3806 10:05:30.318916 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3807 10:05:30.322304 SELPH_MODE 0: By rank 1: By Phase
3808 10:05:30.328449 ==============================================================
3809 10:05:30.331952 GAT_TRACK_EN = 1
3810 10:05:30.335130 RX_GATING_MODE = 2
3811 10:05:30.338640 RX_GATING_TRACK_MODE = 2
3812 10:05:30.341711 SELPH_MODE = 1
3813 10:05:30.345057 PICG_EARLY_EN = 1
3814 10:05:30.348625 VALID_LAT_VALUE = 1
3815 10:05:30.351614 ==============================================================
3816 10:05:30.354915 Enter into Gating configuration >>>>
3817 10:05:30.358700 Exit from Gating configuration <<<<
3818 10:05:30.361517 Enter into DVFS_PRE_config >>>>>
3819 10:05:30.374991 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3820 10:05:30.375455 Exit from DVFS_PRE_config <<<<<
3821 10:05:30.377835 Enter into PICG configuration >>>>
3822 10:05:30.381089 Exit from PICG configuration <<<<
3823 10:05:30.384466 [RX_INPUT] configuration >>>>>
3824 10:05:30.387685 [RX_INPUT] configuration <<<<<
3825 10:05:30.394292 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3826 10:05:30.397561 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3827 10:05:30.404497 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3828 10:05:30.411154 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3829 10:05:30.417315 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3830 10:05:30.424514 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3831 10:05:30.427555 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3832 10:05:30.430629 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3833 10:05:30.437227 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3834 10:05:30.440218 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3835 10:05:30.443726 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3836 10:05:30.447165 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3837 10:05:30.450564 ===================================
3838 10:05:30.453261 LPDDR4 DRAM CONFIGURATION
3839 10:05:30.456941 ===================================
3840 10:05:30.460290 EX_ROW_EN[0] = 0x0
3841 10:05:30.460706 EX_ROW_EN[1] = 0x0
3842 10:05:30.463608 LP4Y_EN = 0x0
3843 10:05:30.464074 WORK_FSP = 0x0
3844 10:05:30.466503 WL = 0x2
3845 10:05:30.466918 RL = 0x2
3846 10:05:30.469926 BL = 0x2
3847 10:05:30.473319 RPST = 0x0
3848 10:05:30.473735 RD_PRE = 0x0
3849 10:05:30.476629 WR_PRE = 0x1
3850 10:05:30.477045 WR_PST = 0x0
3851 10:05:30.480129 DBI_WR = 0x0
3852 10:05:30.480544 DBI_RD = 0x0
3853 10:05:30.483251 OTF = 0x1
3854 10:05:30.486083 ===================================
3855 10:05:30.489988 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3856 10:05:30.493394 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3857 10:05:30.499793 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3858 10:05:30.502978 ===================================
3859 10:05:30.503403 LPDDR4 DRAM CONFIGURATION
3860 10:05:30.505848 ===================================
3861 10:05:30.509433 EX_ROW_EN[0] = 0x10
3862 10:05:30.509878 EX_ROW_EN[1] = 0x0
3863 10:05:30.512639 LP4Y_EN = 0x0
3864 10:05:30.516310 WORK_FSP = 0x0
3865 10:05:30.516786 WL = 0x2
3866 10:05:30.519065 RL = 0x2
3867 10:05:30.519531 BL = 0x2
3868 10:05:30.522366 RPST = 0x0
3869 10:05:30.522835 RD_PRE = 0x0
3870 10:05:30.526003 WR_PRE = 0x1
3871 10:05:30.526436 WR_PST = 0x0
3872 10:05:30.529034 DBI_WR = 0x0
3873 10:05:30.529450 DBI_RD = 0x0
3874 10:05:30.532332 OTF = 0x1
3875 10:05:30.535441 ===================================
3876 10:05:30.541923 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3877 10:05:30.545151 nWR fixed to 30
3878 10:05:30.548680 [ModeRegInit_LP4] CH0 RK0
3879 10:05:30.549098 [ModeRegInit_LP4] CH0 RK1
3880 10:05:30.552080 [ModeRegInit_LP4] CH1 RK0
3881 10:05:30.555161 [ModeRegInit_LP4] CH1 RK1
3882 10:05:30.555589 match AC timing 17
3883 10:05:30.561672 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3884 10:05:30.565032 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3885 10:05:30.567993 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3886 10:05:30.574816 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3887 10:05:30.577835 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3888 10:05:30.578252 ==
3889 10:05:30.581737 Dram Type= 6, Freq= 0, CH_0, rank 0
3890 10:05:30.584629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3891 10:05:30.585052 ==
3892 10:05:30.590889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3893 10:05:30.597248 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3894 10:05:30.600698 [CA 0] Center 36 (6~67) winsize 62
3895 10:05:30.604146 [CA 1] Center 36 (5~67) winsize 63
3896 10:05:30.607467 [CA 2] Center 34 (4~65) winsize 62
3897 10:05:30.610598 [CA 3] Center 34 (4~65) winsize 62
3898 10:05:30.613696 [CA 4] Center 33 (3~64) winsize 62
3899 10:05:30.617210 [CA 5] Center 33 (3~64) winsize 62
3900 10:05:30.617291
3901 10:05:30.620628 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3902 10:05:30.620709
3903 10:05:30.623722 [CATrainingPosCal] consider 1 rank data
3904 10:05:30.626994 u2DelayCellTimex100 = 270/100 ps
3905 10:05:30.630519 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3906 10:05:30.633642 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3907 10:05:30.636617 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3908 10:05:30.643847 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3909 10:05:30.647117 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3910 10:05:30.649965 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3911 10:05:30.650046
3912 10:05:30.653168 CA PerBit enable=1, Macro0, CA PI delay=33
3913 10:05:30.653249
3914 10:05:30.656614 [CBTSetCACLKResult] CA Dly = 33
3915 10:05:30.656695 CS Dly: 6 (0~37)
3916 10:05:30.656759 ==
3917 10:05:30.660439 Dram Type= 6, Freq= 0, CH_0, rank 1
3918 10:05:30.666552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3919 10:05:30.666634 ==
3920 10:05:30.669908 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3921 10:05:30.676774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3922 10:05:30.679944 [CA 0] Center 36 (6~67) winsize 62
3923 10:05:30.683111 [CA 1] Center 36 (6~67) winsize 62
3924 10:05:30.686403 [CA 2] Center 34 (4~65) winsize 62
3925 10:05:30.690083 [CA 3] Center 34 (4~65) winsize 62
3926 10:05:30.693380 [CA 4] Center 34 (3~65) winsize 63
3927 10:05:30.695962 [CA 5] Center 33 (3~64) winsize 62
3928 10:05:30.696083
3929 10:05:30.699527 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3930 10:05:30.699627
3931 10:05:30.702792 [CATrainingPosCal] consider 2 rank data
3932 10:05:30.706110 u2DelayCellTimex100 = 270/100 ps
3933 10:05:30.712749 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3934 10:05:30.715975 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3935 10:05:30.719737 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3936 10:05:30.722422 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3937 10:05:30.726125 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3938 10:05:30.729126 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3939 10:05:30.729334
3940 10:05:30.732373 CA PerBit enable=1, Macro0, CA PI delay=33
3941 10:05:30.732593
3942 10:05:30.735614 [CBTSetCACLKResult] CA Dly = 33
3943 10:05:30.739418 CS Dly: 6 (0~37)
3944 10:05:30.739810
3945 10:05:30.742849 ----->DramcWriteLeveling(PI) begin...
3946 10:05:30.743207 ==
3947 10:05:30.745779 Dram Type= 6, Freq= 0, CH_0, rank 0
3948 10:05:30.749328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3949 10:05:30.749747 ==
3950 10:05:30.752710 Write leveling (Byte 0): 34 => 34
3951 10:05:30.756202 Write leveling (Byte 1): 30 => 30
3952 10:05:30.759482 DramcWriteLeveling(PI) end<-----
3953 10:05:30.760075
3954 10:05:30.760442 ==
3955 10:05:30.762493 Dram Type= 6, Freq= 0, CH_0, rank 0
3956 10:05:30.765451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3957 10:05:30.765868 ==
3958 10:05:30.768991 [Gating] SW mode calibration
3959 10:05:30.775546 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3960 10:05:30.781936 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3961 10:05:30.785177 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3962 10:05:30.792087 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3963 10:05:30.795308 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3964 10:05:30.798487 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
3965 10:05:30.805093 0 9 16 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (1 1)
3966 10:05:30.808621 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3967 10:05:30.811998 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3968 10:05:30.818555 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 10:05:30.821628 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 10:05:30.824536 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 10:05:30.831602 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 10:05:30.834515 0 10 12 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
3973 10:05:30.837868 0 10 16 | B1->B0 | 3c3c 4141 | 0 0 | (0 0) (0 0)
3974 10:05:30.844648 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3975 10:05:30.847709 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3976 10:05:30.851089 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 10:05:30.857814 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 10:05:30.861244 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 10:05:30.864946 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 10:05:30.870793 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3981 10:05:30.874226 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3982 10:05:30.877327 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 10:05:30.883814 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 10:05:30.887781 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 10:05:30.890795 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 10:05:30.897335 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 10:05:30.900348 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 10:05:30.903681 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 10:05:30.910180 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 10:05:30.913742 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 10:05:30.916662 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 10:05:30.923356 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 10:05:30.926742 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 10:05:30.929949 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 10:05:30.936845 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 10:05:30.939531 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 10:05:30.943348 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3998 10:05:30.946307 Total UI for P1: 0, mck2ui 16
3999 10:05:30.949815 best dqsien dly found for B0: ( 0, 13, 14)
4000 10:05:30.956329 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 10:05:30.956764 Total UI for P1: 0, mck2ui 16
4002 10:05:30.962887 best dqsien dly found for B1: ( 0, 13, 16)
4003 10:05:30.966359 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4004 10:05:30.969366 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4005 10:05:30.969801
4006 10:05:30.972517 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4007 10:05:30.975703 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4008 10:05:30.979524 [Gating] SW calibration Done
4009 10:05:30.979960 ==
4010 10:05:30.982675 Dram Type= 6, Freq= 0, CH_0, rank 0
4011 10:05:30.985577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 10:05:30.986015 ==
4013 10:05:30.988788 RX Vref Scan: 0
4014 10:05:30.988872
4015 10:05:30.991898 RX Vref 0 -> 0, step: 1
4016 10:05:30.992002
4017 10:05:30.992107 RX Delay -230 -> 252, step: 16
4018 10:05:30.998744 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4019 10:05:31.001830 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4020 10:05:31.005053 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4021 10:05:31.008551 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4022 10:05:31.014759 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4023 10:05:31.018690 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4024 10:05:31.022035 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4025 10:05:31.025003 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4026 10:05:31.031335 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4027 10:05:31.034567 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4028 10:05:31.038252 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4029 10:05:31.041544 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4030 10:05:31.047980 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4031 10:05:31.051210 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4032 10:05:31.054610 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4033 10:05:31.057593 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4034 10:05:31.057719 ==
4035 10:05:31.061041 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 10:05:31.067903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 10:05:31.068080 ==
4038 10:05:31.068202 DQS Delay:
4039 10:05:31.070896 DQS0 = 0, DQS1 = 0
4040 10:05:31.071067 DQM Delay:
4041 10:05:31.074210 DQM0 = 40, DQM1 = 32
4042 10:05:31.074415 DQ Delay:
4043 10:05:31.078007 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4044 10:05:31.081035 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4045 10:05:31.084792 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4046 10:05:31.087860 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =33
4047 10:05:31.088220
4048 10:05:31.088468
4049 10:05:31.088722 ==
4050 10:05:31.091069 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 10:05:31.094175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 10:05:31.094664 ==
4053 10:05:31.095019
4054 10:05:31.095368
4055 10:05:31.097689 TX Vref Scan disable
4056 10:05:31.101086 == TX Byte 0 ==
4057 10:05:31.104538 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4058 10:05:31.107419 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4059 10:05:31.110924 == TX Byte 1 ==
4060 10:05:31.114409 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4061 10:05:31.117689 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4062 10:05:31.118105 ==
4063 10:05:31.120771 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 10:05:31.127399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 10:05:31.127819 ==
4066 10:05:31.128191
4067 10:05:31.128505
4068 10:05:31.128801 TX Vref Scan disable
4069 10:05:31.131896 == TX Byte 0 ==
4070 10:05:31.135279 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4071 10:05:31.141822 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4072 10:05:31.142239 == TX Byte 1 ==
4073 10:05:31.145017 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4074 10:05:31.151681 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4075 10:05:31.152156
4076 10:05:31.152487 [DATLAT]
4077 10:05:31.152791 Freq=600, CH0 RK0
4078 10:05:31.153084
4079 10:05:31.154711 DATLAT Default: 0x9
4080 10:05:31.155123 0, 0xFFFF, sum = 0
4081 10:05:31.158051 1, 0xFFFF, sum = 0
4082 10:05:31.161599 2, 0xFFFF, sum = 0
4083 10:05:31.162057 3, 0xFFFF, sum = 0
4084 10:05:31.164659 4, 0xFFFF, sum = 0
4085 10:05:31.165083 5, 0xFFFF, sum = 0
4086 10:05:31.168309 6, 0xFFFF, sum = 0
4087 10:05:31.168739 7, 0xFFFF, sum = 0
4088 10:05:31.171491 8, 0x0, sum = 1
4089 10:05:31.171912 9, 0x0, sum = 2
4090 10:05:31.172276 10, 0x0, sum = 3
4091 10:05:31.174349 11, 0x0, sum = 4
4092 10:05:31.174769 best_step = 9
4093 10:05:31.175099
4094 10:05:31.178251 ==
4095 10:05:31.178671 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 10:05:31.184327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 10:05:31.184746 ==
4098 10:05:31.185224 RX Vref Scan: 1
4099 10:05:31.185703
4100 10:05:31.188015 RX Vref 0 -> 0, step: 1
4101 10:05:31.188628
4102 10:05:31.191049 RX Delay -195 -> 252, step: 8
4103 10:05:31.191463
4104 10:05:31.194423 Set Vref, RX VrefLevel [Byte0]: 53
4105 10:05:31.197555 [Byte1]: 44
4106 10:05:31.197969
4107 10:05:31.200705 Final RX Vref Byte 0 = 53 to rank0
4108 10:05:31.204340 Final RX Vref Byte 1 = 44 to rank0
4109 10:05:31.207880 Final RX Vref Byte 0 = 53 to rank1
4110 10:05:31.210810 Final RX Vref Byte 1 = 44 to rank1==
4111 10:05:31.214393 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 10:05:31.217316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 10:05:31.220572 ==
4114 10:05:31.220982 DQS Delay:
4115 10:05:31.221308 DQS0 = 0, DQS1 = 0
4116 10:05:31.224025 DQM Delay:
4117 10:05:31.224464 DQM0 = 41, DQM1 = 33
4118 10:05:31.227349 DQ Delay:
4119 10:05:31.227762 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4120 10:05:31.230787 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4121 10:05:31.234268 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4122 10:05:31.237233 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4123 10:05:31.237646
4124 10:05:31.241120
4125 10:05:31.247602 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c43, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
4126 10:05:31.250452 CH0 RK0: MR19=808, MR18=4C43
4127 10:05:31.257544 CH0_RK0: MR19=0x808, MR18=0x4C43, DQSOSC=395, MR23=63, INC=168, DEC=112
4128 10:05:31.257958
4129 10:05:31.261597 ----->DramcWriteLeveling(PI) begin...
4130 10:05:31.262020 ==
4131 10:05:31.263741 Dram Type= 6, Freq= 0, CH_0, rank 1
4132 10:05:31.266998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 10:05:31.267414 ==
4134 10:05:31.270471 Write leveling (Byte 0): 35 => 35
4135 10:05:31.273534 Write leveling (Byte 1): 31 => 31
4136 10:05:31.277002 DramcWriteLeveling(PI) end<-----
4137 10:05:31.277415
4138 10:05:31.277743 ==
4139 10:05:31.280705 Dram Type= 6, Freq= 0, CH_0, rank 1
4140 10:05:31.283917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 10:05:31.284368 ==
4142 10:05:31.286830 [Gating] SW mode calibration
4143 10:05:31.293451 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4144 10:05:31.300024 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4145 10:05:31.303204 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4146 10:05:31.309767 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4147 10:05:31.313340 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4148 10:05:31.316453 0 9 12 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (0 1)
4149 10:05:31.323244 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
4150 10:05:31.326117 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4151 10:05:31.329305 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4152 10:05:31.336387 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4153 10:05:31.339625 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 10:05:31.342923 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 10:05:31.349383 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 10:05:31.352503 0 10 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (0 0)
4157 10:05:31.355668 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4158 10:05:31.362547 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4159 10:05:31.365664 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4160 10:05:31.368919 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4161 10:05:31.375298 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 10:05:31.379095 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 10:05:31.382371 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 10:05:31.388924 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 10:05:31.392255 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 10:05:31.395032 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 10:05:31.402108 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 10:05:31.405205 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 10:05:31.408444 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 10:05:31.414789 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 10:05:31.418081 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 10:05:31.421296 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 10:05:31.428127 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 10:05:31.431290 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 10:05:31.434811 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 10:05:31.441147 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 10:05:31.444272 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 10:05:31.447937 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 10:05:31.454294 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4180 10:05:31.457624 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4181 10:05:31.461017 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 10:05:31.464486 Total UI for P1: 0, mck2ui 16
4183 10:05:31.467876 best dqsien dly found for B0: ( 0, 13, 10)
4184 10:05:31.471092 Total UI for P1: 0, mck2ui 16
4185 10:05:31.474625 best dqsien dly found for B1: ( 0, 13, 14)
4186 10:05:31.477420 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4187 10:05:31.484536 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4188 10:05:31.484958
4189 10:05:31.487080 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4190 10:05:31.490708 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4191 10:05:31.494104 [Gating] SW calibration Done
4192 10:05:31.494521 ==
4193 10:05:31.497018 Dram Type= 6, Freq= 0, CH_0, rank 1
4194 10:05:31.500357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 10:05:31.500784 ==
4196 10:05:31.503579 RX Vref Scan: 0
4197 10:05:31.503998
4198 10:05:31.504384 RX Vref 0 -> 0, step: 1
4199 10:05:31.504697
4200 10:05:31.506901 RX Delay -230 -> 252, step: 16
4201 10:05:31.510158 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4202 10:05:31.516950 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4203 10:05:31.519946 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4204 10:05:31.523580 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4205 10:05:31.526593 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4206 10:05:31.533770 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4207 10:05:31.536882 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4208 10:05:31.540130 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4209 10:05:31.543736 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4210 10:05:31.546624 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4211 10:05:31.553348 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4212 10:05:31.556395 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4213 10:05:31.559535 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4214 10:05:31.566219 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4215 10:05:31.569501 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4216 10:05:31.573119 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4217 10:05:31.573540 ==
4218 10:05:31.575992 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 10:05:31.579357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 10:05:31.582324 ==
4221 10:05:31.582740 DQS Delay:
4222 10:05:31.583070 DQS0 = 0, DQS1 = 0
4223 10:05:31.585600 DQM Delay:
4224 10:05:31.586014 DQM0 = 41, DQM1 = 32
4225 10:05:31.589366 DQ Delay:
4226 10:05:31.589784 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4227 10:05:31.592771 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4228 10:05:31.595448 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4229 10:05:31.598814 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4230 10:05:31.602180
4231 10:05:31.602597
4232 10:05:31.602926 ==
4233 10:05:31.605558 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 10:05:31.608862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 10:05:31.609281 ==
4236 10:05:31.609622
4237 10:05:31.609930
4238 10:05:31.612310 TX Vref Scan disable
4239 10:05:31.612725 == TX Byte 0 ==
4240 10:05:31.618924 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4241 10:05:31.621842 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4242 10:05:31.622261 == TX Byte 1 ==
4243 10:05:31.628455 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4244 10:05:31.632074 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4245 10:05:31.632501 ==
4246 10:05:31.634980 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 10:05:31.638502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 10:05:31.639115 ==
4249 10:05:31.639605
4250 10:05:31.642036
4251 10:05:31.642496 TX Vref Scan disable
4252 10:05:31.645628 == TX Byte 0 ==
4253 10:05:31.648407 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4254 10:05:31.656128 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4255 10:05:31.656552 == TX Byte 1 ==
4256 10:05:31.658674 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4257 10:05:31.665470 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4258 10:05:31.665891
4259 10:05:31.666231 [DATLAT]
4260 10:05:31.666737 Freq=600, CH0 RK1
4261 10:05:31.667069
4262 10:05:31.668754 DATLAT Default: 0x9
4263 10:05:31.669172 0, 0xFFFF, sum = 0
4264 10:05:31.671844 1, 0xFFFF, sum = 0
4265 10:05:31.675147 2, 0xFFFF, sum = 0
4266 10:05:31.675567 3, 0xFFFF, sum = 0
4267 10:05:31.678255 4, 0xFFFF, sum = 0
4268 10:05:31.678674 5, 0xFFFF, sum = 0
4269 10:05:31.681533 6, 0xFFFF, sum = 0
4270 10:05:31.682036 7, 0xFFFF, sum = 0
4271 10:05:31.684961 8, 0x0, sum = 1
4272 10:05:31.685386 9, 0x0, sum = 2
4273 10:05:31.685719 10, 0x0, sum = 3
4274 10:05:31.688143 11, 0x0, sum = 4
4275 10:05:31.688569 best_step = 9
4276 10:05:31.688943
4277 10:05:31.691406 ==
4278 10:05:31.691823 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 10:05:31.698404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 10:05:31.698824 ==
4281 10:05:31.699152 RX Vref Scan: 0
4282 10:05:31.699458
4283 10:05:31.701305 RX Vref 0 -> 0, step: 1
4284 10:05:31.701722
4285 10:05:31.704861 RX Delay -195 -> 252, step: 8
4286 10:05:31.711332 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4287 10:05:31.714486 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4288 10:05:31.718332 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4289 10:05:31.721109 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4290 10:05:31.727809 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4291 10:05:31.730806 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4292 10:05:31.733959 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4293 10:05:31.737432 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4294 10:05:31.740820 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4295 10:05:31.747041 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4296 10:05:31.751250 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4297 10:05:31.753759 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4298 10:05:31.757100 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4299 10:05:31.763888 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4300 10:05:31.767152 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4301 10:05:31.770078 iDelay=205, Bit 15, Center 40 (-107 ~ 188) 296
4302 10:05:31.770488 ==
4303 10:05:31.773374 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 10:05:31.777237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 10:05:31.780070 ==
4306 10:05:31.780486 DQS Delay:
4307 10:05:31.780839 DQS0 = 0, DQS1 = 0
4308 10:05:31.783568 DQM Delay:
4309 10:05:31.783972 DQM0 = 41, DQM1 = 33
4310 10:05:31.786888 DQ Delay:
4311 10:05:31.790035 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4312 10:05:31.792956 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4313 10:05:31.796682 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4314 10:05:31.799285 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4315 10:05:31.799358
4316 10:05:31.799418
4317 10:05:31.805803 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d39, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4318 10:05:31.809091 CH0 RK1: MR19=808, MR18=3D39
4319 10:05:31.816308 CH0_RK1: MR19=0x808, MR18=0x3D39, DQSOSC=398, MR23=63, INC=165, DEC=110
4320 10:05:31.818958 [RxdqsGatingPostProcess] freq 600
4321 10:05:31.822536 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4322 10:05:31.825931 Pre-setting of DQS Precalculation
4323 10:05:31.832003 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4324 10:05:31.832103 ==
4325 10:05:31.835798 Dram Type= 6, Freq= 0, CH_1, rank 0
4326 10:05:31.839232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 10:05:31.839643 ==
4328 10:05:31.846075 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4329 10:05:31.852692 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4330 10:05:31.856003 [CA 0] Center 36 (6~66) winsize 61
4331 10:05:31.859314 [CA 1] Center 35 (5~66) winsize 62
4332 10:05:31.862289 [CA 2] Center 34 (4~65) winsize 62
4333 10:05:31.865966 [CA 3] Center 34 (4~65) winsize 62
4334 10:05:31.868749 [CA 4] Center 34 (4~65) winsize 62
4335 10:05:31.871923 [CA 5] Center 34 (3~65) winsize 63
4336 10:05:31.872353
4337 10:05:31.875706 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4338 10:05:31.876160
4339 10:05:31.878880 [CATrainingPosCal] consider 1 rank data
4340 10:05:31.882021 u2DelayCellTimex100 = 270/100 ps
4341 10:05:31.885300 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4342 10:05:31.888594 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4343 10:05:31.891823 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4344 10:05:31.894966 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4345 10:05:31.898375 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4346 10:05:31.905319 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4347 10:05:31.905725
4348 10:05:31.908241 CA PerBit enable=1, Macro0, CA PI delay=34
4349 10:05:31.908722
4350 10:05:31.911644 [CBTSetCACLKResult] CA Dly = 34
4351 10:05:31.911997 CS Dly: 4 (0~35)
4352 10:05:31.912331 ==
4353 10:05:31.914991 Dram Type= 6, Freq= 0, CH_1, rank 1
4354 10:05:31.918359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 10:05:31.921771 ==
4356 10:05:31.924923 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4357 10:05:31.931501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4358 10:05:31.935031 [CA 0] Center 35 (5~66) winsize 62
4359 10:05:31.937659 [CA 1] Center 35 (5~66) winsize 62
4360 10:05:31.941233 [CA 2] Center 34 (4~65) winsize 62
4361 10:05:31.944180 [CA 3] Center 33 (3~64) winsize 62
4362 10:05:31.947406 [CA 4] Center 34 (3~65) winsize 63
4363 10:05:31.950893 [CA 5] Center 33 (3~64) winsize 62
4364 10:05:31.951300
4365 10:05:31.953913 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4366 10:05:31.954324
4367 10:05:31.957421 [CATrainingPosCal] consider 2 rank data
4368 10:05:31.961049 u2DelayCellTimex100 = 270/100 ps
4369 10:05:31.964562 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4370 10:05:31.967585 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4371 10:05:31.973843 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4372 10:05:31.977428 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4373 10:05:31.980431 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4374 10:05:31.983686 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4375 10:05:31.984313
4376 10:05:31.987472 CA PerBit enable=1, Macro0, CA PI delay=33
4377 10:05:31.987876
4378 10:05:31.990756 [CBTSetCACLKResult] CA Dly = 33
4379 10:05:31.991169 CS Dly: 4 (0~36)
4380 10:05:31.991487
4381 10:05:31.996935 ----->DramcWriteLeveling(PI) begin...
4382 10:05:31.997347 ==
4383 10:05:32.000646 Dram Type= 6, Freq= 0, CH_1, rank 0
4384 10:05:32.003867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 10:05:32.004341 ==
4386 10:05:32.006798 Write leveling (Byte 0): 27 => 27
4387 10:05:32.010282 Write leveling (Byte 1): 32 => 32
4388 10:05:32.013779 DramcWriteLeveling(PI) end<-----
4389 10:05:32.014322
4390 10:05:32.014793 ==
4391 10:05:32.016935 Dram Type= 6, Freq= 0, CH_1, rank 0
4392 10:05:32.020506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 10:05:32.021007 ==
4394 10:05:32.023667 [Gating] SW mode calibration
4395 10:05:32.030124 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4396 10:05:32.036645 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4397 10:05:32.040224 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4398 10:05:32.043061 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4399 10:05:32.050395 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4400 10:05:32.053384 0 9 12 | B1->B0 | 3030 3131 | 0 0 | (0 1) (1 1)
4401 10:05:32.056314 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 10:05:32.063205 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 10:05:32.066419 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 10:05:32.069902 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 10:05:32.076117 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 10:05:32.079656 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 10:05:32.082808 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 10:05:32.089357 0 10 12 | B1->B0 | 2c2c 3737 | 0 1 | (0 0) (0 0)
4409 10:05:32.092644 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 10:05:32.095988 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 10:05:32.102533 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 10:05:32.106213 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 10:05:32.109078 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 10:05:32.115581 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 10:05:32.119118 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 10:05:32.121981 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4417 10:05:32.128928 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 10:05:32.132438 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 10:05:32.135804 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 10:05:32.141809 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 10:05:32.145194 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 10:05:32.148497 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 10:05:32.155097 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 10:05:32.158375 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 10:05:32.161764 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 10:05:32.168461 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 10:05:32.171486 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 10:05:32.174837 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 10:05:32.181696 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 10:05:32.184518 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 10:05:32.187651 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 10:05:32.194586 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4433 10:05:32.197646 Total UI for P1: 0, mck2ui 16
4434 10:05:32.201102 best dqsien dly found for B0: ( 0, 13, 10)
4435 10:05:32.204051 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 10:05:32.207404 Total UI for P1: 0, mck2ui 16
4437 10:05:32.211079 best dqsien dly found for B1: ( 0, 13, 12)
4438 10:05:32.214547 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4439 10:05:32.218148 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4440 10:05:32.218346
4441 10:05:32.221013 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4442 10:05:32.227481 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4443 10:05:32.227788 [Gating] SW calibration Done
4444 10:05:32.228154 ==
4445 10:05:32.231060 Dram Type= 6, Freq= 0, CH_1, rank 0
4446 10:05:32.237711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4447 10:05:32.238347 ==
4448 10:05:32.238776 RX Vref Scan: 0
4449 10:05:32.239214
4450 10:05:32.241071 RX Vref 0 -> 0, step: 1
4451 10:05:32.241656
4452 10:05:32.244446 RX Delay -230 -> 252, step: 16
4453 10:05:32.247809 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4454 10:05:32.250466 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4455 10:05:32.257717 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4456 10:05:32.260655 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4457 10:05:32.264066 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4458 10:05:32.267093 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4459 10:05:32.270377 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4460 10:05:32.277450 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4461 10:05:32.280341 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4462 10:05:32.283837 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4463 10:05:32.287328 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4464 10:05:32.293740 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4465 10:05:32.296618 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4466 10:05:32.300498 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4467 10:05:32.303592 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4468 10:05:32.310025 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4469 10:05:32.310444 ==
4470 10:05:32.313414 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 10:05:32.316543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 10:05:32.316963 ==
4473 10:05:32.317293 DQS Delay:
4474 10:05:32.319727 DQS0 = 0, DQS1 = 0
4475 10:05:32.320191 DQM Delay:
4476 10:05:32.323410 DQM0 = 45, DQM1 = 39
4477 10:05:32.323825 DQ Delay:
4478 10:05:32.326511 DQ0 =57, DQ1 =33, DQ2 =33, DQ3 =41
4479 10:05:32.329665 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4480 10:05:32.332957 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4481 10:05:32.336312 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4482 10:05:32.336755
4483 10:05:32.337084
4484 10:05:32.337466 ==
4485 10:05:32.339620 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 10:05:32.343084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 10:05:32.346303 ==
4488 10:05:32.346720
4489 10:05:32.347049
4490 10:05:32.347349 TX Vref Scan disable
4491 10:05:32.349776 == TX Byte 0 ==
4492 10:05:32.353177 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4493 10:05:32.356480 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4494 10:05:32.359386 == TX Byte 1 ==
4495 10:05:32.362657 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4496 10:05:32.366018 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4497 10:05:32.369819 ==
4498 10:05:32.373010 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 10:05:32.376365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 10:05:32.376841 ==
4501 10:05:32.377253
4502 10:05:32.377574
4503 10:05:32.379150 TX Vref Scan disable
4504 10:05:32.382685 == TX Byte 0 ==
4505 10:05:32.386242 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4506 10:05:32.389508 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4507 10:05:32.392233 == TX Byte 1 ==
4508 10:05:32.395696 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4509 10:05:32.398654 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4510 10:05:32.398736
4511 10:05:32.398799 [DATLAT]
4512 10:05:32.402041 Freq=600, CH1 RK0
4513 10:05:32.402122
4514 10:05:32.405284 DATLAT Default: 0x9
4515 10:05:32.405365 0, 0xFFFF, sum = 0
4516 10:05:32.408531 1, 0xFFFF, sum = 0
4517 10:05:32.408614 2, 0xFFFF, sum = 0
4518 10:05:32.411859 3, 0xFFFF, sum = 0
4519 10:05:32.411941 4, 0xFFFF, sum = 0
4520 10:05:32.415234 5, 0xFFFF, sum = 0
4521 10:05:32.415322 6, 0xFFFF, sum = 0
4522 10:05:32.418979 7, 0xFFFF, sum = 0
4523 10:05:32.419066 8, 0x0, sum = 1
4524 10:05:32.421887 9, 0x0, sum = 2
4525 10:05:32.421982 10, 0x0, sum = 3
4526 10:05:32.424882 11, 0x0, sum = 4
4527 10:05:32.424984 best_step = 9
4528 10:05:32.425063
4529 10:05:32.425137 ==
4530 10:05:32.428613 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 10:05:32.431902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 10:05:32.432012 ==
4533 10:05:32.434891 RX Vref Scan: 1
4534 10:05:32.435011
4535 10:05:32.438156 RX Vref 0 -> 0, step: 1
4536 10:05:32.438276
4537 10:05:32.438371 RX Delay -179 -> 252, step: 8
4538 10:05:32.441709
4539 10:05:32.441842 Set Vref, RX VrefLevel [Byte0]: 54
4540 10:05:32.444960 [Byte1]: 52
4541 10:05:32.450057
4542 10:05:32.450228 Final RX Vref Byte 0 = 54 to rank0
4543 10:05:32.452974 Final RX Vref Byte 1 = 52 to rank0
4544 10:05:32.456276 Final RX Vref Byte 0 = 54 to rank1
4545 10:05:32.459698 Final RX Vref Byte 1 = 52 to rank1==
4546 10:05:32.463168 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 10:05:32.469444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 10:05:32.469527 ==
4549 10:05:32.469592 DQS Delay:
4550 10:05:32.472501 DQS0 = 0, DQS1 = 0
4551 10:05:32.472582 DQM Delay:
4552 10:05:32.472647 DQM0 = 42, DQM1 = 34
4553 10:05:32.475741 DQ Delay:
4554 10:05:32.479696 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4555 10:05:32.482593 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4556 10:05:32.485834 DQ8 =16, DQ9 =24, DQ10 =36, DQ11 =28
4557 10:05:32.489426 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4558 10:05:32.489528
4559 10:05:32.489608
4560 10:05:32.495750 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c45, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4561 10:05:32.499591 CH1 RK0: MR19=808, MR18=2C45
4562 10:05:32.506155 CH1_RK0: MR19=0x808, MR18=0x2C45, DQSOSC=396, MR23=63, INC=167, DEC=111
4563 10:05:32.506290
4564 10:05:32.508805 ----->DramcWriteLeveling(PI) begin...
4565 10:05:32.508940 ==
4566 10:05:32.512409 Dram Type= 6, Freq= 0, CH_1, rank 1
4567 10:05:32.515699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 10:05:32.515870 ==
4569 10:05:32.518595 Write leveling (Byte 0): 30 => 30
4570 10:05:32.522178 Write leveling (Byte 1): 30 => 30
4571 10:05:32.525357 DramcWriteLeveling(PI) end<-----
4572 10:05:32.525596
4573 10:05:32.525782 ==
4574 10:05:32.529031 Dram Type= 6, Freq= 0, CH_1, rank 1
4575 10:05:32.535968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 10:05:32.536394 ==
4577 10:05:32.536735 [Gating] SW mode calibration
4578 10:05:32.545229 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4579 10:05:32.548548 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4580 10:05:32.551867 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4581 10:05:32.558456 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4582 10:05:32.561827 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4583 10:05:32.565017 0 9 12 | B1->B0 | 3131 2b2b | 0 0 | (0 1) (1 1)
4584 10:05:32.571397 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4585 10:05:32.574830 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4586 10:05:32.578318 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4587 10:05:32.584871 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4588 10:05:32.588291 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 10:05:32.594929 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 10:05:32.597869 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4591 10:05:32.601095 0 10 12 | B1->B0 | 3131 3c3c | 1 0 | (0 0) (0 0)
4592 10:05:32.608290 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4593 10:05:32.611071 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4594 10:05:32.614236 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4595 10:05:32.620545 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4596 10:05:32.624128 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 10:05:32.627525 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 10:05:32.634191 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4599 10:05:32.637308 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4600 10:05:32.640395 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 10:05:32.646859 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 10:05:32.650260 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 10:05:32.653360 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 10:05:32.660313 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 10:05:32.663840 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 10:05:32.666672 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 10:05:32.673258 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 10:05:32.676867 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 10:05:32.680105 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 10:05:32.687022 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 10:05:32.689809 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 10:05:32.692952 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 10:05:32.699293 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 10:05:32.702747 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 10:05:32.705623 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 10:05:32.709642 Total UI for P1: 0, mck2ui 16
4617 10:05:32.712291 best dqsien dly found for B0: ( 0, 13, 10)
4618 10:05:32.715731 Total UI for P1: 0, mck2ui 16
4619 10:05:32.718863 best dqsien dly found for B1: ( 0, 13, 10)
4620 10:05:32.722187 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4621 10:05:32.725723 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4622 10:05:32.728659
4623 10:05:32.732386 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4624 10:05:32.735552 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4625 10:05:32.739385 [Gating] SW calibration Done
4626 10:05:32.739465 ==
4627 10:05:32.741817 Dram Type= 6, Freq= 0, CH_1, rank 1
4628 10:05:32.745475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 10:05:32.745556 ==
4630 10:05:32.745620 RX Vref Scan: 0
4631 10:05:32.748608
4632 10:05:32.748687 RX Vref 0 -> 0, step: 1
4633 10:05:32.748750
4634 10:05:32.751565 RX Delay -230 -> 252, step: 16
4635 10:05:32.755463 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4636 10:05:32.762066 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4637 10:05:32.765075 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4638 10:05:32.768562 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4639 10:05:32.771671 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4640 10:05:32.778115 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4641 10:05:32.781644 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4642 10:05:32.784747 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4643 10:05:32.788197 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4644 10:05:32.791131 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4645 10:05:32.798024 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4646 10:05:32.801052 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4647 10:05:32.804985 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4648 10:05:32.807645 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4649 10:05:32.814290 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4650 10:05:32.817601 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4651 10:05:32.817681 ==
4652 10:05:32.820894 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 10:05:32.824741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 10:05:32.824821 ==
4655 10:05:32.827778 DQS Delay:
4656 10:05:32.827858 DQS0 = 0, DQS1 = 0
4657 10:05:32.830492 DQM Delay:
4658 10:05:32.830572 DQM0 = 41, DQM1 = 39
4659 10:05:32.830635 DQ Delay:
4660 10:05:32.834323 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4661 10:05:32.837275 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4662 10:05:32.840764 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4663 10:05:32.844154 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4664 10:05:32.844235
4665 10:05:32.844298
4666 10:05:32.847261 ==
4667 10:05:32.850719 Dram Type= 6, Freq= 0, CH_1, rank 1
4668 10:05:32.854127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 10:05:32.854207 ==
4670 10:05:32.854271
4671 10:05:32.854327
4672 10:05:32.857467 TX Vref Scan disable
4673 10:05:32.857547 == TX Byte 0 ==
4674 10:05:32.864059 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4675 10:05:32.867342 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4676 10:05:32.867424 == TX Byte 1 ==
4677 10:05:32.873520 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4678 10:05:32.877098 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4679 10:05:32.877179 ==
4680 10:05:32.880673 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 10:05:32.883543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 10:05:32.883624 ==
4683 10:05:32.883688
4684 10:05:32.883746
4685 10:05:32.886759 TX Vref Scan disable
4686 10:05:32.890614 == TX Byte 0 ==
4687 10:05:32.893350 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4688 10:05:32.896713 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4689 10:05:32.900339 == TX Byte 1 ==
4690 10:05:32.903704 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4691 10:05:32.910061 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4692 10:05:32.910195
4693 10:05:32.910301 [DATLAT]
4694 10:05:32.910399 Freq=600, CH1 RK1
4695 10:05:32.910494
4696 10:05:32.913313 DATLAT Default: 0x9
4697 10:05:32.913446 0, 0xFFFF, sum = 0
4698 10:05:32.916639 1, 0xFFFF, sum = 0
4699 10:05:32.919492 2, 0xFFFF, sum = 0
4700 10:05:32.919666 3, 0xFFFF, sum = 0
4701 10:05:32.922690 4, 0xFFFF, sum = 0
4702 10:05:32.922772 5, 0xFFFF, sum = 0
4703 10:05:32.926454 6, 0xFFFF, sum = 0
4704 10:05:32.926536 7, 0xFFFF, sum = 0
4705 10:05:32.929966 8, 0x0, sum = 1
4706 10:05:32.930387 9, 0x0, sum = 2
4707 10:05:32.930722 10, 0x0, sum = 3
4708 10:05:32.933483 11, 0x0, sum = 4
4709 10:05:32.933909 best_step = 9
4710 10:05:32.934237
4711 10:05:32.936473 ==
4712 10:05:32.936889 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 10:05:32.942817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 10:05:32.943257 ==
4715 10:05:32.943595 RX Vref Scan: 0
4716 10:05:32.943903
4717 10:05:32.946629 RX Vref 0 -> 0, step: 1
4718 10:05:32.947042
4719 10:05:32.949726 RX Delay -179 -> 252, step: 8
4720 10:05:32.956090 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4721 10:05:32.959420 iDelay=205, Bit 1, Center 32 (-131 ~ 196) 328
4722 10:05:32.962889 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4723 10:05:32.966005 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4724 10:05:32.969149 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4725 10:05:32.975823 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4726 10:05:32.979039 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4727 10:05:32.982603 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4728 10:05:32.985939 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4729 10:05:32.992296 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4730 10:05:32.995387 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4731 10:05:32.998753 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4732 10:05:33.002665 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4733 10:05:33.008732 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4734 10:05:33.012119 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4735 10:05:33.015555 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4736 10:05:33.016073 ==
4737 10:05:33.018710 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 10:05:33.024938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 10:05:33.025363 ==
4740 10:05:33.025775 DQS Delay:
4741 10:05:33.026087 DQS0 = 0, DQS1 = 0
4742 10:05:33.028479 DQM Delay:
4743 10:05:33.028955 DQM0 = 37, DQM1 = 35
4744 10:05:33.031682 DQ Delay:
4745 10:05:33.034957 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4746 10:05:33.038115 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4747 10:05:33.041678 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4748 10:05:33.044830 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4749 10:05:33.045272
4750 10:05:33.045677
4751 10:05:33.051527 [DQSOSCAuto] RK1, (LSB)MR18= 0x3257, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4752 10:05:33.054982 CH1 RK1: MR19=808, MR18=3257
4753 10:05:33.062042 CH1_RK1: MR19=0x808, MR18=0x3257, DQSOSC=393, MR23=63, INC=169, DEC=113
4754 10:05:33.064830 [RxdqsGatingPostProcess] freq 600
4755 10:05:33.068127 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4756 10:05:33.070922 Pre-setting of DQS Precalculation
4757 10:05:33.077747 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4758 10:05:33.084804 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4759 10:05:33.091871 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4760 10:05:33.092396
4761 10:05:33.092738
4762 10:05:33.094196 [Calibration Summary] 1200 Mbps
4763 10:05:33.094616 CH 0, Rank 0
4764 10:05:33.097523 SW Impedance : PASS
4765 10:05:33.101263 DUTY Scan : NO K
4766 10:05:33.101753 ZQ Calibration : PASS
4767 10:05:33.104113 Jitter Meter : NO K
4768 10:05:33.107811 CBT Training : PASS
4769 10:05:33.108314 Write leveling : PASS
4770 10:05:33.110601 RX DQS gating : PASS
4771 10:05:33.113752 RX DQ/DQS(RDDQC) : PASS
4772 10:05:33.114219 TX DQ/DQS : PASS
4773 10:05:33.117254 RX DATLAT : PASS
4774 10:05:33.120416 RX DQ/DQS(Engine): PASS
4775 10:05:33.120881 TX OE : NO K
4776 10:05:33.123911 All Pass.
4777 10:05:33.124430
4778 10:05:33.124811 CH 0, Rank 1
4779 10:05:33.127477 SW Impedance : PASS
4780 10:05:33.127901 DUTY Scan : NO K
4781 10:05:33.130118 ZQ Calibration : PASS
4782 10:05:33.133845 Jitter Meter : NO K
4783 10:05:33.134260 CBT Training : PASS
4784 10:05:33.137257 Write leveling : PASS
4785 10:05:33.140496 RX DQS gating : PASS
4786 10:05:33.140914 RX DQ/DQS(RDDQC) : PASS
4787 10:05:33.143391 TX DQ/DQS : PASS
4788 10:05:33.147043 RX DATLAT : PASS
4789 10:05:33.147459 RX DQ/DQS(Engine): PASS
4790 10:05:33.150335 TX OE : NO K
4791 10:05:33.150753 All Pass.
4792 10:05:33.151082
4793 10:05:33.153735 CH 1, Rank 0
4794 10:05:33.154152 SW Impedance : PASS
4795 10:05:33.156629 DUTY Scan : NO K
4796 10:05:33.160187 ZQ Calibration : PASS
4797 10:05:33.160600 Jitter Meter : NO K
4798 10:05:33.163444 CBT Training : PASS
4799 10:05:33.166782 Write leveling : PASS
4800 10:05:33.167198 RX DQS gating : PASS
4801 10:05:33.169916 RX DQ/DQS(RDDQC) : PASS
4802 10:05:33.173068 TX DQ/DQS : PASS
4803 10:05:33.173484 RX DATLAT : PASS
4804 10:05:33.176443 RX DQ/DQS(Engine): PASS
4805 10:05:33.176907 TX OE : NO K
4806 10:05:33.179803 All Pass.
4807 10:05:33.180245
4808 10:05:33.180574 CH 1, Rank 1
4809 10:05:33.183003 SW Impedance : PASS
4810 10:05:33.186374 DUTY Scan : NO K
4811 10:05:33.186790 ZQ Calibration : PASS
4812 10:05:33.189291 Jitter Meter : NO K
4813 10:05:33.189706 CBT Training : PASS
4814 10:05:33.193047 Write leveling : PASS
4815 10:05:33.196611 RX DQS gating : PASS
4816 10:05:33.197028 RX DQ/DQS(RDDQC) : PASS
4817 10:05:33.199318 TX DQ/DQS : PASS
4818 10:05:33.202591 RX DATLAT : PASS
4819 10:05:33.203007 RX DQ/DQS(Engine): PASS
4820 10:05:33.205750 TX OE : NO K
4821 10:05:33.206169 All Pass.
4822 10:05:33.206499
4823 10:05:33.208933 DramC Write-DBI off
4824 10:05:33.212496 PER_BANK_REFRESH: Hybrid Mode
4825 10:05:33.212913 TX_TRACKING: ON
4826 10:05:33.222874 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4827 10:05:33.225904 [FAST_K] Save calibration result to emmc
4828 10:05:33.229355 dramc_set_vcore_voltage set vcore to 662500
4829 10:05:33.231808 Read voltage for 933, 3
4830 10:05:33.232268 Vio18 = 0
4831 10:05:33.235280 Vcore = 662500
4832 10:05:33.235695 Vdram = 0
4833 10:05:33.236024 Vddq = 0
4834 10:05:33.236391 Vmddr = 0
4835 10:05:33.241828 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4836 10:05:33.248758 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4837 10:05:33.249192 MEM_TYPE=3, freq_sel=17
4838 10:05:33.251819 sv_algorithm_assistance_LP4_1600
4839 10:05:33.255261 ============ PULL DRAM RESETB DOWN ============
4840 10:05:33.262112 ========== PULL DRAM RESETB DOWN end =========
4841 10:05:33.265285 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4842 10:05:33.267971 ===================================
4843 10:05:33.271568 LPDDR4 DRAM CONFIGURATION
4844 10:05:33.274656 ===================================
4845 10:05:33.274738 EX_ROW_EN[0] = 0x0
4846 10:05:33.278167 EX_ROW_EN[1] = 0x0
4847 10:05:33.278248 LP4Y_EN = 0x0
4848 10:05:33.281317 WORK_FSP = 0x0
4849 10:05:33.284785 WL = 0x3
4850 10:05:33.284866 RL = 0x3
4851 10:05:33.288298 BL = 0x2
4852 10:05:33.288379 RPST = 0x0
4853 10:05:33.291672 RD_PRE = 0x0
4854 10:05:33.291759 WR_PRE = 0x1
4855 10:05:33.294253 WR_PST = 0x0
4856 10:05:33.294360 DBI_WR = 0x0
4857 10:05:33.297755 DBI_RD = 0x0
4858 10:05:33.297849 OTF = 0x1
4859 10:05:33.301397 ===================================
4860 10:05:33.304962 ===================================
4861 10:05:33.307544 ANA top config
4862 10:05:33.310751 ===================================
4863 10:05:33.310834 DLL_ASYNC_EN = 0
4864 10:05:33.314289 ALL_SLAVE_EN = 1
4865 10:05:33.317268 NEW_RANK_MODE = 1
4866 10:05:33.320676 DLL_IDLE_MODE = 1
4867 10:05:33.323858 LP45_APHY_COMB_EN = 1
4868 10:05:33.323966 TX_ODT_DIS = 1
4869 10:05:33.327406 NEW_8X_MODE = 1
4870 10:05:33.330234 ===================================
4871 10:05:33.333976 ===================================
4872 10:05:33.337252 data_rate = 1866
4873 10:05:33.340147 CKR = 1
4874 10:05:33.343591 DQ_P2S_RATIO = 8
4875 10:05:33.346728 ===================================
4876 10:05:33.350224 CA_P2S_RATIO = 8
4877 10:05:33.350306 DQ_CA_OPEN = 0
4878 10:05:33.353366 DQ_SEMI_OPEN = 0
4879 10:05:33.356711 CA_SEMI_OPEN = 0
4880 10:05:33.359782 CA_FULL_RATE = 0
4881 10:05:33.363630 DQ_CKDIV4_EN = 1
4882 10:05:33.366532 CA_CKDIV4_EN = 1
4883 10:05:33.366614 CA_PREDIV_EN = 0
4884 10:05:33.370101 PH8_DLY = 0
4885 10:05:33.373355 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4886 10:05:33.377081 DQ_AAMCK_DIV = 4
4887 10:05:33.379927 CA_AAMCK_DIV = 4
4888 10:05:33.383152 CA_ADMCK_DIV = 4
4889 10:05:33.383243 DQ_TRACK_CA_EN = 0
4890 10:05:33.386447 CA_PICK = 933
4891 10:05:33.389735 CA_MCKIO = 933
4892 10:05:33.392876 MCKIO_SEMI = 0
4893 10:05:33.396553 PLL_FREQ = 3732
4894 10:05:33.399545 DQ_UI_PI_RATIO = 32
4895 10:05:33.402674 CA_UI_PI_RATIO = 0
4896 10:05:33.405997 ===================================
4897 10:05:33.410019 ===================================
4898 10:05:33.410096 memory_type:LPDDR4
4899 10:05:33.412590 GP_NUM : 10
4900 10:05:33.415930 SRAM_EN : 1
4901 10:05:33.416042 MD32_EN : 0
4902 10:05:33.419283 ===================================
4903 10:05:33.422457 [ANA_INIT] >>>>>>>>>>>>>>
4904 10:05:33.425918 <<<<<< [CONFIGURE PHASE]: ANA_TX
4905 10:05:33.429224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4906 10:05:33.432571 ===================================
4907 10:05:33.435877 data_rate = 1866,PCW = 0X8f00
4908 10:05:33.439207 ===================================
4909 10:05:33.442121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4910 10:05:33.445558 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4911 10:05:33.452532 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4912 10:05:33.458595 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4913 10:05:33.461943 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4914 10:05:33.465569 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4915 10:05:33.465659 [ANA_INIT] flow start
4916 10:05:33.468712 [ANA_INIT] PLL >>>>>>>>
4917 10:05:33.471879 [ANA_INIT] PLL <<<<<<<<
4918 10:05:33.471984 [ANA_INIT] MIDPI >>>>>>>>
4919 10:05:33.475396 [ANA_INIT] MIDPI <<<<<<<<
4920 10:05:33.478377 [ANA_INIT] DLL >>>>>>>>
4921 10:05:33.478450 [ANA_INIT] flow end
4922 10:05:33.485369 ============ LP4 DIFF to SE enter ============
4923 10:05:33.488666 ============ LP4 DIFF to SE exit ============
4924 10:05:33.491890 [ANA_INIT] <<<<<<<<<<<<<
4925 10:05:33.494629 [Flow] Enable top DCM control >>>>>
4926 10:05:33.498444 [Flow] Enable top DCM control <<<<<
4927 10:05:33.498516 Enable DLL master slave shuffle
4928 10:05:33.505057 ==============================================================
4929 10:05:33.507969 Gating Mode config
4930 10:05:33.511719 ==============================================================
4931 10:05:33.514417 Config description:
4932 10:05:33.524377 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4933 10:05:33.530969 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4934 10:05:33.534362 SELPH_MODE 0: By rank 1: By Phase
4935 10:05:33.541076 ==============================================================
4936 10:05:33.544396 GAT_TRACK_EN = 1
4937 10:05:33.547349 RX_GATING_MODE = 2
4938 10:05:33.550823 RX_GATING_TRACK_MODE = 2
4939 10:05:33.553935 SELPH_MODE = 1
4940 10:05:33.557370 PICG_EARLY_EN = 1
4941 10:05:33.560360 VALID_LAT_VALUE = 1
4942 10:05:33.563862 ==============================================================
4943 10:05:33.567344 Enter into Gating configuration >>>>
4944 10:05:33.570733 Exit from Gating configuration <<<<
4945 10:05:33.573691 Enter into DVFS_PRE_config >>>>>
4946 10:05:33.587044 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4947 10:05:33.587130 Exit from DVFS_PRE_config <<<<<
4948 10:05:33.590259 Enter into PICG configuration >>>>
4949 10:05:33.593654 Exit from PICG configuration <<<<
4950 10:05:33.596963 [RX_INPUT] configuration >>>>>
4951 10:05:33.600430 [RX_INPUT] configuration <<<<<
4952 10:05:33.606879 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4953 10:05:33.610376 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4954 10:05:33.616671 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4955 10:05:33.623556 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4956 10:05:33.629840 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4957 10:05:33.636324 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4958 10:05:33.639882 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4959 10:05:33.642725 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4960 10:05:33.649295 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4961 10:05:33.653109 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4962 10:05:33.656265 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4963 10:05:33.659584 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4964 10:05:33.662673 ===================================
4965 10:05:33.666197 LPDDR4 DRAM CONFIGURATION
4966 10:05:33.669385 ===================================
4967 10:05:33.672311 EX_ROW_EN[0] = 0x0
4968 10:05:33.672429 EX_ROW_EN[1] = 0x0
4969 10:05:33.675977 LP4Y_EN = 0x0
4970 10:05:33.676107 WORK_FSP = 0x0
4971 10:05:33.679375 WL = 0x3
4972 10:05:33.679474 RL = 0x3
4973 10:05:33.682272 BL = 0x2
4974 10:05:33.685516 RPST = 0x0
4975 10:05:33.685619 RD_PRE = 0x0
4976 10:05:33.689155 WR_PRE = 0x1
4977 10:05:33.689254 WR_PST = 0x0
4978 10:05:33.692440 DBI_WR = 0x0
4979 10:05:33.692511 DBI_RD = 0x0
4980 10:05:33.695361 OTF = 0x1
4981 10:05:33.698905 ===================================
4982 10:05:33.702014 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4983 10:05:33.705504 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4984 10:05:33.711941 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4985 10:05:33.715343 ===================================
4986 10:05:33.715426 LPDDR4 DRAM CONFIGURATION
4987 10:05:33.718271 ===================================
4988 10:05:33.721598 EX_ROW_EN[0] = 0x10
4989 10:05:33.721678 EX_ROW_EN[1] = 0x0
4990 10:05:33.725246 LP4Y_EN = 0x0
4991 10:05:33.728529 WORK_FSP = 0x0
4992 10:05:33.728616 WL = 0x3
4993 10:05:33.731636 RL = 0x3
4994 10:05:33.731709 BL = 0x2
4995 10:05:33.734805 RPST = 0x0
4996 10:05:33.734885 RD_PRE = 0x0
4997 10:05:33.737964 WR_PRE = 0x1
4998 10:05:33.738038 WR_PST = 0x0
4999 10:05:33.741634 DBI_WR = 0x0
5000 10:05:33.741713 DBI_RD = 0x0
5001 10:05:33.744890 OTF = 0x1
5002 10:05:33.747812 ===================================
5003 10:05:33.754443 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5004 10:05:33.757689 nWR fixed to 30
5005 10:05:33.757764 [ModeRegInit_LP4] CH0 RK0
5006 10:05:33.760905 [ModeRegInit_LP4] CH0 RK1
5007 10:05:33.764309 [ModeRegInit_LP4] CH1 RK0
5008 10:05:33.767620 [ModeRegInit_LP4] CH1 RK1
5009 10:05:33.767696 match AC timing 9
5010 10:05:33.774059 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5011 10:05:33.777690 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5012 10:05:33.780546 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5013 10:05:33.787550 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5014 10:05:33.790500 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5015 10:05:33.790584 ==
5016 10:05:33.794079 Dram Type= 6, Freq= 0, CH_0, rank 0
5017 10:05:33.797114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5018 10:05:33.797189 ==
5019 10:05:33.804022 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5020 10:05:33.810552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5021 10:05:33.813956 [CA 0] Center 37 (7~68) winsize 62
5022 10:05:33.817262 [CA 1] Center 37 (7~68) winsize 62
5023 10:05:33.820544 [CA 2] Center 34 (4~64) winsize 61
5024 10:05:33.823748 [CA 3] Center 34 (4~65) winsize 62
5025 10:05:33.827257 [CA 4] Center 33 (3~63) winsize 61
5026 10:05:33.830098 [CA 5] Center 33 (3~63) winsize 61
5027 10:05:33.830180
5028 10:05:33.833811 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5029 10:05:33.833901
5030 10:05:33.837198 [CATrainingPosCal] consider 1 rank data
5031 10:05:33.840165 u2DelayCellTimex100 = 270/100 ps
5032 10:05:33.843589 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5033 10:05:33.846776 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5034 10:05:33.850054 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5035 10:05:33.853360 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5036 10:05:33.856884 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5037 10:05:33.860017 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5038 10:05:33.863884
5039 10:05:33.867055 CA PerBit enable=1, Macro0, CA PI delay=33
5040 10:05:33.867155
5041 10:05:33.869806 [CBTSetCACLKResult] CA Dly = 33
5042 10:05:33.869906 CS Dly: 5 (0~36)
5043 10:05:33.869995 ==
5044 10:05:33.873175 Dram Type= 6, Freq= 0, CH_0, rank 1
5045 10:05:33.876197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5046 10:05:33.879724 ==
5047 10:05:33.882967 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5048 10:05:33.889440 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5049 10:05:33.892801 [CA 0] Center 37 (7~68) winsize 62
5050 10:05:33.896249 [CA 1] Center 37 (7~68) winsize 62
5051 10:05:33.899610 [CA 2] Center 35 (5~65) winsize 61
5052 10:05:33.902974 [CA 3] Center 34 (4~65) winsize 62
5053 10:05:33.906141 [CA 4] Center 33 (3~64) winsize 62
5054 10:05:33.909075 [CA 5] Center 32 (2~63) winsize 62
5055 10:05:33.909169
5056 10:05:33.912559 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5057 10:05:33.912659
5058 10:05:33.915856 [CATrainingPosCal] consider 2 rank data
5059 10:05:33.919044 u2DelayCellTimex100 = 270/100 ps
5060 10:05:33.922479 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5061 10:05:33.925982 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5062 10:05:33.928973 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5063 10:05:33.935597 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5064 10:05:33.938903 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5065 10:05:33.942404 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5066 10:05:33.942485
5067 10:05:33.945777 CA PerBit enable=1, Macro0, CA PI delay=33
5068 10:05:33.945858
5069 10:05:33.948676 [CBTSetCACLKResult] CA Dly = 33
5070 10:05:33.948756 CS Dly: 6 (0~39)
5071 10:05:33.948819
5072 10:05:33.951913 ----->DramcWriteLeveling(PI) begin...
5073 10:05:33.955216 ==
5074 10:05:33.955296 Dram Type= 6, Freq= 0, CH_0, rank 0
5075 10:05:33.961807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5076 10:05:33.961922 ==
5077 10:05:33.965796 Write leveling (Byte 0): 32 => 32
5078 10:05:33.968557 Write leveling (Byte 1): 26 => 26
5079 10:05:33.972330 DramcWriteLeveling(PI) end<-----
5080 10:05:33.972410
5081 10:05:33.972474 ==
5082 10:05:33.975384 Dram Type= 6, Freq= 0, CH_0, rank 0
5083 10:05:33.979182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5084 10:05:33.979263 ==
5085 10:05:33.981912 [Gating] SW mode calibration
5086 10:05:33.988429 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5087 10:05:33.995209 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5088 10:05:33.998809 0 14 0 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
5089 10:05:34.001518 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5090 10:05:34.008038 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5091 10:05:34.011515 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5092 10:05:34.015337 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5093 10:05:34.021263 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 10:05:34.025005 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5095 10:05:34.028336 0 14 28 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 0)
5096 10:05:34.034994 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5097 10:05:34.038394 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5098 10:05:34.041236 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5099 10:05:34.047942 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5100 10:05:34.051528 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 10:05:34.054736 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 10:05:34.060952 0 15 24 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
5103 10:05:34.064251 0 15 28 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
5104 10:05:34.067813 1 0 0 | B1->B0 | 3535 4545 | 0 0 | (0 0) (0 0)
5105 10:05:34.074481 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5106 10:05:34.077761 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 10:05:34.080485 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5108 10:05:34.087407 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 10:05:34.090299 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 10:05:34.093595 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5111 10:05:34.100315 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5112 10:05:34.103257 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5113 10:05:34.106537 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 10:05:34.113761 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 10:05:34.117016 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 10:05:34.120563 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 10:05:34.126569 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 10:05:34.129831 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 10:05:34.133088 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 10:05:34.139891 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 10:05:34.142831 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 10:05:34.146428 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 10:05:34.152611 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 10:05:34.156531 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 10:05:34.159966 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 10:05:34.166126 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 10:05:34.169281 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5128 10:05:34.172912 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5129 10:05:34.176039 Total UI for P1: 0, mck2ui 16
5130 10:05:34.179239 best dqsien dly found for B0: ( 1, 2, 28)
5131 10:05:34.186188 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5132 10:05:34.189450 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 10:05:34.192622 Total UI for P1: 0, mck2ui 16
5134 10:05:34.195535 best dqsien dly found for B1: ( 1, 3, 0)
5135 10:05:34.198902 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5136 10:05:34.202096 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5137 10:05:34.202200
5138 10:05:34.205894 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5139 10:05:34.208765 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5140 10:05:34.211951 [Gating] SW calibration Done
5141 10:05:34.212051 ==
5142 10:05:34.215386 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 10:05:34.218657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 10:05:34.222352 ==
5145 10:05:34.222426 RX Vref Scan: 0
5146 10:05:34.222490
5147 10:05:34.225196 RX Vref 0 -> 0, step: 1
5148 10:05:34.225268
5149 10:05:34.229022 RX Delay -80 -> 252, step: 8
5150 10:05:34.231840 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5151 10:05:34.235380 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5152 10:05:34.238691 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5153 10:05:34.242257 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5154 10:05:34.244972 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5155 10:05:34.251859 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5156 10:05:34.255120 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5157 10:05:34.258208 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5158 10:05:34.262058 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5159 10:05:34.265186 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5160 10:05:34.272252 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5161 10:05:34.274668 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5162 10:05:34.278242 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5163 10:05:34.281699 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5164 10:05:34.285044 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5165 10:05:34.291791 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5166 10:05:34.291894 ==
5167 10:05:34.294464 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 10:05:34.297845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 10:05:34.297918 ==
5170 10:05:34.297982 DQS Delay:
5171 10:05:34.301215 DQS0 = 0, DQS1 = 0
5172 10:05:34.301284 DQM Delay:
5173 10:05:34.304787 DQM0 = 100, DQM1 = 88
5174 10:05:34.304863 DQ Delay:
5175 10:05:34.307959 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5176 10:05:34.311323 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =107
5177 10:05:34.314649 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5178 10:05:34.317469 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5179 10:05:34.317571
5180 10:05:34.317663
5181 10:05:34.317749 ==
5182 10:05:34.321249 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 10:05:34.324153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 10:05:34.327831 ==
5185 10:05:34.327926
5186 10:05:34.328019
5187 10:05:34.328095 TX Vref Scan disable
5188 10:05:34.331212 == TX Byte 0 ==
5189 10:05:34.334088 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5190 10:05:34.337479 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5191 10:05:34.340778 == TX Byte 1 ==
5192 10:05:34.344260 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5193 10:05:34.350427 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5194 10:05:34.350541 ==
5195 10:05:34.353893 Dram Type= 6, Freq= 0, CH_0, rank 0
5196 10:05:34.356919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5197 10:05:34.356993 ==
5198 10:05:34.357056
5199 10:05:34.357116
5200 10:05:34.360413 TX Vref Scan disable
5201 10:05:34.360487 == TX Byte 0 ==
5202 10:05:34.367151 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5203 10:05:34.369947 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5204 10:05:34.373565 == TX Byte 1 ==
5205 10:05:34.376639 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5206 10:05:34.379895 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5207 10:05:34.380003
5208 10:05:34.380088 [DATLAT]
5209 10:05:34.383077 Freq=933, CH0 RK0
5210 10:05:34.383157
5211 10:05:34.386712 DATLAT Default: 0xd
5212 10:05:34.386792 0, 0xFFFF, sum = 0
5213 10:05:34.389956 1, 0xFFFF, sum = 0
5214 10:05:34.390038 2, 0xFFFF, sum = 0
5215 10:05:34.393302 3, 0xFFFF, sum = 0
5216 10:05:34.393383 4, 0xFFFF, sum = 0
5217 10:05:34.396565 5, 0xFFFF, sum = 0
5218 10:05:34.396673 6, 0xFFFF, sum = 0
5219 10:05:34.399742 7, 0xFFFF, sum = 0
5220 10:05:34.399820 8, 0xFFFF, sum = 0
5221 10:05:34.403119 9, 0xFFFF, sum = 0
5222 10:05:34.403217 10, 0x0, sum = 1
5223 10:05:34.406125 11, 0x0, sum = 2
5224 10:05:34.406207 12, 0x0, sum = 3
5225 10:05:34.409654 13, 0x0, sum = 4
5226 10:05:34.409736 best_step = 11
5227 10:05:34.409798
5228 10:05:34.409856 ==
5229 10:05:34.412911 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 10:05:34.416139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 10:05:34.419620 ==
5232 10:05:34.419695 RX Vref Scan: 1
5233 10:05:34.419785
5234 10:05:34.423166 RX Vref 0 -> 0, step: 1
5235 10:05:34.423270
5236 10:05:34.426313 RX Delay -61 -> 252, step: 4
5237 10:05:34.426471
5238 10:05:34.429616 Set Vref, RX VrefLevel [Byte0]: 53
5239 10:05:34.432767 [Byte1]: 44
5240 10:05:34.432868
5241 10:05:34.436367 Final RX Vref Byte 0 = 53 to rank0
5242 10:05:34.438972 Final RX Vref Byte 1 = 44 to rank0
5243 10:05:34.442819 Final RX Vref Byte 0 = 53 to rank1
5244 10:05:34.445682 Final RX Vref Byte 1 = 44 to rank1==
5245 10:05:34.449453 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 10:05:34.452878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 10:05:34.452978 ==
5248 10:05:34.455796 DQS Delay:
5249 10:05:34.455897 DQS0 = 0, DQS1 = 0
5250 10:05:34.455987 DQM Delay:
5251 10:05:34.458773 DQM0 = 98, DQM1 = 86
5252 10:05:34.458875 DQ Delay:
5253 10:05:34.462317 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5254 10:05:34.465542 DQ4 =100, DQ5 =90, DQ6 =106, DQ7 =104
5255 10:05:34.469136 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =82
5256 10:05:34.472325 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =94
5257 10:05:34.472428
5258 10:05:34.472529
5259 10:05:34.482337 [DQSOSCAuto] RK0, (LSB)MR18= 0x1812, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5260 10:05:34.485421 CH0 RK0: MR19=505, MR18=1812
5261 10:05:34.491932 CH0_RK0: MR19=0x505, MR18=0x1812, DQSOSC=414, MR23=63, INC=63, DEC=42
5262 10:05:34.492042
5263 10:05:34.495357 ----->DramcWriteLeveling(PI) begin...
5264 10:05:34.495461 ==
5265 10:05:34.498565 Dram Type= 6, Freq= 0, CH_0, rank 1
5266 10:05:34.502049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 10:05:34.502151 ==
5268 10:05:34.504941 Write leveling (Byte 0): 31 => 31
5269 10:05:34.508747 Write leveling (Byte 1): 27 => 27
5270 10:05:34.511583 DramcWriteLeveling(PI) end<-----
5271 10:05:34.511685
5272 10:05:34.511775 ==
5273 10:05:34.514978 Dram Type= 6, Freq= 0, CH_0, rank 1
5274 10:05:34.518118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 10:05:34.518219 ==
5276 10:05:34.521578 [Gating] SW mode calibration
5277 10:05:34.528220 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5278 10:05:34.534864 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5279 10:05:34.538115 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5280 10:05:34.541208 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5281 10:05:34.548110 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5282 10:05:34.551448 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5283 10:05:34.554360 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 10:05:34.561415 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 10:05:34.564320 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5286 10:05:34.567598 0 14 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
5287 10:05:34.573944 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5288 10:05:34.577229 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5289 10:05:34.581306 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5290 10:05:34.587675 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5291 10:05:34.590949 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 10:05:34.593904 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 10:05:34.600360 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5294 10:05:34.603858 0 15 28 | B1->B0 | 2b2b 3f3f | 0 0 | (0 0) (0 0)
5295 10:05:34.610480 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5296 10:05:34.613693 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5297 10:05:34.616774 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5298 10:05:34.623891 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 10:05:34.626756 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 10:05:34.630210 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 10:05:34.633439 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5302 10:05:34.640361 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5303 10:05:34.643244 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5304 10:05:34.649956 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 10:05:34.653400 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 10:05:34.656191 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 10:05:34.663447 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 10:05:34.666229 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 10:05:34.669563 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 10:05:34.675981 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 10:05:34.679358 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 10:05:34.682998 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 10:05:34.689505 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 10:05:34.692371 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 10:05:34.696234 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 10:05:34.702591 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 10:05:34.705553 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 10:05:34.708772 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5319 10:05:34.712173 Total UI for P1: 0, mck2ui 16
5320 10:05:34.715313 best dqsien dly found for B0: ( 1, 2, 26)
5321 10:05:34.722386 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 10:05:34.722466 Total UI for P1: 0, mck2ui 16
5323 10:05:34.729065 best dqsien dly found for B1: ( 1, 2, 28)
5324 10:05:34.732507 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5325 10:05:34.735736 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5326 10:05:34.735831
5327 10:05:34.738419 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5328 10:05:34.741795 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5329 10:05:34.745023 [Gating] SW calibration Done
5330 10:05:34.745091 ==
5331 10:05:34.748447 Dram Type= 6, Freq= 0, CH_0, rank 1
5332 10:05:34.751938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 10:05:34.752055 ==
5334 10:05:34.755379 RX Vref Scan: 0
5335 10:05:34.755444
5336 10:05:34.755500 RX Vref 0 -> 0, step: 1
5337 10:05:34.755554
5338 10:05:34.758538 RX Delay -80 -> 252, step: 8
5339 10:05:34.762050 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5340 10:05:34.768008 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5341 10:05:34.771496 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5342 10:05:34.774811 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5343 10:05:34.778221 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5344 10:05:34.781228 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5345 10:05:34.784602 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5346 10:05:34.791410 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5347 10:05:34.794767 iDelay=200, Bit 8, Center 79 (-8 ~ 167) 176
5348 10:05:34.798004 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5349 10:05:34.801295 iDelay=200, Bit 10, Center 87 (0 ~ 175) 176
5350 10:05:34.804411 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5351 10:05:34.810971 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5352 10:05:34.814100 iDelay=200, Bit 13, Center 91 (0 ~ 183) 184
5353 10:05:34.817484 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5354 10:05:34.820583 iDelay=200, Bit 15, Center 95 (8 ~ 183) 176
5355 10:05:34.820663 ==
5356 10:05:34.823831 Dram Type= 6, Freq= 0, CH_0, rank 1
5357 10:05:34.827580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 10:05:34.830614 ==
5359 10:05:34.830693 DQS Delay:
5360 10:05:34.830755 DQS0 = 0, DQS1 = 0
5361 10:05:34.833767 DQM Delay:
5362 10:05:34.833848 DQM0 = 97, DQM1 = 87
5363 10:05:34.837446 DQ Delay:
5364 10:05:34.840671 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5365 10:05:34.844189 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5366 10:05:34.847397 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5367 10:05:34.850330 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5368 10:05:34.850411
5369 10:05:34.850475
5370 10:05:34.850534 ==
5371 10:05:34.854132 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 10:05:34.857034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 10:05:34.857115 ==
5374 10:05:34.857180
5375 10:05:34.857239
5376 10:05:34.860394 TX Vref Scan disable
5377 10:05:34.860474 == TX Byte 0 ==
5378 10:05:34.866900 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5379 10:05:34.870066 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5380 10:05:34.873407 == TX Byte 1 ==
5381 10:05:34.876809 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5382 10:05:34.880481 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5383 10:05:34.880562 ==
5384 10:05:34.883166 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 10:05:34.886731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 10:05:34.890036 ==
5387 10:05:34.890117
5388 10:05:34.890180
5389 10:05:34.890240 TX Vref Scan disable
5390 10:05:34.893551 == TX Byte 0 ==
5391 10:05:34.897021 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5392 10:05:34.904126 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5393 10:05:34.904210 == TX Byte 1 ==
5394 10:05:34.906883 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5395 10:05:34.913378 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5396 10:05:34.913460
5397 10:05:34.913541 [DATLAT]
5398 10:05:34.913603 Freq=933, CH0 RK1
5399 10:05:34.913661
5400 10:05:34.916442 DATLAT Default: 0xb
5401 10:05:34.916523 0, 0xFFFF, sum = 0
5402 10:05:34.919937 1, 0xFFFF, sum = 0
5403 10:05:34.923269 2, 0xFFFF, sum = 0
5404 10:05:34.923384 3, 0xFFFF, sum = 0
5405 10:05:34.926221 4, 0xFFFF, sum = 0
5406 10:05:34.926303 5, 0xFFFF, sum = 0
5407 10:05:34.929415 6, 0xFFFF, sum = 0
5408 10:05:34.929519 7, 0xFFFF, sum = 0
5409 10:05:34.932734 8, 0xFFFF, sum = 0
5410 10:05:34.932848 9, 0xFFFF, sum = 0
5411 10:05:34.936340 10, 0x0, sum = 1
5412 10:05:34.936423 11, 0x0, sum = 2
5413 10:05:34.939635 12, 0x0, sum = 3
5414 10:05:34.939717 13, 0x0, sum = 4
5415 10:05:34.942924 best_step = 11
5416 10:05:34.943012
5417 10:05:34.943081 ==
5418 10:05:34.946211 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 10:05:34.949246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 10:05:34.949327 ==
5421 10:05:34.949391 RX Vref Scan: 0
5422 10:05:34.949469
5423 10:05:34.952556 RX Vref 0 -> 0, step: 1
5424 10:05:34.952637
5425 10:05:34.956421 RX Delay -61 -> 252, step: 4
5426 10:05:34.962717 iDelay=199, Bit 0, Center 96 (11 ~ 182) 172
5427 10:05:34.965740 iDelay=199, Bit 1, Center 98 (7 ~ 190) 184
5428 10:05:34.968979 iDelay=199, Bit 2, Center 92 (3 ~ 182) 180
5429 10:05:34.972483 iDelay=199, Bit 3, Center 96 (7 ~ 186) 180
5430 10:05:34.976202 iDelay=199, Bit 4, Center 100 (11 ~ 190) 180
5431 10:05:34.979256 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5432 10:05:34.985853 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5433 10:05:34.989190 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5434 10:05:34.992212 iDelay=199, Bit 8, Center 74 (-13 ~ 162) 176
5435 10:05:34.995523 iDelay=199, Bit 9, Center 74 (-13 ~ 162) 176
5436 10:05:34.998853 iDelay=199, Bit 10, Center 90 (7 ~ 174) 168
5437 10:05:35.005456 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5438 10:05:35.009055 iDelay=199, Bit 12, Center 92 (7 ~ 178) 172
5439 10:05:35.012225 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5440 10:05:35.015532 iDelay=199, Bit 14, Center 98 (15 ~ 182) 168
5441 10:05:35.018728 iDelay=199, Bit 15, Center 94 (11 ~ 178) 168
5442 10:05:35.018799 ==
5443 10:05:35.022282 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 10:05:35.029130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 10:05:35.029207 ==
5446 10:05:35.029270 DQS Delay:
5447 10:05:35.032445 DQS0 = 0, DQS1 = 0
5448 10:05:35.032539 DQM Delay:
5449 10:05:35.032626 DQM0 = 97, DQM1 = 87
5450 10:05:35.035095 DQ Delay:
5451 10:05:35.038694 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =96
5452 10:05:35.041665 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =104
5453 10:05:35.045240 DQ8 =74, DQ9 =74, DQ10 =90, DQ11 =80
5454 10:05:35.048348 DQ12 =92, DQ13 =94, DQ14 =98, DQ15 =94
5455 10:05:35.048433
5456 10:05:35.048498
5457 10:05:35.055198 [DQSOSCAuto] RK1, (LSB)MR18= 0x100d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5458 10:05:35.058142 CH0 RK1: MR19=505, MR18=100D
5459 10:05:35.064694 CH0_RK1: MR19=0x505, MR18=0x100D, DQSOSC=416, MR23=63, INC=62, DEC=41
5460 10:05:35.068237 [RxdqsGatingPostProcess] freq 933
5461 10:05:35.074595 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5462 10:05:35.078450 best DQS0 dly(2T, 0.5T) = (0, 10)
5463 10:05:35.078533 best DQS1 dly(2T, 0.5T) = (0, 11)
5464 10:05:35.081107 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5465 10:05:35.084424 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5466 10:05:35.087890 best DQS0 dly(2T, 0.5T) = (0, 10)
5467 10:05:35.091326 best DQS1 dly(2T, 0.5T) = (0, 10)
5468 10:05:35.094573 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5469 10:05:35.098108 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5470 10:05:35.101374 Pre-setting of DQS Precalculation
5471 10:05:35.107853 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5472 10:05:35.107962 ==
5473 10:05:35.111343 Dram Type= 6, Freq= 0, CH_1, rank 0
5474 10:05:35.114528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 10:05:35.114601 ==
5476 10:05:35.121331 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5477 10:05:35.127362 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5478 10:05:35.130918 [CA 0] Center 36 (6~67) winsize 62
5479 10:05:35.134291 [CA 1] Center 36 (6~67) winsize 62
5480 10:05:35.137910 [CA 2] Center 34 (5~64) winsize 60
5481 10:05:35.140511 [CA 3] Center 34 (4~64) winsize 61
5482 10:05:35.143998 [CA 4] Center 34 (4~64) winsize 61
5483 10:05:35.147303 [CA 5] Center 33 (3~64) winsize 62
5484 10:05:35.147386
5485 10:05:35.150218 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5486 10:05:35.150300
5487 10:05:35.153633 [CATrainingPosCal] consider 1 rank data
5488 10:05:35.156874 u2DelayCellTimex100 = 270/100 ps
5489 10:05:35.160002 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5490 10:05:35.163504 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5491 10:05:35.167005 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5492 10:05:35.170382 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5493 10:05:35.173630 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5494 10:05:35.176583 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5495 10:05:35.176665
5496 10:05:35.183404 CA PerBit enable=1, Macro0, CA PI delay=33
5497 10:05:35.183486
5498 10:05:35.183551 [CBTSetCACLKResult] CA Dly = 33
5499 10:05:35.186742 CS Dly: 5 (0~36)
5500 10:05:35.186853 ==
5501 10:05:35.190063 Dram Type= 6, Freq= 0, CH_1, rank 1
5502 10:05:35.193464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 10:05:35.193571 ==
5504 10:05:35.199855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5505 10:05:35.206171 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5506 10:05:35.209774 [CA 0] Center 36 (6~67) winsize 62
5507 10:05:35.212840 [CA 1] Center 37 (7~67) winsize 61
5508 10:05:35.216552 [CA 2] Center 34 (4~65) winsize 62
5509 10:05:35.219552 [CA 3] Center 33 (3~64) winsize 62
5510 10:05:35.222818 [CA 4] Center 34 (3~65) winsize 63
5511 10:05:35.226253 [CA 5] Center 33 (3~64) winsize 62
5512 10:05:35.226322
5513 10:05:35.229231 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5514 10:05:35.229303
5515 10:05:35.232577 [CATrainingPosCal] consider 2 rank data
5516 10:05:35.235953 u2DelayCellTimex100 = 270/100 ps
5517 10:05:35.240522 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5518 10:05:35.242515 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5519 10:05:35.245943 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5520 10:05:35.249091 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5521 10:05:35.255770 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5522 10:05:35.258855 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5523 10:05:35.258935
5524 10:05:35.262534 CA PerBit enable=1, Macro0, CA PI delay=33
5525 10:05:35.262614
5526 10:05:35.265771 [CBTSetCACLKResult] CA Dly = 33
5527 10:05:35.265852 CS Dly: 6 (0~38)
5528 10:05:35.265917
5529 10:05:35.268921 ----->DramcWriteLeveling(PI) begin...
5530 10:05:35.269004 ==
5531 10:05:35.272199 Dram Type= 6, Freq= 0, CH_1, rank 0
5532 10:05:35.278571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 10:05:35.278654 ==
5534 10:05:35.281952 Write leveling (Byte 0): 28 => 28
5535 10:05:35.285422 Write leveling (Byte 1): 29 => 29
5536 10:05:35.288429 DramcWriteLeveling(PI) end<-----
5537 10:05:35.288510
5538 10:05:35.288574 ==
5539 10:05:35.292012 Dram Type= 6, Freq= 0, CH_1, rank 0
5540 10:05:35.295299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 10:05:35.295381 ==
5542 10:05:35.298216 [Gating] SW mode calibration
5543 10:05:35.305346 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5544 10:05:35.308655 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5545 10:05:35.315193 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5546 10:05:35.318225 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5547 10:05:35.324903 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5548 10:05:35.327885 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 10:05:35.331455 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 10:05:35.338206 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 10:05:35.341250 0 14 24 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
5552 10:05:35.344824 0 14 28 | B1->B0 | 2d2d 2727 | 0 0 | (0 1) (0 1)
5553 10:05:35.351458 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 10:05:35.354163 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5555 10:05:35.357800 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 10:05:35.364204 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 10:05:35.367746 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 10:05:35.370916 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 10:05:35.377193 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5560 10:05:35.380682 0 15 28 | B1->B0 | 3333 3b3b | 0 0 | (0 0) (0 0)
5561 10:05:35.383709 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 10:05:35.390516 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 10:05:35.394034 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 10:05:35.397357 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 10:05:35.403874 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 10:05:35.406834 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 10:05:35.410497 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 10:05:35.417163 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5569 10:05:35.420363 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 10:05:35.423443 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 10:05:35.430234 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 10:05:35.433448 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 10:05:35.436653 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 10:05:35.443417 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 10:05:35.446211 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 10:05:35.449685 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 10:05:35.456201 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 10:05:35.459944 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 10:05:35.462855 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 10:05:35.469458 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 10:05:35.473014 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 10:05:35.475994 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 10:05:35.482892 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 10:05:35.485877 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5585 10:05:35.488969 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5586 10:05:35.492683 Total UI for P1: 0, mck2ui 16
5587 10:05:35.496079 best dqsien dly found for B0: ( 1, 2, 28)
5588 10:05:35.502121 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 10:05:35.502203 Total UI for P1: 0, mck2ui 16
5590 10:05:35.508958 best dqsien dly found for B1: ( 1, 2, 30)
5591 10:05:35.512008 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5592 10:05:35.515331 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5593 10:05:35.515411
5594 10:05:35.518730 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5595 10:05:35.522196 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5596 10:05:35.525580 [Gating] SW calibration Done
5597 10:05:35.525662 ==
5598 10:05:35.528220 Dram Type= 6, Freq= 0, CH_1, rank 0
5599 10:05:35.531650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5600 10:05:35.531732 ==
5601 10:05:35.535478 RX Vref Scan: 0
5602 10:05:35.535560
5603 10:05:35.535625 RX Vref 0 -> 0, step: 1
5604 10:05:35.538266
5605 10:05:35.538348 RX Delay -80 -> 252, step: 8
5606 10:05:35.545266 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5607 10:05:35.548424 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5608 10:05:35.551865 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5609 10:05:35.554947 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5610 10:05:35.558801 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5611 10:05:35.561588 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5612 10:05:35.567979 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5613 10:05:35.571420 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5614 10:05:35.574754 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5615 10:05:35.578282 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5616 10:05:35.581329 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5617 10:05:35.584401 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5618 10:05:35.591073 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5619 10:05:35.594148 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5620 10:05:35.597575 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5621 10:05:35.600667 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5622 10:05:35.600749 ==
5623 10:05:35.604199 Dram Type= 6, Freq= 0, CH_1, rank 0
5624 10:05:35.611445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5625 10:05:35.611528 ==
5626 10:05:35.611607 DQS Delay:
5627 10:05:35.614252 DQS0 = 0, DQS1 = 0
5628 10:05:35.614325 DQM Delay:
5629 10:05:35.617602 DQM0 = 100, DQM1 = 95
5630 10:05:35.617674 DQ Delay:
5631 10:05:35.620756 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5632 10:05:35.624005 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5633 10:05:35.627189 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5634 10:05:35.630628 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5635 10:05:35.630704
5636 10:05:35.630800
5637 10:05:35.630863 ==
5638 10:05:35.633494 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 10:05:35.637166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 10:05:35.637243 ==
5641 10:05:35.640578
5642 10:05:35.640652
5643 10:05:35.640713 TX Vref Scan disable
5644 10:05:35.643753 == TX Byte 0 ==
5645 10:05:35.646935 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5646 10:05:35.650241 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5647 10:05:35.653301 == TX Byte 1 ==
5648 10:05:35.657026 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5649 10:05:35.659919 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5650 10:05:35.660017 ==
5651 10:05:35.663638 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 10:05:35.670258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 10:05:35.670387 ==
5654 10:05:35.670451
5655 10:05:35.670509
5656 10:05:35.673740 TX Vref Scan disable
5657 10:05:35.673820 == TX Byte 0 ==
5658 10:05:35.680065 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5659 10:05:35.683564 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5660 10:05:35.683646 == TX Byte 1 ==
5661 10:05:35.689874 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5662 10:05:35.692904 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5663 10:05:35.692985
5664 10:05:35.693049 [DATLAT]
5665 10:05:35.696511 Freq=933, CH1 RK0
5666 10:05:35.696592
5667 10:05:35.696655 DATLAT Default: 0xd
5668 10:05:35.699747 0, 0xFFFF, sum = 0
5669 10:05:35.699830 1, 0xFFFF, sum = 0
5670 10:05:35.702642 2, 0xFFFF, sum = 0
5671 10:05:35.702723 3, 0xFFFF, sum = 0
5672 10:05:35.706143 4, 0xFFFF, sum = 0
5673 10:05:35.709188 5, 0xFFFF, sum = 0
5674 10:05:35.709272 6, 0xFFFF, sum = 0
5675 10:05:35.712689 7, 0xFFFF, sum = 0
5676 10:05:35.712776 8, 0xFFFF, sum = 0
5677 10:05:35.716300 9, 0xFFFF, sum = 0
5678 10:05:35.716383 10, 0x0, sum = 1
5679 10:05:35.719197 11, 0x0, sum = 2
5680 10:05:35.719279 12, 0x0, sum = 3
5681 10:05:35.719344 13, 0x0, sum = 4
5682 10:05:35.722507 best_step = 11
5683 10:05:35.722575
5684 10:05:35.722633 ==
5685 10:05:35.725831 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 10:05:35.729397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 10:05:35.729478 ==
5688 10:05:35.733047 RX Vref Scan: 1
5689 10:05:35.733153
5690 10:05:35.735552 RX Vref 0 -> 0, step: 1
5691 10:05:35.735632
5692 10:05:35.735696 RX Delay -53 -> 252, step: 4
5693 10:05:35.735755
5694 10:05:35.739434 Set Vref, RX VrefLevel [Byte0]: 54
5695 10:05:35.742179 [Byte1]: 52
5696 10:05:35.747056
5697 10:05:35.747140 Final RX Vref Byte 0 = 54 to rank0
5698 10:05:35.749976 Final RX Vref Byte 1 = 52 to rank0
5699 10:05:35.753520 Final RX Vref Byte 0 = 54 to rank1
5700 10:05:35.756752 Final RX Vref Byte 1 = 52 to rank1==
5701 10:05:35.760229 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 10:05:35.766705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 10:05:35.766787 ==
5704 10:05:35.766852 DQS Delay:
5705 10:05:35.770537 DQS0 = 0, DQS1 = 0
5706 10:05:35.770617 DQM Delay:
5707 10:05:35.770681 DQM0 = 98, DQM1 = 94
5708 10:05:35.773469 DQ Delay:
5709 10:05:35.776675 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =98
5710 10:05:35.779956 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5711 10:05:35.783207 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5712 10:05:35.786340 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5713 10:05:35.786421
5714 10:05:35.786484
5715 10:05:35.793218 [DQSOSCAuto] RK0, (LSB)MR18= 0x717, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5716 10:05:35.796374 CH1 RK0: MR19=505, MR18=717
5717 10:05:35.803339 CH1_RK0: MR19=0x505, MR18=0x717, DQSOSC=414, MR23=63, INC=63, DEC=42
5718 10:05:35.803421
5719 10:05:35.806285 ----->DramcWriteLeveling(PI) begin...
5720 10:05:35.806368 ==
5721 10:05:35.809407 Dram Type= 6, Freq= 0, CH_1, rank 1
5722 10:05:35.812974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 10:05:35.813059 ==
5724 10:05:35.816007 Write leveling (Byte 0): 26 => 26
5725 10:05:35.819632 Write leveling (Byte 1): 29 => 29
5726 10:05:35.822561 DramcWriteLeveling(PI) end<-----
5727 10:05:35.822642
5728 10:05:35.822706 ==
5729 10:05:35.826120 Dram Type= 6, Freq= 0, CH_1, rank 1
5730 10:05:35.832474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 10:05:35.832556 ==
5732 10:05:35.832622 [Gating] SW mode calibration
5733 10:05:35.842351 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5734 10:05:35.845993 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5735 10:05:35.852237 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5736 10:05:35.855640 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5737 10:05:35.858974 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5738 10:05:35.865711 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 10:05:35.868874 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 10:05:35.872211 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 10:05:35.878764 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5742 10:05:35.882290 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5743 10:05:35.885324 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5744 10:05:35.891753 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5745 10:05:35.894876 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5746 10:05:35.899099 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 10:05:35.904800 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 10:05:35.908286 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 10:05:35.911294 0 15 24 | B1->B0 | 2828 3232 | 0 0 | (0 0) (0 0)
5750 10:05:35.917935 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
5751 10:05:35.921440 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5752 10:05:35.924637 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5753 10:05:35.931387 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 10:05:35.934675 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 10:05:35.937878 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 10:05:35.944705 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 10:05:35.947508 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5758 10:05:35.951321 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5759 10:05:35.957502 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 10:05:35.960848 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 10:05:35.964257 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 10:05:35.970669 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 10:05:35.973856 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 10:05:35.977726 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 10:05:35.983664 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 10:05:35.987072 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 10:05:35.990396 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 10:05:35.996971 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 10:05:36.000806 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 10:05:36.004336 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 10:05:36.010244 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 10:05:36.013172 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5773 10:05:36.016794 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5774 10:05:36.023380 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 10:05:36.023468 Total UI for P1: 0, mck2ui 16
5776 10:05:36.030133 best dqsien dly found for B0: ( 1, 2, 22)
5777 10:05:36.030210 Total UI for P1: 0, mck2ui 16
5778 10:05:36.036712 best dqsien dly found for B1: ( 1, 2, 26)
5779 10:05:36.039962 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5780 10:05:36.043436 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5781 10:05:36.043516
5782 10:05:36.046176 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5783 10:05:36.049709 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5784 10:05:36.053072 [Gating] SW calibration Done
5785 10:05:36.053155 ==
5786 10:05:36.056546 Dram Type= 6, Freq= 0, CH_1, rank 1
5787 10:05:36.059814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 10:05:36.059896 ==
5789 10:05:36.062898 RX Vref Scan: 0
5790 10:05:36.062978
5791 10:05:36.063041 RX Vref 0 -> 0, step: 1
5792 10:05:36.063101
5793 10:05:36.066275 RX Delay -80 -> 252, step: 8
5794 10:05:36.069922 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5795 10:05:36.076419 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5796 10:05:36.079745 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5797 10:05:36.082731 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5798 10:05:36.086148 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5799 10:05:36.089530 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5800 10:05:36.092782 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5801 10:05:36.099054 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5802 10:05:36.102468 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5803 10:05:36.105825 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5804 10:05:36.110117 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5805 10:05:36.112932 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5806 10:05:36.119360 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5807 10:05:36.122538 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5808 10:05:36.125720 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5809 10:05:36.128755 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5810 10:05:36.128837 ==
5811 10:05:36.132530 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 10:05:36.139132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 10:05:36.139215 ==
5814 10:05:36.139281 DQS Delay:
5815 10:05:36.139341 DQS0 = 0, DQS1 = 0
5816 10:05:36.142161 DQM Delay:
5817 10:05:36.142231 DQM0 = 97, DQM1 = 94
5818 10:05:36.145130 DQ Delay:
5819 10:05:36.148739 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5820 10:05:36.151640 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5821 10:05:36.155072 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5822 10:05:36.158493 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5823 10:05:36.158573
5824 10:05:36.158637
5825 10:05:36.158697 ==
5826 10:05:36.161801 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 10:05:36.165101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 10:05:36.165200 ==
5829 10:05:36.165278
5830 10:05:36.165337
5831 10:05:36.168421 TX Vref Scan disable
5832 10:05:36.171659 == TX Byte 0 ==
5833 10:05:36.175057 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5834 10:05:36.178689 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5835 10:05:36.181221 == TX Byte 1 ==
5836 10:05:36.184750 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5837 10:05:36.188357 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5838 10:05:36.188438 ==
5839 10:05:36.191167 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 10:05:36.198012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 10:05:36.198096 ==
5842 10:05:36.198161
5843 10:05:36.198219
5844 10:05:36.198276 TX Vref Scan disable
5845 10:05:36.201750 == TX Byte 0 ==
5846 10:05:36.204983 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5847 10:05:36.212034 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5848 10:05:36.212127 == TX Byte 1 ==
5849 10:05:36.215978 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5850 10:05:36.221453 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5851 10:05:36.221560
5852 10:05:36.221665 [DATLAT]
5853 10:05:36.221756 Freq=933, CH1 RK1
5854 10:05:36.221858
5855 10:05:36.225046 DATLAT Default: 0xb
5856 10:05:36.225162 0, 0xFFFF, sum = 0
5857 10:05:36.228233 1, 0xFFFF, sum = 0
5858 10:05:36.231522 2, 0xFFFF, sum = 0
5859 10:05:36.231597 3, 0xFFFF, sum = 0
5860 10:05:36.234960 4, 0xFFFF, sum = 0
5861 10:05:36.235046 5, 0xFFFF, sum = 0
5862 10:05:36.238022 6, 0xFFFF, sum = 0
5863 10:05:36.238108 7, 0xFFFF, sum = 0
5864 10:05:36.242041 8, 0xFFFF, sum = 0
5865 10:05:36.242157 9, 0xFFFF, sum = 0
5866 10:05:36.244597 10, 0x0, sum = 1
5867 10:05:36.244682 11, 0x0, sum = 2
5868 10:05:36.247932 12, 0x0, sum = 3
5869 10:05:36.248020 13, 0x0, sum = 4
5870 10:05:36.248126 best_step = 11
5871 10:05:36.251831
5872 10:05:36.251916 ==
5873 10:05:36.255370 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 10:05:36.258024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 10:05:36.258108 ==
5876 10:05:36.258193 RX Vref Scan: 0
5877 10:05:36.258288
5878 10:05:36.261338 RX Vref 0 -> 0, step: 1
5879 10:05:36.261450
5880 10:05:36.264842 RX Delay -61 -> 252, step: 4
5881 10:05:36.271155 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5882 10:05:36.274682 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5883 10:05:36.277926 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5884 10:05:36.281313 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5885 10:05:36.284810 iDelay=199, Bit 4, Center 98 (3 ~ 194) 192
5886 10:05:36.287538 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5887 10:05:36.294197 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5888 10:05:36.297819 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5889 10:05:36.301028 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5890 10:05:36.304393 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5891 10:05:36.307472 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5892 10:05:36.313820 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5893 10:05:36.317510 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5894 10:05:36.320876 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5895 10:05:36.323930 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5896 10:05:36.330990 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5897 10:05:36.331075 ==
5898 10:05:36.333574 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 10:05:36.336871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 10:05:36.337015 ==
5901 10:05:36.337133 DQS Delay:
5902 10:05:36.340343 DQS0 = 0, DQS1 = 0
5903 10:05:36.340464 DQM Delay:
5904 10:05:36.343427 DQM0 = 97, DQM1 = 92
5905 10:05:36.343526 DQ Delay:
5906 10:05:36.347212 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =92
5907 10:05:36.350327 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =94
5908 10:05:36.353490 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5909 10:05:36.357086 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =102
5910 10:05:36.357170
5911 10:05:36.357253
5912 10:05:36.366412 [DQSOSCAuto] RK1, (LSB)MR18= 0xd23, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5913 10:05:36.366514 CH1 RK1: MR19=505, MR18=D23
5914 10:05:36.373053 CH1_RK1: MR19=0x505, MR18=0xD23, DQSOSC=410, MR23=63, INC=64, DEC=42
5915 10:05:36.376241 [RxdqsGatingPostProcess] freq 933
5916 10:05:36.383287 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5917 10:05:36.386330 best DQS0 dly(2T, 0.5T) = (0, 10)
5918 10:05:36.389464 best DQS1 dly(2T, 0.5T) = (0, 10)
5919 10:05:36.392830 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5920 10:05:36.396196 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5921 10:05:36.399497 best DQS0 dly(2T, 0.5T) = (0, 10)
5922 10:05:36.402993 best DQS1 dly(2T, 0.5T) = (0, 10)
5923 10:05:36.403077 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5924 10:05:36.406292 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5925 10:05:36.409843 Pre-setting of DQS Precalculation
5926 10:05:36.416260 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5927 10:05:36.422413 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5928 10:05:36.429118 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5929 10:05:36.429195
5930 10:05:36.429259
5931 10:05:36.432644 [Calibration Summary] 1866 Mbps
5932 10:05:36.435572 CH 0, Rank 0
5933 10:05:36.435641 SW Impedance : PASS
5934 10:05:36.439186 DUTY Scan : NO K
5935 10:05:36.442498 ZQ Calibration : PASS
5936 10:05:36.442573 Jitter Meter : NO K
5937 10:05:36.445391 CBT Training : PASS
5938 10:05:36.448870 Write leveling : PASS
5939 10:05:36.448941 RX DQS gating : PASS
5940 10:05:36.452171 RX DQ/DQS(RDDQC) : PASS
5941 10:05:36.455297 TX DQ/DQS : PASS
5942 10:05:36.455366 RX DATLAT : PASS
5943 10:05:36.458960 RX DQ/DQS(Engine): PASS
5944 10:05:36.459032 TX OE : NO K
5945 10:05:36.461984 All Pass.
5946 10:05:36.462055
5947 10:05:36.462114 CH 0, Rank 1
5948 10:05:36.465615 SW Impedance : PASS
5949 10:05:36.468750 DUTY Scan : NO K
5950 10:05:36.468832 ZQ Calibration : PASS
5951 10:05:36.471830 Jitter Meter : NO K
5952 10:05:36.471937 CBT Training : PASS
5953 10:05:36.475502 Write leveling : PASS
5954 10:05:36.478920 RX DQS gating : PASS
5955 10:05:36.479001 RX DQ/DQS(RDDQC) : PASS
5956 10:05:36.482115 TX DQ/DQS : PASS
5957 10:05:36.485159 RX DATLAT : PASS
5958 10:05:36.485240 RX DQ/DQS(Engine): PASS
5959 10:05:36.488496 TX OE : NO K
5960 10:05:36.488577 All Pass.
5961 10:05:36.488641
5962 10:05:36.491636 CH 1, Rank 0
5963 10:05:36.491717 SW Impedance : PASS
5964 10:05:36.495145 DUTY Scan : NO K
5965 10:05:36.498456 ZQ Calibration : PASS
5966 10:05:36.498537 Jitter Meter : NO K
5967 10:05:36.501581 CBT Training : PASS
5968 10:05:36.504638 Write leveling : PASS
5969 10:05:36.504718 RX DQS gating : PASS
5970 10:05:36.507937 RX DQ/DQS(RDDQC) : PASS
5971 10:05:36.511315 TX DQ/DQS : PASS
5972 10:05:36.511396 RX DATLAT : PASS
5973 10:05:36.514749 RX DQ/DQS(Engine): PASS
5974 10:05:36.517792 TX OE : NO K
5975 10:05:36.517868 All Pass.
5976 10:05:36.517929
5977 10:05:36.517986 CH 1, Rank 1
5978 10:05:36.521652 SW Impedance : PASS
5979 10:05:36.524507 DUTY Scan : NO K
5980 10:05:36.524575 ZQ Calibration : PASS
5981 10:05:36.527748 Jitter Meter : NO K
5982 10:05:36.531500 CBT Training : PASS
5983 10:05:36.531569 Write leveling : PASS
5984 10:05:36.534464 RX DQS gating : PASS
5985 10:05:36.537575 RX DQ/DQS(RDDQC) : PASS
5986 10:05:36.537678 TX DQ/DQS : PASS
5987 10:05:36.541387 RX DATLAT : PASS
5988 10:05:36.544279 RX DQ/DQS(Engine): PASS
5989 10:05:36.544350 TX OE : NO K
5990 10:05:36.544408 All Pass.
5991 10:05:36.547679
5992 10:05:36.547753 DramC Write-DBI off
5993 10:05:36.551000 PER_BANK_REFRESH: Hybrid Mode
5994 10:05:36.551108 TX_TRACKING: ON
5995 10:05:36.560641 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5996 10:05:36.563806 [FAST_K] Save calibration result to emmc
5997 10:05:36.567224 dramc_set_vcore_voltage set vcore to 650000
5998 10:05:36.570601 Read voltage for 400, 6
5999 10:05:36.570685 Vio18 = 0
6000 10:05:36.573852 Vcore = 650000
6001 10:05:36.573934 Vdram = 0
6002 10:05:36.574017 Vddq = 0
6003 10:05:36.576917 Vmddr = 0
6004 10:05:36.580564 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6005 10:05:36.586890 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6006 10:05:36.586973 MEM_TYPE=3, freq_sel=20
6007 10:05:36.590453 sv_algorithm_assistance_LP4_800
6008 10:05:36.596649 ============ PULL DRAM RESETB DOWN ============
6009 10:05:36.600197 ========== PULL DRAM RESETB DOWN end =========
6010 10:05:36.603957 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6011 10:05:36.606843 ===================================
6012 10:05:36.610127 LPDDR4 DRAM CONFIGURATION
6013 10:05:36.614051 ===================================
6014 10:05:36.614133 EX_ROW_EN[0] = 0x0
6015 10:05:36.616727 EX_ROW_EN[1] = 0x0
6016 10:05:36.620143 LP4Y_EN = 0x0
6017 10:05:36.620225 WORK_FSP = 0x0
6018 10:05:36.623557 WL = 0x2
6019 10:05:36.623639 RL = 0x2
6020 10:05:36.626473 BL = 0x2
6021 10:05:36.626556 RPST = 0x0
6022 10:05:36.629743 RD_PRE = 0x0
6023 10:05:36.629825 WR_PRE = 0x1
6024 10:05:36.633162 WR_PST = 0x0
6025 10:05:36.633244 DBI_WR = 0x0
6026 10:05:36.636140 DBI_RD = 0x0
6027 10:05:36.636222 OTF = 0x1
6028 10:05:36.639645 ===================================
6029 10:05:36.642958 ===================================
6030 10:05:36.646065 ANA top config
6031 10:05:36.649303 ===================================
6032 10:05:36.652721 DLL_ASYNC_EN = 0
6033 10:05:36.652803 ALL_SLAVE_EN = 1
6034 10:05:36.656011 NEW_RANK_MODE = 1
6035 10:05:36.659296 DLL_IDLE_MODE = 1
6036 10:05:36.662933 LP45_APHY_COMB_EN = 1
6037 10:05:36.663015 TX_ODT_DIS = 1
6038 10:05:36.665746 NEW_8X_MODE = 1
6039 10:05:36.669418 ===================================
6040 10:05:36.672515 ===================================
6041 10:05:36.676022 data_rate = 800
6042 10:05:36.679049 CKR = 1
6043 10:05:36.682639 DQ_P2S_RATIO = 4
6044 10:05:36.685938 ===================================
6045 10:05:36.688854 CA_P2S_RATIO = 4
6046 10:05:36.692389 DQ_CA_OPEN = 0
6047 10:05:36.692471 DQ_SEMI_OPEN = 1
6048 10:05:36.695586 CA_SEMI_OPEN = 1
6049 10:05:36.698568 CA_FULL_RATE = 0
6050 10:05:36.702016 DQ_CKDIV4_EN = 0
6051 10:05:36.705442 CA_CKDIV4_EN = 1
6052 10:05:36.708952 CA_PREDIV_EN = 0
6053 10:05:36.709035 PH8_DLY = 0
6054 10:05:36.711719 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6055 10:05:36.715185 DQ_AAMCK_DIV = 0
6056 10:05:36.718366 CA_AAMCK_DIV = 0
6057 10:05:36.721754 CA_ADMCK_DIV = 4
6058 10:05:36.724975 DQ_TRACK_CA_EN = 0
6059 10:05:36.728399 CA_PICK = 800
6060 10:05:36.728482 CA_MCKIO = 400
6061 10:05:36.731794 MCKIO_SEMI = 400
6062 10:05:36.735233 PLL_FREQ = 3016
6063 10:05:36.738284 DQ_UI_PI_RATIO = 32
6064 10:05:36.741605 CA_UI_PI_RATIO = 32
6065 10:05:36.744913 ===================================
6066 10:05:36.748279 ===================================
6067 10:05:36.752022 memory_type:LPDDR4
6068 10:05:36.752141 GP_NUM : 10
6069 10:05:36.754757 SRAM_EN : 1
6070 10:05:36.754839 MD32_EN : 0
6071 10:05:36.757960 ===================================
6072 10:05:36.761239 [ANA_INIT] >>>>>>>>>>>>>>
6073 10:05:36.764745 <<<<<< [CONFIGURE PHASE]: ANA_TX
6074 10:05:36.767886 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6075 10:05:36.771624 ===================================
6076 10:05:36.774525 data_rate = 800,PCW = 0X7400
6077 10:05:36.777883 ===================================
6078 10:05:36.781306 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6079 10:05:36.788078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6080 10:05:36.797521 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6081 10:05:36.803844 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6082 10:05:36.807116 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6083 10:05:36.810629 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6084 10:05:36.810731 [ANA_INIT] flow start
6085 10:05:36.813858 [ANA_INIT] PLL >>>>>>>>
6086 10:05:36.817337 [ANA_INIT] PLL <<<<<<<<
6087 10:05:36.817448 [ANA_INIT] MIDPI >>>>>>>>
6088 10:05:36.820328 [ANA_INIT] MIDPI <<<<<<<<
6089 10:05:36.823669 [ANA_INIT] DLL >>>>>>>>
6090 10:05:36.823767 [ANA_INIT] flow end
6091 10:05:36.830364 ============ LP4 DIFF to SE enter ============
6092 10:05:36.833834 ============ LP4 DIFF to SE exit ============
6093 10:05:36.836714 [ANA_INIT] <<<<<<<<<<<<<
6094 10:05:36.840042 [Flow] Enable top DCM control >>>>>
6095 10:05:36.843571 [Flow] Enable top DCM control <<<<<
6096 10:05:36.843694 Enable DLL master slave shuffle
6097 10:05:36.849914 ==============================================================
6098 10:05:36.853340 Gating Mode config
6099 10:05:36.856904 ==============================================================
6100 10:05:36.860167 Config description:
6101 10:05:36.869551 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6102 10:05:36.876225 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6103 10:05:36.879459 SELPH_MODE 0: By rank 1: By Phase
6104 10:05:36.886441 ==============================================================
6105 10:05:36.889482 GAT_TRACK_EN = 0
6106 10:05:36.892589 RX_GATING_MODE = 2
6107 10:05:36.895897 RX_GATING_TRACK_MODE = 2
6108 10:05:36.899376 SELPH_MODE = 1
6109 10:05:36.902403 PICG_EARLY_EN = 1
6110 10:05:36.905836 VALID_LAT_VALUE = 1
6111 10:05:36.909142 ==============================================================
6112 10:05:36.912432 Enter into Gating configuration >>>>
6113 10:05:36.915962 Exit from Gating configuration <<<<
6114 10:05:36.919227 Enter into DVFS_PRE_config >>>>>
6115 10:05:36.932158 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6116 10:05:36.932249 Exit from DVFS_PRE_config <<<<<
6117 10:05:36.935859 Enter into PICG configuration >>>>
6118 10:05:36.938909 Exit from PICG configuration <<<<
6119 10:05:36.942356 [RX_INPUT] configuration >>>>>
6120 10:05:36.945740 [RX_INPUT] configuration <<<<<
6121 10:05:36.952188 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6122 10:05:36.955619 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6123 10:05:36.961991 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6124 10:05:36.968613 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6125 10:05:36.974832 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6126 10:05:36.982427 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6127 10:05:36.984723 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6128 10:05:36.987945 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6129 10:05:36.994721 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6130 10:05:36.997869 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6131 10:05:37.001132 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6132 10:05:37.004764 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6133 10:05:37.007721 ===================================
6134 10:05:37.011611 LPDDR4 DRAM CONFIGURATION
6135 10:05:37.014272 ===================================
6136 10:05:37.017722 EX_ROW_EN[0] = 0x0
6137 10:05:37.017806 EX_ROW_EN[1] = 0x0
6138 10:05:37.021339 LP4Y_EN = 0x0
6139 10:05:37.021423 WORK_FSP = 0x0
6140 10:05:37.024620 WL = 0x2
6141 10:05:37.024704 RL = 0x2
6142 10:05:37.027585 BL = 0x2
6143 10:05:37.027669 RPST = 0x0
6144 10:05:37.031043 RD_PRE = 0x0
6145 10:05:37.034394 WR_PRE = 0x1
6146 10:05:37.034477 WR_PST = 0x0
6147 10:05:37.037458 DBI_WR = 0x0
6148 10:05:37.037541 DBI_RD = 0x0
6149 10:05:37.040802 OTF = 0x1
6150 10:05:37.044200 ===================================
6151 10:05:37.047824 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6152 10:05:37.050662 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6153 10:05:37.053866 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6154 10:05:37.057189 ===================================
6155 10:05:37.060658 LPDDR4 DRAM CONFIGURATION
6156 10:05:37.064180 ===================================
6157 10:05:37.067385 EX_ROW_EN[0] = 0x10
6158 10:05:37.067469 EX_ROW_EN[1] = 0x0
6159 10:05:37.070616 LP4Y_EN = 0x0
6160 10:05:37.070700 WORK_FSP = 0x0
6161 10:05:37.074248 WL = 0x2
6162 10:05:37.074332 RL = 0x2
6163 10:05:37.077545 BL = 0x2
6164 10:05:37.080678 RPST = 0x0
6165 10:05:37.080762 RD_PRE = 0x0
6166 10:05:37.083767 WR_PRE = 0x1
6167 10:05:37.083851 WR_PST = 0x0
6168 10:05:37.086889 DBI_WR = 0x0
6169 10:05:37.086972 DBI_RD = 0x0
6170 10:05:37.090560 OTF = 0x1
6171 10:05:37.093392 ===================================
6172 10:05:37.100114 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6173 10:05:37.103605 nWR fixed to 30
6174 10:05:37.103691 [ModeRegInit_LP4] CH0 RK0
6175 10:05:37.106669 [ModeRegInit_LP4] CH0 RK1
6176 10:05:37.109808 [ModeRegInit_LP4] CH1 RK0
6177 10:05:37.109896 [ModeRegInit_LP4] CH1 RK1
6178 10:05:37.113257 match AC timing 19
6179 10:05:37.116556 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6180 10:05:37.119747 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6181 10:05:37.126911 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6182 10:05:37.129790 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6183 10:05:37.136485 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6184 10:05:37.136570 ==
6185 10:05:37.139603 Dram Type= 6, Freq= 0, CH_0, rank 0
6186 10:05:37.142995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6187 10:05:37.143077 ==
6188 10:05:37.149403 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6189 10:05:37.156668 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6190 10:05:37.159638 [CA 0] Center 36 (8~64) winsize 57
6191 10:05:37.159720 [CA 1] Center 36 (8~64) winsize 57
6192 10:05:37.162697 [CA 2] Center 36 (8~64) winsize 57
6193 10:05:37.165990 [CA 3] Center 36 (8~64) winsize 57
6194 10:05:37.169539 [CA 4] Center 36 (8~64) winsize 57
6195 10:05:37.173003 [CA 5] Center 36 (8~64) winsize 57
6196 10:05:37.173085
6197 10:05:37.175843 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6198 10:05:37.175925
6199 10:05:37.179162 [CATrainingPosCal] consider 1 rank data
6200 10:05:37.182622 u2DelayCellTimex100 = 270/100 ps
6201 10:05:37.185674 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6202 10:05:37.192493 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6203 10:05:37.195635 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6204 10:05:37.198910 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 10:05:37.202470 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 10:05:37.205564 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 10:05:37.205649
6208 10:05:37.208892 CA PerBit enable=1, Macro0, CA PI delay=36
6209 10:05:37.208975
6210 10:05:37.212018 [CBTSetCACLKResult] CA Dly = 36
6211 10:05:37.215523 CS Dly: 1 (0~32)
6212 10:05:37.215607 ==
6213 10:05:37.218645 Dram Type= 6, Freq= 0, CH_0, rank 1
6214 10:05:37.222439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6215 10:05:37.222525 ==
6216 10:05:37.228917 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6217 10:05:37.231989 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6218 10:05:37.235624 [CA 0] Center 36 (8~64) winsize 57
6219 10:05:37.238527 [CA 1] Center 36 (8~64) winsize 57
6220 10:05:37.242000 [CA 2] Center 36 (8~64) winsize 57
6221 10:05:37.245056 [CA 3] Center 36 (8~64) winsize 57
6222 10:05:37.248476 [CA 4] Center 36 (8~64) winsize 57
6223 10:05:37.251985 [CA 5] Center 36 (8~64) winsize 57
6224 10:05:37.252110
6225 10:05:37.255426 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6226 10:05:37.255510
6227 10:05:37.258545 [CATrainingPosCal] consider 2 rank data
6228 10:05:37.261693 u2DelayCellTimex100 = 270/100 ps
6229 10:05:37.264917 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 10:05:37.271408 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 10:05:37.274767 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 10:05:37.278254 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 10:05:37.281496 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 10:05:37.284808 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 10:05:37.284892
6236 10:05:37.287898 CA PerBit enable=1, Macro0, CA PI delay=36
6237 10:05:37.287983
6238 10:05:37.290963 [CBTSetCACLKResult] CA Dly = 36
6239 10:05:37.291047 CS Dly: 1 (0~32)
6240 10:05:37.294487
6241 10:05:37.297914 ----->DramcWriteLeveling(PI) begin...
6242 10:05:37.298017 ==
6243 10:05:37.300868 Dram Type= 6, Freq= 0, CH_0, rank 0
6244 10:05:37.304345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6245 10:05:37.304430 ==
6246 10:05:37.307408 Write leveling (Byte 0): 40 => 8
6247 10:05:37.311047 Write leveling (Byte 1): 40 => 8
6248 10:05:37.313924 DramcWriteLeveling(PI) end<-----
6249 10:05:37.314039
6250 10:05:37.314122 ==
6251 10:05:37.317163 Dram Type= 6, Freq= 0, CH_0, rank 0
6252 10:05:37.320849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 10:05:37.320934 ==
6254 10:05:37.324178 [Gating] SW mode calibration
6255 10:05:37.330525 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6256 10:05:37.337590 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6257 10:05:37.340333 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6258 10:05:37.344340 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6259 10:05:37.350356 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6260 10:05:37.353796 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6261 10:05:37.356898 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6262 10:05:37.363685 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6263 10:05:37.367125 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 10:05:37.370328 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 10:05:37.376681 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6266 10:05:37.380226 Total UI for P1: 0, mck2ui 16
6267 10:05:37.383318 best dqsien dly found for B0: ( 0, 14, 24)
6268 10:05:37.383390 Total UI for P1: 0, mck2ui 16
6269 10:05:37.390052 best dqsien dly found for B1: ( 0, 14, 24)
6270 10:05:37.393067 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6271 10:05:37.396661 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6272 10:05:37.396743
6273 10:05:37.399831 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6274 10:05:37.403073 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6275 10:05:37.406377 [Gating] SW calibration Done
6276 10:05:37.406446 ==
6277 10:05:37.409542 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 10:05:37.413089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 10:05:37.413168 ==
6280 10:05:37.416448 RX Vref Scan: 0
6281 10:05:37.416517
6282 10:05:37.419489 RX Vref 0 -> 0, step: 1
6283 10:05:37.419559
6284 10:05:37.419618 RX Delay -410 -> 252, step: 16
6285 10:05:37.426411 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6286 10:05:37.429290 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6287 10:05:37.432567 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6288 10:05:37.439442 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6289 10:05:37.442683 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6290 10:05:37.445874 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6291 10:05:37.449251 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6292 10:05:37.455598 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6293 10:05:37.458944 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6294 10:05:37.462085 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6295 10:05:37.465545 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6296 10:05:37.472101 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6297 10:05:37.476099 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6298 10:05:37.478520 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6299 10:05:37.485776 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6300 10:05:37.488399 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6301 10:05:37.488473 ==
6302 10:05:37.492010 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 10:05:37.495400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 10:05:37.495465 ==
6305 10:05:37.498391 DQS Delay:
6306 10:05:37.498466 DQS0 = 35, DQS1 = 51
6307 10:05:37.498536 DQM Delay:
6308 10:05:37.502115 DQM0 = 5, DQM1 = 11
6309 10:05:37.502180 DQ Delay:
6310 10:05:37.504942 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6311 10:05:37.508789 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6312 10:05:37.511720 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6313 10:05:37.514748 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6314 10:05:37.514819
6315 10:05:37.514880
6316 10:05:37.514936 ==
6317 10:05:37.518470 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 10:05:37.521497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 10:05:37.521567 ==
6320 10:05:37.524772
6321 10:05:37.524838
6322 10:05:37.524895 TX Vref Scan disable
6323 10:05:37.528012 == TX Byte 0 ==
6324 10:05:37.531371 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6325 10:05:37.534832 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6326 10:05:37.538048 == TX Byte 1 ==
6327 10:05:37.541138 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6328 10:05:37.544501 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6329 10:05:37.544572 ==
6330 10:05:37.547621 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 10:05:37.554251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 10:05:37.554325 ==
6333 10:05:37.554384
6334 10:05:37.554450
6335 10:05:37.554506 TX Vref Scan disable
6336 10:05:37.557495 == TX Byte 0 ==
6337 10:05:37.560845 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 10:05:37.564290 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 10:05:37.567580 == TX Byte 1 ==
6340 10:05:37.570923 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 10:05:37.574265 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 10:05:37.574350
6343 10:05:37.577665 [DATLAT]
6344 10:05:37.577788 Freq=400, CH0 RK0
6345 10:05:37.577884
6346 10:05:37.580698 DATLAT Default: 0xf
6347 10:05:37.580767 0, 0xFFFF, sum = 0
6348 10:05:37.583771 1, 0xFFFF, sum = 0
6349 10:05:37.583852 2, 0xFFFF, sum = 0
6350 10:05:37.587122 3, 0xFFFF, sum = 0
6351 10:05:37.587203 4, 0xFFFF, sum = 0
6352 10:05:37.590416 5, 0xFFFF, sum = 0
6353 10:05:37.590512 6, 0xFFFF, sum = 0
6354 10:05:37.593853 7, 0xFFFF, sum = 0
6355 10:05:37.596832 8, 0xFFFF, sum = 0
6356 10:05:37.596903 9, 0xFFFF, sum = 0
6357 10:05:37.600103 10, 0xFFFF, sum = 0
6358 10:05:37.600171 11, 0xFFFF, sum = 0
6359 10:05:37.603405 12, 0xFFFF, sum = 0
6360 10:05:37.603481 13, 0x0, sum = 1
6361 10:05:37.606969 14, 0x0, sum = 2
6362 10:05:37.607036 15, 0x0, sum = 3
6363 10:05:37.609877 16, 0x0, sum = 4
6364 10:05:37.609947 best_step = 14
6365 10:05:37.610004
6366 10:05:37.610057 ==
6367 10:05:37.613265 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 10:05:37.616566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 10:05:37.619880 ==
6370 10:05:37.619975 RX Vref Scan: 1
6371 10:05:37.620080
6372 10:05:37.623127 RX Vref 0 -> 0, step: 1
6373 10:05:37.623194
6374 10:05:37.626582 RX Delay -343 -> 252, step: 8
6375 10:05:37.626653
6376 10:05:37.629802 Set Vref, RX VrefLevel [Byte0]: 53
6377 10:05:37.633510 [Byte1]: 44
6378 10:05:37.633610
6379 10:05:37.636202 Final RX Vref Byte 0 = 53 to rank0
6380 10:05:37.639777 Final RX Vref Byte 1 = 44 to rank0
6381 10:05:37.643355 Final RX Vref Byte 0 = 53 to rank1
6382 10:05:37.646481 Final RX Vref Byte 1 = 44 to rank1==
6383 10:05:37.649682 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 10:05:37.653393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 10:05:37.653474 ==
6386 10:05:37.656429 DQS Delay:
6387 10:05:37.656524 DQS0 = 44, DQS1 = 56
6388 10:05:37.659632 DQM Delay:
6389 10:05:37.659699 DQM0 = 10, DQM1 = 13
6390 10:05:37.663006 DQ Delay:
6391 10:05:37.663076 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6392 10:05:37.665954 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6393 10:05:37.669400 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6394 10:05:37.672630 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
6395 10:05:37.672704
6396 10:05:37.672765
6397 10:05:37.683000 [DQSOSCAuto] RK0, (LSB)MR18= 0x8d7f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6398 10:05:37.685941 CH0 RK0: MR19=C0C, MR18=8D7F
6399 10:05:37.692712 CH0_RK0: MR19=0xC0C, MR18=0x8D7F, DQSOSC=392, MR23=63, INC=384, DEC=256
6400 10:05:37.692784 ==
6401 10:05:37.695709 Dram Type= 6, Freq= 0, CH_0, rank 1
6402 10:05:37.699223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 10:05:37.699295 ==
6404 10:05:37.702146 [Gating] SW mode calibration
6405 10:05:37.709041 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6406 10:05:37.715746 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6407 10:05:37.719181 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6408 10:05:37.722036 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6409 10:05:37.728284 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6410 10:05:37.731838 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6411 10:05:37.735087 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6412 10:05:37.742082 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6413 10:05:37.745209 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6414 10:05:37.748486 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 10:05:37.755016 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6416 10:05:37.755092 Total UI for P1: 0, mck2ui 16
6417 10:05:37.758183 best dqsien dly found for B0: ( 0, 14, 24)
6418 10:05:37.761543 Total UI for P1: 0, mck2ui 16
6419 10:05:37.764891 best dqsien dly found for B1: ( 0, 14, 24)
6420 10:05:37.771158 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6421 10:05:37.774689 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6422 10:05:37.774791
6423 10:05:37.777987 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6424 10:05:37.781277 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6425 10:05:37.784627 [Gating] SW calibration Done
6426 10:05:37.784708 ==
6427 10:05:37.787707 Dram Type= 6, Freq= 0, CH_0, rank 1
6428 10:05:37.791529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 10:05:37.791623 ==
6430 10:05:37.794419 RX Vref Scan: 0
6431 10:05:37.794486
6432 10:05:37.794544 RX Vref 0 -> 0, step: 1
6433 10:05:37.794600
6434 10:05:37.798491 RX Delay -410 -> 252, step: 16
6435 10:05:37.804403 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6436 10:05:37.807828 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6437 10:05:37.810891 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6438 10:05:37.814139 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6439 10:05:37.820744 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6440 10:05:37.824094 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6441 10:05:37.827670 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6442 10:05:37.831040 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6443 10:05:37.837335 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6444 10:05:37.840521 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6445 10:05:37.844024 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6446 10:05:37.847393 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6447 10:05:37.854188 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6448 10:05:37.857229 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6449 10:05:37.860255 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6450 10:05:37.867256 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6451 10:05:37.867345 ==
6452 10:05:37.870394 Dram Type= 6, Freq= 0, CH_0, rank 1
6453 10:05:37.873713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 10:05:37.873815 ==
6455 10:05:37.873909 DQS Delay:
6456 10:05:37.876831 DQS0 = 35, DQS1 = 51
6457 10:05:37.876927 DQM Delay:
6458 10:05:37.880775 DQM0 = 8, DQM1 = 10
6459 10:05:37.880856 DQ Delay:
6460 10:05:37.883232 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6461 10:05:37.886643 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6462 10:05:37.890098 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6463 10:05:37.893510 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6464 10:05:37.893578
6465 10:05:37.893637
6466 10:05:37.893692 ==
6467 10:05:37.896749 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 10:05:37.899952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 10:05:37.900065 ==
6470 10:05:37.900140
6471 10:05:37.900196
6472 10:05:37.903499 TX Vref Scan disable
6473 10:05:37.903562 == TX Byte 0 ==
6474 10:05:37.909630 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6475 10:05:37.912888 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6476 10:05:37.912981 == TX Byte 1 ==
6477 10:05:37.919667 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6478 10:05:37.923034 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6479 10:05:37.923115 ==
6480 10:05:37.926361 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 10:05:37.930117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 10:05:37.930206 ==
6483 10:05:37.930266
6484 10:05:37.932741
6485 10:05:37.932807 TX Vref Scan disable
6486 10:05:37.936064 == TX Byte 0 ==
6487 10:05:37.939219 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6488 10:05:37.943086 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6489 10:05:37.945776 == TX Byte 1 ==
6490 10:05:37.949265 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6491 10:05:37.952593 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6492 10:05:37.952691
6493 10:05:37.952799 [DATLAT]
6494 10:05:37.955850 Freq=400, CH0 RK1
6495 10:05:37.955948
6496 10:05:37.959501 DATLAT Default: 0xe
6497 10:05:37.959598 0, 0xFFFF, sum = 0
6498 10:05:37.962782 1, 0xFFFF, sum = 0
6499 10:05:37.962882 2, 0xFFFF, sum = 0
6500 10:05:37.965448 3, 0xFFFF, sum = 0
6501 10:05:37.965558 4, 0xFFFF, sum = 0
6502 10:05:37.969043 5, 0xFFFF, sum = 0
6503 10:05:37.969149 6, 0xFFFF, sum = 0
6504 10:05:37.972337 7, 0xFFFF, sum = 0
6505 10:05:37.972436 8, 0xFFFF, sum = 0
6506 10:05:37.975341 9, 0xFFFF, sum = 0
6507 10:05:37.975415 10, 0xFFFF, sum = 0
6508 10:05:37.979026 11, 0xFFFF, sum = 0
6509 10:05:37.979126 12, 0xFFFF, sum = 0
6510 10:05:37.981878 13, 0x0, sum = 1
6511 10:05:37.981972 14, 0x0, sum = 2
6512 10:05:37.985278 15, 0x0, sum = 3
6513 10:05:37.985350 16, 0x0, sum = 4
6514 10:05:37.988721 best_step = 14
6515 10:05:37.988789
6516 10:05:37.988845 ==
6517 10:05:37.992090 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 10:05:37.995385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 10:05:37.995450 ==
6520 10:05:37.998607 RX Vref Scan: 0
6521 10:05:37.998697
6522 10:05:37.998783 RX Vref 0 -> 0, step: 1
6523 10:05:37.998865
6524 10:05:38.001541 RX Delay -343 -> 252, step: 8
6525 10:05:38.009768 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6526 10:05:38.013272 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6527 10:05:38.016526 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6528 10:05:38.023519 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6529 10:05:38.026558 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6530 10:05:38.029888 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6531 10:05:38.032785 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6532 10:05:38.039511 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6533 10:05:38.042898 iDelay=209, Bit 8, Center -56 (-295 ~ 184) 480
6534 10:05:38.046518 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6535 10:05:38.049721 iDelay=209, Bit 10, Center -44 (-279 ~ 192) 472
6536 10:05:38.055799 iDelay=209, Bit 11, Center -52 (-287 ~ 184) 472
6537 10:05:38.059542 iDelay=209, Bit 12, Center -40 (-279 ~ 200) 480
6538 10:05:38.062400 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6539 10:05:38.065780 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6540 10:05:38.072506 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6541 10:05:38.072589 ==
6542 10:05:38.076144 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 10:05:38.079348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 10:05:38.079445 ==
6545 10:05:38.079509 DQS Delay:
6546 10:05:38.082386 DQS0 = 44, DQS1 = 60
6547 10:05:38.082469 DQM Delay:
6548 10:05:38.086155 DQM0 = 9, DQM1 = 14
6549 10:05:38.086239 DQ Delay:
6550 10:05:38.089067 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6551 10:05:38.092191 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6552 10:05:38.095464 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6553 10:05:38.098632 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6554 10:05:38.098716
6555 10:05:38.098801
6556 10:05:38.105801 [DQSOSCAuto] RK1, (LSB)MR18= 0x807a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6557 10:05:38.109001 CH0 RK1: MR19=C0C, MR18=807A
6558 10:05:38.115143 CH0_RK1: MR19=0xC0C, MR18=0x807A, DQSOSC=393, MR23=63, INC=382, DEC=254
6559 10:05:38.118652 [RxdqsGatingPostProcess] freq 400
6560 10:05:38.125117 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6561 10:05:38.128691 best DQS0 dly(2T, 0.5T) = (0, 10)
6562 10:05:38.131893 best DQS1 dly(2T, 0.5T) = (0, 10)
6563 10:05:38.135180 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6564 10:05:38.138711 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6565 10:05:38.141534 best DQS0 dly(2T, 0.5T) = (0, 10)
6566 10:05:38.141633 best DQS1 dly(2T, 0.5T) = (0, 10)
6567 10:05:38.144907 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6568 10:05:38.148190 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6569 10:05:38.151959 Pre-setting of DQS Precalculation
6570 10:05:38.158273 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6571 10:05:38.158348 ==
6572 10:05:38.161632 Dram Type= 6, Freq= 0, CH_1, rank 0
6573 10:05:38.164626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 10:05:38.164704 ==
6575 10:05:38.171382 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6576 10:05:38.177762 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6577 10:05:38.180914 [CA 0] Center 36 (8~64) winsize 57
6578 10:05:38.183975 [CA 1] Center 36 (8~64) winsize 57
6579 10:05:38.187943 [CA 2] Center 36 (8~64) winsize 57
6580 10:05:38.190908 [CA 3] Center 36 (8~64) winsize 57
6581 10:05:38.193974 [CA 4] Center 36 (8~64) winsize 57
6582 10:05:38.194070 [CA 5] Center 36 (8~64) winsize 57
6583 10:05:38.198054
6584 10:05:38.200582 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6585 10:05:38.200662
6586 10:05:38.203924 [CATrainingPosCal] consider 1 rank data
6587 10:05:38.207335 u2DelayCellTimex100 = 270/100 ps
6588 10:05:38.210674 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6589 10:05:38.214425 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6590 10:05:38.216963 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6591 10:05:38.220724 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 10:05:38.224231 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 10:05:38.227124 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 10:05:38.227204
6595 10:05:38.230444 CA PerBit enable=1, Macro0, CA PI delay=36
6596 10:05:38.230524
6597 10:05:38.233739 [CBTSetCACLKResult] CA Dly = 36
6598 10:05:38.237041 CS Dly: 1 (0~32)
6599 10:05:38.237128 ==
6600 10:05:38.240374 Dram Type= 6, Freq= 0, CH_1, rank 1
6601 10:05:38.243630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 10:05:38.243711 ==
6603 10:05:38.250030 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6604 10:05:38.256636 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6605 10:05:38.260006 [CA 0] Center 36 (8~64) winsize 57
6606 10:05:38.263415 [CA 1] Center 36 (8~64) winsize 57
6607 10:05:38.266644 [CA 2] Center 36 (8~64) winsize 57
6608 10:05:38.266764 [CA 3] Center 36 (8~64) winsize 57
6609 10:05:38.269973 [CA 4] Center 36 (8~64) winsize 57
6610 10:05:38.273171 [CA 5] Center 36 (8~64) winsize 57
6611 10:05:38.273246
6612 10:05:38.280022 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6613 10:05:38.280123
6614 10:05:38.283165 [CATrainingPosCal] consider 2 rank data
6615 10:05:38.286213 u2DelayCellTimex100 = 270/100 ps
6616 10:05:38.289676 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 10:05:38.292785 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 10:05:38.296327 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 10:05:38.299278 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 10:05:38.302354 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 10:05:38.306215 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 10:05:38.306286
6623 10:05:38.309115 CA PerBit enable=1, Macro0, CA PI delay=36
6624 10:05:38.309184
6625 10:05:38.312521 [CBTSetCACLKResult] CA Dly = 36
6626 10:05:38.315946 CS Dly: 1 (0~32)
6627 10:05:38.316083
6628 10:05:38.319517 ----->DramcWriteLeveling(PI) begin...
6629 10:05:38.319627 ==
6630 10:05:38.322425 Dram Type= 6, Freq= 0, CH_1, rank 0
6631 10:05:38.325364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 10:05:38.325445 ==
6633 10:05:38.329277 Write leveling (Byte 0): 40 => 8
6634 10:05:38.332408 Write leveling (Byte 1): 40 => 8
6635 10:05:38.335308 DramcWriteLeveling(PI) end<-----
6636 10:05:38.335398
6637 10:05:38.335497 ==
6638 10:05:38.338461 Dram Type= 6, Freq= 0, CH_1, rank 0
6639 10:05:38.342306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 10:05:38.342400 ==
6641 10:05:38.345340 [Gating] SW mode calibration
6642 10:05:38.352223 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6643 10:05:38.358467 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6644 10:05:38.362256 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6645 10:05:38.368810 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6646 10:05:38.371990 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6647 10:05:38.375006 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6648 10:05:38.381278 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6649 10:05:38.384819 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6650 10:05:38.388292 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6651 10:05:38.395069 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 10:05:38.398048 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6653 10:05:38.401655 Total UI for P1: 0, mck2ui 16
6654 10:05:38.404784 best dqsien dly found for B0: ( 0, 14, 24)
6655 10:05:38.407897 Total UI for P1: 0, mck2ui 16
6656 10:05:38.411135 best dqsien dly found for B1: ( 0, 14, 24)
6657 10:05:38.414568 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6658 10:05:38.418319 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6659 10:05:38.418400
6660 10:05:38.421196 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6661 10:05:38.427620 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6662 10:05:38.427700 [Gating] SW calibration Done
6663 10:05:38.427765 ==
6664 10:05:38.430812 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 10:05:38.437585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 10:05:38.437666 ==
6667 10:05:38.437730 RX Vref Scan: 0
6668 10:05:38.437831
6669 10:05:38.441137 RX Vref 0 -> 0, step: 1
6670 10:05:38.441217
6671 10:05:38.444279 RX Delay -410 -> 252, step: 16
6672 10:05:38.447368 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6673 10:05:38.450810 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6674 10:05:38.457205 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6675 10:05:38.460476 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6676 10:05:38.463659 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6677 10:05:38.467073 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6678 10:05:38.473958 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6679 10:05:38.477215 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6680 10:05:38.480572 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6681 10:05:38.483447 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6682 10:05:38.490045 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6683 10:05:38.493478 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6684 10:05:38.496732 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6685 10:05:38.503285 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6686 10:05:38.506863 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6687 10:05:38.510102 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6688 10:05:38.510183 ==
6689 10:05:38.513022 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 10:05:38.516299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 10:05:38.520071 ==
6692 10:05:38.520166 DQS Delay:
6693 10:05:38.520230 DQS0 = 43, DQS1 = 51
6694 10:05:38.523178 DQM Delay:
6695 10:05:38.523258 DQM0 = 13, DQM1 = 13
6696 10:05:38.526706 DQ Delay:
6697 10:05:38.526787 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6698 10:05:38.529640 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6699 10:05:38.533181 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6700 10:05:38.536796 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6701 10:05:38.536870
6702 10:05:38.536931
6703 10:05:38.539827 ==
6704 10:05:38.543039 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 10:05:38.546135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 10:05:38.546233 ==
6707 10:05:38.546322
6708 10:05:38.546407
6709 10:05:38.549539 TX Vref Scan disable
6710 10:05:38.549607 == TX Byte 0 ==
6711 10:05:38.552747 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6712 10:05:38.559377 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6713 10:05:38.559459 == TX Byte 1 ==
6714 10:05:38.562810 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6715 10:05:38.568955 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6716 10:05:38.569036 ==
6717 10:05:38.572442 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 10:05:38.575943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 10:05:38.576026 ==
6720 10:05:38.576114
6721 10:05:38.576174
6722 10:05:38.579005 TX Vref Scan disable
6723 10:05:38.579086 == TX Byte 0 ==
6724 10:05:38.582214 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 10:05:38.589068 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 10:05:38.589149 == TX Byte 1 ==
6727 10:05:38.592042 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 10:05:38.598676 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 10:05:38.598765
6730 10:05:38.598829 [DATLAT]
6731 10:05:38.601800 Freq=400, CH1 RK0
6732 10:05:38.601881
6733 10:05:38.601945 DATLAT Default: 0xf
6734 10:05:38.605306 0, 0xFFFF, sum = 0
6735 10:05:38.605388 1, 0xFFFF, sum = 0
6736 10:05:38.608566 2, 0xFFFF, sum = 0
6737 10:05:38.608648 3, 0xFFFF, sum = 0
6738 10:05:38.611981 4, 0xFFFF, sum = 0
6739 10:05:38.612100 5, 0xFFFF, sum = 0
6740 10:05:38.615027 6, 0xFFFF, sum = 0
6741 10:05:38.615110 7, 0xFFFF, sum = 0
6742 10:05:38.618248 8, 0xFFFF, sum = 0
6743 10:05:38.618346 9, 0xFFFF, sum = 0
6744 10:05:38.621836 10, 0xFFFF, sum = 0
6745 10:05:38.621919 11, 0xFFFF, sum = 0
6746 10:05:38.625244 12, 0xFFFF, sum = 0
6747 10:05:38.625326 13, 0x0, sum = 1
6748 10:05:38.628579 14, 0x0, sum = 2
6749 10:05:38.628661 15, 0x0, sum = 3
6750 10:05:38.631887 16, 0x0, sum = 4
6751 10:05:38.631985 best_step = 14
6752 10:05:38.632073
6753 10:05:38.632134 ==
6754 10:05:38.634796 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 10:05:38.641572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 10:05:38.641654 ==
6757 10:05:38.641718 RX Vref Scan: 1
6758 10:05:38.641778
6759 10:05:38.644509 RX Vref 0 -> 0, step: 1
6760 10:05:38.644590
6761 10:05:38.647970 RX Delay -343 -> 252, step: 8
6762 10:05:38.648093
6763 10:05:38.651379 Set Vref, RX VrefLevel [Byte0]: 54
6764 10:05:38.654834 [Byte1]: 52
6765 10:05:38.658422
6766 10:05:38.658502 Final RX Vref Byte 0 = 54 to rank0
6767 10:05:38.661365 Final RX Vref Byte 1 = 52 to rank0
6768 10:05:38.664499 Final RX Vref Byte 0 = 54 to rank1
6769 10:05:38.667886 Final RX Vref Byte 1 = 52 to rank1==
6770 10:05:38.671131 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 10:05:38.678004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 10:05:38.678086 ==
6773 10:05:38.678151 DQS Delay:
6774 10:05:38.681550 DQS0 = 44, DQS1 = 52
6775 10:05:38.681631 DQM Delay:
6776 10:05:38.684461 DQM0 = 10, DQM1 = 11
6777 10:05:38.684542 DQ Delay:
6778 10:05:38.687855 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6779 10:05:38.691330 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6780 10:05:38.691426 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6781 10:05:38.697637 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6782 10:05:38.697718
6783 10:05:38.697781
6784 10:05:38.704189 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a91, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6785 10:05:38.707311 CH1 RK0: MR19=C0C, MR18=6A91
6786 10:05:38.713817 CH1_RK0: MR19=0xC0C, MR18=0x6A91, DQSOSC=391, MR23=63, INC=386, DEC=257
6787 10:05:38.713913 ==
6788 10:05:38.717081 Dram Type= 6, Freq= 0, CH_1, rank 1
6789 10:05:38.720164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 10:05:38.720275 ==
6791 10:05:38.724160 [Gating] SW mode calibration
6792 10:05:38.730596 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6793 10:05:38.736886 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6794 10:05:38.739881 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6795 10:05:38.746253 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6796 10:05:38.750530 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6797 10:05:38.753054 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6798 10:05:38.760223 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6799 10:05:38.763336 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6800 10:05:38.766248 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6801 10:05:38.773233 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 10:05:38.776564 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6803 10:05:38.779404 Total UI for P1: 0, mck2ui 16
6804 10:05:38.782934 best dqsien dly found for B0: ( 0, 14, 24)
6805 10:05:38.786208 Total UI for P1: 0, mck2ui 16
6806 10:05:38.789341 best dqsien dly found for B1: ( 0, 14, 24)
6807 10:05:38.792720 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6808 10:05:38.796163 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6809 10:05:38.796254
6810 10:05:38.799181 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6811 10:05:38.802622 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6812 10:05:38.805855 [Gating] SW calibration Done
6813 10:05:38.805951 ==
6814 10:05:38.809364 Dram Type= 6, Freq= 0, CH_1, rank 1
6815 10:05:38.812643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 10:05:38.815745 ==
6817 10:05:38.815825 RX Vref Scan: 0
6818 10:05:38.815911
6819 10:05:38.819147 RX Vref 0 -> 0, step: 1
6820 10:05:38.819228
6821 10:05:38.822667 RX Delay -410 -> 252, step: 16
6822 10:05:38.825563 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6823 10:05:38.828638 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6824 10:05:38.832387 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6825 10:05:38.838780 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6826 10:05:38.842422 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6827 10:05:38.845457 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6828 10:05:38.848913 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6829 10:05:38.855217 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6830 10:05:38.858342 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6831 10:05:38.862112 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6832 10:05:38.868233 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6833 10:05:38.871849 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6834 10:05:38.874954 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6835 10:05:38.878199 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6836 10:05:38.884969 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6837 10:05:38.888022 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6838 10:05:38.888126 ==
6839 10:05:38.891156 Dram Type= 6, Freq= 0, CH_1, rank 1
6840 10:05:38.894449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 10:05:38.894530 ==
6842 10:05:38.897729 DQS Delay:
6843 10:05:38.897810 DQS0 = 43, DQS1 = 51
6844 10:05:38.901088 DQM Delay:
6845 10:05:38.901179 DQM0 = 10, DQM1 = 15
6846 10:05:38.901245 DQ Delay:
6847 10:05:38.904345 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6848 10:05:38.908228 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6849 10:05:38.911569 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6850 10:05:38.914390 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6851 10:05:38.914471
6852 10:05:38.914535
6853 10:05:38.914602 ==
6854 10:05:38.917988 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 10:05:38.924294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 10:05:38.924390 ==
6857 10:05:38.924486
6858 10:05:38.924549
6859 10:05:38.924607 TX Vref Scan disable
6860 10:05:38.927571 == TX Byte 0 ==
6861 10:05:38.931228 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6862 10:05:38.934254 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6863 10:05:38.937422 == TX Byte 1 ==
6864 10:05:38.940931 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6865 10:05:38.943985 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6866 10:05:38.947188 ==
6867 10:05:38.950478 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 10:05:38.953773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 10:05:38.953855 ==
6870 10:05:38.953919
6871 10:05:38.953978
6872 10:05:38.957106 TX Vref Scan disable
6873 10:05:38.957187 == TX Byte 0 ==
6874 10:05:38.960462 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6875 10:05:38.967145 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6876 10:05:38.967226 == TX Byte 1 ==
6877 10:05:38.970850 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6878 10:05:38.977322 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6879 10:05:38.977404
6880 10:05:38.977468 [DATLAT]
6881 10:05:38.977526 Freq=400, CH1 RK1
6882 10:05:38.977584
6883 10:05:38.979918 DATLAT Default: 0xe
6884 10:05:38.983254 0, 0xFFFF, sum = 0
6885 10:05:38.983337 1, 0xFFFF, sum = 0
6886 10:05:38.987514 2, 0xFFFF, sum = 0
6887 10:05:38.987596 3, 0xFFFF, sum = 0
6888 10:05:38.990282 4, 0xFFFF, sum = 0
6889 10:05:38.990364 5, 0xFFFF, sum = 0
6890 10:05:38.993147 6, 0xFFFF, sum = 0
6891 10:05:38.993229 7, 0xFFFF, sum = 0
6892 10:05:38.996746 8, 0xFFFF, sum = 0
6893 10:05:38.996828 9, 0xFFFF, sum = 0
6894 10:05:39.000174 10, 0xFFFF, sum = 0
6895 10:05:39.000257 11, 0xFFFF, sum = 0
6896 10:05:39.003066 12, 0xFFFF, sum = 0
6897 10:05:39.003149 13, 0x0, sum = 1
6898 10:05:39.006638 14, 0x0, sum = 2
6899 10:05:39.006721 15, 0x0, sum = 3
6900 10:05:39.010251 16, 0x0, sum = 4
6901 10:05:39.010333 best_step = 14
6902 10:05:39.010397
6903 10:05:39.010454 ==
6904 10:05:39.013577 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 10:05:39.019847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 10:05:39.019929 ==
6907 10:05:39.019993 RX Vref Scan: 0
6908 10:05:39.020092
6909 10:05:39.023317 RX Vref 0 -> 0, step: 1
6910 10:05:39.023397
6911 10:05:39.026452 RX Delay -343 -> 252, step: 8
6912 10:05:39.032941 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6913 10:05:39.036846 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6914 10:05:39.039768 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6915 10:05:39.042839 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6916 10:05:39.049827 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6917 10:05:39.052704 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6918 10:05:39.056402 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6919 10:05:39.059724 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6920 10:05:39.066201 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6921 10:05:39.069377 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6922 10:05:39.072689 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6923 10:05:39.075949 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6924 10:05:39.082358 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6925 10:05:39.085608 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6926 10:05:39.088954 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6927 10:05:39.095741 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6928 10:05:39.095823 ==
6929 10:05:39.099242 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 10:05:39.102487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 10:05:39.102569 ==
6932 10:05:39.102634 DQS Delay:
6933 10:05:39.105735 DQS0 = 48, DQS1 = 52
6934 10:05:39.105817 DQM Delay:
6935 10:05:39.108710 DQM0 = 12, DQM1 = 10
6936 10:05:39.108792 DQ Delay:
6937 10:05:39.111839 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6938 10:05:39.115263 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6939 10:05:39.118774 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6940 10:05:39.122023 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6941 10:05:39.122104
6942 10:05:39.122169
6943 10:05:39.128704 [DQSOSCAuto] RK1, (LSB)MR18= 0x6da6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
6944 10:05:39.131651 CH1 RK1: MR19=C0C, MR18=6DA6
6945 10:05:39.138433 CH1_RK1: MR19=0xC0C, MR18=0x6DA6, DQSOSC=389, MR23=63, INC=390, DEC=260
6946 10:05:39.141518 [RxdqsGatingPostProcess] freq 400
6947 10:05:39.148434 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6948 10:05:39.151242 best DQS0 dly(2T, 0.5T) = (0, 10)
6949 10:05:39.154908 best DQS1 dly(2T, 0.5T) = (0, 10)
6950 10:05:39.158253 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6951 10:05:39.161023 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6952 10:05:39.164480 best DQS0 dly(2T, 0.5T) = (0, 10)
6953 10:05:39.164562 best DQS1 dly(2T, 0.5T) = (0, 10)
6954 10:05:39.167849 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6955 10:05:39.171034 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6956 10:05:39.174260 Pre-setting of DQS Precalculation
6957 10:05:39.181023 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6958 10:05:39.187757 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6959 10:05:39.194173 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6960 10:05:39.194256
6961 10:05:39.194321
6962 10:05:39.197454 [Calibration Summary] 800 Mbps
6963 10:05:39.200926 CH 0, Rank 0
6964 10:05:39.201008 SW Impedance : PASS
6965 10:05:39.204088 DUTY Scan : NO K
6966 10:05:39.207676 ZQ Calibration : PASS
6967 10:05:39.207758 Jitter Meter : NO K
6968 10:05:39.210986 CBT Training : PASS
6969 10:05:39.214350 Write leveling : PASS
6970 10:05:39.214461 RX DQS gating : PASS
6971 10:05:39.217120 RX DQ/DQS(RDDQC) : PASS
6972 10:05:39.217203 TX DQ/DQS : PASS
6973 10:05:39.220584 RX DATLAT : PASS
6974 10:05:39.223938 RX DQ/DQS(Engine): PASS
6975 10:05:39.224012 TX OE : NO K
6976 10:05:39.227036 All Pass.
6977 10:05:39.227122
6978 10:05:39.227184 CH 0, Rank 1
6979 10:05:39.230162 SW Impedance : PASS
6980 10:05:39.230231 DUTY Scan : NO K
6981 10:05:39.233562 ZQ Calibration : PASS
6982 10:05:39.236994 Jitter Meter : NO K
6983 10:05:39.237080 CBT Training : PASS
6984 10:05:39.240021 Write leveling : NO K
6985 10:05:39.243871 RX DQS gating : PASS
6986 10:05:39.243987 RX DQ/DQS(RDDQC) : PASS
6987 10:05:39.247198 TX DQ/DQS : PASS
6988 10:05:39.250432 RX DATLAT : PASS
6989 10:05:39.250508 RX DQ/DQS(Engine): PASS
6990 10:05:39.253227 TX OE : NO K
6991 10:05:39.253298 All Pass.
6992 10:05:39.253359
6993 10:05:39.256663 CH 1, Rank 0
6994 10:05:39.256747 SW Impedance : PASS
6995 10:05:39.259803 DUTY Scan : NO K
6996 10:05:39.263542 ZQ Calibration : PASS
6997 10:05:39.263626 Jitter Meter : NO K
6998 10:05:39.266942 CBT Training : PASS
6999 10:05:39.270389 Write leveling : PASS
7000 10:05:39.270473 RX DQS gating : PASS
7001 10:05:39.273239 RX DQ/DQS(RDDQC) : PASS
7002 10:05:39.276579 TX DQ/DQS : PASS
7003 10:05:39.276668 RX DATLAT : PASS
7004 10:05:39.279515 RX DQ/DQS(Engine): PASS
7005 10:05:39.283496 TX OE : NO K
7006 10:05:39.283580 All Pass.
7007 10:05:39.283652
7008 10:05:39.283712 CH 1, Rank 1
7009 10:05:39.286366 SW Impedance : PASS
7010 10:05:39.289681 DUTY Scan : NO K
7011 10:05:39.289753 ZQ Calibration : PASS
7012 10:05:39.292684 Jitter Meter : NO K
7013 10:05:39.296302 CBT Training : PASS
7014 10:05:39.296383 Write leveling : NO K
7015 10:05:39.299492 RX DQS gating : PASS
7016 10:05:39.299613 RX DQ/DQS(RDDQC) : PASS
7017 10:05:39.302798 TX DQ/DQS : PASS
7018 10:05:39.306245 RX DATLAT : PASS
7019 10:05:39.306326 RX DQ/DQS(Engine): PASS
7020 10:05:39.309514 TX OE : NO K
7021 10:05:39.309590 All Pass.
7022 10:05:39.309680
7023 10:05:39.312409 DramC Write-DBI off
7024 10:05:39.315776 PER_BANK_REFRESH: Hybrid Mode
7025 10:05:39.315889 TX_TRACKING: ON
7026 10:05:39.326028 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7027 10:05:39.329037 [FAST_K] Save calibration result to emmc
7028 10:05:39.332309 dramc_set_vcore_voltage set vcore to 725000
7029 10:05:39.335704 Read voltage for 1600, 0
7030 10:05:39.335809 Vio18 = 0
7031 10:05:39.339215 Vcore = 725000
7032 10:05:39.339290 Vdram = 0
7033 10:05:39.339353 Vddq = 0
7034 10:05:39.339424 Vmddr = 0
7035 10:05:39.345299 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7036 10:05:39.352220 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7037 10:05:39.352298 MEM_TYPE=3, freq_sel=13
7038 10:05:39.355238 sv_algorithm_assistance_LP4_3733
7039 10:05:39.358873 ============ PULL DRAM RESETB DOWN ============
7040 10:05:39.365461 ========== PULL DRAM RESETB DOWN end =========
7041 10:05:39.368664 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7042 10:05:39.371778 ===================================
7043 10:05:39.375102 LPDDR4 DRAM CONFIGURATION
7044 10:05:39.378395 ===================================
7045 10:05:39.378512 EX_ROW_EN[0] = 0x0
7046 10:05:39.381711 EX_ROW_EN[1] = 0x0
7047 10:05:39.385117 LP4Y_EN = 0x0
7048 10:05:39.385199 WORK_FSP = 0x1
7049 10:05:39.388045 WL = 0x5
7050 10:05:39.388142 RL = 0x5
7051 10:05:39.391822 BL = 0x2
7052 10:05:39.391904 RPST = 0x0
7053 10:05:39.394743 RD_PRE = 0x0
7054 10:05:39.394825 WR_PRE = 0x1
7055 10:05:39.398159 WR_PST = 0x1
7056 10:05:39.398241 DBI_WR = 0x0
7057 10:05:39.401747 DBI_RD = 0x0
7058 10:05:39.401829 OTF = 0x1
7059 10:05:39.405171 ===================================
7060 10:05:39.408181 ===================================
7061 10:05:39.411715 ANA top config
7062 10:05:39.414528 ===================================
7063 10:05:39.414611 DLL_ASYNC_EN = 0
7064 10:05:39.417958 ALL_SLAVE_EN = 0
7065 10:05:39.421415 NEW_RANK_MODE = 1
7066 10:05:39.424677 DLL_IDLE_MODE = 1
7067 10:05:39.428132 LP45_APHY_COMB_EN = 1
7068 10:05:39.428213 TX_ODT_DIS = 0
7069 10:05:39.431481 NEW_8X_MODE = 1
7070 10:05:39.434523 ===================================
7071 10:05:39.437638 ===================================
7072 10:05:39.440953 data_rate = 3200
7073 10:05:39.444256 CKR = 1
7074 10:05:39.447763 DQ_P2S_RATIO = 8
7075 10:05:39.450823 ===================================
7076 10:05:39.454621 CA_P2S_RATIO = 8
7077 10:05:39.454700 DQ_CA_OPEN = 0
7078 10:05:39.457553 DQ_SEMI_OPEN = 0
7079 10:05:39.460845 CA_SEMI_OPEN = 0
7080 10:05:39.464072 CA_FULL_RATE = 0
7081 10:05:39.467723 DQ_CKDIV4_EN = 0
7082 10:05:39.471125 CA_CKDIV4_EN = 0
7083 10:05:39.471214 CA_PREDIV_EN = 0
7084 10:05:39.473905 PH8_DLY = 12
7085 10:05:39.477660 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7086 10:05:39.480915 DQ_AAMCK_DIV = 4
7087 10:05:39.484785 CA_AAMCK_DIV = 4
7088 10:05:39.487467 CA_ADMCK_DIV = 4
7089 10:05:39.491308 DQ_TRACK_CA_EN = 0
7090 10:05:39.491426 CA_PICK = 1600
7091 10:05:39.493944 CA_MCKIO = 1600
7092 10:05:39.497414 MCKIO_SEMI = 0
7093 10:05:39.500259 PLL_FREQ = 3068
7094 10:05:39.503635 DQ_UI_PI_RATIO = 32
7095 10:05:39.507331 CA_UI_PI_RATIO = 0
7096 10:05:39.510603 ===================================
7097 10:05:39.514188 ===================================
7098 10:05:39.516770 memory_type:LPDDR4
7099 10:05:39.517011 GP_NUM : 10
7100 10:05:39.520107 SRAM_EN : 1
7101 10:05:39.520402 MD32_EN : 0
7102 10:05:39.523894 ===================================
7103 10:05:39.527298 [ANA_INIT] >>>>>>>>>>>>>>
7104 10:05:39.530221 <<<<<< [CONFIGURE PHASE]: ANA_TX
7105 10:05:39.533719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7106 10:05:39.536925 ===================================
7107 10:05:39.540229 data_rate = 3200,PCW = 0X7600
7108 10:05:39.543772 ===================================
7109 10:05:39.546542 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7110 10:05:39.553282 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7111 10:05:39.556607 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7112 10:05:39.562928 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7113 10:05:39.566099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7114 10:05:39.569152 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7115 10:05:39.569235 [ANA_INIT] flow start
7116 10:05:39.572440 [ANA_INIT] PLL >>>>>>>>
7117 10:05:39.576319 [ANA_INIT] PLL <<<<<<<<
7118 10:05:39.576395 [ANA_INIT] MIDPI >>>>>>>>
7119 10:05:39.579320 [ANA_INIT] MIDPI <<<<<<<<
7120 10:05:39.582284 [ANA_INIT] DLL >>>>>>>>
7121 10:05:39.585615 [ANA_INIT] DLL <<<<<<<<
7122 10:05:39.585691 [ANA_INIT] flow end
7123 10:05:39.588917 ============ LP4 DIFF to SE enter ============
7124 10:05:39.595917 ============ LP4 DIFF to SE exit ============
7125 10:05:39.595991 [ANA_INIT] <<<<<<<<<<<<<
7126 10:05:39.599024 [Flow] Enable top DCM control >>>>>
7127 10:05:39.602171 [Flow] Enable top DCM control <<<<<
7128 10:05:39.605366 Enable DLL master slave shuffle
7129 10:05:39.612466 ==============================================================
7130 10:05:39.612540 Gating Mode config
7131 10:05:39.618897 ==============================================================
7132 10:05:39.622030 Config description:
7133 10:05:39.632351 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7134 10:05:39.638628 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7135 10:05:39.641954 SELPH_MODE 0: By rank 1: By Phase
7136 10:05:39.648288 ==============================================================
7137 10:05:39.651727 GAT_TRACK_EN = 1
7138 10:05:39.654928 RX_GATING_MODE = 2
7139 10:05:39.658611 RX_GATING_TRACK_MODE = 2
7140 10:05:39.658799 SELPH_MODE = 1
7141 10:05:39.661905 PICG_EARLY_EN = 1
7142 10:05:39.665034 VALID_LAT_VALUE = 1
7143 10:05:39.671384 ==============================================================
7144 10:05:39.675292 Enter into Gating configuration >>>>
7145 10:05:39.678156 Exit from Gating configuration <<<<
7146 10:05:39.682103 Enter into DVFS_PRE_config >>>>>
7147 10:05:39.691121 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7148 10:05:39.694789 Exit from DVFS_PRE_config <<<<<
7149 10:05:39.698239 Enter into PICG configuration >>>>
7150 10:05:39.701224 Exit from PICG configuration <<<<
7151 10:05:39.704819 [RX_INPUT] configuration >>>>>
7152 10:05:39.708096 [RX_INPUT] configuration <<<<<
7153 10:05:39.714420 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7154 10:05:39.717814 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7155 10:05:39.724464 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7156 10:05:39.730967 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7157 10:05:39.737356 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7158 10:05:39.744120 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7159 10:05:39.747678 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7160 10:05:39.750971 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7161 10:05:39.753889 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7162 10:05:39.760435 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7163 10:05:39.764203 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7164 10:05:39.766984 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7165 10:05:39.770074 ===================================
7166 10:05:39.773423 LPDDR4 DRAM CONFIGURATION
7167 10:05:39.776877 ===================================
7168 10:05:39.779994 EX_ROW_EN[0] = 0x0
7169 10:05:39.780102 EX_ROW_EN[1] = 0x0
7170 10:05:39.783286 LP4Y_EN = 0x0
7171 10:05:39.783381 WORK_FSP = 0x1
7172 10:05:39.786752 WL = 0x5
7173 10:05:39.786846 RL = 0x5
7174 10:05:39.789911 BL = 0x2
7175 10:05:39.790056 RPST = 0x0
7176 10:05:39.794303 RD_PRE = 0x0
7177 10:05:39.794459 WR_PRE = 0x1
7178 10:05:39.796751 WR_PST = 0x1
7179 10:05:39.796871 DBI_WR = 0x0
7180 10:05:39.799756 DBI_RD = 0x0
7181 10:05:39.799935 OTF = 0x1
7182 10:05:39.802964 ===================================
7183 10:05:39.809462 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7184 10:05:39.812587 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7185 10:05:39.815971 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7186 10:05:39.819215 ===================================
7187 10:05:39.822745 LPDDR4 DRAM CONFIGURATION
7188 10:05:39.826073 ===================================
7189 10:05:39.829427 EX_ROW_EN[0] = 0x10
7190 10:05:39.829499 EX_ROW_EN[1] = 0x0
7191 10:05:39.832729 LP4Y_EN = 0x0
7192 10:05:39.832799 WORK_FSP = 0x1
7193 10:05:39.835984 WL = 0x5
7194 10:05:39.836099 RL = 0x5
7195 10:05:39.839329 BL = 0x2
7196 10:05:39.839398 RPST = 0x0
7197 10:05:39.842690 RD_PRE = 0x0
7198 10:05:39.842788 WR_PRE = 0x1
7199 10:05:39.846105 WR_PST = 0x1
7200 10:05:39.846205 DBI_WR = 0x0
7201 10:05:39.848800 DBI_RD = 0x0
7202 10:05:39.848870 OTF = 0x1
7203 10:05:39.852564 ===================================
7204 10:05:39.859142 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7205 10:05:39.859240 ==
7206 10:05:39.862151 Dram Type= 6, Freq= 0, CH_0, rank 0
7207 10:05:39.868810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7208 10:05:39.868882 ==
7209 10:05:39.868943 [Duty_Offset_Calibration]
7210 10:05:39.871913 B0:2 B1:0 CA:4
7211 10:05:39.872010
7212 10:05:39.875184 [DutyScan_Calibration_Flow] k_type=0
7213 10:05:39.883796
7214 10:05:39.883890 ==CLK 0==
7215 10:05:39.887507 Final CLK duty delay cell = -4
7216 10:05:39.890941 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7217 10:05:39.894213 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7218 10:05:39.897565 [-4] AVG Duty = 4922%(X100)
7219 10:05:39.897634
7220 10:05:39.900405 CH0 CLK Duty spec in!! Max-Min= 218%
7221 10:05:39.904331 [DutyScan_Calibration_Flow] ====Done====
7222 10:05:39.904409
7223 10:05:39.907457 [DutyScan_Calibration_Flow] k_type=1
7224 10:05:39.923744
7225 10:05:39.923834 ==DQS 0 ==
7226 10:05:39.926561 Final DQS duty delay cell = -4
7227 10:05:39.930021 [-4] MAX Duty = 4938%(X100), DQS PI = 48
7228 10:05:39.933435 [-4] MIN Duty = 4782%(X100), DQS PI = 10
7229 10:05:39.936827 [-4] AVG Duty = 4860%(X100)
7230 10:05:39.936932
7231 10:05:39.937014 ==DQS 1 ==
7232 10:05:39.939724 Final DQS duty delay cell = 0
7233 10:05:39.943340 [0] MAX Duty = 5187%(X100), DQS PI = 2
7234 10:05:39.946459 [0] MIN Duty = 4969%(X100), DQS PI = 10
7235 10:05:39.950215 [0] AVG Duty = 5078%(X100)
7236 10:05:39.950384
7237 10:05:39.953001 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7238 10:05:39.953123
7239 10:05:39.956277 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7240 10:05:39.959838 [DutyScan_Calibration_Flow] ====Done====
7241 10:05:39.960060
7242 10:05:39.962895 [DutyScan_Calibration_Flow] k_type=3
7243 10:05:39.980879
7244 10:05:39.980959 ==DQM 0 ==
7245 10:05:39.984346 Final DQM duty delay cell = 0
7246 10:05:39.987925 [0] MAX Duty = 5124%(X100), DQS PI = 22
7247 10:05:39.990720 [0] MIN Duty = 4875%(X100), DQS PI = 54
7248 10:05:39.994074 [0] AVG Duty = 4999%(X100)
7249 10:05:39.994169
7250 10:05:39.994256 ==DQM 1 ==
7251 10:05:39.997700 Final DQM duty delay cell = 0
7252 10:05:40.000333 [0] MAX Duty = 4969%(X100), DQS PI = 0
7253 10:05:40.003696 [0] MIN Duty = 4844%(X100), DQS PI = 16
7254 10:05:40.007870 [0] AVG Duty = 4906%(X100)
7255 10:05:40.007963
7256 10:05:40.010436 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7257 10:05:40.010511
7258 10:05:40.013663 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7259 10:05:40.017066 [DutyScan_Calibration_Flow] ====Done====
7260 10:05:40.017137
7261 10:05:40.019965 [DutyScan_Calibration_Flow] k_type=2
7262 10:05:40.037813
7263 10:05:40.037897 ==DQ 0 ==
7264 10:05:40.041423 Final DQ duty delay cell = 0
7265 10:05:40.044466 [0] MAX Duty = 5156%(X100), DQS PI = 22
7266 10:05:40.047946 [0] MIN Duty = 4938%(X100), DQS PI = 12
7267 10:05:40.051221 [0] AVG Duty = 5047%(X100)
7268 10:05:40.051303
7269 10:05:40.051367 ==DQ 1 ==
7270 10:05:40.054118 Final DQ duty delay cell = 0
7271 10:05:40.058002 [0] MAX Duty = 5187%(X100), DQS PI = 2
7272 10:05:40.060683 [0] MIN Duty = 4907%(X100), DQS PI = 32
7273 10:05:40.064226 [0] AVG Duty = 5047%(X100)
7274 10:05:40.064308
7275 10:05:40.067719 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7276 10:05:40.067820
7277 10:05:40.070687 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7278 10:05:40.074380 [DutyScan_Calibration_Flow] ====Done====
7279 10:05:40.074462 ==
7280 10:05:40.077242 Dram Type= 6, Freq= 0, CH_1, rank 0
7281 10:05:40.080583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7282 10:05:40.080666 ==
7283 10:05:40.083844 [Duty_Offset_Calibration]
7284 10:05:40.083925 B0:0 B1:-1 CA:3
7285 10:05:40.083990
7286 10:05:40.087533 [DutyScan_Calibration_Flow] k_type=0
7287 10:05:40.097616
7288 10:05:40.097697 ==CLK 0==
7289 10:05:40.100516 Final CLK duty delay cell = -4
7290 10:05:40.103862 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7291 10:05:40.107060 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7292 10:05:40.110632 [-4] AVG Duty = 4922%(X100)
7293 10:05:40.110712
7294 10:05:40.113838 CH1 CLK Duty spec in!! Max-Min= 156%
7295 10:05:40.117002 [DutyScan_Calibration_Flow] ====Done====
7296 10:05:40.117082
7297 10:05:40.120848 [DutyScan_Calibration_Flow] k_type=1
7298 10:05:40.136490
7299 10:05:40.136572 ==DQS 0 ==
7300 10:05:40.139868 Final DQS duty delay cell = 0
7301 10:05:40.143262 [0] MAX Duty = 5250%(X100), DQS PI = 28
7302 10:05:40.146322 [0] MIN Duty = 4907%(X100), DQS PI = 60
7303 10:05:40.149722 [0] AVG Duty = 5078%(X100)
7304 10:05:40.149803
7305 10:05:40.149865 ==DQS 1 ==
7306 10:05:40.153332 Final DQS duty delay cell = -4
7307 10:05:40.156159 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7308 10:05:40.159587 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7309 10:05:40.163022 [-4] AVG Duty = 4922%(X100)
7310 10:05:40.163103
7311 10:05:40.166153 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7312 10:05:40.166233
7313 10:05:40.169597 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7314 10:05:40.172591 [DutyScan_Calibration_Flow] ====Done====
7315 10:05:40.172671
7316 10:05:40.176019 [DutyScan_Calibration_Flow] k_type=3
7317 10:05:40.193727
7318 10:05:40.193806 ==DQM 0 ==
7319 10:05:40.197060 Final DQM duty delay cell = 0
7320 10:05:40.200852 [0] MAX Duty = 5062%(X100), DQS PI = 30
7321 10:05:40.203965 [0] MIN Duty = 4782%(X100), DQS PI = 38
7322 10:05:40.207356 [0] AVG Duty = 4922%(X100)
7323 10:05:40.207436
7324 10:05:40.207499 ==DQM 1 ==
7325 10:05:40.210142 Final DQM duty delay cell = 0
7326 10:05:40.213394 [0] MAX Duty = 5000%(X100), DQS PI = 30
7327 10:05:40.216864 [0] MIN Duty = 4813%(X100), DQS PI = 0
7328 10:05:40.220380 [0] AVG Duty = 4906%(X100)
7329 10:05:40.220459
7330 10:05:40.223329 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7331 10:05:40.223408
7332 10:05:40.226675 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7333 10:05:40.230137 [DutyScan_Calibration_Flow] ====Done====
7334 10:05:40.230217
7335 10:05:40.233502 [DutyScan_Calibration_Flow] k_type=2
7336 10:05:40.249800
7337 10:05:40.249907 ==DQ 0 ==
7338 10:05:40.253112 Final DQ duty delay cell = -4
7339 10:05:40.256636 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7340 10:05:40.259680 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7341 10:05:40.262849 [-4] AVG Duty = 4891%(X100)
7342 10:05:40.262950
7343 10:05:40.263039 ==DQ 1 ==
7344 10:05:40.266546 Final DQ duty delay cell = 0
7345 10:05:40.269636 [0] MAX Duty = 5031%(X100), DQS PI = 30
7346 10:05:40.272833 [0] MIN Duty = 4875%(X100), DQS PI = 0
7347 10:05:40.276097 [0] AVG Duty = 4953%(X100)
7348 10:05:40.276172
7349 10:05:40.279490 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7350 10:05:40.279587
7351 10:05:40.282844 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7352 10:05:40.285836 [DutyScan_Calibration_Flow] ====Done====
7353 10:05:40.289035 nWR fixed to 30
7354 10:05:40.292502 [ModeRegInit_LP4] CH0 RK0
7355 10:05:40.292571 [ModeRegInit_LP4] CH0 RK1
7356 10:05:40.295951 [ModeRegInit_LP4] CH1 RK0
7357 10:05:40.298878 [ModeRegInit_LP4] CH1 RK1
7358 10:05:40.298975 match AC timing 5
7359 10:05:40.305519 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7360 10:05:40.308841 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7361 10:05:40.312289 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7362 10:05:40.319339 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7363 10:05:40.322060 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7364 10:05:40.325466 [MiockJmeterHQA]
7365 10:05:40.325545
7366 10:05:40.328634 [DramcMiockJmeter] u1RxGatingPI = 0
7367 10:05:40.328712 0 : 4252, 4027
7368 10:05:40.328776 4 : 4252, 4027
7369 10:05:40.332384 8 : 4253, 4027
7370 10:05:40.332463 12 : 4253, 4026
7371 10:05:40.335117 16 : 4255, 4029
7372 10:05:40.335222 20 : 4252, 4027
7373 10:05:40.338376 24 : 4253, 4027
7374 10:05:40.338446 28 : 4363, 4137
7375 10:05:40.341921 32 : 4252, 4027
7376 10:05:40.341993 36 : 4253, 4026
7377 10:05:40.342052 40 : 4252, 4027
7378 10:05:40.345022 44 : 4255, 4029
7379 10:05:40.345117 48 : 4253, 4026
7380 10:05:40.348474 52 : 4253, 4026
7381 10:05:40.348552 56 : 4366, 4140
7382 10:05:40.351888 60 : 4250, 4027
7383 10:05:40.351984 64 : 4252, 4029
7384 10:05:40.354947 68 : 4250, 4026
7385 10:05:40.355021 72 : 4361, 4138
7386 10:05:40.355082 76 : 4250, 4027
7387 10:05:40.358074 80 : 4250, 4026
7388 10:05:40.358148 84 : 4252, 4030
7389 10:05:40.361344 88 : 4250, 4027
7390 10:05:40.361477 92 : 4253, 4029
7391 10:05:40.364733 96 : 4250, 3017
7392 10:05:40.364818 100 : 4250, 0
7393 10:05:40.364904 104 : 4250, 0
7394 10:05:40.367967 108 : 4363, 0
7395 10:05:40.368101 112 : 4253, 0
7396 10:05:40.371378 116 : 4250, 0
7397 10:05:40.371463 120 : 4250, 0
7398 10:05:40.371549 124 : 4363, 0
7399 10:05:40.374640 128 : 4250, 0
7400 10:05:40.374739 132 : 4361, 0
7401 10:05:40.378027 136 : 4255, 0
7402 10:05:40.378151 140 : 4250, 0
7403 10:05:40.378256 144 : 4250, 0
7404 10:05:40.381393 148 : 4255, 0
7405 10:05:40.381478 152 : 4361, 0
7406 10:05:40.384864 156 : 4250, 0
7407 10:05:40.384950 160 : 4250, 0
7408 10:05:40.385072 164 : 4250, 0
7409 10:05:40.388294 168 : 4363, 0
7410 10:05:40.388373 172 : 4249, 0
7411 10:05:40.391016 176 : 4361, 0
7412 10:05:40.391117 180 : 4360, 0
7413 10:05:40.391198 184 : 4248, 0
7414 10:05:40.394411 188 : 4360, 0
7415 10:05:40.394511 192 : 4250, 0
7416 10:05:40.397333 196 : 4250, 0
7417 10:05:40.397434 200 : 4361, 0
7418 10:05:40.397533 204 : 4250, 0
7419 10:05:40.400909 208 : 4250, 0
7420 10:05:40.401009 212 : 4249, 0
7421 10:05:40.401108 216 : 4250, 0
7422 10:05:40.404848 220 : 4250, 711
7423 10:05:40.404953 224 : 4363, 4132
7424 10:05:40.407720 228 : 4361, 4138
7425 10:05:40.407824 232 : 4250, 4027
7426 10:05:40.410459 236 : 4250, 4026
7427 10:05:40.410558 240 : 4250, 4026
7428 10:05:40.414274 244 : 4360, 4138
7429 10:05:40.414413 248 : 4250, 4027
7430 10:05:40.417681 252 : 4363, 4140
7431 10:05:40.417759 256 : 4250, 4026
7432 10:05:40.420653 260 : 4250, 4027
7433 10:05:40.420728 264 : 4249, 4027
7434 10:05:40.423874 268 : 4250, 4027
7435 10:05:40.423950 272 : 4255, 4029
7436 10:05:40.427679 276 : 4361, 4137
7437 10:05:40.427760 280 : 4250, 4027
7438 10:05:40.427825 284 : 4250, 4027
7439 10:05:40.430511 288 : 4250, 4027
7440 10:05:40.430586 292 : 4250, 4026
7441 10:05:40.433786 296 : 4363, 4138
7442 10:05:40.433876 300 : 4250, 4027
7443 10:05:40.437461 304 : 4363, 4137
7444 10:05:40.437544 308 : 4250, 4026
7445 10:05:40.440331 312 : 4250, 4027
7446 10:05:40.440456 316 : 4250, 4027
7447 10:05:40.443442 320 : 4252, 4030
7448 10:05:40.443559 324 : 4250, 4026
7449 10:05:40.447071 328 : 4363, 4137
7450 10:05:40.447177 332 : 4250, 3942
7451 10:05:40.450173 336 : 4250, 2070
7452 10:05:40.450260
7453 10:05:40.450328 MIOCK jitter meter ch=0
7454 10:05:40.450391
7455 10:05:40.453632 1T = (336-100) = 236 dly cells
7456 10:05:40.459782 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7457 10:05:40.459862 ==
7458 10:05:40.463518 Dram Type= 6, Freq= 0, CH_0, rank 0
7459 10:05:40.466788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7460 10:05:40.466864 ==
7461 10:05:40.473132 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7462 10:05:40.476427 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7463 10:05:40.483462 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7464 10:05:40.486165 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7465 10:05:40.496714 [CA 0] Center 44 (14~74) winsize 61
7466 10:05:40.499876 [CA 1] Center 43 (13~74) winsize 62
7467 10:05:40.502897 [CA 2] Center 39 (10~68) winsize 59
7468 10:05:40.506537 [CA 3] Center 38 (9~68) winsize 60
7469 10:05:40.509590 [CA 4] Center 36 (7~66) winsize 60
7470 10:05:40.512652 [CA 5] Center 36 (6~66) winsize 61
7471 10:05:40.512727
7472 10:05:40.516460 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7473 10:05:40.516572
7474 10:05:40.523087 [CATrainingPosCal] consider 1 rank data
7475 10:05:40.523165 u2DelayCellTimex100 = 275/100 ps
7476 10:05:40.529178 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7477 10:05:40.533086 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7478 10:05:40.536076 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7479 10:05:40.539246 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7480 10:05:40.542649 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7481 10:05:40.545620 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7482 10:05:40.545703
7483 10:05:40.549269 CA PerBit enable=1, Macro0, CA PI delay=36
7484 10:05:40.549346
7485 10:05:40.552340 [CBTSetCACLKResult] CA Dly = 36
7486 10:05:40.555734 CS Dly: 11 (0~42)
7487 10:05:40.559409 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7488 10:05:40.562332 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7489 10:05:40.565625 ==
7490 10:05:40.565708 Dram Type= 6, Freq= 0, CH_0, rank 1
7491 10:05:40.571927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7492 10:05:40.572025 ==
7493 10:05:40.575170 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7494 10:05:40.582190 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7495 10:05:40.585384 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7496 10:05:40.591554 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7497 10:05:40.599932 [CA 0] Center 44 (13~75) winsize 63
7498 10:05:40.603275 [CA 1] Center 43 (13~74) winsize 62
7499 10:05:40.607149 [CA 2] Center 38 (9~68) winsize 60
7500 10:05:40.610326 [CA 3] Center 38 (9~68) winsize 60
7501 10:05:40.613678 [CA 4] Center 37 (7~67) winsize 61
7502 10:05:40.617005 [CA 5] Center 36 (7~66) winsize 60
7503 10:05:40.617101
7504 10:05:40.620222 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7505 10:05:40.620302
7506 10:05:40.623150 [CATrainingPosCal] consider 2 rank data
7507 10:05:40.626543 u2DelayCellTimex100 = 275/100 ps
7508 10:05:40.629940 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7509 10:05:40.636696 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7510 10:05:40.639911 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7511 10:05:40.642985 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7512 10:05:40.647470 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7513 10:05:40.649549 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7514 10:05:40.649655
7515 10:05:40.652949 CA PerBit enable=1, Macro0, CA PI delay=36
7516 10:05:40.653030
7517 10:05:40.655999 [CBTSetCACLKResult] CA Dly = 36
7518 10:05:40.659576 CS Dly: 12 (0~44)
7519 10:05:40.662516 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7520 10:05:40.666434 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7521 10:05:40.666514
7522 10:05:40.669545 ----->DramcWriteLeveling(PI) begin...
7523 10:05:40.669627 ==
7524 10:05:40.672552 Dram Type= 6, Freq= 0, CH_0, rank 0
7525 10:05:40.679376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7526 10:05:40.679459 ==
7527 10:05:40.682303 Write leveling (Byte 0): 36 => 36
7528 10:05:40.685834 Write leveling (Byte 1): 26 => 26
7529 10:05:40.688853 DramcWriteLeveling(PI) end<-----
7530 10:05:40.688934
7531 10:05:40.688997 ==
7532 10:05:40.692405 Dram Type= 6, Freq= 0, CH_0, rank 0
7533 10:05:40.695799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7534 10:05:40.695880 ==
7535 10:05:40.699343 [Gating] SW mode calibration
7536 10:05:40.705417 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7537 10:05:40.712368 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7538 10:05:40.715473 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7539 10:05:40.718748 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7540 10:05:40.725497 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7541 10:05:40.728952 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7542 10:05:40.731971 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7543 10:05:40.738250 1 4 20 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
7544 10:05:40.741601 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7545 10:05:40.744855 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7546 10:05:40.751278 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7547 10:05:40.754639 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7548 10:05:40.757752 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7549 10:05:40.764454 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
7550 10:05:40.767862 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7551 10:05:40.771065 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
7552 10:05:40.777745 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7553 10:05:40.781190 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 10:05:40.784496 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 10:05:40.790826 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 10:05:40.794456 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7557 10:05:40.797353 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7558 10:05:40.803880 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7559 10:05:40.807726 1 6 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
7560 10:05:40.811115 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7561 10:05:40.818099 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7562 10:05:40.820696 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 10:05:40.824060 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 10:05:40.830795 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7565 10:05:40.833988 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7566 10:05:40.837246 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7567 10:05:40.843478 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7568 10:05:40.846864 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7569 10:05:40.850257 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 10:05:40.857362 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 10:05:40.860153 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 10:05:40.863261 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 10:05:40.870013 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 10:05:40.873086 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 10:05:40.876283 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 10:05:40.882873 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 10:05:40.886282 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 10:05:40.889965 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 10:05:40.896249 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 10:05:40.899765 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7581 10:05:40.903062 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7582 10:05:40.906244 Total UI for P1: 0, mck2ui 16
7583 10:05:40.909838 best dqsien dly found for B0: ( 1, 9, 8)
7584 10:05:40.916057 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7585 10:05:40.919372 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7586 10:05:40.922652 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7587 10:05:40.928994 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 10:05:40.929075 Total UI for P1: 0, mck2ui 16
7589 10:05:40.935674 best dqsien dly found for B1: ( 1, 9, 24)
7590 10:05:40.939020 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7591 10:05:40.942436 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7592 10:05:40.942520
7593 10:05:40.945290 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7594 10:05:40.948831 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7595 10:05:40.952151 [Gating] SW calibration Done
7596 10:05:40.952231 ==
7597 10:05:40.955637 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 10:05:40.958507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 10:05:40.958587 ==
7600 10:05:40.962011 RX Vref Scan: 0
7601 10:05:40.962091
7602 10:05:40.962155 RX Vref 0 -> 0, step: 1
7603 10:05:40.965373
7604 10:05:40.965452 RX Delay 0 -> 252, step: 8
7605 10:05:40.968793 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7606 10:05:40.975488 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7607 10:05:40.978390 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7608 10:05:40.981894 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7609 10:05:40.985346 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7610 10:05:40.991829 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7611 10:05:40.994916 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7612 10:05:40.998178 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7613 10:05:41.001971 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7614 10:05:41.004615 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7615 10:05:41.011415 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7616 10:05:41.015466 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7617 10:05:41.017918 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7618 10:05:41.021184 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7619 10:05:41.024619 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7620 10:05:41.031033 iDelay=192, Bit 15, Center 131 (80 ~ 183) 104
7621 10:05:41.031113 ==
7622 10:05:41.034576 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 10:05:41.037760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 10:05:41.037855 ==
7625 10:05:41.037949 DQS Delay:
7626 10:05:41.040992 DQS0 = 0, DQS1 = 0
7627 10:05:41.041072 DQM Delay:
7628 10:05:41.043993 DQM0 = 131, DQM1 = 126
7629 10:05:41.044113 DQ Delay:
7630 10:05:41.047656 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7631 10:05:41.051101 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7632 10:05:41.054108 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
7633 10:05:41.060626 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =131
7634 10:05:41.060706
7635 10:05:41.060769
7636 10:05:41.060827 ==
7637 10:05:41.064009 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 10:05:41.067646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 10:05:41.067727 ==
7640 10:05:41.067791
7641 10:05:41.067850
7642 10:05:41.070363 TX Vref Scan disable
7643 10:05:41.070443 == TX Byte 0 ==
7644 10:05:41.077166 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7645 10:05:41.080428 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7646 10:05:41.080508 == TX Byte 1 ==
7647 10:05:41.086743 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7648 10:05:41.090898 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7649 10:05:41.090979 ==
7650 10:05:41.093560 Dram Type= 6, Freq= 0, CH_0, rank 0
7651 10:05:41.096799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7652 10:05:41.100060 ==
7653 10:05:41.112490
7654 10:05:41.115398 TX Vref early break, caculate TX vref
7655 10:05:41.118852 TX Vref=16, minBit 1, minWin=20, winSum=356
7656 10:05:41.122203 TX Vref=18, minBit 7, minWin=21, winSum=372
7657 10:05:41.125375 TX Vref=20, minBit 1, minWin=21, winSum=379
7658 10:05:41.128766 TX Vref=22, minBit 0, minWin=23, winSum=391
7659 10:05:41.131985 TX Vref=24, minBit 1, minWin=24, winSum=402
7660 10:05:41.138385 TX Vref=26, minBit 1, minWin=24, winSum=408
7661 10:05:41.141722 TX Vref=28, minBit 0, minWin=24, winSum=413
7662 10:05:41.144826 TX Vref=30, minBit 2, minWin=23, winSum=403
7663 10:05:41.148150 TX Vref=32, minBit 7, minWin=22, winSum=396
7664 10:05:41.151343 TX Vref=34, minBit 0, minWin=22, winSum=384
7665 10:05:41.158399 [TxChooseVref] Worse bit 0, Min win 24, Win sum 413, Final Vref 28
7666 10:05:41.158491
7667 10:05:41.161367 Final TX Range 0 Vref 28
7668 10:05:41.161448
7669 10:05:41.161511 ==
7670 10:05:41.164787 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 10:05:41.168181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 10:05:41.168267 ==
7673 10:05:41.168331
7674 10:05:41.168390
7675 10:05:41.171583 TX Vref Scan disable
7676 10:05:41.177751 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7677 10:05:41.177833 == TX Byte 0 ==
7678 10:05:41.181342 u2DelayCellOfst[0]=14 cells (4 PI)
7679 10:05:41.184523 u2DelayCellOfst[1]=17 cells (5 PI)
7680 10:05:41.188052 u2DelayCellOfst[2]=10 cells (3 PI)
7681 10:05:41.191019 u2DelayCellOfst[3]=14 cells (4 PI)
7682 10:05:41.194425 u2DelayCellOfst[4]=10 cells (3 PI)
7683 10:05:41.198290 u2DelayCellOfst[5]=0 cells (0 PI)
7684 10:05:41.201553 u2DelayCellOfst[6]=21 cells (6 PI)
7685 10:05:41.204564 u2DelayCellOfst[7]=17 cells (5 PI)
7686 10:05:41.207701 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7687 10:05:41.211061 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7688 10:05:41.214150 == TX Byte 1 ==
7689 10:05:41.217194 u2DelayCellOfst[8]=0 cells (0 PI)
7690 10:05:41.221017 u2DelayCellOfst[9]=0 cells (0 PI)
7691 10:05:41.224266 u2DelayCellOfst[10]=3 cells (1 PI)
7692 10:05:41.227098 u2DelayCellOfst[11]=0 cells (0 PI)
7693 10:05:41.230528 u2DelayCellOfst[12]=10 cells (3 PI)
7694 10:05:41.233928 u2DelayCellOfst[13]=10 cells (3 PI)
7695 10:05:41.237060 u2DelayCellOfst[14]=14 cells (4 PI)
7696 10:05:41.237135 u2DelayCellOfst[15]=10 cells (3 PI)
7697 10:05:41.243432 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7698 10:05:41.247081 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7699 10:05:41.250635 DramC Write-DBI on
7700 10:05:41.250706 ==
7701 10:05:41.253615 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 10:05:41.256811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 10:05:41.256881 ==
7704 10:05:41.256947
7705 10:05:41.257004
7706 10:05:41.260265 TX Vref Scan disable
7707 10:05:41.260330 == TX Byte 0 ==
7708 10:05:41.266602 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7709 10:05:41.266673 == TX Byte 1 ==
7710 10:05:41.270127 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7711 10:05:41.273121 DramC Write-DBI off
7712 10:05:41.273207
7713 10:05:41.273266 [DATLAT]
7714 10:05:41.276919 Freq=1600, CH0 RK0
7715 10:05:41.276989
7716 10:05:41.277045 DATLAT Default: 0xf
7717 10:05:41.280183 0, 0xFFFF, sum = 0
7718 10:05:41.283022 1, 0xFFFF, sum = 0
7719 10:05:41.283089 2, 0xFFFF, sum = 0
7720 10:05:41.286532 3, 0xFFFF, sum = 0
7721 10:05:41.286599 4, 0xFFFF, sum = 0
7722 10:05:41.289626 5, 0xFFFF, sum = 0
7723 10:05:41.289693 6, 0xFFFF, sum = 0
7724 10:05:41.293264 7, 0xFFFF, sum = 0
7725 10:05:41.293330 8, 0xFFFF, sum = 0
7726 10:05:41.296193 9, 0xFFFF, sum = 0
7727 10:05:41.296259 10, 0xFFFF, sum = 0
7728 10:05:41.299731 11, 0xFFFF, sum = 0
7729 10:05:41.299806 12, 0xFFFF, sum = 0
7730 10:05:41.302890 13, 0xFFFF, sum = 0
7731 10:05:41.302959 14, 0x0, sum = 1
7732 10:05:41.305938 15, 0x0, sum = 2
7733 10:05:41.306026 16, 0x0, sum = 3
7734 10:05:41.309182 17, 0x0, sum = 4
7735 10:05:41.309266 best_step = 15
7736 10:05:41.309329
7737 10:05:41.309388 ==
7738 10:05:41.312626 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 10:05:41.319125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 10:05:41.319203 ==
7741 10:05:41.319266 RX Vref Scan: 1
7742 10:05:41.319341
7743 10:05:41.322951 Set Vref Range= 24 -> 127
7744 10:05:41.323034
7745 10:05:41.325818 RX Vref 24 -> 127, step: 1
7746 10:05:41.325904
7747 10:05:41.329273 RX Delay 19 -> 252, step: 4
7748 10:05:41.329357
7749 10:05:41.332148 Set Vref, RX VrefLevel [Byte0]: 24
7750 10:05:41.335493 [Byte1]: 24
7751 10:05:41.335580
7752 10:05:41.339315 Set Vref, RX VrefLevel [Byte0]: 25
7753 10:05:41.342586 [Byte1]: 25
7754 10:05:41.342707
7755 10:05:41.345851 Set Vref, RX VrefLevel [Byte0]: 26
7756 10:05:41.349174 [Byte1]: 26
7757 10:05:41.349266
7758 10:05:41.352167 Set Vref, RX VrefLevel [Byte0]: 27
7759 10:05:41.355682 [Byte1]: 27
7760 10:05:41.359474
7761 10:05:41.359550 Set Vref, RX VrefLevel [Byte0]: 28
7762 10:05:41.362727 [Byte1]: 28
7763 10:05:41.366830
7764 10:05:41.366906 Set Vref, RX VrefLevel [Byte0]: 29
7765 10:05:41.370777 [Byte1]: 29
7766 10:05:41.374955
7767 10:05:41.375031 Set Vref, RX VrefLevel [Byte0]: 30
7768 10:05:41.377840 [Byte1]: 30
7769 10:05:41.382682
7770 10:05:41.382757 Set Vref, RX VrefLevel [Byte0]: 31
7771 10:05:41.385451 [Byte1]: 31
7772 10:05:41.389584
7773 10:05:41.389657 Set Vref, RX VrefLevel [Byte0]: 32
7774 10:05:41.393484 [Byte1]: 32
7775 10:05:41.397551
7776 10:05:41.397663 Set Vref, RX VrefLevel [Byte0]: 33
7777 10:05:41.400593 [Byte1]: 33
7778 10:05:41.405115
7779 10:05:41.405215 Set Vref, RX VrefLevel [Byte0]: 34
7780 10:05:41.408356 [Byte1]: 34
7781 10:05:41.412521
7782 10:05:41.412605 Set Vref, RX VrefLevel [Byte0]: 35
7783 10:05:41.415839 [Byte1]: 35
7784 10:05:41.420249
7785 10:05:41.420351 Set Vref, RX VrefLevel [Byte0]: 36
7786 10:05:41.423569 [Byte1]: 36
7787 10:05:41.427720
7788 10:05:41.427839 Set Vref, RX VrefLevel [Byte0]: 37
7789 10:05:41.430897 [Byte1]: 37
7790 10:05:41.435304
7791 10:05:41.435379 Set Vref, RX VrefLevel [Byte0]: 38
7792 10:05:41.438886 [Byte1]: 38
7793 10:05:41.442678
7794 10:05:41.442751 Set Vref, RX VrefLevel [Byte0]: 39
7795 10:05:41.446007 [Byte1]: 39
7796 10:05:41.450554
7797 10:05:41.450630 Set Vref, RX VrefLevel [Byte0]: 40
7798 10:05:41.454028 [Byte1]: 40
7799 10:05:41.458543
7800 10:05:41.458631 Set Vref, RX VrefLevel [Byte0]: 41
7801 10:05:41.461729 [Byte1]: 41
7802 10:05:41.465569
7803 10:05:41.465647 Set Vref, RX VrefLevel [Byte0]: 42
7804 10:05:41.469199 [Byte1]: 42
7805 10:05:41.473065
7806 10:05:41.473134 Set Vref, RX VrefLevel [Byte0]: 43
7807 10:05:41.476336 [Byte1]: 43
7808 10:05:41.480950
7809 10:05:41.481023 Set Vref, RX VrefLevel [Byte0]: 44
7810 10:05:41.483977 [Byte1]: 44
7811 10:05:41.488346
7812 10:05:41.488418 Set Vref, RX VrefLevel [Byte0]: 45
7813 10:05:41.491776 [Byte1]: 45
7814 10:05:41.495851
7815 10:05:41.495938 Set Vref, RX VrefLevel [Byte0]: 46
7816 10:05:41.499286 [Byte1]: 46
7817 10:05:41.503348
7818 10:05:41.503420 Set Vref, RX VrefLevel [Byte0]: 47
7819 10:05:41.506834 [Byte1]: 47
7820 10:05:41.511173
7821 10:05:41.511244 Set Vref, RX VrefLevel [Byte0]: 48
7822 10:05:41.514334 [Byte1]: 48
7823 10:05:41.518835
7824 10:05:41.518914 Set Vref, RX VrefLevel [Byte0]: 49
7825 10:05:41.521785 [Byte1]: 49
7826 10:05:41.526093
7827 10:05:41.526185 Set Vref, RX VrefLevel [Byte0]: 50
7828 10:05:41.529340 [Byte1]: 50
7829 10:05:41.534055
7830 10:05:41.534152 Set Vref, RX VrefLevel [Byte0]: 51
7831 10:05:41.536901 [Byte1]: 51
7832 10:05:41.541135
7833 10:05:41.541247 Set Vref, RX VrefLevel [Byte0]: 52
7834 10:05:41.544606 [Byte1]: 52
7835 10:05:41.548820
7836 10:05:41.548924 Set Vref, RX VrefLevel [Byte0]: 53
7837 10:05:41.551993 [Byte1]: 53
7838 10:05:41.556488
7839 10:05:41.556587 Set Vref, RX VrefLevel [Byte0]: 54
7840 10:05:41.559920 [Byte1]: 54
7841 10:05:41.564391
7842 10:05:41.564473 Set Vref, RX VrefLevel [Byte0]: 55
7843 10:05:41.567142 [Byte1]: 55
7844 10:05:41.571414
7845 10:05:41.571497 Set Vref, RX VrefLevel [Byte0]: 56
7846 10:05:41.574661 [Byte1]: 56
7847 10:05:41.579255
7848 10:05:41.579337 Set Vref, RX VrefLevel [Byte0]: 57
7849 10:05:41.582782 [Byte1]: 57
7850 10:05:41.586739
7851 10:05:41.586821 Set Vref, RX VrefLevel [Byte0]: 58
7852 10:05:41.590122 [Byte1]: 58
7853 10:05:41.594597
7854 10:05:41.594679 Set Vref, RX VrefLevel [Byte0]: 59
7855 10:05:41.597878 [Byte1]: 59
7856 10:05:41.601633
7857 10:05:41.601715 Set Vref, RX VrefLevel [Byte0]: 60
7858 10:05:41.605293 [Byte1]: 60
7859 10:05:41.609382
7860 10:05:41.609464 Set Vref, RX VrefLevel [Byte0]: 61
7861 10:05:41.612831 [Byte1]: 61
7862 10:05:41.617118
7863 10:05:41.617205 Set Vref, RX VrefLevel [Byte0]: 62
7864 10:05:41.620260 [Byte1]: 62
7865 10:05:41.624476
7866 10:05:41.624561 Set Vref, RX VrefLevel [Byte0]: 63
7867 10:05:41.628066 [Byte1]: 63
7868 10:05:41.632270
7869 10:05:41.632353 Set Vref, RX VrefLevel [Byte0]: 64
7870 10:05:41.635436 [Byte1]: 64
7871 10:05:41.639844
7872 10:05:41.639926 Set Vref, RX VrefLevel [Byte0]: 65
7873 10:05:41.643394 [Byte1]: 65
7874 10:05:41.647087
7875 10:05:41.647168 Set Vref, RX VrefLevel [Byte0]: 66
7876 10:05:41.650743 [Byte1]: 66
7877 10:05:41.655023
7878 10:05:41.655104 Set Vref, RX VrefLevel [Byte0]: 67
7879 10:05:41.658421 [Byte1]: 67
7880 10:05:41.662365
7881 10:05:41.662485 Set Vref, RX VrefLevel [Byte0]: 68
7882 10:05:41.665522 [Byte1]: 68
7883 10:05:41.669977
7884 10:05:41.670079 Set Vref, RX VrefLevel [Byte0]: 69
7885 10:05:41.673390 [Byte1]: 69
7886 10:05:41.677554
7887 10:05:41.677636 Set Vref, RX VrefLevel [Byte0]: 70
7888 10:05:41.680900 [Byte1]: 70
7889 10:05:41.685453
7890 10:05:41.685534 Set Vref, RX VrefLevel [Byte0]: 71
7891 10:05:41.688246 [Byte1]: 71
7892 10:05:41.693157
7893 10:05:41.693241 Set Vref, RX VrefLevel [Byte0]: 72
7894 10:05:41.695829 [Byte1]: 72
7895 10:05:41.700254
7896 10:05:41.700338 Set Vref, RX VrefLevel [Byte0]: 73
7897 10:05:41.703720 [Byte1]: 73
7898 10:05:41.707996
7899 10:05:41.708123 Set Vref, RX VrefLevel [Byte0]: 74
7900 10:05:41.711145 [Byte1]: 74
7901 10:05:41.715418
7902 10:05:41.715501 Set Vref, RX VrefLevel [Byte0]: 75
7903 10:05:41.719128 [Byte1]: 75
7904 10:05:41.723019
7905 10:05:41.723141 Set Vref, RX VrefLevel [Byte0]: 76
7906 10:05:41.726190 [Byte1]: 76
7907 10:05:41.730843
7908 10:05:41.730921 Final RX Vref Byte 0 = 54 to rank0
7909 10:05:41.733975 Final RX Vref Byte 1 = 59 to rank0
7910 10:05:41.737334 Final RX Vref Byte 0 = 54 to rank1
7911 10:05:41.740595 Final RX Vref Byte 1 = 59 to rank1==
7912 10:05:41.744101 Dram Type= 6, Freq= 0, CH_0, rank 0
7913 10:05:41.750491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7914 10:05:41.750598 ==
7915 10:05:41.750691 DQS Delay:
7916 10:05:41.753809 DQS0 = 0, DQS1 = 0
7917 10:05:41.753910 DQM Delay:
7918 10:05:41.756907 DQM0 = 129, DQM1 = 124
7919 10:05:41.757004 DQ Delay:
7920 10:05:41.760271 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =126
7921 10:05:41.763065 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =134
7922 10:05:41.766317 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7923 10:05:41.769733 DQ12 =132, DQ13 =128, DQ14 =132, DQ15 =132
7924 10:05:41.769830
7925 10:05:41.769919
7926 10:05:41.770004
7927 10:05:41.773076 [DramC_TX_OE_Calibration] TA2
7928 10:05:41.776381 Original DQ_B0 (3 6) =30, OEN = 27
7929 10:05:41.779961 Original DQ_B1 (3 6) =30, OEN = 27
7930 10:05:41.783330 24, 0x0, End_B0=24 End_B1=24
7931 10:05:41.786598 25, 0x0, End_B0=25 End_B1=25
7932 10:05:41.786680 26, 0x0, End_B0=26 End_B1=26
7933 10:05:41.789685 27, 0x0, End_B0=27 End_B1=27
7934 10:05:41.793312 28, 0x0, End_B0=28 End_B1=28
7935 10:05:41.796242 29, 0x0, End_B0=29 End_B1=29
7936 10:05:41.799914 30, 0x0, End_B0=30 End_B1=30
7937 10:05:41.800022 31, 0x4141, End_B0=30 End_B1=30
7938 10:05:41.802910 Byte0 end_step=30 best_step=27
7939 10:05:41.806439 Byte1 end_step=30 best_step=27
7940 10:05:41.809344 Byte0 TX OE(2T, 0.5T) = (3, 3)
7941 10:05:41.813526 Byte1 TX OE(2T, 0.5T) = (3, 3)
7942 10:05:41.813606
7943 10:05:41.813669
7944 10:05:41.819448 [DQSOSCAuto] RK0, (LSB)MR18= 0x1712, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
7945 10:05:41.822357 CH0 RK0: MR19=303, MR18=1712
7946 10:05:41.828840 CH0_RK0: MR19=0x303, MR18=0x1712, DQSOSC=398, MR23=63, INC=23, DEC=15
7947 10:05:41.828921
7948 10:05:41.832178 ----->DramcWriteLeveling(PI) begin...
7949 10:05:41.832263 ==
7950 10:05:41.835825 Dram Type= 6, Freq= 0, CH_0, rank 1
7951 10:05:41.839033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7952 10:05:41.842275 ==
7953 10:05:41.842394 Write leveling (Byte 0): 32 => 32
7954 10:05:41.845593 Write leveling (Byte 1): 26 => 26
7955 10:05:41.848798 DramcWriteLeveling(PI) end<-----
7956 10:05:41.848908
7957 10:05:41.849008 ==
7958 10:05:41.852310 Dram Type= 6, Freq= 0, CH_0, rank 1
7959 10:05:41.858641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7960 10:05:41.858746 ==
7961 10:05:41.862054 [Gating] SW mode calibration
7962 10:05:41.868260 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7963 10:05:41.871666 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7964 10:05:41.878357 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7965 10:05:41.881704 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7966 10:05:41.884628 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7967 10:05:41.891541 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7968 10:05:41.894810 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7969 10:05:41.898355 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7970 10:05:41.904522 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7971 10:05:41.907833 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7972 10:05:41.911341 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7973 10:05:41.917781 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7974 10:05:41.921532 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7975 10:05:41.924279 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
7976 10:05:41.931009 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7977 10:05:41.933992 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
7978 10:05:41.937192 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7979 10:05:41.944409 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7980 10:05:41.947187 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7981 10:05:41.950597 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 10:05:41.957335 1 6 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7983 10:05:41.960205 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7984 10:05:41.963919 1 6 16 | B1->B0 | 2a29 4646 | 1 0 | (0 0) (0 0)
7985 10:05:41.970155 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7986 10:05:41.973811 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 10:05:41.977029 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 10:05:41.983626 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 10:05:41.986609 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 10:05:41.990048 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 10:05:41.996731 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7992 10:05:41.999670 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7993 10:05:42.003167 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7994 10:05:42.009858 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 10:05:42.013041 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 10:05:42.016524 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 10:05:42.023161 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 10:05:42.026169 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 10:05:42.029506 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 10:05:42.036727 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 10:05:42.039130 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 10:05:42.043070 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 10:05:42.049610 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 10:05:42.052775 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 10:05:42.057030 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 10:05:42.062407 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8007 10:05:42.065682 Total UI for P1: 0, mck2ui 16
8008 10:05:42.069152 best dqsien dly found for B0: ( 1, 9, 6)
8009 10:05:42.072231 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8010 10:05:42.076190 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8011 10:05:42.082153 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8012 10:05:42.085906 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 10:05:42.088897 Total UI for P1: 0, mck2ui 16
8014 10:05:42.092211 best dqsien dly found for B1: ( 1, 9, 18)
8015 10:05:42.095603 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8016 10:05:42.098910 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8017 10:05:42.098987
8018 10:05:42.102274 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8019 10:05:42.105953 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8020 10:05:42.108677 [Gating] SW calibration Done
8021 10:05:42.108757 ==
8022 10:05:42.111993 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 10:05:42.118514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 10:05:42.118596 ==
8025 10:05:42.118660 RX Vref Scan: 0
8026 10:05:42.118720
8027 10:05:42.122032 RX Vref 0 -> 0, step: 1
8028 10:05:42.122113
8029 10:05:42.124968 RX Delay 0 -> 252, step: 8
8030 10:05:42.128120 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8031 10:05:42.131530 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8032 10:05:42.135119 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8033 10:05:42.141684 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8034 10:05:42.145379 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8035 10:05:42.148607 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8036 10:05:42.151759 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8037 10:05:42.155136 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8038 10:05:42.161654 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8039 10:05:42.164798 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8040 10:05:42.168655 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8041 10:05:42.171283 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8042 10:05:42.174312 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8043 10:05:42.181081 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8044 10:05:42.184310 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8045 10:05:42.188111 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8046 10:05:42.188185 ==
8047 10:05:42.191034 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 10:05:42.194456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 10:05:42.197555 ==
8050 10:05:42.197655 DQS Delay:
8051 10:05:42.197750 DQS0 = 0, DQS1 = 0
8052 10:05:42.200698 DQM Delay:
8053 10:05:42.200801 DQM0 = 130, DQM1 = 124
8054 10:05:42.204206 DQ Delay:
8055 10:05:42.207407 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
8056 10:05:42.210947 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8057 10:05:42.213746 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =115
8058 10:05:42.217073 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8059 10:05:42.217189
8060 10:05:42.217283
8061 10:05:42.217422 ==
8062 10:05:42.220487 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 10:05:42.223678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 10:05:42.223783 ==
8065 10:05:42.227395
8066 10:05:42.227500
8067 10:05:42.227601 TX Vref Scan disable
8068 10:05:42.230646 == TX Byte 0 ==
8069 10:05:42.234042 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8070 10:05:42.237432 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8071 10:05:42.240474 == TX Byte 1 ==
8072 10:05:42.243768 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8073 10:05:42.247411 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8074 10:05:42.247523 ==
8075 10:05:42.250232 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 10:05:42.256840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 10:05:42.256945 ==
8078 10:05:42.269578
8079 10:05:42.272530 TX Vref early break, caculate TX vref
8080 10:05:42.275797 TX Vref=16, minBit 0, minWin=23, winSum=374
8081 10:05:42.279343 TX Vref=18, minBit 1, minWin=23, winSum=384
8082 10:05:42.282440 TX Vref=20, minBit 3, minWin=23, winSum=389
8083 10:05:42.286050 TX Vref=22, minBit 1, minWin=24, winSum=403
8084 10:05:42.289220 TX Vref=24, minBit 1, minWin=25, winSum=414
8085 10:05:42.295939 TX Vref=26, minBit 3, minWin=24, winSum=412
8086 10:05:42.299132 TX Vref=28, minBit 1, minWin=25, winSum=416
8087 10:05:42.302626 TX Vref=30, minBit 0, minWin=25, winSum=411
8088 10:05:42.305510 TX Vref=32, minBit 1, minWin=24, winSum=406
8089 10:05:42.309278 TX Vref=34, minBit 4, minWin=23, winSum=394
8090 10:05:42.315900 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 28
8091 10:05:42.316006
8092 10:05:42.318987 Final TX Range 0 Vref 28
8093 10:05:42.319093
8094 10:05:42.319172 ==
8095 10:05:42.322539 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 10:05:42.325252 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 10:05:42.325361 ==
8098 10:05:42.325454
8099 10:05:42.325557
8100 10:05:42.328663 TX Vref Scan disable
8101 10:05:42.335411 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8102 10:05:42.335519 == TX Byte 0 ==
8103 10:05:42.338780 u2DelayCellOfst[0]=14 cells (4 PI)
8104 10:05:42.341820 u2DelayCellOfst[1]=14 cells (4 PI)
8105 10:05:42.345402 u2DelayCellOfst[2]=10 cells (3 PI)
8106 10:05:42.348173 u2DelayCellOfst[3]=10 cells (3 PI)
8107 10:05:42.351484 u2DelayCellOfst[4]=7 cells (2 PI)
8108 10:05:42.355093 u2DelayCellOfst[5]=0 cells (0 PI)
8109 10:05:42.358286 u2DelayCellOfst[6]=17 cells (5 PI)
8110 10:05:42.361411 u2DelayCellOfst[7]=17 cells (5 PI)
8111 10:05:42.364949 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8112 10:05:42.368200 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8113 10:05:42.371642 == TX Byte 1 ==
8114 10:05:42.374828 u2DelayCellOfst[8]=0 cells (0 PI)
8115 10:05:42.377898 u2DelayCellOfst[9]=0 cells (0 PI)
8116 10:05:42.381391 u2DelayCellOfst[10]=3 cells (1 PI)
8117 10:05:42.384608 u2DelayCellOfst[11]=3 cells (1 PI)
8118 10:05:42.384690 u2DelayCellOfst[12]=10 cells (3 PI)
8119 10:05:42.388321 u2DelayCellOfst[13]=10 cells (3 PI)
8120 10:05:42.391449 u2DelayCellOfst[14]=14 cells (4 PI)
8121 10:05:42.394425 u2DelayCellOfst[15]=10 cells (3 PI)
8122 10:05:42.400938 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8123 10:05:42.404669 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8124 10:05:42.408130 DramC Write-DBI on
8125 10:05:42.408211 ==
8126 10:05:42.411069 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 10:05:42.414311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 10:05:42.414393 ==
8129 10:05:42.414457
8130 10:05:42.414515
8131 10:05:42.417327 TX Vref Scan disable
8132 10:05:42.417408 == TX Byte 0 ==
8133 10:05:42.424144 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8134 10:05:42.424225 == TX Byte 1 ==
8135 10:05:42.427359 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8136 10:05:42.430644 DramC Write-DBI off
8137 10:05:42.430724
8138 10:05:42.430789 [DATLAT]
8139 10:05:42.434099 Freq=1600, CH0 RK1
8140 10:05:42.434180
8141 10:05:42.434243 DATLAT Default: 0xf
8142 10:05:42.437633 0, 0xFFFF, sum = 0
8143 10:05:42.440750 1, 0xFFFF, sum = 0
8144 10:05:42.440833 2, 0xFFFF, sum = 0
8145 10:05:42.443767 3, 0xFFFF, sum = 0
8146 10:05:42.443857 4, 0xFFFF, sum = 0
8147 10:05:42.446824 5, 0xFFFF, sum = 0
8148 10:05:42.446907 6, 0xFFFF, sum = 0
8149 10:05:42.450378 7, 0xFFFF, sum = 0
8150 10:05:42.450460 8, 0xFFFF, sum = 0
8151 10:05:42.453736 9, 0xFFFF, sum = 0
8152 10:05:42.453817 10, 0xFFFF, sum = 0
8153 10:05:42.457274 11, 0xFFFF, sum = 0
8154 10:05:42.457356 12, 0xFFFF, sum = 0
8155 10:05:42.460188 13, 0xFFFF, sum = 0
8156 10:05:42.460270 14, 0x0, sum = 1
8157 10:05:42.463463 15, 0x0, sum = 2
8158 10:05:42.463545 16, 0x0, sum = 3
8159 10:05:42.467189 17, 0x0, sum = 4
8160 10:05:42.467270 best_step = 15
8161 10:05:42.467335
8162 10:05:42.467394 ==
8163 10:05:42.470441 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 10:05:42.477071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 10:05:42.477174 ==
8166 10:05:42.477254 RX Vref Scan: 0
8167 10:05:42.477313
8168 10:05:42.480290 RX Vref 0 -> 0, step: 1
8169 10:05:42.480371
8170 10:05:42.483347 RX Delay 11 -> 252, step: 4
8171 10:05:42.486923 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8172 10:05:42.490072 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8173 10:05:42.493367 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8174 10:05:42.499532 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8175 10:05:42.502779 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8176 10:05:42.506541 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8177 10:05:42.509700 iDelay=191, Bit 6, Center 136 (87 ~ 186) 100
8178 10:05:42.515976 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8179 10:05:42.519648 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8180 10:05:42.522905 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8181 10:05:42.526363 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8182 10:05:42.529270 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8183 10:05:42.535868 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8184 10:05:42.539212 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8185 10:05:42.542407 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8186 10:05:42.545819 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8187 10:05:42.545899 ==
8188 10:05:42.549062 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 10:05:42.555945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 10:05:42.556047 ==
8191 10:05:42.556127 DQS Delay:
8192 10:05:42.559069 DQS0 = 0, DQS1 = 0
8193 10:05:42.559173 DQM Delay:
8194 10:05:42.562189 DQM0 = 128, DQM1 = 124
8195 10:05:42.562269 DQ Delay:
8196 10:05:42.565418 DQ0 =128, DQ1 =130, DQ2 =124, DQ3 =126
8197 10:05:42.568860 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =134
8198 10:05:42.572000 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8199 10:05:42.575363 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8200 10:05:42.575443
8201 10:05:42.575510
8202 10:05:42.575567
8203 10:05:42.578517 [DramC_TX_OE_Calibration] TA2
8204 10:05:42.581925 Original DQ_B0 (3 6) =30, OEN = 27
8205 10:05:42.585330 Original DQ_B1 (3 6) =30, OEN = 27
8206 10:05:42.588323 24, 0x0, End_B0=24 End_B1=24
8207 10:05:42.591781 25, 0x0, End_B0=25 End_B1=25
8208 10:05:42.591863 26, 0x0, End_B0=26 End_B1=26
8209 10:05:42.594840 27, 0x0, End_B0=27 End_B1=27
8210 10:05:42.598060 28, 0x0, End_B0=28 End_B1=28
8211 10:05:42.601893 29, 0x0, End_B0=29 End_B1=29
8212 10:05:42.604783 30, 0x0, End_B0=30 End_B1=30
8213 10:05:42.604868 31, 0x4141, End_B0=30 End_B1=30
8214 10:05:42.607979 Byte0 end_step=30 best_step=27
8215 10:05:42.611541 Byte1 end_step=30 best_step=27
8216 10:05:42.614633 Byte0 TX OE(2T, 0.5T) = (3, 3)
8217 10:05:42.618279 Byte1 TX OE(2T, 0.5T) = (3, 3)
8218 10:05:42.618364
8219 10:05:42.618449
8220 10:05:42.624877 [DQSOSCAuto] RK1, (LSB)MR18= 0x110f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
8221 10:05:42.628351 CH0 RK1: MR19=303, MR18=110F
8222 10:05:42.634810 CH0_RK1: MR19=0x303, MR18=0x110F, DQSOSC=401, MR23=63, INC=22, DEC=15
8223 10:05:42.637818 [RxdqsGatingPostProcess] freq 1600
8224 10:05:42.644559 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8225 10:05:42.647887 best DQS0 dly(2T, 0.5T) = (1, 1)
8226 10:05:42.647971 best DQS1 dly(2T, 0.5T) = (1, 1)
8227 10:05:42.651304 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8228 10:05:42.654621 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8229 10:05:42.657602 best DQS0 dly(2T, 0.5T) = (1, 1)
8230 10:05:42.660807 best DQS1 dly(2T, 0.5T) = (1, 1)
8231 10:05:42.664242 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8232 10:05:42.667506 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8233 10:05:42.671940 Pre-setting of DQS Precalculation
8234 10:05:42.677204 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8235 10:05:42.677314 ==
8236 10:05:42.680837 Dram Type= 6, Freq= 0, CH_1, rank 0
8237 10:05:42.683905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 10:05:42.683985 ==
8239 10:05:42.690319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8240 10:05:42.693395 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8241 10:05:42.697062 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8242 10:05:42.703566 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8243 10:05:42.712514 [CA 0] Center 42 (12~72) winsize 61
8244 10:05:42.715568 [CA 1] Center 42 (12~72) winsize 61
8245 10:05:42.718687 [CA 2] Center 38 (9~67) winsize 59
8246 10:05:42.722045 [CA 3] Center 37 (8~66) winsize 59
8247 10:05:42.725266 [CA 4] Center 37 (7~67) winsize 61
8248 10:05:42.728602 [CA 5] Center 36 (7~66) winsize 60
8249 10:05:42.728683
8250 10:05:42.731548 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8251 10:05:42.731629
8252 10:05:42.738337 [CATrainingPosCal] consider 1 rank data
8253 10:05:42.738418 u2DelayCellTimex100 = 275/100 ps
8254 10:05:42.745185 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8255 10:05:42.748326 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8256 10:05:42.751643 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8257 10:05:42.754941 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8258 10:05:42.758382 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8259 10:05:42.761256 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8260 10:05:42.761337
8261 10:05:42.765114 CA PerBit enable=1, Macro0, CA PI delay=36
8262 10:05:42.765195
8263 10:05:42.767824 [CBTSetCACLKResult] CA Dly = 36
8264 10:05:42.771426 CS Dly: 8 (0~39)
8265 10:05:42.774600 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8266 10:05:42.777761 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8267 10:05:42.777842 ==
8268 10:05:42.781048 Dram Type= 6, Freq= 0, CH_1, rank 1
8269 10:05:42.787960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8270 10:05:42.788067 ==
8271 10:05:42.791150 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8272 10:05:42.797893 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8273 10:05:42.800872 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8274 10:05:42.807865 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8275 10:05:42.815549 [CA 0] Center 42 (12~72) winsize 61
8276 10:05:42.818772 [CA 1] Center 42 (12~72) winsize 61
8277 10:05:42.822048 [CA 2] Center 38 (8~68) winsize 61
8278 10:05:42.825173 [CA 3] Center 37 (7~67) winsize 61
8279 10:05:42.828649 [CA 4] Center 37 (8~67) winsize 60
8280 10:05:42.831668 [CA 5] Center 37 (7~67) winsize 61
8281 10:05:42.831789
8282 10:05:42.835497 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8283 10:05:42.835631
8284 10:05:42.841748 [CATrainingPosCal] consider 2 rank data
8285 10:05:42.841899 u2DelayCellTimex100 = 275/100 ps
8286 10:05:42.847899 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8287 10:05:42.851327 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8288 10:05:42.854810 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8289 10:05:42.857955 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8290 10:05:42.861613 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8291 10:05:42.864379 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8292 10:05:42.864473
8293 10:05:42.868149 CA PerBit enable=1, Macro0, CA PI delay=36
8294 10:05:42.868259
8295 10:05:42.871319 [CBTSetCACLKResult] CA Dly = 36
8296 10:05:42.874146 CS Dly: 10 (0~43)
8297 10:05:42.877796 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8298 10:05:42.881259 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8299 10:05:42.881369
8300 10:05:42.883987 ----->DramcWriteLeveling(PI) begin...
8301 10:05:42.887412 ==
8302 10:05:42.887491 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 10:05:42.894111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 10:05:42.894191 ==
8305 10:05:42.897677 Write leveling (Byte 0): 24 => 24
8306 10:05:42.900948 Write leveling (Byte 1): 26 => 26
8307 10:05:42.904027 DramcWriteLeveling(PI) end<-----
8308 10:05:42.904127
8309 10:05:42.904189 ==
8310 10:05:42.907460 Dram Type= 6, Freq= 0, CH_1, rank 0
8311 10:05:42.910309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 10:05:42.910410 ==
8313 10:05:42.914048 [Gating] SW mode calibration
8314 10:05:42.920604 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8315 10:05:42.926916 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8316 10:05:42.930079 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8317 10:05:42.933380 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 10:05:42.940203 1 4 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
8319 10:05:42.943229 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8320 10:05:42.946745 1 4 16 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8321 10:05:42.953048 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 10:05:42.956610 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 10:05:42.959715 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 10:05:42.966195 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 10:05:42.969791 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 10:05:42.973183 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 10:05:42.979259 1 5 12 | B1->B0 | 2d2d 2424 | 1 0 | (1 0) (1 0)
8328 10:05:42.982844 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 10:05:42.986283 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 10:05:42.992896 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 10:05:42.995735 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 10:05:42.999100 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 10:05:43.005915 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 10:05:43.009333 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 10:05:43.012490 1 6 12 | B1->B0 | 2424 4242 | 0 0 | (0 0) (0 0)
8336 10:05:43.019000 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 10:05:43.022580 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 10:05:43.025989 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 10:05:43.032264 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 10:05:43.035487 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 10:05:43.039132 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 10:05:43.045402 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 10:05:43.048765 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8344 10:05:43.052326 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8345 10:05:43.058594 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 10:05:43.061867 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 10:05:43.064995 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 10:05:43.072026 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 10:05:43.074855 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 10:05:43.078055 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 10:05:43.084569 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 10:05:43.088027 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 10:05:43.091336 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 10:05:43.098291 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 10:05:43.101677 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 10:05:43.105044 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 10:05:43.111274 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 10:05:43.114475 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8359 10:05:43.117689 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8360 10:05:43.124288 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 10:05:43.124370 Total UI for P1: 0, mck2ui 16
8362 10:05:43.131039 best dqsien dly found for B0: ( 1, 9, 10)
8363 10:05:43.131121 Total UI for P1: 0, mck2ui 16
8364 10:05:43.137573 best dqsien dly found for B1: ( 1, 9, 12)
8365 10:05:43.140885 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8366 10:05:43.143935 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8367 10:05:43.144058
8368 10:05:43.147421 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8369 10:05:43.151562 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8370 10:05:43.153908 [Gating] SW calibration Done
8371 10:05:43.153982 ==
8372 10:05:43.157459 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 10:05:43.160430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 10:05:43.160510 ==
8375 10:05:43.163781 RX Vref Scan: 0
8376 10:05:43.163853
8377 10:05:43.167548 RX Vref 0 -> 0, step: 1
8378 10:05:43.167617
8379 10:05:43.167678 RX Delay 0 -> 252, step: 8
8380 10:05:43.173750 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8381 10:05:43.177054 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8382 10:05:43.180609 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8383 10:05:43.183818 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8384 10:05:43.187217 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8385 10:05:43.193725 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8386 10:05:43.197253 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8387 10:05:43.200545 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8388 10:05:43.203425 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8389 10:05:43.206774 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8390 10:05:43.213253 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8391 10:05:43.216686 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8392 10:05:43.219952 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8393 10:05:43.223273 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8394 10:05:43.229822 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8395 10:05:43.233199 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8396 10:05:43.233280 ==
8397 10:05:43.236283 Dram Type= 6, Freq= 0, CH_1, rank 0
8398 10:05:43.240000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8399 10:05:43.240121 ==
8400 10:05:43.243424 DQS Delay:
8401 10:05:43.243533 DQS0 = 0, DQS1 = 0
8402 10:05:43.243627 DQM Delay:
8403 10:05:43.246508 DQM0 = 134, DQM1 = 129
8404 10:05:43.246611 DQ Delay:
8405 10:05:43.249661 DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =135
8406 10:05:43.253077 DQ4 =127, DQ5 =143, DQ6 =147, DQ7 =131
8407 10:05:43.256090 DQ8 =115, DQ9 =119, DQ10 =127, DQ11 =123
8408 10:05:43.262684 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8409 10:05:43.262790
8410 10:05:43.262905
8411 10:05:43.262998 ==
8412 10:05:43.265970 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 10:05:43.269177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 10:05:43.269278 ==
8415 10:05:43.269385
8416 10:05:43.269476
8417 10:05:43.273124 TX Vref Scan disable
8418 10:05:43.273240 == TX Byte 0 ==
8419 10:05:43.279467 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8420 10:05:43.282288 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8421 10:05:43.282390 == TX Byte 1 ==
8422 10:05:43.288943 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8423 10:05:43.292528 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8424 10:05:43.292633 ==
8425 10:05:43.295633 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 10:05:43.299330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 10:05:43.299432 ==
8428 10:05:43.313010
8429 10:05:43.316364 TX Vref early break, caculate TX vref
8430 10:05:43.319366 TX Vref=16, minBit 8, minWin=21, winSum=370
8431 10:05:43.322800 TX Vref=18, minBit 13, minWin=22, winSum=380
8432 10:05:43.326242 TX Vref=20, minBit 6, minWin=23, winSum=384
8433 10:05:43.329369 TX Vref=22, minBit 8, minWin=24, winSum=400
8434 10:05:43.335760 TX Vref=24, minBit 13, minWin=24, winSum=408
8435 10:05:43.339197 TX Vref=26, minBit 8, minWin=25, winSum=415
8436 10:05:43.342845 TX Vref=28, minBit 0, minWin=25, winSum=422
8437 10:05:43.346537 TX Vref=30, minBit 9, minWin=24, winSum=414
8438 10:05:43.348904 TX Vref=32, minBit 9, minWin=24, winSum=407
8439 10:05:43.352776 TX Vref=34, minBit 0, minWin=23, winSum=393
8440 10:05:43.359194 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
8441 10:05:43.359285
8442 10:05:43.362491 Final TX Range 0 Vref 28
8443 10:05:43.362574
8444 10:05:43.362639 ==
8445 10:05:43.365304 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 10:05:43.369112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 10:05:43.369195 ==
8448 10:05:43.369260
8449 10:05:43.372191
8450 10:05:43.372293 TX Vref Scan disable
8451 10:05:43.378853 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8452 10:05:43.378940 == TX Byte 0 ==
8453 10:05:43.381683 u2DelayCellOfst[0]=14 cells (4 PI)
8454 10:05:43.385446 u2DelayCellOfst[1]=7 cells (2 PI)
8455 10:05:43.388235 u2DelayCellOfst[2]=0 cells (0 PI)
8456 10:05:43.391739 u2DelayCellOfst[3]=3 cells (1 PI)
8457 10:05:43.395554 u2DelayCellOfst[4]=7 cells (2 PI)
8458 10:05:43.398664 u2DelayCellOfst[5]=14 cells (4 PI)
8459 10:05:43.401463 u2DelayCellOfst[6]=14 cells (4 PI)
8460 10:05:43.404900 u2DelayCellOfst[7]=3 cells (1 PI)
8461 10:05:43.408482 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8462 10:05:43.411183 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8463 10:05:43.414481 == TX Byte 1 ==
8464 10:05:43.417786 u2DelayCellOfst[8]=0 cells (0 PI)
8465 10:05:43.421162 u2DelayCellOfst[9]=3 cells (1 PI)
8466 10:05:43.424478 u2DelayCellOfst[10]=10 cells (3 PI)
8467 10:05:43.427838 u2DelayCellOfst[11]=3 cells (1 PI)
8468 10:05:43.431001 u2DelayCellOfst[12]=14 cells (4 PI)
8469 10:05:43.434613 u2DelayCellOfst[13]=17 cells (5 PI)
8470 10:05:43.434686 u2DelayCellOfst[14]=17 cells (5 PI)
8471 10:05:43.438138 u2DelayCellOfst[15]=17 cells (5 PI)
8472 10:05:43.443989 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8473 10:05:43.447529 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8474 10:05:43.450985 DramC Write-DBI on
8475 10:05:43.451084 ==
8476 10:05:43.454774 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 10:05:43.457375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 10:05:43.457459 ==
8479 10:05:43.457550
8480 10:05:43.457612
8481 10:05:43.460769 TX Vref Scan disable
8482 10:05:43.460866 == TX Byte 0 ==
8483 10:05:43.467255 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8484 10:05:43.467334 == TX Byte 1 ==
8485 10:05:43.470288 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8486 10:05:43.473910 DramC Write-DBI off
8487 10:05:43.473993
8488 10:05:43.474057 [DATLAT]
8489 10:05:43.477218 Freq=1600, CH1 RK0
8490 10:05:43.477333
8491 10:05:43.477444 DATLAT Default: 0xf
8492 10:05:43.480667 0, 0xFFFF, sum = 0
8493 10:05:43.480750 1, 0xFFFF, sum = 0
8494 10:05:43.483860 2, 0xFFFF, sum = 0
8495 10:05:43.486883 3, 0xFFFF, sum = 0
8496 10:05:43.486958 4, 0xFFFF, sum = 0
8497 10:05:43.490204 5, 0xFFFF, sum = 0
8498 10:05:43.490280 6, 0xFFFF, sum = 0
8499 10:05:43.493736 7, 0xFFFF, sum = 0
8500 10:05:43.493815 8, 0xFFFF, sum = 0
8501 10:05:43.496618 9, 0xFFFF, sum = 0
8502 10:05:43.496688 10, 0xFFFF, sum = 0
8503 10:05:43.500194 11, 0xFFFF, sum = 0
8504 10:05:43.500264 12, 0xFFFF, sum = 0
8505 10:05:43.503563 13, 0xFFFF, sum = 0
8506 10:05:43.503633 14, 0x0, sum = 1
8507 10:05:43.506758 15, 0x0, sum = 2
8508 10:05:43.506828 16, 0x0, sum = 3
8509 10:05:43.510286 17, 0x0, sum = 4
8510 10:05:43.510356 best_step = 15
8511 10:05:43.510427
8512 10:05:43.510483 ==
8513 10:05:43.513496 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 10:05:43.519744 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 10:05:43.519827 ==
8516 10:05:43.519892 RX Vref Scan: 1
8517 10:05:43.519951
8518 10:05:43.522991 Set Vref Range= 24 -> 127
8519 10:05:43.523072
8520 10:05:43.526339 RX Vref 24 -> 127, step: 1
8521 10:05:43.526419
8522 10:05:43.530042 RX Delay 19 -> 252, step: 4
8523 10:05:43.530122
8524 10:05:43.533069 Set Vref, RX VrefLevel [Byte0]: 24
8525 10:05:43.536524 [Byte1]: 24
8526 10:05:43.536604
8527 10:05:43.539446 Set Vref, RX VrefLevel [Byte0]: 25
8528 10:05:43.542868 [Byte1]: 25
8529 10:05:43.542949
8530 10:05:43.546359 Set Vref, RX VrefLevel [Byte0]: 26
8531 10:05:43.549152 [Byte1]: 26
8532 10:05:43.549232
8533 10:05:43.552729 Set Vref, RX VrefLevel [Byte0]: 27
8534 10:05:43.555816 [Byte1]: 27
8535 10:05:43.560088
8536 10:05:43.560168 Set Vref, RX VrefLevel [Byte0]: 28
8537 10:05:43.563676 [Byte1]: 28
8538 10:05:43.568025
8539 10:05:43.568143 Set Vref, RX VrefLevel [Byte0]: 29
8540 10:05:43.571295 [Byte1]: 29
8541 10:05:43.575285
8542 10:05:43.575371 Set Vref, RX VrefLevel [Byte0]: 30
8543 10:05:43.578508 [Byte1]: 30
8544 10:05:43.582696
8545 10:05:43.582797 Set Vref, RX VrefLevel [Byte0]: 31
8546 10:05:43.586185 [Byte1]: 31
8547 10:05:43.590151
8548 10:05:43.590252 Set Vref, RX VrefLevel [Byte0]: 32
8549 10:05:43.593796 [Byte1]: 32
8550 10:05:43.598085
8551 10:05:43.598165 Set Vref, RX VrefLevel [Byte0]: 33
8552 10:05:43.601571 [Byte1]: 33
8553 10:05:43.605255
8554 10:05:43.605335 Set Vref, RX VrefLevel [Byte0]: 34
8555 10:05:43.608776 [Byte1]: 34
8556 10:05:43.613102
8557 10:05:43.613182 Set Vref, RX VrefLevel [Byte0]: 35
8558 10:05:43.616675 [Byte1]: 35
8559 10:05:43.620508
8560 10:05:43.620589 Set Vref, RX VrefLevel [Byte0]: 36
8561 10:05:43.623905 [Byte1]: 36
8562 10:05:43.628402
8563 10:05:43.628481 Set Vref, RX VrefLevel [Byte0]: 37
8564 10:05:43.631341 [Byte1]: 37
8565 10:05:43.635797
8566 10:05:43.635905 Set Vref, RX VrefLevel [Byte0]: 38
8567 10:05:43.639193 [Byte1]: 38
8568 10:05:43.643342
8569 10:05:43.643448 Set Vref, RX VrefLevel [Byte0]: 39
8570 10:05:43.646613 [Byte1]: 39
8571 10:05:43.651165
8572 10:05:43.651239 Set Vref, RX VrefLevel [Byte0]: 40
8573 10:05:43.654257 [Byte1]: 40
8574 10:05:43.658433
8575 10:05:43.658541 Set Vref, RX VrefLevel [Byte0]: 41
8576 10:05:43.662007 [Byte1]: 41
8577 10:05:43.666492
8578 10:05:43.666604 Set Vref, RX VrefLevel [Byte0]: 42
8579 10:05:43.669833 [Byte1]: 42
8580 10:05:43.673457
8581 10:05:43.673559 Set Vref, RX VrefLevel [Byte0]: 43
8582 10:05:43.676997 [Byte1]: 43
8583 10:05:43.681211
8584 10:05:43.681291 Set Vref, RX VrefLevel [Byte0]: 44
8585 10:05:43.684679 [Byte1]: 44
8586 10:05:43.689062
8587 10:05:43.689142 Set Vref, RX VrefLevel [Byte0]: 45
8588 10:05:43.691959 [Byte1]: 45
8589 10:05:43.696415
8590 10:05:43.696495 Set Vref, RX VrefLevel [Byte0]: 46
8591 10:05:43.703383 [Byte1]: 46
8592 10:05:43.703464
8593 10:05:43.706217 Set Vref, RX VrefLevel [Byte0]: 47
8594 10:05:43.709565 [Byte1]: 47
8595 10:05:43.709646
8596 10:05:43.712848 Set Vref, RX VrefLevel [Byte0]: 48
8597 10:05:43.715869 [Byte1]: 48
8598 10:05:43.715967
8599 10:05:43.719096 Set Vref, RX VrefLevel [Byte0]: 49
8600 10:05:43.722509 [Byte1]: 49
8601 10:05:43.726471
8602 10:05:43.726551 Set Vref, RX VrefLevel [Byte0]: 50
8603 10:05:43.730428 [Byte1]: 50
8604 10:05:43.734105
8605 10:05:43.734184 Set Vref, RX VrefLevel [Byte0]: 51
8606 10:05:43.737707 [Byte1]: 51
8607 10:05:43.741970
8608 10:05:43.742054 Set Vref, RX VrefLevel [Byte0]: 52
8609 10:05:43.745373 [Byte1]: 52
8610 10:05:43.749289
8611 10:05:43.749399 Set Vref, RX VrefLevel [Byte0]: 53
8612 10:05:43.752649 [Byte1]: 53
8613 10:05:43.757132
8614 10:05:43.757236 Set Vref, RX VrefLevel [Byte0]: 54
8615 10:05:43.760315 [Byte1]: 54
8616 10:05:43.764337
8617 10:05:43.764444 Set Vref, RX VrefLevel [Byte0]: 55
8618 10:05:43.767640 [Byte1]: 55
8619 10:05:43.772345
8620 10:05:43.772448 Set Vref, RX VrefLevel [Byte0]: 56
8621 10:05:43.775299 [Byte1]: 56
8622 10:05:43.779819
8623 10:05:43.779902 Set Vref, RX VrefLevel [Byte0]: 57
8624 10:05:43.782825 [Byte1]: 57
8625 10:05:43.787311
8626 10:05:43.787393 Set Vref, RX VrefLevel [Byte0]: 58
8627 10:05:43.790350 [Byte1]: 58
8628 10:05:43.794931
8629 10:05:43.795014 Set Vref, RX VrefLevel [Byte0]: 59
8630 10:05:43.798255 [Byte1]: 59
8631 10:05:43.802283
8632 10:05:43.802364 Set Vref, RX VrefLevel [Byte0]: 60
8633 10:05:43.805408 [Byte1]: 60
8634 10:05:43.810017
8635 10:05:43.810099 Set Vref, RX VrefLevel [Byte0]: 61
8636 10:05:43.813136 [Byte1]: 61
8637 10:05:43.817560
8638 10:05:43.817641 Set Vref, RX VrefLevel [Byte0]: 62
8639 10:05:43.820951 [Byte1]: 62
8640 10:05:43.825163
8641 10:05:43.825244 Set Vref, RX VrefLevel [Byte0]: 63
8642 10:05:43.828684 [Byte1]: 63
8643 10:05:43.832624
8644 10:05:43.832710 Set Vref, RX VrefLevel [Byte0]: 64
8645 10:05:43.835736 [Byte1]: 64
8646 10:05:43.840398
8647 10:05:43.840479 Set Vref, RX VrefLevel [Byte0]: 65
8648 10:05:43.843693 [Byte1]: 65
8649 10:05:43.847690
8650 10:05:43.847771 Set Vref, RX VrefLevel [Byte0]: 66
8651 10:05:43.850974 [Byte1]: 66
8652 10:05:43.855598
8653 10:05:43.855680 Set Vref, RX VrefLevel [Byte0]: 67
8654 10:05:43.858477 [Byte1]: 67
8655 10:05:43.863071
8656 10:05:43.863153 Set Vref, RX VrefLevel [Byte0]: 68
8657 10:05:43.866142 [Byte1]: 68
8658 10:05:43.870331
8659 10:05:43.870413 Set Vref, RX VrefLevel [Byte0]: 69
8660 10:05:43.873720 [Byte1]: 69
8661 10:05:43.878102
8662 10:05:43.878184 Set Vref, RX VrefLevel [Byte0]: 70
8663 10:05:43.881579 [Byte1]: 70
8664 10:05:43.886111
8665 10:05:43.886193 Set Vref, RX VrefLevel [Byte0]: 71
8666 10:05:43.888877 [Byte1]: 71
8667 10:05:43.893108
8668 10:05:43.893190 Set Vref, RX VrefLevel [Byte0]: 72
8669 10:05:43.899780 [Byte1]: 72
8670 10:05:43.899861
8671 10:05:43.902873 Final RX Vref Byte 0 = 54 to rank0
8672 10:05:43.906057 Final RX Vref Byte 1 = 62 to rank0
8673 10:05:43.909609 Final RX Vref Byte 0 = 54 to rank1
8674 10:05:43.912726 Final RX Vref Byte 1 = 62 to rank1==
8675 10:05:43.916305 Dram Type= 6, Freq= 0, CH_1, rank 0
8676 10:05:43.919915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8677 10:05:43.919998 ==
8678 10:05:43.920103 DQS Delay:
8679 10:05:43.922946 DQS0 = 0, DQS1 = 0
8680 10:05:43.923027 DQM Delay:
8681 10:05:43.926595 DQM0 = 131, DQM1 = 128
8682 10:05:43.926678 DQ Delay:
8683 10:05:43.929828 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =130
8684 10:05:43.933409 DQ4 =126, DQ5 =142, DQ6 =144, DQ7 =126
8685 10:05:43.936180 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8686 10:05:43.939393 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8687 10:05:43.939475
8688 10:05:43.939539
8689 10:05:43.942770
8690 10:05:43.942851 [DramC_TX_OE_Calibration] TA2
8691 10:05:43.945840 Original DQ_B0 (3 6) =30, OEN = 27
8692 10:05:43.949357 Original DQ_B1 (3 6) =30, OEN = 27
8693 10:05:43.952782 24, 0x0, End_B0=24 End_B1=24
8694 10:05:43.955596 25, 0x0, End_B0=25 End_B1=25
8695 10:05:43.959284 26, 0x0, End_B0=26 End_B1=26
8696 10:05:43.959366 27, 0x0, End_B0=27 End_B1=27
8697 10:05:43.962581 28, 0x0, End_B0=28 End_B1=28
8698 10:05:43.966116 29, 0x0, End_B0=29 End_B1=29
8699 10:05:43.968843 30, 0x0, End_B0=30 End_B1=30
8700 10:05:43.972498 31, 0x4141, End_B0=30 End_B1=30
8701 10:05:43.972582 Byte0 end_step=30 best_step=27
8702 10:05:43.975892 Byte1 end_step=30 best_step=27
8703 10:05:43.978739 Byte0 TX OE(2T, 0.5T) = (3, 3)
8704 10:05:43.982099 Byte1 TX OE(2T, 0.5T) = (3, 3)
8705 10:05:43.982181
8706 10:05:43.982246
8707 10:05:43.991895 [DQSOSCAuto] RK0, (LSB)MR18= 0xc16, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8708 10:05:43.991978 CH1 RK0: MR19=303, MR18=C16
8709 10:05:43.998490 CH1_RK0: MR19=0x303, MR18=0xC16, DQSOSC=398, MR23=63, INC=23, DEC=15
8710 10:05:43.998573
8711 10:05:44.001865 ----->DramcWriteLeveling(PI) begin...
8712 10:05:44.001949 ==
8713 10:05:44.004900 Dram Type= 6, Freq= 0, CH_1, rank 1
8714 10:05:44.011747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8715 10:05:44.011830 ==
8716 10:05:44.014783 Write leveling (Byte 0): 25 => 25
8717 10:05:44.018200 Write leveling (Byte 1): 25 => 25
8718 10:05:44.018308 DramcWriteLeveling(PI) end<-----
8719 10:05:44.018384
8720 10:05:44.021364 ==
8721 10:05:44.024547 Dram Type= 6, Freq= 0, CH_1, rank 1
8722 10:05:44.028280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8723 10:05:44.028363 ==
8724 10:05:44.031508 [Gating] SW mode calibration
8725 10:05:44.037881 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8726 10:05:44.041252 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8727 10:05:44.047928 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8728 10:05:44.051230 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8729 10:05:44.054633 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8730 10:05:44.061033 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8731 10:05:44.064615 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8732 10:05:44.067914 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8733 10:05:44.074415 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8734 10:05:44.077347 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 10:05:44.080598 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 10:05:44.086986 1 5 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8737 10:05:44.090333 1 5 8 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
8738 10:05:44.094174 1 5 12 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8739 10:05:44.100620 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 10:05:44.103693 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 10:05:44.107009 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 10:05:44.113349 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 10:05:44.116852 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 10:05:44.123483 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8745 10:05:44.127197 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8746 10:05:44.130192 1 6 12 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
8747 10:05:44.136544 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8748 10:05:44.140098 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8749 10:05:44.143347 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8750 10:05:44.149390 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 10:05:44.152970 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 10:05:44.156424 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 10:05:44.162867 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8754 10:05:44.165837 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8755 10:05:44.169273 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8756 10:05:44.175894 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 10:05:44.179171 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 10:05:44.182130 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 10:05:44.189014 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 10:05:44.192174 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 10:05:44.195521 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 10:05:44.202349 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 10:05:44.205517 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 10:05:44.208840 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 10:05:44.215411 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 10:05:44.218796 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 10:05:44.221933 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 10:05:44.228346 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8769 10:05:44.231916 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8770 10:05:44.235083 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8771 10:05:44.238723 Total UI for P1: 0, mck2ui 16
8772 10:05:44.241725 best dqsien dly found for B0: ( 1, 9, 6)
8773 10:05:44.248530 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 10:05:44.248647 Total UI for P1: 0, mck2ui 16
8775 10:05:44.255080 best dqsien dly found for B1: ( 1, 9, 12)
8776 10:05:44.257997 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8777 10:05:44.261523 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8778 10:05:44.261623
8779 10:05:44.264765 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8780 10:05:44.268145 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8781 10:05:44.271409 [Gating] SW calibration Done
8782 10:05:44.271514 ==
8783 10:05:44.274629 Dram Type= 6, Freq= 0, CH_1, rank 1
8784 10:05:44.277720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8785 10:05:44.277798 ==
8786 10:05:44.281397 RX Vref Scan: 0
8787 10:05:44.281469
8788 10:05:44.281528 RX Vref 0 -> 0, step: 1
8789 10:05:44.281586
8790 10:05:44.284815 RX Delay 0 -> 252, step: 8
8791 10:05:44.287953 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8792 10:05:44.294487 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8793 10:05:44.297785 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8794 10:05:44.300923 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8795 10:05:44.304362 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8796 10:05:44.307946 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8797 10:05:44.314299 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8798 10:05:44.317697 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8799 10:05:44.320854 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8800 10:05:44.323842 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8801 10:05:44.330886 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8802 10:05:44.333846 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8803 10:05:44.336923 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8804 10:05:44.340397 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8805 10:05:44.343598 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8806 10:05:44.350060 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8807 10:05:44.350143 ==
8808 10:05:44.353418 Dram Type= 6, Freq= 0, CH_1, rank 1
8809 10:05:44.356914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8810 10:05:44.356995 ==
8811 10:05:44.357059 DQS Delay:
8812 10:05:44.360440 DQS0 = 0, DQS1 = 0
8813 10:05:44.360521 DQM Delay:
8814 10:05:44.363683 DQM0 = 133, DQM1 = 130
8815 10:05:44.363764 DQ Delay:
8816 10:05:44.367046 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =131
8817 10:05:44.370158 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8818 10:05:44.373080 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8819 10:05:44.379564 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8820 10:05:44.379645
8821 10:05:44.379707
8822 10:05:44.379770 ==
8823 10:05:44.383289 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 10:05:44.386457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 10:05:44.386538 ==
8826 10:05:44.386602
8827 10:05:44.386660
8828 10:05:44.389421 TX Vref Scan disable
8829 10:05:44.389501 == TX Byte 0 ==
8830 10:05:44.396610 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8831 10:05:44.399344 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8832 10:05:44.399425 == TX Byte 1 ==
8833 10:05:44.406363 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8834 10:05:44.409387 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8835 10:05:44.409467 ==
8836 10:05:44.412728 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 10:05:44.415985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 10:05:44.416099 ==
8839 10:05:44.431223
8840 10:05:44.433835 TX Vref early break, caculate TX vref
8841 10:05:44.437507 TX Vref=16, minBit 9, minWin=22, winSum=378
8842 10:05:44.440559 TX Vref=18, minBit 9, minWin=22, winSum=384
8843 10:05:44.443814 TX Vref=20, minBit 9, minWin=22, winSum=393
8844 10:05:44.447207 TX Vref=22, minBit 9, minWin=23, winSum=401
8845 10:05:44.450597 TX Vref=24, minBit 9, minWin=24, winSum=409
8846 10:05:44.457127 TX Vref=26, minBit 9, minWin=24, winSum=415
8847 10:05:44.460481 TX Vref=28, minBit 9, minWin=25, winSum=423
8848 10:05:44.463988 TX Vref=30, minBit 9, minWin=24, winSum=420
8849 10:05:44.467585 TX Vref=32, minBit 0, minWin=24, winSum=412
8850 10:05:44.470582 TX Vref=34, minBit 0, minWin=24, winSum=401
8851 10:05:44.477302 TX Vref=36, minBit 8, minWin=23, winSum=394
8852 10:05:44.480152 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 28
8853 10:05:44.480268
8854 10:05:44.483669 Final TX Range 0 Vref 28
8855 10:05:44.483766
8856 10:05:44.483882 ==
8857 10:05:44.486533 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 10:05:44.490223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 10:05:44.493530 ==
8860 10:05:44.493612
8861 10:05:44.493695
8862 10:05:44.493773 TX Vref Scan disable
8863 10:05:44.500208 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8864 10:05:44.500292 == TX Byte 0 ==
8865 10:05:44.503167 u2DelayCellOfst[0]=14 cells (4 PI)
8866 10:05:44.506495 u2DelayCellOfst[1]=10 cells (3 PI)
8867 10:05:44.509563 u2DelayCellOfst[2]=0 cells (0 PI)
8868 10:05:44.513141 u2DelayCellOfst[3]=3 cells (1 PI)
8869 10:05:44.516685 u2DelayCellOfst[4]=7 cells (2 PI)
8870 10:05:44.519842 u2DelayCellOfst[5]=14 cells (4 PI)
8871 10:05:44.523407 u2DelayCellOfst[6]=14 cells (4 PI)
8872 10:05:44.526265 u2DelayCellOfst[7]=7 cells (2 PI)
8873 10:05:44.529479 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8874 10:05:44.533353 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8875 10:05:44.536027 == TX Byte 1 ==
8876 10:05:44.539219 u2DelayCellOfst[8]=0 cells (0 PI)
8877 10:05:44.542773 u2DelayCellOfst[9]=7 cells (2 PI)
8878 10:05:44.546130 u2DelayCellOfst[10]=14 cells (4 PI)
8879 10:05:44.549218 u2DelayCellOfst[11]=7 cells (2 PI)
8880 10:05:44.552739 u2DelayCellOfst[12]=17 cells (5 PI)
8881 10:05:44.555888 u2DelayCellOfst[13]=17 cells (5 PI)
8882 10:05:44.559087 u2DelayCellOfst[14]=21 cells (6 PI)
8883 10:05:44.562605 u2DelayCellOfst[15]=21 cells (6 PI)
8884 10:05:44.565635 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8885 10:05:44.568662 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8886 10:05:44.572319 DramC Write-DBI on
8887 10:05:44.572402 ==
8888 10:05:44.575762 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 10:05:44.579111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 10:05:44.579601 ==
8891 10:05:44.580146
8892 10:05:44.580684
8893 10:05:44.582789 TX Vref Scan disable
8894 10:05:44.583214 == TX Byte 0 ==
8895 10:05:44.588796 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8896 10:05:44.589224 == TX Byte 1 ==
8897 10:05:44.595473 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8898 10:05:44.595903 DramC Write-DBI off
8899 10:05:44.596380
8900 10:05:44.596794 [DATLAT]
8901 10:05:44.599487 Freq=1600, CH1 RK1
8902 10:05:44.599915
8903 10:05:44.602160 DATLAT Default: 0xf
8904 10:05:44.602585 0, 0xFFFF, sum = 0
8905 10:05:44.605411 1, 0xFFFF, sum = 0
8906 10:05:44.605845 2, 0xFFFF, sum = 0
8907 10:05:44.608971 3, 0xFFFF, sum = 0
8908 10:05:44.609425 4, 0xFFFF, sum = 0
8909 10:05:44.612190 5, 0xFFFF, sum = 0
8910 10:05:44.612676 6, 0xFFFF, sum = 0
8911 10:05:44.615579 7, 0xFFFF, sum = 0
8912 10:05:44.616009 8, 0xFFFF, sum = 0
8913 10:05:44.618747 9, 0xFFFF, sum = 0
8914 10:05:44.619169 10, 0xFFFF, sum = 0
8915 10:05:44.622428 11, 0xFFFF, sum = 0
8916 10:05:44.622852 12, 0xFFFF, sum = 0
8917 10:05:44.625486 13, 0xFFFF, sum = 0
8918 10:05:44.625911 14, 0x0, sum = 1
8919 10:05:44.628914 15, 0x0, sum = 2
8920 10:05:44.629345 16, 0x0, sum = 3
8921 10:05:44.631794 17, 0x0, sum = 4
8922 10:05:44.632271 best_step = 15
8923 10:05:44.632609
8924 10:05:44.632920 ==
8925 10:05:44.635601 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 10:05:44.642387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 10:05:44.642941 ==
8928 10:05:44.643421 RX Vref Scan: 0
8929 10:05:44.643927
8930 10:05:44.645293 RX Vref 0 -> 0, step: 1
8931 10:05:44.645650
8932 10:05:44.648843 RX Delay 11 -> 252, step: 4
8933 10:05:44.652019 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8934 10:05:44.655576 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8935 10:05:44.661852 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8936 10:05:44.664922 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8937 10:05:44.668115 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8938 10:05:44.671286 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8939 10:05:44.674426 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8940 10:05:44.681391 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8941 10:05:44.684332 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8942 10:05:44.687451 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8943 10:05:44.691059 iDelay=195, Bit 10, Center 130 (75 ~ 186) 112
8944 10:05:44.694264 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8945 10:05:44.700851 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8946 10:05:44.704491 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8947 10:05:44.707290 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8948 10:05:44.710736 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8949 10:05:44.713765 ==
8950 10:05:44.713845 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 10:05:44.720324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 10:05:44.720405 ==
8953 10:05:44.720469 DQS Delay:
8954 10:05:44.723721 DQS0 = 0, DQS1 = 0
8955 10:05:44.723800 DQM Delay:
8956 10:05:44.727014 DQM0 = 131, DQM1 = 128
8957 10:05:44.727095 DQ Delay:
8958 10:05:44.730444 DQ0 =134, DQ1 =128, DQ2 =120, DQ3 =128
8959 10:05:44.733315 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =128
8960 10:05:44.736834 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =120
8961 10:05:44.740581 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
8962 10:05:44.740661
8963 10:05:44.740739
8964 10:05:44.740811
8965 10:05:44.743754 [DramC_TX_OE_Calibration] TA2
8966 10:05:44.746630 Original DQ_B0 (3 6) =30, OEN = 27
8967 10:05:44.750213 Original DQ_B1 (3 6) =30, OEN = 27
8968 10:05:44.753767 24, 0x0, End_B0=24 End_B1=24
8969 10:05:44.756685 25, 0x0, End_B0=25 End_B1=25
8970 10:05:44.756778 26, 0x0, End_B0=26 End_B1=26
8971 10:05:44.759668 27, 0x0, End_B0=27 End_B1=27
8972 10:05:44.763335 28, 0x0, End_B0=28 End_B1=28
8973 10:05:44.766616 29, 0x0, End_B0=29 End_B1=29
8974 10:05:44.769611 30, 0x0, End_B0=30 End_B1=30
8975 10:05:44.769693 31, 0x4545, End_B0=30 End_B1=30
8976 10:05:44.773401 Byte0 end_step=30 best_step=27
8977 10:05:44.776333 Byte1 end_step=30 best_step=27
8978 10:05:44.779382 Byte0 TX OE(2T, 0.5T) = (3, 3)
8979 10:05:44.783111 Byte1 TX OE(2T, 0.5T) = (3, 3)
8980 10:05:44.783191
8981 10:05:44.783254
8982 10:05:44.789387 [DQSOSCAuto] RK1, (LSB)MR18= 0xc19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 403 ps
8983 10:05:44.792569 CH1 RK1: MR19=303, MR18=C19
8984 10:05:44.799202 CH1_RK1: MR19=0x303, MR18=0xC19, DQSOSC=397, MR23=63, INC=23, DEC=15
8985 10:05:44.802992 [RxdqsGatingPostProcess] freq 1600
8986 10:05:44.809056 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8987 10:05:44.812591 best DQS0 dly(2T, 0.5T) = (1, 1)
8988 10:05:44.812670 best DQS1 dly(2T, 0.5T) = (1, 1)
8989 10:05:44.815679 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8990 10:05:44.819621 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8991 10:05:44.822372 best DQS0 dly(2T, 0.5T) = (1, 1)
8992 10:05:44.825788 best DQS1 dly(2T, 0.5T) = (1, 1)
8993 10:05:44.828913 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8994 10:05:44.832477 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8995 10:05:44.836063 Pre-setting of DQS Precalculation
8996 10:05:44.839030 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8997 10:05:44.848741 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8998 10:05:44.855196 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8999 10:05:44.855277
9000 10:05:44.855341
9001 10:05:44.858419 [Calibration Summary] 3200 Mbps
9002 10:05:44.858501 CH 0, Rank 0
9003 10:05:44.861732 SW Impedance : PASS
9004 10:05:44.865067 DUTY Scan : NO K
9005 10:05:44.865149 ZQ Calibration : PASS
9006 10:05:44.868677 Jitter Meter : NO K
9007 10:05:44.868759 CBT Training : PASS
9008 10:05:44.871951 Write leveling : PASS
9009 10:05:44.875124 RX DQS gating : PASS
9010 10:05:44.875206 RX DQ/DQS(RDDQC) : PASS
9011 10:05:44.878036 TX DQ/DQS : PASS
9012 10:05:44.881346 RX DATLAT : PASS
9013 10:05:44.881428 RX DQ/DQS(Engine): PASS
9014 10:05:44.884829 TX OE : PASS
9015 10:05:44.884911 All Pass.
9016 10:05:44.884975
9017 10:05:44.888003 CH 0, Rank 1
9018 10:05:44.888131 SW Impedance : PASS
9019 10:05:44.891383 DUTY Scan : NO K
9020 10:05:44.894841 ZQ Calibration : PASS
9021 10:05:44.894922 Jitter Meter : NO K
9022 10:05:44.898282 CBT Training : PASS
9023 10:05:44.901913 Write leveling : PASS
9024 10:05:44.901994 RX DQS gating : PASS
9025 10:05:44.904438 RX DQ/DQS(RDDQC) : PASS
9026 10:05:44.907947 TX DQ/DQS : PASS
9027 10:05:44.908091 RX DATLAT : PASS
9028 10:05:44.911352 RX DQ/DQS(Engine): PASS
9029 10:05:44.914544 TX OE : PASS
9030 10:05:44.914627 All Pass.
9031 10:05:44.914691
9032 10:05:44.914749 CH 1, Rank 0
9033 10:05:44.918136 SW Impedance : PASS
9034 10:05:44.921509 DUTY Scan : NO K
9035 10:05:44.921591 ZQ Calibration : PASS
9036 10:05:44.924658 Jitter Meter : NO K
9037 10:05:44.927473 CBT Training : PASS
9038 10:05:44.927557 Write leveling : PASS
9039 10:05:44.930807 RX DQS gating : PASS
9040 10:05:44.934042 RX DQ/DQS(RDDQC) : PASS
9041 10:05:44.934125 TX DQ/DQS : PASS
9042 10:05:44.937513 RX DATLAT : PASS
9043 10:05:44.940683 RX DQ/DQS(Engine): PASS
9044 10:05:44.940763 TX OE : PASS
9045 10:05:44.940827 All Pass.
9046 10:05:44.944527
9047 10:05:44.944606 CH 1, Rank 1
9048 10:05:44.947323 SW Impedance : PASS
9049 10:05:44.947403 DUTY Scan : NO K
9050 10:05:44.950559 ZQ Calibration : PASS
9051 10:05:44.950639 Jitter Meter : NO K
9052 10:05:44.954492 CBT Training : PASS
9053 10:05:44.957553 Write leveling : PASS
9054 10:05:44.957633 RX DQS gating : PASS
9055 10:05:44.961049 RX DQ/DQS(RDDQC) : PASS
9056 10:05:44.964167 TX DQ/DQS : PASS
9057 10:05:44.964247 RX DATLAT : PASS
9058 10:05:44.967207 RX DQ/DQS(Engine): PASS
9059 10:05:44.970711 TX OE : PASS
9060 10:05:44.970791 All Pass.
9061 10:05:44.970883
9062 10:05:44.973596 DramC Write-DBI on
9063 10:05:44.973676 PER_BANK_REFRESH: Hybrid Mode
9064 10:05:44.976863 TX_TRACKING: ON
9065 10:05:44.987066 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9066 10:05:44.993567 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9067 10:05:44.999988 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9068 10:05:45.003530 [FAST_K] Save calibration result to emmc
9069 10:05:45.006749 sync common calibartion params.
9070 10:05:45.010740 sync cbt_mode0:1, 1:1
9071 10:05:45.010846 dram_init: ddr_geometry: 2
9072 10:05:45.013386 dram_init: ddr_geometry: 2
9073 10:05:45.016686 dram_init: ddr_geometry: 2
9074 10:05:45.019654 0:dram_rank_size:100000000
9075 10:05:45.019736 1:dram_rank_size:100000000
9076 10:05:45.026611 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9077 10:05:45.029553 DFS_SHUFFLE_HW_MODE: ON
9078 10:05:45.032824 dramc_set_vcore_voltage set vcore to 725000
9079 10:05:45.036289 Read voltage for 1600, 0
9080 10:05:45.036369 Vio18 = 0
9081 10:05:45.036432 Vcore = 725000
9082 10:05:45.039560 Vdram = 0
9083 10:05:45.039640 Vddq = 0
9084 10:05:45.039704 Vmddr = 0
9085 10:05:45.043304 switch to 3200 Mbps bootup
9086 10:05:45.046396 [DramcRunTimeConfig]
9087 10:05:45.046476 PHYPLL
9088 10:05:45.046539 DPM_CONTROL_AFTERK: ON
9089 10:05:45.049632 PER_BANK_REFRESH: ON
9090 10:05:45.052810 REFRESH_OVERHEAD_REDUCTION: ON
9091 10:05:45.052890 CMD_PICG_NEW_MODE: OFF
9092 10:05:45.056145 XRTWTW_NEW_MODE: ON
9093 10:05:45.059203 XRTRTR_NEW_MODE: ON
9094 10:05:45.059284 TX_TRACKING: ON
9095 10:05:45.059348 RDSEL_TRACKING: OFF
9096 10:05:45.062833 DQS Precalculation for DVFS: ON
9097 10:05:45.066410 RX_TRACKING: OFF
9098 10:05:45.066490 HW_GATING DBG: ON
9099 10:05:45.068959 ZQCS_ENABLE_LP4: ON
9100 10:05:45.069039 RX_PICG_NEW_MODE: ON
9101 10:05:45.072824 TX_PICG_NEW_MODE: ON
9102 10:05:45.075645 ENABLE_RX_DCM_DPHY: ON
9103 10:05:45.078940 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9104 10:05:45.079021 DUMMY_READ_FOR_TRACKING: OFF
9105 10:05:45.082877 !!! SPM_CONTROL_AFTERK: OFF
9106 10:05:45.085518 !!! SPM could not control APHY
9107 10:05:45.089280 IMPEDANCE_TRACKING: ON
9108 10:05:45.089360 TEMP_SENSOR: ON
9109 10:05:45.092289 HW_SAVE_FOR_SR: OFF
9110 10:05:45.092369 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9111 10:05:45.099172 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9112 10:05:45.099252 Read ODT Tracking: ON
9113 10:05:45.101986 Refresh Rate DeBounce: ON
9114 10:05:45.105342 DFS_NO_QUEUE_FLUSH: ON
9115 10:05:45.108654 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9116 10:05:45.108734 ENABLE_DFS_RUNTIME_MRW: OFF
9117 10:05:45.112177 DDR_RESERVE_NEW_MODE: ON
9118 10:05:45.115046 MR_CBT_SWITCH_FREQ: ON
9119 10:05:45.115126 =========================
9120 10:05:45.135246 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9121 10:05:45.138542 dram_init: ddr_geometry: 2
9122 10:05:45.156809 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9123 10:05:45.160159 dram_init: dram init end (result: 0)
9124 10:05:45.166318 DRAM-K: Full calibration passed in 24433 msecs
9125 10:05:45.169689 MRC: failed to locate region type 0.
9126 10:05:45.169769 DRAM rank0 size:0x100000000,
9127 10:05:45.173054 DRAM rank1 size=0x100000000
9128 10:05:45.183047 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9129 10:05:45.189507 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9130 10:05:45.195865 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9131 10:05:45.206090 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9132 10:05:45.206172 DRAM rank0 size:0x100000000,
9133 10:05:45.209578 DRAM rank1 size=0x100000000
9134 10:05:45.209658 CBMEM:
9135 10:05:45.212677 IMD: root @ 0xfffff000 254 entries.
9136 10:05:45.216220 IMD: root @ 0xffffec00 62 entries.
9137 10:05:45.219897 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9138 10:05:45.225970 WARNING: RO_VPD is uninitialized or empty.
9139 10:05:45.228891 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9140 10:05:45.236703 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9141 10:05:45.249395 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9142 10:05:45.261014 BS: romstage times (exec / console): total (unknown) / 23962 ms
9143 10:05:45.261095
9144 10:05:45.261159
9145 10:05:45.270573 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9146 10:05:45.273968 ARM64: Exception handlers installed.
9147 10:05:45.277419 ARM64: Testing exception
9148 10:05:45.280702 ARM64: Done test exception
9149 10:05:45.280782 Enumerating buses...
9150 10:05:45.284309 Show all devs... Before device enumeration.
9151 10:05:45.287310 Root Device: enabled 1
9152 10:05:45.290420 CPU_CLUSTER: 0: enabled 1
9153 10:05:45.290500 CPU: 00: enabled 1
9154 10:05:45.293852 Compare with tree...
9155 10:05:45.293931 Root Device: enabled 1
9156 10:05:45.297538 CPU_CLUSTER: 0: enabled 1
9157 10:05:45.300035 CPU: 00: enabled 1
9158 10:05:45.300131 Root Device scanning...
9159 10:05:45.303520 scan_static_bus for Root Device
9160 10:05:45.306717 CPU_CLUSTER: 0 enabled
9161 10:05:45.310470 scan_static_bus for Root Device done
9162 10:05:45.313524 scan_bus: bus Root Device finished in 8 msecs
9163 10:05:45.313604 done
9164 10:05:45.320293 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9165 10:05:45.323578 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9166 10:05:45.329720 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9167 10:05:45.336480 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9168 10:05:45.336561 Allocating resources...
9169 10:05:45.340147 Reading resources...
9170 10:05:45.343758 Root Device read_resources bus 0 link: 0
9171 10:05:45.347279 DRAM rank0 size:0x100000000,
9172 10:05:45.347691 DRAM rank1 size=0x100000000
9173 10:05:45.353425 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9174 10:05:45.353835 CPU: 00 missing read_resources
9175 10:05:45.360228 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9176 10:05:45.363603 Root Device read_resources bus 0 link: 0 done
9177 10:05:45.366520 Done reading resources.
9178 10:05:45.369845 Show resources in subtree (Root Device)...After reading.
9179 10:05:45.373301 Root Device child on link 0 CPU_CLUSTER: 0
9180 10:05:45.376525 CPU_CLUSTER: 0 child on link 0 CPU: 00
9181 10:05:45.385987 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9182 10:05:45.386081 CPU: 00
9183 10:05:45.392977 Root Device assign_resources, bus 0 link: 0
9184 10:05:45.396061 CPU_CLUSTER: 0 missing set_resources
9185 10:05:45.399409 Root Device assign_resources, bus 0 link: 0 done
9186 10:05:45.402315 Done setting resources.
9187 10:05:45.406153 Show resources in subtree (Root Device)...After assigning values.
9188 10:05:45.409066 Root Device child on link 0 CPU_CLUSTER: 0
9189 10:05:45.415327 CPU_CLUSTER: 0 child on link 0 CPU: 00
9190 10:05:45.422269 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9191 10:05:45.425487 CPU: 00
9192 10:05:45.425569 Done allocating resources.
9193 10:05:45.431753 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9194 10:05:45.431862 Enabling resources...
9195 10:05:45.435114 done.
9196 10:05:45.438569 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9197 10:05:45.441706 Initializing devices...
9198 10:05:45.441820 Root Device init
9199 10:05:45.445191 init hardware done!
9200 10:05:45.445305 0x00000018: ctrlr->caps
9201 10:05:45.448271 52.000 MHz: ctrlr->f_max
9202 10:05:45.451776 0.400 MHz: ctrlr->f_min
9203 10:05:45.454969 0x40ff8080: ctrlr->voltages
9204 10:05:45.455073 sclk: 390625
9205 10:05:45.455176 Bus Width = 1
9206 10:05:45.458171 sclk: 390625
9207 10:05:45.458270 Bus Width = 1
9208 10:05:45.461559 Early init status = 3
9209 10:05:45.464856 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9210 10:05:45.468847 in-header: 03 fc 00 00 01 00 00 00
9211 10:05:45.471552 in-data: 00
9212 10:05:45.474645 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9213 10:05:45.480274 in-header: 03 fd 00 00 00 00 00 00
9214 10:05:45.483584 in-data:
9215 10:05:45.486853 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9216 10:05:45.490950 in-header: 03 fc 00 00 01 00 00 00
9217 10:05:45.494420 in-data: 00
9218 10:05:45.497677 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9219 10:05:45.503393 in-header: 03 fd 00 00 00 00 00 00
9220 10:05:45.506307 in-data:
9221 10:05:45.510003 [SSUSB] Setting up USB HOST controller...
9222 10:05:45.513131 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9223 10:05:45.516195 [SSUSB] phy power-on done.
9224 10:05:45.519906 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9225 10:05:45.526003 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9226 10:05:45.530004 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9227 10:05:45.536531 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9228 10:05:45.543061 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9229 10:05:45.549597 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9230 10:05:45.555880 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9231 10:05:45.562640 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9232 10:05:45.565646 SPM: binary array size = 0x9dc
9233 10:05:45.569097 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9234 10:05:45.575831 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9235 10:05:45.582532 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9236 10:05:45.589306 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9237 10:05:45.592344 configure_display: Starting display init
9238 10:05:45.626896 anx7625_power_on_init: Init interface.
9239 10:05:45.629607 anx7625_disable_pd_protocol: Disabled PD feature.
9240 10:05:45.633177 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9241 10:05:45.661118 anx7625_start_dp_work: Secure OCM version=00
9242 10:05:45.664508 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9243 10:05:45.678779 sp_tx_get_edid_block: EDID Block = 1
9244 10:05:45.782060 Extracted contents:
9245 10:05:45.784902 header: 00 ff ff ff ff ff ff 00
9246 10:05:45.787944 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9247 10:05:45.791391 version: 01 04
9248 10:05:45.794896 basic params: 95 1f 11 78 0a
9249 10:05:45.797852 chroma info: 76 90 94 55 54 90 27 21 50 54
9250 10:05:45.801066 established: 00 00 00
9251 10:05:45.808058 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9252 10:05:45.814233 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9253 10:05:45.817987 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9254 10:05:45.824429 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9255 10:05:45.830694 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9256 10:05:45.834082 extensions: 00
9257 10:05:45.834167 checksum: fb
9258 10:05:45.834235
9259 10:05:45.840821 Manufacturer: IVO Model 57d Serial Number 0
9260 10:05:45.840900 Made week 0 of 2020
9261 10:05:45.844010 EDID version: 1.4
9262 10:05:45.844122 Digital display
9263 10:05:45.847402 6 bits per primary color channel
9264 10:05:45.850529 DisplayPort interface
9265 10:05:45.850609 Maximum image size: 31 cm x 17 cm
9266 10:05:45.854115 Gamma: 220%
9267 10:05:45.854195 Check DPMS levels
9268 10:05:45.860449 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9269 10:05:45.864762 First detailed timing is preferred timing
9270 10:05:45.866973 Established timings supported:
9271 10:05:45.867053 Standard timings supported:
9272 10:05:45.870269 Detailed timings
9273 10:05:45.873528 Hex of detail: 383680a07038204018303c0035ae10000019
9274 10:05:45.880288 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9275 10:05:45.883568 0780 0798 07c8 0820 hborder 0
9276 10:05:45.886913 0438 043b 0447 0458 vborder 0
9277 10:05:45.890052 -hsync -vsync
9278 10:05:45.890135 Did detailed timing
9279 10:05:45.896956 Hex of detail: 000000000000000000000000000000000000
9280 10:05:45.900281 Manufacturer-specified data, tag 0
9281 10:05:45.903181 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9282 10:05:45.906512 ASCII string: InfoVision
9283 10:05:45.909919 Hex of detail: 000000fe00523134304e574635205248200a
9284 10:05:45.913329 ASCII string: R140NWF5 RH
9285 10:05:45.913411 Checksum
9286 10:05:45.916651 Checksum: 0xfb (valid)
9287 10:05:45.919983 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9288 10:05:45.923362 DSI data_rate: 832800000 bps
9289 10:05:45.929529 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9290 10:05:45.933186 anx7625_parse_edid: pixelclock(138800).
9291 10:05:45.936515 hactive(1920), hsync(48), hfp(24), hbp(88)
9292 10:05:45.939549 vactive(1080), vsync(12), vfp(3), vbp(17)
9293 10:05:45.942639 anx7625_dsi_config: config dsi.
9294 10:05:45.949535 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9295 10:05:45.963411 anx7625_dsi_config: success to config DSI
9296 10:05:45.966743 anx7625_dp_start: MIPI phy setup OK.
9297 10:05:45.970536 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9298 10:05:45.973359 mtk_ddp_mode_set invalid vrefresh 60
9299 10:05:45.977087 main_disp_path_setup
9300 10:05:45.977155 ovl_layer_smi_id_en
9301 10:05:45.979974 ovl_layer_smi_id_en
9302 10:05:45.980097 ccorr_config
9303 10:05:45.980157 aal_config
9304 10:05:45.983558 gamma_config
9305 10:05:45.983625 postmask_config
9306 10:05:45.986610 dither_config
9307 10:05:45.990279 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9308 10:05:45.996794 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9309 10:05:46.000120 Root Device init finished in 553 msecs
9310 10:05:46.002930 CPU_CLUSTER: 0 init
9311 10:05:46.009763 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9312 10:05:46.016510 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9313 10:05:46.016587 APU_MBOX 0x190000b0 = 0x10001
9314 10:05:46.019611 APU_MBOX 0x190001b0 = 0x10001
9315 10:05:46.022965 APU_MBOX 0x190005b0 = 0x10001
9316 10:05:46.026226 APU_MBOX 0x190006b0 = 0x10001
9317 10:05:46.032484 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9318 10:05:46.042427 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9319 10:05:46.054698 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9320 10:05:46.061631 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9321 10:05:46.073730 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9322 10:05:46.082060 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9323 10:05:46.085745 CPU_CLUSTER: 0 init finished in 81 msecs
9324 10:05:46.088921 Devices initialized
9325 10:05:46.092138 Show all devs... After init.
9326 10:05:46.092218 Root Device: enabled 1
9327 10:05:46.095735 CPU_CLUSTER: 0: enabled 1
9328 10:05:46.098821 CPU: 00: enabled 1
9329 10:05:46.102147 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9330 10:05:46.105303 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9331 10:05:46.108320 ELOG: NV offset 0x57f000 size 0x1000
9332 10:05:46.115179 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9333 10:05:46.122144 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9334 10:05:46.125332 ELOG: Event(17) added with size 13 at 2023-06-10 10:05:46 UTC
9335 10:05:46.131920 out: cmd=0x121: 03 db 21 01 00 00 00 00
9336 10:05:46.135316 in-header: 03 20 00 00 2c 00 00 00
9337 10:05:46.145424 in-data: 3f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9338 10:05:46.151548 ELOG: Event(A1) added with size 10 at 2023-06-10 10:05:46 UTC
9339 10:05:46.158843 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9340 10:05:46.164979 ELOG: Event(A0) added with size 9 at 2023-06-10 10:05:46 UTC
9341 10:05:46.168070 elog_add_boot_reason: Logged dev mode boot
9342 10:05:46.174849 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9343 10:05:46.174933 Finalize devices...
9344 10:05:46.177844 Devices finalized
9345 10:05:46.181454 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9346 10:05:46.184445 Writing coreboot table at 0xffe64000
9347 10:05:46.187837 0. 000000000010a000-0000000000113fff: RAMSTAGE
9348 10:05:46.194604 1. 0000000040000000-00000000400fffff: RAM
9349 10:05:46.197886 2. 0000000040100000-000000004032afff: RAMSTAGE
9350 10:05:46.201052 3. 000000004032b000-00000000545fffff: RAM
9351 10:05:46.205002 4. 0000000054600000-000000005465ffff: BL31
9352 10:05:46.207869 5. 0000000054660000-00000000ffe63fff: RAM
9353 10:05:46.214668 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9354 10:05:46.217954 7. 0000000100000000-000000023fffffff: RAM
9355 10:05:46.220775 Passing 5 GPIOs to payload:
9356 10:05:46.224333 NAME | PORT | POLARITY | VALUE
9357 10:05:46.230988 EC in RW | 0x000000aa | low | undefined
9358 10:05:46.233988 EC interrupt | 0x00000005 | low | undefined
9359 10:05:46.237445 TPM interrupt | 0x000000ab | high | undefined
9360 10:05:46.243922 SD card detect | 0x00000011 | high | undefined
9361 10:05:46.247007 speaker enable | 0x00000093 | high | undefined
9362 10:05:46.250804 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9363 10:05:46.254906 in-header: 03 f9 00 00 02 00 00 00
9364 10:05:46.257800 in-data: 02 00
9365 10:05:46.261557 ADC[4]: Raw value=902216 ID=7
9366 10:05:46.264544 ADC[3]: Raw value=213916 ID=1
9367 10:05:46.264626 RAM Code: 0x71
9368 10:05:46.267960 ADC[6]: Raw value=74630 ID=0
9369 10:05:46.271300 ADC[5]: Raw value=213546 ID=1
9370 10:05:46.271377 SKU Code: 0x1
9371 10:05:46.277995 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a51a
9372 10:05:46.278075 coreboot table: 964 bytes.
9373 10:05:46.281146 IMD ROOT 0. 0xfffff000 0x00001000
9374 10:05:46.284091 IMD SMALL 1. 0xffffe000 0x00001000
9375 10:05:46.287500 RO MCACHE 2. 0xffffc000 0x00001104
9376 10:05:46.290787 CONSOLE 3. 0xfff7c000 0x00080000
9377 10:05:46.294085 FMAP 4. 0xfff7b000 0x00000452
9378 10:05:46.297476 TIME STAMP 5. 0xfff7a000 0x00000910
9379 10:05:46.300444 VBOOT WORK 6. 0xfff66000 0x00014000
9380 10:05:46.303894 RAMOOPS 7. 0xffe66000 0x00100000
9381 10:05:46.307068 COREBOOT 8. 0xffe64000 0x00002000
9382 10:05:46.310908 IMD small region:
9383 10:05:46.313962 IMD ROOT 0. 0xffffec00 0x00000400
9384 10:05:46.317193 VPD 1. 0xffffeba0 0x0000004c
9385 10:05:46.320601 MMC STATUS 2. 0xffffeb80 0x00000004
9386 10:05:46.326904 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9387 10:05:46.326986 Probing TPM: done!
9388 10:05:46.334176 Connected to device vid:did:rid of 1ae0:0028:00
9389 10:05:46.340435 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9390 10:05:46.343940 Initialized TPM device CR50 revision 0
9391 10:05:46.347603 Checking cr50 for pending updates
9392 10:05:46.352771 Reading cr50 TPM mode
9393 10:05:46.361396 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9394 10:05:46.368249 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9395 10:05:46.408334 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9396 10:05:46.411504 Checking segment from ROM address 0x40100000
9397 10:05:46.415183 Checking segment from ROM address 0x4010001c
9398 10:05:46.421770 Loading segment from ROM address 0x40100000
9399 10:05:46.421854 code (compression=0)
9400 10:05:46.431260 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9401 10:05:46.438484 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9402 10:05:46.438566 it's not compressed!
9403 10:05:46.444464 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9404 10:05:46.451347 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9405 10:05:46.468712 Loading segment from ROM address 0x4010001c
9406 10:05:46.468795 Entry Point 0x80000000
9407 10:05:46.472279 Loaded segments
9408 10:05:46.475345 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9409 10:05:46.482085 Jumping to boot code at 0x80000000(0xffe64000)
9410 10:05:46.488853 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9411 10:05:46.495456 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9412 10:05:46.502910 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9413 10:05:46.506196 Checking segment from ROM address 0x40100000
9414 10:05:46.509762 Checking segment from ROM address 0x4010001c
9415 10:05:46.516297 Loading segment from ROM address 0x40100000
9416 10:05:46.516378 code (compression=1)
9417 10:05:46.523135 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9418 10:05:46.532379 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9419 10:05:46.532462 using LZMA
9420 10:05:46.541508 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9421 10:05:46.548439 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9422 10:05:46.551094 Loading segment from ROM address 0x4010001c
9423 10:05:46.551175 Entry Point 0x54601000
9424 10:05:46.554950 Loaded segments
9425 10:05:46.558156 NOTICE: MT8192 bl31_setup
9426 10:05:46.564793 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9427 10:05:46.568868 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9428 10:05:46.571452 WARNING: region 0:
9429 10:05:46.575330 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9430 10:05:46.575411 WARNING: region 1:
9431 10:05:46.581498 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9432 10:05:46.584759 WARNING: region 2:
9433 10:05:46.587929 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9434 10:05:46.591665 WARNING: region 3:
9435 10:05:46.595217 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9436 10:05:46.598117 WARNING: region 4:
9437 10:05:46.604802 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9438 10:05:46.604884 WARNING: region 5:
9439 10:05:46.608291 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9440 10:05:46.611288 WARNING: region 6:
9441 10:05:46.614660 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9442 10:05:46.618143 WARNING: region 7:
9443 10:05:46.621405 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9444 10:05:46.627743 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9445 10:05:46.631178 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9446 10:05:46.634642 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9447 10:05:46.640929 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9448 10:05:46.644275 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9449 10:05:46.651402 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9450 10:05:46.654645 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9451 10:05:46.658022 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9452 10:05:46.664688 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9453 10:05:46.667697 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9454 10:05:46.671239 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9455 10:05:46.677761 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9456 10:05:46.681241 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9457 10:05:46.687827 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9458 10:05:46.690492 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9459 10:05:46.694009 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9460 10:05:46.701009 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9461 10:05:46.703979 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9462 10:05:46.711497 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9463 10:05:46.714318 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9464 10:05:46.717193 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9465 10:05:46.723735 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9466 10:05:46.727102 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9467 10:05:46.730556 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9468 10:05:46.737230 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9469 10:05:46.740468 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9470 10:05:46.747381 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9471 10:05:46.750390 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9472 10:05:46.756967 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9473 10:05:46.760354 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9474 10:05:46.763825 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9475 10:05:46.770745 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9476 10:05:46.773700 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9477 10:05:46.776940 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9478 10:05:46.780215 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9479 10:05:46.786977 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9480 10:05:46.790352 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9481 10:05:46.793541 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9482 10:05:46.796926 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9483 10:05:46.803457 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9484 10:05:46.807039 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9485 10:05:46.810180 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9486 10:05:46.813449 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9487 10:05:46.819908 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9488 10:05:46.823307 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9489 10:05:46.826660 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9490 10:05:46.833199 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9491 10:05:46.836824 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9492 10:05:46.839984 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9493 10:05:46.846411 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9494 10:05:46.849717 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9495 10:05:46.856436 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9496 10:05:46.859985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9497 10:05:46.862777 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9498 10:05:46.869706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9499 10:05:46.872778 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9500 10:05:46.879750 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9501 10:05:46.883108 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9502 10:05:46.889676 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9503 10:05:46.893043 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9504 10:05:46.899583 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9505 10:05:46.902655 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9506 10:05:46.906253 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9507 10:05:46.912971 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9508 10:05:46.915984 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9509 10:05:46.922686 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9510 10:05:46.926135 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9511 10:05:46.932603 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9512 10:05:46.935880 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9513 10:05:46.939415 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9514 10:05:46.946275 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9515 10:05:46.949173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9516 10:05:46.956060 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9517 10:05:46.959035 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9518 10:05:46.966195 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9519 10:05:46.969427 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9520 10:05:46.975996 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9521 10:05:46.978926 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9522 10:05:46.982681 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9523 10:05:46.988906 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9524 10:05:46.992340 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9525 10:05:46.998811 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9526 10:05:47.002381 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9527 10:05:47.008651 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9528 10:05:47.011970 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9529 10:05:47.018765 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9530 10:05:47.021995 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9531 10:05:47.025042 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9532 10:05:47.031897 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9533 10:05:47.034775 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9534 10:05:47.041801 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9535 10:05:47.044776 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9536 10:05:47.051396 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9537 10:05:47.055034 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9538 10:05:47.062074 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9539 10:05:47.064961 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9540 10:05:47.068355 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9541 10:05:47.071792 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9542 10:05:47.078675 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9543 10:05:47.081378 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9544 10:05:47.085461 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9545 10:05:47.091799 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9546 10:05:47.094804 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9547 10:05:47.101970 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9548 10:05:47.105005 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9549 10:05:47.108181 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9550 10:05:47.114951 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9551 10:05:47.117947 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9552 10:05:47.124503 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9553 10:05:47.127929 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9554 10:05:47.131341 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9555 10:05:47.137799 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9556 10:05:47.141102 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9557 10:05:47.148147 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9558 10:05:47.151035 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9559 10:05:47.154474 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9560 10:05:47.157781 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9561 10:05:47.164325 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9562 10:05:47.167543 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9563 10:05:47.171499 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9564 10:05:47.177924 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9565 10:05:47.181129 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9566 10:05:47.184355 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9567 10:05:47.187710 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9568 10:05:47.194277 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9569 10:05:47.197658 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9570 10:05:47.204234 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9571 10:05:47.207363 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9572 10:05:47.214306 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9573 10:05:47.217522 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9574 10:05:47.220490 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9575 10:05:47.227497 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9576 10:05:47.230668 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9577 10:05:47.233977 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9578 10:05:47.240842 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9579 10:05:47.243883 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9580 10:05:47.250693 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9581 10:05:47.253912 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9582 10:05:47.257500 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9583 10:05:47.264350 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9584 10:05:47.266954 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9585 10:05:47.273781 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9586 10:05:47.276846 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9587 10:05:47.280561 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9588 10:05:47.286744 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9589 10:05:47.290414 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9590 10:05:47.297123 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9591 10:05:47.300451 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9592 10:05:47.303430 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9593 10:05:47.310402 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9594 10:05:47.313902 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9595 10:05:47.320329 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9596 10:05:47.323349 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9597 10:05:47.326653 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9598 10:05:47.333363 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9599 10:05:47.336779 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9600 10:05:47.340207 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9601 10:05:47.346614 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9602 10:05:47.349950 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9603 10:05:47.356661 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9604 10:05:47.359703 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9605 10:05:47.363273 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9606 10:05:47.369932 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9607 10:05:47.373287 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9608 10:05:47.379479 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9609 10:05:47.383266 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9610 10:05:47.386037 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9611 10:05:47.392675 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9612 10:05:47.396818 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9613 10:05:47.402773 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9614 10:05:47.406030 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9615 10:05:47.412358 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9616 10:05:47.415624 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9617 10:05:47.419471 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9618 10:05:47.425829 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9619 10:05:47.429428 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9620 10:05:47.432540 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9621 10:05:47.439151 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9622 10:05:47.442077 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9623 10:05:47.449091 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9624 10:05:47.452232 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9625 10:05:47.458487 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9626 10:05:47.461781 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9627 10:05:47.464927 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9628 10:05:47.471847 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9629 10:05:47.475129 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9630 10:05:47.478618 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9631 10:05:47.484793 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9632 10:05:47.488345 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9633 10:05:47.495064 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9634 10:05:47.498387 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9635 10:05:47.504667 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9636 10:05:47.508018 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9637 10:05:47.514590 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9638 10:05:47.517915 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9639 10:05:47.520903 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9640 10:05:47.527468 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9641 10:05:47.530811 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9642 10:05:47.537584 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9643 10:05:47.540851 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9644 10:05:47.547426 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9645 10:05:47.550654 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9646 10:05:47.553729 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9647 10:05:47.560787 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9648 10:05:47.564554 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9649 10:05:47.570437 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9650 10:05:47.573674 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9651 10:05:47.580147 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9652 10:05:47.583598 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9653 10:05:47.586735 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9654 10:05:47.593458 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9655 10:05:47.597149 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9656 10:05:47.603332 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9657 10:05:47.606592 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9658 10:05:47.613461 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9659 10:05:47.616270 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9660 10:05:47.620180 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9661 10:05:47.626279 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9662 10:05:47.629632 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9663 10:05:47.636500 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9664 10:05:47.639842 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9665 10:05:47.646034 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9666 10:05:47.649387 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9667 10:05:47.652560 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9668 10:05:47.659050 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9669 10:05:47.662294 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9670 10:05:47.669018 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9671 10:05:47.672501 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9672 10:05:47.678699 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9673 10:05:47.682171 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9674 10:05:47.685166 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9675 10:05:47.689156 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9676 10:05:47.692042 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9677 10:05:47.698507 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9678 10:05:47.702067 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9679 10:05:47.708413 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9680 10:05:47.711782 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9681 10:05:47.715353 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9682 10:05:47.721698 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9683 10:05:47.724734 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9684 10:05:47.728409 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9685 10:05:47.734942 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9686 10:05:47.738286 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9687 10:05:47.742198 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9688 10:05:47.748093 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9689 10:05:47.751636 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9690 10:05:47.757702 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9691 10:05:47.761113 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9692 10:05:47.764608 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9693 10:05:47.771154 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9694 10:05:47.774305 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9695 10:05:47.780972 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9696 10:05:47.783992 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9697 10:05:47.787496 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9698 10:05:47.794232 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9699 10:05:47.797573 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9700 10:05:47.800878 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9701 10:05:47.807304 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9702 10:05:47.811069 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9703 10:05:47.817429 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9704 10:05:47.820313 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9705 10:05:47.823792 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9706 10:05:47.830376 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9707 10:05:47.834004 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9708 10:05:47.837289 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9709 10:05:47.843575 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9710 10:05:47.846816 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9711 10:05:47.853871 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9712 10:05:47.856810 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9713 10:05:47.860120 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9714 10:05:47.863357 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9715 10:05:47.869834 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9716 10:05:47.873496 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9717 10:05:47.876594 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9718 10:05:47.879774 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9719 10:05:47.886469 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9720 10:05:47.890100 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9721 10:05:47.893354 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9722 10:05:47.896587 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9723 10:05:47.903044 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9724 10:05:47.905929 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9725 10:05:47.909899 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9726 10:05:47.916354 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9727 10:05:47.919747 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9728 10:05:47.925708 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9729 10:05:47.928855 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9730 10:05:47.932506 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9731 10:05:47.938827 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9732 10:05:47.942153 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9733 10:05:47.949124 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9734 10:05:47.952276 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9735 10:05:47.958616 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9736 10:05:47.962018 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9737 10:05:47.965361 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9738 10:05:47.971729 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9739 10:05:47.974794 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9740 10:05:47.981757 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9741 10:05:47.985062 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9742 10:05:47.988438 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9743 10:05:47.994983 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9744 10:05:47.997943 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9745 10:05:48.004647 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9746 10:05:48.008215 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9747 10:05:48.014455 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9748 10:05:48.017694 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9749 10:05:48.021390 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9750 10:05:48.027686 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9751 10:05:48.031219 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9752 10:05:48.037680 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9753 10:05:48.040636 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9754 10:05:48.047482 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9755 10:05:48.050971 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9756 10:05:48.054431 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9757 10:05:48.060435 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9758 10:05:48.064195 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9759 10:05:48.070651 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9760 10:05:48.074124 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9761 10:05:48.077342 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9762 10:05:48.083933 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9763 10:05:48.087115 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9764 10:05:48.093571 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9765 10:05:48.096931 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9766 10:05:48.103329 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9767 10:05:48.106936 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9768 10:05:48.110376 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9769 10:05:48.117052 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9770 10:05:48.120648 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9771 10:05:48.127240 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9772 10:05:48.130006 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9773 10:05:48.133243 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9774 10:05:48.139561 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9775 10:05:48.143026 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9776 10:05:48.149616 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9777 10:05:48.153095 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9778 10:05:48.159351 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9779 10:05:48.162860 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9780 10:05:48.169612 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9781 10:05:48.172781 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9782 10:05:48.175861 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9783 10:05:48.182493 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9784 10:05:48.185592 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9785 10:05:48.192528 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9786 10:05:48.195793 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9787 10:05:48.199074 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9788 10:05:48.205856 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9789 10:05:48.209063 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9790 10:05:48.215430 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9791 10:05:48.218976 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9792 10:05:48.225588 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9793 10:05:48.228394 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9794 10:05:48.232214 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9795 10:05:48.238407 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9796 10:05:48.241696 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9797 10:05:48.248304 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9798 10:05:48.251423 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9799 10:05:48.254867 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9800 10:05:48.261508 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9801 10:05:48.264958 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9802 10:05:48.271190 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9803 10:05:48.274557 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9804 10:05:48.281489 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9805 10:05:48.284364 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9806 10:05:48.291369 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9807 10:05:48.294390 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9808 10:05:48.300916 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9809 10:05:48.304365 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9810 10:05:48.307667 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9811 10:05:48.314006 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9812 10:05:48.317148 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9813 10:05:48.323942 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9814 10:05:48.327054 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9815 10:05:48.333560 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9816 10:05:48.337722 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9817 10:05:48.343695 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9818 10:05:48.347284 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9819 10:05:48.353261 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9820 10:05:48.356594 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9821 10:05:48.359982 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9822 10:05:48.366679 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9823 10:05:48.369687 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9824 10:05:48.376338 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9825 10:05:48.379950 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9826 10:05:48.386669 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9827 10:05:48.389693 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9828 10:05:48.396378 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9829 10:05:48.399456 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9830 10:05:48.402606 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9831 10:05:48.409645 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9832 10:05:48.412860 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9833 10:05:48.419467 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9834 10:05:48.422741 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9835 10:05:48.429022 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9836 10:05:48.432548 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9837 10:05:48.435624 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9838 10:05:48.442296 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9839 10:05:48.445572 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9840 10:05:48.451872 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9841 10:05:48.455344 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9842 10:05:48.461666 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9843 10:05:48.465191 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9844 10:05:48.471722 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9845 10:05:48.475367 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9846 10:05:48.478550 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9847 10:05:48.484791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9848 10:05:48.488070 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9849 10:05:48.494663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9850 10:05:48.498175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9851 10:05:48.505061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9852 10:05:48.508228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9853 10:05:48.514575 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9854 10:05:48.518111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9855 10:05:48.524476 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9856 10:05:48.527660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9857 10:05:48.534748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9858 10:05:48.538024 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9859 10:05:48.544220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9860 10:05:48.547332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9861 10:05:48.554116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9862 10:05:48.557101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9863 10:05:48.563677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9864 10:05:48.566912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9865 10:05:48.573867 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9866 10:05:48.576793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9867 10:05:48.583803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9868 10:05:48.586686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9869 10:05:48.593406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9870 10:05:48.596889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9871 10:05:48.603099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9872 10:05:48.606794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9873 10:05:48.613055 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9874 10:05:48.616389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9875 10:05:48.623163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9876 10:05:48.626357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9877 10:05:48.633067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9878 10:05:48.635981 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9879 10:05:48.639254 INFO: [APUAPC] vio 0
9880 10:05:48.642605 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9881 10:05:48.649315 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9882 10:05:48.652615 INFO: [APUAPC] D0_APC_0: 0x400510
9883 10:05:48.655878 INFO: [APUAPC] D0_APC_1: 0x0
9884 10:05:48.659417 INFO: [APUAPC] D0_APC_2: 0x1540
9885 10:05:48.659498 INFO: [APUAPC] D0_APC_3: 0x0
9886 10:05:48.665857 INFO: [APUAPC] D1_APC_0: 0xffffffff
9887 10:05:48.668954 INFO: [APUAPC] D1_APC_1: 0xffffffff
9888 10:05:48.672089 INFO: [APUAPC] D1_APC_2: 0x3fffff
9889 10:05:48.672164 INFO: [APUAPC] D1_APC_3: 0x0
9890 10:05:48.678936 INFO: [APUAPC] D2_APC_0: 0xffffffff
9891 10:05:48.682328 INFO: [APUAPC] D2_APC_1: 0xffffffff
9892 10:05:48.685189 INFO: [APUAPC] D2_APC_2: 0x3fffff
9893 10:05:48.685268 INFO: [APUAPC] D2_APC_3: 0x0
9894 10:05:48.691759 INFO: [APUAPC] D3_APC_0: 0xffffffff
9895 10:05:48.695392 INFO: [APUAPC] D3_APC_1: 0xffffffff
9896 10:05:48.698893 INFO: [APUAPC] D3_APC_2: 0x3fffff
9897 10:05:48.698976 INFO: [APUAPC] D3_APC_3: 0x0
9898 10:05:48.702029 INFO: [APUAPC] D4_APC_0: 0xffffffff
9899 10:05:48.708273 INFO: [APUAPC] D4_APC_1: 0xffffffff
9900 10:05:48.711845 INFO: [APUAPC] D4_APC_2: 0x3fffff
9901 10:05:48.711927 INFO: [APUAPC] D4_APC_3: 0x0
9902 10:05:48.715156 INFO: [APUAPC] D5_APC_0: 0xffffffff
9903 10:05:48.718311 INFO: [APUAPC] D5_APC_1: 0xffffffff
9904 10:05:48.721369 INFO: [APUAPC] D5_APC_2: 0x3fffff
9905 10:05:48.725001 INFO: [APUAPC] D5_APC_3: 0x0
9906 10:05:48.728235 INFO: [APUAPC] D6_APC_0: 0xffffffff
9907 10:05:48.731417 INFO: [APUAPC] D6_APC_1: 0xffffffff
9908 10:05:48.734716 INFO: [APUAPC] D6_APC_2: 0x3fffff
9909 10:05:48.737991 INFO: [APUAPC] D6_APC_3: 0x0
9910 10:05:48.741508 INFO: [APUAPC] D7_APC_0: 0xffffffff
9911 10:05:48.744956 INFO: [APUAPC] D7_APC_1: 0xffffffff
9912 10:05:48.747929 INFO: [APUAPC] D7_APC_2: 0x3fffff
9913 10:05:48.751246 INFO: [APUAPC] D7_APC_3: 0x0
9914 10:05:48.754844 INFO: [APUAPC] D8_APC_0: 0xffffffff
9915 10:05:48.757662 INFO: [APUAPC] D8_APC_1: 0xffffffff
9916 10:05:48.761231 INFO: [APUAPC] D8_APC_2: 0x3fffff
9917 10:05:48.764672 INFO: [APUAPC] D8_APC_3: 0x0
9918 10:05:48.767316 INFO: [APUAPC] D9_APC_0: 0xffffffff
9919 10:05:48.770931 INFO: [APUAPC] D9_APC_1: 0xffffffff
9920 10:05:48.774161 INFO: [APUAPC] D9_APC_2: 0x3fffff
9921 10:05:48.777530 INFO: [APUAPC] D9_APC_3: 0x0
9922 10:05:48.780406 INFO: [APUAPC] D10_APC_0: 0xffffffff
9923 10:05:48.784052 INFO: [APUAPC] D10_APC_1: 0xffffffff
9924 10:05:48.787108 INFO: [APUAPC] D10_APC_2: 0x3fffff
9925 10:05:48.790538 INFO: [APUAPC] D10_APC_3: 0x0
9926 10:05:48.793746 INFO: [APUAPC] D11_APC_0: 0xffffffff
9927 10:05:48.797064 INFO: [APUAPC] D11_APC_1: 0xffffffff
9928 10:05:48.800670 INFO: [APUAPC] D11_APC_2: 0x3fffff
9929 10:05:48.803674 INFO: [APUAPC] D11_APC_3: 0x0
9930 10:05:48.806820 INFO: [APUAPC] D12_APC_0: 0xffffffff
9931 10:05:48.810033 INFO: [APUAPC] D12_APC_1: 0xffffffff
9932 10:05:48.813772 INFO: [APUAPC] D12_APC_2: 0x3fffff
9933 10:05:48.817133 INFO: [APUAPC] D12_APC_3: 0x0
9934 10:05:48.820165 INFO: [APUAPC] D13_APC_0: 0xffffffff
9935 10:05:48.823762 INFO: [APUAPC] D13_APC_1: 0xffffffff
9936 10:05:48.826963 INFO: [APUAPC] D13_APC_2: 0x3fffff
9937 10:05:48.830071 INFO: [APUAPC] D13_APC_3: 0x0
9938 10:05:48.833140 INFO: [APUAPC] D14_APC_0: 0xffffffff
9939 10:05:48.839722 INFO: [APUAPC] D14_APC_1: 0xffffffff
9940 10:05:48.843612 INFO: [APUAPC] D14_APC_2: 0x3fffff
9941 10:05:48.843714 INFO: [APUAPC] D14_APC_3: 0x0
9942 10:05:48.850109 INFO: [APUAPC] D15_APC_0: 0xffffffff
9943 10:05:48.852920 INFO: [APUAPC] D15_APC_1: 0xffffffff
9944 10:05:48.856289 INFO: [APUAPC] D15_APC_2: 0x3fffff
9945 10:05:48.859878 INFO: [APUAPC] D15_APC_3: 0x0
9946 10:05:48.859952 INFO: [APUAPC] APC_CON: 0x4
9947 10:05:48.863155 INFO: [NOCDAPC] D0_APC_0: 0x0
9948 10:05:48.866497 INFO: [NOCDAPC] D0_APC_1: 0x0
9949 10:05:48.869370 INFO: [NOCDAPC] D1_APC_0: 0x0
9950 10:05:48.872667 INFO: [NOCDAPC] D1_APC_1: 0xfff
9951 10:05:48.876021 INFO: [NOCDAPC] D2_APC_0: 0x0
9952 10:05:48.879349 INFO: [NOCDAPC] D2_APC_1: 0xfff
9953 10:05:48.882861 INFO: [NOCDAPC] D3_APC_0: 0x0
9954 10:05:48.886069 INFO: [NOCDAPC] D3_APC_1: 0xfff
9955 10:05:48.889351 INFO: [NOCDAPC] D4_APC_0: 0x0
9956 10:05:48.889431 INFO: [NOCDAPC] D4_APC_1: 0xfff
9957 10:05:48.892599 INFO: [NOCDAPC] D5_APC_0: 0x0
9958 10:05:48.895886 INFO: [NOCDAPC] D5_APC_1: 0xfff
9959 10:05:48.898888 INFO: [NOCDAPC] D6_APC_0: 0x0
9960 10:05:48.902324 INFO: [NOCDAPC] D6_APC_1: 0xfff
9961 10:05:48.905896 INFO: [NOCDAPC] D7_APC_0: 0x0
9962 10:05:48.909283 INFO: [NOCDAPC] D7_APC_1: 0xfff
9963 10:05:48.912513 INFO: [NOCDAPC] D8_APC_0: 0x0
9964 10:05:48.915386 INFO: [NOCDAPC] D8_APC_1: 0xfff
9965 10:05:48.919047 INFO: [NOCDAPC] D9_APC_0: 0x0
9966 10:05:48.922156 INFO: [NOCDAPC] D9_APC_1: 0xfff
9967 10:05:48.925605 INFO: [NOCDAPC] D10_APC_0: 0x0
9968 10:05:48.928545 INFO: [NOCDAPC] D10_APC_1: 0xfff
9969 10:05:48.928626 INFO: [NOCDAPC] D11_APC_0: 0x0
9970 10:05:48.931958 INFO: [NOCDAPC] D11_APC_1: 0xfff
9971 10:05:48.935347 INFO: [NOCDAPC] D12_APC_0: 0x0
9972 10:05:48.938501 INFO: [NOCDAPC] D12_APC_1: 0xfff
9973 10:05:48.941775 INFO: [NOCDAPC] D13_APC_0: 0x0
9974 10:05:48.945251 INFO: [NOCDAPC] D13_APC_1: 0xfff
9975 10:05:48.948497 INFO: [NOCDAPC] D14_APC_0: 0x0
9976 10:05:48.951870 INFO: [NOCDAPC] D14_APC_1: 0xfff
9977 10:05:48.955089 INFO: [NOCDAPC] D15_APC_0: 0x0
9978 10:05:48.957991 INFO: [NOCDAPC] D15_APC_1: 0xfff
9979 10:05:48.961608 INFO: [NOCDAPC] APC_CON: 0x4
9980 10:05:48.964983 INFO: [APUAPC] set_apusys_apc done
9981 10:05:48.968353 INFO: [DEVAPC] devapc_init done
9982 10:05:48.971301 INFO: GICv3 without legacy support detected.
9983 10:05:48.974650 INFO: ARM GICv3 driver initialized in EL3
9984 10:05:48.977961 INFO: Maximum SPI INTID supported: 639
9985 10:05:48.984650 INFO: BL31: Initializing runtime services
9986 10:05:48.987552 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9987 10:05:48.991063 INFO: SPM: enable CPC mode
9988 10:05:48.997756 INFO: mcdi ready for mcusys-off-idle and system suspend
9989 10:05:49.000794 INFO: BL31: Preparing for EL3 exit to normal world
9990 10:05:49.004036 INFO: Entry point address = 0x80000000
9991 10:05:49.007345 INFO: SPSR = 0x8
9992 10:05:49.013017
9993 10:05:49.013106
9994 10:05:49.013171
9995 10:05:49.016618 Starting depthcharge on Spherion...
9996 10:05:49.016724
9997 10:05:49.016818 Wipe memory regions:
9998 10:05:49.016911
9999 10:05:49.017718 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10000 10:05:49.017847 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10001 10:05:49.017964 Setting prompt string to ['asurada:']
10002 10:05:49.018070 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10003 10:05:49.019957 [0x00000040000000, 0x00000054600000)
10004 10:05:49.142130
10005 10:05:49.142262 [0x00000054660000, 0x00000080000000)
10006 10:05:49.402542
10007 10:05:49.402691 [0x000000821a7280, 0x000000ffe64000)
10008 10:05:50.147387
10009 10:05:50.147524 [0x00000100000000, 0x00000240000000)
10010 10:05:52.037716
10011 10:05:52.040682 Initializing XHCI USB controller at 0x11200000.
10012 10:05:53.079714
10013 10:05:53.082716 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10014 10:05:53.082852
10015 10:05:53.082944
10016 10:05:53.083037
10017 10:05:53.083412 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10019 10:05:53.183833 asurada: tftpboot 192.168.201.1 10670700/tftp-deploy-0exqgs1y/kernel/image.itb 10670700/tftp-deploy-0exqgs1y/kernel/cmdline
10020 10:05:53.184020 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10021 10:05:53.184130 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10022 10:05:53.188227 tftpboot 192.168.201.1 10670700/tftp-deploy-0exqgs1y/kernel/image.ittp-deploy-0exqgs1y/kernel/cmdline
10023 10:05:53.188317
10024 10:05:53.188383 Waiting for link
10025 10:05:53.349026
10026 10:05:53.349185 R8152: Initializing
10027 10:05:53.349281
10028 10:05:53.351980 Version 6 (ocp_data = 5c30)
10029 10:05:53.352092
10030 10:05:53.355603 R8152: Done initializing
10031 10:05:53.355695
10032 10:05:53.355761 Adding net device
10033 10:05:55.399421
10034 10:05:55.399571 done.
10035 10:05:55.399640
10036 10:05:55.399718 MAC: 00:24:32:30:7c:7b
10037 10:05:55.399793
10038 10:05:55.403008 Sending DHCP discover... done.
10039 10:05:55.403083
10040 10:05:55.405758 Waiting for reply... done.
10041 10:05:55.405838
10042 10:05:55.409288 Sending DHCP request... done.
10043 10:05:55.409362
10044 10:05:55.409423 Waiting for reply... done.
10045 10:05:55.409482
10046 10:05:55.412563 My ip is 192.168.201.14
10047 10:05:55.412632
10048 10:05:55.416263 The DHCP server ip is 192.168.201.1
10049 10:05:55.416333
10050 10:05:55.419047 TFTP server IP predefined by user: 192.168.201.1
10051 10:05:55.419117
10052 10:05:55.425821 Bootfile predefined by user: 10670700/tftp-deploy-0exqgs1y/kernel/image.itb
10053 10:05:55.425920
10054 10:05:55.429226 Sending tftp read request... done.
10055 10:05:55.429322
10056 10:05:55.432548 Waiting for the transfer...
10057 10:05:55.432659
10058 10:05:55.956467 00000000 ################################################################
10059 10:05:55.956615
10060 10:05:56.481743 00080000 ################################################################
10061 10:05:56.481888
10062 10:05:57.011702 00100000 ################################################################
10063 10:05:57.011872
10064 10:05:57.525246 00180000 ################################################################
10065 10:05:57.525386
10066 10:05:58.059362 00200000 ################################################################
10067 10:05:58.059513
10068 10:05:58.592888 00280000 ################################################################
10069 10:05:58.593034
10070 10:05:59.124644 00300000 ################################################################
10071 10:05:59.124791
10072 10:05:59.657148 00380000 ################################################################
10073 10:05:59.657332
10074 10:06:00.172212 00400000 ################################################################
10075 10:06:00.172398
10076 10:06:00.689964 00480000 ################################################################
10077 10:06:00.690119
10078 10:06:01.221128 00500000 ################################################################
10079 10:06:01.221264
10080 10:06:01.749284 00580000 ################################################################
10081 10:06:01.749469
10082 10:06:02.279322 00600000 ################################################################
10083 10:06:02.279512
10084 10:06:02.809963 00680000 ################################################################
10085 10:06:02.810152
10086 10:06:03.343040 00700000 ################################################################
10087 10:06:03.343227
10088 10:06:03.881137 00780000 ################################################################
10089 10:06:03.881314
10090 10:06:04.408267 00800000 ################################################################
10091 10:06:04.408473
10092 10:06:04.933055 00880000 ################################################################
10093 10:06:04.933232
10094 10:06:05.463310 00900000 ################################################################
10095 10:06:05.463496
10096 10:06:05.998300 00980000 ################################################################
10097 10:06:05.998474
10098 10:06:06.527097 00a00000 ################################################################
10099 10:06:06.527247
10100 10:06:07.077119 00a80000 ################################################################
10101 10:06:07.077273
10102 10:06:07.612885 00b00000 ################################################################
10103 10:06:07.613031
10104 10:06:08.143031 00b80000 ################################################################
10105 10:06:08.143202
10106 10:06:08.669186 00c00000 ################################################################
10107 10:06:08.669335
10108 10:06:09.219033 00c80000 ################################################################
10109 10:06:09.219190
10110 10:06:09.748012 00d00000 ################################################################
10111 10:06:09.748164
10112 10:06:10.282956 00d80000 ################################################################
10113 10:06:10.283112
10114 10:06:10.820180 00e00000 ################################################################
10115 10:06:10.820334
10116 10:06:11.364651 00e80000 ################################################################
10117 10:06:11.364811
10118 10:06:11.905649 00f00000 ################################################################
10119 10:06:11.905839
10120 10:06:12.435766 00f80000 ################################################################
10121 10:06:12.435942
10122 10:06:12.969470 01000000 ################################################################
10123 10:06:12.969613
10124 10:06:13.494562 01080000 ################################################################
10125 10:06:13.494745
10126 10:06:14.023692 01100000 ################################################################
10127 10:06:14.023848
10128 10:06:14.565490 01180000 ################################################################
10129 10:06:14.565655
10130 10:06:15.110098 01200000 ################################################################
10131 10:06:15.110255
10132 10:06:15.637739 01280000 ################################################################
10133 10:06:15.637889
10134 10:06:16.163478 01300000 ################################################################
10135 10:06:16.163653
10136 10:06:16.693246 01380000 ################################################################
10137 10:06:16.693393
10138 10:06:17.220793 01400000 ################################################################
10139 10:06:17.220938
10140 10:06:17.760171 01480000 ################################################################
10141 10:06:17.760330
10142 10:06:18.304433 01500000 ################################################################
10143 10:06:18.304602
10144 10:06:18.842399 01580000 ################################################################
10145 10:06:18.842571
10146 10:06:19.387471 01600000 ################################################################
10147 10:06:19.387651
10148 10:06:19.914169 01680000 ################################################################
10149 10:06:19.914312
10150 10:06:20.446584 01700000 ################################################################
10151 10:06:20.446769
10152 10:06:20.971855 01780000 ################################################################
10153 10:06:20.972045
10154 10:06:21.498744 01800000 ################################################################
10155 10:06:21.498919
10156 10:06:22.022156 01880000 ################################################################
10157 10:06:22.022315
10158 10:06:22.547586 01900000 ################################################################
10159 10:06:22.547761
10160 10:06:23.072538 01980000 ################################################################
10161 10:06:23.072690
10162 10:06:23.601290 01a00000 ################################################################
10163 10:06:23.601466
10164 10:06:24.125724 01a80000 ################################################################
10165 10:06:24.125884
10166 10:06:24.650727 01b00000 ################################################################
10167 10:06:24.650913
10168 10:06:25.175305 01b80000 ################################################################
10169 10:06:25.175461
10170 10:06:25.712173 01c00000 ################################################################
10171 10:06:25.712359
10172 10:06:26.238551 01c80000 ################################################################
10173 10:06:26.238754
10174 10:06:26.763003 01d00000 ################################################################
10175 10:06:26.763165
10176 10:06:27.303372 01d80000 ################################################################
10177 10:06:27.303533
10178 10:06:27.831609 01e00000 ################################################################
10179 10:06:27.831798
10180 10:06:28.352649 01e80000 ################################################################
10181 10:06:28.352841
10182 10:06:28.879881 01f00000 ################################################################
10183 10:06:28.880082
10184 10:06:29.422724 01f80000 ################################################################
10185 10:06:29.422883
10186 10:06:29.970027 02000000 ################################################################
10187 10:06:29.970188
10188 10:06:30.508433 02080000 ################################################################
10189 10:06:30.508588
10190 10:06:31.041288 02100000 ################################################################
10191 10:06:31.041447
10192 10:06:31.581896 02180000 ################################################################
10193 10:06:31.582062
10194 10:06:32.117755 02200000 ################################################################
10195 10:06:32.117964
10196 10:06:32.663038 02280000 ################################################################
10197 10:06:32.663211
10198 10:06:33.205774 02300000 ################################################################
10199 10:06:33.205935
10200 10:06:33.762718 02380000 ################################################################
10201 10:06:33.762898
10202 10:06:34.304832 02400000 ################################################################
10203 10:06:34.305041
10204 10:06:34.840936 02480000 ################################################################
10205 10:06:34.841095
10206 10:06:35.397457 02500000 ################################################################
10207 10:06:35.397612
10208 10:06:35.949137 02580000 ################################################################
10209 10:06:35.949314
10210 10:06:36.498509 02600000 ################################################################
10211 10:06:36.498654
10212 10:06:37.068385 02680000 ################################################################
10213 10:06:37.068536
10214 10:06:37.614490 02700000 ################################################################
10215 10:06:37.614641
10216 10:06:38.159989 02780000 ################################################################
10217 10:06:38.160143
10218 10:06:38.691312 02800000 ################################################################
10219 10:06:38.691466
10220 10:06:39.225645 02880000 ################################################################
10221 10:06:39.225796
10222 10:06:39.761770 02900000 ################################################################
10223 10:06:39.761913
10224 10:06:40.300250 02980000 ################################################################
10225 10:06:40.300404
10226 10:06:40.844764 02a00000 ################################################################
10227 10:06:40.844910
10228 10:06:41.391673 02a80000 ################################################################
10229 10:06:41.391855
10230 10:06:41.930365 02b00000 ################################################################
10231 10:06:41.930522
10232 10:06:42.469236 02b80000 ################################################################
10233 10:06:42.469377
10234 10:06:43.017456 02c00000 ################################################################
10235 10:06:43.017612
10236 10:06:43.562934 02c80000 ################################################################
10237 10:06:43.563109
10238 10:06:44.103904 02d00000 ################################################################
10239 10:06:44.104095
10240 10:06:44.635425 02d80000 ################################################################
10241 10:06:44.635573
10242 10:06:45.171347 02e00000 ################################################################
10243 10:06:45.171502
10244 10:06:45.712909 02e80000 ################################################################
10245 10:06:45.713058
10246 10:06:46.253436 02f00000 ################################################################
10247 10:06:46.253571
10248 10:06:46.779671 02f80000 ################################################################
10249 10:06:46.779808
10250 10:06:47.305470 03000000 ################################################################
10251 10:06:47.305653
10252 10:06:47.826643 03080000 ################################################################
10253 10:06:47.826789
10254 10:06:48.350682 03100000 ################################################################
10255 10:06:48.350831
10256 10:06:48.874813 03180000 ################################################################
10257 10:06:48.874961
10258 10:06:49.396638 03200000 ################################################################
10259 10:06:49.396790
10260 10:06:49.920503 03280000 ################################################################
10261 10:06:49.920659
10262 10:06:50.449088 03300000 ################################################################
10263 10:06:50.449237
10264 10:06:50.979600 03380000 ################################################################
10265 10:06:50.979761
10266 10:06:51.504370 03400000 ################################################################
10267 10:06:51.504548
10268 10:06:52.034612 03480000 ################################################################
10269 10:06:52.034789
10270 10:06:52.558945 03500000 ################################################################
10271 10:06:52.559092
10272 10:06:53.082077 03580000 ################################################################
10273 10:06:53.082227
10274 10:06:53.597182 03600000 ################################################################
10275 10:06:53.597327
10276 10:06:54.123384 03680000 ################################################################
10277 10:06:54.123555
10278 10:06:54.663299 03700000 ################################################################
10279 10:06:54.663481
10280 10:06:55.223399 03780000 ################################################################
10281 10:06:55.223548
10282 10:06:55.794139 03800000 ################################################################
10283 10:06:55.794293
10284 10:06:56.345217 03880000 ################################################################
10285 10:06:56.345361
10286 10:06:56.890290 03900000 ################################################################
10287 10:06:56.890471
10288 10:06:57.422088 03980000 ################################################################
10289 10:06:57.422266
10290 10:06:57.957138 03a00000 ################################################################
10291 10:06:57.957322
10292 10:06:58.511356 03a80000 ################################################################
10293 10:06:58.511508
10294 10:06:59.049250 03b00000 ################################################################
10295 10:06:59.049433
10296 10:06:59.591922 03b80000 ################################################################
10297 10:06:59.592107
10298 10:07:00.127053 03c00000 ################################################################
10299 10:07:00.127199
10300 10:07:00.682745 03c80000 ################################################################
10301 10:07:00.682996
10302 10:07:01.243153 03d00000 ################################################################
10303 10:07:01.243306
10304 10:07:01.816086 03d80000 ################################################################
10305 10:07:01.816230
10306 10:07:02.416907 03e00000 ################################################################
10307 10:07:02.417068
10308 10:07:02.986246 03e80000 ################################################################
10309 10:07:02.986393
10310 10:07:03.460735 03f00000 ####################################################### done.
10311 10:07:03.460890
10312 10:07:03.463512 The bootfile was 66510406 bytes long.
10313 10:07:03.463609
10314 10:07:03.467474 Sending tftp read request... done.
10315 10:07:03.467550
10316 10:07:03.467612 Waiting for the transfer...
10317 10:07:03.467670
10318 10:07:03.470079 00000000 # done.
10319 10:07:03.470163
10320 10:07:03.476645 Command line loaded dynamically from TFTP file: 10670700/tftp-deploy-0exqgs1y/kernel/cmdline
10321 10:07:03.476729
10322 10:07:03.490250 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10323 10:07:03.490374
10324 10:07:03.490471 Loading FIT.
10325 10:07:03.490561
10326 10:07:03.493095 Image ramdisk-1 has 56374129 bytes.
10327 10:07:03.493198
10328 10:07:03.496557 Image fdt-1 has 46924 bytes.
10329 10:07:03.496664
10330 10:07:03.500233 Image kernel-1 has 10087317 bytes.
10331 10:07:03.500319
10332 10:07:03.510071 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10333 10:07:03.510181
10334 10:07:03.526549 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10335 10:07:03.526676
10336 10:07:03.529483 Choosing best match conf-1 for compat google,spherion-rev2.
10337 10:07:03.535367
10338 10:07:03.540264 Connected to device vid:did:rid of 1ae0:0028:00
10339 10:07:03.547143
10340 10:07:03.550508 tpm_get_response: command 0x17b, return code 0x0
10341 10:07:03.550653
10342 10:07:03.553309 ec_init: CrosEC protocol v3 supported (256, 248)
10343 10:07:03.557511
10344 10:07:03.560683 tpm_cleanup: add release locality here.
10345 10:07:03.560900
10346 10:07:03.561082 Shutting down all USB controllers.
10347 10:07:03.563942
10348 10:07:03.564071 Removing current net device
10349 10:07:03.564184
10350 10:07:03.570527 Exiting depthcharge with code 4 at timestamp: 103811815
10351 10:07:03.570609
10352 10:07:03.574408 LZMA decompressing kernel-1 to 0x821a6718
10353 10:07:03.574497
10354 10:07:03.577446 LZMA decompressing kernel-1 to 0x40000000
10355 10:07:04.845191
10356 10:07:04.845706 jumping to kernel
10357 10:07:04.847244 end: 2.2.4 bootloader-commands (duration 00:01:16) [common]
10358 10:07:04.847745 start: 2.2.5 auto-login-action (timeout 00:03:09) [common]
10359 10:07:04.848170 Setting prompt string to ['Linux version [0-9]']
10360 10:07:04.848538 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10361 10:07:04.848897 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10362 10:07:04.926521
10363 10:07:04.930175 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10364 10:07:04.933840 start: 2.2.5.1 login-action (timeout 00:03:09) [common]
10365 10:07:04.934441 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10366 10:07:04.935064 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10367 10:07:04.935631 Using line separator: #'\n'#
10368 10:07:04.936171 No login prompt set.
10369 10:07:04.936679 Parsing kernel messages
10370 10:07:04.937177 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10371 10:07:04.938076 [login-action] Waiting for messages, (timeout 00:03:09)
10372 10:07:04.953087 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j19381-arm64-gcc-10-defconfig-arm64-chromebook-d6qsg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023
10373 10:07:04.956437 [ 0.000000] random: crng init done
10374 10:07:04.959447 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10375 10:07:04.962991 [ 0.000000] efi: UEFI not found.
10376 10:07:04.972969 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10377 10:07:04.979604 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10378 10:07:04.989165 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10379 10:07:04.999054 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10380 10:07:05.005624 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10381 10:07:05.011902 [ 0.000000] printk: bootconsole [mtk8250] enabled
10382 10:07:05.018589 [ 0.000000] NUMA: No NUMA configuration found
10383 10:07:05.025569 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10384 10:07:05.028284 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10385 10:07:05.031862 [ 0.000000] Zone ranges:
10386 10:07:05.038493 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10387 10:07:05.041743 [ 0.000000] DMA32 empty
10388 10:07:05.048080 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10389 10:07:05.051467 [ 0.000000] Movable zone start for each node
10390 10:07:05.054816 [ 0.000000] Early memory node ranges
10391 10:07:05.061432 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10392 10:07:05.068392 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10393 10:07:05.074660 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10394 10:07:05.080922 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10395 10:07:05.087855 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10396 10:07:05.094178 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10397 10:07:05.150137 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10398 10:07:05.156925 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10399 10:07:05.163773 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10400 10:07:05.166961 [ 0.000000] psci: probing for conduit method from DT.
10401 10:07:05.173401 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10402 10:07:05.177023 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10403 10:07:05.183937 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10404 10:07:05.186932 [ 0.000000] psci: SMC Calling Convention v1.2
10405 10:07:05.193540 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10406 10:07:05.197084 [ 0.000000] Detected VIPT I-cache on CPU0
10407 10:07:05.203449 [ 0.000000] CPU features: detected: GIC system register CPU interface
10408 10:07:05.209729 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10409 10:07:05.216660 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10410 10:07:05.223135 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10411 10:07:05.232596 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10412 10:07:05.239382 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10413 10:07:05.242315 [ 0.000000] alternatives: applying boot alternatives
10414 10:07:05.249275 [ 0.000000] Fallback order for Node 0: 0
10415 10:07:05.255521 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10416 10:07:05.259319 [ 0.000000] Policy zone: Normal
10417 10:07:05.272137 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10418 10:07:05.281829 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10419 10:07:05.292403 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10420 10:07:05.302032 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10421 10:07:05.309074 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10422 10:07:05.312054 <6>[ 0.000000] software IO TLB: area num 8.
10423 10:07:05.368547 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10424 10:07:05.518464 <6>[ 0.000000] Memory: 7917884K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 434884K reserved, 32768K cma-reserved)
10425 10:07:05.524797 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10426 10:07:05.531420 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10427 10:07:05.535437 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10428 10:07:05.541551 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10429 10:07:05.547474 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10430 10:07:05.551236 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10431 10:07:05.561054 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10432 10:07:05.567836 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10433 10:07:05.574194 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10434 10:07:05.580259 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10435 10:07:05.583942 <6>[ 0.000000] GICv3: 608 SPIs implemented
10436 10:07:05.586897 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10437 10:07:05.593445 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10438 10:07:05.596647 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10439 10:07:05.603698 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10440 10:07:05.616642 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10441 10:07:05.629889 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10442 10:07:05.636352 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10443 10:07:05.644490 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10444 10:07:05.657792 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10445 10:07:05.664122 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10446 10:07:05.670797 <6>[ 0.009170] Console: colour dummy device 80x25
10447 10:07:05.681042 <6>[ 0.013897] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10448 10:07:05.687377 <6>[ 0.024340] pid_max: default: 32768 minimum: 301
10449 10:07:05.690578 <6>[ 0.029214] LSM: Security Framework initializing
10450 10:07:05.697198 <6>[ 0.034182] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10451 10:07:05.707230 <6>[ 0.041997] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10452 10:07:05.717337 <6>[ 0.051482] cblist_init_generic: Setting adjustable number of callback queues.
10453 10:07:05.720360 <6>[ 0.058935] cblist_init_generic: Setting shift to 3 and lim to 1.
10454 10:07:05.727336 <6>[ 0.065273] cblist_init_generic: Setting shift to 3 and lim to 1.
10455 10:07:05.733565 <6>[ 0.071680] rcu: Hierarchical SRCU implementation.
10456 10:07:05.740086 <6>[ 0.076694] rcu: Max phase no-delay instances is 1000.
10457 10:07:05.743417 <6>[ 0.083745] EFI services will not be available.
10458 10:07:05.750464 <6>[ 0.088715] smp: Bringing up secondary CPUs ...
10459 10:07:05.757841 <6>[ 0.093769] Detected VIPT I-cache on CPU1
10460 10:07:05.764258 <6>[ 0.093840] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10461 10:07:05.770871 <6>[ 0.093872] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10462 10:07:05.774320 <6>[ 0.094198] Detected VIPT I-cache on CPU2
10463 10:07:05.781017 <6>[ 0.094246] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10464 10:07:05.787694 <6>[ 0.094261] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10465 10:07:05.794456 <6>[ 0.094517] Detected VIPT I-cache on CPU3
10466 10:07:05.801099 <6>[ 0.094563] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10467 10:07:05.807541 <6>[ 0.094576] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10468 10:07:05.810457 <6>[ 0.094880] CPU features: detected: Spectre-v4
10469 10:07:05.817541 <6>[ 0.094887] CPU features: detected: Spectre-BHB
10470 10:07:05.820539 <6>[ 0.094893] Detected PIPT I-cache on CPU4
10471 10:07:05.827265 <6>[ 0.094950] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10472 10:07:05.834214 <6>[ 0.094966] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10473 10:07:05.840123 <6>[ 0.095257] Detected PIPT I-cache on CPU5
10474 10:07:05.847483 <6>[ 0.095321] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10475 10:07:05.853671 <6>[ 0.095337] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10476 10:07:05.857077 <6>[ 0.095618] Detected PIPT I-cache on CPU6
10477 10:07:05.864255 <6>[ 0.095684] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10478 10:07:05.870449 <6>[ 0.095700] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10479 10:07:05.877038 <6>[ 0.095994] Detected PIPT I-cache on CPU7
10480 10:07:05.883866 <6>[ 0.096062] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10481 10:07:05.890436 <6>[ 0.096078] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10482 10:07:05.893706 <6>[ 0.096126] smp: Brought up 1 node, 8 CPUs
10483 10:07:05.900224 <6>[ 0.237534] SMP: Total of 8 processors activated.
10484 10:07:05.903850 <6>[ 0.242455] CPU features: detected: 32-bit EL0 Support
10485 10:07:05.912890 <6>[ 0.247817] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10486 10:07:05.919654 <6>[ 0.256672] CPU features: detected: Common not Private translations
10487 10:07:05.926430 <6>[ 0.263148] CPU features: detected: CRC32 instructions
10488 10:07:05.933093 <6>[ 0.268499] CPU features: detected: RCpc load-acquire (LDAPR)
10489 10:07:05.936203 <6>[ 0.274495] CPU features: detected: LSE atomic instructions
10490 10:07:05.942868 <6>[ 0.280277] CPU features: detected: Privileged Access Never
10491 10:07:05.949421 <6>[ 0.286056] CPU features: detected: RAS Extension Support
10492 10:07:05.956021 <6>[ 0.291665] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10493 10:07:05.959297 <6>[ 0.298886] CPU: All CPU(s) started at EL2
10494 10:07:05.965628 <6>[ 0.303203] alternatives: applying system-wide alternatives
10495 10:07:05.975985 <6>[ 0.313950] devtmpfs: initialized
10496 10:07:05.992276 <6>[ 0.322995] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10497 10:07:05.998780 <6>[ 0.332962] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10498 10:07:06.005357 <6>[ 0.341186] pinctrl core: initialized pinctrl subsystem
10499 10:07:06.008410 <6>[ 0.347850] DMI not present or invalid.
10500 10:07:06.014549 <6>[ 0.352260] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10501 10:07:06.024621 <6>[ 0.359149] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10502 10:07:06.031226 <6>[ 0.366735] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10503 10:07:06.040944 <6>[ 0.374958] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10504 10:07:06.044598 <6>[ 0.383199] audit: initializing netlink subsys (disabled)
10505 10:07:06.054296 <5>[ 0.388893] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10506 10:07:06.061010 <6>[ 0.389609] thermal_sys: Registered thermal governor 'step_wise'
10507 10:07:06.067534 <6>[ 0.396861] thermal_sys: Registered thermal governor 'power_allocator'
10508 10:07:06.070868 <6>[ 0.403116] cpuidle: using governor menu
10509 10:07:06.077028 <6>[ 0.414074] NET: Registered PF_QIPCRTR protocol family
10510 10:07:06.083500 <6>[ 0.419550] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10511 10:07:06.089935 <6>[ 0.426651] ASID allocator initialised with 32768 entries
10512 10:07:06.093318 <6>[ 0.433222] Serial: AMBA PL011 UART driver
10513 10:07:06.103707 <4>[ 0.441927] Trying to register duplicate clock ID: 134
10514 10:07:06.160080 <6>[ 0.501253] KASLR enabled
10515 10:07:06.174802 <6>[ 0.509048] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10516 10:07:06.181340 <6>[ 0.516062] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10517 10:07:06.187687 <6>[ 0.522551] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10518 10:07:06.193926 <6>[ 0.529556] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10519 10:07:06.200837 <6>[ 0.536042] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10520 10:07:06.207198 <6>[ 0.543046] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10521 10:07:06.214025 <6>[ 0.549533] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10522 10:07:06.220565 <6>[ 0.556539] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10523 10:07:06.223672 <6>[ 0.564071] ACPI: Interpreter disabled.
10524 10:07:06.232442 <6>[ 0.570479] iommu: Default domain type: Translated
10525 10:07:06.239528 <6>[ 0.575592] iommu: DMA domain TLB invalidation policy: strict mode
10526 10:07:06.242705 <5>[ 0.582251] SCSI subsystem initialized
10527 10:07:06.248995 <6>[ 0.586416] usbcore: registered new interface driver usbfs
10528 10:07:06.255963 <6>[ 0.592150] usbcore: registered new interface driver hub
10529 10:07:06.258782 <6>[ 0.597702] usbcore: registered new device driver usb
10530 10:07:06.265636 <6>[ 0.603795] pps_core: LinuxPPS API ver. 1 registered
10531 10:07:06.276106 <6>[ 0.608986] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10532 10:07:06.279406 <6>[ 0.618333] PTP clock support registered
10533 10:07:06.282574 <6>[ 0.622574] EDAC MC: Ver: 3.0.0
10534 10:07:06.290199 <6>[ 0.627728] FPGA manager framework
10535 10:07:06.297039 <6>[ 0.631410] Advanced Linux Sound Architecture Driver Initialized.
10536 10:07:06.299807 <6>[ 0.638183] vgaarb: loaded
10537 10:07:06.307054 <6>[ 0.641350] clocksource: Switched to clocksource arch_sys_counter
10538 10:07:06.309717 <5>[ 0.647786] VFS: Disk quotas dquot_6.6.0
10539 10:07:06.316457 <6>[ 0.651971] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10540 10:07:06.319426 <6>[ 0.659161] pnp: PnP ACPI: disabled
10541 10:07:06.327951 <6>[ 0.665922] NET: Registered PF_INET protocol family
10542 10:07:06.337837 <6>[ 0.671501] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10543 10:07:06.349056 <6>[ 0.683712] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10544 10:07:06.359172 <6>[ 0.692527] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10545 10:07:06.365268 <6>[ 0.700496] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10546 10:07:06.374986 <6>[ 0.709194] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10547 10:07:06.382075 <6>[ 0.718913] TCP: Hash tables configured (established 65536 bind 65536)
10548 10:07:06.388918 <6>[ 0.725769] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10549 10:07:06.398668 <6>[ 0.732967] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10550 10:07:06.404567 <6>[ 0.740665] NET: Registered PF_UNIX/PF_LOCAL protocol family
10551 10:07:06.411658 <6>[ 0.746845] RPC: Registered named UNIX socket transport module.
10552 10:07:06.414807 <6>[ 0.753001] RPC: Registered udp transport module.
10553 10:07:06.421723 <6>[ 0.757934] RPC: Registered tcp transport module.
10554 10:07:06.427815 <6>[ 0.762867] RPC: Registered tcp NFSv4.1 backchannel transport module.
10555 10:07:06.431250 <6>[ 0.769539] PCI: CLS 0 bytes, default 64
10556 10:07:06.434314 <6>[ 0.773880] Unpacking initramfs...
10557 10:07:06.444380 <6>[ 0.778023] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10558 10:07:06.450934 <6>[ 0.786680] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10559 10:07:06.457665 <6>[ 0.795532] kvm [1]: IPA Size Limit: 40 bits
10560 10:07:06.461052 <6>[ 0.800064] kvm [1]: GICv3: no GICV resource entry
10561 10:07:06.467343 <6>[ 0.805086] kvm [1]: disabling GICv2 emulation
10562 10:07:06.474372 <6>[ 0.809790] kvm [1]: GIC system register CPU interface enabled
10563 10:07:06.477780 <6>[ 0.815957] kvm [1]: vgic interrupt IRQ18
10564 10:07:06.484084 <6>[ 0.820315] kvm [1]: VHE mode initialized successfully
10565 10:07:06.487717 <5>[ 0.826779] Initialise system trusted keyrings
10566 10:07:06.494233 <6>[ 0.831576] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10567 10:07:06.504928 <6>[ 0.841892] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10568 10:07:06.510704 <5>[ 0.848332] NFS: Registering the id_resolver key type
10569 10:07:06.514118 <5>[ 0.853642] Key type id_resolver registered
10570 10:07:06.520546 <5>[ 0.858055] Key type id_legacy registered
10571 10:07:06.527306 <6>[ 0.862333] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10572 10:07:06.534344 <6>[ 0.869258] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10573 10:07:06.540063 <6>[ 0.876991] 9p: Installing v9fs 9p2000 file system support
10574 10:07:06.577278 <5>[ 0.914734] Key type asymmetric registered
10575 10:07:06.580735 <5>[ 0.919068] Asymmetric key parser 'x509' registered
10576 10:07:06.589650 <6>[ 0.924211] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10577 10:07:06.593005 <6>[ 0.931823] io scheduler mq-deadline registered
10578 10:07:06.596380 <6>[ 0.936583] io scheduler kyber registered
10579 10:07:06.615390 <6>[ 0.953541] EINJ: ACPI disabled.
10580 10:07:06.648158 <4>[ 0.979476] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10581 10:07:06.657960 <4>[ 0.990132] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10582 10:07:06.672714 <6>[ 1.010749] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10583 10:07:06.680440 <6>[ 1.018684] printk: console [ttyS0] disabled
10584 10:07:06.708656 <6>[ 1.043327] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10585 10:07:06.715260 <6>[ 1.052796] printk: console [ttyS0] enabled
10586 10:07:06.718943 <6>[ 1.052796] printk: console [ttyS0] enabled
10587 10:07:06.725590 <6>[ 1.061690] printk: bootconsole [mtk8250] disabled
10588 10:07:06.728836 <6>[ 1.061690] printk: bootconsole [mtk8250] disabled
10589 10:07:06.735276 <6>[ 1.072909] SuperH (H)SCI(F) driver initialized
10590 10:07:06.738915 <6>[ 1.078184] msm_serial: driver initialized
10591 10:07:06.752716 <6>[ 1.087134] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10592 10:07:06.762353 <6>[ 1.095680] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10593 10:07:06.769370 <6>[ 1.104221] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10594 10:07:06.779108 <6>[ 1.112849] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10595 10:07:06.788842 <6>[ 1.121554] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10596 10:07:06.795598 <6>[ 1.130267] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10597 10:07:06.805352 <6>[ 1.138806] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10598 10:07:06.812794 <6>[ 1.147607] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10599 10:07:06.822035 <6>[ 1.156150] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10600 10:07:06.833295 <6>[ 1.171486] loop: module loaded
10601 10:07:06.840230 <6>[ 1.177548] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10602 10:07:06.863376 <4>[ 1.200793] mtk-pmic-keys: Failed to locate of_node [id: -1]
10603 10:07:06.869723 <6>[ 1.207559] megasas: 07.719.03.00-rc1
10604 10:07:06.879395 <6>[ 1.217162] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10605 10:07:06.887124 <6>[ 1.224740] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10606 10:07:06.903773 <6>[ 1.241528] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10607 10:07:06.960927 <6>[ 1.291899] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10608 10:07:08.875351 <6>[ 3.212994] Freeing initrd memory: 55048K
10609 10:07:08.885358 <6>[ 3.223443] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10610 10:07:08.896306 <6>[ 3.234549] tun: Universal TUN/TAP device driver, 1.6
10611 10:07:08.900560 <6>[ 3.240614] thunder_xcv, ver 1.0
10612 10:07:08.903442 <6>[ 3.244123] thunder_bgx, ver 1.0
10613 10:07:08.906211 <6>[ 3.247615] nicpf, ver 1.0
10614 10:07:08.917060 <6>[ 3.251647] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10615 10:07:08.920224 <6>[ 3.259123] hns3: Copyright (c) 2017 Huawei Corporation.
10616 10:07:08.926508 <6>[ 3.264711] hclge is initializing
10617 10:07:08.929777 <6>[ 3.268292] e1000: Intel(R) PRO/1000 Network Driver
10618 10:07:08.936590 <6>[ 3.273421] e1000: Copyright (c) 1999-2006 Intel Corporation.
10619 10:07:08.940083 <6>[ 3.279435] e1000e: Intel(R) PRO/1000 Network Driver
10620 10:07:08.946617 <6>[ 3.284651] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10621 10:07:08.953110 <6>[ 3.290837] igb: Intel(R) Gigabit Ethernet Network Driver
10622 10:07:08.959827 <6>[ 3.296486] igb: Copyright (c) 2007-2014 Intel Corporation.
10623 10:07:08.966959 <6>[ 3.302324] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10624 10:07:08.973239 <6>[ 3.308842] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10625 10:07:08.976390 <6>[ 3.315304] sky2: driver version 1.30
10626 10:07:08.983109 <6>[ 3.320296] VFIO - User Level meta-driver version: 0.3
10627 10:07:08.990571 <6>[ 3.328503] usbcore: registered new interface driver usb-storage
10628 10:07:08.996934 <6>[ 3.334956] usbcore: registered new device driver onboard-usb-hub
10629 10:07:09.005876 <6>[ 3.344092] mt6397-rtc mt6359-rtc: registered as rtc0
10630 10:07:09.016219 <6>[ 3.349581] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-10T10:07:09 UTC (1686391629)
10631 10:07:09.019130 <6>[ 3.359159] i2c_dev: i2c /dev entries driver
10632 10:07:09.035696 <6>[ 3.370782] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10633 10:07:09.042593 <6>[ 3.381000] sdhci: Secure Digital Host Controller Interface driver
10634 10:07:09.049537 <6>[ 3.387437] sdhci: Copyright(c) Pierre Ossman
10635 10:07:09.055666 <6>[ 3.392852] Synopsys Designware Multimedia Card Interface Driver
10636 10:07:09.059232 <6>[ 3.399425] mmc0: CQHCI version 5.10
10637 10:07:09.065986 <6>[ 3.399996] sdhci-pltfm: SDHCI platform and OF driver helper
10638 10:07:09.073288 <6>[ 3.411652] ledtrig-cpu: registered to indicate activity on CPUs
10639 10:07:09.084256 <6>[ 3.419056] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10640 10:07:09.090752 <6>[ 3.426482] usbcore: registered new interface driver usbhid
10641 10:07:09.094397 <6>[ 3.432316] usbhid: USB HID core driver
10642 10:07:09.100498 <6>[ 3.436565] spi_master spi0: will run message pump with realtime priority
10643 10:07:09.147406 <6>[ 3.478901] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10644 10:07:09.154369 <6>[ 3.492650] mmc0: Command Queue Engine enabled
10645 10:07:09.161125 <6>[ 3.497428] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10646 10:07:09.168186 <6>[ 3.504909] mmcblk0: mmc0:0001 DA4128 116 GiB
10647 10:07:09.181038 <6>[ 3.510261] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10648 10:07:09.187701 <6>[ 3.513143] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10649 10:07:09.194573 <6>[ 3.530758] cros-ec-spi spi0.0: Chrome EC device registered
10650 10:07:09.197306 <6>[ 3.531206] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10651 10:07:09.204814 <6>[ 3.542606] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10652 10:07:09.211198 <6>[ 3.548648] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10653 10:07:09.234251 <6>[ 3.568926] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10654 10:07:09.242332 <6>[ 3.580395] NET: Registered PF_PACKET protocol family
10655 10:07:09.248796 <6>[ 3.585897] 9pnet: Installing 9P2000 support
10656 10:07:09.251973 <5>[ 3.590488] Key type dns_resolver registered
10657 10:07:09.255034 <6>[ 3.595648] registered taskstats version 1
10658 10:07:09.261833 <5>[ 3.600080] Loading compiled-in X.509 certificates
10659 10:07:09.295551 <4>[ 3.626818] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10660 10:07:09.304674 <4>[ 3.637568] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10661 10:07:09.316021 <3>[ 3.650149] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10662 10:07:09.327802 <6>[ 3.665683] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10663 10:07:09.334517 <6>[ 3.672457] xhci-mtk 11200000.usb: xHCI Host Controller
10664 10:07:09.340716 <6>[ 3.677959] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10665 10:07:09.350766 <6>[ 3.685816] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10666 10:07:09.357196 <6>[ 3.695250] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10667 10:07:09.364352 <6>[ 3.701459] xhci-mtk 11200000.usb: xHCI Host Controller
10668 10:07:09.370772 <6>[ 3.706955] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10669 10:07:09.377195 <6>[ 3.714613] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10670 10:07:09.384615 <6>[ 3.722523] hub 1-0:1.0: USB hub found
10671 10:07:09.388124 <6>[ 3.726570] hub 1-0:1.0: 1 port detected
10672 10:07:09.397509 <6>[ 3.730927] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10673 10:07:09.400555 <6>[ 3.739757] hub 2-0:1.0: USB hub found
10674 10:07:09.404207 <6>[ 3.743800] hub 2-0:1.0: 1 port detected
10675 10:07:09.412714 <6>[ 3.750882] mtk-msdc 11f70000.mmc: Got CD GPIO
10676 10:07:09.431093 <6>[ 3.765443] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10677 10:07:09.436860 <6>[ 3.773601] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10678 10:07:09.446986 <4>[ 3.781610] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10679 10:07:09.457024 <6>[ 3.791327] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10680 10:07:09.463686 <6>[ 3.799412] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10681 10:07:09.473870 <6>[ 3.807467] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10682 10:07:09.480498 <6>[ 3.815402] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10683 10:07:09.486617 <6>[ 3.823272] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10684 10:07:09.496999 <6>[ 3.831102] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10685 10:07:09.506956 <6>[ 3.841808] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10686 10:07:09.516951 <6>[ 3.850174] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10687 10:07:09.523618 <6>[ 3.858565] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10688 10:07:09.533396 <6>[ 3.866911] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10689 10:07:09.539594 <6>[ 3.875281] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10690 10:07:09.549973 <6>[ 3.883626] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10691 10:07:09.556615 <6>[ 3.891995] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10692 10:07:09.566699 <6>[ 3.900339] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10693 10:07:09.572958 <6>[ 3.908704] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10694 10:07:09.582902 <6>[ 3.917049] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10695 10:07:09.589585 <6>[ 3.925393] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10696 10:07:09.599663 <6>[ 3.933736] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10697 10:07:09.605837 <6>[ 3.942081] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10698 10:07:09.616091 <6>[ 3.950425] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10699 10:07:09.622993 <6>[ 3.958769] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10700 10:07:09.629510 <6>[ 3.967667] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10701 10:07:09.636821 <6>[ 3.975089] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10702 10:07:09.644155 <6>[ 3.982143] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10703 10:07:09.651077 <6>[ 3.989242] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10704 10:07:09.661578 <6>[ 3.996533] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10705 10:07:09.668532 <6>[ 4.003437] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10706 10:07:09.678258 <6>[ 4.012577] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10707 10:07:09.688266 <6>[ 4.021749] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10708 10:07:09.697715 <6>[ 4.031062] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10709 10:07:09.707823 <6>[ 4.040537] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10710 10:07:09.714803 <6>[ 4.050012] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10711 10:07:09.724362 <6>[ 4.059139] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10712 10:07:09.734864 <6>[ 4.068614] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10713 10:07:09.744465 <6>[ 4.077741] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10714 10:07:09.753977 <6>[ 4.087043] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10715 10:07:09.763908 <6>[ 4.097210] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10716 10:07:09.774105 <6>[ 4.109221] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10717 10:07:09.794805 <6>[ 4.129662] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10718 10:07:09.822352 <6>[ 4.160187] hub 2-1:1.0: USB hub found
10719 10:07:09.825121 <6>[ 4.164591] hub 2-1:1.0: 3 ports detected
10720 10:07:09.946300 <6>[ 4.281621] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10721 10:07:10.100386 <6>[ 4.439056] hub 1-1:1.0: USB hub found
10722 10:07:10.103571 <6>[ 4.443483] hub 1-1:1.0: 4 ports detected
10723 10:07:10.179449 <6>[ 4.513877] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10724 10:07:10.426690 <6>[ 4.761627] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10725 10:07:10.558770 <6>[ 4.897209] hub 1-1.4:1.0: USB hub found
10726 10:07:10.562118 <6>[ 4.901858] hub 1-1.4:1.0: 2 ports detected
10727 10:07:10.862866 <6>[ 5.197625] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10728 10:07:11.054611 <6>[ 5.389621] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10729 10:07:22.051343 <6>[ 16.394253] ALSA device list:
10730 10:07:22.058102 <6>[ 16.397509] No soundcards found.
10731 10:07:22.070314 <6>[ 16.409982] Freeing unused kernel memory: 8384K
10732 10:07:22.073606 <6>[ 16.414890] Run /init as init process
10733 10:07:22.103602 <6>[ 16.443325] NET: Registered PF_INET6 protocol family
10734 10:07:22.110310 <6>[ 16.449795] Segment Routing with IPv6
10735 10:07:22.113757 <6>[ 16.453761] In-situ OAM (IOAM) with IPv6
10736 10:07:22.148191 <30>[ 16.468126] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10737 10:07:22.151255 <30>[ 16.492154] systemd[1]: Detected architecture arm64.
10738 10:07:22.155090
10739 10:07:22.157970 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10740 10:07:22.158702
10741 10:07:22.173689 <30>[ 16.513794] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10742 10:07:22.300679 <30>[ 16.637385] systemd[1]: Queued start job for default target Graphical Interface.
10743 10:07:22.339716 <30>[ 16.679149] systemd[1]: Created slice system-getty.slice.
10744 10:07:22.346120 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10745 10:07:22.362874 <30>[ 16.702295] systemd[1]: Created slice system-modprobe.slice.
10746 10:07:22.369013 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10747 10:07:22.387114 <30>[ 16.726743] systemd[1]: Created slice system-serial\x2dgetty.slice.
10748 10:07:22.397402 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10749 10:07:22.410574 <30>[ 16.750134] systemd[1]: Created slice User and Session Slice.
10750 10:07:22.417008 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10751 10:07:22.437862 <30>[ 16.774183] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10752 10:07:22.447235 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10753 10:07:22.465809 <30>[ 16.801782] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10754 10:07:22.471613 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10755 10:07:22.492369 <30>[ 16.825769] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10756 10:07:22.499360 <30>[ 16.837820] systemd[1]: Reached target Local Encrypted Volumes.
10757 10:07:22.505926 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10758 10:07:22.522355 <30>[ 16.861971] systemd[1]: Reached target Paths.
10759 10:07:22.525518 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10760 10:07:22.542266 <30>[ 16.881672] systemd[1]: Reached target Remote File Systems.
10761 10:07:22.548084 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10762 10:07:22.565969 <30>[ 16.905991] systemd[1]: Reached target Slices.
10763 10:07:22.572935 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10764 10:07:22.585935 <30>[ 16.925693] systemd[1]: Reached target Swap.
10765 10:07:22.588717 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10766 10:07:22.610343 <30>[ 16.945982] systemd[1]: Listening on initctl Compatibility Named Pipe.
10767 10:07:22.616109 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10768 10:07:22.622236 <30>[ 16.960745] systemd[1]: Listening on Journal Audit Socket.
10769 10:07:22.629042 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10770 10:07:22.642035 <30>[ 16.981931] systemd[1]: Listening on Journal Socket (/dev/log).
10771 10:07:22.648477 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10772 10:07:22.666556 <30>[ 17.006405] systemd[1]: Listening on Journal Socket.
10773 10:07:22.672996 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10774 10:07:22.686325 <30>[ 17.025984] systemd[1]: Listening on udev Control Socket.
10775 10:07:22.692678 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10776 10:07:22.710394 <30>[ 17.050289] systemd[1]: Listening on udev Kernel Socket.
10777 10:07:22.716949 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10778 10:07:22.746154 <30>[ 17.085906] systemd[1]: Mounting Huge Pages File System...
10779 10:07:22.752876 Mounting [0;1;39mHuge Pages File System[0m...
10780 10:07:22.767991 <30>[ 17.107701] systemd[1]: Mounting POSIX Message Queue File System...
10781 10:07:22.774710 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10782 10:07:22.791482 <30>[ 17.131591] systemd[1]: Mounting Kernel Debug File System...
10783 10:07:22.798580 Mounting [0;1;39mKernel Debug File System[0m...
10784 10:07:22.816700 <30>[ 17.153837] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10785 10:07:22.861271 <30>[ 17.198093] systemd[1]: Starting Create list of static device nodes for the current kernel...
10786 10:07:22.867775 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10787 10:07:22.888231 <30>[ 17.227867] systemd[1]: Starting Load Kernel Module configfs...
10788 10:07:22.894463 Starting [0;1;39mLoad Kernel Module configfs[0m...
10789 10:07:22.912342 <30>[ 17.252012] systemd[1]: Starting Load Kernel Module drm...
10790 10:07:22.918787 Starting [0;1;39mLoad Kernel Module drm[0m...
10791 10:07:22.937160 <30>[ 17.273845] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10792 10:07:22.947461 <30>[ 17.287494] systemd[1]: Starting Journal Service...
10793 10:07:22.951082 Starting [0;1;39mJournal Service[0m...
10794 10:07:22.968136 <30>[ 17.308235] systemd[1]: Starting Load Kernel Modules...
10795 10:07:22.974923 Starting [0;1;39mLoad Kernel Modules[0m...
10796 10:07:22.995931 <30>[ 17.332359] systemd[1]: Starting Remount Root and Kernel File Systems...
10797 10:07:23.002598 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10798 10:07:23.016296 <30>[ 17.356118] systemd[1]: Starting Coldplug All udev Devices...
10799 10:07:23.022987 Starting [0;1;39mColdplug All udev Devices[0m...
10800 10:07:23.040435 <30>[ 17.380146] systemd[1]: Mounted Huge Pages File System.
10801 10:07:23.046748 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10802 10:07:23.053283 <30>[ 17.392426] systemd[1]: Started Journal Service.
10803 10:07:23.056562 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10804 10:07:23.076648 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10805 10:07:23.095251 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10806 10:07:23.118019 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10807 10:07:23.135215 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10808 10:07:23.151679 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10809 10:07:23.167182 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10810 10:07:23.187263 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10811 10:07:23.206241 See 'systemctl status systemd-remount-fs.service' for details.
10812 10:07:23.266072 Mounting [0;1;39mKernel Configuration File System[0m...
10813 10:07:23.284153 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10814 10:07:23.301903 <46>[ 17.638379] systemd-journald[175]: Received client request to flush runtime journal.
10815 10:07:23.310025 Starting [0;1;39mLoad/Save Random Seed[0m...
10816 10:07:23.332679 Starting [0;1;39mApply Kernel Variables[0m...
10817 10:07:23.352612 Starting [0;1;39mCreate System Users[0m...
10818 10:07:23.368124 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10819 10:07:23.394370 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10820 10:07:23.406550 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10821 10:07:23.423485 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10822 10:07:23.443027 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10823 10:07:23.458405 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10824 10:07:23.514353 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10825 10:07:23.536653 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10826 10:07:23.554081 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10827 10:07:23.573950 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10828 10:07:23.617913 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10829 10:07:23.641112 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10830 10:07:23.658297 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10831 10:07:23.678844 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10832 10:07:23.723333 Starting [0;1;39mNetwork Time Synchronization[0m...
10833 10:07:23.744527 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10834 10:07:23.779614 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10835 10:07:23.851315 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10836 10:07:23.876349 <6>[ 18.213185] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10837 10:07:23.893989 Startin<6>[ 18.231282] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10838 10:07:23.904082 <6>[ 18.239850] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10839 10:07:23.906895 <6>[ 18.247951] remoteproc remoteproc0: scp is available
10840 10:07:23.916972 g [0;1;39mLoad/<6>[ 18.248710] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10841 10:07:23.930245 Save Screen …o<4>[ 18.254121] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10842 10:07:23.940016 f leds:white:kbd<3>[ 18.269332] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10843 10:07:23.946444 _backlight[0m..<6>[ 18.275065] remoteproc remoteproc0: powering up scp
10844 10:07:23.946525 .
10845 10:07:23.953240 <3>[ 18.284633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10846 10:07:23.963169 <4>[ 18.291098] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10847 10:07:23.973038 <3>[ 18.299399] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10848 10:07:23.976358 <3>[ 18.309227] remoteproc remoteproc0: request_firmware failed: -2
10849 10:07:23.983021 <6>[ 18.317694] mc: Linux media interface: v0.10
10850 10:07:23.993247 <3>[ 18.330366] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10851 10:07:23.999842 <3>[ 18.338762] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10852 10:07:24.009840 <4>[ 18.342343] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10853 10:07:24.019997 [[0;32m OK [<3>[ 18.347214] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 10:07:24.026420 0m] Started [0;<3>[ 18.363776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10855 10:07:24.036611 1;39mNetwork Tim<4>[ 18.366122] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10856 10:07:24.043056 <6>[ 18.372465] usbcore: registered new interface driver r8152
10857 10:07:24.052978 e Synchronizatio<3>[ 18.373372] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10858 10:07:24.053094 n[0m.
10859 10:07:24.059486 <6>[ 18.374386] videodev: Linux video capture interface: v2.00
10860 10:07:24.066299 <6>[ 18.384856] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10861 10:07:24.072706 <3>[ 18.392851] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10862 10:07:24.079686 <6>[ 18.397033] pci_bus 0000:00: root bus resource [bus 00-ff]
10863 10:07:24.086030 <3>[ 18.411193] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10864 10:07:24.092418 <6>[ 18.418407] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10865 10:07:24.103187 <6>[ 18.418418] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10866 10:07:24.109255 <6>[ 18.418600] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10867 10:07:24.118780 <6>[ 18.422050] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10868 10:07:24.125228 <3>[ 18.424206] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10869 10:07:24.132225 <6>[ 18.432317] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10870 10:07:24.142065 <3>[ 18.439441] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10871 10:07:24.149220 <3>[ 18.439586] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10872 10:07:24.158465 <4>[ 18.448053] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10873 10:07:24.162107 <4>[ 18.448053] Fallback method does not support PEC.
10874 10:07:24.168518 <6>[ 18.449811] pci 0000:00:00.0: supports D1 D2
10875 10:07:24.174979 <3>[ 18.455744] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 10:07:24.181953 <6>[ 18.463327] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10877 10:07:24.191982 <3>[ 18.471390] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10878 10:07:24.198599 <6>[ 18.473810] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10879 10:07:24.205631 <6>[ 18.481821] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10880 10:07:24.215636 <3>[ 18.486948] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10881 10:07:24.222029 <6>[ 18.495558] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10882 10:07:24.229003 <6>[ 18.496544] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10883 10:07:24.238722 <4>[ 18.497154] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10884 10:07:24.248650 <4>[ 18.497168] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10885 10:07:24.258434 <6>[ 18.504024] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10886 10:07:24.265508 <6>[ 18.504344] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10887 10:07:24.275225 <3>[ 18.509534] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10888 10:07:24.282162 <6>[ 18.513287] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10889 10:07:24.292022 <3>[ 18.521404] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10890 10:07:24.298203 <6>[ 18.528456] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10891 10:07:24.305165 <6>[ 18.537597] usbcore: registered new interface driver cdc_ether
10892 10:07:24.311307 <6>[ 18.545878] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10893 10:07:24.318235 <6>[ 18.552973] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10894 10:07:24.321604 <6>[ 18.560305] pci 0000:01:00.0: supports D1 D2
10895 10:07:24.328100 <6>[ 18.561257] r8152 2-1.3:1.0 eth0: v1.12.13
10896 10:07:24.331484 <6>[ 18.564396] Bluetooth: Core ver 2.22
10897 10:07:24.338480 <6>[ 18.564476] NET: Registered PF_BLUETOOTH protocol family
10898 10:07:24.342011 <6>[ 18.564479] Bluetooth: HCI device and connection manager initialized
10899 10:07:24.348927 <6>[ 18.564495] Bluetooth: HCI socket layer initialized
10900 10:07:24.352316 <6>[ 18.564500] Bluetooth: L2CAP socket layer initialized
10901 10:07:24.359336 <6>[ 18.564510] Bluetooth: SCO socket layer initialized
10902 10:07:24.366283 <6>[ 18.567292] usbcore: registered new interface driver r8153_ecm
10903 10:07:24.376139 <6>[ 18.568095] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10904 10:07:24.382750 <6>[ 18.568229] usbcore: registered new interface driver uvcvideo
10905 10:07:24.389288 <6>[ 18.575545] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10906 10:07:24.396332 <6>[ 18.598105] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10907 10:07:24.402991 <6>[ 18.604235] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10908 10:07:24.409676 <6>[ 18.617448] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10909 10:07:24.416544 <6>[ 18.624510] remoteproc remoteproc0: powering up scp
10910 10:07:24.422789 <6>[ 18.627717] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10911 10:07:24.430544 <6>[ 18.628191] usbcore: registered new interface driver btusb
10912 10:07:24.436751 <3>[ 18.635677] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 10:07:24.447196 <4>[ 18.636040] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10914 10:07:24.453887 <3>[ 18.636051] Bluetooth: hci0: Failed to load firmware file (-2)
10915 10:07:24.460422 <3>[ 18.636055] Bluetooth: hci0: Failed to set up firmware (-2)
10916 10:07:24.470965 <4>[ 18.636061] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10917 10:07:24.480991 <4>[ 18.636158] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10918 10:07:24.487868 <3>[ 18.636165] remoteproc remoteproc0: request_firmware failed: -2
10919 10:07:24.494318 <3>[ 18.636180] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10920 10:07:24.501334 <6>[ 18.643273] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10921 10:07:24.511122 <3>[ 18.651238] power_supply sbs-5-000b: driver failed to report `status' property: -6
10922 10:07:24.518027 <6>[ 18.656666] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10923 10:07:24.524580 <6>[ 18.656683] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10924 10:07:24.534695 <3>[ 18.697073] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 10:07:24.540732 <6>[ 18.699005] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10926 10:07:24.551608 <3>[ 18.704409] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10927 10:07:24.555205 <6>[ 18.710224] pci 0000:00:00.0: PCI bridge to [bus 01]
10928 10:07:24.565041 <3>[ 18.712734] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 10:07:24.575090 <3>[ 18.744490] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 10:07:24.581961 <6>[ 18.748096] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10931 10:07:24.588315 <6>[ 18.748329] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10932 10:07:24.595354 <3>[ 18.774972] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 10:07:24.602227 <6>[ 18.783574] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10934 10:07:24.612459 <3>[ 18.814035] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 10:07:24.616547 <6>[ 18.815847] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10936 10:07:24.626429 <3>[ 18.847118] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 10:07:24.633112 <5>[ 18.873882] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10938 10:07:24.643083 <3>[ 18.900064] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 10:07:24.649563 <5>[ 18.911261] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10940 10:07:24.659804 <4>[ 18.995011] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10941 10:07:24.663163 <6>[ 19.003900] cfg80211: failed to load regulatory.db
10942 10:07:24.673132 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10943 10:07:24.688967 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10944 10:07:24.716659 <6>[ 19.053132] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10945 10:07:24.723467 <6>[ 19.060729] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10946 10:07:24.747215 <6>[ 19.087508] mt7921e 0000:01:00.0: ASIC revision: 79610010
10947 10:07:24.851607 <4>[ 19.184729] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10948 10:07:24.862665 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10949 10:07:24.878256 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10950 10:07:24.896638 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10951 10:07:24.913539 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10952 10:07:24.933884 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10953 10:07:24.953283 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10954 10:07:24.969999 <4>[ 19.304026] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10955 10:07:24.976675 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10956 10:07:24.994337 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10957 10:07:25.005234 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10958 10:07:25.021571 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10959 10:07:25.041204 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10960 10:07:25.090100 <4>[ 19.423779] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10961 10:07:25.108150 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10962 10:07:25.136749 Starting [0;1;39mUser Login Management[0m...
10963 10:07:25.151886 Starting [0;1;39mPermit User Sessions[0m...
10964 10:07:25.169713 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10965 10:07:25.189309 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10966 10:07:25.212305 [[0;32m OK [<4>[ 19.546877] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10967 10:07:25.219202 0m] Finished [0;1;39mPermit User Sessions[0m.
10968 10:07:25.239556 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10969 10:07:25.257039 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10970 10:07:25.273885 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10971 10:07:25.291211 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10972 10:07:25.298118 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10973 10:07:25.313614 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10974 10:07:25.343306 <4>[ 19.676988] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10975 10:07:25.378073 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10976 10:07:25.402417 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10977 10:07:25.454040
10978 10:07:25.454560
10979 10:07:25.457361 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10980 10:07:25.457779
10981 10:07:25.470308 debian-bullse<4>[ 19.802121] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10982 10:07:25.473599 ye-arm64 login: root (automatic login)
10983 10:07:25.474204
10984 10:07:25.474704
10985 10:07:25.480432 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023 aarch64
10986 10:07:25.480862
10987 10:07:25.487377 The programs included with the Debian GNU/Linux system are free software;
10988 10:07:25.493638 the exact distribution terms for each program are described in the
10989 10:07:25.497267 individual files in /usr/share/doc/*/copyright.
10990 10:07:25.497783
10991 10:07:25.503618 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10992 10:07:25.506583 permitted by applicable law.
10993 10:07:25.507699 Matched prompt #10: / #
10995 10:07:25.508761 Setting prompt string to ['/ #']
10996 10:07:25.509426 end: 2.2.5.1 login-action (duration 00:00:21) [common]
10998 10:07:25.510442 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
10999 10:07:25.510882 start: 2.2.6 expect-shell-connection (timeout 00:02:49) [common]
11000 10:07:25.511247 Setting prompt string to ['/ #']
11001 10:07:25.511555 Forcing a shell prompt, looking for ['/ #']
11003 10:07:25.562390 / #
11004 10:07:25.562958 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11005 10:07:25.563353 Waiting using forced prompt support (timeout 00:02:30)
11006 10:07:25.568244
11007 10:07:25.568999 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11008 10:07:25.569455 start: 2.2.7 export-device-env (timeout 00:02:48) [common]
11009 10:07:25.569912 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11010 10:07:25.570349 end: 2.2 depthcharge-retry (duration 00:02:12) [common]
11011 10:07:25.570766 end: 2 depthcharge-action (duration 00:02:12) [common]
11012 10:07:25.571193 start: 3 lava-test-retry (timeout 00:07:26) [common]
11013 10:07:25.571618 start: 3.1 lava-test-shell (timeout 00:07:26) [common]
11014 10:07:25.571972 Using namespace: common
11016 10:07:25.672965 / # #
11017 10:07:25.673606 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11018 10:07:25.674281 <4>[ 19.924008] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11019 10:07:25.679145 #
11020 10:07:25.679848 Using /lava-10670700
11022 10:07:25.780933 / # export SHELL=/bin/sh
11023 10:07:25.781611 <4>[ 20.043657] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11024 10:07:25.786720 export SHELL=/bin/sh
11026 10:07:25.888324 / # . /lava-10670700/environment
11027 10:07:25.888479 <4>[ 20.163936] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11028 10:07:25.893762 . /lava-10670700/environment
11030 10:07:25.994408 / # /lava-10670700/bin/lava-test-runner /lava-10670700/0
11031 10:07:25.994938 Test shell timeout: 10s (minimum of the action and connection timeout)
11032 10:07:25.996476 <4>[ 20.283558] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11033 10:07:26.000403 /lava-10670700/bin/lava-test-runner /lava-10670700/0
11034 10:07:26.044346 + export TESTRUN_ID=0_igt-gpu-panf<8>[ 20.364772] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 10670700_1.5.2.3.1>
11035 10:07:26.044824 rost
11036 10:07:26.045157 + cd /lava-10670700/0/tests/0_igt-gpu-panfrost
11037 10:07:26.045473 + cat uuid
11038 10:07:26.046040 Received signal: <STARTRUN> 0_igt-gpu-panfrost 10670700_1.5.2.3.1
11039 10:07:26.046380 Starting test lava.0_igt-gpu-panfrost (10670700_1.5.2.3.1)
11040 10:07:26.046758 Skipping test definition patterns.
11041 10:07:26.047229 + UUID=10670700_1.5.2.3.1
11042 10:07:26.047558 + set +x
11043 10:07:26.047858 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11044 10:07:26.063082 <8>[ 20.403230] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11045 10:07:26.063751 Received signal: <TESTSET> START panfrost_gem_new
11046 10:07:26.064181 Starting test_set panfrost_gem_new
11047 10:07:26.069547 <3>[ 20.403657] mt7921e 0000:01:00.0: hardware init failed
11048 10:07:26.085719 <14>[ 20.426146] [IGT] panfrost_gem_new: executing
11049 10:07:26.095780 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.434175] [IGT] panfrost_gem_new: exiting, ret=77
11050 10:07:26.095863 .1.31 aarch64)
11051 10:07:26.108918 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.446691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11052 10:07:26.109172 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11054 10:07:26.111785 b/drmtest.c:621:
11055 10:07:26.111866 Test requirement: !(fd<0)
11056 10:07:26.118381 No known gpu found for chipset flags 0x32 (panfrost)
11057 10:07:26.122130 Last errno: 2, No such file or directory
11058 10:07:26.125311 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11059 10:07:26.131901 <14>[ 20.471865] [IGT] panfrost_gem_new: executing
11060 10:07:26.141661 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.480095] [IGT] panfrost_gem_new: exiting, ret=77
11061 10:07:26.141746 .1.31 aarch64)
11062 10:07:26.154835 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.492203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11063 10:07:26.154928 b/drmtest.c:621:
11064 10:07:26.155164 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11066 10:07:26.157933 Test requirement: !(fd<0)
11067 10:07:26.161389 No known gpu found for chipset flags 0x32 (panfrost)
11068 10:07:26.168311 Last errno: 2, No such file or directory
11069 10:07:26.171489 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11070 10:07:26.177901 <14>[ 20.518286] [IGT] panfrost_gem_new: executing
11071 10:07:26.188095 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.526591] [IGT] panfrost_gem_new: exiting, ret=77
11072 10:07:26.188682 .1.31 aarch64)
11073 10:07:26.201534 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.538492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11074 10:07:26.202107 b/drmtest.c:621:
11075 10:07:26.202895 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11077 10:07:26.208361 Test requireme<8>[ 20.548375] <LAVA_SIGNAL_TESTSET STOP>
11078 10:07:26.208783 nt: !(fd<0)
11079 10:07:26.209361 Received signal: <TESTSET> STOP
11080 10:07:26.209704 Closing test_set panfrost_gem_new
11081 10:07:26.214799 No known gpu found for chipset flags 0x32 (panfrost)
11082 10:07:26.218363 Last errno: 2, No such file or directory
11083 10:07:26.221210 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11084 10:07:26.234751 <8>[ 20.574929] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11085 10:07:26.235671 Received signal: <TESTSET> START panfrost_get_param
11086 10:07:26.236157 Starting test_set panfrost_get_param
11087 10:07:26.258502 <14>[ 20.598671] [IGT] panfrost_get_param: executing
11088 10:07:26.268422 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.607169] [IGT] panfrost_get_param: exiting, ret=77
11089 10:07:26.268882 .1.31 aarch64)
11090 10:07:26.281545 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.619529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11091 10:07:26.282245 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11093 10:07:26.284629 b/drmtest.c:621:
11094 10:07:26.285044 Test requirement: !(fd<0)
11095 10:07:26.291555 No known gpu found for chipset flags 0x32 (panfrost)
11096 10:07:26.294847 Last errno: 2, No such file or directory
11097 10:07:26.298296 [1mSubtest base-params: SKIP (0.000s)[0m
11098 10:07:26.305275 <14>[ 20.645709] [IGT] panfrost_get_param: executing
11099 10:07:26.315159 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.654118] [IGT] panfrost_get_param: exiting, ret=77
11100 10:07:26.315649 .1.31 aarch64)
11101 10:07:26.328669 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.666703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11102 10:07:26.329347 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11104 10:07:26.331812 b/drmtest.c:621:
11105 10:07:26.332273 Test requirement: !(fd<0)
11106 10:07:26.338494 No known gpu found for chipset flags 0x32 (panfrost)
11107 10:07:26.342178 Last errno: 2, No such file or directory
11108 10:07:26.344698 [1mSubtest get-bad-param: SKIP (0.000s)[0m
11109 10:07:26.352403 <14>[ 20.692719] [IGT] panfrost_get_param: executing
11110 10:07:26.362373 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.700958] [IGT] panfrost_get_param: exiting, ret=77
11111 10:07:26.362853 .1.31 aarch64)
11112 10:07:26.375204 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.713589] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11113 10:07:26.375888 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11115 10:07:26.379127 b/drmtest.c:621:
11116 10:07:26.382093 Test requireme<8>[ 20.723023] <LAVA_SIGNAL_TESTSET STOP>
11117 10:07:26.382761 Received signal: <TESTSET> STOP
11118 10:07:26.383108 Closing test_set panfrost_get_param
11119 10:07:26.385596 nt: !(fd<0)
11120 10:07:26.388509 No known gpu found for chipset flags 0x32 (panfrost)
11121 10:07:26.392115 Last errno: 2, No such file or directory
11122 10:07:26.395623 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11123 10:07:26.409276 <8>[ 20.749777] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11124 10:07:26.410014 Received signal: <TESTSET> START panfrost_prime
11125 10:07:26.410370 Starting test_set panfrost_prime
11126 10:07:26.432365 <14>[ 20.772445] [IGT] panfrost_prime: executing
11127 10:07:26.441626 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.780384] [IGT] panfrost_prime: exiting, ret=77
11128 10:07:26.442055 .1.31 aarch64)
11129 10:07:26.455593 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.792335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11130 10:07:26.456180 b/drmtest.c:621:
11131 10:07:26.456937 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11133 10:07:26.462176 Test requireme<8>[ 20.802295] <LAVA_SIGNAL_TESTSET STOP>
11134 10:07:26.463036 nt: !(fd<0)
11135 10:07:26.463850 Received signal: <TESTSET> STOP
11136 10:07:26.464428 Closing test_set panfrost_prime
11137 10:07:26.468360 No known gpu found for chipset flags 0x32 (panfrost)
11138 10:07:26.471503 Last errno: 2, No such file or directory
11139 10:07:26.474673 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11140 10:07:26.486953 <8>[ 20.827870] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11141 10:07:26.487239 Received signal: <TESTSET> START panfrost_submit
11142 10:07:26.487335 Starting test_set panfrost_submit
11143 10:07:26.510220 <14>[ 20.850515] [IGT] panfrost_submit: executing
11144 10:07:26.520007 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.858516] [IGT] panfrost_submit: exiting, ret=77
11145 10:07:26.520134 .1.31 aarch64)
11146 10:07:26.533027 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.870419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11147 10:07:26.533154 b/drmtest.c:621:
11148 10:07:26.533438 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11150 10:07:26.536166 Test requirement: !(fd<0)
11151 10:07:26.539610 No known gpu found for chipset flags 0x32 (panfrost)
11152 10:07:26.546549 Last errno: 2, No such file or directory
11153 10:07:26.549654 [1mSubtest pan-submit: SKIP (0.000s)[0m
11154 10:07:26.556319 <14>[ 20.895649] [IGT] panfrost_submit: executing
11155 10:07:26.562719 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.903649] [IGT] panfrost_submit: exiting, ret=77
11156 10:07:26.566091 .1.31 aarch64)
11157 10:07:26.579425 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.915566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11158 10:07:26.579734 b/drmtest.c:621:
11159 10:07:26.580198 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11161 10:07:26.583289 Test requirement: !(fd<0)
11162 10:07:26.586419 No known gpu found for chipset flags 0x32 (panfrost)
11163 10:07:26.593231 Last errno: 2, No such file or directory
11164 10:07:26.596364 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11165 10:07:26.599653 <14>[ 20.941769] [IGT] panfrost_submit: executing
11166 10:07:26.609443 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.949716] [IGT] panfrost_submit: exiting, ret=77
11167 10:07:26.612986 .1.31 aarch64)
11168 10:07:26.625903 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.961826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11169 10:07:26.626338 b/drmtest.c:621:
11170 10:07:26.626933 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11172 10:07:26.629627 Test requirement: !(fd<0)
11173 10:07:26.636366 No known gpu found for chipset flags 0x32 (panfrost)
11174 10:07:26.638912 Last errno: 2, No such file or directory
11175 10:07:26.642399 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11176 10:07:26.649231 <14>[ 20.988246] [IGT] panfrost_submit: executing
11177 10:07:26.659207 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.996768] [IGT] panfrost_submit: exiting, ret=77
11178 10:07:26.659766 .1.31 aarch64)
11179 10:07:26.672625 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.008938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11180 10:07:26.673449 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11182 10:07:26.675491 b/drmtest.c:621:
11183 10:07:26.676076 Test requirement: !(fd<0)
11184 10:07:26.682087 No known gpu found for chipset flags 0x32 (panfrost)
11185 10:07:26.685772 Last errno: 2, No such file or directory
11186 10:07:26.692370 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11187 10:07:26.695664 <14>[ 21.035755] [IGT] panfrost_submit: executing
11188 10:07:26.705375 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.044425] [IGT] panfrost_submit: exiting, ret=77
11189 10:07:26.705931 .1.31 aarch64)
11190 10:07:26.722181 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.056321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11191 10:07:26.722619 b/drmtest.c:621:
11192 10:07:26.723304 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11194 10:07:26.724980 Test requirement: !(fd<0)
11195 10:07:26.728899 No known gpu found for chipset flags 0x32 (panfrost)
11196 10:07:26.732095 Last errno: 2, No such file or directory
11197 10:07:26.738569 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11198 10:07:26.745010 <14>[ 21.083697] [IGT] panfrost_submit: executing
11199 10:07:26.751390 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.092182] [IGT] panfrost_submit: exiting, ret=77
11200 10:07:26.754739 .1.31 aarch64)
11201 10:07:26.768378 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.104288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11202 10:07:26.769083 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11204 10:07:26.771541 b/drmtest.c:621:
11205 10:07:26.772063 Test requirement: !(fd<0)
11206 10:07:26.778167 No known gpu found for chipset flags 0x32 (panfrost)
11207 10:07:26.781037 Last errno: 2, No such file or directory
11208 10:07:26.784418 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11209 10:07:26.791865 <14>[ 21.131885] [IGT] panfrost_submit: executing
11210 10:07:26.801375 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.140390] [IGT] panfrost_submit: exiting, ret=77
11211 10:07:26.801800 .1.31 aarch64)
11212 10:07:26.814385 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.152139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11213 10:07:26.814820 b/drmtest.c:621:
11214 10:07:26.815406 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11216 10:07:26.817926 Test requirement: !(fd<0)
11217 10:07:26.824789 No known gpu found for chipset flags 0x32 (panfrost)
11218 10:07:26.827620 Last errno: 2, No such file or directory
11219 10:07:26.831304 [1mSubtest pan-reset: SKIP (0.000s)[0m
11220 10:07:26.837891 <14>[ 21.176931] [IGT] panfrost_submit: executing
11221 10:07:26.844379 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.184896] [IGT] panfrost_submit: exiting, ret=77
11222 10:07:26.847949 .1.31 aarch64)
11223 10:07:26.860556 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.197031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11224 10:07:26.860986 b/drmtest.c:621:
11225 10:07:26.861572 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11227 10:07:26.864447 Test requirement: !(fd<0)
11228 10:07:26.867130 No known gpu found for chipset flags 0x32 (panfrost)
11229 10:07:26.873957 Last errno: 2, No such file or directory
11230 10:07:26.877097 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11231 10:07:26.884028 <14>[ 21.223044] [IGT] panfrost_submit: executing
11232 10:07:26.890438 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.231019] [IGT] panfrost_submit: exiting, ret=77
11233 10:07:26.894117 .1.31 aarch64)
11234 10:07:26.907350 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.243121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11235 10:07:26.907922 b/drmtest.c:621:
11236 10:07:26.908194 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11238 10:07:26.913143 Test requireme<8>[ 21.253883] <LAVA_SIGNAL_TESTSET STOP>
11239 10:07:26.913230 nt: !(fd<0)
11240 10:07:26.913500 Received signal: <TESTSET> STOP
11241 10:07:26.913599 Closing test_set panfrost_submit
11242 10:07:26.919738 No <8>[ 21.259537] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 10670700_1.5.2.3.1>
11243 10:07:26.920023 Received signal: <ENDRUN> 0_igt-gpu-panfrost 10670700_1.5.2.3.1
11244 10:07:26.920161 Ending use of test pattern.
11245 10:07:26.920235 Ending test lava.0_igt-gpu-panfrost (10670700_1.5.2.3.1), duration 0.87
11247 10:07:26.926766 known gpu found for chipset flags 0x32 (panfrost)
11248 10:07:26.929835 Last errno: 2, No such file or directory
11249 10:07:26.932976 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11250 10:07:26.936555 + set +x
11251 10:07:26.936683 <LAVA_TEST_RUNNER EXIT>
11252 10:07:26.936969 ok: lava_test_shell seems to have completed
11253 10:07:26.937317 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11254 10:07:26.937433 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11255 10:07:26.937530 end: 3 lava-test-retry (duration 00:00:01) [common]
11256 10:07:26.937630 start: 4 finalize (timeout 00:07:25) [common]
11257 10:07:26.937741 start: 4.1 power-off (timeout 00:00:30) [common]
11258 10:07:26.937936 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11259 10:07:27.016644 >> Command sent successfully.
11260 10:07:27.019299 Returned 0 in 0 seconds
11261 10:07:27.119703 end: 4.1 power-off (duration 00:00:00) [common]
11263 10:07:27.120068 start: 4.2 read-feedback (timeout 00:07:25) [common]
11264 10:07:27.120330 Listened to connection for namespace 'common' for up to 1s
11265 10:07:28.121470 Finalising connection for namespace 'common'
11266 10:07:28.122121 Disconnecting from shell: Finalise
11267 10:07:28.122526 / #
11268 10:07:28.223213 end: 4.2 read-feedback (duration 00:00:01) [common]
11269 10:07:28.223380 end: 4 finalize (duration 00:00:01) [common]
11270 10:07:28.223526 Cleaning after the job
11271 10:07:28.223620 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670700/tftp-deploy-0exqgs1y/ramdisk
11272 10:07:28.229463 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670700/tftp-deploy-0exqgs1y/kernel
11273 10:07:28.235166 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670700/tftp-deploy-0exqgs1y/dtb
11274 10:07:28.235320 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670700/tftp-deploy-0exqgs1y/modules
11275 10:07:28.240619 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10670700
11276 10:07:28.336356 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10670700
11277 10:07:28.336510 Job finished correctly