Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 34
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
- Errors: 0
1 10:04:42.784749 lava-dispatcher, installed at version: 2023.05.1
2 10:04:42.784978 start: 0 validate
3 10:04:42.785121 Start time: 2023-06-10 10:04:42.785107+00:00 (UTC)
4 10:04:42.785257 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:04:42.785393 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 10:04:43.054493 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:04:43.054704 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:04:43.320994 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:04:43.321195 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:04:43.580001 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:04:43.580183 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:04:43.846547 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:04:43.846711 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:04:44.105792 validate duration: 1.32
16 10:04:44.106060 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:04:44.106155 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:04:44.106244 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:04:44.106369 Not decompressing ramdisk as can be used compressed.
20 10:04:44.106454 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/initrd.cpio.gz
21 10:04:44.106518 saving as /var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/ramdisk/initrd.cpio.gz
22 10:04:44.106580 total size: 5624321 (5MB)
23 10:04:44.107617 progress 0% (0MB)
24 10:04:44.109119 progress 5% (0MB)
25 10:04:44.110646 progress 10% (0MB)
26 10:04:44.112080 progress 15% (0MB)
27 10:04:44.113612 progress 20% (1MB)
28 10:04:44.115012 progress 25% (1MB)
29 10:04:44.116590 progress 30% (1MB)
30 10:04:44.118136 progress 35% (1MB)
31 10:04:44.119525 progress 40% (2MB)
32 10:04:44.121194 progress 45% (2MB)
33 10:04:44.122596 progress 50% (2MB)
34 10:04:44.124196 progress 55% (2MB)
35 10:04:44.125534 progress 60% (3MB)
36 10:04:44.127149 progress 65% (3MB)
37 10:04:44.128780 progress 70% (3MB)
38 10:04:44.130151 progress 75% (4MB)
39 10:04:44.131702 progress 80% (4MB)
40 10:04:44.133100 progress 85% (4MB)
41 10:04:44.134694 progress 90% (4MB)
42 10:04:44.136260 progress 95% (5MB)
43 10:04:44.137666 progress 100% (5MB)
44 10:04:44.137858 5MB downloaded in 0.03s (171.51MB/s)
45 10:04:44.138014 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:04:44.138254 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:04:44.138341 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:04:44.138425 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:04:44.138557 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:04:44.138630 saving as /var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/kernel/Image
52 10:04:44.138690 total size: 45746688 (43MB)
53 10:04:44.138750 No compression specified
54 10:04:44.139928 progress 0% (0MB)
55 10:04:44.151526 progress 5% (2MB)
56 10:04:44.163256 progress 10% (4MB)
57 10:04:44.175035 progress 15% (6MB)
58 10:04:44.186719 progress 20% (8MB)
59 10:04:44.198382 progress 25% (10MB)
60 10:04:44.209933 progress 30% (13MB)
61 10:04:44.221503 progress 35% (15MB)
62 10:04:44.233170 progress 40% (17MB)
63 10:04:44.244883 progress 45% (19MB)
64 10:04:44.256685 progress 50% (21MB)
65 10:04:44.268318 progress 55% (24MB)
66 10:04:44.280090 progress 60% (26MB)
67 10:04:44.291759 progress 65% (28MB)
68 10:04:44.303433 progress 70% (30MB)
69 10:04:44.315058 progress 75% (32MB)
70 10:04:44.326443 progress 80% (34MB)
71 10:04:44.338099 progress 85% (37MB)
72 10:04:44.349760 progress 90% (39MB)
73 10:04:44.361321 progress 95% (41MB)
74 10:04:44.372884 progress 100% (43MB)
75 10:04:44.373056 43MB downloaded in 0.23s (186.15MB/s)
76 10:04:44.373213 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:04:44.373445 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:04:44.373538 start: 1.3 download-retry (timeout 00:10:00) [common]
80 10:04:44.373627 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 10:04:44.373758 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 10:04:44.373827 saving as /var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/dtb/mt8192-asurada-spherion-r0.dtb
83 10:04:44.373889 total size: 46924 (0MB)
84 10:04:44.373949 No compression specified
85 10:04:44.375098 progress 69% (0MB)
86 10:04:44.375403 progress 100% (0MB)
87 10:04:44.375573 0MB downloaded in 0.00s (26.62MB/s)
88 10:04:44.375696 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:04:44.375924 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:04:44.376010 start: 1.4 download-retry (timeout 00:10:00) [common]
92 10:04:44.376093 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 10:04:44.376203 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 10:04:44.376272 saving as /var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/nfsrootfs/full.rootfs.tar
95 10:04:44.376365 total size: 195125384 (186MB)
96 10:04:44.376448 Using unxz to decompress xz
97 10:04:44.380221 progress 0% (0MB)
98 10:04:44.922018 progress 5% (9MB)
99 10:04:45.416559 progress 10% (18MB)
100 10:04:45.991537 progress 15% (27MB)
101 10:04:46.263306 progress 20% (37MB)
102 10:04:46.706338 progress 25% (46MB)
103 10:04:47.264523 progress 30% (55MB)
104 10:04:47.810297 progress 35% (65MB)
105 10:04:48.357103 progress 40% (74MB)
106 10:04:48.917622 progress 45% (83MB)
107 10:04:49.512970 progress 50% (93MB)
108 10:04:50.107743 progress 55% (102MB)
109 10:04:50.746974 progress 60% (111MB)
110 10:04:51.138377 progress 65% (120MB)
111 10:04:51.217026 progress 70% (130MB)
112 10:04:51.366106 progress 75% (139MB)
113 10:04:51.438151 progress 80% (148MB)
114 10:04:51.483758 progress 85% (158MB)
115 10:04:51.571583 progress 90% (167MB)
116 10:04:51.938160 progress 95% (176MB)
117 10:04:52.497545 progress 100% (186MB)
118 10:04:52.503618 186MB downloaded in 8.13s (22.90MB/s)
119 10:04:52.503899 end: 1.4.1 http-download (duration 00:00:08) [common]
121 10:04:52.504153 end: 1.4 download-retry (duration 00:00:08) [common]
122 10:04:52.504263 start: 1.5 download-retry (timeout 00:09:52) [common]
123 10:04:52.504351 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 10:04:52.504501 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:04:52.504571 saving as /var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/modules/modules.tar
126 10:04:52.504632 total size: 8540248 (8MB)
127 10:04:52.504694 Using unxz to decompress xz
128 10:04:52.508260 progress 0% (0MB)
129 10:04:52.530064 progress 5% (0MB)
130 10:04:52.554081 progress 10% (0MB)
131 10:04:52.577604 progress 15% (1MB)
132 10:04:52.606401 progress 20% (1MB)
133 10:04:52.630427 progress 25% (2MB)
134 10:04:52.652606 progress 30% (2MB)
135 10:04:52.677502 progress 35% (2MB)
136 10:04:52.701654 progress 40% (3MB)
137 10:04:52.724713 progress 45% (3MB)
138 10:04:52.750806 progress 50% (4MB)
139 10:04:52.774603 progress 55% (4MB)
140 10:04:52.799792 progress 60% (4MB)
141 10:04:52.824904 progress 65% (5MB)
142 10:04:52.849185 progress 70% (5MB)
143 10:04:52.872546 progress 75% (6MB)
144 10:04:52.895232 progress 80% (6MB)
145 10:04:52.918663 progress 85% (6MB)
146 10:04:52.946584 progress 90% (7MB)
147 10:04:52.970927 progress 95% (7MB)
148 10:04:52.995146 progress 100% (8MB)
149 10:04:53.000325 8MB downloaded in 0.50s (16.43MB/s)
150 10:04:53.000580 end: 1.5.1 http-download (duration 00:00:00) [common]
152 10:04:53.000836 end: 1.5 download-retry (duration 00:00:00) [common]
153 10:04:53.000926 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 10:04:53.001016 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 10:04:56.252182 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10670699/extract-nfsrootfs-1ly9ggbb
156 10:04:56.252391 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 10:04:56.252492 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 10:04:56.252665 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s
159 10:04:56.252791 makedir: /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin
160 10:04:56.252893 makedir: /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/tests
161 10:04:56.252988 makedir: /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/results
162 10:04:56.253089 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-add-keys
163 10:04:56.253230 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-add-sources
164 10:04:56.253354 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-background-process-start
165 10:04:56.253478 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-background-process-stop
166 10:04:56.253599 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-common-functions
167 10:04:56.253718 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-echo-ipv4
168 10:04:56.253838 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-install-packages
169 10:04:56.253957 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-installed-packages
170 10:04:56.254076 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-os-build
171 10:04:56.254195 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-probe-channel
172 10:04:56.254321 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-probe-ip
173 10:04:56.254439 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-target-ip
174 10:04:56.254558 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-target-mac
175 10:04:56.254675 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-target-storage
176 10:04:56.254796 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-test-case
177 10:04:56.254914 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-test-event
178 10:04:56.255032 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-test-feedback
179 10:04:56.255150 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-test-raise
180 10:04:56.255267 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-test-reference
181 10:04:56.255614 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-test-runner
182 10:04:56.255749 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-test-set
183 10:04:56.255872 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-test-shell
184 10:04:56.255995 Updating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-add-keys (debian)
185 10:04:56.256143 Updating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-add-sources (debian)
186 10:04:56.256288 Updating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-install-packages (debian)
187 10:04:56.256426 Updating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-installed-packages (debian)
188 10:04:56.256566 Updating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/bin/lava-os-build (debian)
189 10:04:56.256683 Creating /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/environment
190 10:04:56.256787 LAVA metadata
191 10:04:56.256857 - LAVA_JOB_ID=10670699
192 10:04:56.256919 - LAVA_DISPATCHER_IP=192.168.201.1
193 10:04:56.257017 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 10:04:56.257083 skipped lava-vland-overlay
195 10:04:56.257155 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 10:04:56.257233 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 10:04:56.257292 skipped lava-multinode-overlay
198 10:04:56.257363 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 10:04:56.257439 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 10:04:56.257510 Loading test definitions
201 10:04:56.257625 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 10:04:56.257727 Using /lava-10670699 at stage 0
203 10:04:56.258012 uuid=10670699_1.6.2.3.1 testdef=None
204 10:04:56.258100 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 10:04:56.258185 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 10:04:56.258616 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 10:04:56.258837 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 10:04:56.259423 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 10:04:56.259706 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 10:04:56.260233 runner path: /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/0/tests/0_timesync-off test_uuid 10670699_1.6.2.3.1
213 10:04:56.260382 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 10:04:56.260603 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 10:04:56.260676 Using /lava-10670699 at stage 0
217 10:04:56.260771 Fetching tests from https://github.com/kernelci/test-definitions.git
218 10:04:56.260847 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/0/tests/1_kselftest-alsa'
219 10:05:00.751287 Running '/usr/bin/git checkout kernelci.org
220 10:05:00.892417 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 10:05:00.893121 uuid=10670699_1.6.2.3.5 testdef=None
222 10:05:00.893280 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 10:05:00.893528 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 10:05:00.894248 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 10:05:00.894480 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 10:05:00.895476 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 10:05:00.895709 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 10:05:00.896615 runner path: /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/0/tests/1_kselftest-alsa test_uuid 10670699_1.6.2.3.5
232 10:05:00.896707 BOARD='mt8192-asurada-spherion-r0'
233 10:05:00.896773 BRANCH='cip'
234 10:05:00.896833 SKIPFILE='/dev/null'
235 10:05:00.896891 SKIP_INSTALL='True'
236 10:05:00.896947 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 10:05:00.897004 TST_CASENAME=''
238 10:05:00.897059 TST_CMDFILES='alsa'
239 10:05:00.897198 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 10:05:00.897398 Creating lava-test-runner.conf files
242 10:05:00.897460 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10670699/lava-overlay-3kstnq2s/lava-10670699/0 for stage 0
243 10:05:00.897550 - 0_timesync-off
244 10:05:00.897619 - 1_kselftest-alsa
245 10:05:00.897713 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 10:05:00.897802 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 10:05:08.744969 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 10:05:08.745174 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 10:05:08.745401 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 10:05:08.745550 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 10:05:08.745683 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 10:05:08.916262 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 10:05:08.916637 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 10:05:08.916797 extracting modules file /var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670699/extract-nfsrootfs-1ly9ggbb
255 10:05:09.186076 extracting modules file /var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670699/extract-overlay-ramdisk-yvwevu_b/ramdisk
256 10:05:09.484198 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 10:05:09.484383 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 10:05:09.484496 [common] Applying overlay to NFS
259 10:05:09.484593 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670699/compress-overlay-opjspr8k/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10670699/extract-nfsrootfs-1ly9ggbb
260 10:05:10.488567 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 10:05:10.488737 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 10:05:10.488873 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 10:05:10.489004 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 10:05:10.489095 Building ramdisk /var/lib/lava/dispatcher/tmp/10670699/extract-overlay-ramdisk-yvwevu_b/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10670699/extract-overlay-ramdisk-yvwevu_b/ramdisk
265 10:05:10.863361 >> 128929 blocks
266 10:05:12.904685 rename /var/lib/lava/dispatcher/tmp/10670699/extract-overlay-ramdisk-yvwevu_b/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/ramdisk/ramdisk.cpio.gz
267 10:05:12.905123 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 10:05:12.905250 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 10:05:12.905350 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 10:05:12.905456 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/kernel/Image'
271 10:05:26.369238 Returned 0 in 13 seconds
272 10:05:26.469877 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/kernel/image.itb
273 10:05:27.235286 output: FIT description: Kernel Image image with one or more FDT blobs
274 10:05:27.235743 output: Created: Sat Jun 10 11:05:27 2023
275 10:05:27.235853 output: Image 0 (kernel-1)
276 10:05:27.235928 output: Description:
277 10:05:27.235991 output: Created: Sat Jun 10 11:05:27 2023
278 10:05:27.236057 output: Type: Kernel Image
279 10:05:27.236118 output: Compression: lzma compressed
280 10:05:27.236179 output: Data Size: 10087317 Bytes = 9850.90 KiB = 9.62 MiB
281 10:05:27.236238 output: Architecture: AArch64
282 10:05:27.236301 output: OS: Linux
283 10:05:27.236359 output: Load Address: 0x00000000
284 10:05:27.236418 output: Entry Point: 0x00000000
285 10:05:27.236476 output: Hash algo: crc32
286 10:05:27.236531 output: Hash value: c9e456fd
287 10:05:27.236585 output: Image 1 (fdt-1)
288 10:05:27.236638 output: Description: mt8192-asurada-spherion-r0
289 10:05:27.236693 output: Created: Sat Jun 10 11:05:27 2023
290 10:05:27.236746 output: Type: Flat Device Tree
291 10:05:27.236800 output: Compression: uncompressed
292 10:05:27.236886 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 10:05:27.236971 output: Architecture: AArch64
294 10:05:27.237074 output: Hash algo: crc32
295 10:05:27.237143 output: Hash value: 1df858fa
296 10:05:27.237196 output: Image 2 (ramdisk-1)
297 10:05:27.237250 output: Description: unavailable
298 10:05:27.237303 output: Created: Sat Jun 10 11:05:27 2023
299 10:05:27.237357 output: Type: RAMDisk Image
300 10:05:27.237411 output: Compression: Unknown Compression
301 10:05:27.237464 output: Data Size: 18600031 Bytes = 18164.09 KiB = 17.74 MiB
302 10:05:27.237518 output: Architecture: AArch64
303 10:05:27.237571 output: OS: Linux
304 10:05:27.237624 output: Load Address: unavailable
305 10:05:27.237678 output: Entry Point: unavailable
306 10:05:27.237731 output: Hash algo: crc32
307 10:05:27.237783 output: Hash value: d51949b8
308 10:05:27.237837 output: Default Configuration: 'conf-1'
309 10:05:27.237890 output: Configuration 0 (conf-1)
310 10:05:27.237944 output: Description: mt8192-asurada-spherion-r0
311 10:05:27.237997 output: Kernel: kernel-1
312 10:05:27.238051 output: Init Ramdisk: ramdisk-1
313 10:05:27.238104 output: FDT: fdt-1
314 10:05:27.238157 output: Loadables: kernel-1
315 10:05:27.238211 output:
316 10:05:27.238409 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 10:05:27.238507 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 10:05:27.238608 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 10:05:27.238708 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:17) [common]
320 10:05:27.238791 No LXC device requested
321 10:05:27.238872 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 10:05:27.238959 start: 1.8 deploy-device-env (timeout 00:09:17) [common]
323 10:05:27.239056 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 10:05:27.239129 Checking files for TFTP limit of 4294967296 bytes.
325 10:05:27.239712 end: 1 tftp-deploy (duration 00:00:43) [common]
326 10:05:27.239844 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 10:05:27.239972 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 10:05:27.240153 substitutions:
329 10:05:27.240261 - {DTB}: 10670699/tftp-deploy-9imtukcw/dtb/mt8192-asurada-spherion-r0.dtb
330 10:05:27.240366 - {INITRD}: 10670699/tftp-deploy-9imtukcw/ramdisk/ramdisk.cpio.gz
331 10:05:27.240459 - {KERNEL}: 10670699/tftp-deploy-9imtukcw/kernel/Image
332 10:05:27.240551 - {LAVA_MAC}: None
333 10:05:27.240637 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10670699/extract-nfsrootfs-1ly9ggbb
334 10:05:27.240717 - {NFS_SERVER_IP}: 192.168.201.1
335 10:05:27.240777 - {PRESEED_CONFIG}: None
336 10:05:27.240836 - {PRESEED_LOCAL}: None
337 10:05:27.240893 - {RAMDISK}: 10670699/tftp-deploy-9imtukcw/ramdisk/ramdisk.cpio.gz
338 10:05:27.240950 - {ROOT_PART}: None
339 10:05:27.241007 - {ROOT}: None
340 10:05:27.241062 - {SERVER_IP}: 192.168.201.1
341 10:05:27.241117 - {TEE}: None
342 10:05:27.241175 Parsed boot commands:
343 10:05:27.241229 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 10:05:27.241414 Parsed boot commands: tftpboot 192.168.201.1 10670699/tftp-deploy-9imtukcw/kernel/image.itb 10670699/tftp-deploy-9imtukcw/kernel/cmdline
345 10:05:27.241508 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 10:05:27.241593 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 10:05:27.241689 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 10:05:27.241775 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 10:05:27.241853 Not connected, no need to disconnect.
350 10:05:27.241928 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 10:05:27.242012 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 10:05:27.242084 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
353 10:05:27.245745 Setting prompt string to ['lava-test: # ']
354 10:05:27.246141 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 10:05:27.246276 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 10:05:27.246376 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 10:05:27.246498 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 10:05:27.246829 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
359 10:05:32.380319 >> Command sent successfully.
360 10:05:32.382601 Returned 0 in 5 seconds
361 10:05:32.482990 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 10:05:32.483423 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 10:05:32.483531 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 10:05:32.483626 Setting prompt string to 'Starting depthcharge on Spherion...'
366 10:05:32.483695 Changing prompt to 'Starting depthcharge on Spherion...'
367 10:05:32.483769 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 10:05:32.484030 [Enter `^Ec?' for help]
369 10:05:32.657809
370 10:05:32.657949
371 10:05:32.658017 F0: 102B 0000
372 10:05:32.658081
373 10:05:32.658142 F3: 1001 0000 [0200]
374 10:05:32.661100
375 10:05:32.661185 F3: 1001 0000
376 10:05:32.661252
377 10:05:32.661315 F7: 102D 0000
378 10:05:32.661375
379 10:05:32.664523 F1: 0000 0000
380 10:05:32.664608
381 10:05:32.664675 V0: 0000 0000 [0001]
382 10:05:32.664737
383 10:05:32.667975 00: 0007 8000
384 10:05:32.668061
385 10:05:32.668128 01: 0000 0000
386 10:05:32.668192
387 10:05:32.670881 BP: 0C00 0209 [0000]
388 10:05:32.670965
389 10:05:32.671031 G0: 1182 0000
390 10:05:32.671093
391 10:05:32.674720 EC: 0000 0021 [4000]
392 10:05:32.674804
393 10:05:32.674870 S7: 0000 0000 [0000]
394 10:05:32.674932
395 10:05:32.677815 CC: 0000 0000 [0001]
396 10:05:32.677899
397 10:05:32.677965 T0: 0000 0040 [010F]
398 10:05:32.678032
399 10:05:32.681425 Jump to BL
400 10:05:32.681509
401 10:05:32.704855
402 10:05:32.704947
403 10:05:32.705014
404 10:05:32.711514 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 10:05:32.714781 ARM64: Exception handlers installed.
406 10:05:32.718617 ARM64: Testing exception
407 10:05:32.721565 ARM64: Done test exception
408 10:05:32.728532 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 10:05:32.738900 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 10:05:32.745242 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 10:05:32.755525 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 10:05:32.762065 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 10:05:32.772187 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 10:05:32.783199 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 10:05:32.790137 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 10:05:32.807386 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 10:05:32.811020 WDT: Last reset was cold boot
418 10:05:32.814017 SPI1(PAD0) initialized at 2873684 Hz
419 10:05:32.817304 SPI5(PAD0) initialized at 992727 Hz
420 10:05:32.820813 VBOOT: Loading verstage.
421 10:05:32.827571 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 10:05:32.831060 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 10:05:32.834160 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 10:05:32.837448 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 10:05:32.845310 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 10:05:32.851558 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 10:05:32.862714 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 10:05:32.862798
429 10:05:32.862864
430 10:05:32.872514 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 10:05:32.876262 ARM64: Exception handlers installed.
432 10:05:32.878985 ARM64: Testing exception
433 10:05:32.879068 ARM64: Done test exception
434 10:05:32.885936 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 10:05:32.888974 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 10:05:32.903375 Probing TPM: . done!
437 10:05:32.903460 TPM ready after 0 ms
438 10:05:32.909867 Connected to device vid:did:rid of 1ae0:0028:00
439 10:05:32.920283 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 10:05:32.977271 Initialized TPM device CR50 revision 0
441 10:05:32.989349 tlcl_send_startup: Startup return code is 0
442 10:05:32.989465 TPM: setup succeeded
443 10:05:33.000796 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 10:05:33.009706 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 10:05:33.021624 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 10:05:33.031877 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 10:05:33.034977 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 10:05:33.038590 in-header: 03 07 00 00 08 00 00 00
449 10:05:33.042163 in-data: aa e4 47 04 13 02 00 00
450 10:05:33.045670 Chrome EC: UHEPI supported
451 10:05:33.052895 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 10:05:33.056797 in-header: 03 ad 00 00 08 00 00 00
453 10:05:33.060111 in-data: 00 20 20 08 00 00 00 00
454 10:05:33.060190 Phase 1
455 10:05:33.064123 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 10:05:33.070387 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 10:05:33.074451 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 10:05:33.078037 Recovery requested (1009000e)
459 10:05:33.087920 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 10:05:33.093509 tlcl_extend: response is 0
461 10:05:33.103799 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 10:05:33.109452 tlcl_extend: response is 0
463 10:05:33.116589 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 10:05:33.136864 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 10:05:33.143756 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 10:05:33.143879
467 10:05:33.143973
468 10:05:33.153908 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 10:05:33.158186 ARM64: Exception handlers installed.
470 10:05:33.158268 ARM64: Testing exception
471 10:05:33.160578 ARM64: Done test exception
472 10:05:33.182273 pmic_efuse_setting: Set efuses in 11 msecs
473 10:05:33.185686 pmwrap_interface_init: Select PMIF_VLD_RDY
474 10:05:33.192652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 10:05:33.195767 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 10:05:33.199778 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 10:05:33.207247 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 10:05:33.210825 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 10:05:33.214212 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 10:05:33.220680 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 10:05:33.224237 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 10:05:33.231677 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 10:05:33.235024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 10:05:33.238673 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 10:05:33.242353 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 10:05:33.249525 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 10:05:33.252926 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 10:05:33.260358 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 10:05:33.267921 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 10:05:33.271320 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 10:05:33.278358 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 10:05:33.282041 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 10:05:33.289783 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 10:05:33.293102 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 10:05:33.301274 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 10:05:33.304775 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 10:05:33.312169 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 10:05:33.316482 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 10:05:33.323490 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 10:05:33.327076 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 10:05:33.330746 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 10:05:33.334313 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 10:05:33.341919 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 10:05:33.345582 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 10:05:33.352345 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 10:05:33.356356 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 10:05:33.359592 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 10:05:33.367412 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 10:05:33.371058 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 10:05:33.378319 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 10:05:33.381648 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 10:05:33.385629 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 10:05:33.388851 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 10:05:33.392529 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 10:05:33.399882 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 10:05:33.403325 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 10:05:33.407150 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 10:05:33.410782 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 10:05:33.417602 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 10:05:33.421224 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 10:05:33.424913 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 10:05:33.428543 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 10:05:33.432130 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 10:05:33.436296 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 10:05:33.446664 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 10:05:33.453858 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 10:05:33.458081 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 10:05:33.465269 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 10:05:33.476293 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 10:05:33.479500 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 10:05:33.482913 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 10:05:33.486677 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 10:05:33.494630 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0xe
534 10:05:33.501471 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 10:05:33.505545 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 10:05:33.509274 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 10:05:33.519247 [RTC]rtc_get_frequency_meter,154: input=15, output=788
538 10:05:33.529229 [RTC]rtc_get_frequency_meter,154: input=23, output=978
539 10:05:33.538525 [RTC]rtc_get_frequency_meter,154: input=19, output=884
540 10:05:33.547891 [RTC]rtc_get_frequency_meter,154: input=17, output=837
541 10:05:33.557586 [RTC]rtc_get_frequency_meter,154: input=16, output=813
542 10:05:33.566617 [RTC]rtc_get_frequency_meter,154: input=15, output=790
543 10:05:33.576986 [RTC]rtc_get_frequency_meter,154: input=16, output=812
544 10:05:33.581287 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 10:05:33.584943 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
546 10:05:33.589052 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 10:05:33.595706 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 10:05:33.599462 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 10:05:33.603240 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 10:05:33.607323 ADC[4]: Raw value=901697 ID=7
551 10:05:33.607434 ADC[3]: Raw value=213336 ID=1
552 10:05:33.610723 RAM Code: 0x71
553 10:05:33.614626 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 10:05:33.617986 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 10:05:33.629424 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 10:05:33.633117 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 10:05:33.637094 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 10:05:33.640535 in-header: 03 07 00 00 08 00 00 00
559 10:05:33.644240 in-data: aa e4 47 04 13 02 00 00
560 10:05:33.647743 Chrome EC: UHEPI supported
561 10:05:33.651542 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 10:05:33.655560 in-header: 03 ed 00 00 08 00 00 00
563 10:05:33.659261 in-data: 80 20 60 08 00 00 00 00
564 10:05:33.663079 MRC: failed to locate region type 0.
565 10:05:33.670392 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 10:05:33.674035 DRAM-K: Running full calibration
567 10:05:33.677740 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 10:05:33.681231 header.status = 0x0
569 10:05:33.685521 header.version = 0x6 (expected: 0x6)
570 10:05:33.688711 header.size = 0xd00 (expected: 0xd00)
571 10:05:33.688831 header.flags = 0x0
572 10:05:33.696056 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 10:05:33.713754 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 10:05:33.721161 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 10:05:33.724807 dram_init: ddr_geometry: 2
576 10:05:33.724892 [EMI] MDL number = 2
577 10:05:33.728335 [EMI] Get MDL freq = 0
578 10:05:33.728457 dram_init: ddr_type: 0
579 10:05:33.732037 is_discrete_lpddr4: 1
580 10:05:33.735879 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 10:05:33.735982
582 10:05:33.736087
583 10:05:33.736164 [Bian_co] ETT version 0.0.0.1
584 10:05:33.743030 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 10:05:33.743115
586 10:05:33.746575 dramc_set_vcore_voltage set vcore to 650000
587 10:05:33.746658 Read voltage for 800, 4
588 10:05:33.750203 Vio18 = 0
589 10:05:33.750289 Vcore = 650000
590 10:05:33.750385 Vdram = 0
591 10:05:33.753996 Vddq = 0
592 10:05:33.754131 Vmddr = 0
593 10:05:33.754234 dram_init: config_dvfs: 1
594 10:05:33.760950 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 10:05:33.764648 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 10:05:33.771210 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
597 10:05:33.774889 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
598 10:05:33.777978 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
599 10:05:33.781598 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
600 10:05:33.784556 MEM_TYPE=3, freq_sel=18
601 10:05:33.788283 sv_algorithm_assistance_LP4_1600
602 10:05:33.791379 ============ PULL DRAM RESETB DOWN ============
603 10:05:33.795086 ========== PULL DRAM RESETB DOWN end =========
604 10:05:33.798171 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 10:05:33.801124 ===================================
606 10:05:33.804833 LPDDR4 DRAM CONFIGURATION
607 10:05:33.807721 ===================================
608 10:05:33.811229 EX_ROW_EN[0] = 0x0
609 10:05:33.811329 EX_ROW_EN[1] = 0x0
610 10:05:33.814810 LP4Y_EN = 0x0
611 10:05:33.814905 WORK_FSP = 0x0
612 10:05:33.817769 WL = 0x2
613 10:05:33.817852 RL = 0x2
614 10:05:33.821137 BL = 0x2
615 10:05:33.821220 RPST = 0x0
616 10:05:33.824665 RD_PRE = 0x0
617 10:05:33.824747 WR_PRE = 0x1
618 10:05:33.828446 WR_PST = 0x0
619 10:05:33.828529 DBI_WR = 0x0
620 10:05:33.831147 DBI_RD = 0x0
621 10:05:33.831231 OTF = 0x1
622 10:05:33.834647 ===================================
623 10:05:33.838032 ===================================
624 10:05:33.841222 ANA top config
625 10:05:33.844677 ===================================
626 10:05:33.848139 DLL_ASYNC_EN = 0
627 10:05:33.848219 ALL_SLAVE_EN = 1
628 10:05:33.851461 NEW_RANK_MODE = 1
629 10:05:33.855222 DLL_IDLE_MODE = 1
630 10:05:33.858232 LP45_APHY_COMB_EN = 1
631 10:05:33.858312 TX_ODT_DIS = 1
632 10:05:33.861726 NEW_8X_MODE = 1
633 10:05:33.865083 ===================================
634 10:05:33.868252 ===================================
635 10:05:33.871852 data_rate = 1600
636 10:05:33.874854 CKR = 1
637 10:05:33.878288 DQ_P2S_RATIO = 8
638 10:05:33.881959 ===================================
639 10:05:33.882037 CA_P2S_RATIO = 8
640 10:05:33.884960 DQ_CA_OPEN = 0
641 10:05:33.888582 DQ_SEMI_OPEN = 0
642 10:05:33.891581 CA_SEMI_OPEN = 0
643 10:05:33.895210 CA_FULL_RATE = 0
644 10:05:33.898231 DQ_CKDIV4_EN = 1
645 10:05:33.898312 CA_CKDIV4_EN = 1
646 10:05:33.902005 CA_PREDIV_EN = 0
647 10:05:33.905193 PH8_DLY = 0
648 10:05:33.908824 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 10:05:33.911968 DQ_AAMCK_DIV = 4
650 10:05:33.915284 CA_AAMCK_DIV = 4
651 10:05:33.915430 CA_ADMCK_DIV = 4
652 10:05:33.918232 DQ_TRACK_CA_EN = 0
653 10:05:33.921451 CA_PICK = 800
654 10:05:33.924815 CA_MCKIO = 800
655 10:05:33.928912 MCKIO_SEMI = 0
656 10:05:33.932364 PLL_FREQ = 3068
657 10:05:33.932447 DQ_UI_PI_RATIO = 32
658 10:05:33.935721 CA_UI_PI_RATIO = 0
659 10:05:33.939216 ===================================
660 10:05:33.942882 ===================================
661 10:05:33.946722 memory_type:LPDDR4
662 10:05:33.946812 GP_NUM : 10
663 10:05:33.950112 SRAM_EN : 1
664 10:05:33.950195 MD32_EN : 0
665 10:05:33.954257 ===================================
666 10:05:33.957678 [ANA_INIT] >>>>>>>>>>>>>>
667 10:05:33.961384 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 10:05:33.964742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 10:05:33.968398 ===================================
670 10:05:33.968529 data_rate = 1600,PCW = 0X7600
671 10:05:33.971508 ===================================
672 10:05:33.975073 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 10:05:33.981606 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 10:05:33.988172 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 10:05:33.991909 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 10:05:33.995057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 10:05:33.998687 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 10:05:34.001940 [ANA_INIT] flow start
679 10:05:34.002024 [ANA_INIT] PLL >>>>>>>>
680 10:05:34.004901 [ANA_INIT] PLL <<<<<<<<
681 10:05:34.008277 [ANA_INIT] MIDPI >>>>>>>>
682 10:05:34.011358 [ANA_INIT] MIDPI <<<<<<<<
683 10:05:34.011474 [ANA_INIT] DLL >>>>>>>>
684 10:05:34.015003 [ANA_INIT] flow end
685 10:05:34.018128 ============ LP4 DIFF to SE enter ============
686 10:05:34.021607 ============ LP4 DIFF to SE exit ============
687 10:05:34.025046 [ANA_INIT] <<<<<<<<<<<<<
688 10:05:34.028021 [Flow] Enable top DCM control >>>>>
689 10:05:34.031485 [Flow] Enable top DCM control <<<<<
690 10:05:34.034792 Enable DLL master slave shuffle
691 10:05:34.041286 ==============================================================
692 10:05:34.041370 Gating Mode config
693 10:05:34.048233 ==============================================================
694 10:05:34.048318 Config description:
695 10:05:34.058383 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 10:05:34.064683 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 10:05:34.071774 SELPH_MODE 0: By rank 1: By Phase
698 10:05:34.074882 ==============================================================
699 10:05:34.078285 GAT_TRACK_EN = 1
700 10:05:34.081473 RX_GATING_MODE = 2
701 10:05:34.084976 RX_GATING_TRACK_MODE = 2
702 10:05:34.088546 SELPH_MODE = 1
703 10:05:34.091661 PICG_EARLY_EN = 1
704 10:05:34.095119 VALID_LAT_VALUE = 1
705 10:05:34.098160 ==============================================================
706 10:05:34.101810 Enter into Gating configuration >>>>
707 10:05:34.105042 Exit from Gating configuration <<<<
708 10:05:34.108736 Enter into DVFS_PRE_config >>>>>
709 10:05:34.121901 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 10:05:34.122031 Exit from DVFS_PRE_config <<<<<
711 10:05:34.125241 Enter into PICG configuration >>>>
712 10:05:34.128211 Exit from PICG configuration <<<<
713 10:05:34.131910 [RX_INPUT] configuration >>>>>
714 10:05:34.135357 [RX_INPUT] configuration <<<<<
715 10:05:34.141615 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 10:05:34.145472 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 10:05:34.151870 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 10:05:34.159227 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 10:05:34.165510 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 10:05:34.168653 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 10:05:34.175709 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 10:05:34.178831 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 10:05:34.182430 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 10:05:34.185334 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 10:05:34.192502 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 10:05:34.195516 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 10:05:34.198688 ===================================
728 10:05:34.202239 LPDDR4 DRAM CONFIGURATION
729 10:05:34.205810 ===================================
730 10:05:34.205895 EX_ROW_EN[0] = 0x0
731 10:05:34.208880 EX_ROW_EN[1] = 0x0
732 10:05:34.208964 LP4Y_EN = 0x0
733 10:05:34.212573 WORK_FSP = 0x0
734 10:05:34.212658 WL = 0x2
735 10:05:34.215589 RL = 0x2
736 10:05:34.215673 BL = 0x2
737 10:05:34.219297 RPST = 0x0
738 10:05:34.219429 RD_PRE = 0x0
739 10:05:34.222375 WR_PRE = 0x1
740 10:05:34.222486 WR_PST = 0x0
741 10:05:34.225948 DBI_WR = 0x0
742 10:05:34.226027 DBI_RD = 0x0
743 10:05:34.228920 OTF = 0x1
744 10:05:34.232463 ===================================
745 10:05:34.235234 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 10:05:34.238952 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 10:05:34.245838 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 10:05:34.248893 ===================================
749 10:05:34.248973 LPDDR4 DRAM CONFIGURATION
750 10:05:34.252474 ===================================
751 10:05:34.255883 EX_ROW_EN[0] = 0x10
752 10:05:34.259084 EX_ROW_EN[1] = 0x0
753 10:05:34.259210 LP4Y_EN = 0x0
754 10:05:34.262420 WORK_FSP = 0x0
755 10:05:34.262519 WL = 0x2
756 10:05:34.265401 RL = 0x2
757 10:05:34.265501 BL = 0x2
758 10:05:34.269488 RPST = 0x0
759 10:05:34.269602 RD_PRE = 0x0
760 10:05:34.272691 WR_PRE = 0x1
761 10:05:34.272799 WR_PST = 0x0
762 10:05:34.275258 DBI_WR = 0x0
763 10:05:34.275379 DBI_RD = 0x0
764 10:05:34.279043 OTF = 0x1
765 10:05:34.282416 ===================================
766 10:05:34.289012 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 10:05:34.291965 nWR fixed to 40
768 10:05:34.292069 [ModeRegInit_LP4] CH0 RK0
769 10:05:34.295443 [ModeRegInit_LP4] CH0 RK1
770 10:05:34.299156 [ModeRegInit_LP4] CH1 RK0
771 10:05:34.302348 [ModeRegInit_LP4] CH1 RK1
772 10:05:34.302450 match AC timing 13
773 10:05:34.306000 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 10:05:34.312763 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 10:05:34.315816 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 10:05:34.319084 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 10:05:34.325771 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 10:05:34.325858 [EMI DOE] emi_dcm 0
779 10:05:34.332474 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 10:05:34.332558 ==
781 10:05:34.335922 Dram Type= 6, Freq= 0, CH_0, rank 0
782 10:05:34.338863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 10:05:34.338947 ==
784 10:05:34.346184 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 10:05:34.349092 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 10:05:34.359177 [CA 0] Center 37 (7~68) winsize 62
787 10:05:34.362491 [CA 1] Center 37 (6~68) winsize 63
788 10:05:34.365844 [CA 2] Center 35 (5~66) winsize 62
789 10:05:34.369115 [CA 3] Center 35 (4~66) winsize 63
790 10:05:34.372630 [CA 4] Center 34 (4~65) winsize 62
791 10:05:34.376042 [CA 5] Center 33 (3~64) winsize 62
792 10:05:34.376131
793 10:05:34.379319 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 10:05:34.379465
795 10:05:34.381989 [CATrainingPosCal] consider 1 rank data
796 10:05:34.385489 u2DelayCellTimex100 = 270/100 ps
797 10:05:34.388778 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 10:05:34.392675 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 10:05:34.399058 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 10:05:34.402298 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 10:05:34.405464 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
802 10:05:34.408815 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 10:05:34.408900
804 10:05:34.412546 CA PerBit enable=1, Macro0, CA PI delay=33
805 10:05:34.412635
806 10:05:34.415633 [CBTSetCACLKResult] CA Dly = 33
807 10:05:34.415711 CS Dly: 6 (0~37)
808 10:05:34.419076 ==
809 10:05:34.422617 Dram Type= 6, Freq= 0, CH_0, rank 1
810 10:05:34.425566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 10:05:34.425641 ==
812 10:05:34.429160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 10:05:34.435888 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 10:05:34.445739 [CA 0] Center 37 (6~68) winsize 63
815 10:05:34.448798 [CA 1] Center 37 (7~68) winsize 62
816 10:05:34.452113 [CA 2] Center 35 (4~66) winsize 63
817 10:05:34.455604 [CA 3] Center 34 (4~65) winsize 62
818 10:05:34.458703 [CA 4] Center 34 (3~65) winsize 63
819 10:05:34.462080 [CA 5] Center 33 (3~64) winsize 62
820 10:05:34.462163
821 10:05:34.465630 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 10:05:34.465744
823 10:05:34.468673 [CATrainingPosCal] consider 2 rank data
824 10:05:34.472116 u2DelayCellTimex100 = 270/100 ps
825 10:05:34.475912 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 10:05:34.478877 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 10:05:34.485586 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 10:05:34.488856 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 10:05:34.492236 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
830 10:05:34.495575 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 10:05:34.495682
832 10:05:34.498670 CA PerBit enable=1, Macro0, CA PI delay=33
833 10:05:34.498753
834 10:05:34.502279 [CBTSetCACLKResult] CA Dly = 33
835 10:05:34.502362 CS Dly: 6 (0~37)
836 10:05:34.502427
837 10:05:34.505899 ----->DramcWriteLeveling(PI) begin...
838 10:05:34.509020 ==
839 10:05:34.512865 Dram Type= 6, Freq= 0, CH_0, rank 0
840 10:05:34.515946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 10:05:34.516054 ==
842 10:05:34.519595 Write leveling (Byte 0): 29 => 29
843 10:05:34.519678 Write leveling (Byte 1): 28 => 28
844 10:05:34.523063 DramcWriteLeveling(PI) end<-----
845 10:05:34.523145
846 10:05:34.523209 ==
847 10:05:34.526732 Dram Type= 6, Freq= 0, CH_0, rank 0
848 10:05:34.530424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 10:05:34.533498 ==
850 10:05:34.533587 [Gating] SW mode calibration
851 10:05:34.540674 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 10:05:34.547551 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 10:05:34.550670 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 10:05:34.554399 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 10:05:34.561088 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 10:05:34.564042 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
857 10:05:34.567689 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 10:05:34.574143 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 10:05:34.577208 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 10:05:34.580407 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 10:05:34.587522 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 10:05:34.590814 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 10:05:34.594338 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 10:05:34.600673 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 10:05:34.604018 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 10:05:34.607551 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 10:05:34.614449 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 10:05:34.617272 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 10:05:34.621036 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 10:05:34.627301 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 10:05:34.631015 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 10:05:34.634180 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 10:05:34.640808 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 10:05:34.643968 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 10:05:34.647561 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 10:05:34.654244 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 10:05:34.657134 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 10:05:34.660513 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 10:05:34.663762 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 10:05:34.670419 0 9 12 | B1->B0 | 2727 3030 | 0 0 | (0 0) (1 1)
881 10:05:34.674621 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 10:05:34.677514 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 10:05:34.683863 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 10:05:34.687618 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 10:05:34.690930 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 10:05:34.697040 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
887 10:05:34.700569 0 10 8 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
888 10:05:34.704418 0 10 12 | B1->B0 | 2d2d 2424 | 1 0 | (1 0) (0 0)
889 10:05:34.710983 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 10:05:34.714285 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 10:05:34.717773 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 10:05:34.724448 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 10:05:34.727277 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 10:05:34.730847 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 10:05:34.737683 0 11 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
896 10:05:34.740834 0 11 12 | B1->B0 | 3535 3d3d | 0 0 | (0 0) (0 0)
897 10:05:34.744092 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 10:05:34.747299 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 10:05:34.754540 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 10:05:34.757464 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 10:05:34.760864 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 10:05:34.767401 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 10:05:34.771077 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
904 10:05:34.774234 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 10:05:34.781022 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 10:05:34.784010 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 10:05:34.787484 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 10:05:34.793858 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 10:05:34.797249 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 10:05:34.800735 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 10:05:34.807452 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 10:05:34.810857 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 10:05:34.814211 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 10:05:34.820703 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 10:05:34.824473 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 10:05:34.827740 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 10:05:34.834533 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 10:05:34.837502 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 10:05:34.841178 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 10:05:34.844193 Total UI for P1: 0, mck2ui 16
921 10:05:34.847784 best dqsien dly found for B0: ( 0, 14, 4)
922 10:05:34.850694 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 10:05:34.854119 Total UI for P1: 0, mck2ui 16
924 10:05:34.857992 best dqsien dly found for B1: ( 0, 14, 8)
925 10:05:34.860856 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 10:05:34.864150 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 10:05:34.864237
928 10:05:34.871523 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 10:05:34.874382 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 10:05:34.874466 [Gating] SW calibration Done
931 10:05:34.877963 ==
932 10:05:34.880848 Dram Type= 6, Freq= 0, CH_0, rank 0
933 10:05:34.884622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 10:05:34.884706 ==
935 10:05:34.884771 RX Vref Scan: 0
936 10:05:34.884830
937 10:05:34.887718 RX Vref 0 -> 0, step: 1
938 10:05:34.887801
939 10:05:34.891309 RX Delay -130 -> 252, step: 16
940 10:05:34.894432 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 10:05:34.897833 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 10:05:34.904086 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 10:05:34.907913 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 10:05:34.911067 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 10:05:34.914009 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 10:05:34.917761 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
947 10:05:34.921452 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
948 10:05:34.927428 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 10:05:34.930713 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 10:05:34.934224 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 10:05:34.937429 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 10:05:34.941076 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 10:05:34.947638 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 10:05:34.950685 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 10:05:34.954241 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 10:05:34.954323 ==
957 10:05:34.957848 Dram Type= 6, Freq= 0, CH_0, rank 0
958 10:05:34.960963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 10:05:34.964032 ==
960 10:05:34.964114 DQS Delay:
961 10:05:34.964189 DQS0 = 0, DQS1 = 0
962 10:05:34.967479 DQM Delay:
963 10:05:34.967587 DQM0 = 84, DQM1 = 79
964 10:05:34.971110 DQ Delay:
965 10:05:34.971218 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 10:05:34.974115 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
967 10:05:34.977801 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
968 10:05:34.980986 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 10:05:34.981068
970 10:05:34.983875
971 10:05:34.983956 ==
972 10:05:34.987339 Dram Type= 6, Freq= 0, CH_0, rank 0
973 10:05:34.991040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 10:05:34.991148 ==
975 10:05:34.991243
976 10:05:34.991337
977 10:05:34.994007 TX Vref Scan disable
978 10:05:34.994104 == TX Byte 0 ==
979 10:05:35.000792 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
980 10:05:35.004415 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
981 10:05:35.004489 == TX Byte 1 ==
982 10:05:35.007287 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
983 10:05:35.013734 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
984 10:05:35.013842 ==
985 10:05:35.017072 Dram Type= 6, Freq= 0, CH_0, rank 0
986 10:05:35.020321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 10:05:35.020400 ==
988 10:05:35.034329 TX Vref=22, minBit 0, minWin=27, winSum=437
989 10:05:35.037550 TX Vref=24, minBit 0, minWin=27, winSum=443
990 10:05:35.040905 TX Vref=26, minBit 0, minWin=27, winSum=447
991 10:05:35.044482 TX Vref=28, minBit 1, minWin=28, winSum=453
992 10:05:35.047888 TX Vref=30, minBit 2, minWin=28, winSum=452
993 10:05:35.050815 TX Vref=32, minBit 3, minWin=27, winSum=452
994 10:05:35.057520 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 28
995 10:05:35.057625
996 10:05:35.060746 Final TX Range 1 Vref 28
997 10:05:35.060818
998 10:05:35.060878 ==
999 10:05:35.064425 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 10:05:35.067567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 10:05:35.067664 ==
1002 10:05:35.067759
1003 10:05:35.070563
1004 10:05:35.070665 TX Vref Scan disable
1005 10:05:35.073932 == TX Byte 0 ==
1006 10:05:35.077719 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1007 10:05:35.084303 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1008 10:05:35.084386 == TX Byte 1 ==
1009 10:05:35.087509 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1010 10:05:35.090996 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1011 10:05:35.094095
1012 10:05:35.094180 [DATLAT]
1013 10:05:35.094249 Freq=800, CH0 RK0
1014 10:05:35.094309
1015 10:05:35.097633 DATLAT Default: 0xa
1016 10:05:35.097714 0, 0xFFFF, sum = 0
1017 10:05:35.100689 1, 0xFFFF, sum = 0
1018 10:05:35.100774 2, 0xFFFF, sum = 0
1019 10:05:35.103890 3, 0xFFFF, sum = 0
1020 10:05:35.103973 4, 0xFFFF, sum = 0
1021 10:05:35.107518 5, 0xFFFF, sum = 0
1022 10:05:35.110920 6, 0xFFFF, sum = 0
1023 10:05:35.111002 7, 0xFFFF, sum = 0
1024 10:05:35.113939 8, 0xFFFF, sum = 0
1025 10:05:35.114029 9, 0x0, sum = 1
1026 10:05:35.114096 10, 0x0, sum = 2
1027 10:05:35.117283 11, 0x0, sum = 3
1028 10:05:35.117365 12, 0x0, sum = 4
1029 10:05:35.120620 best_step = 10
1030 10:05:35.120700
1031 10:05:35.120762 ==
1032 10:05:35.124014 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 10:05:35.127342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 10:05:35.127461 ==
1035 10:05:35.130511 RX Vref Scan: 1
1036 10:05:35.130591
1037 10:05:35.130656 Set Vref Range= 32 -> 127
1038 10:05:35.133928
1039 10:05:35.134009 RX Vref 32 -> 127, step: 1
1040 10:05:35.134073
1041 10:05:35.137402 RX Delay -95 -> 252, step: 8
1042 10:05:35.137483
1043 10:05:35.140812 Set Vref, RX VrefLevel [Byte0]: 32
1044 10:05:35.144182 [Byte1]: 32
1045 10:05:35.144263
1046 10:05:35.147186 Set Vref, RX VrefLevel [Byte0]: 33
1047 10:05:35.150668 [Byte1]: 33
1048 10:05:35.154740
1049 10:05:35.154821 Set Vref, RX VrefLevel [Byte0]: 34
1050 10:05:35.157856 [Byte1]: 34
1051 10:05:35.161986
1052 10:05:35.162093 Set Vref, RX VrefLevel [Byte0]: 35
1053 10:05:35.165883 [Byte1]: 35
1054 10:05:35.169948
1055 10:05:35.170030 Set Vref, RX VrefLevel [Byte0]: 36
1056 10:05:35.173006 [Byte1]: 36
1057 10:05:35.177108
1058 10:05:35.177184 Set Vref, RX VrefLevel [Byte0]: 37
1059 10:05:35.180849 [Byte1]: 37
1060 10:05:35.185736
1061 10:05:35.185811 Set Vref, RX VrefLevel [Byte0]: 38
1062 10:05:35.188807 [Byte1]: 38
1063 10:05:35.193111
1064 10:05:35.193188 Set Vref, RX VrefLevel [Byte0]: 39
1065 10:05:35.196739 [Byte1]: 39
1066 10:05:35.200569
1067 10:05:35.200675 Set Vref, RX VrefLevel [Byte0]: 40
1068 10:05:35.203667 [Byte1]: 40
1069 10:05:35.208196
1070 10:05:35.208277 Set Vref, RX VrefLevel [Byte0]: 41
1071 10:05:35.211165 [Byte1]: 41
1072 10:05:35.215580
1073 10:05:35.215661 Set Vref, RX VrefLevel [Byte0]: 42
1074 10:05:35.218551 [Byte1]: 42
1075 10:05:35.222847
1076 10:05:35.222929 Set Vref, RX VrefLevel [Byte0]: 43
1077 10:05:35.226253 [Byte1]: 43
1078 10:05:35.230716
1079 10:05:35.230798 Set Vref, RX VrefLevel [Byte0]: 44
1080 10:05:35.233942 [Byte1]: 44
1081 10:05:35.237928
1082 10:05:35.238010 Set Vref, RX VrefLevel [Byte0]: 45
1083 10:05:35.242205 [Byte1]: 45
1084 10:05:35.245750
1085 10:05:35.245828 Set Vref, RX VrefLevel [Byte0]: 46
1086 10:05:35.249221 [Byte1]: 46
1087 10:05:35.253143
1088 10:05:35.253217 Set Vref, RX VrefLevel [Byte0]: 47
1089 10:05:35.256665 [Byte1]: 47
1090 10:05:35.261182
1091 10:05:35.261257 Set Vref, RX VrefLevel [Byte0]: 48
1092 10:05:35.263984 [Byte1]: 48
1093 10:05:35.268670
1094 10:05:35.268776 Set Vref, RX VrefLevel [Byte0]: 49
1095 10:05:35.271681 [Byte1]: 49
1096 10:05:35.276396
1097 10:05:35.276474 Set Vref, RX VrefLevel [Byte0]: 50
1098 10:05:35.279782 [Byte1]: 50
1099 10:05:35.284241
1100 10:05:35.284315 Set Vref, RX VrefLevel [Byte0]: 51
1101 10:05:35.286947 [Byte1]: 51
1102 10:05:35.291325
1103 10:05:35.291472 Set Vref, RX VrefLevel [Byte0]: 52
1104 10:05:35.294338 [Byte1]: 52
1105 10:05:35.298621
1106 10:05:35.298742 Set Vref, RX VrefLevel [Byte0]: 53
1107 10:05:35.302162 [Byte1]: 53
1108 10:05:35.306894
1109 10:05:35.307003 Set Vref, RX VrefLevel [Byte0]: 54
1110 10:05:35.310072 [Byte1]: 54
1111 10:05:35.314174
1112 10:05:35.317379 Set Vref, RX VrefLevel [Byte0]: 55
1113 10:05:35.320427 [Byte1]: 55
1114 10:05:35.320508
1115 10:05:35.323903 Set Vref, RX VrefLevel [Byte0]: 56
1116 10:05:35.327160 [Byte1]: 56
1117 10:05:35.327242
1118 10:05:35.330174 Set Vref, RX VrefLevel [Byte0]: 57
1119 10:05:35.333907 [Byte1]: 57
1120 10:05:35.333988
1121 10:05:35.337157 Set Vref, RX VrefLevel [Byte0]: 58
1122 10:05:35.340841 [Byte1]: 58
1123 10:05:35.344606
1124 10:05:35.344717 Set Vref, RX VrefLevel [Byte0]: 59
1125 10:05:35.347778 [Byte1]: 59
1126 10:05:35.351713
1127 10:05:35.351793 Set Vref, RX VrefLevel [Byte0]: 60
1128 10:05:35.355525 [Byte1]: 60
1129 10:05:35.359566
1130 10:05:35.359646 Set Vref, RX VrefLevel [Byte0]: 61
1131 10:05:35.362641 [Byte1]: 61
1132 10:05:35.367177
1133 10:05:35.367286 Set Vref, RX VrefLevel [Byte0]: 62
1134 10:05:35.370402 [Byte1]: 62
1135 10:05:35.374799
1136 10:05:35.374881 Set Vref, RX VrefLevel [Byte0]: 63
1137 10:05:35.378122 [Byte1]: 63
1138 10:05:35.382344
1139 10:05:35.382424 Set Vref, RX VrefLevel [Byte0]: 64
1140 10:05:35.385377 [Byte1]: 64
1141 10:05:35.390233
1142 10:05:35.390313 Set Vref, RX VrefLevel [Byte0]: 65
1143 10:05:35.393329 [Byte1]: 65
1144 10:05:35.397605
1145 10:05:35.397735 Set Vref, RX VrefLevel [Byte0]: 66
1146 10:05:35.400650 [Byte1]: 66
1147 10:05:35.404875
1148 10:05:35.404956 Set Vref, RX VrefLevel [Byte0]: 67
1149 10:05:35.408228 [Byte1]: 67
1150 10:05:35.412629
1151 10:05:35.412709 Set Vref, RX VrefLevel [Byte0]: 68
1152 10:05:35.416209 [Byte1]: 68
1153 10:05:35.420060
1154 10:05:35.420140 Set Vref, RX VrefLevel [Byte0]: 69
1155 10:05:35.423703 [Byte1]: 69
1156 10:05:35.427797
1157 10:05:35.427900 Set Vref, RX VrefLevel [Byte0]: 70
1158 10:05:35.431653 [Byte1]: 70
1159 10:05:35.435516
1160 10:05:35.435597 Set Vref, RX VrefLevel [Byte0]: 71
1161 10:05:35.438988 [Byte1]: 71
1162 10:05:35.443513
1163 10:05:35.443594 Set Vref, RX VrefLevel [Byte0]: 72
1164 10:05:35.449539 [Byte1]: 72
1165 10:05:35.449620
1166 10:05:35.452685 Set Vref, RX VrefLevel [Byte0]: 73
1167 10:05:35.456214 [Byte1]: 73
1168 10:05:35.456294
1169 10:05:35.459227 Set Vref, RX VrefLevel [Byte0]: 74
1170 10:05:35.462685 [Byte1]: 74
1171 10:05:35.462766
1172 10:05:35.466348 Set Vref, RX VrefLevel [Byte0]: 75
1173 10:05:35.469759 [Byte1]: 75
1174 10:05:35.473417
1175 10:05:35.473513 Set Vref, RX VrefLevel [Byte0]: 76
1176 10:05:35.476930 [Byte1]: 76
1177 10:05:35.481128
1178 10:05:35.481210 Set Vref, RX VrefLevel [Byte0]: 77
1179 10:05:35.484778 [Byte1]: 77
1180 10:05:35.488467
1181 10:05:35.488547 Final RX Vref Byte 0 = 63 to rank0
1182 10:05:35.491866 Final RX Vref Byte 1 = 58 to rank0
1183 10:05:35.495461 Final RX Vref Byte 0 = 63 to rank1
1184 10:05:35.498428 Final RX Vref Byte 1 = 58 to rank1==
1185 10:05:35.501963 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 10:05:35.505774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 10:05:35.508670 ==
1188 10:05:35.508745 DQS Delay:
1189 10:05:35.508808 DQS0 = 0, DQS1 = 0
1190 10:05:35.512345 DQM Delay:
1191 10:05:35.512420 DQM0 = 88, DQM1 = 79
1192 10:05:35.515398 DQ Delay:
1193 10:05:35.515475 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1194 10:05:35.518944 DQ4 =92, DQ5 =76, DQ6 =96, DQ7 =96
1195 10:05:35.522661 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1196 10:05:35.525387 DQ12 =88, DQ13 =80, DQ14 =88, DQ15 =88
1197 10:05:35.525464
1198 10:05:35.528914
1199 10:05:35.535808 [DQSOSCAuto] RK0, (LSB)MR18= 0x260e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1200 10:05:35.538703 CH0 RK0: MR19=606, MR18=260E
1201 10:05:35.545456 CH0_RK0: MR19=0x606, MR18=0x260E, DQSOSC=400, MR23=63, INC=92, DEC=61
1202 10:05:35.545536
1203 10:05:35.548711 ----->DramcWriteLeveling(PI) begin...
1204 10:05:35.548786 ==
1205 10:05:35.552103 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 10:05:35.555498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 10:05:35.555578 ==
1208 10:05:35.558870 Write leveling (Byte 0): 31 => 31
1209 10:05:35.562349 Write leveling (Byte 1): 31 => 31
1210 10:05:35.565468 DramcWriteLeveling(PI) end<-----
1211 10:05:35.565546
1212 10:05:35.565609 ==
1213 10:05:35.568840 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 10:05:35.572026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 10:05:35.572108 ==
1216 10:05:35.575700 [Gating] SW mode calibration
1217 10:05:35.582204 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 10:05:35.588762 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 10:05:35.592319 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 10:05:35.636559 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1221 10:05:35.637223 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1222 10:05:35.637472 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 10:05:35.637540 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 10:05:35.637780 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 10:05:35.637853 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 10:05:35.637923 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 10:05:35.638253 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 10:05:35.638317 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 10:05:35.639007 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 10:05:35.663825 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 10:05:35.663926 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 10:05:35.664188 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 10:05:35.664310 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 10:05:35.664390 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 10:05:35.664504 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 10:05:35.667789 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1237 10:05:35.670663 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1238 10:05:35.673999 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 10:05:35.681320 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 10:05:35.684142 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 10:05:35.687381 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 10:05:35.694128 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 10:05:35.697041 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 10:05:35.700382 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1245 10:05:35.707073 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1246 10:05:35.710666 0 9 12 | B1->B0 | 3231 3434 | 1 1 | (0 0) (1 1)
1247 10:05:35.714135 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 10:05:35.720696 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 10:05:35.723711 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 10:05:35.727407 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 10:05:35.734251 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 10:05:35.737098 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1253 10:05:35.740358 0 10 8 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
1254 10:05:35.747396 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 10:05:35.750799 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 10:05:35.753878 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 10:05:35.760636 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 10:05:35.764141 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 10:05:35.767695 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 10:05:35.771023 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1261 10:05:35.778492 0 11 8 | B1->B0 | 2d2d 4444 | 0 0 | (0 0) (0 0)
1262 10:05:35.781886 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1263 10:05:35.785455 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 10:05:35.788809 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 10:05:35.796093 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 10:05:35.799456 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 10:05:35.802781 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 10:05:35.805848 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1269 10:05:35.812569 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1270 10:05:35.816186 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 10:05:35.819081 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 10:05:35.825704 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 10:05:35.829334 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 10:05:35.833072 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 10:05:35.839132 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 10:05:35.842707 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 10:05:35.845742 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 10:05:35.852536 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 10:05:35.856272 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 10:05:35.859241 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 10:05:35.866078 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 10:05:35.869287 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 10:05:35.872709 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 10:05:35.879246 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1285 10:05:35.882708 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 10:05:35.885731 Total UI for P1: 0, mck2ui 16
1287 10:05:35.889157 best dqsien dly found for B0: ( 0, 14, 4)
1288 10:05:35.892694 Total UI for P1: 0, mck2ui 16
1289 10:05:35.896160 best dqsien dly found for B1: ( 0, 14, 6)
1290 10:05:35.899333 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1291 10:05:35.902671 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1292 10:05:35.902746
1293 10:05:35.906334 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1294 10:05:35.909295 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1295 10:05:35.912929 [Gating] SW calibration Done
1296 10:05:35.913002 ==
1297 10:05:35.916094 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 10:05:35.919612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 10:05:35.919712 ==
1300 10:05:35.922730 RX Vref Scan: 0
1301 10:05:35.922802
1302 10:05:35.922863 RX Vref 0 -> 0, step: 1
1303 10:05:35.922929
1304 10:05:35.926331 RX Delay -130 -> 252, step: 16
1305 10:05:35.932484 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1306 10:05:35.936033 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1307 10:05:35.939008 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1308 10:05:35.942783 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1309 10:05:35.945864 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1310 10:05:35.949698 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1311 10:05:35.956549 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1312 10:05:35.959252 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1313 10:05:35.963247 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1314 10:05:35.966110 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1315 10:05:35.969449 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1316 10:05:35.976276 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1317 10:05:35.979096 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1318 10:05:35.982747 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1319 10:05:35.986082 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1320 10:05:35.992766 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1321 10:05:35.992848 ==
1322 10:05:35.996136 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 10:05:35.999311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 10:05:35.999433 ==
1325 10:05:35.999498 DQS Delay:
1326 10:05:36.002638 DQS0 = 0, DQS1 = 0
1327 10:05:36.002747 DQM Delay:
1328 10:05:36.006220 DQM0 = 86, DQM1 = 75
1329 10:05:36.006301 DQ Delay:
1330 10:05:36.009491 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1331 10:05:36.012408 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1332 10:05:36.015760 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1333 10:05:36.019508 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1334 10:05:36.019589
1335 10:05:36.019653
1336 10:05:36.019713 ==
1337 10:05:36.022405 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 10:05:36.025888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 10:05:36.025973 ==
1340 10:05:36.026036
1341 10:05:36.026095
1342 10:05:36.029701 TX Vref Scan disable
1343 10:05:36.032645 == TX Byte 0 ==
1344 10:05:36.036245 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1345 10:05:36.039251 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1346 10:05:36.042899 == TX Byte 1 ==
1347 10:05:36.045868 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1348 10:05:36.049518 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1349 10:05:36.049594 ==
1350 10:05:36.052590 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 10:05:36.055741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 10:05:36.059280 ==
1353 10:05:36.070683 TX Vref=22, minBit 3, minWin=27, winSum=445
1354 10:05:36.073841 TX Vref=24, minBit 8, minWin=27, winSum=447
1355 10:05:36.077210 TX Vref=26, minBit 9, minWin=27, winSum=450
1356 10:05:36.080605 TX Vref=28, minBit 2, minWin=28, winSum=457
1357 10:05:36.083970 TX Vref=30, minBit 2, minWin=28, winSum=456
1358 10:05:36.090668 TX Vref=32, minBit 13, minWin=27, winSum=454
1359 10:05:36.094142 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 28
1360 10:05:36.094247
1361 10:05:36.097246 Final TX Range 1 Vref 28
1362 10:05:36.097346
1363 10:05:36.097439 ==
1364 10:05:36.100503 Dram Type= 6, Freq= 0, CH_0, rank 1
1365 10:05:36.103843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 10:05:36.103946 ==
1367 10:05:36.107390
1368 10:05:36.107492
1369 10:05:36.107582 TX Vref Scan disable
1370 10:05:36.110588 == TX Byte 0 ==
1371 10:05:36.113889 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1372 10:05:36.120757 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1373 10:05:36.120833 == TX Byte 1 ==
1374 10:05:36.123967 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1375 10:05:36.130285 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1376 10:05:36.130361
1377 10:05:36.130422 [DATLAT]
1378 10:05:36.130480 Freq=800, CH0 RK1
1379 10:05:36.130542
1380 10:05:36.133980 DATLAT Default: 0xa
1381 10:05:36.134051 0, 0xFFFF, sum = 0
1382 10:05:36.136974 1, 0xFFFF, sum = 0
1383 10:05:36.137048 2, 0xFFFF, sum = 0
1384 10:05:36.140567 3, 0xFFFF, sum = 0
1385 10:05:36.143745 4, 0xFFFF, sum = 0
1386 10:05:36.143850 5, 0xFFFF, sum = 0
1387 10:05:36.146885 6, 0xFFFF, sum = 0
1388 10:05:36.146957 7, 0xFFFF, sum = 0
1389 10:05:36.150478 8, 0xFFFF, sum = 0
1390 10:05:36.150578 9, 0x0, sum = 1
1391 10:05:36.150667 10, 0x0, sum = 2
1392 10:05:36.154421 11, 0x0, sum = 3
1393 10:05:36.154498 12, 0x0, sum = 4
1394 10:05:36.157155 best_step = 10
1395 10:05:36.157230
1396 10:05:36.157289 ==
1397 10:05:36.160766 Dram Type= 6, Freq= 0, CH_0, rank 1
1398 10:05:36.163760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 10:05:36.163834 ==
1400 10:05:36.167229 RX Vref Scan: 0
1401 10:05:36.167333
1402 10:05:36.167459 RX Vref 0 -> 0, step: 1
1403 10:05:36.167550
1404 10:05:36.170309 RX Delay -95 -> 252, step: 8
1405 10:05:36.177677 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1406 10:05:36.180718 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1407 10:05:36.184104 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1408 10:05:36.187113 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1409 10:05:36.190838 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1410 10:05:36.197266 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1411 10:05:36.200623 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1412 10:05:36.203740 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1413 10:05:36.207170 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1414 10:05:36.211008 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1415 10:05:36.217443 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1416 10:05:36.220670 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1417 10:05:36.223579 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1418 10:05:36.227359 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1419 10:05:36.230790 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1420 10:05:36.237073 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1421 10:05:36.237167 ==
1422 10:05:36.240775 Dram Type= 6, Freq= 0, CH_0, rank 1
1423 10:05:36.243887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 10:05:36.243985 ==
1425 10:05:36.244114 DQS Delay:
1426 10:05:36.247511 DQS0 = 0, DQS1 = 0
1427 10:05:36.247583 DQM Delay:
1428 10:05:36.250470 DQM0 = 87, DQM1 = 77
1429 10:05:36.250552 DQ Delay:
1430 10:05:36.253615 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1431 10:05:36.257153 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1432 10:05:36.260716 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1433 10:05:36.263799 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1434 10:05:36.263868
1435 10:05:36.263929
1436 10:05:36.273519 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1437 10:05:36.273630 CH0 RK1: MR19=606, MR18=2D17
1438 10:05:36.280242 CH0_RK1: MR19=0x606, MR18=0x2D17, DQSOSC=398, MR23=63, INC=93, DEC=62
1439 10:05:36.283954 [RxdqsGatingPostProcess] freq 800
1440 10:05:36.290548 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1441 10:05:36.293701 Pre-setting of DQS Precalculation
1442 10:05:36.296882 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1443 10:05:36.296977 ==
1444 10:05:36.300475 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 10:05:36.303685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 10:05:36.303785 ==
1447 10:05:36.310397 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1448 10:05:36.317100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1449 10:05:36.325338 [CA 0] Center 36 (6~67) winsize 62
1450 10:05:36.328918 [CA 1] Center 36 (5~67) winsize 63
1451 10:05:36.332326 [CA 2] Center 34 (4~64) winsize 61
1452 10:05:36.335603 [CA 3] Center 33 (3~64) winsize 62
1453 10:05:36.338915 [CA 4] Center 34 (4~65) winsize 62
1454 10:05:36.342050 [CA 5] Center 33 (3~64) winsize 62
1455 10:05:36.342151
1456 10:05:36.345643 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1457 10:05:36.345743
1458 10:05:36.348781 [CATrainingPosCal] consider 1 rank data
1459 10:05:36.352302 u2DelayCellTimex100 = 270/100 ps
1460 10:05:36.355352 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1461 10:05:36.358574 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1462 10:05:36.365243 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1463 10:05:36.368864 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1464 10:05:36.371840 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1465 10:05:36.375307 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1466 10:05:36.375429
1467 10:05:36.378415 CA PerBit enable=1, Macro0, CA PI delay=33
1468 10:05:36.378513
1469 10:05:36.382263 [CBTSetCACLKResult] CA Dly = 33
1470 10:05:36.382359 CS Dly: 5 (0~36)
1471 10:05:36.385266 ==
1472 10:05:36.385338 Dram Type= 6, Freq= 0, CH_1, rank 1
1473 10:05:36.391859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 10:05:36.391935 ==
1475 10:05:36.395488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1476 10:05:36.401925 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1477 10:05:36.411669 [CA 0] Center 36 (5~67) winsize 63
1478 10:05:36.414983 [CA 1] Center 36 (5~67) winsize 63
1479 10:05:36.418490 [CA 2] Center 33 (3~64) winsize 62
1480 10:05:36.421862 [CA 3] Center 33 (3~64) winsize 62
1481 10:05:36.425168 [CA 4] Center 34 (3~65) winsize 63
1482 10:05:36.428254 [CA 5] Center 33 (3~64) winsize 62
1483 10:05:36.428351
1484 10:05:36.431574 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1485 10:05:36.431676
1486 10:05:36.435344 [CATrainingPosCal] consider 2 rank data
1487 10:05:36.439071 u2DelayCellTimex100 = 270/100 ps
1488 10:05:36.442946 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1489 10:05:36.446145 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1490 10:05:36.450120 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1491 10:05:36.453735 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1492 10:05:36.457442 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1493 10:05:36.461295 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1494 10:05:36.461393
1495 10:05:36.465017 CA PerBit enable=1, Macro0, CA PI delay=33
1496 10:05:36.465159
1497 10:05:36.468108 [CBTSetCACLKResult] CA Dly = 33
1498 10:05:36.468186 CS Dly: 5 (0~36)
1499 10:05:36.468257
1500 10:05:36.471727 ----->DramcWriteLeveling(PI) begin...
1501 10:05:36.474529 ==
1502 10:05:36.478259 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 10:05:36.481246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1504 10:05:36.481321 ==
1505 10:05:36.484662 Write leveling (Byte 0): 27 => 27
1506 10:05:36.488186 Write leveling (Byte 1): 30 => 30
1507 10:05:36.491325 DramcWriteLeveling(PI) end<-----
1508 10:05:36.491431
1509 10:05:36.491495 ==
1510 10:05:36.494746 Dram Type= 6, Freq= 0, CH_1, rank 0
1511 10:05:36.498487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1512 10:05:36.498569 ==
1513 10:05:36.501423 [Gating] SW mode calibration
1514 10:05:36.507872 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1515 10:05:36.511640 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1516 10:05:36.517980 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1517 10:05:36.521599 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1518 10:05:36.524498 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1519 10:05:36.531465 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 10:05:36.534847 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 10:05:36.537858 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 10:05:36.544853 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 10:05:36.547862 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 10:05:36.551189 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 10:05:36.558054 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 10:05:36.561247 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 10:05:36.564829 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 10:05:36.571297 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 10:05:36.574853 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 10:05:36.577984 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 10:05:36.584692 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 10:05:36.588204 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 10:05:36.591234 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1534 10:05:36.598184 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1535 10:05:36.601716 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 10:05:36.604511 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 10:05:36.608394 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 10:05:36.614786 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 10:05:36.618202 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 10:05:36.621732 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 10:05:36.627941 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 10:05:36.631428 0 9 8 | B1->B0 | 2424 2727 | 1 1 | (1 1) (1 1)
1543 10:05:36.634584 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1544 10:05:36.641149 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 10:05:36.644492 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 10:05:36.647871 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 10:05:36.654875 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 10:05:36.658025 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 10:05:36.661450 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 10:05:36.667933 0 10 8 | B1->B0 | 2525 2f2f | 1 0 | (1 0) (0 1)
1551 10:05:36.671062 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 10:05:36.674215 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 10:05:36.681255 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 10:05:36.684381 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 10:05:36.687834 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 10:05:36.694585 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 10:05:36.698050 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1558 10:05:36.701699 0 11 8 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 0)
1559 10:05:36.707610 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 10:05:36.711182 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 10:05:36.714375 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 10:05:36.717834 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 10:05:36.724810 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 10:05:36.727696 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 10:05:36.731180 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 10:05:36.737489 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 10:05:36.741421 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 10:05:36.744314 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 10:05:36.751085 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 10:05:36.754449 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 10:05:36.757864 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 10:05:36.764428 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 10:05:36.767897 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 10:05:36.770891 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 10:05:36.777713 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 10:05:36.781081 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 10:05:36.784716 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 10:05:36.790963 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 10:05:36.794843 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 10:05:36.797572 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 10:05:36.804722 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 10:05:36.808044 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1583 10:05:36.811108 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 10:05:36.814877 Total UI for P1: 0, mck2ui 16
1585 10:05:36.817647 best dqsien dly found for B0: ( 0, 14, 8)
1586 10:05:36.821668 Total UI for P1: 0, mck2ui 16
1587 10:05:36.824837 best dqsien dly found for B1: ( 0, 14, 8)
1588 10:05:36.827474 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1589 10:05:36.831030 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1590 10:05:36.831130
1591 10:05:36.834471 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1592 10:05:36.838121 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1593 10:05:36.841001 [Gating] SW calibration Done
1594 10:05:36.841098 ==
1595 10:05:36.844282 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 10:05:36.851311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 10:05:36.851419 ==
1598 10:05:36.851482 RX Vref Scan: 0
1599 10:05:36.851539
1600 10:05:36.854351 RX Vref 0 -> 0, step: 1
1601 10:05:36.854446
1602 10:05:36.858098 RX Delay -130 -> 252, step: 16
1603 10:05:36.860997 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1604 10:05:36.864191 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1605 10:05:36.867583 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1606 10:05:36.870847 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1607 10:05:36.877476 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1608 10:05:36.881105 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1609 10:05:36.884159 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1610 10:05:36.887803 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1611 10:05:36.890961 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1612 10:05:36.898003 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1613 10:05:36.900918 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1614 10:05:36.904369 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1615 10:05:36.907872 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1616 10:05:36.910951 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1617 10:05:36.917728 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1618 10:05:36.921274 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1619 10:05:36.921377 ==
1620 10:05:36.924383 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 10:05:36.927829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 10:05:36.927899 ==
1623 10:05:36.930927 DQS Delay:
1624 10:05:36.931025 DQS0 = 0, DQS1 = 0
1625 10:05:36.931112 DQM Delay:
1626 10:05:36.934553 DQM0 = 82, DQM1 = 76
1627 10:05:36.934654 DQ Delay:
1628 10:05:36.937846 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1629 10:05:36.941297 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1630 10:05:36.944762 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1631 10:05:36.947745 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1632 10:05:36.947828
1633 10:05:36.947891
1634 10:05:36.947949 ==
1635 10:05:36.951058 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 10:05:36.957884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 10:05:36.957983 ==
1638 10:05:36.958079
1639 10:05:36.958167
1640 10:05:36.958252 TX Vref Scan disable
1641 10:05:36.961498 == TX Byte 0 ==
1642 10:05:36.964298 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1643 10:05:36.967584 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1644 10:05:36.970946 == TX Byte 1 ==
1645 10:05:36.974343 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1646 10:05:36.977671 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1647 10:05:36.980942 ==
1648 10:05:36.984595 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 10:05:36.987592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 10:05:36.987666 ==
1651 10:05:37.000903 TX Vref=22, minBit 0, minWin=27, winSum=436
1652 10:05:37.004156 TX Vref=24, minBit 0, minWin=27, winSum=439
1653 10:05:37.007066 TX Vref=26, minBit 7, minWin=27, winSum=446
1654 10:05:37.010598 TX Vref=28, minBit 3, minWin=27, winSum=448
1655 10:05:37.013738 TX Vref=30, minBit 0, minWin=28, winSum=455
1656 10:05:37.017954 TX Vref=32, minBit 0, minWin=28, winSum=456
1657 10:05:37.024595 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 32
1658 10:05:37.024694
1659 10:05:37.027547 Final TX Range 1 Vref 32
1660 10:05:37.027619
1661 10:05:37.027679 ==
1662 10:05:37.030494 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 10:05:37.033966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1664 10:05:37.034063 ==
1665 10:05:37.034150
1666 10:05:37.034238
1667 10:05:37.037166 TX Vref Scan disable
1668 10:05:37.040672 == TX Byte 0 ==
1669 10:05:37.044173 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1670 10:05:37.047625 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1671 10:05:37.050622 == TX Byte 1 ==
1672 10:05:37.054109 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1673 10:05:37.056933 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1674 10:05:37.057006
1675 10:05:37.060242 [DATLAT]
1676 10:05:37.060340 Freq=800, CH1 RK0
1677 10:05:37.060429
1678 10:05:37.063732 DATLAT Default: 0xa
1679 10:05:37.063828 0, 0xFFFF, sum = 0
1680 10:05:37.066798 1, 0xFFFF, sum = 0
1681 10:05:37.066896 2, 0xFFFF, sum = 0
1682 10:05:37.070336 3, 0xFFFF, sum = 0
1683 10:05:37.070436 4, 0xFFFF, sum = 0
1684 10:05:37.073718 5, 0xFFFF, sum = 0
1685 10:05:37.077160 6, 0xFFFF, sum = 0
1686 10:05:37.077263 7, 0xFFFF, sum = 0
1687 10:05:37.080494 8, 0xFFFF, sum = 0
1688 10:05:37.080596 9, 0x0, sum = 1
1689 10:05:37.080687 10, 0x0, sum = 2
1690 10:05:37.083680 11, 0x0, sum = 3
1691 10:05:37.083758 12, 0x0, sum = 4
1692 10:05:37.086867 best_step = 10
1693 10:05:37.086965
1694 10:05:37.087052 ==
1695 10:05:37.090747 Dram Type= 6, Freq= 0, CH_1, rank 0
1696 10:05:37.093698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1697 10:05:37.093798 ==
1698 10:05:37.096887 RX Vref Scan: 1
1699 10:05:37.096985
1700 10:05:37.097073 Set Vref Range= 32 -> 127
1701 10:05:37.100409
1702 10:05:37.100484 RX Vref 32 -> 127, step: 1
1703 10:05:37.100550
1704 10:05:37.103624 RX Delay -95 -> 252, step: 8
1705 10:05:37.103692
1706 10:05:37.107082 Set Vref, RX VrefLevel [Byte0]: 32
1707 10:05:37.109915 [Byte1]: 32
1708 10:05:37.110013
1709 10:05:37.113526 Set Vref, RX VrefLevel [Byte0]: 33
1710 10:05:37.116501 [Byte1]: 33
1711 10:05:37.120653
1712 10:05:37.120726 Set Vref, RX VrefLevel [Byte0]: 34
1713 10:05:37.124257 [Byte1]: 34
1714 10:05:37.128527
1715 10:05:37.128625 Set Vref, RX VrefLevel [Byte0]: 35
1716 10:05:37.131584 [Byte1]: 35
1717 10:05:37.135950
1718 10:05:37.136049 Set Vref, RX VrefLevel [Byte0]: 36
1719 10:05:37.139479 [Byte1]: 36
1720 10:05:37.143471
1721 10:05:37.143569 Set Vref, RX VrefLevel [Byte0]: 37
1722 10:05:37.146833 [Byte1]: 37
1723 10:05:37.150867
1724 10:05:37.150966 Set Vref, RX VrefLevel [Byte0]: 38
1725 10:05:37.154280 [Byte1]: 38
1726 10:05:37.158374
1727 10:05:37.158445 Set Vref, RX VrefLevel [Byte0]: 39
1728 10:05:37.161784 [Byte1]: 39
1729 10:05:37.166215
1730 10:05:37.166314 Set Vref, RX VrefLevel [Byte0]: 40
1731 10:05:37.169675 [Byte1]: 40
1732 10:05:37.174068
1733 10:05:37.174171 Set Vref, RX VrefLevel [Byte0]: 41
1734 10:05:37.177447 [Byte1]: 41
1735 10:05:37.181314
1736 10:05:37.181430 Set Vref, RX VrefLevel [Byte0]: 42
1737 10:05:37.184588 [Byte1]: 42
1738 10:05:37.188996
1739 10:05:37.189096 Set Vref, RX VrefLevel [Byte0]: 43
1740 10:05:37.192241 [Byte1]: 43
1741 10:05:37.196463
1742 10:05:37.196561 Set Vref, RX VrefLevel [Byte0]: 44
1743 10:05:37.199973 [Byte1]: 44
1744 10:05:37.204114
1745 10:05:37.204214 Set Vref, RX VrefLevel [Byte0]: 45
1746 10:05:37.207242 [Byte1]: 45
1747 10:05:37.211814
1748 10:05:37.211888 Set Vref, RX VrefLevel [Byte0]: 46
1749 10:05:37.215440 [Byte1]: 46
1750 10:05:37.219613
1751 10:05:37.219687 Set Vref, RX VrefLevel [Byte0]: 47
1752 10:05:37.222538 [Byte1]: 47
1753 10:05:37.226774
1754 10:05:37.226871 Set Vref, RX VrefLevel [Byte0]: 48
1755 10:05:37.230423 [Byte1]: 48
1756 10:05:37.234522
1757 10:05:37.234621 Set Vref, RX VrefLevel [Byte0]: 49
1758 10:05:37.237725 [Byte1]: 49
1759 10:05:37.242292
1760 10:05:37.242402 Set Vref, RX VrefLevel [Byte0]: 50
1761 10:05:37.245652 [Byte1]: 50
1762 10:05:37.250013
1763 10:05:37.250112 Set Vref, RX VrefLevel [Byte0]: 51
1764 10:05:37.253057 [Byte1]: 51
1765 10:05:37.257037
1766 10:05:37.257142 Set Vref, RX VrefLevel [Byte0]: 52
1767 10:05:37.260585 [Byte1]: 52
1768 10:05:37.264796
1769 10:05:37.264893 Set Vref, RX VrefLevel [Byte0]: 53
1770 10:05:37.268304 [Byte1]: 53
1771 10:05:37.272793
1772 10:05:37.272898 Set Vref, RX VrefLevel [Byte0]: 54
1773 10:05:37.275639 [Byte1]: 54
1774 10:05:37.280161
1775 10:05:37.280262 Set Vref, RX VrefLevel [Byte0]: 55
1776 10:05:37.283601 [Byte1]: 55
1777 10:05:37.288023
1778 10:05:37.288118 Set Vref, RX VrefLevel [Byte0]: 56
1779 10:05:37.290956 [Byte1]: 56
1780 10:05:37.295198
1781 10:05:37.295292 Set Vref, RX VrefLevel [Byte0]: 57
1782 10:05:37.298702 [Byte1]: 57
1783 10:05:37.302792
1784 10:05:37.302890 Set Vref, RX VrefLevel [Byte0]: 58
1785 10:05:37.306510 [Byte1]: 58
1786 10:05:37.311265
1787 10:05:37.311402 Set Vref, RX VrefLevel [Byte0]: 59
1788 10:05:37.313797 [Byte1]: 59
1789 10:05:37.318519
1790 10:05:37.318597 Set Vref, RX VrefLevel [Byte0]: 60
1791 10:05:37.321439 [Byte1]: 60
1792 10:05:37.326205
1793 10:05:37.326318 Set Vref, RX VrefLevel [Byte0]: 61
1794 10:05:37.329105 [Byte1]: 61
1795 10:05:37.333391
1796 10:05:37.333496 Set Vref, RX VrefLevel [Byte0]: 62
1797 10:05:37.336587 [Byte1]: 62
1798 10:05:37.341394
1799 10:05:37.341475 Set Vref, RX VrefLevel [Byte0]: 63
1800 10:05:37.344380 [Byte1]: 63
1801 10:05:37.348600
1802 10:05:37.348688 Set Vref, RX VrefLevel [Byte0]: 64
1803 10:05:37.352177 [Byte1]: 64
1804 10:05:37.356319
1805 10:05:37.356399 Set Vref, RX VrefLevel [Byte0]: 65
1806 10:05:37.362345 [Byte1]: 65
1807 10:05:37.362426
1808 10:05:37.365829 Set Vref, RX VrefLevel [Byte0]: 66
1809 10:05:37.369565 [Byte1]: 66
1810 10:05:37.369645
1811 10:05:37.372432 Set Vref, RX VrefLevel [Byte0]: 67
1812 10:05:37.375730 [Byte1]: 67
1813 10:05:37.375812
1814 10:05:37.379134 Set Vref, RX VrefLevel [Byte0]: 68
1815 10:05:37.382502 [Byte1]: 68
1816 10:05:37.386835
1817 10:05:37.386916 Set Vref, RX VrefLevel [Byte0]: 69
1818 10:05:37.389780 [Byte1]: 69
1819 10:05:37.394249
1820 10:05:37.394329 Set Vref, RX VrefLevel [Byte0]: 70
1821 10:05:37.397647 [Byte1]: 70
1822 10:05:37.401518
1823 10:05:37.401600 Set Vref, RX VrefLevel [Byte0]: 71
1824 10:05:37.405009 [Byte1]: 71
1825 10:05:37.409264
1826 10:05:37.409344 Set Vref, RX VrefLevel [Byte0]: 72
1827 10:05:37.413066 [Byte1]: 72
1828 10:05:37.417027
1829 10:05:37.417100 Set Vref, RX VrefLevel [Byte0]: 73
1830 10:05:37.420583 [Byte1]: 73
1831 10:05:37.424812
1832 10:05:37.424886 Set Vref, RX VrefLevel [Byte0]: 74
1833 10:05:37.427807 [Byte1]: 74
1834 10:05:37.431948
1835 10:05:37.432054 Set Vref, RX VrefLevel [Byte0]: 75
1836 10:05:37.435896 [Byte1]: 75
1837 10:05:37.439983
1838 10:05:37.440060 Set Vref, RX VrefLevel [Byte0]: 76
1839 10:05:37.443042 [Byte1]: 76
1840 10:05:37.447190
1841 10:05:37.447264 Set Vref, RX VrefLevel [Byte0]: 77
1842 10:05:37.450362 [Byte1]: 77
1843 10:05:37.454910
1844 10:05:37.455016 Set Vref, RX VrefLevel [Byte0]: 78
1845 10:05:37.457964 [Byte1]: 78
1846 10:05:37.462285
1847 10:05:37.462359 Final RX Vref Byte 0 = 60 to rank0
1848 10:05:37.465775 Final RX Vref Byte 1 = 59 to rank0
1849 10:05:37.469208 Final RX Vref Byte 0 = 60 to rank1
1850 10:05:37.472333 Final RX Vref Byte 1 = 59 to rank1==
1851 10:05:37.475820 Dram Type= 6, Freq= 0, CH_1, rank 0
1852 10:05:37.482539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1853 10:05:37.482618 ==
1854 10:05:37.482681 DQS Delay:
1855 10:05:37.482749 DQS0 = 0, DQS1 = 0
1856 10:05:37.485810 DQM Delay:
1857 10:05:37.485884 DQM0 = 84, DQM1 = 74
1858 10:05:37.489039 DQ Delay:
1859 10:05:37.492113 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =84
1860 10:05:37.495670 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =80
1861 10:05:37.498835 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1862 10:05:37.502170 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1863 10:05:37.502245
1864 10:05:37.502307
1865 10:05:37.508884 [DQSOSCAuto] RK0, (LSB)MR18= 0x2aff, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
1866 10:05:37.512369 CH1 RK0: MR19=605, MR18=2AFF
1867 10:05:37.518863 CH1_RK0: MR19=0x605, MR18=0x2AFF, DQSOSC=399, MR23=63, INC=92, DEC=61
1868 10:05:37.518939
1869 10:05:37.522314 ----->DramcWriteLeveling(PI) begin...
1870 10:05:37.522397 ==
1871 10:05:37.525347 Dram Type= 6, Freq= 0, CH_1, rank 1
1872 10:05:37.528725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1873 10:05:37.528800 ==
1874 10:05:37.532472 Write leveling (Byte 0): 29 => 29
1875 10:05:37.535576 Write leveling (Byte 1): 31 => 31
1876 10:05:37.539115 DramcWriteLeveling(PI) end<-----
1877 10:05:37.539189
1878 10:05:37.539251 ==
1879 10:05:37.542110 Dram Type= 6, Freq= 0, CH_1, rank 1
1880 10:05:37.545815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1881 10:05:37.545907 ==
1882 10:05:37.549316 [Gating] SW mode calibration
1883 10:05:37.556067 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1884 10:05:37.562181 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1885 10:05:37.565694 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1886 10:05:37.568853 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1887 10:05:37.575628 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1888 10:05:37.578746 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 10:05:37.582368 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 10:05:37.589229 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 10:05:37.592477 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 10:05:37.595839 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 10:05:37.602547 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 10:05:37.605258 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 10:05:37.609005 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 10:05:37.615757 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 10:05:37.618523 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 10:05:37.622296 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1899 10:05:37.628663 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 10:05:37.632002 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 10:05:37.635795 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1902 10:05:37.641964 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1903 10:05:37.645667 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1904 10:05:37.648888 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 10:05:37.652129 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 10:05:37.658865 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 10:05:37.661949 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 10:05:37.665541 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 10:05:37.672191 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 10:05:37.675187 0 9 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
1911 10:05:37.678720 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1912 10:05:37.685791 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 10:05:37.688752 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 10:05:37.692225 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1915 10:05:37.699158 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 10:05:37.702045 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 10:05:37.705706 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 10:05:37.712004 0 10 4 | B1->B0 | 3030 2727 | 0 0 | (1 0) (0 0)
1919 10:05:37.715581 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1920 10:05:37.719177 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 10:05:37.725713 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 10:05:37.754866 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 10:05:37.754975 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 10:05:37.755079 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 10:05:37.755181 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 10:05:37.755281 0 11 4 | B1->B0 | 3030 3636 | 0 1 | (0 0) (1 1)
1927 10:05:37.755384 0 11 8 | B1->B0 | 3d3d 4545 | 0 1 | (1 1) (0 0)
1928 10:05:37.755708 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 10:05:37.758686 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 10:05:37.762516 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 10:05:37.769000 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 10:05:37.772560 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 10:05:37.775460 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 10:05:37.782141 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1935 10:05:37.785309 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 10:05:37.789108 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 10:05:37.795570 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 10:05:37.799186 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 10:05:37.801973 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 10:05:37.809023 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 10:05:37.812036 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 10:05:37.815449 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 10:05:37.822117 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 10:05:37.825586 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 10:05:37.828865 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 10:05:37.832151 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 10:05:37.839054 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 10:05:37.842177 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 10:05:37.845851 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1950 10:05:37.852236 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 10:05:37.855976 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1952 10:05:37.859039 Total UI for P1: 0, mck2ui 16
1953 10:05:37.862760 best dqsien dly found for B0: ( 0, 14, 6)
1954 10:05:37.865619 Total UI for P1: 0, mck2ui 16
1955 10:05:37.869215 best dqsien dly found for B1: ( 0, 14, 6)
1956 10:05:37.872112 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1957 10:05:37.875504 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1958 10:05:37.875609
1959 10:05:37.878886 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1960 10:05:37.882521 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1961 10:05:37.885469 [Gating] SW calibration Done
1962 10:05:37.885550 ==
1963 10:05:37.888806 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 10:05:37.892276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 10:05:37.895655 ==
1966 10:05:37.895736 RX Vref Scan: 0
1967 10:05:37.895800
1968 10:05:37.899245 RX Vref 0 -> 0, step: 1
1969 10:05:37.899329
1970 10:05:37.902248 RX Delay -130 -> 252, step: 16
1971 10:05:37.905685 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1972 10:05:37.908636 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1973 10:05:37.912048 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1974 10:05:37.915551 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1975 10:05:37.922475 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1976 10:05:37.926018 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1977 10:05:37.928919 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1978 10:05:37.932456 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1979 10:05:37.935575 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1980 10:05:37.938935 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1981 10:05:37.945557 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1982 10:05:37.949089 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1983 10:05:37.952038 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1984 10:05:37.955672 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1985 10:05:37.962504 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1986 10:05:37.965490 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1987 10:05:37.965592 ==
1988 10:05:37.968706 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 10:05:37.972209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 10:05:37.972329 ==
1991 10:05:37.972422 DQS Delay:
1992 10:05:37.975783 DQS0 = 0, DQS1 = 0
1993 10:05:37.975933 DQM Delay:
1994 10:05:37.978873 DQM0 = 79, DQM1 = 78
1995 10:05:37.978983 DQ Delay:
1996 10:05:37.982528 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1997 10:05:37.985707 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1998 10:05:37.988679 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1999 10:05:37.992077 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2000 10:05:37.992189
2001 10:05:37.992283
2002 10:05:37.992382 ==
2003 10:05:37.995637 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 10:05:37.999151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 10:05:38.002112 ==
2006 10:05:38.002193
2007 10:05:38.002256
2008 10:05:38.002314 TX Vref Scan disable
2009 10:05:38.005687 == TX Byte 0 ==
2010 10:05:38.008687 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2011 10:05:38.012289 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2012 10:05:38.015298 == TX Byte 1 ==
2013 10:05:38.018730 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2014 10:05:38.022109 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2015 10:05:38.025562 ==
2016 10:05:38.025692 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 10:05:38.032016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 10:05:38.032154 ==
2019 10:05:38.044811 TX Vref=22, minBit 7, minWin=27, winSum=444
2020 10:05:38.047687 TX Vref=24, minBit 13, minWin=27, winSum=450
2021 10:05:38.051170 TX Vref=26, minBit 0, minWin=27, winSum=450
2022 10:05:38.054761 TX Vref=28, minBit 15, minWin=27, winSum=452
2023 10:05:38.057736 TX Vref=30, minBit 15, minWin=27, winSum=452
2024 10:05:38.064578 TX Vref=32, minBit 0, minWin=28, winSum=454
2025 10:05:38.067683 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
2026 10:05:38.067768
2027 10:05:38.071327 Final TX Range 1 Vref 32
2028 10:05:38.071421
2029 10:05:38.071505 ==
2030 10:05:38.074122 Dram Type= 6, Freq= 0, CH_1, rank 1
2031 10:05:38.077767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2032 10:05:38.080919 ==
2033 10:05:38.081002
2034 10:05:38.081067
2035 10:05:38.081127 TX Vref Scan disable
2036 10:05:38.084442 == TX Byte 0 ==
2037 10:05:38.088108 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2038 10:05:38.091216 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2039 10:05:38.094539 == TX Byte 1 ==
2040 10:05:38.097513 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2041 10:05:38.104666 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2042 10:05:38.104750
2043 10:05:38.104816 [DATLAT]
2044 10:05:38.104876 Freq=800, CH1 RK1
2045 10:05:38.104933
2046 10:05:38.107937 DATLAT Default: 0xa
2047 10:05:38.108020 0, 0xFFFF, sum = 0
2048 10:05:38.111012 1, 0xFFFF, sum = 0
2049 10:05:38.111096 2, 0xFFFF, sum = 0
2050 10:05:38.114594 3, 0xFFFF, sum = 0
2051 10:05:38.114678 4, 0xFFFF, sum = 0
2052 10:05:38.117850 5, 0xFFFF, sum = 0
2053 10:05:38.121276 6, 0xFFFF, sum = 0
2054 10:05:38.121384 7, 0xFFFF, sum = 0
2055 10:05:38.124687 8, 0xFFFF, sum = 0
2056 10:05:38.124769 9, 0x0, sum = 1
2057 10:05:38.124836 10, 0x0, sum = 2
2058 10:05:38.128009 11, 0x0, sum = 3
2059 10:05:38.128093 12, 0x0, sum = 4
2060 10:05:38.131436 best_step = 10
2061 10:05:38.131510
2062 10:05:38.131573 ==
2063 10:05:38.134481 Dram Type= 6, Freq= 0, CH_1, rank 1
2064 10:05:38.137778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2065 10:05:38.137879 ==
2066 10:05:38.141416 RX Vref Scan: 0
2067 10:05:38.141498
2068 10:05:38.141563 RX Vref 0 -> 0, step: 1
2069 10:05:38.141624
2070 10:05:38.145095 RX Delay -95 -> 252, step: 8
2071 10:05:38.151287 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2072 10:05:38.154795 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2073 10:05:38.157922 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2074 10:05:38.161292 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2075 10:05:38.164491 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2076 10:05:38.171117 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
2077 10:05:38.174756 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2078 10:05:38.178122 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2079 10:05:38.181188 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2080 10:05:38.184905 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2081 10:05:38.191630 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2082 10:05:38.195112 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2083 10:05:38.197922 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2084 10:05:38.201459 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2085 10:05:38.204818 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2086 10:05:38.211801 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2087 10:05:38.211883 ==
2088 10:05:38.214762 Dram Type= 6, Freq= 0, CH_1, rank 1
2089 10:05:38.217989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2090 10:05:38.218072 ==
2091 10:05:38.218137 DQS Delay:
2092 10:05:38.221502 DQS0 = 0, DQS1 = 0
2093 10:05:38.221584 DQM Delay:
2094 10:05:38.224410 DQM0 = 80, DQM1 = 75
2095 10:05:38.224493 DQ Delay:
2096 10:05:38.228005 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2097 10:05:38.231652 DQ4 =84, DQ5 =88, DQ6 =92, DQ7 =76
2098 10:05:38.234485 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2099 10:05:38.237797 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2100 10:05:38.237888
2101 10:05:38.237953
2102 10:05:38.244530 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
2103 10:05:38.247914 CH1 RK1: MR19=606, MR18=1B26
2104 10:05:38.254892 CH1_RK1: MR19=0x606, MR18=0x1B26, DQSOSC=400, MR23=63, INC=92, DEC=61
2105 10:05:38.258388 [RxdqsGatingPostProcess] freq 800
2106 10:05:38.264715 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2107 10:05:38.267899 Pre-setting of DQS Precalculation
2108 10:05:38.271417 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2109 10:05:38.278030 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2110 10:05:38.284724 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2111 10:05:38.284805
2112 10:05:38.284876
2113 10:05:38.287786 [Calibration Summary] 1600 Mbps
2114 10:05:38.291499 CH 0, Rank 0
2115 10:05:38.291574 SW Impedance : PASS
2116 10:05:38.294546 DUTY Scan : NO K
2117 10:05:38.297941 ZQ Calibration : PASS
2118 10:05:38.298014 Jitter Meter : NO K
2119 10:05:38.301598 CBT Training : PASS
2120 10:05:38.304516 Write leveling : PASS
2121 10:05:38.304591 RX DQS gating : PASS
2122 10:05:38.308053 RX DQ/DQS(RDDQC) : PASS
2123 10:05:38.308134 TX DQ/DQS : PASS
2124 10:05:38.311302 RX DATLAT : PASS
2125 10:05:38.314927 RX DQ/DQS(Engine): PASS
2126 10:05:38.315006 TX OE : NO K
2127 10:05:38.317876 All Pass.
2128 10:05:38.317971
2129 10:05:38.318061 CH 0, Rank 1
2130 10:05:38.321098 SW Impedance : PASS
2131 10:05:38.321170 DUTY Scan : NO K
2132 10:05:38.324618 ZQ Calibration : PASS
2133 10:05:38.328280 Jitter Meter : NO K
2134 10:05:38.328354 CBT Training : PASS
2135 10:05:38.331564 Write leveling : PASS
2136 10:05:38.334493 RX DQS gating : PASS
2137 10:05:38.334571 RX DQ/DQS(RDDQC) : PASS
2138 10:05:38.338063 TX DQ/DQS : PASS
2139 10:05:38.341384 RX DATLAT : PASS
2140 10:05:38.341463 RX DQ/DQS(Engine): PASS
2141 10:05:38.344796 TX OE : NO K
2142 10:05:38.344872 All Pass.
2143 10:05:38.344935
2144 10:05:38.348238 CH 1, Rank 0
2145 10:05:38.348315 SW Impedance : PASS
2146 10:05:38.351215 DUTY Scan : NO K
2147 10:05:38.351300 ZQ Calibration : PASS
2148 10:05:38.354563 Jitter Meter : NO K
2149 10:05:38.358414 CBT Training : PASS
2150 10:05:38.358497 Write leveling : PASS
2151 10:05:38.361451 RX DQS gating : PASS
2152 10:05:38.364455 RX DQ/DQS(RDDQC) : PASS
2153 10:05:38.364540 TX DQ/DQS : PASS
2154 10:05:38.367981 RX DATLAT : PASS
2155 10:05:38.371127 RX DQ/DQS(Engine): PASS
2156 10:05:38.371203 TX OE : NO K
2157 10:05:38.374851 All Pass.
2158 10:05:38.374938
2159 10:05:38.375024 CH 1, Rank 1
2160 10:05:38.377720 SW Impedance : PASS
2161 10:05:38.377805 DUTY Scan : NO K
2162 10:05:38.381237 ZQ Calibration : PASS
2163 10:05:38.384458 Jitter Meter : NO K
2164 10:05:38.384544 CBT Training : PASS
2165 10:05:38.388034 Write leveling : PASS
2166 10:05:38.391111 RX DQS gating : PASS
2167 10:05:38.391195 RX DQ/DQS(RDDQC) : PASS
2168 10:05:38.394684 TX DQ/DQS : PASS
2169 10:05:38.394769 RX DATLAT : PASS
2170 10:05:38.397807 RX DQ/DQS(Engine): PASS
2171 10:05:38.401303 TX OE : NO K
2172 10:05:38.401389 All Pass.
2173 10:05:38.401473
2174 10:05:38.404408 DramC Write-DBI off
2175 10:05:38.404493 PER_BANK_REFRESH: Hybrid Mode
2176 10:05:38.408058 TX_TRACKING: ON
2177 10:05:38.411369 [GetDramInforAfterCalByMRR] Vendor 6.
2178 10:05:38.414898 [GetDramInforAfterCalByMRR] Revision 606.
2179 10:05:38.418038 [GetDramInforAfterCalByMRR] Revision 2 0.
2180 10:05:38.418122 MR0 0x3b3b
2181 10:05:38.421560 MR8 0x5151
2182 10:05:38.424666 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2183 10:05:38.424750
2184 10:05:38.424835 MR0 0x3b3b
2185 10:05:38.427771 MR8 0x5151
2186 10:05:38.431210 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2187 10:05:38.431294
2188 10:05:38.437780 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2189 10:05:38.441335 [FAST_K] Save calibration result to emmc
2190 10:05:38.448154 [FAST_K] Save calibration result to emmc
2191 10:05:38.448238 dram_init: config_dvfs: 1
2192 10:05:38.451324 dramc_set_vcore_voltage set vcore to 662500
2193 10:05:38.454606 Read voltage for 1200, 2
2194 10:05:38.454689 Vio18 = 0
2195 10:05:38.457738 Vcore = 662500
2196 10:05:38.457846 Vdram = 0
2197 10:05:38.457947 Vddq = 0
2198 10:05:38.460879 Vmddr = 0
2199 10:05:38.464786 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2200 10:05:38.471207 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2201 10:05:38.471318 MEM_TYPE=3, freq_sel=15
2202 10:05:38.474356 sv_algorithm_assistance_LP4_1600
2203 10:05:38.480930 ============ PULL DRAM RESETB DOWN ============
2204 10:05:38.484609 ========== PULL DRAM RESETB DOWN end =========
2205 10:05:38.487612 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2206 10:05:38.491554 ===================================
2207 10:05:38.494325 LPDDR4 DRAM CONFIGURATION
2208 10:05:38.498048 ===================================
2209 10:05:38.498153 EX_ROW_EN[0] = 0x0
2210 10:05:38.500981 EX_ROW_EN[1] = 0x0
2211 10:05:38.504163 LP4Y_EN = 0x0
2212 10:05:38.504261 WORK_FSP = 0x0
2213 10:05:38.507722 WL = 0x4
2214 10:05:38.507830 RL = 0x4
2215 10:05:38.510794 BL = 0x2
2216 10:05:38.510961 RPST = 0x0
2217 10:05:38.514314 RD_PRE = 0x0
2218 10:05:38.514412 WR_PRE = 0x1
2219 10:05:38.517838 WR_PST = 0x0
2220 10:05:38.517935 DBI_WR = 0x0
2221 10:05:38.520816 DBI_RD = 0x0
2222 10:05:38.520916 OTF = 0x1
2223 10:05:38.524378 ===================================
2224 10:05:38.527317 ===================================
2225 10:05:38.531077 ANA top config
2226 10:05:38.534522 ===================================
2227 10:05:38.534630 DLL_ASYNC_EN = 0
2228 10:05:38.537696 ALL_SLAVE_EN = 0
2229 10:05:38.541223 NEW_RANK_MODE = 1
2230 10:05:38.544580 DLL_IDLE_MODE = 1
2231 10:05:38.548044 LP45_APHY_COMB_EN = 1
2232 10:05:38.548157 TX_ODT_DIS = 1
2233 10:05:38.551086 NEW_8X_MODE = 1
2234 10:05:38.554157 ===================================
2235 10:05:38.557473 ===================================
2236 10:05:38.560995 data_rate = 2400
2237 10:05:38.564296 CKR = 1
2238 10:05:38.567643 DQ_P2S_RATIO = 8
2239 10:05:38.571151 ===================================
2240 10:05:38.571267 CA_P2S_RATIO = 8
2241 10:05:38.574378 DQ_CA_OPEN = 0
2242 10:05:38.577789 DQ_SEMI_OPEN = 0
2243 10:05:38.580899 CA_SEMI_OPEN = 0
2244 10:05:38.584036 CA_FULL_RATE = 0
2245 10:05:38.587643 DQ_CKDIV4_EN = 0
2246 10:05:38.587720 CA_CKDIV4_EN = 0
2247 10:05:38.591200 CA_PREDIV_EN = 0
2248 10:05:38.594132 PH8_DLY = 17
2249 10:05:38.597346 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2250 10:05:38.601099 DQ_AAMCK_DIV = 4
2251 10:05:38.604567 CA_AAMCK_DIV = 4
2252 10:05:38.604646 CA_ADMCK_DIV = 4
2253 10:05:38.607631 DQ_TRACK_CA_EN = 0
2254 10:05:38.611297 CA_PICK = 1200
2255 10:05:38.614479 CA_MCKIO = 1200
2256 10:05:38.617989 MCKIO_SEMI = 0
2257 10:05:38.620741 PLL_FREQ = 2366
2258 10:05:38.624513 DQ_UI_PI_RATIO = 32
2259 10:05:38.624615 CA_UI_PI_RATIO = 0
2260 10:05:38.627476 ===================================
2261 10:05:38.630998 ===================================
2262 10:05:38.634179 memory_type:LPDDR4
2263 10:05:38.637513 GP_NUM : 10
2264 10:05:38.637608 SRAM_EN : 1
2265 10:05:38.640615 MD32_EN : 0
2266 10:05:38.644354 ===================================
2267 10:05:38.647767 [ANA_INIT] >>>>>>>>>>>>>>
2268 10:05:38.650709 <<<<<< [CONFIGURE PHASE]: ANA_TX
2269 10:05:38.654189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2270 10:05:38.657547 ===================================
2271 10:05:38.657665 data_rate = 2400,PCW = 0X5b00
2272 10:05:38.661064 ===================================
2273 10:05:38.664580 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2274 10:05:38.670989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2275 10:05:38.677566 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2276 10:05:38.681254 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2277 10:05:38.684354 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2278 10:05:38.687139 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2279 10:05:38.690795 [ANA_INIT] flow start
2280 10:05:38.690894 [ANA_INIT] PLL >>>>>>>>
2281 10:05:38.693994 [ANA_INIT] PLL <<<<<<<<
2282 10:05:38.697614 [ANA_INIT] MIDPI >>>>>>>>
2283 10:05:38.700879 [ANA_INIT] MIDPI <<<<<<<<
2284 10:05:38.700979 [ANA_INIT] DLL >>>>>>>>
2285 10:05:38.703933 [ANA_INIT] DLL <<<<<<<<
2286 10:05:38.704037 [ANA_INIT] flow end
2287 10:05:38.711092 ============ LP4 DIFF to SE enter ============
2288 10:05:38.714117 ============ LP4 DIFF to SE exit ============
2289 10:05:38.717361 [ANA_INIT] <<<<<<<<<<<<<
2290 10:05:38.720782 [Flow] Enable top DCM control >>>>>
2291 10:05:38.724363 [Flow] Enable top DCM control <<<<<
2292 10:05:38.727169 Enable DLL master slave shuffle
2293 10:05:38.730732 ==============================================================
2294 10:05:38.734167 Gating Mode config
2295 10:05:38.737251 ==============================================================
2296 10:05:38.741016 Config description:
2297 10:05:38.751121 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2298 10:05:38.757077 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2299 10:05:38.760618 SELPH_MODE 0: By rank 1: By Phase
2300 10:05:38.767645 ==============================================================
2301 10:05:38.770620 GAT_TRACK_EN = 1
2302 10:05:38.774363 RX_GATING_MODE = 2
2303 10:05:38.777479 RX_GATING_TRACK_MODE = 2
2304 10:05:38.780864 SELPH_MODE = 1
2305 10:05:38.780991 PICG_EARLY_EN = 1
2306 10:05:38.784505 VALID_LAT_VALUE = 1
2307 10:05:38.790527 ==============================================================
2308 10:05:38.794359 Enter into Gating configuration >>>>
2309 10:05:38.797325 Exit from Gating configuration <<<<
2310 10:05:38.800485 Enter into DVFS_PRE_config >>>>>
2311 10:05:38.810750 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2312 10:05:38.814349 Exit from DVFS_PRE_config <<<<<
2313 10:05:38.817485 Enter into PICG configuration >>>>
2314 10:05:38.820643 Exit from PICG configuration <<<<
2315 10:05:38.823771 [RX_INPUT] configuration >>>>>
2316 10:05:38.827110 [RX_INPUT] configuration <<<<<
2317 10:05:38.830595 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2318 10:05:38.837598 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2319 10:05:38.843857 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2320 10:05:38.850502 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2321 10:05:38.857343 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2322 10:05:38.860751 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2323 10:05:38.867237 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2324 10:05:38.870701 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2325 10:05:38.874108 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2326 10:05:38.877211 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2327 10:05:38.880240 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2328 10:05:38.887228 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2329 10:05:38.890964 ===================================
2330 10:05:38.893768 LPDDR4 DRAM CONFIGURATION
2331 10:05:38.897515 ===================================
2332 10:05:38.897613 EX_ROW_EN[0] = 0x0
2333 10:05:38.900836 EX_ROW_EN[1] = 0x0
2334 10:05:38.900936 LP4Y_EN = 0x0
2335 10:05:38.903917 WORK_FSP = 0x0
2336 10:05:38.903987 WL = 0x4
2337 10:05:38.907436 RL = 0x4
2338 10:05:38.907503 BL = 0x2
2339 10:05:38.910436 RPST = 0x0
2340 10:05:38.910503 RD_PRE = 0x0
2341 10:05:38.914122 WR_PRE = 0x1
2342 10:05:38.914214 WR_PST = 0x0
2343 10:05:38.917241 DBI_WR = 0x0
2344 10:05:38.917333 DBI_RD = 0x0
2345 10:05:38.920764 OTF = 0x1
2346 10:05:38.923795 ===================================
2347 10:05:38.926937 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2348 10:05:38.930320 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2349 10:05:38.936952 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2350 10:05:38.940450 ===================================
2351 10:05:38.940521 LPDDR4 DRAM CONFIGURATION
2352 10:05:38.943949 ===================================
2353 10:05:38.947360 EX_ROW_EN[0] = 0x10
2354 10:05:38.950525 EX_ROW_EN[1] = 0x0
2355 10:05:38.950594 LP4Y_EN = 0x0
2356 10:05:38.954162 WORK_FSP = 0x0
2357 10:05:38.954255 WL = 0x4
2358 10:05:38.957125 RL = 0x4
2359 10:05:38.957220 BL = 0x2
2360 10:05:38.960748 RPST = 0x0
2361 10:05:38.960844 RD_PRE = 0x0
2362 10:05:38.963838 WR_PRE = 0x1
2363 10:05:38.963905 WR_PST = 0x0
2364 10:05:38.967298 DBI_WR = 0x0
2365 10:05:38.967420 DBI_RD = 0x0
2366 10:05:38.970192 OTF = 0x1
2367 10:05:38.973794 ===================================
2368 10:05:38.980134 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2369 10:05:38.980240 ==
2370 10:05:38.983648 Dram Type= 6, Freq= 0, CH_0, rank 0
2371 10:05:38.987062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2372 10:05:38.987161 ==
2373 10:05:38.990050 [Duty_Offset_Calibration]
2374 10:05:38.990142 B0:2 B1:-1 CA:1
2375 10:05:38.990229
2376 10:05:38.993443 [DutyScan_Calibration_Flow] k_type=0
2377 10:05:39.003131
2378 10:05:39.003234 ==CLK 0==
2379 10:05:39.006707 Final CLK duty delay cell = -4
2380 10:05:39.009897 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2381 10:05:39.013308 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2382 10:05:39.016366 [-4] AVG Duty = 4953%(X100)
2383 10:05:39.016445
2384 10:05:39.019995 CH0 CLK Duty spec in!! Max-Min= 156%
2385 10:05:39.023578 [DutyScan_Calibration_Flow] ====Done====
2386 10:05:39.023657
2387 10:05:39.026681 [DutyScan_Calibration_Flow] k_type=1
2388 10:05:39.041496
2389 10:05:39.041574 ==DQS 0 ==
2390 10:05:39.044348 Final DQS duty delay cell = -4
2391 10:05:39.047656 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2392 10:05:39.051106 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2393 10:05:39.054698 [-4] AVG Duty = 4938%(X100)
2394 10:05:39.054799
2395 10:05:39.054886 ==DQS 1 ==
2396 10:05:39.057794 Final DQS duty delay cell = -4
2397 10:05:39.061284 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2398 10:05:39.064304 [-4] MIN Duty = 4969%(X100), DQS PI = 50
2399 10:05:39.068090 [-4] AVG Duty = 5046%(X100)
2400 10:05:39.068184
2401 10:05:39.071235 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2402 10:05:39.071335
2403 10:05:39.074555 CH0 DQS 1 Duty spec in!! Max-Min= 155%
2404 10:05:39.078111 [DutyScan_Calibration_Flow] ====Done====
2405 10:05:39.078216
2406 10:05:39.081475 [DutyScan_Calibration_Flow] k_type=3
2407 10:05:39.098455
2408 10:05:39.098534 ==DQM 0 ==
2409 10:05:39.101551 Final DQM duty delay cell = 0
2410 10:05:39.105051 [0] MAX Duty = 5031%(X100), DQS PI = 54
2411 10:05:39.108837 [0] MIN Duty = 4907%(X100), DQS PI = 2
2412 10:05:39.108916 [0] AVG Duty = 4969%(X100)
2413 10:05:39.111781
2414 10:05:39.111859 ==DQM 1 ==
2415 10:05:39.115236 Final DQM duty delay cell = 0
2416 10:05:39.118553 [0] MAX Duty = 5156%(X100), DQS PI = 62
2417 10:05:39.122088 [0] MIN Duty = 4969%(X100), DQS PI = 10
2418 10:05:39.122167 [0] AVG Duty = 5062%(X100)
2419 10:05:39.125331
2420 10:05:39.128394 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2421 10:05:39.128473
2422 10:05:39.132127 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2423 10:05:39.135089 [DutyScan_Calibration_Flow] ====Done====
2424 10:05:39.135168
2425 10:05:39.138576 [DutyScan_Calibration_Flow] k_type=2
2426 10:05:39.154112
2427 10:05:39.154190 ==DQ 0 ==
2428 10:05:39.157697 Final DQ duty delay cell = -4
2429 10:05:39.160889 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2430 10:05:39.164320 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2431 10:05:39.167676 [-4] AVG Duty = 4969%(X100)
2432 10:05:39.167755
2433 10:05:39.167817 ==DQ 1 ==
2434 10:05:39.170584 Final DQ duty delay cell = 0
2435 10:05:39.173974 [0] MAX Duty = 5031%(X100), DQS PI = 18
2436 10:05:39.177432 [0] MIN Duty = 4907%(X100), DQS PI = 46
2437 10:05:39.177526 [0] AVG Duty = 4969%(X100)
2438 10:05:39.180822
2439 10:05:39.184106 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2440 10:05:39.184203
2441 10:05:39.187525 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2442 10:05:39.190928 [DutyScan_Calibration_Flow] ====Done====
2443 10:05:39.191032 ==
2444 10:05:39.194166 Dram Type= 6, Freq= 0, CH_1, rank 0
2445 10:05:39.197593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2446 10:05:39.197669 ==
2447 10:05:39.200841 [Duty_Offset_Calibration]
2448 10:05:39.200911 B0:1 B1:1 CA:2
2449 10:05:39.200970
2450 10:05:39.203795 [DutyScan_Calibration_Flow] k_type=0
2451 10:05:39.214679
2452 10:05:39.214759 ==CLK 0==
2453 10:05:39.217537 Final CLK duty delay cell = 0
2454 10:05:39.221195 [0] MAX Duty = 5156%(X100), DQS PI = 24
2455 10:05:39.224786 [0] MIN Duty = 4969%(X100), DQS PI = 42
2456 10:05:39.224870 [0] AVG Duty = 5062%(X100)
2457 10:05:39.227825
2458 10:05:39.230951 CH1 CLK Duty spec in!! Max-Min= 187%
2459 10:05:39.234114 [DutyScan_Calibration_Flow] ====Done====
2460 10:05:39.234207
2461 10:05:39.237685 [DutyScan_Calibration_Flow] k_type=1
2462 10:05:39.253542
2463 10:05:39.253651 ==DQS 0 ==
2464 10:05:39.257119 Final DQS duty delay cell = 0
2465 10:05:39.260688 [0] MAX Duty = 5031%(X100), DQS PI = 18
2466 10:05:39.263779 [0] MIN Duty = 4813%(X100), DQS PI = 50
2467 10:05:39.267479 [0] AVG Duty = 4922%(X100)
2468 10:05:39.267605
2469 10:05:39.267728 ==DQS 1 ==
2470 10:05:39.270725 Final DQS duty delay cell = 0
2471 10:05:39.273469 [0] MAX Duty = 5062%(X100), DQS PI = 36
2472 10:05:39.277092 [0] MIN Duty = 4907%(X100), DQS PI = 16
2473 10:05:39.280322 [0] AVG Duty = 4984%(X100)
2474 10:05:39.280477
2475 10:05:39.283635 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2476 10:05:39.283738
2477 10:05:39.286871 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2478 10:05:39.290397 [DutyScan_Calibration_Flow] ====Done====
2479 10:05:39.290561
2480 10:05:39.293925 [DutyScan_Calibration_Flow] k_type=3
2481 10:05:39.310121
2482 10:05:39.310228 ==DQM 0 ==
2483 10:05:39.313353 Final DQM duty delay cell = 0
2484 10:05:39.317153 [0] MAX Duty = 5093%(X100), DQS PI = 16
2485 10:05:39.319973 [0] MIN Duty = 4907%(X100), DQS PI = 48
2486 10:05:39.323687 [0] AVG Duty = 5000%(X100)
2487 10:05:39.323813
2488 10:05:39.323944 ==DQM 1 ==
2489 10:05:39.326682 Final DQM duty delay cell = 0
2490 10:05:39.330345 [0] MAX Duty = 5156%(X100), DQS PI = 62
2491 10:05:39.333291 [0] MIN Duty = 4969%(X100), DQS PI = 4
2492 10:05:39.336932 [0] AVG Duty = 5062%(X100)
2493 10:05:39.337039
2494 10:05:39.340197 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2495 10:05:39.340300
2496 10:05:39.343161 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2497 10:05:39.346745 [DutyScan_Calibration_Flow] ====Done====
2498 10:05:39.346843
2499 10:05:39.350371 [DutyScan_Calibration_Flow] k_type=2
2500 10:05:39.367016
2501 10:05:39.367101 ==DQ 0 ==
2502 10:05:39.370192 Final DQ duty delay cell = 0
2503 10:05:39.373353 [0] MAX Duty = 5124%(X100), DQS PI = 18
2504 10:05:39.376674 [0] MIN Duty = 4938%(X100), DQS PI = 50
2505 10:05:39.376761 [0] AVG Duty = 5031%(X100)
2506 10:05:39.376829
2507 10:05:39.380126 ==DQ 1 ==
2508 10:05:39.383400 Final DQ duty delay cell = 0
2509 10:05:39.386826 [0] MAX Duty = 5093%(X100), DQS PI = 10
2510 10:05:39.390095 [0] MIN Duty = 5000%(X100), DQS PI = 50
2511 10:05:39.390179 [0] AVG Duty = 5046%(X100)
2512 10:05:39.390246
2513 10:05:39.393550 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2514 10:05:39.396880
2515 10:05:39.400243 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2516 10:05:39.403667 [DutyScan_Calibration_Flow] ====Done====
2517 10:05:39.406535 nWR fixed to 30
2518 10:05:39.406620 [ModeRegInit_LP4] CH0 RK0
2519 10:05:39.409957 [ModeRegInit_LP4] CH0 RK1
2520 10:05:39.413663 [ModeRegInit_LP4] CH1 RK0
2521 10:05:39.413747 [ModeRegInit_LP4] CH1 RK1
2522 10:05:39.417199 match AC timing 7
2523 10:05:39.420174 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2524 10:05:39.423344 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2525 10:05:39.430043 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2526 10:05:39.433172 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2527 10:05:39.439803 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2528 10:05:39.439893 ==
2529 10:05:39.443506 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 10:05:39.446852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2531 10:05:39.446926 ==
2532 10:05:39.453360 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2533 10:05:39.456771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2534 10:05:39.466814 [CA 0] Center 40 (10~71) winsize 62
2535 10:05:39.469839 [CA 1] Center 39 (9~70) winsize 62
2536 10:05:39.473260 [CA 2] Center 36 (6~67) winsize 62
2537 10:05:39.476974 [CA 3] Center 36 (5~67) winsize 63
2538 10:05:39.480190 [CA 4] Center 35 (5~65) winsize 61
2539 10:05:39.483069 [CA 5] Center 34 (4~64) winsize 61
2540 10:05:39.483171
2541 10:05:39.486530 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2542 10:05:39.486612
2543 10:05:39.490014 [CATrainingPosCal] consider 1 rank data
2544 10:05:39.493464 u2DelayCellTimex100 = 270/100 ps
2545 10:05:39.496978 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2546 10:05:39.503277 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2547 10:05:39.506644 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2548 10:05:39.510161 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2549 10:05:39.513119 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2550 10:05:39.516422 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2551 10:05:39.516515
2552 10:05:39.520087 CA PerBit enable=1, Macro0, CA PI delay=34
2553 10:05:39.520193
2554 10:05:39.523654 [CBTSetCACLKResult] CA Dly = 34
2555 10:05:39.523739 CS Dly: 7 (0~38)
2556 10:05:39.526758 ==
2557 10:05:39.529764 Dram Type= 6, Freq= 0, CH_0, rank 1
2558 10:05:39.533349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2559 10:05:39.533425 ==
2560 10:05:39.536628 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2561 10:05:39.543192 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2562 10:05:39.552535 [CA 0] Center 39 (9~70) winsize 62
2563 10:05:39.556013 [CA 1] Center 39 (9~70) winsize 62
2564 10:05:39.559352 [CA 2] Center 36 (6~67) winsize 62
2565 10:05:39.563002 [CA 3] Center 36 (5~67) winsize 63
2566 10:05:39.565893 [CA 4] Center 34 (4~65) winsize 62
2567 10:05:39.569387 [CA 5] Center 34 (4~64) winsize 61
2568 10:05:39.569468
2569 10:05:39.573049 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2570 10:05:39.573126
2571 10:05:39.576082 [CATrainingPosCal] consider 2 rank data
2572 10:05:39.579153 u2DelayCellTimex100 = 270/100 ps
2573 10:05:39.582778 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2574 10:05:39.586266 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2575 10:05:39.592844 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2576 10:05:39.596181 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2577 10:05:39.599597 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2578 10:05:39.603006 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2579 10:05:39.603115
2580 10:05:39.606592 CA PerBit enable=1, Macro0, CA PI delay=34
2581 10:05:39.606677
2582 10:05:39.609272 [CBTSetCACLKResult] CA Dly = 34
2583 10:05:39.609362 CS Dly: 8 (0~41)
2584 10:05:39.609447
2585 10:05:39.612876 ----->DramcWriteLeveling(PI) begin...
2586 10:05:39.615904 ==
2587 10:05:39.615993 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 10:05:39.622925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 10:05:39.623007 ==
2590 10:05:39.626336 Write leveling (Byte 0): 30 => 30
2591 10:05:39.629547 Write leveling (Byte 1): 30 => 30
2592 10:05:39.632559 DramcWriteLeveling(PI) end<-----
2593 10:05:39.632641
2594 10:05:39.632706 ==
2595 10:05:39.636220 Dram Type= 6, Freq= 0, CH_0, rank 0
2596 10:05:39.639230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2597 10:05:39.639338 ==
2598 10:05:39.642994 [Gating] SW mode calibration
2599 10:05:39.649145 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2600 10:05:39.652855 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2601 10:05:39.659268 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 10:05:39.662820 0 15 4 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2603 10:05:39.666342 0 15 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2604 10:05:39.672578 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 10:05:39.676198 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 10:05:39.679219 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 10:05:39.686399 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 10:05:39.689361 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 10:05:39.692858 1 0 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2610 10:05:39.699210 1 0 4 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2611 10:05:39.702615 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 10:05:39.706037 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 10:05:39.713115 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 10:05:39.716445 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 10:05:39.719344 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 10:05:39.725751 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 10:05:39.729182 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2618 10:05:39.732778 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2619 10:05:39.739474 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 10:05:39.742512 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 10:05:39.746018 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 10:05:39.749167 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 10:05:39.755959 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 10:05:39.759544 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 10:05:39.763455 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2626 10:05:39.769410 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2627 10:05:39.772936 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 10:05:39.776459 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 10:05:39.782502 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 10:05:39.786036 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 10:05:39.789187 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 10:05:39.795961 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 10:05:39.799282 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 10:05:39.802923 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 10:05:39.809289 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 10:05:39.812719 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 10:05:39.816115 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 10:05:39.822920 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 10:05:39.825757 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 10:05:39.829185 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2641 10:05:39.835911 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2642 10:05:39.838933 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2643 10:05:39.842689 Total UI for P1: 0, mck2ui 16
2644 10:05:39.845698 best dqsien dly found for B0: ( 1, 3, 30)
2645 10:05:39.849426 Total UI for P1: 0, mck2ui 16
2646 10:05:39.852395 best dqsien dly found for B1: ( 1, 3, 30)
2647 10:05:39.855969 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2648 10:05:39.859078 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2649 10:05:39.859178
2650 10:05:39.862196 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2651 10:05:39.865659 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2652 10:05:39.869313 [Gating] SW calibration Done
2653 10:05:39.869411 ==
2654 10:05:39.872638 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 10:05:39.875625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 10:05:39.875739 ==
2657 10:05:39.879098 RX Vref Scan: 0
2658 10:05:39.879207
2659 10:05:39.882520 RX Vref 0 -> 0, step: 1
2660 10:05:39.882625
2661 10:05:39.882719 RX Delay -40 -> 252, step: 8
2662 10:05:39.889104 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2663 10:05:39.892854 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2664 10:05:39.895714 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2665 10:05:39.899208 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2666 10:05:39.902735 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2667 10:05:39.909070 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2668 10:05:39.912467 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2669 10:05:39.916045 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2670 10:05:39.918874 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2671 10:05:39.922705 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2672 10:05:39.925869 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2673 10:05:39.932715 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2674 10:05:39.935745 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2675 10:05:39.939553 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2676 10:05:39.942503 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2677 10:05:39.949094 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2678 10:05:39.949202 ==
2679 10:05:39.952191 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 10:05:39.955906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 10:05:39.956004 ==
2682 10:05:39.956081 DQS Delay:
2683 10:05:39.959559 DQS0 = 0, DQS1 = 0
2684 10:05:39.959655 DQM Delay:
2685 10:05:39.962537 DQM0 = 116, DQM1 = 107
2686 10:05:39.962632 DQ Delay:
2687 10:05:39.965647 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2688 10:05:39.969057 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2689 10:05:39.972752 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2690 10:05:39.976002 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2691 10:05:39.976105
2692 10:05:39.976205
2693 10:05:39.976293 ==
2694 10:05:39.979369 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 10:05:39.985686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 10:05:39.985791 ==
2697 10:05:39.985887
2698 10:05:39.985981
2699 10:05:39.986070 TX Vref Scan disable
2700 10:05:39.989415 == TX Byte 0 ==
2701 10:05:39.992504 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2702 10:05:39.995979 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2703 10:05:39.999587 == TX Byte 1 ==
2704 10:05:40.002689 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2705 10:05:40.006446 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2706 10:05:40.009379 ==
2707 10:05:40.012787 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 10:05:40.016217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 10:05:40.016323 ==
2710 10:05:40.027026 TX Vref=22, minBit 7, minWin=24, winSum=415
2711 10:05:40.030604 TX Vref=24, minBit 1, minWin=25, winSum=423
2712 10:05:40.033802 TX Vref=26, minBit 1, minWin=25, winSum=426
2713 10:05:40.036854 TX Vref=28, minBit 1, minWin=26, winSum=431
2714 10:05:40.040425 TX Vref=30, minBit 1, minWin=26, winSum=432
2715 10:05:40.047221 TX Vref=32, minBit 12, minWin=25, winSum=430
2716 10:05:40.050165 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
2717 10:05:40.050269
2718 10:05:40.054005 Final TX Range 1 Vref 30
2719 10:05:40.054101
2720 10:05:40.054200 ==
2721 10:05:40.056896 Dram Type= 6, Freq= 0, CH_0, rank 0
2722 10:05:40.060551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2723 10:05:40.060649 ==
2724 10:05:40.060747
2725 10:05:40.063513
2726 10:05:40.063581 TX Vref Scan disable
2727 10:05:40.067063 == TX Byte 0 ==
2728 10:05:40.070680 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2729 10:05:40.073747 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2730 10:05:40.077382 == TX Byte 1 ==
2731 10:05:40.080617 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2732 10:05:40.084261 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2733 10:05:40.084370
2734 10:05:40.087164 [DATLAT]
2735 10:05:40.087266 Freq=1200, CH0 RK0
2736 10:05:40.087380
2737 10:05:40.090558 DATLAT Default: 0xd
2738 10:05:40.090659 0, 0xFFFF, sum = 0
2739 10:05:40.093690 1, 0xFFFF, sum = 0
2740 10:05:40.093796 2, 0xFFFF, sum = 0
2741 10:05:40.097230 3, 0xFFFF, sum = 0
2742 10:05:40.097330 4, 0xFFFF, sum = 0
2743 10:05:40.100368 5, 0xFFFF, sum = 0
2744 10:05:40.100468 6, 0xFFFF, sum = 0
2745 10:05:40.103846 7, 0xFFFF, sum = 0
2746 10:05:40.103948 8, 0xFFFF, sum = 0
2747 10:05:40.107252 9, 0xFFFF, sum = 0
2748 10:05:40.110216 10, 0xFFFF, sum = 0
2749 10:05:40.110315 11, 0xFFFF, sum = 0
2750 10:05:40.113761 12, 0x0, sum = 1
2751 10:05:40.113858 13, 0x0, sum = 2
2752 10:05:40.113951 14, 0x0, sum = 3
2753 10:05:40.117101 15, 0x0, sum = 4
2754 10:05:40.117202 best_step = 13
2755 10:05:40.117289
2756 10:05:40.117374 ==
2757 10:05:40.120730 Dram Type= 6, Freq= 0, CH_0, rank 0
2758 10:05:40.127330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2759 10:05:40.127448 ==
2760 10:05:40.127509 RX Vref Scan: 1
2761 10:05:40.127575
2762 10:05:40.131089 Set Vref Range= 32 -> 127
2763 10:05:40.131185
2764 10:05:40.133793 RX Vref 32 -> 127, step: 1
2765 10:05:40.133866
2766 10:05:40.137077 RX Delay -21 -> 252, step: 4
2767 10:05:40.137148
2768 10:05:40.141016 Set Vref, RX VrefLevel [Byte0]: 32
2769 10:05:40.141087 [Byte1]: 32
2770 10:05:40.145752
2771 10:05:40.145850 Set Vref, RX VrefLevel [Byte0]: 33
2772 10:05:40.151773 [Byte1]: 33
2773 10:05:40.151871
2774 10:05:40.155658 Set Vref, RX VrefLevel [Byte0]: 34
2775 10:05:40.158493 [Byte1]: 34
2776 10:05:40.158591
2777 10:05:40.161672 Set Vref, RX VrefLevel [Byte0]: 35
2778 10:05:40.165172 [Byte1]: 35
2779 10:05:40.168848
2780 10:05:40.168944 Set Vref, RX VrefLevel [Byte0]: 36
2781 10:05:40.172291 [Byte1]: 36
2782 10:05:40.177362
2783 10:05:40.177468 Set Vref, RX VrefLevel [Byte0]: 37
2784 10:05:40.180350 [Byte1]: 37
2785 10:05:40.184849
2786 10:05:40.184953 Set Vref, RX VrefLevel [Byte0]: 38
2787 10:05:40.188347 [Byte1]: 38
2788 10:05:40.193067
2789 10:05:40.193166 Set Vref, RX VrefLevel [Byte0]: 39
2790 10:05:40.196415 [Byte1]: 39
2791 10:05:40.200661
2792 10:05:40.200756 Set Vref, RX VrefLevel [Byte0]: 40
2793 10:05:40.204387 [Byte1]: 40
2794 10:05:40.208563
2795 10:05:40.208636 Set Vref, RX VrefLevel [Byte0]: 41
2796 10:05:40.211984 [Byte1]: 41
2797 10:05:40.216771
2798 10:05:40.216870 Set Vref, RX VrefLevel [Byte0]: 42
2799 10:05:40.220200 [Byte1]: 42
2800 10:05:40.224830
2801 10:05:40.224927 Set Vref, RX VrefLevel [Byte0]: 43
2802 10:05:40.227734 [Byte1]: 43
2803 10:05:40.232741
2804 10:05:40.232839 Set Vref, RX VrefLevel [Byte0]: 44
2805 10:05:40.236153 [Byte1]: 44
2806 10:05:40.240601
2807 10:05:40.240699 Set Vref, RX VrefLevel [Byte0]: 45
2808 10:05:40.243588 [Byte1]: 45
2809 10:05:40.248174
2810 10:05:40.251831 Set Vref, RX VrefLevel [Byte0]: 46
2811 10:05:40.254760 [Byte1]: 46
2812 10:05:40.254858
2813 10:05:40.258453 Set Vref, RX VrefLevel [Byte0]: 47
2814 10:05:40.261493 [Byte1]: 47
2815 10:05:40.261596
2816 10:05:40.265122 Set Vref, RX VrefLevel [Byte0]: 48
2817 10:05:40.268216 [Byte1]: 48
2818 10:05:40.272425
2819 10:05:40.272521 Set Vref, RX VrefLevel [Byte0]: 49
2820 10:05:40.275480 [Byte1]: 49
2821 10:05:40.280262
2822 10:05:40.280367 Set Vref, RX VrefLevel [Byte0]: 50
2823 10:05:40.283233 [Byte1]: 50
2824 10:05:40.287803
2825 10:05:40.287877 Set Vref, RX VrefLevel [Byte0]: 51
2826 10:05:40.291423 [Byte1]: 51
2827 10:05:40.295836
2828 10:05:40.295937 Set Vref, RX VrefLevel [Byte0]: 52
2829 10:05:40.299430 [Byte1]: 52
2830 10:05:40.304118
2831 10:05:40.304221 Set Vref, RX VrefLevel [Byte0]: 53
2832 10:05:40.307135 [Byte1]: 53
2833 10:05:40.311766
2834 10:05:40.311862 Set Vref, RX VrefLevel [Byte0]: 54
2835 10:05:40.315424 [Byte1]: 54
2836 10:05:40.319772
2837 10:05:40.319841 Set Vref, RX VrefLevel [Byte0]: 55
2838 10:05:40.323120 [Byte1]: 55
2839 10:05:40.327960
2840 10:05:40.328057 Set Vref, RX VrefLevel [Byte0]: 56
2841 10:05:40.330738 [Byte1]: 56
2842 10:05:40.335922
2843 10:05:40.336007 Set Vref, RX VrefLevel [Byte0]: 57
2844 10:05:40.338786 [Byte1]: 57
2845 10:05:40.343385
2846 10:05:40.343478 Set Vref, RX VrefLevel [Byte0]: 58
2847 10:05:40.346563 [Byte1]: 58
2848 10:05:40.351186
2849 10:05:40.351292 Set Vref, RX VrefLevel [Byte0]: 59
2850 10:05:40.354724 [Byte1]: 59
2851 10:05:40.359025
2852 10:05:40.359128 Set Vref, RX VrefLevel [Byte0]: 60
2853 10:05:40.362699 [Byte1]: 60
2854 10:05:40.367365
2855 10:05:40.367445 Set Vref, RX VrefLevel [Byte0]: 61
2856 10:05:40.370402 [Byte1]: 61
2857 10:05:40.375189
2858 10:05:40.375287 Set Vref, RX VrefLevel [Byte0]: 62
2859 10:05:40.378253 [Byte1]: 62
2860 10:05:40.383132
2861 10:05:40.383230 Set Vref, RX VrefLevel [Byte0]: 63
2862 10:05:40.386796 [Byte1]: 63
2863 10:05:40.390966
2864 10:05:40.391062 Set Vref, RX VrefLevel [Byte0]: 64
2865 10:05:40.394483 [Byte1]: 64
2866 10:05:40.399055
2867 10:05:40.399154 Set Vref, RX VrefLevel [Byte0]: 65
2868 10:05:40.401998 [Byte1]: 65
2869 10:05:40.406598
2870 10:05:40.406670 Set Vref, RX VrefLevel [Byte0]: 66
2871 10:05:40.410092 [Byte1]: 66
2872 10:05:40.414970
2873 10:05:40.415067 Set Vref, RX VrefLevel [Byte0]: 67
2874 10:05:40.417988 [Byte1]: 67
2875 10:05:40.422786
2876 10:05:40.422879 Set Vref, RX VrefLevel [Byte0]: 68
2877 10:05:40.425699 [Byte1]: 68
2878 10:05:40.430932
2879 10:05:40.431027 Set Vref, RX VrefLevel [Byte0]: 69
2880 10:05:40.433802 [Byte1]: 69
2881 10:05:40.438434
2882 10:05:40.438504 Final RX Vref Byte 0 = 54 to rank0
2883 10:05:40.441834 Final RX Vref Byte 1 = 51 to rank0
2884 10:05:40.445285 Final RX Vref Byte 0 = 54 to rank1
2885 10:05:40.448667 Final RX Vref Byte 1 = 51 to rank1==
2886 10:05:40.452122 Dram Type= 6, Freq= 0, CH_0, rank 0
2887 10:05:40.458480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 10:05:40.458551 ==
2889 10:05:40.458614 DQS Delay:
2890 10:05:40.458671 DQS0 = 0, DQS1 = 0
2891 10:05:40.462098 DQM Delay:
2892 10:05:40.462191 DQM0 = 115, DQM1 = 105
2893 10:05:40.465141 DQ Delay:
2894 10:05:40.468756 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2895 10:05:40.472184 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2896 10:05:40.475453 DQ8 =92, DQ9 =92, DQ10 =104, DQ11 =96
2897 10:05:40.478335 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2898 10:05:40.478437
2899 10:05:40.478501
2900 10:05:40.485003 [DQSOSCAuto] RK0, (LSB)MR18= 0xffee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2901 10:05:40.488587 CH0 RK0: MR19=303, MR18=FFEE
2902 10:05:40.495328 CH0_RK0: MR19=0x303, MR18=0xFFEE, DQSOSC=410, MR23=63, INC=39, DEC=26
2903 10:05:40.495435
2904 10:05:40.498715 ----->DramcWriteLeveling(PI) begin...
2905 10:05:40.498819 ==
2906 10:05:40.501568 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 10:05:40.505271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 10:05:40.508655 ==
2909 10:05:40.508753 Write leveling (Byte 0): 34 => 34
2910 10:05:40.511640 Write leveling (Byte 1): 29 => 29
2911 10:05:40.515342 DramcWriteLeveling(PI) end<-----
2912 10:05:40.515485
2913 10:05:40.515583 ==
2914 10:05:40.518241 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 10:05:40.524861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 10:05:40.524966 ==
2917 10:05:40.525067 [Gating] SW mode calibration
2918 10:05:40.535400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2919 10:05:40.538362 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2920 10:05:40.541667 0 15 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2921 10:05:40.548364 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
2922 10:05:40.551472 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 10:05:40.555111 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 10:05:40.561974 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 10:05:40.565216 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 10:05:40.568126 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 10:05:40.575326 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 1)
2928 10:05:40.578443 1 0 0 | B1->B0 | 2c2c 2828 | 0 0 | (0 0) (0 0)
2929 10:05:40.581974 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2930 10:05:40.588339 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 10:05:40.591838 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 10:05:40.594838 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 10:05:40.601950 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 10:05:40.604968 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2935 10:05:40.608182 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (1 1)
2936 10:05:40.615005 1 1 0 | B1->B0 | 2b2a 3e3e | 1 0 | (1 1) (0 0)
2937 10:05:40.618552 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 10:05:40.621470 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 10:05:40.628232 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 10:05:40.631866 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 10:05:40.635071 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 10:05:40.638492 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2943 10:05:40.644939 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2944 10:05:40.648518 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2945 10:05:40.651830 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2946 10:05:40.658628 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 10:05:40.661456 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 10:05:40.664868 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 10:05:40.671568 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 10:05:40.675237 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 10:05:40.678114 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 10:05:40.685574 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 10:05:40.688453 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 10:05:40.691607 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 10:05:40.698291 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 10:05:40.701791 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 10:05:40.705326 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 10:05:40.711766 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 10:05:40.714730 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2960 10:05:40.718302 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2961 10:05:40.722037 Total UI for P1: 0, mck2ui 16
2962 10:05:40.725167 best dqsien dly found for B0: ( 1, 3, 28)
2963 10:05:40.728153 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 10:05:40.731674 Total UI for P1: 0, mck2ui 16
2965 10:05:40.735399 best dqsien dly found for B1: ( 1, 4, 0)
2966 10:05:40.738291 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2967 10:05:40.741810 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2968 10:05:40.745373
2969 10:05:40.748383 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2970 10:05:40.751820 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2971 10:05:40.755144 [Gating] SW calibration Done
2972 10:05:40.755224 ==
2973 10:05:40.758537 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 10:05:40.761980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 10:05:40.762063 ==
2976 10:05:40.762129 RX Vref Scan: 0
2977 10:05:40.762199
2978 10:05:40.765110 RX Vref 0 -> 0, step: 1
2979 10:05:40.765188
2980 10:05:40.768444 RX Delay -40 -> 252, step: 8
2981 10:05:40.771722 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2982 10:05:40.775097 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2983 10:05:40.781842 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2984 10:05:40.785291 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2985 10:05:40.788218 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2986 10:05:40.792095 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2987 10:05:40.794934 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2988 10:05:40.801651 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2989 10:05:40.805233 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2990 10:05:40.808168 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2991 10:05:40.811614 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2992 10:05:40.815468 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2993 10:05:40.818289 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2994 10:05:40.825069 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2995 10:05:40.828271 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2996 10:05:40.831318 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2997 10:05:40.831440 ==
2998 10:05:40.835306 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 10:05:40.838540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 10:05:40.841480 ==
3001 10:05:40.841557 DQS Delay:
3002 10:05:40.841621 DQS0 = 0, DQS1 = 0
3003 10:05:40.844907 DQM Delay:
3004 10:05:40.844980 DQM0 = 115, DQM1 = 106
3005 10:05:40.848217 DQ Delay:
3006 10:05:40.851769 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
3007 10:05:40.854892 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
3008 10:05:40.858055 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3009 10:05:40.861470 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3010 10:05:40.861540
3011 10:05:40.861639
3012 10:05:40.861702 ==
3013 10:05:40.865068 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 10:05:40.868539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 10:05:40.868611 ==
3016 10:05:40.868672
3017 10:05:40.868729
3018 10:05:40.871635 TX Vref Scan disable
3019 10:05:40.874914 == TX Byte 0 ==
3020 10:05:40.878164 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3021 10:05:40.881340 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3022 10:05:40.884855 == TX Byte 1 ==
3023 10:05:40.888507 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3024 10:05:40.891524 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3025 10:05:40.891607 ==
3026 10:05:40.895218 Dram Type= 6, Freq= 0, CH_0, rank 1
3027 10:05:40.898332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3028 10:05:40.901855 ==
3029 10:05:40.911907 TX Vref=22, minBit 1, minWin=25, winSum=422
3030 10:05:40.915495 TX Vref=24, minBit 1, minWin=25, winSum=428
3031 10:05:40.918802 TX Vref=26, minBit 2, minWin=26, winSum=431
3032 10:05:40.922155 TX Vref=28, minBit 3, minWin=26, winSum=437
3033 10:05:40.925108 TX Vref=30, minBit 4, minWin=26, winSum=438
3034 10:05:40.931755 TX Vref=32, minBit 13, minWin=26, winSum=436
3035 10:05:40.935408 [TxChooseVref] Worse bit 4, Min win 26, Win sum 438, Final Vref 30
3036 10:05:40.935490
3037 10:05:40.938484 Final TX Range 1 Vref 30
3038 10:05:40.938566
3039 10:05:40.938629 ==
3040 10:05:40.941650 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 10:05:40.945184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 10:05:40.948619 ==
3043 10:05:40.948699
3044 10:05:40.948762
3045 10:05:40.948820 TX Vref Scan disable
3046 10:05:40.952069 == TX Byte 0 ==
3047 10:05:40.955173 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3048 10:05:40.961999 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3049 10:05:40.962081 == TX Byte 1 ==
3050 10:05:40.965418 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3051 10:05:40.971933 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3052 10:05:40.972016
3053 10:05:40.972080 [DATLAT]
3054 10:05:40.972140 Freq=1200, CH0 RK1
3055 10:05:40.972251
3056 10:05:40.975408 DATLAT Default: 0xd
3057 10:05:40.975514 0, 0xFFFF, sum = 0
3058 10:05:40.978348 1, 0xFFFF, sum = 0
3059 10:05:40.981630 2, 0xFFFF, sum = 0
3060 10:05:40.981736 3, 0xFFFF, sum = 0
3061 10:05:40.985230 4, 0xFFFF, sum = 0
3062 10:05:40.985332 5, 0xFFFF, sum = 0
3063 10:05:40.988227 6, 0xFFFF, sum = 0
3064 10:05:40.988328 7, 0xFFFF, sum = 0
3065 10:05:40.991778 8, 0xFFFF, sum = 0
3066 10:05:40.991876 9, 0xFFFF, sum = 0
3067 10:05:40.995487 10, 0xFFFF, sum = 0
3068 10:05:40.995586 11, 0xFFFF, sum = 0
3069 10:05:40.998423 12, 0x0, sum = 1
3070 10:05:40.998531 13, 0x0, sum = 2
3071 10:05:41.002056 14, 0x0, sum = 3
3072 10:05:41.002129 15, 0x0, sum = 4
3073 10:05:41.002220 best_step = 13
3074 10:05:41.005177
3075 10:05:41.005247 ==
3076 10:05:41.008191 Dram Type= 6, Freq= 0, CH_0, rank 1
3077 10:05:41.011810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 10:05:41.011909 ==
3079 10:05:41.011997 RX Vref Scan: 0
3080 10:05:41.012085
3081 10:05:41.015470 RX Vref 0 -> 0, step: 1
3082 10:05:41.015546
3083 10:05:41.018277 RX Delay -21 -> 252, step: 4
3084 10:05:41.021755 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3085 10:05:41.028343 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3086 10:05:41.032000 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3087 10:05:41.035322 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3088 10:05:41.038211 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3089 10:05:41.041707 iDelay=195, Bit 5, Center 106 (39 ~ 174) 136
3090 10:05:41.048424 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3091 10:05:41.052260 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3092 10:05:41.054797 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3093 10:05:41.058416 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3094 10:05:41.061379 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3095 10:05:41.065125 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3096 10:05:41.071400 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3097 10:05:41.074878 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3098 10:05:41.078575 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3099 10:05:41.081726 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3100 10:05:41.081808 ==
3101 10:05:41.084658 Dram Type= 6, Freq= 0, CH_0, rank 1
3102 10:05:41.091972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 10:05:41.092055 ==
3104 10:05:41.092120 DQS Delay:
3105 10:05:41.094803 DQS0 = 0, DQS1 = 0
3106 10:05:41.094884 DQM Delay:
3107 10:05:41.098613 DQM0 = 114, DQM1 = 104
3108 10:05:41.098694 DQ Delay:
3109 10:05:41.101556 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3110 10:05:41.105168 DQ4 =112, DQ5 =106, DQ6 =120, DQ7 =122
3111 10:05:41.108190 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3112 10:05:41.111321 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3113 10:05:41.111449
3114 10:05:41.111518
3115 10:05:41.121315 [DQSOSCAuto] RK1, (LSB)MR18= 0xfff0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
3116 10:05:41.121394 CH0 RK1: MR19=303, MR18=FFF0
3117 10:05:41.128273 CH0_RK1: MR19=0x303, MR18=0xFFF0, DQSOSC=410, MR23=63, INC=39, DEC=26
3118 10:05:41.132095 [RxdqsGatingPostProcess] freq 1200
3119 10:05:41.138280 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3120 10:05:41.141311 best DQS0 dly(2T, 0.5T) = (0, 11)
3121 10:05:41.144745 best DQS1 dly(2T, 0.5T) = (0, 11)
3122 10:05:41.148290 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3123 10:05:41.151477 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3124 10:05:41.151552 best DQS0 dly(2T, 0.5T) = (0, 11)
3125 10:05:41.155010 best DQS1 dly(2T, 0.5T) = (0, 12)
3126 10:05:41.158515 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3127 10:05:41.161603 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3128 10:05:41.165073 Pre-setting of DQS Precalculation
3129 10:05:41.171755 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3130 10:05:41.171826 ==
3131 10:05:41.175195 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 10:05:41.178637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 10:05:41.178718 ==
3134 10:05:41.184906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3135 10:05:41.188416 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3136 10:05:41.198492 [CA 0] Center 38 (8~68) winsize 61
3137 10:05:41.201424 [CA 1] Center 38 (8~68) winsize 61
3138 10:05:41.204626 [CA 2] Center 35 (5~65) winsize 61
3139 10:05:41.208296 [CA 3] Center 34 (4~65) winsize 62
3140 10:05:41.211754 [CA 4] Center 35 (5~65) winsize 61
3141 10:05:41.214865 [CA 5] Center 33 (3~64) winsize 62
3142 10:05:41.214938
3143 10:05:41.218348 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3144 10:05:41.218422
3145 10:05:41.221329 [CATrainingPosCal] consider 1 rank data
3146 10:05:41.224994 u2DelayCellTimex100 = 270/100 ps
3147 10:05:41.228373 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3148 10:05:41.231924 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3149 10:05:41.234677 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3150 10:05:41.241629 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3151 10:05:41.244995 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3152 10:05:41.248298 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3153 10:05:41.248382
3154 10:05:41.252010 CA PerBit enable=1, Macro0, CA PI delay=33
3155 10:05:41.252079
3156 10:05:41.255089 [CBTSetCACLKResult] CA Dly = 33
3157 10:05:41.255161 CS Dly: 6 (0~37)
3158 10:05:41.255222 ==
3159 10:05:41.258219 Dram Type= 6, Freq= 0, CH_1, rank 1
3160 10:05:41.264739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3161 10:05:41.264821 ==
3162 10:05:41.268212 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3163 10:05:41.274731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3164 10:05:41.283501 [CA 0] Center 38 (8~68) winsize 61
3165 10:05:41.287392 [CA 1] Center 38 (8~68) winsize 61
3166 10:05:41.290078 [CA 2] Center 34 (4~65) winsize 62
3167 10:05:41.293481 [CA 3] Center 34 (4~65) winsize 62
3168 10:05:41.297082 [CA 4] Center 34 (4~65) winsize 62
3169 10:05:41.300448 [CA 5] Center 33 (3~63) winsize 61
3170 10:05:41.300527
3171 10:05:41.303800 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3172 10:05:41.303881
3173 10:05:41.307288 [CATrainingPosCal] consider 2 rank data
3174 10:05:41.310342 u2DelayCellTimex100 = 270/100 ps
3175 10:05:41.313510 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3176 10:05:41.316982 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3177 10:05:41.323678 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3178 10:05:41.332551 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3179 10:05:41.332668 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3180 10:05:41.333861 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3181 10:05:41.333943
3182 10:05:41.337715 CA PerBit enable=1, Macro0, CA PI delay=33
3183 10:05:41.337797
3184 10:05:41.340260 [CBTSetCACLKResult] CA Dly = 33
3185 10:05:41.340343 CS Dly: 7 (0~40)
3186 10:05:41.340408
3187 10:05:41.343977 ----->DramcWriteLeveling(PI) begin...
3188 10:05:41.346989 ==
3189 10:05:41.347074 Dram Type= 6, Freq= 0, CH_1, rank 0
3190 10:05:41.353445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3191 10:05:41.353537 ==
3192 10:05:41.356959 Write leveling (Byte 0): 25 => 25
3193 10:05:41.360498 Write leveling (Byte 1): 29 => 29
3194 10:05:41.364161 DramcWriteLeveling(PI) end<-----
3195 10:05:41.364267
3196 10:05:41.364363 ==
3197 10:05:41.366852 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 10:05:41.370866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 10:05:41.370969 ==
3200 10:05:41.373712 [Gating] SW mode calibration
3201 10:05:41.380450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3202 10:05:41.383405 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3203 10:05:41.390580 0 15 0 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
3204 10:05:41.393736 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3205 10:05:41.397316 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 10:05:41.403728 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 10:05:41.407284 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 10:05:41.410222 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3209 10:05:41.416922 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 10:05:41.420489 0 15 28 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 0)
3211 10:05:41.423580 1 0 0 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 0)
3212 10:05:41.430298 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 10:05:41.433596 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 10:05:41.436830 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 10:05:41.443487 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 10:05:41.447025 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 10:05:41.450588 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 10:05:41.457094 1 0 28 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
3219 10:05:41.460047 1 1 0 | B1->B0 | 4343 3434 | 0 0 | (0 0) (0 0)
3220 10:05:41.463802 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 10:05:41.470431 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 10:05:41.473564 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 10:05:41.476657 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 10:05:41.479940 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 10:05:41.487011 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 10:05:41.489951 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3227 10:05:41.493508 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 10:05:41.500300 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 10:05:41.503238 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 10:05:41.506769 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 10:05:41.513710 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 10:05:41.516766 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 10:05:41.520202 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 10:05:41.526945 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 10:05:41.530043 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 10:05:41.533625 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 10:05:41.540170 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 10:05:41.543430 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 10:05:41.547294 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 10:05:41.553682 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 10:05:41.557157 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 10:05:41.560030 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3243 10:05:41.566770 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3244 10:05:41.570214 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3245 10:05:41.573727 Total UI for P1: 0, mck2ui 16
3246 10:05:41.576627 best dqsien dly found for B0: ( 1, 3, 30)
3247 10:05:41.580251 Total UI for P1: 0, mck2ui 16
3248 10:05:41.583907 best dqsien dly found for B1: ( 1, 4, 0)
3249 10:05:41.586708 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3250 10:05:41.590326 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3251 10:05:41.590409
3252 10:05:41.593882 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3253 10:05:41.596774 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3254 10:05:41.600393 [Gating] SW calibration Done
3255 10:05:41.600474 ==
3256 10:05:41.603366 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 10:05:41.606938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 10:05:41.607021 ==
3259 10:05:41.610087 RX Vref Scan: 0
3260 10:05:41.610169
3261 10:05:41.610234 RX Vref 0 -> 0, step: 1
3262 10:05:41.610294
3263 10:05:41.613472 RX Delay -40 -> 252, step: 8
3264 10:05:41.617077 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3265 10:05:41.623528 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3266 10:05:41.626709 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3267 10:05:41.630155 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3268 10:05:41.633770 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3269 10:05:41.636756 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3270 10:05:41.643632 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3271 10:05:41.646908 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3272 10:05:41.650398 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3273 10:05:41.653407 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3274 10:05:41.656759 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3275 10:05:41.663714 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3276 10:05:41.667131 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3277 10:05:41.670697 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3278 10:05:41.673586 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3279 10:05:41.677219 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3280 10:05:41.677301 ==
3281 10:05:41.680841 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 10:05:41.687288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 10:05:41.687424 ==
3284 10:05:41.687490 DQS Delay:
3285 10:05:41.690644 DQS0 = 0, DQS1 = 0
3286 10:05:41.690726 DQM Delay:
3287 10:05:41.693699 DQM0 = 115, DQM1 = 108
3288 10:05:41.693781 DQ Delay:
3289 10:05:41.697118 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3290 10:05:41.700714 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =111
3291 10:05:41.704477 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3292 10:05:41.707271 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3293 10:05:41.707411
3294 10:05:41.707498
3295 10:05:41.707577 ==
3296 10:05:41.710515 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 10:05:41.714096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 10:05:41.717090 ==
3299 10:05:41.717201
3300 10:05:41.717320
3301 10:05:41.717472 TX Vref Scan disable
3302 10:05:41.720629 == TX Byte 0 ==
3303 10:05:41.724184 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3304 10:05:41.727090 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3305 10:05:41.730727 == TX Byte 1 ==
3306 10:05:41.733942 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3307 10:05:41.737474 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3308 10:05:41.737562 ==
3309 10:05:41.740543 Dram Type= 6, Freq= 0, CH_1, rank 0
3310 10:05:41.747557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3311 10:05:41.747639 ==
3312 10:05:41.758041 TX Vref=22, minBit 1, minWin=24, winSum=409
3313 10:05:41.761544 TX Vref=24, minBit 1, minWin=25, winSum=415
3314 10:05:41.765056 TX Vref=26, minBit 1, minWin=26, winSum=422
3315 10:05:41.767868 TX Vref=28, minBit 0, minWin=26, winSum=425
3316 10:05:41.771473 TX Vref=30, minBit 0, minWin=26, winSum=429
3317 10:05:41.777967 TX Vref=32, minBit 15, minWin=25, winSum=424
3318 10:05:41.787360 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 30
3319 10:05:41.787522
3320 10:05:41.787618 Final TX Range 1 Vref 30
3321 10:05:41.787705
3322 10:05:41.787775 ==
3323 10:05:41.788513 Dram Type= 6, Freq= 0, CH_1, rank 0
3324 10:05:41.791401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3325 10:05:41.791483 ==
3326 10:05:41.794770
3327 10:05:41.794891
3328 10:05:41.795042 TX Vref Scan disable
3329 10:05:41.798271 == TX Byte 0 ==
3330 10:05:41.801612 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3331 10:05:41.804670 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3332 10:05:41.808146 == TX Byte 1 ==
3333 10:05:41.811175 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3334 10:05:41.814649 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3335 10:05:41.818254
3336 10:05:41.818377 [DATLAT]
3337 10:05:41.818501 Freq=1200, CH1 RK0
3338 10:05:41.818619
3339 10:05:41.821388 DATLAT Default: 0xd
3340 10:05:41.821469 0, 0xFFFF, sum = 0
3341 10:05:41.824822 1, 0xFFFF, sum = 0
3342 10:05:41.824904 2, 0xFFFF, sum = 0
3343 10:05:41.827664 3, 0xFFFF, sum = 0
3344 10:05:41.831337 4, 0xFFFF, sum = 0
3345 10:05:41.831442 5, 0xFFFF, sum = 0
3346 10:05:41.834465 6, 0xFFFF, sum = 0
3347 10:05:41.834555 7, 0xFFFF, sum = 0
3348 10:05:41.838115 8, 0xFFFF, sum = 0
3349 10:05:41.838197 9, 0xFFFF, sum = 0
3350 10:05:41.841042 10, 0xFFFF, sum = 0
3351 10:05:41.841123 11, 0xFFFF, sum = 0
3352 10:05:41.844598 12, 0x0, sum = 1
3353 10:05:41.844680 13, 0x0, sum = 2
3354 10:05:41.847714 14, 0x0, sum = 3
3355 10:05:41.847803 15, 0x0, sum = 4
3356 10:05:41.847867 best_step = 13
3357 10:05:41.851066
3358 10:05:41.851146 ==
3359 10:05:41.854130 Dram Type= 6, Freq= 0, CH_1, rank 0
3360 10:05:41.857922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3361 10:05:41.858019 ==
3362 10:05:41.858082 RX Vref Scan: 1
3363 10:05:41.858140
3364 10:05:41.861295 Set Vref Range= 32 -> 127
3365 10:05:41.861383
3366 10:05:41.864716 RX Vref 32 -> 127, step: 1
3367 10:05:41.864795
3368 10:05:41.867804 RX Delay -21 -> 252, step: 4
3369 10:05:41.867883
3370 10:05:41.870950 Set Vref, RX VrefLevel [Byte0]: 32
3371 10:05:41.874397 [Byte1]: 32
3372 10:05:41.874475
3373 10:05:41.877804 Set Vref, RX VrefLevel [Byte0]: 33
3374 10:05:41.881076 [Byte1]: 33
3375 10:05:41.884819
3376 10:05:41.884910 Set Vref, RX VrefLevel [Byte0]: 34
3377 10:05:41.887593 [Byte1]: 34
3378 10:05:41.892233
3379 10:05:41.892312 Set Vref, RX VrefLevel [Byte0]: 35
3380 10:05:41.895870 [Byte1]: 35
3381 10:05:41.900375
3382 10:05:41.900454 Set Vref, RX VrefLevel [Byte0]: 36
3383 10:05:41.903604 [Byte1]: 36
3384 10:05:41.908231
3385 10:05:41.908326 Set Vref, RX VrefLevel [Byte0]: 37
3386 10:05:41.911167 [Byte1]: 37
3387 10:05:41.916091
3388 10:05:41.916187 Set Vref, RX VrefLevel [Byte0]: 38
3389 10:05:41.919030 [Byte1]: 38
3390 10:05:41.924147
3391 10:05:41.924272 Set Vref, RX VrefLevel [Byte0]: 39
3392 10:05:41.927488 [Byte1]: 39
3393 10:05:41.932093
3394 10:05:41.932171 Set Vref, RX VrefLevel [Byte0]: 40
3395 10:05:41.935023 [Byte1]: 40
3396 10:05:41.940010
3397 10:05:41.940088 Set Vref, RX VrefLevel [Byte0]: 41
3398 10:05:41.942775 [Byte1]: 41
3399 10:05:41.947724
3400 10:05:41.947803 Set Vref, RX VrefLevel [Byte0]: 42
3401 10:05:41.951278 [Byte1]: 42
3402 10:05:41.955507
3403 10:05:41.955586 Set Vref, RX VrefLevel [Byte0]: 43
3404 10:05:41.959220 [Byte1]: 43
3405 10:05:41.963612
3406 10:05:41.963690 Set Vref, RX VrefLevel [Byte0]: 44
3407 10:05:41.967206 [Byte1]: 44
3408 10:05:41.971310
3409 10:05:41.971412 Set Vref, RX VrefLevel [Byte0]: 45
3410 10:05:41.974955 [Byte1]: 45
3411 10:05:41.979096
3412 10:05:41.979213 Set Vref, RX VrefLevel [Byte0]: 46
3413 10:05:41.982493 [Byte1]: 46
3414 10:05:41.987605
3415 10:05:41.987685 Set Vref, RX VrefLevel [Byte0]: 47
3416 10:05:41.990957 [Byte1]: 47
3417 10:05:41.994923
3418 10:05:41.995002 Set Vref, RX VrefLevel [Byte0]: 48
3419 10:05:41.998554 [Byte1]: 48
3420 10:05:42.003269
3421 10:05:42.003356 Set Vref, RX VrefLevel [Byte0]: 49
3422 10:05:42.006506 [Byte1]: 49
3423 10:05:42.011069
3424 10:05:42.011149 Set Vref, RX VrefLevel [Byte0]: 50
3425 10:05:42.014543 [Byte1]: 50
3426 10:05:42.018855
3427 10:05:42.018936 Set Vref, RX VrefLevel [Byte0]: 51
3428 10:05:42.022592 [Byte1]: 51
3429 10:05:42.026870
3430 10:05:42.026951 Set Vref, RX VrefLevel [Byte0]: 52
3431 10:05:42.030284 [Byte1]: 52
3432 10:05:42.035024
3433 10:05:42.035155 Set Vref, RX VrefLevel [Byte0]: 53
3434 10:05:42.038010 [Byte1]: 53
3435 10:05:42.042842
3436 10:05:42.042923 Set Vref, RX VrefLevel [Byte0]: 54
3437 10:05:42.045812 [Byte1]: 54
3438 10:05:42.050589
3439 10:05:42.050700 Set Vref, RX VrefLevel [Byte0]: 55
3440 10:05:42.054302 [Byte1]: 55
3441 10:05:42.058592
3442 10:05:42.058682 Set Vref, RX VrefLevel [Byte0]: 56
3443 10:05:42.062013 [Byte1]: 56
3444 10:05:42.066202
3445 10:05:42.066303 Set Vref, RX VrefLevel [Byte0]: 57
3446 10:05:42.070037 [Byte1]: 57
3447 10:05:42.074375
3448 10:05:42.074473 Set Vref, RX VrefLevel [Byte0]: 58
3449 10:05:42.077861 [Byte1]: 58
3450 10:05:42.082070
3451 10:05:42.082156 Set Vref, RX VrefLevel [Byte0]: 59
3452 10:05:42.089406 [Byte1]: 59
3453 10:05:42.090343
3454 10:05:42.090418 Set Vref, RX VrefLevel [Byte0]: 60
3455 10:05:42.093367 [Byte1]: 60
3456 10:05:42.098174
3457 10:05:42.098295 Set Vref, RX VrefLevel [Byte0]: 61
3458 10:05:42.101686 [Byte1]: 61
3459 10:05:42.106420
3460 10:05:42.106529 Set Vref, RX VrefLevel [Byte0]: 62
3461 10:05:42.109300 [Byte1]: 62
3462 10:05:42.114419
3463 10:05:42.114538 Set Vref, RX VrefLevel [Byte0]: 63
3464 10:05:42.117429 [Byte1]: 63
3465 10:05:42.122320
3466 10:05:42.122421 Set Vref, RX VrefLevel [Byte0]: 64
3467 10:05:42.125105 [Byte1]: 64
3468 10:05:42.129637
3469 10:05:42.129740 Set Vref, RX VrefLevel [Byte0]: 65
3470 10:05:42.133132 [Byte1]: 65
3471 10:05:42.137652
3472 10:05:42.137757 Set Vref, RX VrefLevel [Byte0]: 66
3473 10:05:42.141244 [Byte1]: 66
3474 10:05:42.145952
3475 10:05:42.146058 Set Vref, RX VrefLevel [Byte0]: 67
3476 10:05:42.149001 [Byte1]: 67
3477 10:05:42.153733
3478 10:05:42.153835 Set Vref, RX VrefLevel [Byte0]: 68
3479 10:05:42.157458 [Byte1]: 68
3480 10:05:42.161481
3481 10:05:42.161583 Set Vref, RX VrefLevel [Byte0]: 69
3482 10:05:42.164860 [Byte1]: 69
3483 10:05:42.169349
3484 10:05:42.169450 Set Vref, RX VrefLevel [Byte0]: 70
3485 10:05:42.176100 [Byte1]: 70
3486 10:05:42.176217
3487 10:05:42.179003 Set Vref, RX VrefLevel [Byte0]: 71
3488 10:05:42.182662 [Byte1]: 71
3489 10:05:42.182765
3490 10:05:42.186429 Set Vref, RX VrefLevel [Byte0]: 72
3491 10:05:42.188858 [Byte1]: 72
3492 10:05:42.193690
3493 10:05:42.193798 Final RX Vref Byte 0 = 60 to rank0
3494 10:05:42.196752 Final RX Vref Byte 1 = 51 to rank0
3495 10:05:42.200009 Final RX Vref Byte 0 = 60 to rank1
3496 10:05:42.203465 Final RX Vref Byte 1 = 51 to rank1==
3497 10:05:42.206393 Dram Type= 6, Freq= 0, CH_1, rank 0
3498 10:05:42.209906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 10:05:42.213304 ==
3500 10:05:42.213404 DQS Delay:
3501 10:05:42.213494 DQS0 = 0, DQS1 = 0
3502 10:05:42.216738 DQM Delay:
3503 10:05:42.216852 DQM0 = 116, DQM1 = 109
3504 10:05:42.220150 DQ Delay:
3505 10:05:42.223172 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =116
3506 10:05:42.226921 DQ4 =116, DQ5 =124, DQ6 =126, DQ7 =114
3507 10:05:42.230053 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3508 10:05:42.233649 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3509 10:05:42.233755
3510 10:05:42.233847
3511 10:05:42.240174 [DQSOSCAuto] RK0, (LSB)MR18= 0xfce1, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3512 10:05:42.243673 CH1 RK0: MR19=303, MR18=FCE1
3513 10:05:42.250440 CH1_RK0: MR19=0x303, MR18=0xFCE1, DQSOSC=411, MR23=63, INC=38, DEC=25
3514 10:05:42.250543
3515 10:05:42.253289 ----->DramcWriteLeveling(PI) begin...
3516 10:05:42.253389 ==
3517 10:05:42.256888 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 10:05:42.260667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 10:05:42.260765 ==
3520 10:05:42.263537 Write leveling (Byte 0): 26 => 26
3521 10:05:42.267057 Write leveling (Byte 1): 27 => 27
3522 10:05:42.270133 DramcWriteLeveling(PI) end<-----
3523 10:05:42.270251
3524 10:05:42.270314 ==
3525 10:05:42.273759 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 10:05:42.276897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 10:05:42.280221 ==
3528 10:05:42.280312 [Gating] SW mode calibration
3529 10:05:42.290454 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3530 10:05:42.293452 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3531 10:05:42.296747 0 15 0 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
3532 10:05:42.303519 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3533 10:05:42.307051 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3534 10:05:42.310266 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3535 10:05:42.316697 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3536 10:05:42.320082 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3537 10:05:42.323578 0 15 24 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
3538 10:05:42.330009 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3539 10:05:42.333830 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3540 10:05:42.336699 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3541 10:05:42.343341 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3542 10:05:42.346493 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3543 10:05:42.350048 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3544 10:05:42.356709 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3545 10:05:42.360206 1 0 24 | B1->B0 | 2525 4141 | 0 0 | (0 0) (0 0)
3546 10:05:42.363181 1 0 28 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
3547 10:05:42.369812 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3548 10:05:42.372987 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 10:05:42.376547 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3550 10:05:42.382961 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3551 10:05:42.386321 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3552 10:05:42.389579 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3553 10:05:42.393211 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3554 10:05:42.399897 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3555 10:05:42.403509 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 10:05:42.406281 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 10:05:42.413176 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 10:05:42.416495 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 10:05:42.419802 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 10:05:42.426537 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 10:05:42.429938 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 10:05:42.432941 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 10:05:42.439689 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 10:05:42.443182 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 10:05:42.446269 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 10:05:42.452659 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 10:05:42.456357 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 10:05:42.459918 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3569 10:05:42.466423 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3570 10:05:42.469427 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3571 10:05:42.472931 Total UI for P1: 0, mck2ui 16
3572 10:05:42.476073 best dqsien dly found for B0: ( 1, 3, 22)
3573 10:05:42.479463 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3574 10:05:42.482498 Total UI for P1: 0, mck2ui 16
3575 10:05:42.486197 best dqsien dly found for B1: ( 1, 3, 28)
3576 10:05:42.489199 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3577 10:05:42.492755 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3578 10:05:42.492855
3579 10:05:42.499424 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3580 10:05:42.502430 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3581 10:05:42.502529 [Gating] SW calibration Done
3582 10:05:42.506011 ==
3583 10:05:42.509028 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 10:05:42.512569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 10:05:42.512652 ==
3586 10:05:42.512717 RX Vref Scan: 0
3587 10:05:42.512777
3588 10:05:42.515925 RX Vref 0 -> 0, step: 1
3589 10:05:42.516000
3590 10:05:42.519054 RX Delay -40 -> 252, step: 8
3591 10:05:42.522486 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3592 10:05:42.525313 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3593 10:05:42.532552 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3594 10:05:42.535905 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3595 10:05:42.538775 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3596 10:05:42.542419 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3597 10:05:42.545652 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3598 10:05:42.549284 iDelay=192, Bit 7, Center 111 (48 ~ 175) 128
3599 10:05:42.555464 iDelay=192, Bit 8, Center 103 (32 ~ 175) 144
3600 10:05:42.559134 iDelay=192, Bit 9, Center 99 (32 ~ 167) 136
3601 10:05:42.562182 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3602 10:05:42.565668 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3603 10:05:42.569289 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3604 10:05:42.575614 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3605 10:05:42.579188 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3606 10:05:42.582188 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3607 10:05:42.582280 ==
3608 10:05:42.585267 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 10:05:42.588956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 10:05:42.592269 ==
3611 10:05:42.592370 DQS Delay:
3612 10:05:42.592465 DQS0 = 0, DQS1 = 0
3613 10:05:42.595527 DQM Delay:
3614 10:05:42.595630 DQM0 = 113, DQM1 = 111
3615 10:05:42.598786 DQ Delay:
3616 10:05:42.602281 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =115
3617 10:05:42.605557 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =111
3618 10:05:42.608488 DQ8 =103, DQ9 =99, DQ10 =111, DQ11 =103
3619 10:05:42.611984 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3620 10:05:42.612097
3621 10:05:42.612203
3622 10:05:42.612294 ==
3623 10:05:42.615114 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 10:05:42.618685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 10:05:42.618785 ==
3626 10:05:42.618888
3627 10:05:42.622358
3628 10:05:42.622461 TX Vref Scan disable
3629 10:05:42.625135 == TX Byte 0 ==
3630 10:05:42.628609 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3631 10:05:42.631929 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3632 10:05:42.635233 == TX Byte 1 ==
3633 10:05:42.638518 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3634 10:05:42.642029 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3635 10:05:42.642143 ==
3636 10:05:42.645021 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 10:05:42.651702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 10:05:42.651821 ==
3639 10:05:42.662511 TX Vref=22, minBit 1, minWin=25, winSum=416
3640 10:05:42.665315 TX Vref=24, minBit 3, minWin=25, winSum=421
3641 10:05:42.668864 TX Vref=26, minBit 1, minWin=26, winSum=428
3642 10:05:42.672092 TX Vref=28, minBit 2, minWin=26, winSum=433
3643 10:05:42.675722 TX Vref=30, minBit 4, minWin=26, winSum=435
3644 10:05:42.682233 TX Vref=32, minBit 3, minWin=26, winSum=434
3645 10:05:42.685126 [TxChooseVref] Worse bit 4, Min win 26, Win sum 435, Final Vref 30
3646 10:05:42.685242
3647 10:05:42.688405 Final TX Range 1 Vref 30
3648 10:05:42.688519
3649 10:05:42.688611 ==
3650 10:05:42.691971 Dram Type= 6, Freq= 0, CH_1, rank 1
3651 10:05:42.695133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3652 10:05:42.698196 ==
3653 10:05:42.698307
3654 10:05:42.698398
3655 10:05:42.698498 TX Vref Scan disable
3656 10:05:42.701681 == TX Byte 0 ==
3657 10:05:42.704967 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3658 10:05:42.711655 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3659 10:05:42.711765 == TX Byte 1 ==
3660 10:05:42.715232 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3661 10:05:42.721510 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3662 10:05:42.721595
3663 10:05:42.721661 [DATLAT]
3664 10:05:42.721749 Freq=1200, CH1 RK1
3665 10:05:42.721811
3666 10:05:42.725086 DATLAT Default: 0xd
3667 10:05:42.725207 0, 0xFFFF, sum = 0
3668 10:05:42.728524 1, 0xFFFF, sum = 0
3669 10:05:42.731580 2, 0xFFFF, sum = 0
3670 10:05:42.731658 3, 0xFFFF, sum = 0
3671 10:05:42.734961 4, 0xFFFF, sum = 0
3672 10:05:42.735063 5, 0xFFFF, sum = 0
3673 10:05:42.738556 6, 0xFFFF, sum = 0
3674 10:05:42.738667 7, 0xFFFF, sum = 0
3675 10:05:42.741875 8, 0xFFFF, sum = 0
3676 10:05:42.741990 9, 0xFFFF, sum = 0
3677 10:05:42.744666 10, 0xFFFF, sum = 0
3678 10:05:42.744762 11, 0xFFFF, sum = 0
3679 10:05:42.748060 12, 0x0, sum = 1
3680 10:05:42.748145 13, 0x0, sum = 2
3681 10:05:42.751651 14, 0x0, sum = 3
3682 10:05:42.751727 15, 0x0, sum = 4
3683 10:05:42.754667 best_step = 13
3684 10:05:42.754750
3685 10:05:42.754812 ==
3686 10:05:42.758360 Dram Type= 6, Freq= 0, CH_1, rank 1
3687 10:05:42.761760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3688 10:05:42.761834 ==
3689 10:05:42.761895 RX Vref Scan: 0
3690 10:05:42.761954
3691 10:05:42.764782 RX Vref 0 -> 0, step: 1
3692 10:05:42.764865
3693 10:05:42.768196 RX Delay -13 -> 252, step: 4
3694 10:05:42.771701 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3695 10:05:42.778065 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3696 10:05:42.781223 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3697 10:05:42.784749 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3698 10:05:42.788243 iDelay=191, Bit 4, Center 116 (51 ~ 182) 132
3699 10:05:42.791221 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3700 10:05:42.797991 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3701 10:05:42.801536 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3702 10:05:42.804448 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3703 10:05:42.807861 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3704 10:05:42.811371 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3705 10:05:42.818122 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3706 10:05:42.821314 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3707 10:05:42.824745 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3708 10:05:42.827772 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3709 10:05:42.834288 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3710 10:05:42.834409 ==
3711 10:05:42.837542 Dram Type= 6, Freq= 0, CH_1, rank 1
3712 10:05:42.840891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3713 10:05:42.841007 ==
3714 10:05:42.841101 DQS Delay:
3715 10:05:42.844411 DQS0 = 0, DQS1 = 0
3716 10:05:42.844492 DQM Delay:
3717 10:05:42.847800 DQM0 = 114, DQM1 = 109
3718 10:05:42.847914 DQ Delay:
3719 10:05:42.851063 DQ0 =114, DQ1 =108, DQ2 =106, DQ3 =112
3720 10:05:42.854586 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =110
3721 10:05:42.857613 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3722 10:05:42.860655 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =118
3723 10:05:42.860759
3724 10:05:42.860851
3725 10:05:42.870834 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3726 10:05:42.874034 CH1 RK1: MR19=303, MR18=F7FE
3727 10:05:42.877683 CH1_RK1: MR19=0x303, MR18=0xF7FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3728 10:05:42.880686 [RxdqsGatingPostProcess] freq 1200
3729 10:05:42.887154 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3730 10:05:42.890666 best DQS0 dly(2T, 0.5T) = (0, 11)
3731 10:05:42.894283 best DQS1 dly(2T, 0.5T) = (0, 12)
3732 10:05:42.897404 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3733 10:05:42.900995 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3734 10:05:42.903996 best DQS0 dly(2T, 0.5T) = (0, 11)
3735 10:05:42.907435 best DQS1 dly(2T, 0.5T) = (0, 11)
3736 10:05:42.910804 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3737 10:05:42.914218 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3738 10:05:42.914313 Pre-setting of DQS Precalculation
3739 10:05:42.920895 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3740 10:05:42.927438 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3741 10:05:42.934201 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3742 10:05:42.934278
3743 10:05:42.934342
3744 10:05:42.937153 [Calibration Summary] 2400 Mbps
3745 10:05:42.940603 CH 0, Rank 0
3746 10:05:42.940677 SW Impedance : PASS
3747 10:05:42.944018 DUTY Scan : NO K
3748 10:05:42.946939 ZQ Calibration : PASS
3749 10:05:42.947016 Jitter Meter : NO K
3750 10:05:42.950360 CBT Training : PASS
3751 10:05:42.953725 Write leveling : PASS
3752 10:05:42.953828 RX DQS gating : PASS
3753 10:05:42.957016 RX DQ/DQS(RDDQC) : PASS
3754 10:05:42.960539 TX DQ/DQS : PASS
3755 10:05:42.960619 RX DATLAT : PASS
3756 10:05:42.963912 RX DQ/DQS(Engine): PASS
3757 10:05:42.966916 TX OE : NO K
3758 10:05:42.967027 All Pass.
3759 10:05:42.967130
3760 10:05:42.967221 CH 0, Rank 1
3761 10:05:42.970287 SW Impedance : PASS
3762 10:05:42.973474 DUTY Scan : NO K
3763 10:05:42.973559 ZQ Calibration : PASS
3764 10:05:42.977043 Jitter Meter : NO K
3765 10:05:42.977148 CBT Training : PASS
3766 10:05:42.980477 Write leveling : PASS
3767 10:05:42.984187 RX DQS gating : PASS
3768 10:05:42.984269 RX DQ/DQS(RDDQC) : PASS
3769 10:05:42.986942 TX DQ/DQS : PASS
3770 10:05:42.990475 RX DATLAT : PASS
3771 10:05:42.990577 RX DQ/DQS(Engine): PASS
3772 10:05:42.993934 TX OE : NO K
3773 10:05:42.994034 All Pass.
3774 10:05:42.994131
3775 10:05:42.996981 CH 1, Rank 0
3776 10:05:42.997070 SW Impedance : PASS
3777 10:05:43.000534 DUTY Scan : NO K
3778 10:05:43.003640 ZQ Calibration : PASS
3779 10:05:43.003725 Jitter Meter : NO K
3780 10:05:43.006695 CBT Training : PASS
3781 10:05:43.010162 Write leveling : PASS
3782 10:05:43.010271 RX DQS gating : PASS
3783 10:05:43.013645 RX DQ/DQS(RDDQC) : PASS
3784 10:05:43.016689 TX DQ/DQS : PASS
3785 10:05:43.016787 RX DATLAT : PASS
3786 10:05:43.020217 RX DQ/DQS(Engine): PASS
3787 10:05:43.023201 TX OE : NO K
3788 10:05:43.023299 All Pass.
3789 10:05:43.023405
3790 10:05:43.023493 CH 1, Rank 1
3791 10:05:43.026807 SW Impedance : PASS
3792 10:05:43.029832 DUTY Scan : NO K
3793 10:05:43.029938 ZQ Calibration : PASS
3794 10:05:43.033564 Jitter Meter : NO K
3795 10:05:43.033670 CBT Training : PASS
3796 10:05:43.036580 Write leveling : PASS
3797 10:05:43.040069 RX DQS gating : PASS
3798 10:05:43.040143 RX DQ/DQS(RDDQC) : PASS
3799 10:05:43.043734 TX DQ/DQS : PASS
3800 10:05:43.046663 RX DATLAT : PASS
3801 10:05:43.046749 RX DQ/DQS(Engine): PASS
3802 10:05:43.050059 TX OE : NO K
3803 10:05:43.050171 All Pass.
3804 10:05:43.050269
3805 10:05:43.053353 DramC Write-DBI off
3806 10:05:43.056792 PER_BANK_REFRESH: Hybrid Mode
3807 10:05:43.056896 TX_TRACKING: ON
3808 10:05:43.066988 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3809 10:05:43.069774 [FAST_K] Save calibration result to emmc
3810 10:05:43.073364 dramc_set_vcore_voltage set vcore to 650000
3811 10:05:43.076578 Read voltage for 600, 5
3812 10:05:43.076666 Vio18 = 0
3813 10:05:43.076732 Vcore = 650000
3814 10:05:43.079982 Vdram = 0
3815 10:05:43.080063 Vddq = 0
3816 10:05:43.080127 Vmddr = 0
3817 10:05:43.086582 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3818 10:05:43.090264 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3819 10:05:43.093312 MEM_TYPE=3, freq_sel=19
3820 10:05:43.096353 sv_algorithm_assistance_LP4_1600
3821 10:05:43.099901 ============ PULL DRAM RESETB DOWN ============
3822 10:05:43.103068 ========== PULL DRAM RESETB DOWN end =========
3823 10:05:43.109637 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3824 10:05:43.112753 ===================================
3825 10:05:43.116387 LPDDR4 DRAM CONFIGURATION
3826 10:05:43.119307 ===================================
3827 10:05:43.119447 EX_ROW_EN[0] = 0x0
3828 10:05:43.122657 EX_ROW_EN[1] = 0x0
3829 10:05:43.122740 LP4Y_EN = 0x0
3830 10:05:43.126585 WORK_FSP = 0x0
3831 10:05:43.126670 WL = 0x2
3832 10:05:43.129521 RL = 0x2
3833 10:05:43.129605 BL = 0x2
3834 10:05:43.132718 RPST = 0x0
3835 10:05:43.132802 RD_PRE = 0x0
3836 10:05:43.136208 WR_PRE = 0x1
3837 10:05:43.136290 WR_PST = 0x0
3838 10:05:43.139367 DBI_WR = 0x0
3839 10:05:43.139450 DBI_RD = 0x0
3840 10:05:43.143022 OTF = 0x1
3841 10:05:43.146376 ===================================
3842 10:05:43.149269 ===================================
3843 10:05:43.149353 ANA top config
3844 10:05:43.152929 ===================================
3845 10:05:43.156424 DLL_ASYNC_EN = 0
3846 10:05:43.159630 ALL_SLAVE_EN = 1
3847 10:05:43.163126 NEW_RANK_MODE = 1
3848 10:05:43.163211 DLL_IDLE_MODE = 1
3849 10:05:43.165993 LP45_APHY_COMB_EN = 1
3850 10:05:43.169272 TX_ODT_DIS = 1
3851 10:05:43.172613 NEW_8X_MODE = 1
3852 10:05:43.175987 ===================================
3853 10:05:43.179278 ===================================
3854 10:05:43.182598 data_rate = 1200
3855 10:05:43.182715 CKR = 1
3856 10:05:43.185933 DQ_P2S_RATIO = 8
3857 10:05:43.189460 ===================================
3858 10:05:43.192786 CA_P2S_RATIO = 8
3859 10:05:43.196146 DQ_CA_OPEN = 0
3860 10:05:43.199620 DQ_SEMI_OPEN = 0
3861 10:05:43.202625 CA_SEMI_OPEN = 0
3862 10:05:43.202736 CA_FULL_RATE = 0
3863 10:05:43.206227 DQ_CKDIV4_EN = 1
3864 10:05:43.209246 CA_CKDIV4_EN = 1
3865 10:05:43.212840 CA_PREDIV_EN = 0
3866 10:05:43.216051 PH8_DLY = 0
3867 10:05:43.219517 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3868 10:05:43.219629 DQ_AAMCK_DIV = 4
3869 10:05:43.222527 CA_AAMCK_DIV = 4
3870 10:05:43.225990 CA_ADMCK_DIV = 4
3871 10:05:43.229531 DQ_TRACK_CA_EN = 0
3872 10:05:43.232553 CA_PICK = 600
3873 10:05:43.236013 CA_MCKIO = 600
3874 10:05:43.239010 MCKIO_SEMI = 0
3875 10:05:43.239117 PLL_FREQ = 2288
3876 10:05:43.242591 DQ_UI_PI_RATIO = 32
3877 10:05:43.246027 CA_UI_PI_RATIO = 0
3878 10:05:43.248955 ===================================
3879 10:05:43.252509 ===================================
3880 10:05:43.256070 memory_type:LPDDR4
3881 10:05:43.256179 GP_NUM : 10
3882 10:05:43.259078 SRAM_EN : 1
3883 10:05:43.262569 MD32_EN : 0
3884 10:05:43.266011 ===================================
3885 10:05:43.266117 [ANA_INIT] >>>>>>>>>>>>>>
3886 10:05:43.269804 <<<<<< [CONFIGURE PHASE]: ANA_TX
3887 10:05:43.272684 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3888 10:05:43.275964 ===================================
3889 10:05:43.279283 data_rate = 1200,PCW = 0X5800
3890 10:05:43.282620 ===================================
3891 10:05:43.285982 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3892 10:05:43.292408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3893 10:05:43.295587 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3894 10:05:43.302369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3895 10:05:43.305834 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3896 10:05:43.308862 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3897 10:05:43.308943 [ANA_INIT] flow start
3898 10:05:43.312350 [ANA_INIT] PLL >>>>>>>>
3899 10:05:43.315516 [ANA_INIT] PLL <<<<<<<<
3900 10:05:43.319100 [ANA_INIT] MIDPI >>>>>>>>
3901 10:05:43.319206 [ANA_INIT] MIDPI <<<<<<<<
3902 10:05:43.322089 [ANA_INIT] DLL >>>>>>>>
3903 10:05:43.325751 [ANA_INIT] flow end
3904 10:05:43.328982 ============ LP4 DIFF to SE enter ============
3905 10:05:43.332050 ============ LP4 DIFF to SE exit ============
3906 10:05:43.335239 [ANA_INIT] <<<<<<<<<<<<<
3907 10:05:43.338817 [Flow] Enable top DCM control >>>>>
3908 10:05:43.341868 [Flow] Enable top DCM control <<<<<
3909 10:05:43.345617 Enable DLL master slave shuffle
3910 10:05:43.348592 ==============================================================
3911 10:05:43.352248 Gating Mode config
3912 10:05:43.358561 ==============================================================
3913 10:05:43.358656 Config description:
3914 10:05:43.368489 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3915 10:05:43.375295 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3916 10:05:43.378688 SELPH_MODE 0: By rank 1: By Phase
3917 10:05:43.384898 ==============================================================
3918 10:05:43.388762 GAT_TRACK_EN = 1
3919 10:05:43.392062 RX_GATING_MODE = 2
3920 10:05:43.395016 RX_GATING_TRACK_MODE = 2
3921 10:05:43.398537 SELPH_MODE = 1
3922 10:05:43.402002 PICG_EARLY_EN = 1
3923 10:05:43.405351 VALID_LAT_VALUE = 1
3924 10:05:43.408560 ==============================================================
3925 10:05:43.411496 Enter into Gating configuration >>>>
3926 10:05:43.415142 Exit from Gating configuration <<<<
3927 10:05:43.418132 Enter into DVFS_PRE_config >>>>>
3928 10:05:43.428283 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3929 10:05:43.431313 Exit from DVFS_PRE_config <<<<<
3930 10:05:43.434766 Enter into PICG configuration >>>>
3931 10:05:43.438462 Exit from PICG configuration <<<<
3932 10:05:43.441422 [RX_INPUT] configuration >>>>>
3933 10:05:43.445134 [RX_INPUT] configuration <<<<<
3934 10:05:43.451829 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3935 10:05:43.454809 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3936 10:05:43.461627 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3937 10:05:43.467857 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3938 10:05:43.474766 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3939 10:05:43.481256 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3940 10:05:43.484627 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3941 10:05:43.488045 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3942 10:05:43.491306 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3943 10:05:43.498164 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3944 10:05:43.501273 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3945 10:05:43.504769 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3946 10:05:43.508193 ===================================
3947 10:05:43.511428 LPDDR4 DRAM CONFIGURATION
3948 10:05:43.514368 ===================================
3949 10:05:43.514464 EX_ROW_EN[0] = 0x0
3950 10:05:43.517866 EX_ROW_EN[1] = 0x0
3951 10:05:43.521031 LP4Y_EN = 0x0
3952 10:05:43.521113 WORK_FSP = 0x0
3953 10:05:43.524685 WL = 0x2
3954 10:05:43.524761 RL = 0x2
3955 10:05:43.528371 BL = 0x2
3956 10:05:43.528445 RPST = 0x0
3957 10:05:43.531420 RD_PRE = 0x0
3958 10:05:43.531493 WR_PRE = 0x1
3959 10:05:43.534895 WR_PST = 0x0
3960 10:05:43.534966 DBI_WR = 0x0
3961 10:05:43.537797 DBI_RD = 0x0
3962 10:05:43.537874 OTF = 0x1
3963 10:05:43.541575 ===================================
3964 10:05:43.544682 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3965 10:05:43.551276 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3966 10:05:43.554363 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3967 10:05:43.557445 ===================================
3968 10:05:43.561041 LPDDR4 DRAM CONFIGURATION
3969 10:05:43.564466 ===================================
3970 10:05:43.564555 EX_ROW_EN[0] = 0x10
3971 10:05:43.567446 EX_ROW_EN[1] = 0x0
3972 10:05:43.567567 LP4Y_EN = 0x0
3973 10:05:43.571044 WORK_FSP = 0x0
3974 10:05:43.574009 WL = 0x2
3975 10:05:43.574086 RL = 0x2
3976 10:05:43.577699 BL = 0x2
3977 10:05:43.577776 RPST = 0x0
3978 10:05:43.581202 RD_PRE = 0x0
3979 10:05:43.581286 WR_PRE = 0x1
3980 10:05:43.584576 WR_PST = 0x0
3981 10:05:43.584666 DBI_WR = 0x0
3982 10:05:43.587438 DBI_RD = 0x0
3983 10:05:43.587548 OTF = 0x1
3984 10:05:43.590954 ===================================
3985 10:05:43.597132 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3986 10:05:43.601142 nWR fixed to 30
3987 10:05:43.604937 [ModeRegInit_LP4] CH0 RK0
3988 10:05:43.605017 [ModeRegInit_LP4] CH0 RK1
3989 10:05:43.608412 [ModeRegInit_LP4] CH1 RK0
3990 10:05:43.611113 [ModeRegInit_LP4] CH1 RK1
3991 10:05:43.611231 match AC timing 17
3992 10:05:43.618007 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3993 10:05:43.621390 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3994 10:05:43.624443 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3995 10:05:43.631101 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3996 10:05:43.634555 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3997 10:05:43.634642 ==
3998 10:05:43.637668 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 10:05:43.641156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 10:05:43.641240 ==
4001 10:05:43.647755 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4002 10:05:43.654505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4003 10:05:43.657520 [CA 0] Center 36 (6~66) winsize 61
4004 10:05:43.661140 [CA 1] Center 36 (6~66) winsize 61
4005 10:05:43.664131 [CA 2] Center 34 (4~65) winsize 62
4006 10:05:43.667576 [CA 3] Center 34 (4~65) winsize 62
4007 10:05:43.670974 [CA 4] Center 34 (4~64) winsize 61
4008 10:05:43.674087 [CA 5] Center 33 (3~64) winsize 62
4009 10:05:43.674199
4010 10:05:43.677118 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4011 10:05:43.677193
4012 10:05:43.680761 [CATrainingPosCal] consider 1 rank data
4013 10:05:43.684300 u2DelayCellTimex100 = 270/100 ps
4014 10:05:43.687512 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4015 10:05:43.690424 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4016 10:05:43.693905 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4017 10:05:43.697433 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4018 10:05:43.703717 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4019 10:05:43.707114 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4020 10:05:43.707219
4021 10:05:43.710528 CA PerBit enable=1, Macro0, CA PI delay=33
4022 10:05:43.710634
4023 10:05:43.714032 [CBTSetCACLKResult] CA Dly = 33
4024 10:05:43.714139 CS Dly: 5 (0~36)
4025 10:05:43.714240 ==
4026 10:05:43.717014 Dram Type= 6, Freq= 0, CH_0, rank 1
4027 10:05:43.720409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 10:05:43.723851 ==
4029 10:05:43.727230 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4030 10:05:43.733546 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4031 10:05:43.737194 [CA 0] Center 36 (6~66) winsize 61
4032 10:05:43.741010 [CA 1] Center 36 (6~66) winsize 61
4033 10:05:43.743895 [CA 2] Center 34 (4~65) winsize 62
4034 10:05:43.747505 [CA 3] Center 34 (4~65) winsize 62
4035 10:05:43.750323 [CA 4] Center 33 (3~64) winsize 62
4036 10:05:43.753838 [CA 5] Center 33 (3~64) winsize 62
4037 10:05:43.753921
4038 10:05:43.756985 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4039 10:05:43.757068
4040 10:05:43.760546 [CATrainingPosCal] consider 2 rank data
4041 10:05:43.763679 u2DelayCellTimex100 = 270/100 ps
4042 10:05:43.767295 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4043 10:05:43.770147 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4044 10:05:43.773816 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4045 10:05:43.780399 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4046 10:05:43.783558 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4047 10:05:43.787194 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4048 10:05:43.787297
4049 10:05:43.789961 CA PerBit enable=1, Macro0, CA PI delay=33
4050 10:05:43.790082
4051 10:05:43.793384 [CBTSetCACLKResult] CA Dly = 33
4052 10:05:43.793482 CS Dly: 5 (0~36)
4053 10:05:43.793578
4054 10:05:43.796645 ----->DramcWriteLeveling(PI) begin...
4055 10:05:43.800259 ==
4056 10:05:43.800343 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 10:05:43.806506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 10:05:43.806635 ==
4059 10:05:43.810318 Write leveling (Byte 0): 34 => 34
4060 10:05:43.813278 Write leveling (Byte 1): 30 => 30
4061 10:05:43.816678 DramcWriteLeveling(PI) end<-----
4062 10:05:43.816764
4063 10:05:43.816830 ==
4064 10:05:43.819844 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 10:05:43.823527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 10:05:43.823630 ==
4067 10:05:43.826784 [Gating] SW mode calibration
4068 10:05:43.832995 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4069 10:05:43.836586 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4070 10:05:43.843296 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4071 10:05:43.846368 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4072 10:05:43.849818 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4073 10:05:43.856803 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4074 10:05:43.859825 0 9 16 | B1->B0 | 3232 2424 | 0 1 | (0 0) (1 0)
4075 10:05:43.863063 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4076 10:05:43.869682 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4077 10:05:43.873215 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4078 10:05:43.876352 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4079 10:05:43.883097 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4080 10:05:43.886225 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4081 10:05:43.889815 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4082 10:05:43.896544 0 10 16 | B1->B0 | 2f2f 4141 | 0 0 | (0 0) (1 1)
4083 10:05:43.899883 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4084 10:05:43.902700 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 10:05:43.909486 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 10:05:43.913106 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4087 10:05:43.915931 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4088 10:05:43.922778 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4089 10:05:43.926161 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4090 10:05:43.929465 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4091 10:05:43.935983 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 10:05:43.939611 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 10:05:43.942568 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 10:05:43.949252 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 10:05:43.952750 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 10:05:43.955961 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 10:05:43.962566 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 10:05:43.965950 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 10:05:43.969026 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 10:05:43.976192 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 10:05:43.979165 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 10:05:43.982614 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 10:05:43.989251 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 10:05:43.992335 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 10:05:43.995792 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 10:05:44.002213 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4107 10:05:44.005977 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4108 10:05:44.009213 Total UI for P1: 0, mck2ui 16
4109 10:05:44.012046 best dqsien dly found for B0: ( 0, 13, 16)
4110 10:05:44.015614 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4111 10:05:44.019009 Total UI for P1: 0, mck2ui 16
4112 10:05:44.022418 best dqsien dly found for B1: ( 0, 13, 18)
4113 10:05:44.025871 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4114 10:05:44.028885 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4115 10:05:44.028972
4116 10:05:44.035659 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4117 10:05:44.038589 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4118 10:05:44.038703 [Gating] SW calibration Done
4119 10:05:44.041958 ==
4120 10:05:44.042065 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 10:05:44.048492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 10:05:44.048611 ==
4123 10:05:44.048706 RX Vref Scan: 0
4124 10:05:44.048805
4125 10:05:44.051599 RX Vref 0 -> 0, step: 1
4126 10:05:44.051708
4127 10:05:44.055166 RX Delay -230 -> 252, step: 16
4128 10:05:44.058753 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4129 10:05:44.061587 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4130 10:05:44.068428 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4131 10:05:44.072040 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4132 10:05:44.075057 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4133 10:05:44.078022 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4134 10:05:44.084971 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4135 10:05:44.088446 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4136 10:05:44.091436 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4137 10:05:44.095162 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4138 10:05:44.097940 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4139 10:05:44.104889 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4140 10:05:44.107902 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4141 10:05:44.111439 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4142 10:05:44.114625 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4143 10:05:44.121345 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4144 10:05:44.121453 ==
4145 10:05:44.124756 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 10:05:44.128195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 10:05:44.128276 ==
4148 10:05:44.128340 DQS Delay:
4149 10:05:44.131651 DQS0 = 0, DQS1 = 0
4150 10:05:44.131726 DQM Delay:
4151 10:05:44.134592 DQM0 = 40, DQM1 = 34
4152 10:05:44.134688 DQ Delay:
4153 10:05:44.138032 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4154 10:05:44.141367 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4155 10:05:44.144708 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4156 10:05:44.147726 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4157 10:05:44.147834
4158 10:05:44.147930
4159 10:05:44.148025 ==
4160 10:05:44.151302 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 10:05:44.154358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 10:05:44.158043 ==
4163 10:05:44.158150
4164 10:05:44.158247
4165 10:05:44.158354 TX Vref Scan disable
4166 10:05:44.161304 == TX Byte 0 ==
4167 10:05:44.164284 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4168 10:05:44.167825 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4169 10:05:44.171093 == TX Byte 1 ==
4170 10:05:44.174552 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4171 10:05:44.178221 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4172 10:05:44.178301 ==
4173 10:05:44.181243 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 10:05:44.188295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 10:05:44.188390 ==
4176 10:05:44.188463
4177 10:05:44.188539
4178 10:05:44.188629 TX Vref Scan disable
4179 10:05:44.192632 == TX Byte 0 ==
4180 10:05:44.196281 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4181 10:05:44.199257 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4182 10:05:44.202320 == TX Byte 1 ==
4183 10:05:44.205822 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4184 10:05:44.212464 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4185 10:05:44.212542
4186 10:05:44.212606 [DATLAT]
4187 10:05:44.212669 Freq=600, CH0 RK0
4188 10:05:44.212730
4189 10:05:44.215915 DATLAT Default: 0x9
4190 10:05:44.215993 0, 0xFFFF, sum = 0
4191 10:05:44.219611 1, 0xFFFF, sum = 0
4192 10:05:44.219689 2, 0xFFFF, sum = 0
4193 10:05:44.222544 3, 0xFFFF, sum = 0
4194 10:05:44.225923 4, 0xFFFF, sum = 0
4195 10:05:44.225998 5, 0xFFFF, sum = 0
4196 10:05:44.229767 6, 0xFFFF, sum = 0
4197 10:05:44.229844 7, 0xFFFF, sum = 0
4198 10:05:44.229909 8, 0x0, sum = 1
4199 10:05:44.232323 9, 0x0, sum = 2
4200 10:05:44.232407 10, 0x0, sum = 3
4201 10:05:44.236335 11, 0x0, sum = 4
4202 10:05:44.236422 best_step = 9
4203 10:05:44.236487
4204 10:05:44.236548 ==
4205 10:05:44.239160 Dram Type= 6, Freq= 0, CH_0, rank 0
4206 10:05:44.245517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 10:05:44.245634 ==
4208 10:05:44.245738 RX Vref Scan: 1
4209 10:05:44.245828
4210 10:05:44.249158 RX Vref 0 -> 0, step: 1
4211 10:05:44.249260
4212 10:05:44.252643 RX Delay -179 -> 252, step: 8
4213 10:05:44.252716
4214 10:05:44.255678 Set Vref, RX VrefLevel [Byte0]: 54
4215 10:05:44.259218 [Byte1]: 51
4216 10:05:44.259325
4217 10:05:44.262960 Final RX Vref Byte 0 = 54 to rank0
4218 10:05:44.265905 Final RX Vref Byte 1 = 51 to rank0
4219 10:05:44.269310 Final RX Vref Byte 0 = 54 to rank1
4220 10:05:44.272373 Final RX Vref Byte 1 = 51 to rank1==
4221 10:05:44.276058 Dram Type= 6, Freq= 0, CH_0, rank 0
4222 10:05:44.278992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 10:05:44.279093 ==
4224 10:05:44.282861 DQS Delay:
4225 10:05:44.282969 DQS0 = 0, DQS1 = 0
4226 10:05:44.283062 DQM Delay:
4227 10:05:44.285634 DQM0 = 42, DQM1 = 34
4228 10:05:44.285741 DQ Delay:
4229 10:05:44.289266 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4230 10:05:44.292352 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4231 10:05:44.295789 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =32
4232 10:05:44.298892 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4233 10:05:44.298999
4234 10:05:44.299097
4235 10:05:44.309157 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e1c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4236 10:05:44.312802 CH0 RK0: MR19=808, MR18=3E1C
4237 10:05:44.315722 CH0_RK0: MR19=0x808, MR18=0x3E1C, DQSOSC=398, MR23=63, INC=165, DEC=110
4238 10:05:44.315808
4239 10:05:44.319112 ----->DramcWriteLeveling(PI) begin...
4240 10:05:44.322257 ==
4241 10:05:44.325371 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 10:05:44.329074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 10:05:44.329158 ==
4244 10:05:44.332565 Write leveling (Byte 0): 34 => 34
4245 10:05:44.335391 Write leveling (Byte 1): 30 => 30
4246 10:05:44.338899 DramcWriteLeveling(PI) end<-----
4247 10:05:44.339013
4248 10:05:44.339113 ==
4249 10:05:44.342369 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 10:05:44.345666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 10:05:44.345776 ==
4252 10:05:44.348557 [Gating] SW mode calibration
4253 10:05:44.355499 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4254 10:05:44.362438 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4255 10:05:44.365595 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4256 10:05:44.369125 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4257 10:05:44.371973 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4258 10:05:44.378630 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
4259 10:05:44.382146 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4260 10:05:44.385179 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4261 10:05:44.391747 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4262 10:05:44.395674 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4263 10:05:44.398593 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4264 10:05:44.405223 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4265 10:05:44.408360 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4266 10:05:44.411887 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
4267 10:05:44.418768 0 10 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
4268 10:05:44.421827 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 10:05:44.425175 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 10:05:44.431897 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 10:05:44.434858 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4272 10:05:44.438671 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 10:05:44.444848 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 10:05:44.448352 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4275 10:05:44.451749 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4276 10:05:44.458599 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 10:05:44.461719 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 10:05:44.464785 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 10:05:44.471422 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 10:05:44.475052 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 10:05:44.478473 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 10:05:44.485137 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 10:05:44.488166 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 10:05:44.491318 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 10:05:44.498608 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 10:05:44.501770 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 10:05:44.504691 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 10:05:44.511301 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 10:05:44.514875 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 10:05:44.518402 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4291 10:05:44.521358 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4292 10:05:44.524851 Total UI for P1: 0, mck2ui 16
4293 10:05:44.528240 best dqsien dly found for B0: ( 0, 13, 12)
4294 10:05:44.534577 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4295 10:05:44.538326 Total UI for P1: 0, mck2ui 16
4296 10:05:44.541245 best dqsien dly found for B1: ( 0, 13, 16)
4297 10:05:44.545131 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4298 10:05:44.547954 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4299 10:05:44.548033
4300 10:05:44.551400 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4301 10:05:44.554777 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4302 10:05:44.558251 [Gating] SW calibration Done
4303 10:05:44.558339 ==
4304 10:05:44.561634 Dram Type= 6, Freq= 0, CH_0, rank 1
4305 10:05:44.564756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4306 10:05:44.564848 ==
4307 10:05:44.567781 RX Vref Scan: 0
4308 10:05:44.567859
4309 10:05:44.571285 RX Vref 0 -> 0, step: 1
4310 10:05:44.571385
4311 10:05:44.571453 RX Delay -230 -> 252, step: 16
4312 10:05:44.577982 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4313 10:05:44.581216 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4314 10:05:44.584350 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4315 10:05:44.587923 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4316 10:05:44.594538 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4317 10:05:44.597583 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4318 10:05:44.601576 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4319 10:05:44.604113 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4320 10:05:44.607820 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4321 10:05:44.614421 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4322 10:05:44.617939 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4323 10:05:44.620811 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4324 10:05:44.624381 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4325 10:05:44.630601 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4326 10:05:44.633999 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4327 10:05:44.637299 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4328 10:05:44.637406 ==
4329 10:05:44.640991 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 10:05:44.644063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 10:05:44.647505 ==
4332 10:05:44.647606 DQS Delay:
4333 10:05:44.647698 DQS0 = 0, DQS1 = 0
4334 10:05:44.650765 DQM Delay:
4335 10:05:44.650841 DQM0 = 41, DQM1 = 32
4336 10:05:44.654132 DQ Delay:
4337 10:05:44.657466 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4338 10:05:44.657568 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4339 10:05:44.660905 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4340 10:05:44.664228 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4341 10:05:44.667137
4342 10:05:44.667218
4343 10:05:44.667283 ==
4344 10:05:44.670650 Dram Type= 6, Freq= 0, CH_0, rank 1
4345 10:05:44.673837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 10:05:44.673921 ==
4347 10:05:44.673986
4348 10:05:44.674046
4349 10:05:44.677409 TX Vref Scan disable
4350 10:05:44.677519 == TX Byte 0 ==
4351 10:05:44.683945 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4352 10:05:44.687580 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4353 10:05:44.687696 == TX Byte 1 ==
4354 10:05:44.694130 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4355 10:05:44.697753 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4356 10:05:44.697855 ==
4357 10:05:44.700700 Dram Type= 6, Freq= 0, CH_0, rank 1
4358 10:05:44.704414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4359 10:05:44.704520 ==
4360 10:05:44.704613
4361 10:05:44.704704
4362 10:05:44.707143 TX Vref Scan disable
4363 10:05:44.710386 == TX Byte 0 ==
4364 10:05:44.714226 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4365 10:05:44.720759 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4366 10:05:44.720873 == TX Byte 1 ==
4367 10:05:44.723805 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4368 10:05:44.730304 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4369 10:05:44.730416
4370 10:05:44.730514 [DATLAT]
4371 10:05:44.730606 Freq=600, CH0 RK1
4372 10:05:44.730700
4373 10:05:44.733776 DATLAT Default: 0x9
4374 10:05:44.733878 0, 0xFFFF, sum = 0
4375 10:05:44.737290 1, 0xFFFF, sum = 0
4376 10:05:44.737398 2, 0xFFFF, sum = 0
4377 10:05:44.740193 3, 0xFFFF, sum = 0
4378 10:05:44.743634 4, 0xFFFF, sum = 0
4379 10:05:44.743742 5, 0xFFFF, sum = 0
4380 10:05:44.747425 6, 0xFFFF, sum = 0
4381 10:05:44.747532 7, 0xFFFF, sum = 0
4382 10:05:44.750573 8, 0x0, sum = 1
4383 10:05:44.750678 9, 0x0, sum = 2
4384 10:05:44.750776 10, 0x0, sum = 3
4385 10:05:44.753762 11, 0x0, sum = 4
4386 10:05:44.753869 best_step = 9
4387 10:05:44.753961
4388 10:05:44.754051 ==
4389 10:05:44.757016 Dram Type= 6, Freq= 0, CH_0, rank 1
4390 10:05:44.763825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 10:05:44.763935 ==
4392 10:05:44.764034 RX Vref Scan: 0
4393 10:05:44.764125
4394 10:05:44.766672 RX Vref 0 -> 0, step: 1
4395 10:05:44.766773
4396 10:05:44.770200 RX Delay -195 -> 252, step: 8
4397 10:05:44.773786 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4398 10:05:44.779959 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4399 10:05:44.783712 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4400 10:05:44.786578 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4401 10:05:44.790019 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4402 10:05:44.796763 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4403 10:05:44.800528 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4404 10:05:44.803533 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4405 10:05:44.806447 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4406 10:05:44.809571 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4407 10:05:44.816441 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4408 10:05:44.819837 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4409 10:05:44.822984 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4410 10:05:44.826653 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4411 10:05:44.833003 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4412 10:05:44.836361 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4413 10:05:44.836468 ==
4414 10:05:44.839931 Dram Type= 6, Freq= 0, CH_0, rank 1
4415 10:05:44.843275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 10:05:44.843383 ==
4417 10:05:44.846431 DQS Delay:
4418 10:05:44.846532 DQS0 = 0, DQS1 = 0
4419 10:05:44.849456 DQM Delay:
4420 10:05:44.849556 DQM0 = 39, DQM1 = 33
4421 10:05:44.849649 DQ Delay:
4422 10:05:44.852853 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4423 10:05:44.855940 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4424 10:05:44.859398 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4425 10:05:44.862824 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4426 10:05:44.862931
4427 10:05:44.863023
4428 10:05:44.872471 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b2d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
4429 10:05:44.876048 CH0 RK1: MR19=808, MR18=4B2D
4430 10:05:44.882562 CH0_RK1: MR19=0x808, MR18=0x4B2D, DQSOSC=395, MR23=63, INC=168, DEC=112
4431 10:05:44.882673 [RxdqsGatingPostProcess] freq 600
4432 10:05:44.889328 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4433 10:05:44.892720 Pre-setting of DQS Precalculation
4434 10:05:44.896369 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4435 10:05:44.899398 ==
4436 10:05:44.899477 Dram Type= 6, Freq= 0, CH_1, rank 0
4437 10:05:44.905821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4438 10:05:44.905931 ==
4439 10:05:44.909658 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4440 10:05:44.915804 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4441 10:05:44.919677 [CA 0] Center 35 (5~66) winsize 62
4442 10:05:44.923073 [CA 1] Center 35 (5~65) winsize 61
4443 10:05:44.926084 [CA 2] Center 34 (4~65) winsize 62
4444 10:05:44.929743 [CA 3] Center 33 (3~64) winsize 62
4445 10:05:44.932645 [CA 4] Center 34 (3~65) winsize 63
4446 10:05:44.936066 [CA 5] Center 33 (2~64) winsize 63
4447 10:05:44.936151
4448 10:05:44.939633 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4449 10:05:44.939717
4450 10:05:44.943283 [CATrainingPosCal] consider 1 rank data
4451 10:05:44.946259 u2DelayCellTimex100 = 270/100 ps
4452 10:05:44.949589 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4453 10:05:44.953119 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4454 10:05:44.959506 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4455 10:05:44.962862 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4456 10:05:44.966285 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4457 10:05:44.969507 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4458 10:05:44.969601
4459 10:05:44.972458 CA PerBit enable=1, Macro0, CA PI delay=33
4460 10:05:44.972547
4461 10:05:44.976455 [CBTSetCACLKResult] CA Dly = 33
4462 10:05:44.976544 CS Dly: 5 (0~36)
4463 10:05:44.979371 ==
4464 10:05:44.979486 Dram Type= 6, Freq= 0, CH_1, rank 1
4465 10:05:44.986188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4466 10:05:44.986305 ==
4467 10:05:44.989794 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4468 10:05:44.996000 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4469 10:05:44.999485 [CA 0] Center 35 (5~66) winsize 62
4470 10:05:45.002658 [CA 1] Center 35 (5~66) winsize 62
4471 10:05:45.006165 [CA 2] Center 34 (4~65) winsize 62
4472 10:05:45.009692 [CA 3] Center 34 (3~65) winsize 63
4473 10:05:45.012756 [CA 4] Center 34 (3~65) winsize 63
4474 10:05:45.016279 [CA 5] Center 33 (3~64) winsize 62
4475 10:05:45.016363
4476 10:05:45.019388 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4477 10:05:45.019463
4478 10:05:45.022760 [CATrainingPosCal] consider 2 rank data
4479 10:05:45.026439 u2DelayCellTimex100 = 270/100 ps
4480 10:05:45.029343 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4481 10:05:45.033004 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4482 10:05:45.039533 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4483 10:05:45.042527 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4484 10:05:45.046107 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4485 10:05:45.049188 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4486 10:05:45.049300
4487 10:05:45.052632 CA PerBit enable=1, Macro0, CA PI delay=33
4488 10:05:45.052736
4489 10:05:45.056134 [CBTSetCACLKResult] CA Dly = 33
4490 10:05:45.056243 CS Dly: 5 (0~37)
4491 10:05:45.059568
4492 10:05:45.062352 ----->DramcWriteLeveling(PI) begin...
4493 10:05:45.062469 ==
4494 10:05:45.065816 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 10:05:45.069350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 10:05:45.069463 ==
4497 10:05:45.072775 Write leveling (Byte 0): 29 => 29
4498 10:05:45.075673 Write leveling (Byte 1): 32 => 32
4499 10:05:45.079170 DramcWriteLeveling(PI) end<-----
4500 10:05:45.079258
4501 10:05:45.079324 ==
4502 10:05:45.082558 Dram Type= 6, Freq= 0, CH_1, rank 0
4503 10:05:45.085507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4504 10:05:45.085616 ==
4505 10:05:45.089169 [Gating] SW mode calibration
4506 10:05:45.095679 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4507 10:05:45.102353 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4508 10:05:45.105802 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4509 10:05:45.108885 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4510 10:05:45.115606 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4511 10:05:45.118584 0 9 12 | B1->B0 | 3333 3232 | 1 1 | (0 0) (0 0)
4512 10:05:45.122316 0 9 16 | B1->B0 | 2827 2323 | 1 0 | (0 0) (0 0)
4513 10:05:45.128725 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4514 10:05:45.132320 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4515 10:05:45.135276 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4516 10:05:45.142346 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4517 10:05:45.145388 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4518 10:05:45.149015 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4519 10:05:45.155179 0 10 12 | B1->B0 | 2a2a 2b2b | 0 0 | (0 0) (0 0)
4520 10:05:45.158497 0 10 16 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
4521 10:05:45.162013 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 10:05:45.168419 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 10:05:45.171944 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4524 10:05:45.175262 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4525 10:05:45.178655 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4526 10:05:45.185557 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4527 10:05:45.188364 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 10:05:45.192033 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4529 10:05:45.198150 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 10:05:45.201866 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 10:05:45.204815 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 10:05:45.211559 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 10:05:45.214922 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 10:05:45.217989 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 10:05:45.224601 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 10:05:45.228360 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 10:05:45.231638 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 10:05:45.238014 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 10:05:45.241432 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 10:05:45.244544 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 10:05:45.251077 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 10:05:45.254838 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 10:05:45.257877 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 10:05:45.264816 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4545 10:05:45.264896 Total UI for P1: 0, mck2ui 16
4546 10:05:45.271154 best dqsien dly found for B0: ( 0, 13, 14)
4547 10:05:45.271233 Total UI for P1: 0, mck2ui 16
4548 10:05:45.278037 best dqsien dly found for B1: ( 0, 13, 14)
4549 10:05:45.281485 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4550 10:05:45.284852 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4551 10:05:45.284961
4552 10:05:45.288391 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4553 10:05:45.291165 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4554 10:05:45.294810 [Gating] SW calibration Done
4555 10:05:45.294886 ==
4556 10:05:45.297894 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 10:05:45.301498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 10:05:45.301620 ==
4559 10:05:45.304448 RX Vref Scan: 0
4560 10:05:45.304531
4561 10:05:45.304621 RX Vref 0 -> 0, step: 1
4562 10:05:45.304706
4563 10:05:45.308019 RX Delay -230 -> 252, step: 16
4564 10:05:45.314577 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4565 10:05:45.317549 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4566 10:05:45.321231 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4567 10:05:45.324107 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4568 10:05:45.327753 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4569 10:05:45.334330 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4570 10:05:45.337639 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4571 10:05:45.341059 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4572 10:05:45.344268 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4573 10:05:45.351000 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4574 10:05:45.353962 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4575 10:05:45.357608 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4576 10:05:45.360632 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4577 10:05:45.367515 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4578 10:05:45.370820 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4579 10:05:45.373815 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4580 10:05:45.373932 ==
4581 10:05:45.377406 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 10:05:45.380833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 10:05:45.384193 ==
4584 10:05:45.384299 DQS Delay:
4585 10:05:45.384406 DQS0 = 0, DQS1 = 0
4586 10:05:45.387118 DQM Delay:
4587 10:05:45.387229 DQM0 = 44, DQM1 = 35
4588 10:05:45.387332 DQ Delay:
4589 10:05:45.390439 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4590 10:05:45.393906 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4591 10:05:45.397283 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4592 10:05:45.400840 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4593 10:05:45.400948
4594 10:05:45.403837
4595 10:05:45.403937 ==
4596 10:05:45.406999 Dram Type= 6, Freq= 0, CH_1, rank 0
4597 10:05:45.410610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 10:05:45.410719 ==
4599 10:05:45.410811
4600 10:05:45.410907
4601 10:05:45.413515 TX Vref Scan disable
4602 10:05:45.413595 == TX Byte 0 ==
4603 10:05:45.420829 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4604 10:05:45.423749 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4605 10:05:45.423834 == TX Byte 1 ==
4606 10:05:45.430427 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4607 10:05:45.433486 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4608 10:05:45.433563 ==
4609 10:05:45.437114 Dram Type= 6, Freq= 0, CH_1, rank 0
4610 10:05:45.439929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 10:05:45.440007 ==
4612 10:05:45.440079
4613 10:05:45.440162
4614 10:05:45.443681 TX Vref Scan disable
4615 10:05:45.447167 == TX Byte 0 ==
4616 10:05:45.450447 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4617 10:05:45.453438 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4618 10:05:45.457002 == TX Byte 1 ==
4619 10:05:45.459790 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4620 10:05:45.463570 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4621 10:05:45.466536
4622 10:05:45.466645 [DATLAT]
4623 10:05:45.466738 Freq=600, CH1 RK0
4624 10:05:45.466850
4625 10:05:45.469847 DATLAT Default: 0x9
4626 10:05:45.469958 0, 0xFFFF, sum = 0
4627 10:05:45.473522 1, 0xFFFF, sum = 0
4628 10:05:45.473639 2, 0xFFFF, sum = 0
4629 10:05:45.476875 3, 0xFFFF, sum = 0
4630 10:05:45.476982 4, 0xFFFF, sum = 0
4631 10:05:45.479811 5, 0xFFFF, sum = 0
4632 10:05:45.483445 6, 0xFFFF, sum = 0
4633 10:05:45.483556 7, 0xFFFF, sum = 0
4634 10:05:45.483666 8, 0x0, sum = 1
4635 10:05:45.486968 9, 0x0, sum = 2
4636 10:05:45.487098 10, 0x0, sum = 3
4637 10:05:45.489857 11, 0x0, sum = 4
4638 10:05:45.489961 best_step = 9
4639 10:05:45.490030
4640 10:05:45.490092 ==
4641 10:05:45.493122 Dram Type= 6, Freq= 0, CH_1, rank 0
4642 10:05:45.500126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 10:05:45.500225 ==
4644 10:05:45.500294 RX Vref Scan: 1
4645 10:05:45.500354
4646 10:05:45.503103 RX Vref 0 -> 0, step: 1
4647 10:05:45.503202
4648 10:05:45.506857 RX Delay -195 -> 252, step: 8
4649 10:05:45.506933
4650 10:05:45.509881 Set Vref, RX VrefLevel [Byte0]: 60
4651 10:05:45.513403 [Byte1]: 51
4652 10:05:45.513521
4653 10:05:45.516395 Final RX Vref Byte 0 = 60 to rank0
4654 10:05:45.520298 Final RX Vref Byte 1 = 51 to rank0
4655 10:05:45.522941 Final RX Vref Byte 0 = 60 to rank1
4656 10:05:45.526443 Final RX Vref Byte 1 = 51 to rank1==
4657 10:05:45.530063 Dram Type= 6, Freq= 0, CH_1, rank 0
4658 10:05:45.533039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 10:05:45.533150 ==
4660 10:05:45.536707 DQS Delay:
4661 10:05:45.536826 DQS0 = 0, DQS1 = 0
4662 10:05:45.539710 DQM Delay:
4663 10:05:45.539826 DQM0 = 40, DQM1 = 32
4664 10:05:45.539923 DQ Delay:
4665 10:05:45.542742 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4666 10:05:45.546107 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4667 10:05:45.549747 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4668 10:05:45.552809 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4669 10:05:45.552916
4670 10:05:45.553013
4671 10:05:45.562808 [DQSOSCAuto] RK0, (LSB)MR18= 0x460d, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4672 10:05:45.565850 CH1 RK0: MR19=808, MR18=460D
4673 10:05:45.572399 CH1_RK0: MR19=0x808, MR18=0x460D, DQSOSC=396, MR23=63, INC=167, DEC=111
4674 10:05:45.572504
4675 10:05:45.576131 ----->DramcWriteLeveling(PI) begin...
4676 10:05:45.576229 ==
4677 10:05:45.578960 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 10:05:45.582362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 10:05:45.582467 ==
4680 10:05:45.585889 Write leveling (Byte 0): 28 => 28
4681 10:05:45.589302 Write leveling (Byte 1): 32 => 32
4682 10:05:45.592562 DramcWriteLeveling(PI) end<-----
4683 10:05:45.592645
4684 10:05:45.592711 ==
4685 10:05:45.596021 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 10:05:45.598958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 10:05:45.599069 ==
4688 10:05:45.602155 [Gating] SW mode calibration
4689 10:05:45.609256 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4690 10:05:45.615303 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4691 10:05:45.619003 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4692 10:05:45.622443 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4693 10:05:45.628851 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4694 10:05:45.631847 0 9 12 | B1->B0 | 3232 2b2b | 1 0 | (1 0) (0 0)
4695 10:05:45.635609 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4696 10:05:45.642207 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4697 10:05:45.645229 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4698 10:05:45.648823 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4699 10:05:45.655559 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4700 10:05:45.658821 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4701 10:05:45.662104 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4702 10:05:45.668888 0 10 12 | B1->B0 | 2e2e 4141 | 0 0 | (1 1) (0 0)
4703 10:05:45.672248 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4704 10:05:45.675513 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4705 10:05:45.681917 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4706 10:05:45.685226 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4707 10:05:45.688297 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 10:05:45.695030 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4709 10:05:45.698449 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 10:05:45.701798 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4711 10:05:45.708145 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4712 10:05:45.711754 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 10:05:45.715300 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 10:05:45.721430 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 10:05:45.725190 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 10:05:45.728103 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 10:05:45.734876 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 10:05:45.737938 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 10:05:45.741436 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 10:05:45.744941 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 10:05:45.751667 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 10:05:45.754546 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 10:05:45.758308 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 10:05:45.764560 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 10:05:45.767871 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 10:05:45.771497 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4727 10:05:45.778019 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4728 10:05:45.781040 Total UI for P1: 0, mck2ui 16
4729 10:05:45.784530 best dqsien dly found for B0: ( 0, 13, 12)
4730 10:05:45.784644 Total UI for P1: 0, mck2ui 16
4731 10:05:45.791399 best dqsien dly found for B1: ( 0, 13, 14)
4732 10:05:45.794803 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4733 10:05:45.797611 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4734 10:05:45.797712
4735 10:05:45.801017 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4736 10:05:45.804618 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4737 10:05:45.808087 [Gating] SW calibration Done
4738 10:05:45.808165 ==
4739 10:05:45.810928 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 10:05:45.814549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 10:05:45.814654 ==
4742 10:05:45.817538 RX Vref Scan: 0
4743 10:05:45.817614
4744 10:05:45.821089 RX Vref 0 -> 0, step: 1
4745 10:05:45.821178
4746 10:05:45.821255 RX Delay -230 -> 252, step: 16
4747 10:05:45.827595 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4748 10:05:45.831084 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4749 10:05:45.834071 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4750 10:05:45.837739 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4751 10:05:45.844492 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4752 10:05:45.847407 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4753 10:05:45.850625 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4754 10:05:45.854124 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4755 10:05:45.860495 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4756 10:05:45.863949 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4757 10:05:45.867330 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4758 10:05:45.870654 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4759 10:05:45.873738 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4760 10:05:45.880425 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4761 10:05:45.883924 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4762 10:05:45.886979 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4763 10:05:45.887086 ==
4764 10:05:45.890624 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 10:05:45.896917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 10:05:45.897005 ==
4767 10:05:45.897071 DQS Delay:
4768 10:05:45.897140 DQS0 = 0, DQS1 = 0
4769 10:05:45.900372 DQM Delay:
4770 10:05:45.900479 DQM0 = 41, DQM1 = 36
4771 10:05:45.903763 DQ Delay:
4772 10:05:45.906771 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4773 10:05:45.906850 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4774 10:05:45.910142 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4775 10:05:45.916923 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4776 10:05:45.917004
4777 10:05:45.917069
4778 10:05:45.917145 ==
4779 10:05:45.920545 Dram Type= 6, Freq= 0, CH_1, rank 1
4780 10:05:45.923662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4781 10:05:45.923747 ==
4782 10:05:45.923812
4783 10:05:45.923879
4784 10:05:45.927260 TX Vref Scan disable
4785 10:05:45.927334 == TX Byte 0 ==
4786 10:05:45.933681 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4787 10:05:45.937068 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4788 10:05:45.937159 == TX Byte 1 ==
4789 10:05:45.943584 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4790 10:05:45.947115 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4791 10:05:45.947216 ==
4792 10:05:45.950050 Dram Type= 6, Freq= 0, CH_1, rank 1
4793 10:05:45.953469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4794 10:05:45.953567 ==
4795 10:05:45.953637
4796 10:05:45.956582
4797 10:05:45.956657 TX Vref Scan disable
4798 10:05:45.960010 == TX Byte 0 ==
4799 10:05:45.963818 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4800 10:05:45.970144 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4801 10:05:45.970228 == TX Byte 1 ==
4802 10:05:45.973812 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4803 10:05:45.980212 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4804 10:05:45.980293
4805 10:05:45.980358 [DATLAT]
4806 10:05:45.980434 Freq=600, CH1 RK1
4807 10:05:45.980494
4808 10:05:45.983088 DATLAT Default: 0x9
4809 10:05:45.983190 0, 0xFFFF, sum = 0
4810 10:05:45.986696 1, 0xFFFF, sum = 0
4811 10:05:45.989764 2, 0xFFFF, sum = 0
4812 10:05:45.989852 3, 0xFFFF, sum = 0
4813 10:05:45.993536 4, 0xFFFF, sum = 0
4814 10:05:45.993647 5, 0xFFFF, sum = 0
4815 10:05:45.996775 6, 0xFFFF, sum = 0
4816 10:05:45.996881 7, 0xFFFF, sum = 0
4817 10:05:46.000272 8, 0x0, sum = 1
4818 10:05:46.000374 9, 0x0, sum = 2
4819 10:05:46.000466 10, 0x0, sum = 3
4820 10:05:46.003062 11, 0x0, sum = 4
4821 10:05:46.003161 best_step = 9
4822 10:05:46.003250
4823 10:05:46.003336 ==
4824 10:05:46.006700 Dram Type= 6, Freq= 0, CH_1, rank 1
4825 10:05:46.013578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4826 10:05:46.013685 ==
4827 10:05:46.013785 RX Vref Scan: 0
4828 10:05:46.013874
4829 10:05:46.016389 RX Vref 0 -> 0, step: 1
4830 10:05:46.016487
4831 10:05:46.019749 RX Delay -179 -> 252, step: 8
4832 10:05:46.023399 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4833 10:05:46.029575 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4834 10:05:46.033318 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4835 10:05:46.036241 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4836 10:05:46.039569 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4837 10:05:46.046138 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4838 10:05:46.049511 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4839 10:05:46.053193 iDelay=205, Bit 7, Center 32 (-115 ~ 180) 296
4840 10:05:46.056048 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4841 10:05:46.059703 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4842 10:05:46.066203 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4843 10:05:46.069248 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4844 10:05:46.073001 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4845 10:05:46.075943 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4846 10:05:46.082739 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4847 10:05:46.086329 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4848 10:05:46.086458 ==
4849 10:05:46.089130 Dram Type= 6, Freq= 0, CH_1, rank 1
4850 10:05:46.092713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4851 10:05:46.092811 ==
4852 10:05:46.096192 DQS Delay:
4853 10:05:46.096296 DQS0 = 0, DQS1 = 0
4854 10:05:46.096391 DQM Delay:
4855 10:05:46.099660 DQM0 = 38, DQM1 = 33
4856 10:05:46.099759 DQ Delay:
4857 10:05:46.102499 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4858 10:05:46.106105 DQ4 =36, DQ5 =52, DQ6 =48, DQ7 =32
4859 10:05:46.109521 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4860 10:05:46.112301 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4861 10:05:46.112377
4862 10:05:46.112439
4863 10:05:46.122744 [DQSOSCAuto] RK1, (LSB)MR18= 0x3645, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4864 10:05:46.125745 CH1 RK1: MR19=808, MR18=3645
4865 10:05:46.129431 CH1_RK1: MR19=0x808, MR18=0x3645, DQSOSC=396, MR23=63, INC=167, DEC=111
4866 10:05:46.132376 [RxdqsGatingPostProcess] freq 600
4867 10:05:46.139067 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4868 10:05:46.142641 Pre-setting of DQS Precalculation
4869 10:05:46.145510 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4870 10:05:46.155623 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4871 10:05:46.162229 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4872 10:05:46.162332
4873 10:05:46.162423
4874 10:05:46.165693 [Calibration Summary] 1200 Mbps
4875 10:05:46.165768 CH 0, Rank 0
4876 10:05:46.168743 SW Impedance : PASS
4877 10:05:46.168810 DUTY Scan : NO K
4878 10:05:46.172148 ZQ Calibration : PASS
4879 10:05:46.175774 Jitter Meter : NO K
4880 10:05:46.175879 CBT Training : PASS
4881 10:05:46.178925 Write leveling : PASS
4882 10:05:46.182351 RX DQS gating : PASS
4883 10:05:46.182453 RX DQ/DQS(RDDQC) : PASS
4884 10:05:46.185919 TX DQ/DQS : PASS
4885 10:05:46.186028 RX DATLAT : PASS
4886 10:05:46.189091 RX DQ/DQS(Engine): PASS
4887 10:05:46.192096 TX OE : NO K
4888 10:05:46.192194 All Pass.
4889 10:05:46.192291
4890 10:05:46.195631 CH 0, Rank 1
4891 10:05:46.195705 SW Impedance : PASS
4892 10:05:46.198546 DUTY Scan : NO K
4893 10:05:46.198640 ZQ Calibration : PASS
4894 10:05:46.202137 Jitter Meter : NO K
4895 10:05:46.205588 CBT Training : PASS
4896 10:05:46.205695 Write leveling : PASS
4897 10:05:46.209163 RX DQS gating : PASS
4898 10:05:46.211954 RX DQ/DQS(RDDQC) : PASS
4899 10:05:46.212029 TX DQ/DQS : PASS
4900 10:05:46.215413 RX DATLAT : PASS
4901 10:05:46.218709 RX DQ/DQS(Engine): PASS
4902 10:05:46.218806 TX OE : NO K
4903 10:05:46.222278 All Pass.
4904 10:05:46.222378
4905 10:05:46.222468 CH 1, Rank 0
4906 10:05:46.225155 SW Impedance : PASS
4907 10:05:46.225257 DUTY Scan : NO K
4908 10:05:46.229171 ZQ Calibration : PASS
4909 10:05:46.232037 Jitter Meter : NO K
4910 10:05:46.232122 CBT Training : PASS
4911 10:05:46.235237 Write leveling : PASS
4912 10:05:46.239000 RX DQS gating : PASS
4913 10:05:46.239102 RX DQ/DQS(RDDQC) : PASS
4914 10:05:46.241986 TX DQ/DQS : PASS
4915 10:05:46.242088 RX DATLAT : PASS
4916 10:05:46.245419 RX DQ/DQS(Engine): PASS
4917 10:05:46.248711 TX OE : NO K
4918 10:05:46.248781 All Pass.
4919 10:05:46.248840
4920 10:05:46.248897 CH 1, Rank 1
4921 10:05:46.252297 SW Impedance : PASS
4922 10:05:46.255292 DUTY Scan : NO K
4923 10:05:46.255413 ZQ Calibration : PASS
4924 10:05:46.258670 Jitter Meter : NO K
4925 10:05:46.261802 CBT Training : PASS
4926 10:05:46.261900 Write leveling : PASS
4927 10:05:46.265245 RX DQS gating : PASS
4928 10:05:46.268256 RX DQ/DQS(RDDQC) : PASS
4929 10:05:46.268328 TX DQ/DQS : PASS
4930 10:05:46.271525 RX DATLAT : PASS
4931 10:05:46.274940 RX DQ/DQS(Engine): PASS
4932 10:05:46.275039 TX OE : NO K
4933 10:05:46.278211 All Pass.
4934 10:05:46.278308
4935 10:05:46.278397 DramC Write-DBI off
4936 10:05:46.281552 PER_BANK_REFRESH: Hybrid Mode
4937 10:05:46.281648 TX_TRACKING: ON
4938 10:05:46.291688 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4939 10:05:46.295168 [FAST_K] Save calibration result to emmc
4940 10:05:46.298169 dramc_set_vcore_voltage set vcore to 662500
4941 10:05:46.301275 Read voltage for 933, 3
4942 10:05:46.301357 Vio18 = 0
4943 10:05:46.304947 Vcore = 662500
4944 10:05:46.305028 Vdram = 0
4945 10:05:46.305093 Vddq = 0
4946 10:05:46.308342 Vmddr = 0
4947 10:05:46.311628 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4948 10:05:46.318147 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4949 10:05:46.318231 MEM_TYPE=3, freq_sel=17
4950 10:05:46.321462 sv_algorithm_assistance_LP4_1600
4951 10:05:46.328023 ============ PULL DRAM RESETB DOWN ============
4952 10:05:46.331344 ========== PULL DRAM RESETB DOWN end =========
4953 10:05:46.334860 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4954 10:05:46.338385 ===================================
4955 10:05:46.341475 LPDDR4 DRAM CONFIGURATION
4956 10:05:46.345104 ===================================
4957 10:05:46.345190 EX_ROW_EN[0] = 0x0
4958 10:05:46.347944 EX_ROW_EN[1] = 0x0
4959 10:05:46.351545 LP4Y_EN = 0x0
4960 10:05:46.351622 WORK_FSP = 0x0
4961 10:05:46.354442 WL = 0x3
4962 10:05:46.354515 RL = 0x3
4963 10:05:46.358130 BL = 0x2
4964 10:05:46.358241 RPST = 0x0
4965 10:05:46.361766 RD_PRE = 0x0
4966 10:05:46.361869 WR_PRE = 0x1
4967 10:05:46.364600 WR_PST = 0x0
4968 10:05:46.364701 DBI_WR = 0x0
4969 10:05:46.368316 DBI_RD = 0x0
4970 10:05:46.368391 OTF = 0x1
4971 10:05:46.371036 ===================================
4972 10:05:46.374572 ===================================
4973 10:05:46.378063 ANA top config
4974 10:05:46.381369 ===================================
4975 10:05:46.381477 DLL_ASYNC_EN = 0
4976 10:05:46.384902 ALL_SLAVE_EN = 1
4977 10:05:46.387951 NEW_RANK_MODE = 1
4978 10:05:46.391125 DLL_IDLE_MODE = 1
4979 10:05:46.394543 LP45_APHY_COMB_EN = 1
4980 10:05:46.394647 TX_ODT_DIS = 1
4981 10:05:46.398199 NEW_8X_MODE = 1
4982 10:05:46.401223 ===================================
4983 10:05:46.404816 ===================================
4984 10:05:46.407949 data_rate = 1866
4985 10:05:46.411442 CKR = 1
4986 10:05:46.414305 DQ_P2S_RATIO = 8
4987 10:05:46.417798 ===================================
4988 10:05:46.417876 CA_P2S_RATIO = 8
4989 10:05:46.421166 DQ_CA_OPEN = 0
4990 10:05:46.424618 DQ_SEMI_OPEN = 0
4991 10:05:46.427953 CA_SEMI_OPEN = 0
4992 10:05:46.431447 CA_FULL_RATE = 0
4993 10:05:46.434261 DQ_CKDIV4_EN = 1
4994 10:05:46.434332 CA_CKDIV4_EN = 1
4995 10:05:46.437747 CA_PREDIV_EN = 0
4996 10:05:46.440744 PH8_DLY = 0
4997 10:05:46.444392 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4998 10:05:46.447602 DQ_AAMCK_DIV = 4
4999 10:05:46.450612 CA_AAMCK_DIV = 4
5000 10:05:46.450695 CA_ADMCK_DIV = 4
5001 10:05:46.454116 DQ_TRACK_CA_EN = 0
5002 10:05:46.457516 CA_PICK = 933
5003 10:05:46.460824 CA_MCKIO = 933
5004 10:05:46.464282 MCKIO_SEMI = 0
5005 10:05:46.467589 PLL_FREQ = 3732
5006 10:05:46.470648 DQ_UI_PI_RATIO = 32
5007 10:05:46.470762 CA_UI_PI_RATIO = 0
5008 10:05:46.474164 ===================================
5009 10:05:46.477196 ===================================
5010 10:05:46.480796 memory_type:LPDDR4
5011 10:05:46.484273 GP_NUM : 10
5012 10:05:46.484367 SRAM_EN : 1
5013 10:05:46.487276 MD32_EN : 0
5014 10:05:46.490973 ===================================
5015 10:05:46.493984 [ANA_INIT] >>>>>>>>>>>>>>
5016 10:05:46.497480 <<<<<< [CONFIGURE PHASE]: ANA_TX
5017 10:05:46.500556 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5018 10:05:46.504327 ===================================
5019 10:05:46.504428 data_rate = 1866,PCW = 0X8f00
5020 10:05:46.507318 ===================================
5021 10:05:46.510895 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5022 10:05:46.517210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5023 10:05:46.523873 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5024 10:05:46.527378 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5025 10:05:46.530712 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5026 10:05:46.533663 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5027 10:05:46.537066 [ANA_INIT] flow start
5028 10:05:46.540062 [ANA_INIT] PLL >>>>>>>>
5029 10:05:46.540171 [ANA_INIT] PLL <<<<<<<<
5030 10:05:46.543643 [ANA_INIT] MIDPI >>>>>>>>
5031 10:05:46.547290 [ANA_INIT] MIDPI <<<<<<<<
5032 10:05:46.547397 [ANA_INIT] DLL >>>>>>>>
5033 10:05:46.550241 [ANA_INIT] flow end
5034 10:05:46.553690 ============ LP4 DIFF to SE enter ============
5035 10:05:46.556799 ============ LP4 DIFF to SE exit ============
5036 10:05:46.560296 [ANA_INIT] <<<<<<<<<<<<<
5037 10:05:46.563835 [Flow] Enable top DCM control >>>>>
5038 10:05:46.566683 [Flow] Enable top DCM control <<<<<
5039 10:05:46.570225 Enable DLL master slave shuffle
5040 10:05:46.577440 ==============================================================
5041 10:05:46.577524 Gating Mode config
5042 10:05:46.583337 ==============================================================
5043 10:05:46.583455 Config description:
5044 10:05:46.593538 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5045 10:05:46.599765 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5046 10:05:46.607037 SELPH_MODE 0: By rank 1: By Phase
5047 10:05:46.609590 ==============================================================
5048 10:05:46.613087 GAT_TRACK_EN = 1
5049 10:05:46.616267 RX_GATING_MODE = 2
5050 10:05:46.620101 RX_GATING_TRACK_MODE = 2
5051 10:05:46.622978 SELPH_MODE = 1
5052 10:05:46.626610 PICG_EARLY_EN = 1
5053 10:05:46.629889 VALID_LAT_VALUE = 1
5054 10:05:46.636772 ==============================================================
5055 10:05:46.640169 Enter into Gating configuration >>>>
5056 10:05:46.642923 Exit from Gating configuration <<<<
5057 10:05:46.646208 Enter into DVFS_PRE_config >>>>>
5058 10:05:46.656687 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5059 10:05:46.659631 Exit from DVFS_PRE_config <<<<<
5060 10:05:46.663319 Enter into PICG configuration >>>>
5061 10:05:46.666161 Exit from PICG configuration <<<<
5062 10:05:46.669677 [RX_INPUT] configuration >>>>>
5063 10:05:46.669764 [RX_INPUT] configuration <<<<<
5064 10:05:46.676250 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5065 10:05:46.682916 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5066 10:05:46.686403 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5067 10:05:46.693155 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5068 10:05:46.699938 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5069 10:05:46.706260 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5070 10:05:46.709287 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5071 10:05:46.712994 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5072 10:05:46.719296 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5073 10:05:46.722653 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5074 10:05:46.726115 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5075 10:05:46.733031 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5076 10:05:46.736247 ===================================
5077 10:05:46.736332 LPDDR4 DRAM CONFIGURATION
5078 10:05:46.739670 ===================================
5079 10:05:46.742986 EX_ROW_EN[0] = 0x0
5080 10:05:46.743068 EX_ROW_EN[1] = 0x0
5081 10:05:46.745862 LP4Y_EN = 0x0
5082 10:05:46.745945 WORK_FSP = 0x0
5083 10:05:46.749449 WL = 0x3
5084 10:05:46.749532 RL = 0x3
5085 10:05:46.752396 BL = 0x2
5086 10:05:46.755923 RPST = 0x0
5087 10:05:46.756012 RD_PRE = 0x0
5088 10:05:46.759087 WR_PRE = 0x1
5089 10:05:46.759157 WR_PST = 0x0
5090 10:05:46.762553 DBI_WR = 0x0
5091 10:05:46.762629 DBI_RD = 0x0
5092 10:05:46.765696 OTF = 0x1
5093 10:05:46.769279 ===================================
5094 10:05:46.772273 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5095 10:05:46.775467 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5096 10:05:46.782269 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5097 10:05:46.782352 ===================================
5098 10:05:46.785369 LPDDR4 DRAM CONFIGURATION
5099 10:05:46.789109 ===================================
5100 10:05:46.792006 EX_ROW_EN[0] = 0x10
5101 10:05:46.792084 EX_ROW_EN[1] = 0x0
5102 10:05:46.795311 LP4Y_EN = 0x0
5103 10:05:46.795406 WORK_FSP = 0x0
5104 10:05:46.798497 WL = 0x3
5105 10:05:46.798575 RL = 0x3
5106 10:05:46.802093 BL = 0x2
5107 10:05:46.805261 RPST = 0x0
5108 10:05:46.805335 RD_PRE = 0x0
5109 10:05:46.808826 WR_PRE = 0x1
5110 10:05:46.808926 WR_PST = 0x0
5111 10:05:46.811844 DBI_WR = 0x0
5112 10:05:46.811923 DBI_RD = 0x0
5113 10:05:46.815472 OTF = 0x1
5114 10:05:46.818483 ===================================
5115 10:05:46.825262 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5116 10:05:46.828763 nWR fixed to 30
5117 10:05:46.828837 [ModeRegInit_LP4] CH0 RK0
5118 10:05:46.832192 [ModeRegInit_LP4] CH0 RK1
5119 10:05:46.835152 [ModeRegInit_LP4] CH1 RK0
5120 10:05:46.835227 [ModeRegInit_LP4] CH1 RK1
5121 10:05:46.838400 match AC timing 9
5122 10:05:46.841532 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5123 10:05:46.845233 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5124 10:05:46.851799 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5125 10:05:46.855200 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5126 10:05:46.861792 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5127 10:05:46.861871 ==
5128 10:05:46.864692 Dram Type= 6, Freq= 0, CH_0, rank 0
5129 10:05:46.868275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 10:05:46.868355 ==
5131 10:05:46.874744 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5132 10:05:46.878633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5133 10:05:46.882579 [CA 0] Center 38 (8~69) winsize 62
5134 10:05:46.885640 [CA 1] Center 38 (7~69) winsize 63
5135 10:05:46.889308 [CA 2] Center 35 (5~66) winsize 62
5136 10:05:46.892314 [CA 3] Center 35 (5~66) winsize 62
5137 10:05:46.895493 [CA 4] Center 34 (4~64) winsize 61
5138 10:05:46.898949 [CA 5] Center 34 (4~64) winsize 61
5139 10:05:46.899058
5140 10:05:46.902648 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5141 10:05:46.902747
5142 10:05:46.905669 [CATrainingPosCal] consider 1 rank data
5143 10:05:46.908912 u2DelayCellTimex100 = 270/100 ps
5144 10:05:46.912417 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5145 10:05:46.918990 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5146 10:05:46.922039 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5147 10:05:46.925669 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5148 10:05:46.928650 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5149 10:05:46.932159 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5150 10:05:46.932239
5151 10:05:46.935377 CA PerBit enable=1, Macro0, CA PI delay=34
5152 10:05:46.935456
5153 10:05:46.939040 [CBTSetCACLKResult] CA Dly = 34
5154 10:05:46.941981 CS Dly: 6 (0~37)
5155 10:05:46.942084 ==
5156 10:05:46.945241 Dram Type= 6, Freq= 0, CH_0, rank 1
5157 10:05:46.948654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5158 10:05:46.948738 ==
5159 10:05:46.955528 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5160 10:05:46.958405 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5161 10:05:46.962337 [CA 0] Center 38 (8~69) winsize 62
5162 10:05:46.965944 [CA 1] Center 38 (8~69) winsize 62
5163 10:05:46.968926 [CA 2] Center 35 (5~66) winsize 62
5164 10:05:46.972465 [CA 3] Center 35 (4~66) winsize 63
5165 10:05:46.975935 [CA 4] Center 34 (3~65) winsize 63
5166 10:05:46.979578 [CA 5] Center 33 (3~64) winsize 62
5167 10:05:46.979661
5168 10:05:46.982513 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5169 10:05:46.982597
5170 10:05:46.985845 [CATrainingPosCal] consider 2 rank data
5171 10:05:46.989235 u2DelayCellTimex100 = 270/100 ps
5172 10:05:46.992358 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5173 10:05:46.995978 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5174 10:05:47.002846 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5175 10:05:47.005823 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5176 10:05:47.009302 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5177 10:05:47.012246 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5178 10:05:47.012348
5179 10:05:47.015886 CA PerBit enable=1, Macro0, CA PI delay=34
5180 10:05:47.015958
5181 10:05:47.018796 [CBTSetCACLKResult] CA Dly = 34
5182 10:05:47.018899 CS Dly: 7 (0~39)
5183 10:05:47.018988
5184 10:05:47.022333 ----->DramcWriteLeveling(PI) begin...
5185 10:05:47.025506 ==
5186 10:05:47.029095 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 10:05:47.032062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 10:05:47.032136 ==
5189 10:05:47.035937 Write leveling (Byte 0): 28 => 28
5190 10:05:47.038796 Write leveling (Byte 1): 27 => 27
5191 10:05:47.042338 DramcWriteLeveling(PI) end<-----
5192 10:05:47.042420
5193 10:05:47.042485 ==
5194 10:05:47.045848 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 10:05:47.049196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 10:05:47.049280 ==
5197 10:05:47.052536 [Gating] SW mode calibration
5198 10:05:47.058904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5199 10:05:47.065580 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5200 10:05:47.068679 0 14 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5201 10:05:47.072227 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
5202 10:05:47.075296 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5203 10:05:47.082000 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5204 10:05:47.085571 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5205 10:05:47.088596 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5206 10:05:47.095374 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5207 10:05:47.098906 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
5208 10:05:47.102184 0 15 0 | B1->B0 | 3232 2d2d | 0 0 | (0 1) (0 0)
5209 10:05:47.109051 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5210 10:05:47.112123 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5211 10:05:47.115595 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5212 10:05:47.122073 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5213 10:05:47.125773 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5214 10:05:47.128700 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5215 10:05:47.135429 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5216 10:05:47.138874 1 0 0 | B1->B0 | 3030 3d3d | 0 0 | (0 0) (0 0)
5217 10:05:47.142316 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 10:05:47.148617 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 10:05:47.152100 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5220 10:05:47.155582 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5221 10:05:47.162106 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5222 10:05:47.165478 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 10:05:47.168442 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 10:05:47.175046 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5225 10:05:47.178525 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5226 10:05:47.182170 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 10:05:47.188612 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 10:05:47.191611 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 10:05:47.195081 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 10:05:47.201420 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 10:05:47.204841 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 10:05:47.208705 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 10:05:47.215550 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 10:05:47.218496 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 10:05:47.221553 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 10:05:47.225256 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 10:05:47.231490 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 10:05:47.235195 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 10:05:47.238254 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5240 10:05:47.244788 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5241 10:05:47.248114 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5242 10:05:47.251715 Total UI for P1: 0, mck2ui 16
5243 10:05:47.255143 best dqsien dly found for B0: ( 1, 2, 30)
5244 10:05:47.257837 Total UI for P1: 0, mck2ui 16
5245 10:05:47.261323 best dqsien dly found for B1: ( 1, 2, 30)
5246 10:05:47.264670 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5247 10:05:47.268342 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5248 10:05:47.268452
5249 10:05:47.271220 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5250 10:05:47.277694 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5251 10:05:47.277811 [Gating] SW calibration Done
5252 10:05:47.277923 ==
5253 10:05:47.281352 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 10:05:47.288124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 10:05:47.288243 ==
5256 10:05:47.288353 RX Vref Scan: 0
5257 10:05:47.288462
5258 10:05:47.291004 RX Vref 0 -> 0, step: 1
5259 10:05:47.291108
5260 10:05:47.294157 RX Delay -80 -> 252, step: 8
5261 10:05:47.297790 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5262 10:05:47.300763 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5263 10:05:47.304165 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5264 10:05:47.307728 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5265 10:05:47.314009 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5266 10:05:47.317478 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5267 10:05:47.321059 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5268 10:05:47.324126 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5269 10:05:47.327813 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5270 10:05:47.333805 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5271 10:05:47.337455 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5272 10:05:47.340640 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5273 10:05:47.344182 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5274 10:05:47.347108 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5275 10:05:47.350511 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5276 10:05:47.357009 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5277 10:05:47.357092 ==
5278 10:05:47.360408 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 10:05:47.363706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 10:05:47.363790 ==
5281 10:05:47.363871 DQS Delay:
5282 10:05:47.367178 DQS0 = 0, DQS1 = 0
5283 10:05:47.367287 DQM Delay:
5284 10:05:47.370469 DQM0 = 98, DQM1 = 88
5285 10:05:47.370552 DQ Delay:
5286 10:05:47.373998 DQ0 =99, DQ1 =103, DQ2 =91, DQ3 =91
5287 10:05:47.377505 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5288 10:05:47.380810 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5289 10:05:47.383966 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5290 10:05:47.384042
5291 10:05:47.384140
5292 10:05:47.384228 ==
5293 10:05:47.387313 Dram Type= 6, Freq= 0, CH_0, rank 0
5294 10:05:47.391327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 10:05:47.391420 ==
5296 10:05:47.393852
5297 10:05:47.393935
5298 10:05:47.394000 TX Vref Scan disable
5299 10:05:47.397365 == TX Byte 0 ==
5300 10:05:47.400932 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5301 10:05:47.404000 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5302 10:05:47.407233 == TX Byte 1 ==
5303 10:05:47.410362 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5304 10:05:47.413805 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5305 10:05:47.413889 ==
5306 10:05:47.417412 Dram Type= 6, Freq= 0, CH_0, rank 0
5307 10:05:47.424179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 10:05:47.424263 ==
5309 10:05:47.424330
5310 10:05:47.424390
5311 10:05:47.424448 TX Vref Scan disable
5312 10:05:47.428356 == TX Byte 0 ==
5313 10:05:47.431493 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5314 10:05:47.437937 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5315 10:05:47.438022 == TX Byte 1 ==
5316 10:05:47.441713 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5317 10:05:47.447871 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5318 10:05:47.447959
5319 10:05:47.448026 [DATLAT]
5320 10:05:47.448088 Freq=933, CH0 RK0
5321 10:05:47.448148
5322 10:05:47.451257 DATLAT Default: 0xd
5323 10:05:47.451373 0, 0xFFFF, sum = 0
5324 10:05:47.454272 1, 0xFFFF, sum = 0
5325 10:05:47.457693 2, 0xFFFF, sum = 0
5326 10:05:47.457779 3, 0xFFFF, sum = 0
5327 10:05:47.461389 4, 0xFFFF, sum = 0
5328 10:05:47.461474 5, 0xFFFF, sum = 0
5329 10:05:47.464151 6, 0xFFFF, sum = 0
5330 10:05:47.464265 7, 0xFFFF, sum = 0
5331 10:05:47.467600 8, 0xFFFF, sum = 0
5332 10:05:47.467702 9, 0xFFFF, sum = 0
5333 10:05:47.471128 10, 0x0, sum = 1
5334 10:05:47.471238 11, 0x0, sum = 2
5335 10:05:47.474709 12, 0x0, sum = 3
5336 10:05:47.474794 13, 0x0, sum = 4
5337 10:05:47.474862 best_step = 11
5338 10:05:47.477700
5339 10:05:47.477782 ==
5340 10:05:47.481222 Dram Type= 6, Freq= 0, CH_0, rank 0
5341 10:05:47.484519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 10:05:47.484604 ==
5343 10:05:47.484671 RX Vref Scan: 1
5344 10:05:47.484733
5345 10:05:47.487580 RX Vref 0 -> 0, step: 1
5346 10:05:47.487690
5347 10:05:47.490796 RX Delay -61 -> 252, step: 4
5348 10:05:47.490880
5349 10:05:47.494667 Set Vref, RX VrefLevel [Byte0]: 54
5350 10:05:47.497544 [Byte1]: 51
5351 10:05:47.497651
5352 10:05:47.500789 Final RX Vref Byte 0 = 54 to rank0
5353 10:05:47.504146 Final RX Vref Byte 1 = 51 to rank0
5354 10:05:47.507829 Final RX Vref Byte 0 = 54 to rank1
5355 10:05:47.510789 Final RX Vref Byte 1 = 51 to rank1==
5356 10:05:47.514330 Dram Type= 6, Freq= 0, CH_0, rank 0
5357 10:05:47.517547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 10:05:47.520741 ==
5359 10:05:47.520837 DQS Delay:
5360 10:05:47.520908 DQS0 = 0, DQS1 = 0
5361 10:05:47.524297 DQM Delay:
5362 10:05:47.524379 DQM0 = 97, DQM1 = 88
5363 10:05:47.527311 DQ Delay:
5364 10:05:47.530947 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5365 10:05:47.531061 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =102
5366 10:05:47.533963 DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =82
5367 10:05:47.537211 DQ12 =96, DQ13 =90, DQ14 =98, DQ15 =96
5368 10:05:47.541004
5369 10:05:47.541123
5370 10:05:47.547773 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5371 10:05:47.550962 CH0 RK0: MR19=504, MR18=10FB
5372 10:05:47.557657 CH0_RK0: MR19=0x504, MR18=0x10FB, DQSOSC=416, MR23=63, INC=62, DEC=41
5373 10:05:47.557779
5374 10:05:47.561131 ----->DramcWriteLeveling(PI) begin...
5375 10:05:47.561223 ==
5376 10:05:47.564066 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 10:05:47.567481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 10:05:47.567568 ==
5379 10:05:47.570571 Write leveling (Byte 0): 31 => 31
5380 10:05:47.574330 Write leveling (Byte 1): 26 => 26
5381 10:05:47.577158 DramcWriteLeveling(PI) end<-----
5382 10:05:47.577239
5383 10:05:47.577306 ==
5384 10:05:47.580604 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 10:05:47.583600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 10:05:47.583681 ==
5387 10:05:47.587572 [Gating] SW mode calibration
5388 10:05:47.594084 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5389 10:05:47.600666 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5390 10:05:47.603703 0 14 0 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
5391 10:05:47.607069 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5392 10:05:47.613720 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5393 10:05:47.617184 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5394 10:05:47.620849 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5395 10:05:47.627034 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5396 10:05:47.630525 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5397 10:05:47.633482 0 14 28 | B1->B0 | 3131 2a2a | 1 0 | (1 0) (0 0)
5398 10:05:47.640164 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
5399 10:05:47.643621 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5400 10:05:47.646597 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5401 10:05:47.653980 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5402 10:05:47.656894 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5403 10:05:47.660295 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5404 10:05:47.666627 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5405 10:05:47.670298 0 15 28 | B1->B0 | 2a2a 3939 | 1 0 | (0 0) (0 0)
5406 10:05:47.673148 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5407 10:05:47.680112 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5408 10:05:47.683008 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 10:05:47.686380 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5410 10:05:47.693216 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 10:05:47.697068 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 10:05:47.699937 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 10:05:47.706323 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5414 10:05:47.709919 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5415 10:05:47.712923 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 10:05:47.719960 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 10:05:47.723040 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 10:05:47.726642 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 10:05:47.733287 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 10:05:47.736276 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 10:05:47.739899 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 10:05:47.746289 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 10:05:47.749677 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 10:05:47.752690 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 10:05:47.759526 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 10:05:47.763080 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 10:05:47.766249 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 10:05:47.769969 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5429 10:05:47.776195 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5430 10:05:47.779541 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5431 10:05:47.783015 Total UI for P1: 0, mck2ui 16
5432 10:05:47.786235 best dqsien dly found for B0: ( 1, 2, 26)
5433 10:05:47.789188 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5434 10:05:47.795948 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5435 10:05:47.799548 Total UI for P1: 0, mck2ui 16
5436 10:05:47.802891 best dqsien dly found for B1: ( 1, 3, 0)
5437 10:05:47.805906 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5438 10:05:47.809635 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5439 10:05:47.809718
5440 10:05:47.812501 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5441 10:05:47.816088 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5442 10:05:47.819066 [Gating] SW calibration Done
5443 10:05:47.819149 ==
5444 10:05:47.822635 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 10:05:47.825689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 10:05:47.825772 ==
5447 10:05:47.829068 RX Vref Scan: 0
5448 10:05:47.829150
5449 10:05:47.829235 RX Vref 0 -> 0, step: 1
5450 10:05:47.832248
5451 10:05:47.832330 RX Delay -80 -> 252, step: 8
5452 10:05:47.838834 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5453 10:05:47.842885 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5454 10:05:47.845922 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5455 10:05:47.848863 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5456 10:05:47.852454 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5457 10:05:47.856148 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5458 10:05:47.859013 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5459 10:05:47.865848 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5460 10:05:47.869271 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5461 10:05:47.872536 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5462 10:05:47.875702 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5463 10:05:47.878679 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5464 10:05:47.885733 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5465 10:05:47.889283 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5466 10:05:47.892001 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5467 10:05:47.895282 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5468 10:05:47.895376 ==
5469 10:05:47.899193 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 10:05:47.902114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 10:05:47.905447 ==
5472 10:05:47.905531 DQS Delay:
5473 10:05:47.905598 DQS0 = 0, DQS1 = 0
5474 10:05:47.908807 DQM Delay:
5475 10:05:47.908890 DQM0 = 97, DQM1 = 87
5476 10:05:47.912337 DQ Delay:
5477 10:05:47.912421 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5478 10:05:47.915445 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5479 10:05:47.918974 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5480 10:05:47.922664 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5481 10:05:47.925664
5482 10:05:47.925751
5483 10:05:47.925816 ==
5484 10:05:47.928637 Dram Type= 6, Freq= 0, CH_0, rank 1
5485 10:05:47.932283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 10:05:47.932390 ==
5487 10:05:47.932475
5488 10:05:47.932537
5489 10:05:47.935767 TX Vref Scan disable
5490 10:05:47.935869 == TX Byte 0 ==
5491 10:05:47.942314 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5492 10:05:47.945327 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5493 10:05:47.945401 == TX Byte 1 ==
5494 10:05:47.952262 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5495 10:05:47.955199 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5496 10:05:47.955274 ==
5497 10:05:47.958717 Dram Type= 6, Freq= 0, CH_0, rank 1
5498 10:05:47.962384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 10:05:47.962464 ==
5500 10:05:47.962530
5501 10:05:47.962588
5502 10:05:47.965499 TX Vref Scan disable
5503 10:05:47.968545 == TX Byte 0 ==
5504 10:05:47.971790 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5505 10:05:47.975715 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5506 10:05:47.978878 == TX Byte 1 ==
5507 10:05:47.981851 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5508 10:05:47.985376 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5509 10:05:47.985456
5510 10:05:47.988658 [DATLAT]
5511 10:05:47.988735 Freq=933, CH0 RK1
5512 10:05:47.988797
5513 10:05:47.991897 DATLAT Default: 0xb
5514 10:05:47.991974 0, 0xFFFF, sum = 0
5515 10:05:47.995330 1, 0xFFFF, sum = 0
5516 10:05:47.995479 2, 0xFFFF, sum = 0
5517 10:05:47.998789 3, 0xFFFF, sum = 0
5518 10:05:47.998894 4, 0xFFFF, sum = 0
5519 10:05:48.001460 5, 0xFFFF, sum = 0
5520 10:05:48.001558 6, 0xFFFF, sum = 0
5521 10:05:48.005385 7, 0xFFFF, sum = 0
5522 10:05:48.005485 8, 0xFFFF, sum = 0
5523 10:05:48.008294 9, 0xFFFF, sum = 0
5524 10:05:48.008443 10, 0x0, sum = 1
5525 10:05:48.011887 11, 0x0, sum = 2
5526 10:05:48.011997 12, 0x0, sum = 3
5527 10:05:48.014894 13, 0x0, sum = 4
5528 10:05:48.014997 best_step = 11
5529 10:05:48.015088
5530 10:05:48.015177 ==
5531 10:05:48.018164 Dram Type= 6, Freq= 0, CH_0, rank 1
5532 10:05:48.025373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 10:05:48.025475 ==
5534 10:05:48.025569 RX Vref Scan: 0
5535 10:05:48.025658
5536 10:05:48.028022 RX Vref 0 -> 0, step: 1
5537 10:05:48.028132
5538 10:05:48.031682 RX Delay -61 -> 252, step: 4
5539 10:05:48.035332 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5540 10:05:48.038289 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5541 10:05:48.044724 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5542 10:05:48.048273 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5543 10:05:48.051343 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5544 10:05:48.054503 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5545 10:05:48.058146 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5546 10:05:48.061739 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5547 10:05:48.068577 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5548 10:05:48.071487 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5549 10:05:48.075125 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5550 10:05:48.077952 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5551 10:05:48.081392 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5552 10:05:48.087975 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5553 10:05:48.091367 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5554 10:05:48.095045 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5555 10:05:48.095147 ==
5556 10:05:48.097943 Dram Type= 6, Freq= 0, CH_0, rank 1
5557 10:05:48.100933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 10:05:48.101039 ==
5559 10:05:48.104358 DQS Delay:
5560 10:05:48.104456 DQS0 = 0, DQS1 = 0
5561 10:05:48.107840 DQM Delay:
5562 10:05:48.107937 DQM0 = 95, DQM1 = 87
5563 10:05:48.108024 DQ Delay:
5564 10:05:48.111294 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5565 10:05:48.114561 DQ4 =94, DQ5 =84, DQ6 =106, DQ7 =104
5566 10:05:48.118123 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =78
5567 10:05:48.121257 DQ12 =92, DQ13 =92, DQ14 =100, DQ15 =94
5568 10:05:48.121360
5569 10:05:48.121454
5570 10:05:48.131554 [DQSOSCAuto] RK1, (LSB)MR18= 0x1603, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5571 10:05:48.134428 CH0 RK1: MR19=505, MR18=1603
5572 10:05:48.141063 CH0_RK1: MR19=0x505, MR18=0x1603, DQSOSC=414, MR23=63, INC=63, DEC=42
5573 10:05:48.141143 [RxdqsGatingPostProcess] freq 933
5574 10:05:48.147744 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5575 10:05:48.150825 best DQS0 dly(2T, 0.5T) = (0, 10)
5576 10:05:48.154554 best DQS1 dly(2T, 0.5T) = (0, 10)
5577 10:05:48.157581 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5578 10:05:48.161124 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5579 10:05:48.164095 best DQS0 dly(2T, 0.5T) = (0, 10)
5580 10:05:48.167608 best DQS1 dly(2T, 0.5T) = (0, 11)
5581 10:05:48.171418 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5582 10:05:48.174477 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5583 10:05:48.177401 Pre-setting of DQS Precalculation
5584 10:05:48.180917 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5585 10:05:48.181000 ==
5586 10:05:48.184332 Dram Type= 6, Freq= 0, CH_1, rank 0
5587 10:05:48.187663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5588 10:05:48.187783 ==
5589 10:05:48.194173 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5590 10:05:48.200821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5591 10:05:48.203838 [CA 0] Center 36 (6~67) winsize 62
5592 10:05:48.207320 [CA 1] Center 36 (6~67) winsize 62
5593 10:05:48.210707 [CA 2] Center 34 (4~64) winsize 61
5594 10:05:48.214003 [CA 3] Center 33 (3~64) winsize 62
5595 10:05:48.217544 [CA 4] Center 34 (4~64) winsize 61
5596 10:05:48.220840 [CA 5] Center 33 (3~64) winsize 62
5597 10:05:48.220958
5598 10:05:48.223680 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5599 10:05:48.223765
5600 10:05:48.227320 [CATrainingPosCal] consider 1 rank data
5601 10:05:48.230798 u2DelayCellTimex100 = 270/100 ps
5602 10:05:48.234209 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5603 10:05:48.237165 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5604 10:05:48.240245 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5605 10:05:48.243926 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5606 10:05:48.250584 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5607 10:05:48.253478 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5608 10:05:48.253556
5609 10:05:48.257255 CA PerBit enable=1, Macro0, CA PI delay=33
5610 10:05:48.257331
5611 10:05:48.260282 [CBTSetCACLKResult] CA Dly = 33
5612 10:05:48.260356 CS Dly: 4 (0~35)
5613 10:05:48.260418 ==
5614 10:05:48.264106 Dram Type= 6, Freq= 0, CH_1, rank 1
5615 10:05:48.270405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 10:05:48.270511 ==
5617 10:05:48.273421 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5618 10:05:48.280269 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5619 10:05:48.283790 [CA 0] Center 36 (6~67) winsize 62
5620 10:05:48.287235 [CA 1] Center 36 (6~67) winsize 62
5621 10:05:48.289939 [CA 2] Center 33 (3~64) winsize 62
5622 10:05:48.293469 [CA 3] Center 33 (3~64) winsize 62
5623 10:05:48.296618 [CA 4] Center 33 (3~64) winsize 62
5624 10:05:48.300134 [CA 5] Center 33 (2~64) winsize 63
5625 10:05:48.300219
5626 10:05:48.303603 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5627 10:05:48.303687
5628 10:05:48.306753 [CATrainingPosCal] consider 2 rank data
5629 10:05:48.310279 u2DelayCellTimex100 = 270/100 ps
5630 10:05:48.313428 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5631 10:05:48.316483 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5632 10:05:48.320209 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5633 10:05:48.326482 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5634 10:05:48.330034 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5635 10:05:48.333243 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5636 10:05:48.333346
5637 10:05:48.336732 CA PerBit enable=1, Macro0, CA PI delay=33
5638 10:05:48.336824
5639 10:05:48.340573 [CBTSetCACLKResult] CA Dly = 33
5640 10:05:48.340647 CS Dly: 5 (0~38)
5641 10:05:48.340719
5642 10:05:48.343070 ----->DramcWriteLeveling(PI) begin...
5643 10:05:48.343143 ==
5644 10:05:48.346679 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 10:05:48.353077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 10:05:48.353159 ==
5647 10:05:48.356469 Write leveling (Byte 0): 25 => 25
5648 10:05:48.359718 Write leveling (Byte 1): 30 => 30
5649 10:05:48.359795 DramcWriteLeveling(PI) end<-----
5650 10:05:48.363272
5651 10:05:48.363354 ==
5652 10:05:48.366459 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 10:05:48.369990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 10:05:48.370108 ==
5655 10:05:48.372938 [Gating] SW mode calibration
5656 10:05:48.380209 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5657 10:05:48.383243 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5658 10:05:48.389758 0 14 0 | B1->B0 | 2e2e 3232 | 0 0 | (1 1) (0 0)
5659 10:05:48.393140 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5660 10:05:48.396077 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5661 10:05:48.402746 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5662 10:05:48.406356 0 14 16 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
5663 10:05:48.409438 0 14 20 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
5664 10:05:48.415935 0 14 24 | B1->B0 | 3535 3434 | 1 1 | (0 1) (1 0)
5665 10:05:48.419396 0 14 28 | B1->B0 | 2f2f 3131 | 1 0 | (1 1) (0 0)
5666 10:05:48.422892 0 15 0 | B1->B0 | 2525 2424 | 0 0 | (1 0) (0 0)
5667 10:05:48.429202 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5668 10:05:48.432562 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5669 10:05:48.435927 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5670 10:05:48.442766 0 15 16 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5671 10:05:48.446401 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 10:05:48.449355 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5673 10:05:48.456455 0 15 28 | B1->B0 | 2b2b 2525 | 0 0 | (0 0) (0 0)
5674 10:05:48.459452 1 0 0 | B1->B0 | 4444 4545 | 1 0 | (0 0) (0 0)
5675 10:05:48.463062 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 10:05:48.469776 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5677 10:05:48.472813 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5678 10:05:48.476250 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 10:05:48.482927 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 10:05:48.485964 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5681 10:05:48.489684 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5682 10:05:48.496039 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5683 10:05:48.499363 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 10:05:48.502803 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 10:05:48.505993 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 10:05:48.512409 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 10:05:48.516113 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 10:05:48.519471 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 10:05:48.525961 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 10:05:48.529169 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 10:05:48.532746 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 10:05:48.539013 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 10:05:48.542508 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 10:05:48.546100 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 10:05:48.552678 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 10:05:48.555692 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5697 10:05:48.559182 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5698 10:05:48.565812 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5699 10:05:48.565898 Total UI for P1: 0, mck2ui 16
5700 10:05:48.572564 best dqsien dly found for B0: ( 1, 2, 26)
5701 10:05:48.572650 Total UI for P1: 0, mck2ui 16
5702 10:05:48.579341 best dqsien dly found for B1: ( 1, 2, 26)
5703 10:05:48.582274 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5704 10:05:48.585399 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5705 10:05:48.585484
5706 10:05:48.589100 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5707 10:05:48.592080 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5708 10:05:48.595750 [Gating] SW calibration Done
5709 10:05:48.595828 ==
5710 10:05:48.599072 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 10:05:48.602045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 10:05:48.602125 ==
5713 10:05:48.605419 RX Vref Scan: 0
5714 10:05:48.605500
5715 10:05:48.605567 RX Vref 0 -> 0, step: 1
5716 10:05:48.605628
5717 10:05:48.609145 RX Delay -80 -> 252, step: 8
5718 10:05:48.611958 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5719 10:05:48.619057 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5720 10:05:48.621946 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5721 10:05:48.625351 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5722 10:05:48.628948 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5723 10:05:48.631815 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5724 10:05:48.635308 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5725 10:05:48.642121 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5726 10:05:48.645176 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5727 10:05:48.648783 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5728 10:05:48.652031 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5729 10:05:48.655018 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5730 10:05:48.662132 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5731 10:05:48.665133 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5732 10:05:48.668810 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5733 10:05:48.671890 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5734 10:05:48.671973 ==
5735 10:05:48.675490 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 10:05:48.678354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 10:05:48.681983 ==
5738 10:05:48.682066 DQS Delay:
5739 10:05:48.682132 DQS0 = 0, DQS1 = 0
5740 10:05:48.684957 DQM Delay:
5741 10:05:48.685058 DQM0 = 96, DQM1 = 89
5742 10:05:48.688767 DQ Delay:
5743 10:05:48.688850 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =99
5744 10:05:48.691805 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5745 10:05:48.695481 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =87
5746 10:05:48.698492 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =91
5747 10:05:48.701672
5748 10:05:48.701755
5749 10:05:48.701822 ==
5750 10:05:48.705284 Dram Type= 6, Freq= 0, CH_1, rank 0
5751 10:05:48.708165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 10:05:48.708250 ==
5753 10:05:48.708317
5754 10:05:48.708378
5755 10:05:48.711566 TX Vref Scan disable
5756 10:05:48.711650 == TX Byte 0 ==
5757 10:05:48.718610 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5758 10:05:48.721585 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5759 10:05:48.721669 == TX Byte 1 ==
5760 10:05:48.727964 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5761 10:05:48.731779 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5762 10:05:48.731889 ==
5763 10:05:48.734751 Dram Type= 6, Freq= 0, CH_1, rank 0
5764 10:05:48.738343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 10:05:48.738452 ==
5766 10:05:48.738557
5767 10:05:48.738656
5768 10:05:48.741103 TX Vref Scan disable
5769 10:05:48.744486 == TX Byte 0 ==
5770 10:05:48.747944 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5771 10:05:48.751479 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5772 10:05:48.754357 == TX Byte 1 ==
5773 10:05:48.757619 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5774 10:05:48.760813 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5775 10:05:48.764284
5776 10:05:48.764391 [DATLAT]
5777 10:05:48.764493 Freq=933, CH1 RK0
5778 10:05:48.764597
5779 10:05:48.767910 DATLAT Default: 0xd
5780 10:05:48.768013 0, 0xFFFF, sum = 0
5781 10:05:48.771312 1, 0xFFFF, sum = 0
5782 10:05:48.771412 2, 0xFFFF, sum = 0
5783 10:05:48.774386 3, 0xFFFF, sum = 0
5784 10:05:48.774488 4, 0xFFFF, sum = 0
5785 10:05:48.777890 5, 0xFFFF, sum = 0
5786 10:05:48.778001 6, 0xFFFF, sum = 0
5787 10:05:48.780980 7, 0xFFFF, sum = 0
5788 10:05:48.784631 8, 0xFFFF, sum = 0
5789 10:05:48.784739 9, 0xFFFF, sum = 0
5790 10:05:48.784846 10, 0x0, sum = 1
5791 10:05:48.787725 11, 0x0, sum = 2
5792 10:05:48.787834 12, 0x0, sum = 3
5793 10:05:48.790844 13, 0x0, sum = 4
5794 10:05:48.790964 best_step = 11
5795 10:05:48.791062
5796 10:05:48.791165 ==
5797 10:05:48.794537 Dram Type= 6, Freq= 0, CH_1, rank 0
5798 10:05:48.801127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 10:05:48.801236 ==
5800 10:05:48.801329 RX Vref Scan: 1
5801 10:05:48.801420
5802 10:05:48.804110 RX Vref 0 -> 0, step: 1
5803 10:05:48.804211
5804 10:05:48.807760 RX Delay -61 -> 252, step: 4
5805 10:05:48.807862
5806 10:05:48.811270 Set Vref, RX VrefLevel [Byte0]: 60
5807 10:05:48.814012 [Byte1]: 51
5808 10:05:48.814116
5809 10:05:48.817658 Final RX Vref Byte 0 = 60 to rank0
5810 10:05:48.821112 Final RX Vref Byte 1 = 51 to rank0
5811 10:05:48.824041 Final RX Vref Byte 0 = 60 to rank1
5812 10:05:48.827622 Final RX Vref Byte 1 = 51 to rank1==
5813 10:05:48.831176 Dram Type= 6, Freq= 0, CH_1, rank 0
5814 10:05:48.833907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 10:05:48.834015 ==
5816 10:05:48.837358 DQS Delay:
5817 10:05:48.837462 DQS0 = 0, DQS1 = 0
5818 10:05:48.841014 DQM Delay:
5819 10:05:48.841102 DQM0 = 98, DQM1 = 90
5820 10:05:48.841199 DQ Delay:
5821 10:05:48.844472 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =96
5822 10:05:48.847279 DQ4 =96, DQ5 =108, DQ6 =110, DQ7 =94
5823 10:05:48.850426 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
5824 10:05:48.854107 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =92
5825 10:05:48.854202
5826 10:05:48.857072
5827 10:05:48.864066 [DQSOSCAuto] RK0, (LSB)MR18= 0x14f2, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 415 ps
5828 10:05:48.866996 CH1 RK0: MR19=504, MR18=14F2
5829 10:05:48.874192 CH1_RK0: MR19=0x504, MR18=0x14F2, DQSOSC=415, MR23=63, INC=62, DEC=41
5830 10:05:48.874304
5831 10:05:48.877241 ----->DramcWriteLeveling(PI) begin...
5832 10:05:48.877345 ==
5833 10:05:48.880461 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 10:05:48.884095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 10:05:48.884177 ==
5836 10:05:48.887142 Write leveling (Byte 0): 25 => 25
5837 10:05:48.890637 Write leveling (Byte 1): 24 => 24
5838 10:05:48.894157 DramcWriteLeveling(PI) end<-----
5839 10:05:48.894265
5840 10:05:48.894358 ==
5841 10:05:48.897272 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 10:05:48.900257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 10:05:48.900340 ==
5844 10:05:48.904021 [Gating] SW mode calibration
5845 10:05:48.910559 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5846 10:05:48.916901 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5847 10:05:48.920330 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5848 10:05:48.923867 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5849 10:05:48.930404 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5850 10:05:48.933366 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5851 10:05:48.936813 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5852 10:05:48.943205 0 14 20 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 0)
5853 10:05:48.946699 0 14 24 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (0 0)
5854 10:05:48.950115 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
5855 10:05:48.956905 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5856 10:05:48.959854 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5857 10:05:48.963393 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5858 10:05:48.969925 0 15 12 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5859 10:05:48.972957 0 15 16 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5860 10:05:48.976491 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5861 10:05:48.983323 0 15 24 | B1->B0 | 2525 3231 | 0 1 | (0 0) (0 0)
5862 10:05:48.986326 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5863 10:05:48.989922 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 10:05:48.996487 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5865 10:05:48.999628 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5866 10:05:49.003289 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 10:05:49.009967 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 10:05:49.012921 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 10:05:49.016500 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5870 10:05:49.022772 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5871 10:05:49.026536 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5872 10:05:49.029779 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 10:05:49.036221 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 10:05:49.039664 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 10:05:49.042635 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 10:05:49.049553 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 10:05:49.053006 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 10:05:49.056452 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 10:05:49.059418 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 10:05:49.066290 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 10:05:49.069506 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 10:05:49.072682 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 10:05:49.079480 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 10:05:49.083057 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 10:05:49.085945 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5886 10:05:49.092567 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5887 10:05:49.095643 Total UI for P1: 0, mck2ui 16
5888 10:05:49.099200 best dqsien dly found for B0: ( 1, 2, 24)
5889 10:05:49.102569 Total UI for P1: 0, mck2ui 16
5890 10:05:49.105522 best dqsien dly found for B1: ( 1, 2, 24)
5891 10:05:49.109242 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5892 10:05:49.112154 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5893 10:05:49.112257
5894 10:05:49.116010 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5895 10:05:49.119040 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5896 10:05:49.122318 [Gating] SW calibration Done
5897 10:05:49.122395 ==
5898 10:05:49.125709 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 10:05:49.129428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 10:05:49.129513 ==
5901 10:05:49.132350 RX Vref Scan: 0
5902 10:05:49.132451
5903 10:05:49.135888 RX Vref 0 -> 0, step: 1
5904 10:05:49.135963
5905 10:05:49.136031 RX Delay -80 -> 252, step: 8
5906 10:05:49.141967 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5907 10:05:49.145614 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5908 10:05:49.148536 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5909 10:05:49.152430 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5910 10:05:49.155483 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5911 10:05:49.158953 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5912 10:05:49.165097 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5913 10:05:49.168561 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5914 10:05:49.172117 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5915 10:05:49.174994 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5916 10:05:49.178597 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5917 10:05:49.185170 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5918 10:05:49.188803 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5919 10:05:49.192476 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5920 10:05:49.195340 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5921 10:05:49.198360 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5922 10:05:49.198437 ==
5923 10:05:49.201958 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 10:05:49.208576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 10:05:49.208658 ==
5926 10:05:49.208722 DQS Delay:
5927 10:05:49.208780 DQS0 = 0, DQS1 = 0
5928 10:05:49.211719 DQM Delay:
5929 10:05:49.211804 DQM0 = 94, DQM1 = 88
5930 10:05:49.215490 DQ Delay:
5931 10:05:49.218381 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5932 10:05:49.221588 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5933 10:05:49.225113 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5934 10:05:49.228515 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5935 10:05:49.228598
5936 10:05:49.228684
5937 10:05:49.228751 ==
5938 10:05:49.231260 Dram Type= 6, Freq= 0, CH_1, rank 1
5939 10:05:49.234767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5940 10:05:49.234842 ==
5941 10:05:49.234904
5942 10:05:49.234962
5943 10:05:49.238470 TX Vref Scan disable
5944 10:05:49.238550 == TX Byte 0 ==
5945 10:05:49.244649 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5946 10:05:49.248209 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5947 10:05:49.248300 == TX Byte 1 ==
5948 10:05:49.254595 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5949 10:05:49.257976 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5950 10:05:49.258056 ==
5951 10:05:49.261491 Dram Type= 6, Freq= 0, CH_1, rank 1
5952 10:05:49.264666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5953 10:05:49.264746 ==
5954 10:05:49.264812
5955 10:05:49.268016
5956 10:05:49.268094 TX Vref Scan disable
5957 10:05:49.271419 == TX Byte 0 ==
5958 10:05:49.274808 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5959 10:05:49.277667 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5960 10:05:49.281238 == TX Byte 1 ==
5961 10:05:49.284342 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5962 10:05:49.287819 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5963 10:05:49.291507
5964 10:05:49.291587 [DATLAT]
5965 10:05:49.291651 Freq=933, CH1 RK1
5966 10:05:49.291715
5967 10:05:49.294994 DATLAT Default: 0xb
5968 10:05:49.295068 0, 0xFFFF, sum = 0
5969 10:05:49.297919 1, 0xFFFF, sum = 0
5970 10:05:49.297990 2, 0xFFFF, sum = 0
5971 10:05:49.301514 3, 0xFFFF, sum = 0
5972 10:05:49.301590 4, 0xFFFF, sum = 0
5973 10:05:49.304621 5, 0xFFFF, sum = 0
5974 10:05:49.304695 6, 0xFFFF, sum = 0
5975 10:05:49.308279 7, 0xFFFF, sum = 0
5976 10:05:49.311587 8, 0xFFFF, sum = 0
5977 10:05:49.311662 9, 0xFFFF, sum = 0
5978 10:05:49.314516 10, 0x0, sum = 1
5979 10:05:49.314591 11, 0x0, sum = 2
5980 10:05:49.314652 12, 0x0, sum = 3
5981 10:05:49.318154 13, 0x0, sum = 4
5982 10:05:49.318226 best_step = 11
5983 10:05:49.318291
5984 10:05:49.318349 ==
5985 10:05:49.321170 Dram Type= 6, Freq= 0, CH_1, rank 1
5986 10:05:49.327854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5987 10:05:49.327933 ==
5988 10:05:49.327995 RX Vref Scan: 0
5989 10:05:49.328059
5990 10:05:49.331323 RX Vref 0 -> 0, step: 1
5991 10:05:49.331408
5992 10:05:49.334810 RX Delay -61 -> 252, step: 4
5993 10:05:49.337603 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5994 10:05:49.344641 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5995 10:05:49.347608 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5996 10:05:49.351111 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5997 10:05:49.354022 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5998 10:05:49.357480 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5999 10:05:49.360941 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
6000 10:05:49.367255 iDelay=195, Bit 7, Center 90 (3 ~ 178) 176
6001 10:05:49.370790 iDelay=195, Bit 8, Center 80 (-13 ~ 174) 188
6002 10:05:49.374284 iDelay=195, Bit 9, Center 78 (-13 ~ 170) 184
6003 10:05:49.377728 iDelay=195, Bit 10, Center 92 (-1 ~ 186) 188
6004 10:05:49.380714 iDelay=195, Bit 11, Center 82 (-9 ~ 174) 184
6005 10:05:49.387231 iDelay=195, Bit 12, Center 98 (11 ~ 186) 176
6006 10:05:49.390931 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
6007 10:05:49.394454 iDelay=195, Bit 14, Center 102 (15 ~ 190) 176
6008 10:05:49.397533 iDelay=195, Bit 15, Center 100 (11 ~ 190) 180
6009 10:05:49.397648 ==
6010 10:05:49.400592 Dram Type= 6, Freq= 0, CH_1, rank 1
6011 10:05:49.404150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6012 10:05:49.407269 ==
6013 10:05:49.407345 DQS Delay:
6014 10:05:49.407425 DQS0 = 0, DQS1 = 0
6015 10:05:49.410787 DQM Delay:
6016 10:05:49.410868 DQM0 = 95, DQM1 = 91
6017 10:05:49.414393 DQ Delay:
6018 10:05:49.414475 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
6019 10:05:49.417577 DQ4 =96, DQ5 =104, DQ6 =104, DQ7 =90
6020 10:05:49.420577 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =82
6021 10:05:49.424222 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =100
6022 10:05:49.427365
6023 10:05:49.427448
6024 10:05:49.433766 [DQSOSCAuto] RK1, (LSB)MR18= 0xa13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
6025 10:05:49.437256 CH1 RK1: MR19=505, MR18=A13
6026 10:05:49.444323 CH1_RK1: MR19=0x505, MR18=0xA13, DQSOSC=415, MR23=63, INC=62, DEC=41
6027 10:05:49.444425 [RxdqsGatingPostProcess] freq 933
6028 10:05:49.450434 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6029 10:05:49.453951 best DQS0 dly(2T, 0.5T) = (0, 10)
6030 10:05:49.457476 best DQS1 dly(2T, 0.5T) = (0, 10)
6031 10:05:49.460464 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6032 10:05:49.463945 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6033 10:05:49.467211 best DQS0 dly(2T, 0.5T) = (0, 10)
6034 10:05:49.470465 best DQS1 dly(2T, 0.5T) = (0, 10)
6035 10:05:49.474184 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6036 10:05:49.477547 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6037 10:05:49.480408 Pre-setting of DQS Precalculation
6038 10:05:49.483806 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6039 10:05:49.490416 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6040 10:05:49.497583 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6041 10:05:49.500598
6042 10:05:49.500682
6043 10:05:49.500747 [Calibration Summary] 1866 Mbps
6044 10:05:49.503681 CH 0, Rank 0
6045 10:05:49.503764 SW Impedance : PASS
6046 10:05:49.507332 DUTY Scan : NO K
6047 10:05:49.510390 ZQ Calibration : PASS
6048 10:05:49.510467 Jitter Meter : NO K
6049 10:05:49.514151 CBT Training : PASS
6050 10:05:49.516969 Write leveling : PASS
6051 10:05:49.517045 RX DQS gating : PASS
6052 10:05:49.520390 RX DQ/DQS(RDDQC) : PASS
6053 10:05:49.523415 TX DQ/DQS : PASS
6054 10:05:49.523500 RX DATLAT : PASS
6055 10:05:49.526937 RX DQ/DQS(Engine): PASS
6056 10:05:49.530648 TX OE : NO K
6057 10:05:49.530734 All Pass.
6058 10:05:49.530801
6059 10:05:49.530862 CH 0, Rank 1
6060 10:05:49.533693 SW Impedance : PASS
6061 10:05:49.537109 DUTY Scan : NO K
6062 10:05:49.537211 ZQ Calibration : PASS
6063 10:05:49.540621 Jitter Meter : NO K
6064 10:05:49.543631 CBT Training : PASS
6065 10:05:49.543715 Write leveling : PASS
6066 10:05:49.546996 RX DQS gating : PASS
6067 10:05:49.547079 RX DQ/DQS(RDDQC) : PASS
6068 10:05:49.550342 TX DQ/DQS : PASS
6069 10:05:49.553345 RX DATLAT : PASS
6070 10:05:49.553440 RX DQ/DQS(Engine): PASS
6071 10:05:49.556942 TX OE : NO K
6072 10:05:49.557026 All Pass.
6073 10:05:49.557092
6074 10:05:49.560411 CH 1, Rank 0
6075 10:05:49.560516 SW Impedance : PASS
6076 10:05:49.563638 DUTY Scan : NO K
6077 10:05:49.567091 ZQ Calibration : PASS
6078 10:05:49.567174 Jitter Meter : NO K
6079 10:05:49.570107 CBT Training : PASS
6080 10:05:49.573856 Write leveling : PASS
6081 10:05:49.573940 RX DQS gating : PASS
6082 10:05:49.576730 RX DQ/DQS(RDDQC) : PASS
6083 10:05:49.580200 TX DQ/DQS : PASS
6084 10:05:49.580325 RX DATLAT : PASS
6085 10:05:49.583642 RX DQ/DQS(Engine): PASS
6086 10:05:49.586929 TX OE : NO K
6087 10:05:49.587024 All Pass.
6088 10:05:49.587092
6089 10:05:49.587153 CH 1, Rank 1
6090 10:05:49.590580 SW Impedance : PASS
6091 10:05:49.593394 DUTY Scan : NO K
6092 10:05:49.593480 ZQ Calibration : PASS
6093 10:05:49.597134 Jitter Meter : NO K
6094 10:05:49.597254 CBT Training : PASS
6095 10:05:49.599997 Write leveling : PASS
6096 10:05:49.603550 RX DQS gating : PASS
6097 10:05:49.603629 RX DQ/DQS(RDDQC) : PASS
6098 10:05:49.606662 TX DQ/DQS : PASS
6099 10:05:49.610138 RX DATLAT : PASS
6100 10:05:49.610262 RX DQ/DQS(Engine): PASS
6101 10:05:49.613341 TX OE : NO K
6102 10:05:49.613464 All Pass.
6103 10:05:49.613556
6104 10:05:49.616951 DramC Write-DBI off
6105 10:05:49.619875 PER_BANK_REFRESH: Hybrid Mode
6106 10:05:49.619949 TX_TRACKING: ON
6107 10:05:49.630234 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6108 10:05:49.633321 [FAST_K] Save calibration result to emmc
6109 10:05:49.636832 dramc_set_vcore_voltage set vcore to 650000
6110 10:05:49.639850 Read voltage for 400, 6
6111 10:05:49.639937 Vio18 = 0
6112 10:05:49.640017 Vcore = 650000
6113 10:05:49.643233 Vdram = 0
6114 10:05:49.643317 Vddq = 0
6115 10:05:49.643396 Vmddr = 0
6116 10:05:49.650014 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6117 10:05:49.653835 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6118 10:05:49.656852 MEM_TYPE=3, freq_sel=20
6119 10:05:49.660477 sv_algorithm_assistance_LP4_800
6120 10:05:49.663239 ============ PULL DRAM RESETB DOWN ============
6121 10:05:49.666930 ========== PULL DRAM RESETB DOWN end =========
6122 10:05:49.673466 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6123 10:05:49.676472 ===================================
6124 10:05:49.679768 LPDDR4 DRAM CONFIGURATION
6125 10:05:49.679858 ===================================
6126 10:05:49.683209 EX_ROW_EN[0] = 0x0
6127 10:05:49.686742 EX_ROW_EN[1] = 0x0
6128 10:05:49.686856 LP4Y_EN = 0x0
6129 10:05:49.689681 WORK_FSP = 0x0
6130 10:05:49.689787 WL = 0x2
6131 10:05:49.693569 RL = 0x2
6132 10:05:49.693650 BL = 0x2
6133 10:05:49.696980 RPST = 0x0
6134 10:05:49.697064 RD_PRE = 0x0
6135 10:05:49.699931 WR_PRE = 0x1
6136 10:05:49.700006 WR_PST = 0x0
6137 10:05:49.703546 DBI_WR = 0x0
6138 10:05:49.703632 DBI_RD = 0x0
6139 10:05:49.707092 OTF = 0x1
6140 10:05:49.710030 ===================================
6141 10:05:49.713053 ===================================
6142 10:05:49.713127 ANA top config
6143 10:05:49.716705 ===================================
6144 10:05:49.720386 DLL_ASYNC_EN = 0
6145 10:05:49.723384 ALL_SLAVE_EN = 1
6146 10:05:49.726393 NEW_RANK_MODE = 1
6147 10:05:49.726473 DLL_IDLE_MODE = 1
6148 10:05:49.730150 LP45_APHY_COMB_EN = 1
6149 10:05:49.732956 TX_ODT_DIS = 1
6150 10:05:49.736629 NEW_8X_MODE = 1
6151 10:05:49.739541 ===================================
6152 10:05:49.743289 ===================================
6153 10:05:49.746264 data_rate = 800
6154 10:05:49.746346 CKR = 1
6155 10:05:49.749656 DQ_P2S_RATIO = 4
6156 10:05:49.753020 ===================================
6157 10:05:49.756244 CA_P2S_RATIO = 4
6158 10:05:49.759767 DQ_CA_OPEN = 0
6159 10:05:49.762852 DQ_SEMI_OPEN = 1
6160 10:05:49.766346 CA_SEMI_OPEN = 1
6161 10:05:49.766431 CA_FULL_RATE = 0
6162 10:05:49.769353 DQ_CKDIV4_EN = 0
6163 10:05:49.772980 CA_CKDIV4_EN = 1
6164 10:05:49.776175 CA_PREDIV_EN = 0
6165 10:05:49.779665 PH8_DLY = 0
6166 10:05:49.782944 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6167 10:05:49.783028 DQ_AAMCK_DIV = 0
6168 10:05:49.786412 CA_AAMCK_DIV = 0
6169 10:05:49.789327 CA_ADMCK_DIV = 4
6170 10:05:49.792749 DQ_TRACK_CA_EN = 0
6171 10:05:49.796236 CA_PICK = 800
6172 10:05:49.799884 CA_MCKIO = 400
6173 10:05:49.802747 MCKIO_SEMI = 400
6174 10:05:49.802827 PLL_FREQ = 3016
6175 10:05:49.806496 DQ_UI_PI_RATIO = 32
6176 10:05:49.809883 CA_UI_PI_RATIO = 32
6177 10:05:49.812791 ===================================
6178 10:05:49.816552 ===================================
6179 10:05:49.819463 memory_type:LPDDR4
6180 10:05:49.822577 GP_NUM : 10
6181 10:05:49.822661 SRAM_EN : 1
6182 10:05:49.825951 MD32_EN : 0
6183 10:05:49.829153 ===================================
6184 10:05:49.829233 [ANA_INIT] >>>>>>>>>>>>>>
6185 10:05:49.832795 <<<<<< [CONFIGURE PHASE]: ANA_TX
6186 10:05:49.835964 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6187 10:05:49.839384 ===================================
6188 10:05:49.842347 data_rate = 800,PCW = 0X7400
6189 10:05:49.845876 ===================================
6190 10:05:49.849083 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6191 10:05:49.856017 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6192 10:05:49.866110 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6193 10:05:49.873094 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6194 10:05:49.876164 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6195 10:05:49.879095 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6196 10:05:49.879185 [ANA_INIT] flow start
6197 10:05:49.882744 [ANA_INIT] PLL >>>>>>>>
6198 10:05:49.885787 [ANA_INIT] PLL <<<<<<<<
6199 10:05:49.885866 [ANA_INIT] MIDPI >>>>>>>>
6200 10:05:49.888984 [ANA_INIT] MIDPI <<<<<<<<
6201 10:05:49.892785 [ANA_INIT] DLL >>>>>>>>
6202 10:05:49.892898 [ANA_INIT] flow end
6203 10:05:49.899078 ============ LP4 DIFF to SE enter ============
6204 10:05:49.902413 ============ LP4 DIFF to SE exit ============
6205 10:05:49.905887 [ANA_INIT] <<<<<<<<<<<<<
6206 10:05:49.905988 [Flow] Enable top DCM control >>>>>
6207 10:05:49.908928 [Flow] Enable top DCM control <<<<<
6208 10:05:49.912498 Enable DLL master slave shuffle
6209 10:05:49.919090 ==============================================================
6210 10:05:49.922236 Gating Mode config
6211 10:05:49.925902 ==============================================================
6212 10:05:49.929412 Config description:
6213 10:05:49.939010 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6214 10:05:49.945552 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6215 10:05:49.948698 SELPH_MODE 0: By rank 1: By Phase
6216 10:05:49.955353 ==============================================================
6217 10:05:49.959139 GAT_TRACK_EN = 0
6218 10:05:49.961995 RX_GATING_MODE = 2
6219 10:05:49.965505 RX_GATING_TRACK_MODE = 2
6220 10:05:49.965590 SELPH_MODE = 1
6221 10:05:49.968943 PICG_EARLY_EN = 1
6222 10:05:49.971968 VALID_LAT_VALUE = 1
6223 10:05:49.978838 ==============================================================
6224 10:05:49.982306 Enter into Gating configuration >>>>
6225 10:05:49.985447 Exit from Gating configuration <<<<
6226 10:05:49.988464 Enter into DVFS_PRE_config >>>>>
6227 10:05:49.998884 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6228 10:05:50.001801 Exit from DVFS_PRE_config <<<<<
6229 10:05:50.005302 Enter into PICG configuration >>>>
6230 10:05:50.008842 Exit from PICG configuration <<<<
6231 10:05:50.011708 [RX_INPUT] configuration >>>>>
6232 10:05:50.015329 [RX_INPUT] configuration <<<<<
6233 10:05:50.018740 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6234 10:05:50.025413 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6235 10:05:50.032174 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6236 10:05:50.038162 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6237 10:05:50.044983 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6238 10:05:50.048597 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6239 10:05:50.055296 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6240 10:05:50.058218 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6241 10:05:50.061647 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6242 10:05:50.064825 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6243 10:05:50.071563 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6244 10:05:50.075241 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6245 10:05:50.078000 ===================================
6246 10:05:50.081579 LPDDR4 DRAM CONFIGURATION
6247 10:05:50.085119 ===================================
6248 10:05:50.085206 EX_ROW_EN[0] = 0x0
6249 10:05:50.088126 EX_ROW_EN[1] = 0x0
6250 10:05:50.088213 LP4Y_EN = 0x0
6251 10:05:50.091267 WORK_FSP = 0x0
6252 10:05:50.091395 WL = 0x2
6253 10:05:50.094858 RL = 0x2
6254 10:05:50.094950 BL = 0x2
6255 10:05:50.097718 RPST = 0x0
6256 10:05:50.097794 RD_PRE = 0x0
6257 10:05:50.101279 WR_PRE = 0x1
6258 10:05:50.104764 WR_PST = 0x0
6259 10:05:50.104844 DBI_WR = 0x0
6260 10:05:50.107646 DBI_RD = 0x0
6261 10:05:50.107723 OTF = 0x1
6262 10:05:50.111057 ===================================
6263 10:05:50.114698 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6264 10:05:50.117846 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6265 10:05:50.124395 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6266 10:05:50.127932 ===================================
6267 10:05:50.131445 LPDDR4 DRAM CONFIGURATION
6268 10:05:50.134443 ===================================
6269 10:05:50.134522 EX_ROW_EN[0] = 0x10
6270 10:05:50.137677 EX_ROW_EN[1] = 0x0
6271 10:05:50.137762 LP4Y_EN = 0x0
6272 10:05:50.141156 WORK_FSP = 0x0
6273 10:05:50.141234 WL = 0x2
6274 10:05:50.144334 RL = 0x2
6275 10:05:50.144414 BL = 0x2
6276 10:05:50.147777 RPST = 0x0
6277 10:05:50.147879 RD_PRE = 0x0
6278 10:05:50.151365 WR_PRE = 0x1
6279 10:05:50.151448 WR_PST = 0x0
6280 10:05:50.154176 DBI_WR = 0x0
6281 10:05:50.154255 DBI_RD = 0x0
6282 10:05:50.157698 OTF = 0x1
6283 10:05:50.161385 ===================================
6284 10:05:50.167623 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6285 10:05:50.171042 nWR fixed to 30
6286 10:05:50.174385 [ModeRegInit_LP4] CH0 RK0
6287 10:05:50.174471 [ModeRegInit_LP4] CH0 RK1
6288 10:05:50.177992 [ModeRegInit_LP4] CH1 RK0
6289 10:05:50.181007 [ModeRegInit_LP4] CH1 RK1
6290 10:05:50.181091 match AC timing 19
6291 10:05:50.187612 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6292 10:05:50.190779 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6293 10:05:50.194401 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6294 10:05:50.200901 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6295 10:05:50.204381 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6296 10:05:50.204471 ==
6297 10:05:50.207826 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 10:05:50.211231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 10:05:50.211366 ==
6300 10:05:50.217779 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6301 10:05:50.224279 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6302 10:05:50.227755 [CA 0] Center 36 (8~64) winsize 57
6303 10:05:50.230793 [CA 1] Center 36 (8~64) winsize 57
6304 10:05:50.234318 [CA 2] Center 36 (8~64) winsize 57
6305 10:05:50.237310 [CA 3] Center 36 (8~64) winsize 57
6306 10:05:50.237421 [CA 4] Center 36 (8~64) winsize 57
6307 10:05:50.241092 [CA 5] Center 36 (8~64) winsize 57
6308 10:05:50.241181
6309 10:05:50.247979 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6310 10:05:50.248054
6311 10:05:50.250387 [CATrainingPosCal] consider 1 rank data
6312 10:05:50.254132 u2DelayCellTimex100 = 270/100 ps
6313 10:05:50.257069 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 10:05:50.260701 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 10:05:50.264364 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 10:05:50.267383 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 10:05:50.270855 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 10:05:50.273647 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 10:05:50.273727
6320 10:05:50.277440 CA PerBit enable=1, Macro0, CA PI delay=36
6321 10:05:50.277523
6322 10:05:50.280423 [CBTSetCACLKResult] CA Dly = 36
6323 10:05:50.283926 CS Dly: 1 (0~32)
6324 10:05:50.284002 ==
6325 10:05:50.287298 Dram Type= 6, Freq= 0, CH_0, rank 1
6326 10:05:50.290332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 10:05:50.290420 ==
6328 10:05:50.297115 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6329 10:05:50.303536 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6330 10:05:50.303621 [CA 0] Center 36 (8~64) winsize 57
6331 10:05:50.307069 [CA 1] Center 36 (8~64) winsize 57
6332 10:05:50.310562 [CA 2] Center 36 (8~64) winsize 57
6333 10:05:50.313307 [CA 3] Center 36 (8~64) winsize 57
6334 10:05:50.317010 [CA 4] Center 36 (8~64) winsize 57
6335 10:05:50.320523 [CA 5] Center 36 (8~64) winsize 57
6336 10:05:50.320599
6337 10:05:50.323604 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6338 10:05:50.323680
6339 10:05:50.326748 [CATrainingPosCal] consider 2 rank data
6340 10:05:50.330115 u2DelayCellTimex100 = 270/100 ps
6341 10:05:50.333620 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 10:05:50.337256 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6343 10:05:50.343361 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6344 10:05:50.346952 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6345 10:05:50.349912 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 10:05:50.353556 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 10:05:50.353706
6348 10:05:50.356723 CA PerBit enable=1, Macro0, CA PI delay=36
6349 10:05:50.356867
6350 10:05:50.360263 [CBTSetCACLKResult] CA Dly = 36
6351 10:05:50.360410 CS Dly: 1 (0~32)
6352 10:05:50.360539
6353 10:05:50.363411 ----->DramcWriteLeveling(PI) begin...
6354 10:05:50.367028 ==
6355 10:05:50.369937 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 10:05:50.373529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 10:05:50.373625 ==
6358 10:05:50.376726 Write leveling (Byte 0): 40 => 8
6359 10:05:50.380232 Write leveling (Byte 1): 32 => 0
6360 10:05:50.383698 DramcWriteLeveling(PI) end<-----
6361 10:05:50.383783
6362 10:05:50.383847 ==
6363 10:05:50.387128 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 10:05:50.390188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 10:05:50.390271 ==
6366 10:05:50.393665 [Gating] SW mode calibration
6367 10:05:50.399999 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6368 10:05:50.403503 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6369 10:05:50.410005 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6370 10:05:50.413489 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6371 10:05:50.417122 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6372 10:05:50.423793 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6373 10:05:50.426812 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6374 10:05:50.429962 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6375 10:05:50.436751 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6376 10:05:50.439769 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6377 10:05:50.443258 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6378 10:05:50.446224 Total UI for P1: 0, mck2ui 16
6379 10:05:50.449940 best dqsien dly found for B0: ( 0, 14, 24)
6380 10:05:50.453572 Total UI for P1: 0, mck2ui 16
6381 10:05:50.456604 best dqsien dly found for B1: ( 0, 14, 24)
6382 10:05:50.459653 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6383 10:05:50.463307 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6384 10:05:50.463412
6385 10:05:50.469923 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6386 10:05:50.473224 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6387 10:05:50.476701 [Gating] SW calibration Done
6388 10:05:50.476786 ==
6389 10:05:50.479494 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 10:05:50.483132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 10:05:50.483251 ==
6392 10:05:50.483345 RX Vref Scan: 0
6393 10:05:50.483421
6394 10:05:50.486569 RX Vref 0 -> 0, step: 1
6395 10:05:50.486697
6396 10:05:50.489469 RX Delay -410 -> 252, step: 16
6397 10:05:50.493044 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6398 10:05:50.499276 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6399 10:05:50.502923 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6400 10:05:50.505990 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6401 10:05:50.509555 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6402 10:05:50.515871 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6403 10:05:50.519250 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6404 10:05:50.522617 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6405 10:05:50.526093 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6406 10:05:50.532449 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6407 10:05:50.536166 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6408 10:05:50.538975 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6409 10:05:50.542277 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6410 10:05:50.548969 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6411 10:05:50.552582 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6412 10:05:50.555666 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6413 10:05:50.555741 ==
6414 10:05:50.559284 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 10:05:50.565987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 10:05:50.566098 ==
6417 10:05:50.566190 DQS Delay:
6418 10:05:50.569534 DQS0 = 35, DQS1 = 51
6419 10:05:50.569619 DQM Delay:
6420 10:05:50.569699 DQM0 = 6, DQM1 = 10
6421 10:05:50.572576 DQ Delay:
6422 10:05:50.576195 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6423 10:05:50.576269 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6424 10:05:50.579385 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6425 10:05:50.582314 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6426 10:05:50.582414
6427 10:05:50.582509
6428 10:05:50.586263 ==
6429 10:05:50.586364 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 10:05:50.592440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 10:05:50.592546 ==
6432 10:05:50.592646
6433 10:05:50.592740
6434 10:05:50.595950 TX Vref Scan disable
6435 10:05:50.596055 == TX Byte 0 ==
6436 10:05:50.599309 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6437 10:05:50.605638 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6438 10:05:50.605753 == TX Byte 1 ==
6439 10:05:50.609162 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6440 10:05:50.615717 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6441 10:05:50.615828 ==
6442 10:05:50.618603 Dram Type= 6, Freq= 0, CH_0, rank 0
6443 10:05:50.622299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 10:05:50.622402 ==
6445 10:05:50.622501
6446 10:05:50.622589
6447 10:05:50.625655 TX Vref Scan disable
6448 10:05:50.625729 == TX Byte 0 ==
6449 10:05:50.629040 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6450 10:05:50.635296 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6451 10:05:50.635417 == TX Byte 1 ==
6452 10:05:50.638500 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6453 10:05:50.645225 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6454 10:05:50.645306
6455 10:05:50.645378 [DATLAT]
6456 10:05:50.648768 Freq=400, CH0 RK0
6457 10:05:50.648842
6458 10:05:50.648905 DATLAT Default: 0xf
6459 10:05:50.651713 0, 0xFFFF, sum = 0
6460 10:05:50.651788 1, 0xFFFF, sum = 0
6461 10:05:50.655426 2, 0xFFFF, sum = 0
6462 10:05:50.655535 3, 0xFFFF, sum = 0
6463 10:05:50.658584 4, 0xFFFF, sum = 0
6464 10:05:50.658686 5, 0xFFFF, sum = 0
6465 10:05:50.662131 6, 0xFFFF, sum = 0
6466 10:05:50.662252 7, 0xFFFF, sum = 0
6467 10:05:50.665270 8, 0xFFFF, sum = 0
6468 10:05:50.665379 9, 0xFFFF, sum = 0
6469 10:05:50.668245 10, 0xFFFF, sum = 0
6470 10:05:50.668365 11, 0xFFFF, sum = 0
6471 10:05:50.671923 12, 0xFFFF, sum = 0
6472 10:05:50.672031 13, 0x0, sum = 1
6473 10:05:50.675375 14, 0x0, sum = 2
6474 10:05:50.675448 15, 0x0, sum = 3
6475 10:05:50.678529 16, 0x0, sum = 4
6476 10:05:50.678616 best_step = 14
6477 10:05:50.678705
6478 10:05:50.678804 ==
6479 10:05:50.682092 Dram Type= 6, Freq= 0, CH_0, rank 0
6480 10:05:50.688498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 10:05:50.688613 ==
6482 10:05:50.688712 RX Vref Scan: 1
6483 10:05:50.688802
6484 10:05:50.691440 RX Vref 0 -> 0, step: 1
6485 10:05:50.691518
6486 10:05:50.694854 RX Delay -343 -> 252, step: 8
6487 10:05:50.694968
6488 10:05:50.698157 Set Vref, RX VrefLevel [Byte0]: 54
6489 10:05:50.701516 [Byte1]: 51
6490 10:05:50.704590
6491 10:05:50.704691 Final RX Vref Byte 0 = 54 to rank0
6492 10:05:50.708166 Final RX Vref Byte 1 = 51 to rank0
6493 10:05:50.711597 Final RX Vref Byte 0 = 54 to rank1
6494 10:05:50.714651 Final RX Vref Byte 1 = 51 to rank1==
6495 10:05:50.718405 Dram Type= 6, Freq= 0, CH_0, rank 0
6496 10:05:50.724983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 10:05:50.725113 ==
6498 10:05:50.725201 DQS Delay:
6499 10:05:50.728276 DQS0 = 44, DQS1 = 60
6500 10:05:50.728397 DQM Delay:
6501 10:05:50.728490 DQM0 = 11, DQM1 = 15
6502 10:05:50.731381 DQ Delay:
6503 10:05:50.734733 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6504 10:05:50.734847 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6505 10:05:50.738048 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6506 10:05:50.741319 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6507 10:05:50.744548
6508 10:05:50.744635
6509 10:05:50.751598 [DQSOSCAuto] RK0, (LSB)MR18= 0x8352, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6510 10:05:50.754427 CH0 RK0: MR19=C0C, MR18=8352
6511 10:05:50.761081 CH0_RK0: MR19=0xC0C, MR18=0x8352, DQSOSC=393, MR23=63, INC=382, DEC=254
6512 10:05:50.761188 ==
6513 10:05:50.764818 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 10:05:50.767826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 10:05:50.767900 ==
6516 10:05:50.771555 [Gating] SW mode calibration
6517 10:05:50.777540 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6518 10:05:50.784265 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6519 10:05:50.787649 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6520 10:05:50.790874 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6521 10:05:50.797938 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6522 10:05:50.800707 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6523 10:05:50.804122 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6524 10:05:50.811089 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6525 10:05:50.814596 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6526 10:05:50.817589 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6527 10:05:50.821283 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6528 10:05:50.824288 Total UI for P1: 0, mck2ui 16
6529 10:05:50.827791 best dqsien dly found for B0: ( 0, 14, 24)
6530 10:05:50.830623 Total UI for P1: 0, mck2ui 16
6531 10:05:50.834267 best dqsien dly found for B1: ( 0, 14, 24)
6532 10:05:50.837487 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6533 10:05:50.844423 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6534 10:05:50.844559
6535 10:05:50.847826 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6536 10:05:50.850871 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6537 10:05:50.854482 [Gating] SW calibration Done
6538 10:05:50.854568 ==
6539 10:05:50.857512 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 10:05:50.860932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 10:05:50.861093 ==
6542 10:05:50.861203 RX Vref Scan: 0
6543 10:05:50.864243
6544 10:05:50.864357 RX Vref 0 -> 0, step: 1
6545 10:05:50.864460
6546 10:05:50.867501 RX Delay -410 -> 252, step: 16
6547 10:05:50.871092 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6548 10:05:50.877318 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6549 10:05:50.880977 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6550 10:05:50.883829 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6551 10:05:50.887442 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6552 10:05:50.894309 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6553 10:05:50.897199 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6554 10:05:50.900629 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6555 10:05:50.904002 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6556 10:05:50.910344 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6557 10:05:50.914292 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6558 10:05:50.917274 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6559 10:05:50.920635 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6560 10:05:50.927284 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6561 10:05:50.930636 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6562 10:05:50.933750 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6563 10:05:50.933847 ==
6564 10:05:50.937234 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 10:05:50.944058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 10:05:50.944154 ==
6567 10:05:50.944261 DQS Delay:
6568 10:05:50.947066 DQS0 = 35, DQS1 = 51
6569 10:05:50.947153 DQM Delay:
6570 10:05:50.947255 DQM0 = 6, DQM1 = 10
6571 10:05:50.950321 DQ Delay:
6572 10:05:50.953560 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6573 10:05:50.953646 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6574 10:05:50.956959 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6575 10:05:50.960500 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6576 10:05:50.960586
6577 10:05:50.960672
6578 10:05:50.963572 ==
6579 10:05:50.967214 Dram Type= 6, Freq= 0, CH_0, rank 1
6580 10:05:50.970227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 10:05:50.970314 ==
6582 10:05:50.970400
6583 10:05:50.970480
6584 10:05:50.973968 TX Vref Scan disable
6585 10:05:50.974054 == TX Byte 0 ==
6586 10:05:50.976898 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6587 10:05:50.983608 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6588 10:05:50.983698 == TX Byte 1 ==
6589 10:05:50.986560 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6590 10:05:50.993364 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6591 10:05:50.993456 ==
6592 10:05:50.996957 Dram Type= 6, Freq= 0, CH_0, rank 1
6593 10:05:51.000272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 10:05:51.000357 ==
6595 10:05:51.000448
6596 10:05:51.000512
6597 10:05:51.003540 TX Vref Scan disable
6598 10:05:51.003617 == TX Byte 0 ==
6599 10:05:51.006440 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6600 10:05:51.013376 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6601 10:05:51.013500 == TX Byte 1 ==
6602 10:05:51.016491 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6603 10:05:51.023242 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6604 10:05:51.023361
6605 10:05:51.023461 [DATLAT]
6606 10:05:51.023549 Freq=400, CH0 RK1
6607 10:05:51.026700
6608 10:05:51.026809 DATLAT Default: 0xe
6609 10:05:51.029683 0, 0xFFFF, sum = 0
6610 10:05:51.029792 1, 0xFFFF, sum = 0
6611 10:05:51.033156 2, 0xFFFF, sum = 0
6612 10:05:51.033265 3, 0xFFFF, sum = 0
6613 10:05:51.036712 4, 0xFFFF, sum = 0
6614 10:05:51.036819 5, 0xFFFF, sum = 0
6615 10:05:51.039527 6, 0xFFFF, sum = 0
6616 10:05:51.039637 7, 0xFFFF, sum = 0
6617 10:05:51.042940 8, 0xFFFF, sum = 0
6618 10:05:51.043050 9, 0xFFFF, sum = 0
6619 10:05:51.046497 10, 0xFFFF, sum = 0
6620 10:05:51.046612 11, 0xFFFF, sum = 0
6621 10:05:51.049475 12, 0xFFFF, sum = 0
6622 10:05:51.049583 13, 0x0, sum = 1
6623 10:05:51.053095 14, 0x0, sum = 2
6624 10:05:51.053203 15, 0x0, sum = 3
6625 10:05:51.056020 16, 0x0, sum = 4
6626 10:05:51.056129 best_step = 14
6627 10:05:51.056220
6628 10:05:51.056292 ==
6629 10:05:51.059619 Dram Type= 6, Freq= 0, CH_0, rank 1
6630 10:05:51.066309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 10:05:51.066425 ==
6632 10:05:51.066520 RX Vref Scan: 0
6633 10:05:51.066622
6634 10:05:51.069773 RX Vref 0 -> 0, step: 1
6635 10:05:51.069883
6636 10:05:51.072945 RX Delay -343 -> 252, step: 8
6637 10:05:51.079661 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6638 10:05:51.082680 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6639 10:05:51.086351 iDelay=217, Bit 2, Center -36 (-279 ~ 208) 488
6640 10:05:51.089230 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6641 10:05:51.096298 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6642 10:05:51.099569 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6643 10:05:51.103033 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6644 10:05:51.106489 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6645 10:05:51.112869 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6646 10:05:51.116361 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6647 10:05:51.119555 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6648 10:05:51.122559 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6649 10:05:51.129069 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6650 10:05:51.132854 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6651 10:05:51.136343 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6652 10:05:51.139157 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6653 10:05:51.143101 ==
6654 10:05:51.146102 Dram Type= 6, Freq= 0, CH_0, rank 1
6655 10:05:51.148952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 10:05:51.149065 ==
6657 10:05:51.149165 DQS Delay:
6658 10:05:51.152304 DQS0 = 48, DQS1 = 60
6659 10:05:51.152418 DQM Delay:
6660 10:05:51.155637 DQM0 = 13, DQM1 = 14
6661 10:05:51.155744 DQ Delay:
6662 10:05:51.159120 DQ0 =12, DQ1 =12, DQ2 =12, DQ3 =12
6663 10:05:51.162728 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6664 10:05:51.165526 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =4
6665 10:05:51.169175 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6666 10:05:51.169284
6667 10:05:51.169377
6668 10:05:51.175359 [DQSOSCAuto] RK1, (LSB)MR18= 0x9467, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6669 10:05:51.179082 CH0 RK1: MR19=C0C, MR18=9467
6670 10:05:51.185590 CH0_RK1: MR19=0xC0C, MR18=0x9467, DQSOSC=391, MR23=63, INC=386, DEC=257
6671 10:05:51.189196 [RxdqsGatingPostProcess] freq 400
6672 10:05:51.195749 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6673 10:05:51.195842 best DQS0 dly(2T, 0.5T) = (0, 10)
6674 10:05:51.199242 best DQS1 dly(2T, 0.5T) = (0, 10)
6675 10:05:51.202218 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6676 10:05:51.205796 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6677 10:05:51.209048 best DQS0 dly(2T, 0.5T) = (0, 10)
6678 10:05:51.212320 best DQS1 dly(2T, 0.5T) = (0, 10)
6679 10:05:51.215803 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6680 10:05:51.218604 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6681 10:05:51.222070 Pre-setting of DQS Precalculation
6682 10:05:51.228597 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6683 10:05:51.228690 ==
6684 10:05:51.232052 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 10:05:51.235651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 10:05:51.235799 ==
6687 10:05:51.241655 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6688 10:05:51.245249 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6689 10:05:51.248323 [CA 0] Center 36 (8~64) winsize 57
6690 10:05:51.251763 [CA 1] Center 36 (8~64) winsize 57
6691 10:05:51.255202 [CA 2] Center 36 (8~64) winsize 57
6692 10:05:51.258645 [CA 3] Center 36 (8~64) winsize 57
6693 10:05:51.261486 [CA 4] Center 36 (8~64) winsize 57
6694 10:05:51.265094 [CA 5] Center 36 (8~64) winsize 57
6695 10:05:51.265180
6696 10:05:51.268098 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6697 10:05:51.268182
6698 10:05:51.271577 [CATrainingPosCal] consider 1 rank data
6699 10:05:51.275057 u2DelayCellTimex100 = 270/100 ps
6700 10:05:51.278609 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 10:05:51.281502 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 10:05:51.285363 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 10:05:51.291396 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 10:05:51.295146 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 10:05:51.297912 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 10:05:51.297995
6707 10:05:51.301441 CA PerBit enable=1, Macro0, CA PI delay=36
6708 10:05:51.301521
6709 10:05:51.305098 [CBTSetCACLKResult] CA Dly = 36
6710 10:05:51.305178 CS Dly: 1 (0~32)
6711 10:05:51.305254 ==
6712 10:05:51.308026 Dram Type= 6, Freq= 0, CH_1, rank 1
6713 10:05:51.315206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 10:05:51.315288 ==
6715 10:05:51.317988 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6716 10:05:51.325139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6717 10:05:51.327941 [CA 0] Center 36 (8~64) winsize 57
6718 10:05:51.331542 [CA 1] Center 36 (8~64) winsize 57
6719 10:05:51.335073 [CA 2] Center 36 (8~64) winsize 57
6720 10:05:51.337812 [CA 3] Center 36 (8~64) winsize 57
6721 10:05:51.341502 [CA 4] Center 36 (8~64) winsize 57
6722 10:05:51.344502 [CA 5] Center 36 (8~64) winsize 57
6723 10:05:51.344617
6724 10:05:51.347927 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6725 10:05:51.348017
6726 10:05:51.351568 [CATrainingPosCal] consider 2 rank data
6727 10:05:51.354355 u2DelayCellTimex100 = 270/100 ps
6728 10:05:51.357950 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 10:05:51.361369 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6730 10:05:51.364494 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6731 10:05:51.368069 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6732 10:05:51.371078 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 10:05:51.374212 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 10:05:51.377543
6735 10:05:51.381252 CA PerBit enable=1, Macro0, CA PI delay=36
6736 10:05:51.381358
6737 10:05:51.384148 [CBTSetCACLKResult] CA Dly = 36
6738 10:05:51.384244 CS Dly: 1 (0~32)
6739 10:05:51.384350
6740 10:05:51.387798 ----->DramcWriteLeveling(PI) begin...
6741 10:05:51.387882 ==
6742 10:05:51.390788 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 10:05:51.394475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 10:05:51.397744 ==
6745 10:05:51.397835 Write leveling (Byte 0): 40 => 8
6746 10:05:51.401065 Write leveling (Byte 1): 40 => 8
6747 10:05:51.404090 DramcWriteLeveling(PI) end<-----
6748 10:05:51.404170
6749 10:05:51.404234 ==
6750 10:05:51.407615 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 10:05:51.414326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 10:05:51.414433 ==
6753 10:05:51.414526 [Gating] SW mode calibration
6754 10:05:51.424513 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6755 10:05:51.427652 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6756 10:05:51.431050 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6757 10:05:51.437692 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6758 10:05:51.440996 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6759 10:05:51.443965 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6760 10:05:51.450700 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6761 10:05:51.454116 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6762 10:05:51.457527 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6763 10:05:51.464391 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6764 10:05:51.467818 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6765 10:05:51.470567 Total UI for P1: 0, mck2ui 16
6766 10:05:51.474251 best dqsien dly found for B0: ( 0, 14, 24)
6767 10:05:51.477736 Total UI for P1: 0, mck2ui 16
6768 10:05:51.480596 best dqsien dly found for B1: ( 0, 14, 24)
6769 10:05:51.483787 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6770 10:05:51.487487 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6771 10:05:51.487564
6772 10:05:51.490414 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6773 10:05:51.494066 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6774 10:05:51.497097 [Gating] SW calibration Done
6775 10:05:51.497181 ==
6776 10:05:51.500674 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 10:05:51.506920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 10:05:51.507035 ==
6779 10:05:51.507139 RX Vref Scan: 0
6780 10:05:51.507231
6781 10:05:51.510447 RX Vref 0 -> 0, step: 1
6782 10:05:51.510544
6783 10:05:51.514158 RX Delay -410 -> 252, step: 16
6784 10:05:51.517055 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6785 10:05:51.520170 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6786 10:05:51.527043 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6787 10:05:51.530059 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6788 10:05:51.533500 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6789 10:05:51.536930 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6790 10:05:51.543956 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6791 10:05:51.547017 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6792 10:05:51.550029 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6793 10:05:51.553559 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6794 10:05:51.560685 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6795 10:05:51.563480 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6796 10:05:51.567044 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6797 10:05:51.570266 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6798 10:05:51.576957 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6799 10:05:51.579967 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6800 10:05:51.580057 ==
6801 10:05:51.583228 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 10:05:51.586854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 10:05:51.586962 ==
6804 10:05:51.590388 DQS Delay:
6805 10:05:51.590483 DQS0 = 51, DQS1 = 59
6806 10:05:51.590595 DQM Delay:
6807 10:05:51.593554 DQM0 = 18, DQM1 = 16
6808 10:05:51.593640 DQ Delay:
6809 10:05:51.596704 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6810 10:05:51.600326 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6811 10:05:51.603359 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6812 10:05:51.606917 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6813 10:05:51.607021
6814 10:05:51.607118
6815 10:05:51.607208 ==
6816 10:05:51.610506 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 10:05:51.617122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 10:05:51.617203 ==
6819 10:05:51.617276
6820 10:05:51.617337
6821 10:05:51.617395 TX Vref Scan disable
6822 10:05:51.620029 == TX Byte 0 ==
6823 10:05:51.623352 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6824 10:05:51.626632 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6825 10:05:51.630069 == TX Byte 1 ==
6826 10:05:51.633638 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6827 10:05:51.636976 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6828 10:05:51.637055 ==
6829 10:05:51.639850 Dram Type= 6, Freq= 0, CH_1, rank 0
6830 10:05:51.646988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 10:05:51.647071 ==
6832 10:05:51.647136
6833 10:05:51.647204
6834 10:05:51.647262 TX Vref Scan disable
6835 10:05:51.649717 == TX Byte 0 ==
6836 10:05:51.653398 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6837 10:05:51.656552 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6838 10:05:51.660060 == TX Byte 1 ==
6839 10:05:51.663656 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6840 10:05:51.666329 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6841 10:05:51.666435
6842 10:05:51.669728 [DATLAT]
6843 10:05:51.669834 Freq=400, CH1 RK0
6844 10:05:51.669930
6845 10:05:51.673152 DATLAT Default: 0xf
6846 10:05:51.673263 0, 0xFFFF, sum = 0
6847 10:05:51.676505 1, 0xFFFF, sum = 0
6848 10:05:51.676614 2, 0xFFFF, sum = 0
6849 10:05:51.680056 3, 0xFFFF, sum = 0
6850 10:05:51.680159 4, 0xFFFF, sum = 0
6851 10:05:51.683686 5, 0xFFFF, sum = 0
6852 10:05:51.683789 6, 0xFFFF, sum = 0
6853 10:05:51.686558 7, 0xFFFF, sum = 0
6854 10:05:51.686659 8, 0xFFFF, sum = 0
6855 10:05:51.689938 9, 0xFFFF, sum = 0
6856 10:05:51.690039 10, 0xFFFF, sum = 0
6857 10:05:51.693213 11, 0xFFFF, sum = 0
6858 10:05:51.696793 12, 0xFFFF, sum = 0
6859 10:05:51.696903 13, 0x0, sum = 1
6860 10:05:51.699611 14, 0x0, sum = 2
6861 10:05:51.699713 15, 0x0, sum = 3
6862 10:05:51.699809 16, 0x0, sum = 4
6863 10:05:51.703385 best_step = 14
6864 10:05:51.703484
6865 10:05:51.703573 ==
6866 10:05:51.706295 Dram Type= 6, Freq= 0, CH_1, rank 0
6867 10:05:51.709602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 10:05:51.709701 ==
6869 10:05:51.713265 RX Vref Scan: 1
6870 10:05:51.713362
6871 10:05:51.713456 RX Vref 0 -> 0, step: 1
6872 10:05:51.716325
6873 10:05:51.716429 RX Delay -359 -> 252, step: 8
6874 10:05:51.716519
6875 10:05:51.719481 Set Vref, RX VrefLevel [Byte0]: 60
6876 10:05:51.723053 [Byte1]: 51
6877 10:05:51.728179
6878 10:05:51.728282 Final RX Vref Byte 0 = 60 to rank0
6879 10:05:51.731469 Final RX Vref Byte 1 = 51 to rank0
6880 10:05:51.735144 Final RX Vref Byte 0 = 60 to rank1
6881 10:05:51.738094 Final RX Vref Byte 1 = 51 to rank1==
6882 10:05:51.741692 Dram Type= 6, Freq= 0, CH_1, rank 0
6883 10:05:51.748251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 10:05:51.748365 ==
6885 10:05:51.748461 DQS Delay:
6886 10:05:51.751617 DQS0 = 48, DQS1 = 60
6887 10:05:51.751725 DQM Delay:
6888 10:05:51.751818 DQM0 = 12, DQM1 = 12
6889 10:05:51.754981 DQ Delay:
6890 10:05:51.757989 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6891 10:05:51.758093 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =12
6892 10:05:51.760976 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6893 10:05:51.764592 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6894 10:05:51.764694
6895 10:05:51.767940
6896 10:05:51.774452 [DQSOSCAuto] RK0, (LSB)MR18= 0x852d, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6897 10:05:51.777741 CH1 RK0: MR19=C0C, MR18=852D
6898 10:05:51.784546 CH1_RK0: MR19=0xC0C, MR18=0x852D, DQSOSC=393, MR23=63, INC=382, DEC=254
6899 10:05:51.784654 ==
6900 10:05:51.787543 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 10:05:51.790993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 10:05:51.791094 ==
6903 10:05:51.794607 [Gating] SW mode calibration
6904 10:05:51.800710 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6905 10:05:51.807978 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6906 10:05:51.810942 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6907 10:05:51.814133 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6908 10:05:51.820674 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6909 10:05:51.824335 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6910 10:05:51.827740 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6911 10:05:51.834488 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6912 10:05:51.837580 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6913 10:05:51.841123 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6914 10:05:51.847640 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6915 10:05:51.847735 Total UI for P1: 0, mck2ui 16
6916 10:05:51.850597 best dqsien dly found for B0: ( 0, 14, 24)
6917 10:05:51.854084 Total UI for P1: 0, mck2ui 16
6918 10:05:51.857347 best dqsien dly found for B1: ( 0, 14, 24)
6919 10:05:51.864177 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6920 10:05:51.867237 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6921 10:05:51.867345
6922 10:05:51.870550 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6923 10:05:51.874082 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6924 10:05:51.877380 [Gating] SW calibration Done
6925 10:05:51.877462 ==
6926 10:05:51.880773 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 10:05:51.883746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 10:05:51.883893 ==
6929 10:05:51.887234 RX Vref Scan: 0
6930 10:05:51.887354
6931 10:05:51.887481 RX Vref 0 -> 0, step: 1
6932 10:05:51.887569
6933 10:05:51.890950 RX Delay -410 -> 252, step: 16
6934 10:05:51.893988 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6935 10:05:51.900814 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6936 10:05:51.903899 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6937 10:05:51.907249 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6938 10:05:51.910473 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6939 10:05:51.917447 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6940 10:05:51.920556 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6941 10:05:51.924276 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6942 10:05:51.927241 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6943 10:05:51.933719 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6944 10:05:51.937419 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6945 10:05:51.940423 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6946 10:05:51.946975 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6947 10:05:51.950596 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6948 10:05:51.953583 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6949 10:05:51.957141 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6950 10:05:51.957241 ==
6951 10:05:51.960611 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 10:05:51.966832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 10:05:51.966915 ==
6954 10:05:51.966981 DQS Delay:
6955 10:05:51.970228 DQS0 = 51, DQS1 = 59
6956 10:05:51.970309 DQM Delay:
6957 10:05:51.970411 DQM0 = 18, DQM1 = 19
6958 10:05:51.973610 DQ Delay:
6959 10:05:51.977207 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6960 10:05:51.980096 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6961 10:05:51.983389 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6962 10:05:51.986987 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6963 10:05:51.987068
6964 10:05:51.987132
6965 10:05:51.987191 ==
6966 10:05:51.990466 Dram Type= 6, Freq= 0, CH_1, rank 1
6967 10:05:51.993406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6968 10:05:51.993488 ==
6969 10:05:51.993552
6970 10:05:51.993611
6971 10:05:51.996931 TX Vref Scan disable
6972 10:05:51.997044 == TX Byte 0 ==
6973 10:05:52.003577 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6974 10:05:52.006613 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6975 10:05:52.006694 == TX Byte 1 ==
6976 10:05:52.010227 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6977 10:05:52.016823 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6978 10:05:52.016935 ==
6979 10:05:52.020000 Dram Type= 6, Freq= 0, CH_1, rank 1
6980 10:05:52.023706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6981 10:05:52.023803 ==
6982 10:05:52.023925
6983 10:05:52.024015
6984 10:05:52.026440 TX Vref Scan disable
6985 10:05:52.026522 == TX Byte 0 ==
6986 10:05:52.033183 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6987 10:05:52.036786 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6988 10:05:52.036869 == TX Byte 1 ==
6989 10:05:52.043404 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6990 10:05:52.046399 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6991 10:05:52.046481
6992 10:05:52.046546 [DATLAT]
6993 10:05:52.050000 Freq=400, CH1 RK1
6994 10:05:52.050084
6995 10:05:52.050149 DATLAT Default: 0xe
6996 10:05:52.053233 0, 0xFFFF, sum = 0
6997 10:05:52.053317 1, 0xFFFF, sum = 0
6998 10:05:52.056984 2, 0xFFFF, sum = 0
6999 10:05:52.057068 3, 0xFFFF, sum = 0
7000 10:05:52.059826 4, 0xFFFF, sum = 0
7001 10:05:52.059910 5, 0xFFFF, sum = 0
7002 10:05:52.063173 6, 0xFFFF, sum = 0
7003 10:05:52.063257 7, 0xFFFF, sum = 0
7004 10:05:52.066634 8, 0xFFFF, sum = 0
7005 10:05:52.066718 9, 0xFFFF, sum = 0
7006 10:05:52.069872 10, 0xFFFF, sum = 0
7007 10:05:52.069956 11, 0xFFFF, sum = 0
7008 10:05:52.073314 12, 0xFFFF, sum = 0
7009 10:05:52.073399 13, 0x0, sum = 1
7010 10:05:52.076226 14, 0x0, sum = 2
7011 10:05:52.076311 15, 0x0, sum = 3
7012 10:05:52.079626 16, 0x0, sum = 4
7013 10:05:52.079710 best_step = 14
7014 10:05:52.079775
7015 10:05:52.079835 ==
7016 10:05:52.082888 Dram Type= 6, Freq= 0, CH_1, rank 1
7017 10:05:52.089540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7018 10:05:52.089635 ==
7019 10:05:52.089704 RX Vref Scan: 0
7020 10:05:52.089764
7021 10:05:52.093139 RX Vref 0 -> 0, step: 1
7022 10:05:52.093242
7023 10:05:52.096400 RX Delay -359 -> 252, step: 8
7024 10:05:52.102986 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7025 10:05:52.106195 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7026 10:05:52.110142 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7027 10:05:52.112978 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
7028 10:05:52.119986 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7029 10:05:52.123020 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7030 10:05:52.126642 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7031 10:05:52.129519 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7032 10:05:52.136257 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7033 10:05:52.139727 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7034 10:05:52.142721 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7035 10:05:52.146316 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7036 10:05:52.152912 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
7037 10:05:52.155934 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7038 10:05:52.159644 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7039 10:05:52.166346 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7040 10:05:52.166447 ==
7041 10:05:52.169076 Dram Type= 6, Freq= 0, CH_1, rank 1
7042 10:05:52.172448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7043 10:05:52.172521 ==
7044 10:05:52.172584 DQS Delay:
7045 10:05:52.175822 DQS0 = 52, DQS1 = 56
7046 10:05:52.175898 DQM Delay:
7047 10:05:52.179192 DQM0 = 13, DQM1 = 9
7048 10:05:52.179289 DQ Delay:
7049 10:05:52.182634 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7050 10:05:52.186002 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7051 10:05:52.189010 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7052 10:05:52.192907 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
7053 10:05:52.193012
7054 10:05:52.193079
7055 10:05:52.199001 [DQSOSCAuto] RK1, (LSB)MR18= 0x748c, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
7056 10:05:52.202304 CH1 RK1: MR19=C0C, MR18=748C
7057 10:05:52.209030 CH1_RK1: MR19=0xC0C, MR18=0x748C, DQSOSC=392, MR23=63, INC=384, DEC=256
7058 10:05:52.212453 [RxdqsGatingPostProcess] freq 400
7059 10:05:52.219201 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7060 10:05:52.219287 best DQS0 dly(2T, 0.5T) = (0, 10)
7061 10:05:52.222208 best DQS1 dly(2T, 0.5T) = (0, 10)
7062 10:05:52.225694 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7063 10:05:52.229232 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7064 10:05:52.232183 best DQS0 dly(2T, 0.5T) = (0, 10)
7065 10:05:52.235930 best DQS1 dly(2T, 0.5T) = (0, 10)
7066 10:05:52.239089 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7067 10:05:52.242492 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7068 10:05:52.245642 Pre-setting of DQS Precalculation
7069 10:05:52.249305 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7070 10:05:52.259178 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7071 10:05:52.265692 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7072 10:05:52.265777
7073 10:05:52.265842
7074 10:05:52.268809 [Calibration Summary] 800 Mbps
7075 10:05:52.268918 CH 0, Rank 0
7076 10:05:52.272450 SW Impedance : PASS
7077 10:05:52.272534 DUTY Scan : NO K
7078 10:05:52.275493 ZQ Calibration : PASS
7079 10:05:52.279014 Jitter Meter : NO K
7080 10:05:52.279098 CBT Training : PASS
7081 10:05:52.282494 Write leveling : PASS
7082 10:05:52.285622 RX DQS gating : PASS
7083 10:05:52.285696 RX DQ/DQS(RDDQC) : PASS
7084 10:05:52.288996 TX DQ/DQS : PASS
7085 10:05:52.292448 RX DATLAT : PASS
7086 10:05:52.292533 RX DQ/DQS(Engine): PASS
7087 10:05:52.295714 TX OE : NO K
7088 10:05:52.295798 All Pass.
7089 10:05:52.295864
7090 10:05:52.298697 CH 0, Rank 1
7091 10:05:52.298781 SW Impedance : PASS
7092 10:05:52.302147 DUTY Scan : NO K
7093 10:05:52.305542 ZQ Calibration : PASS
7094 10:05:52.305615 Jitter Meter : NO K
7095 10:05:52.308625 CBT Training : PASS
7096 10:05:52.311713 Write leveling : NO K
7097 10:05:52.311818 RX DQS gating : PASS
7098 10:05:52.315136 RX DQ/DQS(RDDQC) : PASS
7099 10:05:52.318361 TX DQ/DQS : PASS
7100 10:05:52.318468 RX DATLAT : PASS
7101 10:05:52.321688 RX DQ/DQS(Engine): PASS
7102 10:05:52.321799 TX OE : NO K
7103 10:05:52.325291 All Pass.
7104 10:05:52.325403
7105 10:05:52.325500 CH 1, Rank 0
7106 10:05:52.328370 SW Impedance : PASS
7107 10:05:52.328474 DUTY Scan : NO K
7108 10:05:52.331940 ZQ Calibration : PASS
7109 10:05:52.335389 Jitter Meter : NO K
7110 10:05:52.335502 CBT Training : PASS
7111 10:05:52.338649 Write leveling : PASS
7112 10:05:52.341644 RX DQS gating : PASS
7113 10:05:52.341779 RX DQ/DQS(RDDQC) : PASS
7114 10:05:52.345045 TX DQ/DQS : PASS
7115 10:05:52.348193 RX DATLAT : PASS
7116 10:05:52.348300 RX DQ/DQS(Engine): PASS
7117 10:05:52.351833 TX OE : NO K
7118 10:05:52.351939 All Pass.
7119 10:05:52.352030
7120 10:05:52.354809 CH 1, Rank 1
7121 10:05:52.354908 SW Impedance : PASS
7122 10:05:52.358053 DUTY Scan : NO K
7123 10:05:52.361581 ZQ Calibration : PASS
7124 10:05:52.361682 Jitter Meter : NO K
7125 10:05:52.364642 CBT Training : PASS
7126 10:05:52.368364 Write leveling : NO K
7127 10:05:52.368475 RX DQS gating : PASS
7128 10:05:52.371410 RX DQ/DQS(RDDQC) : PASS
7129 10:05:52.374893 TX DQ/DQS : PASS
7130 10:05:52.375009 RX DATLAT : PASS
7131 10:05:52.377896 RX DQ/DQS(Engine): PASS
7132 10:05:52.378036 TX OE : NO K
7133 10:05:52.381534 All Pass.
7134 10:05:52.381649
7135 10:05:52.381745 DramC Write-DBI off
7136 10:05:52.385066 PER_BANK_REFRESH: Hybrid Mode
7137 10:05:52.388490 TX_TRACKING: ON
7138 10:05:52.395018 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7139 10:05:52.398045 [FAST_K] Save calibration result to emmc
7140 10:05:52.404701 dramc_set_vcore_voltage set vcore to 725000
7141 10:05:52.404834 Read voltage for 1600, 0
7142 10:05:52.407956 Vio18 = 0
7143 10:05:52.408071 Vcore = 725000
7144 10:05:52.408164 Vdram = 0
7145 10:05:52.408280 Vddq = 0
7146 10:05:52.411505 Vmddr = 0
7147 10:05:52.414261 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7148 10:05:52.421244 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7149 10:05:52.424373 MEM_TYPE=3, freq_sel=13
7150 10:05:52.424484 sv_algorithm_assistance_LP4_3733
7151 10:05:52.431251 ============ PULL DRAM RESETB DOWN ============
7152 10:05:52.434407 ========== PULL DRAM RESETB DOWN end =========
7153 10:05:52.437897 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7154 10:05:52.440930 ===================================
7155 10:05:52.444752 LPDDR4 DRAM CONFIGURATION
7156 10:05:52.447692 ===================================
7157 10:05:52.451203 EX_ROW_EN[0] = 0x0
7158 10:05:52.451307 EX_ROW_EN[1] = 0x0
7159 10:05:52.454878 LP4Y_EN = 0x0
7160 10:05:52.454987 WORK_FSP = 0x1
7161 10:05:52.457911 WL = 0x5
7162 10:05:52.458021 RL = 0x5
7163 10:05:52.461442 BL = 0x2
7164 10:05:52.461542 RPST = 0x0
7165 10:05:52.464588 RD_PRE = 0x0
7166 10:05:52.464689 WR_PRE = 0x1
7167 10:05:52.468376 WR_PST = 0x1
7168 10:05:52.468476 DBI_WR = 0x0
7169 10:05:52.471291 DBI_RD = 0x0
7170 10:05:52.471401 OTF = 0x1
7171 10:05:52.474304 ===================================
7172 10:05:52.478007 ===================================
7173 10:05:52.481137 ANA top config
7174 10:05:52.484133 ===================================
7175 10:05:52.487801 DLL_ASYNC_EN = 0
7176 10:05:52.487875 ALL_SLAVE_EN = 0
7177 10:05:52.491331 NEW_RANK_MODE = 1
7178 10:05:52.494177 DLL_IDLE_MODE = 1
7179 10:05:52.497434 LP45_APHY_COMB_EN = 1
7180 10:05:52.500726 TX_ODT_DIS = 0
7181 10:05:52.500801 NEW_8X_MODE = 1
7182 10:05:52.504023 ===================================
7183 10:05:52.507768 ===================================
7184 10:05:52.510625 data_rate = 3200
7185 10:05:52.514378 CKR = 1
7186 10:05:52.517579 DQ_P2S_RATIO = 8
7187 10:05:52.520940 ===================================
7188 10:05:52.524313 CA_P2S_RATIO = 8
7189 10:05:52.527628 DQ_CA_OPEN = 0
7190 10:05:52.527714 DQ_SEMI_OPEN = 0
7191 10:05:52.530764 CA_SEMI_OPEN = 0
7192 10:05:52.534504 CA_FULL_RATE = 0
7193 10:05:52.537445 DQ_CKDIV4_EN = 0
7194 10:05:52.540430 CA_CKDIV4_EN = 0
7195 10:05:52.544037 CA_PREDIV_EN = 0
7196 10:05:52.544121 PH8_DLY = 12
7197 10:05:52.547235 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7198 10:05:52.550812 DQ_AAMCK_DIV = 4
7199 10:05:52.553742 CA_AAMCK_DIV = 4
7200 10:05:52.557241 CA_ADMCK_DIV = 4
7201 10:05:52.560299 DQ_TRACK_CA_EN = 0
7202 10:05:52.560384 CA_PICK = 1600
7203 10:05:52.563981 CA_MCKIO = 1600
7204 10:05:52.566917 MCKIO_SEMI = 0
7205 10:05:52.570156 PLL_FREQ = 3068
7206 10:05:52.573646 DQ_UI_PI_RATIO = 32
7207 10:05:52.577193 CA_UI_PI_RATIO = 0
7208 10:05:52.580165 ===================================
7209 10:05:52.584033 ===================================
7210 10:05:52.587090 memory_type:LPDDR4
7211 10:05:52.587207 GP_NUM : 10
7212 10:05:52.590196 SRAM_EN : 1
7213 10:05:52.590297 MD32_EN : 0
7214 10:05:52.593764 ===================================
7215 10:05:52.596700 [ANA_INIT] >>>>>>>>>>>>>>
7216 10:05:52.600186 <<<<<< [CONFIGURE PHASE]: ANA_TX
7217 10:05:52.603493 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7218 10:05:52.607131 ===================================
7219 10:05:52.610072 data_rate = 3200,PCW = 0X7600
7220 10:05:52.613779 ===================================
7221 10:05:52.617031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7222 10:05:52.619946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7223 10:05:52.626749 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7224 10:05:52.630457 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7225 10:05:52.636828 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7226 10:05:52.640007 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7227 10:05:52.640097 [ANA_INIT] flow start
7228 10:05:52.643394 [ANA_INIT] PLL >>>>>>>>
7229 10:05:52.646915 [ANA_INIT] PLL <<<<<<<<
7230 10:05:52.647003 [ANA_INIT] MIDPI >>>>>>>>
7231 10:05:52.650009 [ANA_INIT] MIDPI <<<<<<<<
7232 10:05:52.653257 [ANA_INIT] DLL >>>>>>>>
7233 10:05:52.653342 [ANA_INIT] DLL <<<<<<<<
7234 10:05:52.656474 [ANA_INIT] flow end
7235 10:05:52.659999 ============ LP4 DIFF to SE enter ============
7236 10:05:52.663700 ============ LP4 DIFF to SE exit ============
7237 10:05:52.666741 [ANA_INIT] <<<<<<<<<<<<<
7238 10:05:52.669909 [Flow] Enable top DCM control >>>>>
7239 10:05:52.673663 [Flow] Enable top DCM control <<<<<
7240 10:05:52.676632 Enable DLL master slave shuffle
7241 10:05:52.683519 ==============================================================
7242 10:05:52.683630 Gating Mode config
7243 10:05:52.690012 ==============================================================
7244 10:05:52.690139 Config description:
7245 10:05:52.699551 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7246 10:05:52.706128 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7247 10:05:52.713028 SELPH_MODE 0: By rank 1: By Phase
7248 10:05:52.716372 ==============================================================
7249 10:05:52.719893 GAT_TRACK_EN = 1
7250 10:05:52.723072 RX_GATING_MODE = 2
7251 10:05:52.725921 RX_GATING_TRACK_MODE = 2
7252 10:05:52.729306 SELPH_MODE = 1
7253 10:05:52.732731 PICG_EARLY_EN = 1
7254 10:05:52.735928 VALID_LAT_VALUE = 1
7255 10:05:52.742581 ==============================================================
7256 10:05:52.746081 Enter into Gating configuration >>>>
7257 10:05:52.749174 Exit from Gating configuration <<<<
7258 10:05:52.752655 Enter into DVFS_PRE_config >>>>>
7259 10:05:52.763108 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7260 10:05:52.766172 Exit from DVFS_PRE_config <<<<<
7261 10:05:52.769214 Enter into PICG configuration >>>>
7262 10:05:52.772692 Exit from PICG configuration <<<<
7263 10:05:52.775700 [RX_INPUT] configuration >>>>>
7264 10:05:52.775779 [RX_INPUT] configuration <<<<<
7265 10:05:52.782390 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7266 10:05:52.789056 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7267 10:05:52.792695 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7268 10:05:52.798977 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7269 10:05:52.805903 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7270 10:05:52.812425 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7271 10:05:52.815492 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7272 10:05:52.819198 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7273 10:05:52.825594 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7274 10:05:52.828932 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7275 10:05:52.832419 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7276 10:05:52.839087 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7277 10:05:52.842442 ===================================
7278 10:05:52.842520 LPDDR4 DRAM CONFIGURATION
7279 10:05:52.845721 ===================================
7280 10:05:52.849022 EX_ROW_EN[0] = 0x0
7281 10:05:52.849095 EX_ROW_EN[1] = 0x0
7282 10:05:52.852467 LP4Y_EN = 0x0
7283 10:05:52.852549 WORK_FSP = 0x1
7284 10:05:52.855901 WL = 0x5
7285 10:05:52.855983 RL = 0x5
7286 10:05:52.859174 BL = 0x2
7287 10:05:52.862476 RPST = 0x0
7288 10:05:52.862560 RD_PRE = 0x0
7289 10:05:52.865586 WR_PRE = 0x1
7290 10:05:52.865669 WR_PST = 0x1
7291 10:05:52.868956 DBI_WR = 0x0
7292 10:05:52.869040 DBI_RD = 0x0
7293 10:05:52.872744 OTF = 0x1
7294 10:05:52.875580 ===================================
7295 10:05:52.879022 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7296 10:05:52.882112 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7297 10:05:52.885807 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7298 10:05:52.888807 ===================================
7299 10:05:52.892450 LPDDR4 DRAM CONFIGURATION
7300 10:05:52.895343 ===================================
7301 10:05:52.898537 EX_ROW_EN[0] = 0x10
7302 10:05:52.898652 EX_ROW_EN[1] = 0x0
7303 10:05:52.902273 LP4Y_EN = 0x0
7304 10:05:52.902355 WORK_FSP = 0x1
7305 10:05:52.905200 WL = 0x5
7306 10:05:52.905282 RL = 0x5
7307 10:05:52.909069 BL = 0x2
7308 10:05:52.909226 RPST = 0x0
7309 10:05:52.912005 RD_PRE = 0x0
7310 10:05:52.912111 WR_PRE = 0x1
7311 10:05:52.915781 WR_PST = 0x1
7312 10:05:52.918518 DBI_WR = 0x0
7313 10:05:52.918618 DBI_RD = 0x0
7314 10:05:52.922193 OTF = 0x1
7315 10:05:52.925226 ===================================
7316 10:05:52.928472 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7317 10:05:52.932002 ==
7318 10:05:52.932079 Dram Type= 6, Freq= 0, CH_0, rank 0
7319 10:05:52.938659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7320 10:05:52.938747 ==
7321 10:05:52.942058 [Duty_Offset_Calibration]
7322 10:05:52.942144 B0:2 B1:-1 CA:1
7323 10:05:52.942209
7324 10:05:52.944918 [DutyScan_Calibration_Flow] k_type=0
7325 10:05:52.954226
7326 10:05:52.954397 ==CLK 0==
7327 10:05:52.957478 Final CLK duty delay cell = -4
7328 10:05:52.960860 [-4] MAX Duty = 5031%(X100), DQS PI = 6
7329 10:05:52.964174 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7330 10:05:52.967408 [-4] AVG Duty = 4937%(X100)
7331 10:05:52.967487
7332 10:05:52.970570 CH0 CLK Duty spec in!! Max-Min= 187%
7333 10:05:52.974537 [DutyScan_Calibration_Flow] ====Done====
7334 10:05:52.974637
7335 10:05:52.977560 [DutyScan_Calibration_Flow] k_type=1
7336 10:05:52.993748
7337 10:05:52.993849 ==DQS 0 ==
7338 10:05:52.996927 Final DQS duty delay cell = 0
7339 10:05:53.000474 [0] MAX Duty = 5125%(X100), DQS PI = 20
7340 10:05:53.003646 [0] MIN Duty = 5000%(X100), DQS PI = 14
7341 10:05:53.007236 [0] AVG Duty = 5062%(X100)
7342 10:05:53.007334
7343 10:05:53.007427 ==DQS 1 ==
7344 10:05:53.010596 Final DQS duty delay cell = -4
7345 10:05:53.013494 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7346 10:05:53.016677 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7347 10:05:53.020090 [-4] AVG Duty = 5046%(X100)
7348 10:05:53.020173
7349 10:05:53.023858 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7350 10:05:53.023942
7351 10:05:53.026814 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7352 10:05:53.030515 [DutyScan_Calibration_Flow] ====Done====
7353 10:05:53.030595
7354 10:05:53.033483 [DutyScan_Calibration_Flow] k_type=3
7355 10:05:53.050941
7356 10:05:53.051031 ==DQM 0 ==
7357 10:05:53.054575 Final DQM duty delay cell = 0
7358 10:05:53.057570 [0] MAX Duty = 5000%(X100), DQS PI = 20
7359 10:05:53.060874 [0] MIN Duty = 4875%(X100), DQS PI = 4
7360 10:05:53.060949 [0] AVG Duty = 4937%(X100)
7361 10:05:53.064084
7362 10:05:53.064161 ==DQM 1 ==
7363 10:05:53.067776 Final DQM duty delay cell = 0
7364 10:05:53.070899 [0] MAX Duty = 5218%(X100), DQS PI = 58
7365 10:05:53.074391 [0] MIN Duty = 4969%(X100), DQS PI = 18
7366 10:05:53.077849 [0] AVG Duty = 5093%(X100)
7367 10:05:53.077934
7368 10:05:53.080656 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7369 10:05:53.080730
7370 10:05:53.083905 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7371 10:05:53.087540 [DutyScan_Calibration_Flow] ====Done====
7372 10:05:53.087612
7373 10:05:53.090669 [DutyScan_Calibration_Flow] k_type=2
7374 10:05:53.108343
7375 10:05:53.108444 ==DQ 0 ==
7376 10:05:53.111904 Final DQ duty delay cell = 0
7377 10:05:53.114623 [0] MAX Duty = 5156%(X100), DQS PI = 0
7378 10:05:53.118183 [0] MIN Duty = 5031%(X100), DQS PI = 10
7379 10:05:53.118285 [0] AVG Duty = 5093%(X100)
7380 10:05:53.121219
7381 10:05:53.121290 ==DQ 1 ==
7382 10:05:53.124630 Final DQ duty delay cell = 0
7383 10:05:53.128170 [0] MAX Duty = 5031%(X100), DQS PI = 30
7384 10:05:53.131356 [0] MIN Duty = 4907%(X100), DQS PI = 18
7385 10:05:53.131437 [0] AVG Duty = 4969%(X100)
7386 10:05:53.131500
7387 10:05:53.137912 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7388 10:05:53.138077
7389 10:05:53.141500 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7390 10:05:53.144600 [DutyScan_Calibration_Flow] ====Done====
7391 10:05:53.144682 ==
7392 10:05:53.148071 Dram Type= 6, Freq= 0, CH_1, rank 0
7393 10:05:53.151287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7394 10:05:53.151381 ==
7395 10:05:53.154912 [Duty_Offset_Calibration]
7396 10:05:53.154993 B0:1 B1:1 CA:2
7397 10:05:53.155057
7398 10:05:53.157978 [DutyScan_Calibration_Flow] k_type=0
7399 10:05:53.168554
7400 10:05:53.168637 ==CLK 0==
7401 10:05:53.172170 Final CLK duty delay cell = 0
7402 10:05:53.175054 [0] MAX Duty = 5187%(X100), DQS PI = 24
7403 10:05:53.178106 [0] MIN Duty = 4969%(X100), DQS PI = 42
7404 10:05:53.181256 [0] AVG Duty = 5078%(X100)
7405 10:05:53.181330
7406 10:05:53.184758 CH1 CLK Duty spec in!! Max-Min= 218%
7407 10:05:53.188141 [DutyScan_Calibration_Flow] ====Done====
7408 10:05:53.188222
7409 10:05:53.191723 [DutyScan_Calibration_Flow] k_type=1
7410 10:05:53.208049
7411 10:05:53.208147 ==DQS 0 ==
7412 10:05:53.211603 Final DQS duty delay cell = 0
7413 10:05:53.214542 [0] MAX Duty = 5062%(X100), DQS PI = 22
7414 10:05:53.218259 [0] MIN Duty = 4813%(X100), DQS PI = 52
7415 10:05:53.221155 [0] AVG Duty = 4937%(X100)
7416 10:05:53.221229
7417 10:05:53.221291 ==DQS 1 ==
7418 10:05:53.224667 Final DQS duty delay cell = 0
7419 10:05:53.227647 [0] MAX Duty = 5062%(X100), DQS PI = 34
7420 10:05:53.231032 [0] MIN Duty = 4938%(X100), DQS PI = 12
7421 10:05:53.234279 [0] AVG Duty = 5000%(X100)
7422 10:05:53.234362
7423 10:05:53.237679 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7424 10:05:53.237752
7425 10:05:53.241082 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7426 10:05:53.244534 [DutyScan_Calibration_Flow] ====Done====
7427 10:05:53.244607
7428 10:05:53.248108 [DutyScan_Calibration_Flow] k_type=3
7429 10:05:53.265342
7430 10:05:53.265426 ==DQM 0 ==
7431 10:05:53.268989 Final DQM duty delay cell = 0
7432 10:05:53.271716 [0] MAX Duty = 5156%(X100), DQS PI = 20
7433 10:05:53.275337 [0] MIN Duty = 4844%(X100), DQS PI = 50
7434 10:05:53.278700 [0] AVG Duty = 5000%(X100)
7435 10:05:53.278779
7436 10:05:53.278842 ==DQM 1 ==
7437 10:05:53.281844 Final DQM duty delay cell = 0
7438 10:05:53.284985 [0] MAX Duty = 5125%(X100), DQS PI = 8
7439 10:05:53.288126 [0] MIN Duty = 4907%(X100), DQS PI = 20
7440 10:05:53.291769 [0] AVG Duty = 5016%(X100)
7441 10:05:53.291851
7442 10:05:53.294499 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7443 10:05:53.294589
7444 10:05:53.297895 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7445 10:05:53.301572 [DutyScan_Calibration_Flow] ====Done====
7446 10:05:53.301653
7447 10:05:53.304669 [DutyScan_Calibration_Flow] k_type=2
7448 10:05:53.321723
7449 10:05:53.321805 ==DQ 0 ==
7450 10:05:53.324970 Final DQ duty delay cell = 0
7451 10:05:53.328536 [0] MAX Duty = 5156%(X100), DQS PI = 20
7452 10:05:53.332230 [0] MIN Duty = 4907%(X100), DQS PI = 52
7453 10:05:53.332312 [0] AVG Duty = 5031%(X100)
7454 10:05:53.335792
7455 10:05:53.335876 ==DQ 1 ==
7456 10:05:53.338640 Final DQ duty delay cell = 0
7457 10:05:53.341704 [0] MAX Duty = 5093%(X100), DQS PI = 8
7458 10:05:53.345423 [0] MIN Duty = 5031%(X100), DQS PI = 2
7459 10:05:53.345497 [0] AVG Duty = 5062%(X100)
7460 10:05:53.345558
7461 10:05:53.348894 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7462 10:05:53.348966
7463 10:05:53.351996 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7464 10:05:53.358340 [DutyScan_Calibration_Flow] ====Done====
7465 10:05:53.362019 nWR fixed to 30
7466 10:05:53.362121 [ModeRegInit_LP4] CH0 RK0
7467 10:05:53.365388 [ModeRegInit_LP4] CH0 RK1
7468 10:05:53.368492 [ModeRegInit_LP4] CH1 RK0
7469 10:05:53.368567 [ModeRegInit_LP4] CH1 RK1
7470 10:05:53.372384 match AC timing 5
7471 10:05:53.375017 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7472 10:05:53.378478 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7473 10:05:53.385577 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7474 10:05:53.388687 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7475 10:05:53.395317 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7476 10:05:53.395436 [MiockJmeterHQA]
7477 10:05:53.395505
7478 10:05:53.398650 [DramcMiockJmeter] u1RxGatingPI = 0
7479 10:05:53.401990 0 : 4366, 4137
7480 10:05:53.402093 4 : 4253, 4027
7481 10:05:53.402194 8 : 4252, 4027
7482 10:05:53.405372 12 : 4252, 4027
7483 10:05:53.405474 16 : 4252, 4026
7484 10:05:53.408682 20 : 4252, 4027
7485 10:05:53.408780 24 : 4252, 4027
7486 10:05:53.412230 28 : 4366, 4139
7487 10:05:53.412316 32 : 4253, 4027
7488 10:05:53.412379 36 : 4255, 4029
7489 10:05:53.415165 40 : 4253, 4027
7490 10:05:53.415270 44 : 4363, 4137
7491 10:05:53.418980 48 : 4253, 4026
7492 10:05:53.419089 52 : 4361, 4137
7493 10:05:53.421864 56 : 4252, 4029
7494 10:05:53.421972 60 : 4250, 4027
7495 10:05:53.424906 64 : 4250, 4027
7496 10:05:53.425022 68 : 4252, 4029
7497 10:05:53.425125 72 : 4250, 4027
7498 10:05:53.428397 76 : 4250, 4027
7499 10:05:53.428474 80 : 4363, 4140
7500 10:05:53.431856 84 : 4250, 4027
7501 10:05:53.431932 88 : 4253, 4029
7502 10:05:53.435026 92 : 4250, 4027
7503 10:05:53.435126 96 : 4361, 3567
7504 10:05:53.435215 100 : 4250, 0
7505 10:05:53.438317 104 : 4250, 0
7506 10:05:53.438417 108 : 4363, 0
7507 10:05:53.442017 112 : 4253, 0
7508 10:05:53.442124 116 : 4249, 0
7509 10:05:53.442215 120 : 4363, 0
7510 10:05:53.445001 124 : 4361, 0
7511 10:05:53.445106 128 : 4250, 0
7512 10:05:53.448734 132 : 4250, 0
7513 10:05:53.448807 136 : 4250, 0
7514 10:05:53.448870 140 : 4253, 0
7515 10:05:53.451591 144 : 4255, 0
7516 10:05:53.451711 148 : 4250, 0
7517 10:05:53.455264 152 : 4253, 0
7518 10:05:53.455339 156 : 4363, 0
7519 10:05:53.455463 160 : 4361, 0
7520 10:05:53.458404 164 : 4250, 0
7521 10:05:53.458476 168 : 4250, 0
7522 10:05:53.458535 172 : 4361, 0
7523 10:05:53.461624 176 : 4360, 0
7524 10:05:53.461699 180 : 4250, 0
7525 10:05:53.465552 184 : 4250, 0
7526 10:05:53.465635 188 : 4250, 0
7527 10:05:53.465701 192 : 4252, 0
7528 10:05:53.468146 196 : 4250, 0
7529 10:05:53.468245 200 : 4250, 0
7530 10:05:53.471371 204 : 4252, 0
7531 10:05:53.471477 208 : 4361, 0
7532 10:05:53.471562 212 : 4361, 150
7533 10:05:53.475190 216 : 4250, 3932
7534 10:05:53.475300 220 : 4250, 4026
7535 10:05:53.478527 224 : 4250, 4027
7536 10:05:53.478648 228 : 4250, 4027
7537 10:05:53.481993 232 : 4250, 4026
7538 10:05:53.482110 236 : 4252, 4029
7539 10:05:53.484814 240 : 4250, 4027
7540 10:05:53.484915 244 : 4360, 4138
7541 10:05:53.488111 248 : 4361, 4137
7542 10:05:53.488188 252 : 4250, 4026
7543 10:05:53.491665 256 : 4363, 4139
7544 10:05:53.491766 260 : 4250, 4027
7545 10:05:53.491876 264 : 4249, 4027
7546 10:05:53.494880 268 : 4250, 4026
7547 10:05:53.494954 272 : 4253, 4029
7548 10:05:53.498270 276 : 4250, 4027
7549 10:05:53.498404 280 : 4250, 4027
7550 10:05:53.501205 284 : 4250, 4026
7551 10:05:53.501323 288 : 4253, 4029
7552 10:05:53.504714 292 : 4250, 4027
7553 10:05:53.504830 296 : 4361, 4137
7554 10:05:53.508146 300 : 4361, 4137
7555 10:05:53.508266 304 : 4250, 4026
7556 10:05:53.511447 308 : 4363, 4139
7557 10:05:53.511553 312 : 4361, 4137
7558 10:05:53.514484 316 : 4249, 4027
7559 10:05:53.514605 320 : 4250, 4026
7560 10:05:53.514698 324 : 4253, 4029
7561 10:05:53.518247 328 : 4250, 4027
7562 10:05:53.518367 332 : 4249, 2775
7563 10:05:53.520989 336 : 4250, 42
7564 10:05:53.521104
7565 10:05:53.524677 MIOCK jitter meter ch=0
7566 10:05:53.524787
7567 10:05:53.524891 1T = (336-100) = 236 dly cells
7568 10:05:53.531562 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7569 10:05:53.531658 ==
7570 10:05:53.534854 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 10:05:53.537920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 10:05:53.541351 ==
7573 10:05:53.544429 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7574 10:05:53.547955 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7575 10:05:53.554494 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7576 10:05:53.561022 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7577 10:05:53.568496 [CA 0] Center 44 (14~75) winsize 62
7578 10:05:53.571332 [CA 1] Center 44 (14~74) winsize 61
7579 10:05:53.575282 [CA 2] Center 39 (10~68) winsize 59
7580 10:05:53.578255 [CA 3] Center 39 (10~68) winsize 59
7581 10:05:53.581793 [CA 4] Center 37 (7~67) winsize 61
7582 10:05:53.584667 [CA 5] Center 37 (7~67) winsize 61
7583 10:05:53.584776
7584 10:05:53.587940 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7585 10:05:53.588023
7586 10:05:53.594789 [CATrainingPosCal] consider 1 rank data
7587 10:05:53.594876 u2DelayCellTimex100 = 275/100 ps
7588 10:05:53.601783 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7589 10:05:53.604596 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7590 10:05:53.608098 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7591 10:05:53.611514 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7592 10:05:53.614977 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7593 10:05:53.618254 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7594 10:05:53.618349
7595 10:05:53.621296 CA PerBit enable=1, Macro0, CA PI delay=37
7596 10:05:53.621378
7597 10:05:53.624711 [CBTSetCACLKResult] CA Dly = 37
7598 10:05:53.628478 CS Dly: 11 (0~42)
7599 10:05:53.631462 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7600 10:05:53.634651 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7601 10:05:53.634753 ==
7602 10:05:53.638113 Dram Type= 6, Freq= 0, CH_0, rank 1
7603 10:05:53.644471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 10:05:53.644555 ==
7605 10:05:53.647981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7606 10:05:53.654809 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7607 10:05:53.658427 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7608 10:05:53.664368 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7609 10:05:53.672644 [CA 0] Center 44 (14~75) winsize 62
7610 10:05:53.675307 [CA 1] Center 44 (14~75) winsize 62
7611 10:05:53.679083 [CA 2] Center 40 (11~69) winsize 59
7612 10:05:53.681898 [CA 3] Center 39 (10~69) winsize 60
7613 10:05:53.685356 [CA 4] Center 37 (8~67) winsize 60
7614 10:05:53.688791 [CA 5] Center 37 (7~67) winsize 61
7615 10:05:53.688895
7616 10:05:53.692234 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7617 10:05:53.692348
7618 10:05:53.698423 [CATrainingPosCal] consider 2 rank data
7619 10:05:53.698507 u2DelayCellTimex100 = 275/100 ps
7620 10:05:53.705098 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7621 10:05:53.708519 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7622 10:05:53.711811 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7623 10:05:53.715028 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7624 10:05:53.718433 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7625 10:05:53.721840 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7626 10:05:53.721941
7627 10:05:53.725480 CA PerBit enable=1, Macro0, CA PI delay=37
7628 10:05:53.725589
7629 10:05:53.728160 [CBTSetCACLKResult] CA Dly = 37
7630 10:05:53.731743 CS Dly: 12 (0~44)
7631 10:05:53.735283 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7632 10:05:53.738411 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7633 10:05:53.738513
7634 10:05:53.742018 ----->DramcWriteLeveling(PI) begin...
7635 10:05:53.742119 ==
7636 10:05:53.745100 Dram Type= 6, Freq= 0, CH_0, rank 0
7637 10:05:53.752000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7638 10:05:53.752115 ==
7639 10:05:53.755187 Write leveling (Byte 0): 31 => 31
7640 10:05:53.758752 Write leveling (Byte 1): 26 => 26
7641 10:05:53.758859 DramcWriteLeveling(PI) end<-----
7642 10:05:53.758953
7643 10:05:53.761748 ==
7644 10:05:53.765361 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 10:05:53.768372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 10:05:53.768469 ==
7647 10:05:53.771843 [Gating] SW mode calibration
7648 10:05:53.778466 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7649 10:05:53.781500 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7650 10:05:53.788341 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 10:05:53.791539 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 10:05:53.794748 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 10:05:53.801427 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 10:05:53.804652 1 4 16 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
7655 10:05:53.808147 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7656 10:05:53.815043 1 4 24 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
7657 10:05:53.818121 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7658 10:05:53.821639 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7659 10:05:53.827757 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7660 10:05:53.831657 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7661 10:05:53.834598 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7662 10:05:53.841181 1 5 16 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 0)
7663 10:05:53.844768 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7664 10:05:53.847717 1 5 24 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
7665 10:05:53.854385 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 10:05:53.858506 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7667 10:05:53.861386 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7668 10:05:53.867491 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7669 10:05:53.871136 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7670 10:05:53.874505 1 6 16 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7671 10:05:53.881145 1 6 20 | B1->B0 | 2424 4242 | 0 0 | (0 0) (0 0)
7672 10:05:53.884042 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7673 10:05:53.887435 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7674 10:05:53.894037 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 10:05:53.897382 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 10:05:53.900785 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7677 10:05:53.907339 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 10:05:53.910789 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7679 10:05:53.913697 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7680 10:05:53.920583 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7681 10:05:53.924282 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 10:05:53.927206 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 10:05:53.930248 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 10:05:53.937453 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 10:05:53.940520 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 10:05:53.944073 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 10:05:53.950667 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 10:05:53.953714 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 10:05:53.957146 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 10:05:53.964072 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 10:05:53.967147 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 10:05:53.970737 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 10:05:53.977295 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 10:05:53.981050 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7695 10:05:53.983902 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7696 10:05:53.987597 Total UI for P1: 0, mck2ui 16
7697 10:05:53.990550 best dqsien dly found for B0: ( 1, 9, 16)
7698 10:05:53.997476 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7699 10:05:54.000602 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7700 10:05:54.003643 Total UI for P1: 0, mck2ui 16
7701 10:05:54.007132 best dqsien dly found for B1: ( 1, 9, 22)
7702 10:05:54.010691 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7703 10:05:54.013562 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7704 10:05:54.013645
7705 10:05:54.016822 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7706 10:05:54.020275 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7707 10:05:54.023745 [Gating] SW calibration Done
7708 10:05:54.023829 ==
7709 10:05:54.027311 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 10:05:54.030355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 10:05:54.033493 ==
7712 10:05:54.033577 RX Vref Scan: 0
7713 10:05:54.033642
7714 10:05:54.037278 RX Vref 0 -> 0, step: 1
7715 10:05:54.037361
7716 10:05:54.037426 RX Delay 0 -> 252, step: 8
7717 10:05:54.044029 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7718 10:05:54.047271 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7719 10:05:54.050950 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7720 10:05:54.053961 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7721 10:05:54.057488 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7722 10:05:54.063982 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7723 10:05:54.067667 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7724 10:05:54.070544 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7725 10:05:54.073790 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7726 10:05:54.077378 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7727 10:05:54.083906 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7728 10:05:54.087081 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7729 10:05:54.090610 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7730 10:05:54.093632 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7731 10:05:54.097298 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7732 10:05:54.104116 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7733 10:05:54.104206 ==
7734 10:05:54.107079 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 10:05:54.110136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 10:05:54.110216 ==
7737 10:05:54.110286 DQS Delay:
7738 10:05:54.113797 DQS0 = 0, DQS1 = 0
7739 10:05:54.113871 DQM Delay:
7740 10:05:54.117000 DQM0 = 132, DQM1 = 125
7741 10:05:54.117078 DQ Delay:
7742 10:05:54.120331 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7743 10:05:54.123715 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7744 10:05:54.127123 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7745 10:05:54.130130 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7746 10:05:54.133812
7747 10:05:54.133886
7748 10:05:54.133958 ==
7749 10:05:54.136753 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 10:05:54.140148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 10:05:54.140223 ==
7752 10:05:54.140293
7753 10:05:54.140357
7754 10:05:54.143603 TX Vref Scan disable
7755 10:05:54.143682 == TX Byte 0 ==
7756 10:05:54.150080 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7757 10:05:54.153568 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7758 10:05:54.153643 == TX Byte 1 ==
7759 10:05:54.160097 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7760 10:05:54.163190 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7761 10:05:54.163293 ==
7762 10:05:54.166683 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 10:05:54.170215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 10:05:54.170286 ==
7765 10:05:54.183953
7766 10:05:54.187366 TX Vref early break, caculate TX vref
7767 10:05:54.191041 TX Vref=16, minBit 7, minWin=21, winSum=354
7768 10:05:54.194164 TX Vref=18, minBit 0, minWin=22, winSum=366
7769 10:05:54.197178 TX Vref=20, minBit 4, minWin=22, winSum=374
7770 10:05:54.200777 TX Vref=22, minBit 7, minWin=22, winSum=380
7771 10:05:54.204110 TX Vref=24, minBit 7, minWin=23, winSum=396
7772 10:05:54.210224 TX Vref=26, minBit 1, minWin=25, winSum=410
7773 10:05:54.213755 TX Vref=28, minBit 1, minWin=24, winSum=414
7774 10:05:54.216807 TX Vref=30, minBit 4, minWin=24, winSum=415
7775 10:05:54.220048 TX Vref=32, minBit 0, minWin=24, winSum=405
7776 10:05:54.223509 TX Vref=34, minBit 4, minWin=23, winSum=391
7777 10:05:54.230152 [TxChooseVref] Worse bit 1, Min win 25, Win sum 410, Final Vref 26
7778 10:05:54.230262
7779 10:05:54.233553 Final TX Range 0 Vref 26
7780 10:05:54.233683
7781 10:05:54.233788 ==
7782 10:05:54.236630 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 10:05:54.240287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 10:05:54.240364 ==
7785 10:05:54.240434
7786 10:05:54.240499
7787 10:05:54.243101 TX Vref Scan disable
7788 10:05:54.250138 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7789 10:05:54.250221 == TX Byte 0 ==
7790 10:05:54.252957 u2DelayCellOfst[0]=17 cells (5 PI)
7791 10:05:54.256574 u2DelayCellOfst[1]=21 cells (6 PI)
7792 10:05:54.260228 u2DelayCellOfst[2]=14 cells (4 PI)
7793 10:05:54.262965 u2DelayCellOfst[3]=17 cells (5 PI)
7794 10:05:54.266596 u2DelayCellOfst[4]=10 cells (3 PI)
7795 10:05:54.269576 u2DelayCellOfst[5]=0 cells (0 PI)
7796 10:05:54.273180 u2DelayCellOfst[6]=21 cells (6 PI)
7797 10:05:54.276795 u2DelayCellOfst[7]=21 cells (6 PI)
7798 10:05:54.279858 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7799 10:05:54.282883 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7800 10:05:54.286427 == TX Byte 1 ==
7801 10:05:54.289909 u2DelayCellOfst[8]=0 cells (0 PI)
7802 10:05:54.293176 u2DelayCellOfst[9]=0 cells (0 PI)
7803 10:05:54.296096 u2DelayCellOfst[10]=7 cells (2 PI)
7804 10:05:54.296173 u2DelayCellOfst[11]=3 cells (1 PI)
7805 10:05:54.299695 u2DelayCellOfst[12]=10 cells (3 PI)
7806 10:05:54.302739 u2DelayCellOfst[13]=10 cells (3 PI)
7807 10:05:54.306379 u2DelayCellOfst[14]=14 cells (4 PI)
7808 10:05:54.309326 u2DelayCellOfst[15]=10 cells (3 PI)
7809 10:05:54.316251 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7810 10:05:54.319247 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7811 10:05:54.319372 DramC Write-DBI on
7812 10:05:54.319471 ==
7813 10:05:54.322722 Dram Type= 6, Freq= 0, CH_0, rank 0
7814 10:05:54.329418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7815 10:05:54.329517 ==
7816 10:05:54.329584
7817 10:05:54.329646
7818 10:05:54.329721 TX Vref Scan disable
7819 10:05:54.333675 == TX Byte 0 ==
7820 10:05:54.337115 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7821 10:05:54.340874 == TX Byte 1 ==
7822 10:05:54.343841 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7823 10:05:54.347217 DramC Write-DBI off
7824 10:05:54.347343
7825 10:05:54.347459 [DATLAT]
7826 10:05:54.347550 Freq=1600, CH0 RK0
7827 10:05:54.347647
7828 10:05:54.350292 DATLAT Default: 0xf
7829 10:05:54.350374 0, 0xFFFF, sum = 0
7830 10:05:54.353611 1, 0xFFFF, sum = 0
7831 10:05:54.357102 2, 0xFFFF, sum = 0
7832 10:05:54.357178 3, 0xFFFF, sum = 0
7833 10:05:54.359995 4, 0xFFFF, sum = 0
7834 10:05:54.360081 5, 0xFFFF, sum = 0
7835 10:05:54.363472 6, 0xFFFF, sum = 0
7836 10:05:54.363583 7, 0xFFFF, sum = 0
7837 10:05:54.366935 8, 0xFFFF, sum = 0
7838 10:05:54.367045 9, 0xFFFF, sum = 0
7839 10:05:54.370313 10, 0xFFFF, sum = 0
7840 10:05:54.370430 11, 0xFFFF, sum = 0
7841 10:05:54.373269 12, 0xFFFF, sum = 0
7842 10:05:54.373372 13, 0xFFFF, sum = 0
7843 10:05:54.376788 14, 0x0, sum = 1
7844 10:05:54.376861 15, 0x0, sum = 2
7845 10:05:54.380487 16, 0x0, sum = 3
7846 10:05:54.380571 17, 0x0, sum = 4
7847 10:05:54.383291 best_step = 15
7848 10:05:54.383452
7849 10:05:54.383544 ==
7850 10:05:54.386303 Dram Type= 6, Freq= 0, CH_0, rank 0
7851 10:05:54.389869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7852 10:05:54.389975 ==
7853 10:05:54.392937 RX Vref Scan: 1
7854 10:05:54.393042
7855 10:05:54.393131 Set Vref Range= 24 -> 127
7856 10:05:54.393231
7857 10:05:54.396501 RX Vref 24 -> 127, step: 1
7858 10:05:54.396587
7859 10:05:54.399688 RX Delay 11 -> 252, step: 4
7860 10:05:54.399801
7861 10:05:54.403139 Set Vref, RX VrefLevel [Byte0]: 24
7862 10:05:54.406831 [Byte1]: 24
7863 10:05:54.406904
7864 10:05:54.409693 Set Vref, RX VrefLevel [Byte0]: 25
7865 10:05:54.413577 [Byte1]: 25
7866 10:05:54.416520
7867 10:05:54.416620 Set Vref, RX VrefLevel [Byte0]: 26
7868 10:05:54.420030 [Byte1]: 26
7869 10:05:54.424081
7870 10:05:54.424167 Set Vref, RX VrefLevel [Byte0]: 27
7871 10:05:54.427732 [Byte1]: 27
7872 10:05:54.431815
7873 10:05:54.431895 Set Vref, RX VrefLevel [Byte0]: 28
7874 10:05:54.435145 [Byte1]: 28
7875 10:05:54.439198
7876 10:05:54.439337 Set Vref, RX VrefLevel [Byte0]: 29
7877 10:05:54.442281 [Byte1]: 29
7878 10:05:54.446912
7879 10:05:54.446996 Set Vref, RX VrefLevel [Byte0]: 30
7880 10:05:54.449934 [Byte1]: 30
7881 10:05:54.454719
7882 10:05:54.454796 Set Vref, RX VrefLevel [Byte0]: 31
7883 10:05:54.457806 [Byte1]: 31
7884 10:05:54.462286
7885 10:05:54.462364 Set Vref, RX VrefLevel [Byte0]: 32
7886 10:05:54.465392 [Byte1]: 32
7887 10:05:54.469690
7888 10:05:54.469766 Set Vref, RX VrefLevel [Byte0]: 33
7889 10:05:54.473447 [Byte1]: 33
7890 10:05:54.477213
7891 10:05:54.477320 Set Vref, RX VrefLevel [Byte0]: 34
7892 10:05:54.480504 [Byte1]: 34
7893 10:05:54.485245
7894 10:05:54.485346 Set Vref, RX VrefLevel [Byte0]: 35
7895 10:05:54.488190 [Byte1]: 35
7896 10:05:54.492849
7897 10:05:54.492923 Set Vref, RX VrefLevel [Byte0]: 36
7898 10:05:54.495834 [Byte1]: 36
7899 10:05:54.499948
7900 10:05:54.500031 Set Vref, RX VrefLevel [Byte0]: 37
7901 10:05:54.503172 [Byte1]: 37
7902 10:05:54.507792
7903 10:05:54.507871 Set Vref, RX VrefLevel [Byte0]: 38
7904 10:05:54.511500 [Byte1]: 38
7905 10:05:54.515100
7906 10:05:54.515207 Set Vref, RX VrefLevel [Byte0]: 39
7907 10:05:54.518618 [Byte1]: 39
7908 10:05:54.523201
7909 10:05:54.523280 Set Vref, RX VrefLevel [Byte0]: 40
7910 10:05:54.526281 [Byte1]: 40
7911 10:05:54.531179
7912 10:05:54.531251 Set Vref, RX VrefLevel [Byte0]: 41
7913 10:05:54.533879 [Byte1]: 41
7914 10:05:54.538353
7915 10:05:54.541303 Set Vref, RX VrefLevel [Byte0]: 42
7916 10:05:54.544749 [Byte1]: 42
7917 10:05:54.544856
7918 10:05:54.547858 Set Vref, RX VrefLevel [Byte0]: 43
7919 10:05:54.551300 [Byte1]: 43
7920 10:05:54.551468
7921 10:05:54.554499 Set Vref, RX VrefLevel [Byte0]: 44
7922 10:05:54.557923 [Byte1]: 44
7923 10:05:54.558009
7924 10:05:54.561600 Set Vref, RX VrefLevel [Byte0]: 45
7925 10:05:54.564518 [Byte1]: 45
7926 10:05:54.568458
7927 10:05:54.568532 Set Vref, RX VrefLevel [Byte0]: 46
7928 10:05:54.572094 [Byte1]: 46
7929 10:05:54.576095
7930 10:05:54.576188 Set Vref, RX VrefLevel [Byte0]: 47
7931 10:05:54.579608 [Byte1]: 47
7932 10:05:54.583930
7933 10:05:54.584007 Set Vref, RX VrefLevel [Byte0]: 48
7934 10:05:54.587416 [Byte1]: 48
7935 10:05:54.591739
7936 10:05:54.591820 Set Vref, RX VrefLevel [Byte0]: 49
7937 10:05:54.594767 [Byte1]: 49
7938 10:05:54.599292
7939 10:05:54.599396 Set Vref, RX VrefLevel [Byte0]: 50
7940 10:05:54.602508 [Byte1]: 50
7941 10:05:54.606604
7942 10:05:54.606682 Set Vref, RX VrefLevel [Byte0]: 51
7943 10:05:54.610156 [Byte1]: 51
7944 10:05:54.614407
7945 10:05:54.614523 Set Vref, RX VrefLevel [Byte0]: 52
7946 10:05:54.617867 [Byte1]: 52
7947 10:05:54.621660
7948 10:05:54.621773 Set Vref, RX VrefLevel [Byte0]: 53
7949 10:05:54.625530 [Byte1]: 53
7950 10:05:54.629557
7951 10:05:54.629631 Set Vref, RX VrefLevel [Byte0]: 54
7952 10:05:54.632914 [Byte1]: 54
7953 10:05:54.637439
7954 10:05:54.637513 Set Vref, RX VrefLevel [Byte0]: 55
7955 10:05:54.640300 [Byte1]: 55
7956 10:05:54.644986
7957 10:05:54.645068 Set Vref, RX VrefLevel [Byte0]: 56
7958 10:05:54.647764 [Byte1]: 56
7959 10:05:54.652490
7960 10:05:54.652571 Set Vref, RX VrefLevel [Byte0]: 57
7961 10:05:54.655532 [Byte1]: 57
7962 10:05:54.660122
7963 10:05:54.660199 Set Vref, RX VrefLevel [Byte0]: 58
7964 10:05:54.663336 [Byte1]: 58
7965 10:05:54.667575
7966 10:05:54.667661 Set Vref, RX VrefLevel [Byte0]: 59
7967 10:05:54.674569 [Byte1]: 59
7968 10:05:54.674650
7969 10:05:54.677459 Set Vref, RX VrefLevel [Byte0]: 60
7970 10:05:54.680426 [Byte1]: 60
7971 10:05:54.680503
7972 10:05:54.684167 Set Vref, RX VrefLevel [Byte0]: 61
7973 10:05:54.687716 [Byte1]: 61
7974 10:05:54.687798
7975 10:05:54.690609 Set Vref, RX VrefLevel [Byte0]: 62
7976 10:05:54.694249 [Byte1]: 62
7977 10:05:54.698444
7978 10:05:54.698522 Set Vref, RX VrefLevel [Byte0]: 63
7979 10:05:54.701276 [Byte1]: 63
7980 10:05:54.705583
7981 10:05:54.705684 Set Vref, RX VrefLevel [Byte0]: 64
7982 10:05:54.709275 [Byte1]: 64
7983 10:05:54.713343
7984 10:05:54.713449 Set Vref, RX VrefLevel [Byte0]: 65
7985 10:05:54.716867 [Byte1]: 65
7986 10:05:54.721054
7987 10:05:54.721131 Set Vref, RX VrefLevel [Byte0]: 66
7988 10:05:54.723945 [Byte1]: 66
7989 10:05:54.728601
7990 10:05:54.728684 Set Vref, RX VrefLevel [Byte0]: 67
7991 10:05:54.732147 [Byte1]: 67
7992 10:05:54.736330
7993 10:05:54.736417 Set Vref, RX VrefLevel [Byte0]: 68
7994 10:05:54.739174 [Byte1]: 68
7995 10:05:54.743741
7996 10:05:54.743828 Set Vref, RX VrefLevel [Byte0]: 69
7997 10:05:54.747167 [Byte1]: 69
7998 10:05:54.751838
7999 10:05:54.751922 Set Vref, RX VrefLevel [Byte0]: 70
8000 10:05:54.754550 [Byte1]: 70
8001 10:05:54.758828
8002 10:05:54.758928 Set Vref, RX VrefLevel [Byte0]: 71
8003 10:05:54.762259 [Byte1]: 71
8004 10:05:54.766567
8005 10:05:54.766678 Set Vref, RX VrefLevel [Byte0]: 72
8006 10:05:54.769629 [Byte1]: 72
8007 10:05:54.774097
8008 10:05:54.774178 Set Vref, RX VrefLevel [Byte0]: 73
8009 10:05:54.777465 [Byte1]: 73
8010 10:05:54.781767
8011 10:05:54.781852 Set Vref, RX VrefLevel [Byte0]: 74
8012 10:05:54.785233 [Byte1]: 74
8013 10:05:54.789379
8014 10:05:54.789459 Set Vref, RX VrefLevel [Byte0]: 75
8015 10:05:54.792978 [Byte1]: 75
8016 10:05:54.796834
8017 10:05:54.796920 Set Vref, RX VrefLevel [Byte0]: 76
8018 10:05:54.800229 [Byte1]: 76
8019 10:05:54.804491
8020 10:05:54.804573 Final RX Vref Byte 0 = 61 to rank0
8021 10:05:54.808133 Final RX Vref Byte 1 = 63 to rank0
8022 10:05:54.811230 Final RX Vref Byte 0 = 61 to rank1
8023 10:05:54.814895 Final RX Vref Byte 1 = 63 to rank1==
8024 10:05:54.818342 Dram Type= 6, Freq= 0, CH_0, rank 0
8025 10:05:54.824918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 10:05:54.825000 ==
8027 10:05:54.825064 DQS Delay:
8028 10:05:54.825123 DQS0 = 0, DQS1 = 0
8029 10:05:54.827991 DQM Delay:
8030 10:05:54.828113 DQM0 = 129, DQM1 = 122
8031 10:05:54.831519 DQ Delay:
8032 10:05:54.834532 DQ0 =128, DQ1 =132, DQ2 =126, DQ3 =126
8033 10:05:54.838035 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =138
8034 10:05:54.840969 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8035 10:05:54.844903 DQ12 =128, DQ13 =128, DQ14 =130, DQ15 =132
8036 10:05:54.844996
8037 10:05:54.845061
8038 10:05:54.845122
8039 10:05:54.847960 [DramC_TX_OE_Calibration] TA2
8040 10:05:54.851237 Original DQ_B0 (3 6) =30, OEN = 27
8041 10:05:54.854305 Original DQ_B1 (3 6) =30, OEN = 27
8042 10:05:54.857590 24, 0x0, End_B0=24 End_B1=24
8043 10:05:54.857673 25, 0x0, End_B0=25 End_B1=25
8044 10:05:54.861124 26, 0x0, End_B0=26 End_B1=26
8045 10:05:54.864085 27, 0x0, End_B0=27 End_B1=27
8046 10:05:54.867776 28, 0x0, End_B0=28 End_B1=28
8047 10:05:54.870740 29, 0x0, End_B0=29 End_B1=29
8048 10:05:54.870822 30, 0x0, End_B0=30 End_B1=30
8049 10:05:54.874327 31, 0x4545, End_B0=30 End_B1=30
8050 10:05:54.877312 Byte0 end_step=30 best_step=27
8051 10:05:54.880650 Byte1 end_step=30 best_step=27
8052 10:05:54.884259 Byte0 TX OE(2T, 0.5T) = (3, 3)
8053 10:05:54.887996 Byte1 TX OE(2T, 0.5T) = (3, 3)
8054 10:05:54.888077
8055 10:05:54.888140
8056 10:05:54.894489 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8057 10:05:54.897943 CH0 RK0: MR19=303, MR18=1509
8058 10:05:54.904367 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
8059 10:05:54.904516
8060 10:05:54.907356 ----->DramcWriteLeveling(PI) begin...
8061 10:05:54.907449 ==
8062 10:05:54.911146 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 10:05:54.914021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 10:05:54.914091 ==
8065 10:05:54.917743 Write leveling (Byte 0): 33 => 33
8066 10:05:54.920622 Write leveling (Byte 1): 26 => 26
8067 10:05:54.924055 DramcWriteLeveling(PI) end<-----
8068 10:05:54.924132
8069 10:05:54.924206 ==
8070 10:05:54.927185 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 10:05:54.930579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 10:05:54.930674 ==
8073 10:05:54.934226 [Gating] SW mode calibration
8074 10:05:54.940714 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8075 10:05:54.947165 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8076 10:05:54.950613 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 10:05:54.953974 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 10:05:54.960679 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 10:05:54.964070 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8080 10:05:54.967252 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8081 10:05:54.973772 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8082 10:05:54.977383 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8083 10:05:54.980360 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8084 10:05:54.987219 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8085 10:05:54.990325 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8086 10:05:54.993825 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8087 10:05:55.000545 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 1)
8088 10:05:55.003976 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8089 10:05:55.006987 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
8090 10:05:55.013770 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8091 10:05:55.017295 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 10:05:55.020563 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8093 10:05:55.026890 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8094 10:05:55.029972 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8095 10:05:55.033510 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8096 10:05:55.040281 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
8097 10:05:55.043219 1 6 20 | B1->B0 | 3b3a 4646 | 1 0 | (0 0) (0 0)
8098 10:05:55.046623 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 10:05:55.053746 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 10:05:55.056623 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8101 10:05:55.060022 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 10:05:55.066698 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8103 10:05:55.070351 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8104 10:05:55.073311 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8105 10:05:55.080253 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8106 10:05:55.083148 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 10:05:55.086510 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 10:05:55.093644 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 10:05:55.096613 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 10:05:55.099938 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 10:05:55.106724 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 10:05:55.109910 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 10:05:55.113287 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 10:05:55.116979 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 10:05:55.123458 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 10:05:55.126445 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 10:05:55.129957 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 10:05:55.136447 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8119 10:05:55.139528 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8120 10:05:55.143053 Total UI for P1: 0, mck2ui 16
8121 10:05:55.146291 best dqsien dly found for B0: ( 1, 9, 8)
8122 10:05:55.149731 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8123 10:05:55.156424 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8124 10:05:55.159837 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8125 10:05:55.163043 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8126 10:05:55.166511 Total UI for P1: 0, mck2ui 16
8127 10:05:55.169342 best dqsien dly found for B1: ( 1, 9, 20)
8128 10:05:55.173278 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8129 10:05:55.176187 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8130 10:05:55.176294
8131 10:05:55.182851 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8132 10:05:55.185930 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8133 10:05:55.189381 [Gating] SW calibration Done
8134 10:05:55.189483 ==
8135 10:05:55.192995 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 10:05:55.195871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 10:05:55.195970 ==
8138 10:05:55.196061 RX Vref Scan: 0
8139 10:05:55.196158
8140 10:05:55.199556 RX Vref 0 -> 0, step: 1
8141 10:05:55.199653
8142 10:05:55.203038 RX Delay 0 -> 252, step: 8
8143 10:05:55.205961 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8144 10:05:55.209505 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8145 10:05:55.212893 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8146 10:05:55.219270 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8147 10:05:55.222621 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8148 10:05:55.226291 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8149 10:05:55.229051 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8150 10:05:55.232679 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8151 10:05:55.239344 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8152 10:05:55.242460 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8153 10:05:55.246061 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8154 10:05:55.249061 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8155 10:05:55.255813 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8156 10:05:55.259392 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8157 10:05:55.262046 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8158 10:05:55.265474 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8159 10:05:55.265552 ==
8160 10:05:55.268950 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 10:05:55.275402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 10:05:55.275480 ==
8163 10:05:55.275548 DQS Delay:
8164 10:05:55.275611 DQS0 = 0, DQS1 = 0
8165 10:05:55.278950 DQM Delay:
8166 10:05:55.279021 DQM0 = 131, DQM1 = 125
8167 10:05:55.282109 DQ Delay:
8168 10:05:55.285617 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8169 10:05:55.289114 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8170 10:05:55.292155 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =119
8171 10:05:55.295717 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
8172 10:05:55.295790
8173 10:05:55.295856
8174 10:05:55.295918 ==
8175 10:05:55.299020 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 10:05:55.302201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 10:05:55.305675 ==
8178 10:05:55.305756
8179 10:05:55.305824
8180 10:05:55.305887 TX Vref Scan disable
8181 10:05:55.309112 == TX Byte 0 ==
8182 10:05:55.312280 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8183 10:05:55.315629 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8184 10:05:55.318765 == TX Byte 1 ==
8185 10:05:55.322132 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8186 10:05:55.325883 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8187 10:05:55.325967 ==
8188 10:05:55.329179 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 10:05:55.335179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 10:05:55.335262 ==
8191 10:05:55.349119
8192 10:05:55.352738 TX Vref early break, caculate TX vref
8193 10:05:55.356255 TX Vref=16, minBit 8, minWin=22, winSum=372
8194 10:05:55.359234 TX Vref=18, minBit 9, minWin=22, winSum=381
8195 10:05:55.362773 TX Vref=20, minBit 3, minWin=23, winSum=390
8196 10:05:55.365720 TX Vref=22, minBit 8, minWin=23, winSum=398
8197 10:05:55.369146 TX Vref=24, minBit 9, minWin=24, winSum=406
8198 10:05:55.375887 TX Vref=26, minBit 7, minWin=25, winSum=415
8199 10:05:55.379257 TX Vref=28, minBit 3, minWin=25, winSum=421
8200 10:05:55.382904 TX Vref=30, minBit 10, minWin=25, winSum=418
8201 10:05:55.385857 TX Vref=32, minBit 1, minWin=25, winSum=411
8202 10:05:55.388885 TX Vref=34, minBit 0, minWin=25, winSum=405
8203 10:05:55.392727 TX Vref=36, minBit 0, minWin=24, winSum=395
8204 10:05:55.399108 [TxChooseVref] Worse bit 3, Min win 25, Win sum 421, Final Vref 28
8205 10:05:55.399188
8206 10:05:55.402582 Final TX Range 0 Vref 28
8207 10:05:55.402686
8208 10:05:55.402798 ==
8209 10:05:55.405576 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 10:05:55.409250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 10:05:55.409329 ==
8212 10:05:55.409392
8213 10:05:55.412459
8214 10:05:55.412545 TX Vref Scan disable
8215 10:05:55.418947 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8216 10:05:55.419027 == TX Byte 0 ==
8217 10:05:55.422524 u2DelayCellOfst[0]=14 cells (4 PI)
8218 10:05:55.425564 u2DelayCellOfst[1]=21 cells (6 PI)
8219 10:05:55.429246 u2DelayCellOfst[2]=10 cells (3 PI)
8220 10:05:55.432283 u2DelayCellOfst[3]=14 cells (4 PI)
8221 10:05:55.435784 u2DelayCellOfst[4]=10 cells (3 PI)
8222 10:05:55.439286 u2DelayCellOfst[5]=0 cells (0 PI)
8223 10:05:55.442197 u2DelayCellOfst[6]=21 cells (6 PI)
8224 10:05:55.445834 u2DelayCellOfst[7]=21 cells (6 PI)
8225 10:05:55.448694 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8226 10:05:55.452401 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8227 10:05:55.456038 == TX Byte 1 ==
8228 10:05:55.458953 u2DelayCellOfst[8]=0 cells (0 PI)
8229 10:05:55.462415 u2DelayCellOfst[9]=0 cells (0 PI)
8230 10:05:55.462517 u2DelayCellOfst[10]=7 cells (2 PI)
8231 10:05:55.465593 u2DelayCellOfst[11]=0 cells (0 PI)
8232 10:05:55.468988 u2DelayCellOfst[12]=10 cells (3 PI)
8233 10:05:55.472269 u2DelayCellOfst[13]=10 cells (3 PI)
8234 10:05:55.475661 u2DelayCellOfst[14]=14 cells (4 PI)
8235 10:05:55.479033 u2DelayCellOfst[15]=10 cells (3 PI)
8236 10:05:55.485473 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8237 10:05:55.489141 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8238 10:05:55.489254 DramC Write-DBI on
8239 10:05:55.489347 ==
8240 10:05:55.492073 Dram Type= 6, Freq= 0, CH_0, rank 1
8241 10:05:55.498861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8242 10:05:55.498962 ==
8243 10:05:55.499074
8244 10:05:55.499164
8245 10:05:55.499265 TX Vref Scan disable
8246 10:05:55.503148 == TX Byte 0 ==
8247 10:05:55.506576 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8248 10:05:55.509750 == TX Byte 1 ==
8249 10:05:55.512727 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8250 10:05:55.516029 DramC Write-DBI off
8251 10:05:55.516153
8252 10:05:55.516246 [DATLAT]
8253 10:05:55.516349 Freq=1600, CH0 RK1
8254 10:05:55.516446
8255 10:05:55.519475 DATLAT Default: 0xf
8256 10:05:55.519559 0, 0xFFFF, sum = 0
8257 10:05:55.522575 1, 0xFFFF, sum = 0
8258 10:05:55.525959 2, 0xFFFF, sum = 0
8259 10:05:55.526083 3, 0xFFFF, sum = 0
8260 10:05:55.529484 4, 0xFFFF, sum = 0
8261 10:05:55.529593 5, 0xFFFF, sum = 0
8262 10:05:55.532937 6, 0xFFFF, sum = 0
8263 10:05:55.533039 7, 0xFFFF, sum = 0
8264 10:05:55.535680 8, 0xFFFF, sum = 0
8265 10:05:55.535758 9, 0xFFFF, sum = 0
8266 10:05:55.539329 10, 0xFFFF, sum = 0
8267 10:05:55.539458 11, 0xFFFF, sum = 0
8268 10:05:55.543086 12, 0xFFFF, sum = 0
8269 10:05:55.543190 13, 0xFFFF, sum = 0
8270 10:05:55.546080 14, 0x0, sum = 1
8271 10:05:55.546188 15, 0x0, sum = 2
8272 10:05:55.549541 16, 0x0, sum = 3
8273 10:05:55.549655 17, 0x0, sum = 4
8274 10:05:55.552774 best_step = 15
8275 10:05:55.552862
8276 10:05:55.552933 ==
8277 10:05:55.555804 Dram Type= 6, Freq= 0, CH_0, rank 1
8278 10:05:55.558970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 10:05:55.559075 ==
8280 10:05:55.562551 RX Vref Scan: 0
8281 10:05:55.562669
8282 10:05:55.562759 RX Vref 0 -> 0, step: 1
8283 10:05:55.562850
8284 10:05:55.566025 RX Delay 11 -> 252, step: 4
8285 10:05:55.572609 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8286 10:05:55.575545 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8287 10:05:55.578986 iDelay=195, Bit 2, Center 124 (67 ~ 182) 116
8288 10:05:55.582307 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8289 10:05:55.585843 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8290 10:05:55.589131 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8291 10:05:55.595820 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
8292 10:05:55.598850 iDelay=195, Bit 7, Center 134 (79 ~ 190) 112
8293 10:05:55.601929 iDelay=195, Bit 8, Center 114 (63 ~ 166) 104
8294 10:05:55.605649 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8295 10:05:55.612174 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8296 10:05:55.615688 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8297 10:05:55.618788 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8298 10:05:55.622082 iDelay=195, Bit 13, Center 130 (75 ~ 186) 112
8299 10:05:55.625441 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8300 10:05:55.631840 iDelay=195, Bit 15, Center 132 (75 ~ 190) 116
8301 10:05:55.631918 ==
8302 10:05:55.635312 Dram Type= 6, Freq= 0, CH_0, rank 1
8303 10:05:55.638680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 10:05:55.638760 ==
8305 10:05:55.638856 DQS Delay:
8306 10:05:55.641679 DQS0 = 0, DQS1 = 0
8307 10:05:55.641760 DQM Delay:
8308 10:05:55.645401 DQM0 = 127, DQM1 = 123
8309 10:05:55.645482 DQ Delay:
8310 10:05:55.648352 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8311 10:05:55.652114 DQ4 =126, DQ5 =116, DQ6 =136, DQ7 =134
8312 10:05:55.655100 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =116
8313 10:05:55.658695 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =132
8314 10:05:55.658798
8315 10:05:55.661698
8316 10:05:55.661780
8317 10:05:55.661862 [DramC_TX_OE_Calibration] TA2
8318 10:05:55.664705 Original DQ_B0 (3 6) =30, OEN = 27
8319 10:05:55.668330 Original DQ_B1 (3 6) =30, OEN = 27
8320 10:05:55.671842 24, 0x0, End_B0=24 End_B1=24
8321 10:05:55.674819 25, 0x0, End_B0=25 End_B1=25
8322 10:05:55.677985 26, 0x0, End_B0=26 End_B1=26
8323 10:05:55.678069 27, 0x0, End_B0=27 End_B1=27
8324 10:05:55.681754 28, 0x0, End_B0=28 End_B1=28
8325 10:05:55.685222 29, 0x0, End_B0=29 End_B1=29
8326 10:05:55.688586 30, 0x0, End_B0=30 End_B1=30
8327 10:05:55.691472 31, 0x4141, End_B0=30 End_B1=30
8328 10:05:55.691556 Byte0 end_step=30 best_step=27
8329 10:05:55.695079 Byte1 end_step=30 best_step=27
8330 10:05:55.698198 Byte0 TX OE(2T, 0.5T) = (3, 3)
8331 10:05:55.701374 Byte1 TX OE(2T, 0.5T) = (3, 3)
8332 10:05:55.701458
8333 10:05:55.701540
8334 10:05:55.708442 [DQSOSCAuto] RK1, (LSB)MR18= 0x160b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8335 10:05:55.711484 CH0 RK1: MR19=303, MR18=160B
8336 10:05:55.718344 CH0_RK1: MR19=0x303, MR18=0x160B, DQSOSC=398, MR23=63, INC=23, DEC=15
8337 10:05:55.721986 [RxdqsGatingPostProcess] freq 1600
8338 10:05:55.728547 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8339 10:05:55.731473 best DQS0 dly(2T, 0.5T) = (1, 1)
8340 10:05:55.735056 best DQS1 dly(2T, 0.5T) = (1, 1)
8341 10:05:55.735138 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8342 10:05:55.738029 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8343 10:05:55.741460 best DQS0 dly(2T, 0.5T) = (1, 1)
8344 10:05:55.744994 best DQS1 dly(2T, 0.5T) = (1, 1)
8345 10:05:55.747861 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8346 10:05:55.751329 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8347 10:05:55.754950 Pre-setting of DQS Precalculation
8348 10:05:55.761199 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8349 10:05:55.761282 ==
8350 10:05:55.764732 Dram Type= 6, Freq= 0, CH_1, rank 0
8351 10:05:55.767769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 10:05:55.767867 ==
8353 10:05:55.774784 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8354 10:05:55.777998 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8355 10:05:55.780839 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8356 10:05:55.787601 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8357 10:05:55.796355 [CA 0] Center 43 (15~72) winsize 58
8358 10:05:55.799779 [CA 1] Center 43 (14~72) winsize 59
8359 10:05:55.802925 [CA 2] Center 38 (9~67) winsize 59
8360 10:05:55.805944 [CA 3] Center 36 (7~66) winsize 60
8361 10:05:55.809536 [CA 4] Center 38 (9~68) winsize 60
8362 10:05:55.812525 [CA 5] Center 37 (8~66) winsize 59
8363 10:05:55.812604
8364 10:05:55.815688 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8365 10:05:55.815766
8366 10:05:55.819040 [CATrainingPosCal] consider 1 rank data
8367 10:05:55.822579 u2DelayCellTimex100 = 275/100 ps
8368 10:05:55.825914 CA0 delay=43 (15~72),Diff = 7 PI (24 cell)
8369 10:05:55.832497 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8370 10:05:55.835986 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8371 10:05:55.839026 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8372 10:05:55.842577 CA4 delay=38 (9~68),Diff = 2 PI (7 cell)
8373 10:05:55.845925 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8374 10:05:55.846004
8375 10:05:55.848774 CA PerBit enable=1, Macro0, CA PI delay=36
8376 10:05:55.848853
8377 10:05:55.852152 [CBTSetCACLKResult] CA Dly = 36
8378 10:05:55.855410 CS Dly: 9 (0~40)
8379 10:05:55.859036 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8380 10:05:55.862094 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8381 10:05:55.862174 ==
8382 10:05:55.865338 Dram Type= 6, Freq= 0, CH_1, rank 1
8383 10:05:55.868891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8384 10:05:55.872483 ==
8385 10:05:55.875544 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8386 10:05:55.879124 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8387 10:05:55.886017 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8388 10:05:55.888893 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8389 10:05:55.899166 [CA 0] Center 43 (14~72) winsize 59
8390 10:05:55.902809 [CA 1] Center 43 (14~72) winsize 59
8391 10:05:55.905622 [CA 2] Center 38 (9~67) winsize 59
8392 10:05:55.909375 [CA 3] Center 37 (8~67) winsize 60
8393 10:05:55.912264 [CA 4] Center 38 (9~68) winsize 60
8394 10:05:55.915882 [CA 5] Center 36 (7~66) winsize 60
8395 10:05:55.915962
8396 10:05:55.919690 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8397 10:05:55.919770
8398 10:05:55.922768 [CATrainingPosCal] consider 2 rank data
8399 10:05:55.926054 u2DelayCellTimex100 = 275/100 ps
8400 10:05:55.928966 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8401 10:05:55.935480 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8402 10:05:55.939280 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8403 10:05:55.942188 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8404 10:05:55.945823 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8405 10:05:55.949364 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8406 10:05:55.949446
8407 10:05:55.952170 CA PerBit enable=1, Macro0, CA PI delay=37
8408 10:05:55.952251
8409 10:05:55.955621 [CBTSetCACLKResult] CA Dly = 37
8410 10:05:55.958739 CS Dly: 11 (0~44)
8411 10:05:55.962366 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8412 10:05:55.965307 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8413 10:05:55.965390
8414 10:05:55.968837 ----->DramcWriteLeveling(PI) begin...
8415 10:05:55.968920 ==
8416 10:05:55.972660 Dram Type= 6, Freq= 0, CH_1, rank 0
8417 10:05:55.978711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8418 10:05:55.978797 ==
8419 10:05:55.982097 Write leveling (Byte 0): 26 => 26
8420 10:05:55.982179 Write leveling (Byte 1): 28 => 28
8421 10:05:55.985418 DramcWriteLeveling(PI) end<-----
8422 10:05:55.985500
8423 10:05:55.985565 ==
8424 10:05:55.988932 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 10:05:55.995065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 10:05:55.995148 ==
8427 10:05:55.998504 [Gating] SW mode calibration
8428 10:05:56.004908 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8429 10:05:56.008506 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8430 10:05:56.015272 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 10:05:56.018335 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 10:05:56.021781 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 10:05:56.028219 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 10:05:56.031459 1 4 16 | B1->B0 | 2e2e 2525 | 0 0 | (1 1) (0 0)
8435 10:05:56.035064 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8436 10:05:56.041725 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8437 10:05:56.045172 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8438 10:05:56.047973 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8439 10:05:56.055121 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8440 10:05:56.058501 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8441 10:05:56.061486 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8442 10:05:56.068254 1 5 16 | B1->B0 | 3030 3333 | 1 0 | (1 0) (0 1)
8443 10:05:56.071225 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8444 10:05:56.074981 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8445 10:05:56.081618 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8446 10:05:56.084677 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8447 10:05:56.088079 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 10:05:56.094590 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 10:05:56.097997 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 10:05:56.101395 1 6 16 | B1->B0 | 3b3b 3333 | 1 1 | (0 0) (0 0)
8451 10:05:56.107678 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8452 10:05:56.111180 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8453 10:05:56.114795 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8454 10:05:56.117777 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8455 10:05:56.124370 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 10:05:56.127542 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 10:05:56.130880 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8458 10:05:56.137773 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8459 10:05:56.141197 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8460 10:05:56.144606 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 10:05:56.150902 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 10:05:56.154167 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 10:05:56.157804 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 10:05:56.164325 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 10:05:56.167962 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 10:05:56.170969 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 10:05:56.177584 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 10:05:56.181207 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 10:05:56.184326 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 10:05:56.190689 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 10:05:56.194328 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 10:05:56.197234 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 10:05:56.204004 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8474 10:05:56.207483 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8475 10:05:56.210832 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8476 10:05:56.214306 Total UI for P1: 0, mck2ui 16
8477 10:05:56.217707 best dqsien dly found for B0: ( 1, 9, 14)
8478 10:05:56.221483 Total UI for P1: 0, mck2ui 16
8479 10:05:56.224546 best dqsien dly found for B1: ( 1, 9, 14)
8480 10:05:56.227340 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8481 10:05:56.230473 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8482 10:05:56.230562
8483 10:05:56.233845 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8484 10:05:56.240820 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8485 10:05:56.240923 [Gating] SW calibration Done
8486 10:05:56.244425 ==
8487 10:05:56.244575 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 10:05:56.250787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 10:05:56.250908 ==
8490 10:05:56.251061 RX Vref Scan: 0
8491 10:05:56.251125
8492 10:05:56.253900 RX Vref 0 -> 0, step: 1
8493 10:05:56.254011
8494 10:05:56.257710 RX Delay 0 -> 252, step: 8
8495 10:05:56.260814 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8496 10:05:56.264244 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8497 10:05:56.267115 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8498 10:05:56.273848 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8499 10:05:56.277403 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8500 10:05:56.280671 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8501 10:05:56.284115 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8502 10:05:56.287205 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8503 10:05:56.293852 iDelay=208, Bit 8, Center 115 (64 ~ 167) 104
8504 10:05:56.297369 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8505 10:05:56.300446 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8506 10:05:56.303835 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8507 10:05:56.306695 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8508 10:05:56.313613 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8509 10:05:56.317141 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8510 10:05:56.320180 iDelay=208, Bit 15, Center 131 (80 ~ 183) 104
8511 10:05:56.320260 ==
8512 10:05:56.323655 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 10:05:56.326730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 10:05:56.330450 ==
8515 10:05:56.330865 DQS Delay:
8516 10:05:56.331275 DQS0 = 0, DQS1 = 0
8517 10:05:56.334197 DQM Delay:
8518 10:05:56.334659 DQM0 = 135, DQM1 = 127
8519 10:05:56.337138 DQ Delay:
8520 10:05:56.340771 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8521 10:05:56.344298 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =131
8522 10:05:56.347099 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8523 10:05:56.350356 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8524 10:05:56.350780
8525 10:05:56.351133
8526 10:05:56.351501 ==
8527 10:05:56.353979 Dram Type= 6, Freq= 0, CH_1, rank 0
8528 10:05:56.356803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8529 10:05:56.357262 ==
8530 10:05:56.357599
8531 10:05:56.360378
8532 10:05:56.360803 TX Vref Scan disable
8533 10:05:56.363815 == TX Byte 0 ==
8534 10:05:56.367461 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8535 10:05:56.370497 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8536 10:05:56.373645 == TX Byte 1 ==
8537 10:05:56.377050 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8538 10:05:56.380053 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8539 10:05:56.380480 ==
8540 10:05:56.383756 Dram Type= 6, Freq= 0, CH_1, rank 0
8541 10:05:56.390397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8542 10:05:56.390915 ==
8543 10:05:56.401767
8544 10:05:56.404835 TX Vref early break, caculate TX vref
8545 10:05:56.408022 TX Vref=16, minBit 8, minWin=20, winSum=357
8546 10:05:56.411782 TX Vref=18, minBit 8, minWin=21, winSum=371
8547 10:05:56.414967 TX Vref=20, minBit 5, minWin=22, winSum=378
8548 10:05:56.417882 TX Vref=22, minBit 8, minWin=22, winSum=387
8549 10:05:56.421470 TX Vref=24, minBit 5, minWin=24, winSum=398
8550 10:05:56.428510 TX Vref=26, minBit 8, minWin=24, winSum=412
8551 10:05:56.431669 TX Vref=28, minBit 9, minWin=25, winSum=420
8552 10:05:56.435004 TX Vref=30, minBit 1, minWin=25, winSum=418
8553 10:05:56.438080 TX Vref=32, minBit 11, minWin=24, winSum=409
8554 10:05:56.441771 TX Vref=34, minBit 8, minWin=23, winSum=396
8555 10:05:56.448330 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 28
8556 10:05:56.448756
8557 10:05:56.451708 Final TX Range 0 Vref 28
8558 10:05:56.452134
8559 10:05:56.452472 ==
8560 10:05:56.454759 Dram Type= 6, Freq= 0, CH_1, rank 0
8561 10:05:56.458100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8562 10:05:56.458528 ==
8563 10:05:56.458865
8564 10:05:56.459176
8565 10:05:56.461682 TX Vref Scan disable
8566 10:05:56.468067 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8567 10:05:56.468560 == TX Byte 0 ==
8568 10:05:56.471010 u2DelayCellOfst[0]=17 cells (5 PI)
8569 10:05:56.474767 u2DelayCellOfst[1]=10 cells (3 PI)
8570 10:05:56.478262 u2DelayCellOfst[2]=0 cells (0 PI)
8571 10:05:56.480998 u2DelayCellOfst[3]=7 cells (2 PI)
8572 10:05:56.484142 u2DelayCellOfst[4]=7 cells (2 PI)
8573 10:05:56.487717 u2DelayCellOfst[5]=21 cells (6 PI)
8574 10:05:56.490770 u2DelayCellOfst[6]=17 cells (5 PI)
8575 10:05:56.494177 u2DelayCellOfst[7]=7 cells (2 PI)
8576 10:05:56.497884 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8577 10:05:56.500740 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8578 10:05:56.504284 == TX Byte 1 ==
8579 10:05:56.504714 u2DelayCellOfst[8]=0 cells (0 PI)
8580 10:05:56.507752 u2DelayCellOfst[9]=7 cells (2 PI)
8581 10:05:56.511010 u2DelayCellOfst[10]=10 cells (3 PI)
8582 10:05:56.514018 u2DelayCellOfst[11]=7 cells (2 PI)
8583 10:05:56.517418 u2DelayCellOfst[12]=14 cells (4 PI)
8584 10:05:56.520940 u2DelayCellOfst[13]=14 cells (4 PI)
8585 10:05:56.524358 u2DelayCellOfst[14]=17 cells (5 PI)
8586 10:05:56.527841 u2DelayCellOfst[15]=17 cells (5 PI)
8587 10:05:56.530799 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8588 10:05:56.538152 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8589 10:05:56.538691 DramC Write-DBI on
8590 10:05:56.539032 ==
8591 10:05:56.540857 Dram Type= 6, Freq= 0, CH_1, rank 0
8592 10:05:56.544606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8593 10:05:56.547509 ==
8594 10:05:56.547932
8595 10:05:56.548263
8596 10:05:56.548577 TX Vref Scan disable
8597 10:05:56.551185 == TX Byte 0 ==
8598 10:05:56.554169 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8599 10:05:56.557645 == TX Byte 1 ==
8600 10:05:56.560995 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8601 10:05:56.564389 DramC Write-DBI off
8602 10:05:56.564819
8603 10:05:56.565190 [DATLAT]
8604 10:05:56.565535 Freq=1600, CH1 RK0
8605 10:05:56.565870
8606 10:05:56.568052 DATLAT Default: 0xf
8607 10:05:56.568475 0, 0xFFFF, sum = 0
8608 10:05:56.571066 1, 0xFFFF, sum = 0
8609 10:05:56.574578 2, 0xFFFF, sum = 0
8610 10:05:56.575059 3, 0xFFFF, sum = 0
8611 10:05:56.577538 4, 0xFFFF, sum = 0
8612 10:05:56.577967 5, 0xFFFF, sum = 0
8613 10:05:56.580956 6, 0xFFFF, sum = 0
8614 10:05:56.581406 7, 0xFFFF, sum = 0
8615 10:05:56.584339 8, 0xFFFF, sum = 0
8616 10:05:56.584886 9, 0xFFFF, sum = 0
8617 10:05:56.587072 10, 0xFFFF, sum = 0
8618 10:05:56.587544 11, 0xFFFF, sum = 0
8619 10:05:56.590751 12, 0xFFFF, sum = 0
8620 10:05:56.591181 13, 0xFFFF, sum = 0
8621 10:05:56.593902 14, 0x0, sum = 1
8622 10:05:56.594329 15, 0x0, sum = 2
8623 10:05:56.597464 16, 0x0, sum = 3
8624 10:05:56.597908 17, 0x0, sum = 4
8625 10:05:56.600484 best_step = 15
8626 10:05:56.600967
8627 10:05:56.601345 ==
8628 10:05:56.604046 Dram Type= 6, Freq= 0, CH_1, rank 0
8629 10:05:56.607596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8630 10:05:56.608014 ==
8631 10:05:56.610456 RX Vref Scan: 1
8632 10:05:56.610872
8633 10:05:56.611200 Set Vref Range= 24 -> 127
8634 10:05:56.611560
8635 10:05:56.614261 RX Vref 24 -> 127, step: 1
8636 10:05:56.614678
8637 10:05:56.617555 RX Delay 19 -> 252, step: 4
8638 10:05:56.617976
8639 10:05:56.620565 Set Vref, RX VrefLevel [Byte0]: 24
8640 10:05:56.623632 [Byte1]: 24
8641 10:05:56.624050
8642 10:05:56.627334 Set Vref, RX VrefLevel [Byte0]: 25
8643 10:05:56.630882 [Byte1]: 25
8644 10:05:56.631293
8645 10:05:56.633834 Set Vref, RX VrefLevel [Byte0]: 26
8646 10:05:56.637157 [Byte1]: 26
8647 10:05:56.641356
8648 10:05:56.641770 Set Vref, RX VrefLevel [Byte0]: 27
8649 10:05:56.644891 [Byte1]: 27
8650 10:05:56.648662
8651 10:05:56.649177 Set Vref, RX VrefLevel [Byte0]: 28
8652 10:05:56.652305 [Byte1]: 28
8653 10:05:56.656301
8654 10:05:56.656713 Set Vref, RX VrefLevel [Byte0]: 29
8655 10:05:56.659762 [Byte1]: 29
8656 10:05:56.664224
8657 10:05:56.664736 Set Vref, RX VrefLevel [Byte0]: 30
8658 10:05:56.667491 [Byte1]: 30
8659 10:05:56.671903
8660 10:05:56.672408 Set Vref, RX VrefLevel [Byte0]: 31
8661 10:05:56.674893 [Byte1]: 31
8662 10:05:56.679023
8663 10:05:56.679566 Set Vref, RX VrefLevel [Byte0]: 32
8664 10:05:56.682792 [Byte1]: 32
8665 10:05:56.686826
8666 10:05:56.687241 Set Vref, RX VrefLevel [Byte0]: 33
8667 10:05:56.689854 [Byte1]: 33
8668 10:05:56.694183
8669 10:05:56.694672 Set Vref, RX VrefLevel [Byte0]: 34
8670 10:05:56.697743 [Byte1]: 34
8671 10:05:56.701931
8672 10:05:56.702350 Set Vref, RX VrefLevel [Byte0]: 35
8673 10:05:56.704784 [Byte1]: 35
8674 10:05:56.709980
8675 10:05:56.710395 Set Vref, RX VrefLevel [Byte0]: 36
8676 10:05:56.713163 [Byte1]: 36
8677 10:05:56.717195
8678 10:05:56.717657 Set Vref, RX VrefLevel [Byte0]: 37
8679 10:05:56.720531 [Byte1]: 37
8680 10:05:56.724745
8681 10:05:56.725203 Set Vref, RX VrefLevel [Byte0]: 38
8682 10:05:56.727518 [Byte1]: 38
8683 10:05:56.732352
8684 10:05:56.732767 Set Vref, RX VrefLevel [Byte0]: 39
8685 10:05:56.735667 [Byte1]: 39
8686 10:05:56.739539
8687 10:05:56.740110 Set Vref, RX VrefLevel [Byte0]: 40
8688 10:05:56.742751 [Byte1]: 40
8689 10:05:56.747420
8690 10:05:56.747934 Set Vref, RX VrefLevel [Byte0]: 41
8691 10:05:56.750413 [Byte1]: 41
8692 10:05:56.755046
8693 10:05:56.755622 Set Vref, RX VrefLevel [Byte0]: 42
8694 10:05:56.758118 [Byte1]: 42
8695 10:05:56.762497
8696 10:05:56.763064 Set Vref, RX VrefLevel [Byte0]: 43
8697 10:05:56.765701 [Byte1]: 43
8698 10:05:56.770010
8699 10:05:56.770476 Set Vref, RX VrefLevel [Byte0]: 44
8700 10:05:56.773684 [Byte1]: 44
8701 10:05:56.777250
8702 10:05:56.777712 Set Vref, RX VrefLevel [Byte0]: 45
8703 10:05:56.780838 [Byte1]: 45
8704 10:05:56.785809
8705 10:05:56.786372 Set Vref, RX VrefLevel [Byte0]: 46
8706 10:05:56.788368 [Byte1]: 46
8707 10:05:56.792634
8708 10:05:56.793224 Set Vref, RX VrefLevel [Byte0]: 47
8709 10:05:56.795860 [Byte1]: 47
8710 10:05:56.800518
8711 10:05:56.800936 Set Vref, RX VrefLevel [Byte0]: 48
8712 10:05:56.803414 [Byte1]: 48
8713 10:05:56.807769
8714 10:05:56.808219 Set Vref, RX VrefLevel [Byte0]: 49
8715 10:05:56.811509 [Byte1]: 49
8716 10:05:56.815243
8717 10:05:56.815870 Set Vref, RX VrefLevel [Byte0]: 50
8718 10:05:56.818598 [Byte1]: 50
8719 10:05:56.822744
8720 10:05:56.823224 Set Vref, RX VrefLevel [Byte0]: 51
8721 10:05:56.826399 [Byte1]: 51
8722 10:05:56.830809
8723 10:05:56.831403 Set Vref, RX VrefLevel [Byte0]: 52
8724 10:05:56.833851 [Byte1]: 52
8725 10:05:56.838200
8726 10:05:56.838667 Set Vref, RX VrefLevel [Byte0]: 53
8727 10:05:56.841530 [Byte1]: 53
8728 10:05:56.845916
8729 10:05:56.846363 Set Vref, RX VrefLevel [Byte0]: 54
8730 10:05:56.848933 [Byte1]: 54
8731 10:05:56.853376
8732 10:05:56.853798 Set Vref, RX VrefLevel [Byte0]: 55
8733 10:05:56.856238 [Byte1]: 55
8734 10:05:56.861063
8735 10:05:56.861529 Set Vref, RX VrefLevel [Byte0]: 56
8736 10:05:56.863963 [Byte1]: 56
8737 10:05:56.868320
8738 10:05:56.868813 Set Vref, RX VrefLevel [Byte0]: 57
8739 10:05:56.871730 [Byte1]: 57
8740 10:05:56.875827
8741 10:05:56.876242 Set Vref, RX VrefLevel [Byte0]: 58
8742 10:05:56.879237 [Byte1]: 58
8743 10:05:56.883951
8744 10:05:56.884410 Set Vref, RX VrefLevel [Byte0]: 59
8745 10:05:56.886729 [Byte1]: 59
8746 10:05:56.890763
8747 10:05:56.894333 Set Vref, RX VrefLevel [Byte0]: 60
8748 10:05:56.897365 [Byte1]: 60
8749 10:05:56.897780
8750 10:05:56.901245 Set Vref, RX VrefLevel [Byte0]: 61
8751 10:05:56.903977 [Byte1]: 61
8752 10:05:56.904414
8753 10:05:56.907712 Set Vref, RX VrefLevel [Byte0]: 62
8754 10:05:56.911122 [Byte1]: 62
8755 10:05:56.911539
8756 10:05:56.914211 Set Vref, RX VrefLevel [Byte0]: 63
8757 10:05:56.917237 [Byte1]: 63
8758 10:05:56.921441
8759 10:05:56.921854 Set Vref, RX VrefLevel [Byte0]: 64
8760 10:05:56.924848 [Byte1]: 64
8761 10:05:56.928915
8762 10:05:56.929487 Set Vref, RX VrefLevel [Byte0]: 65
8763 10:05:56.932413 [Byte1]: 65
8764 10:05:56.936575
8765 10:05:56.937006 Set Vref, RX VrefLevel [Byte0]: 66
8766 10:05:56.939687 [Byte1]: 66
8767 10:05:56.944440
8768 10:05:56.944855 Set Vref, RX VrefLevel [Byte0]: 67
8769 10:05:56.947294 [Byte1]: 67
8770 10:05:56.951709
8771 10:05:56.952247 Set Vref, RX VrefLevel [Byte0]: 68
8772 10:05:56.954954 [Byte1]: 68
8773 10:05:56.959290
8774 10:05:56.959890 Set Vref, RX VrefLevel [Byte0]: 69
8775 10:05:56.962660 [Byte1]: 69
8776 10:05:56.990678
8777 10:05:56.991401 Set Vref, RX VrefLevel [Byte0]: 70
8778 10:05:56.991923 [Byte1]: 70
8779 10:05:56.992313
8780 10:05:56.992617 Set Vref, RX VrefLevel [Byte0]: 71
8781 10:05:56.992909 [Byte1]: 71
8782 10:05:56.993140
8783 10:05:56.993338 Set Vref, RX VrefLevel [Byte0]: 72
8784 10:05:56.993550 [Byte1]: 72
8785 10:05:56.993751
8786 10:05:56.993948 Set Vref, RX VrefLevel [Byte0]: 73
8787 10:05:56.994434 [Byte1]: 73
8788 10:05:56.997219
8789 10:05:56.997540 Final RX Vref Byte 0 = 61 to rank0
8790 10:05:56.999998 Final RX Vref Byte 1 = 56 to rank0
8791 10:05:57.003650 Final RX Vref Byte 0 = 61 to rank1
8792 10:05:57.006835 Final RX Vref Byte 1 = 56 to rank1==
8793 10:05:57.010371 Dram Type= 6, Freq= 0, CH_1, rank 0
8794 10:05:57.017264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8795 10:05:57.017659 ==
8796 10:05:57.017946 DQS Delay:
8797 10:05:57.020247 DQS0 = 0, DQS1 = 0
8798 10:05:57.020571 DQM Delay:
8799 10:05:57.020806 DQM0 = 131, DQM1 = 124
8800 10:05:57.023683 DQ Delay:
8801 10:05:57.026661 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8802 10:05:57.030010 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8803 10:05:57.033811 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8804 10:05:57.036865 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8805 10:05:57.037253
8806 10:05:57.037560
8807 10:05:57.037843
8808 10:05:57.040485 [DramC_TX_OE_Calibration] TA2
8809 10:05:57.043710 Original DQ_B0 (3 6) =30, OEN = 27
8810 10:05:57.047073 Original DQ_B1 (3 6) =30, OEN = 27
8811 10:05:57.050508 24, 0x0, End_B0=24 End_B1=24
8812 10:05:57.051103 25, 0x0, End_B0=25 End_B1=25
8813 10:05:57.053393 26, 0x0, End_B0=26 End_B1=26
8814 10:05:57.056640 27, 0x0, End_B0=27 End_B1=27
8815 10:05:57.059864 28, 0x0, End_B0=28 End_B1=28
8816 10:05:57.063930 29, 0x0, End_B0=29 End_B1=29
8817 10:05:57.064362 30, 0x0, End_B0=30 End_B1=30
8818 10:05:57.066634 31, 0x4141, End_B0=30 End_B1=30
8819 10:05:57.069846 Byte0 end_step=30 best_step=27
8820 10:05:57.073320 Byte1 end_step=30 best_step=27
8821 10:05:57.076215 Byte0 TX OE(2T, 0.5T) = (3, 3)
8822 10:05:57.079835 Byte1 TX OE(2T, 0.5T) = (3, 3)
8823 10:05:57.080060
8824 10:05:57.080243
8825 10:05:57.086636 [DQSOSCAuto] RK0, (LSB)MR18= 0x1600, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
8826 10:05:57.089468 CH1 RK0: MR19=303, MR18=1600
8827 10:05:57.096620 CH1_RK0: MR19=0x303, MR18=0x1600, DQSOSC=398, MR23=63, INC=23, DEC=15
8828 10:05:57.096745
8829 10:05:57.099540 ----->DramcWriteLeveling(PI) begin...
8830 10:05:57.099621 ==
8831 10:05:57.102462 Dram Type= 6, Freq= 0, CH_1, rank 1
8832 10:05:57.106133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8833 10:05:57.106251 ==
8834 10:05:57.109603 Write leveling (Byte 0): 26 => 26
8835 10:05:57.112645 Write leveling (Byte 1): 26 => 26
8836 10:05:57.116406 DramcWriteLeveling(PI) end<-----
8837 10:05:57.116477
8838 10:05:57.116539 ==
8839 10:05:57.119571 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 10:05:57.122584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 10:05:57.122666 ==
8842 10:05:57.126082 [Gating] SW mode calibration
8843 10:05:57.132753 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8844 10:05:57.139243 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8845 10:05:57.142092 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 10:05:57.149206 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 10:05:57.153405 1 4 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
8848 10:05:57.156209 1 4 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8849 10:05:57.162863 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8850 10:05:57.166018 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8851 10:05:57.168940 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8852 10:05:57.175783 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8853 10:05:57.179042 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8854 10:05:57.182426 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8855 10:05:57.188977 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
8856 10:05:57.192129 1 5 12 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
8857 10:05:57.195919 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8858 10:05:57.202107 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8859 10:05:57.205683 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 10:05:57.208781 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 10:05:57.215434 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8862 10:05:57.219089 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8863 10:05:57.222148 1 6 8 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8864 10:05:57.228341 1 6 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8865 10:05:57.231828 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 10:05:57.235328 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 10:05:57.241690 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 10:05:57.245341 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 10:05:57.248338 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 10:05:57.255187 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 10:05:57.258102 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8872 10:05:57.261973 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8873 10:05:57.268452 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8874 10:05:57.271265 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 10:05:57.274799 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 10:05:57.281588 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 10:05:57.284662 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 10:05:57.288262 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 10:05:57.294948 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 10:05:57.297905 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 10:05:57.301286 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 10:05:57.304668 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 10:05:57.311385 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 10:05:57.314938 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 10:05:57.317980 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 10:05:57.324531 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8887 10:05:57.327608 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8888 10:05:57.331241 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8889 10:05:57.334933 Total UI for P1: 0, mck2ui 16
8890 10:05:57.337828 best dqsien dly found for B0: ( 1, 9, 6)
8891 10:05:57.344214 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8892 10:05:57.348021 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8893 10:05:57.350881 Total UI for P1: 0, mck2ui 16
8894 10:05:57.354173 best dqsien dly found for B1: ( 1, 9, 14)
8895 10:05:57.357985 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8896 10:05:57.360917 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8897 10:05:57.361356
8898 10:05:57.364546 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8899 10:05:57.367775 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8900 10:05:57.370998 [Gating] SW calibration Done
8901 10:05:57.371480 ==
8902 10:05:57.374249 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 10:05:57.377778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 10:05:57.380925 ==
8905 10:05:57.381488 RX Vref Scan: 0
8906 10:05:57.381964
8907 10:05:57.384203 RX Vref 0 -> 0, step: 1
8908 10:05:57.384637
8909 10:05:57.387565 RX Delay 0 -> 252, step: 8
8910 10:05:57.390989 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8911 10:05:57.394374 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8912 10:05:57.397853 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8913 10:05:57.400566 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8914 10:05:57.407246 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8915 10:05:57.411060 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8916 10:05:57.413919 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8917 10:05:57.417161 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8918 10:05:57.420692 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8919 10:05:57.427232 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8920 10:05:57.430341 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8921 10:05:57.433898 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8922 10:05:57.436829 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8923 10:05:57.440813 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8924 10:05:57.447402 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8925 10:05:57.450296 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8926 10:05:57.450720 ==
8927 10:05:57.453497 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 10:05:57.456989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 10:05:57.457413 ==
8930 10:05:57.460874 DQS Delay:
8931 10:05:57.461294 DQS0 = 0, DQS1 = 0
8932 10:05:57.461726 DQM Delay:
8933 10:05:57.463898 DQM0 = 132, DQM1 = 128
8934 10:05:57.464356 DQ Delay:
8935 10:05:57.467522 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8936 10:05:57.470369 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8937 10:05:57.476755 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8938 10:05:57.480036 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8939 10:05:57.480218
8940 10:05:57.480360
8941 10:05:57.480494 ==
8942 10:05:57.482974 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 10:05:57.486547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 10:05:57.486707 ==
8945 10:05:57.486826
8946 10:05:57.486935
8947 10:05:57.490114 TX Vref Scan disable
8948 10:05:57.493287 == TX Byte 0 ==
8949 10:05:57.496466 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8950 10:05:57.499830 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8951 10:05:57.503173 == TX Byte 1 ==
8952 10:05:57.506687 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8953 10:05:57.509454 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8954 10:05:57.509562 ==
8955 10:05:57.512834 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 10:05:57.516442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 10:05:57.520000 ==
8958 10:05:57.531872
8959 10:05:57.535062 TX Vref early break, caculate TX vref
8960 10:05:57.538521 TX Vref=16, minBit 8, minWin=22, winSum=378
8961 10:05:57.542072 TX Vref=18, minBit 1, minWin=23, winSum=386
8962 10:05:57.545037 TX Vref=20, minBit 5, minWin=24, winSum=398
8963 10:05:57.548660 TX Vref=22, minBit 1, minWin=24, winSum=405
8964 10:05:57.551814 TX Vref=24, minBit 15, minWin=24, winSum=417
8965 10:05:57.558289 TX Vref=26, minBit 8, minWin=25, winSum=423
8966 10:05:57.561843 TX Vref=28, minBit 0, minWin=26, winSum=427
8967 10:05:57.564874 TX Vref=30, minBit 1, minWin=25, winSum=424
8968 10:05:57.568342 TX Vref=32, minBit 0, minWin=25, winSum=416
8969 10:05:57.571343 TX Vref=34, minBit 5, minWin=24, winSum=409
8970 10:05:57.575032 TX Vref=36, minBit 0, minWin=24, winSum=400
8971 10:05:57.581550 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8972 10:05:57.582076
8973 10:05:57.584537 Final TX Range 0 Vref 28
8974 10:05:57.584960
8975 10:05:57.585294 ==
8976 10:05:57.587934 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 10:05:57.591300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 10:05:57.591792 ==
8979 10:05:57.592131
8980 10:05:57.594927
8981 10:05:57.595378 TX Vref Scan disable
8982 10:05:57.600964 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8983 10:05:57.601377 == TX Byte 0 ==
8984 10:05:57.604347 u2DelayCellOfst[0]=17 cells (5 PI)
8985 10:05:57.607791 u2DelayCellOfst[1]=14 cells (4 PI)
8986 10:05:57.611445 u2DelayCellOfst[2]=0 cells (0 PI)
8987 10:05:57.614813 u2DelayCellOfst[3]=7 cells (2 PI)
8988 10:05:57.618149 u2DelayCellOfst[4]=7 cells (2 PI)
8989 10:05:57.621528 u2DelayCellOfst[5]=17 cells (5 PI)
8990 10:05:57.624841 u2DelayCellOfst[6]=17 cells (5 PI)
8991 10:05:57.628222 u2DelayCellOfst[7]=3 cells (1 PI)
8992 10:05:57.631668 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8993 10:05:57.634834 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8994 10:05:57.637843 == TX Byte 1 ==
8995 10:05:57.641393 u2DelayCellOfst[8]=0 cells (0 PI)
8996 10:05:57.641809 u2DelayCellOfst[9]=3 cells (1 PI)
8997 10:05:57.644621 u2DelayCellOfst[10]=10 cells (3 PI)
8998 10:05:57.648107 u2DelayCellOfst[11]=7 cells (2 PI)
8999 10:05:57.651151 u2DelayCellOfst[12]=14 cells (4 PI)
9000 10:05:57.654312 u2DelayCellOfst[13]=14 cells (4 PI)
9001 10:05:57.657863 u2DelayCellOfst[14]=17 cells (5 PI)
9002 10:05:57.661948 u2DelayCellOfst[15]=14 cells (4 PI)
9003 10:05:57.664525 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9004 10:05:57.671136 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9005 10:05:57.671673 DramC Write-DBI on
9006 10:05:57.672015 ==
9007 10:05:57.674646 Dram Type= 6, Freq= 0, CH_1, rank 1
9008 10:05:57.681364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9009 10:05:57.681793 ==
9010 10:05:57.682132
9011 10:05:57.682443
9012 10:05:57.682745 TX Vref Scan disable
9013 10:05:57.684888 == TX Byte 0 ==
9014 10:05:57.688329 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9015 10:05:57.691264 == TX Byte 1 ==
9016 10:05:57.695450 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9017 10:05:57.698023 DramC Write-DBI off
9018 10:05:57.698446
9019 10:05:57.698777 [DATLAT]
9020 10:05:57.699087 Freq=1600, CH1 RK1
9021 10:05:57.699429
9022 10:05:57.701543 DATLAT Default: 0xf
9023 10:05:57.704822 0, 0xFFFF, sum = 0
9024 10:05:57.705252 1, 0xFFFF, sum = 0
9025 10:05:57.708353 2, 0xFFFF, sum = 0
9026 10:05:57.708920 3, 0xFFFF, sum = 0
9027 10:05:57.710904 4, 0xFFFF, sum = 0
9028 10:05:57.711470 5, 0xFFFF, sum = 0
9029 10:05:57.714634 6, 0xFFFF, sum = 0
9030 10:05:57.715109 7, 0xFFFF, sum = 0
9031 10:05:57.718251 8, 0xFFFF, sum = 0
9032 10:05:57.718682 9, 0xFFFF, sum = 0
9033 10:05:57.720988 10, 0xFFFF, sum = 0
9034 10:05:57.721507 11, 0xFFFF, sum = 0
9035 10:05:57.724453 12, 0xFFFF, sum = 0
9036 10:05:57.724855 13, 0xFFFF, sum = 0
9037 10:05:57.727766 14, 0x0, sum = 1
9038 10:05:57.728196 15, 0x0, sum = 2
9039 10:05:57.730981 16, 0x0, sum = 3
9040 10:05:57.731454 17, 0x0, sum = 4
9041 10:05:57.734421 best_step = 15
9042 10:05:57.734850
9043 10:05:57.735184 ==
9044 10:05:57.738038 Dram Type= 6, Freq= 0, CH_1, rank 1
9045 10:05:57.741605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9046 10:05:57.742033 ==
9047 10:05:57.744667 RX Vref Scan: 0
9048 10:05:57.745088
9049 10:05:57.745427 RX Vref 0 -> 0, step: 1
9050 10:05:57.745738
9051 10:05:57.748322 RX Delay 11 -> 252, step: 4
9052 10:05:57.751040 iDelay=191, Bit 0, Center 132 (79 ~ 186) 108
9053 10:05:57.757841 iDelay=191, Bit 1, Center 126 (75 ~ 178) 104
9054 10:05:57.761549 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
9055 10:05:57.764441 iDelay=191, Bit 3, Center 128 (75 ~ 182) 108
9056 10:05:57.768059 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
9057 10:05:57.771072 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
9058 10:05:57.777719 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
9059 10:05:57.780680 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
9060 10:05:57.784044 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
9061 10:05:57.787675 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
9062 10:05:57.791283 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
9063 10:05:57.797603 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
9064 10:05:57.800572 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
9065 10:05:57.804014 iDelay=191, Bit 13, Center 136 (83 ~ 190) 108
9066 10:05:57.807532 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
9067 10:05:57.814412 iDelay=191, Bit 15, Center 136 (83 ~ 190) 108
9068 10:05:57.814861 ==
9069 10:05:57.817353 Dram Type= 6, Freq= 0, CH_1, rank 1
9070 10:05:57.820968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9071 10:05:57.821384 ==
9072 10:05:57.821713 DQS Delay:
9073 10:05:57.824551 DQS0 = 0, DQS1 = 0
9074 10:05:57.825128 DQM Delay:
9075 10:05:57.828001 DQM0 = 129, DQM1 = 126
9076 10:05:57.828591 DQ Delay:
9077 10:05:57.830732 DQ0 =132, DQ1 =126, DQ2 =118, DQ3 =128
9078 10:05:57.834438 DQ4 =128, DQ5 =142, DQ6 =138, DQ7 =126
9079 10:05:57.837764 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9080 10:05:57.841238 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =136
9081 10:05:57.841851
9082 10:05:57.842327
9083 10:05:57.842801
9084 10:05:57.844475 [DramC_TX_OE_Calibration] TA2
9085 10:05:57.847465 Original DQ_B0 (3 6) =30, OEN = 27
9086 10:05:57.850429 Original DQ_B1 (3 6) =30, OEN = 27
9087 10:05:57.854372 24, 0x0, End_B0=24 End_B1=24
9088 10:05:57.857238 25, 0x0, End_B0=25 End_B1=25
9089 10:05:57.857665 26, 0x0, End_B0=26 End_B1=26
9090 10:05:57.860904 27, 0x0, End_B0=27 End_B1=27
9091 10:05:57.863903 28, 0x0, End_B0=28 End_B1=28
9092 10:05:57.867330 29, 0x0, End_B0=29 End_B1=29
9093 10:05:57.870758 30, 0x0, End_B0=30 End_B1=30
9094 10:05:57.871181 31, 0x5151, End_B0=30 End_B1=30
9095 10:05:57.873831 Byte0 end_step=30 best_step=27
9096 10:05:57.877390 Byte1 end_step=30 best_step=27
9097 10:05:57.880807 Byte0 TX OE(2T, 0.5T) = (3, 3)
9098 10:05:57.883926 Byte1 TX OE(2T, 0.5T) = (3, 3)
9099 10:05:57.884480
9100 10:05:57.884970
9101 10:05:57.890284 [DQSOSCAuto] RK1, (LSB)MR18= 0xc11, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
9102 10:05:57.893732 CH1 RK1: MR19=303, MR18=C11
9103 10:05:57.900682 CH1_RK1: MR19=0x303, MR18=0xC11, DQSOSC=401, MR23=63, INC=22, DEC=15
9104 10:05:57.903824 [RxdqsGatingPostProcess] freq 1600
9105 10:05:57.910381 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9106 10:05:57.910832 best DQS0 dly(2T, 0.5T) = (1, 1)
9107 10:05:57.913979 best DQS1 dly(2T, 0.5T) = (1, 1)
9108 10:05:57.916975 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9109 10:05:57.920260 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9110 10:05:57.923538 best DQS0 dly(2T, 0.5T) = (1, 1)
9111 10:05:57.926635 best DQS1 dly(2T, 0.5T) = (1, 1)
9112 10:05:57.930368 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9113 10:05:57.933753 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9114 10:05:57.936678 Pre-setting of DQS Precalculation
9115 10:05:57.940583 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9116 10:05:57.950425 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9117 10:05:57.956907 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9118 10:05:57.957335
9119 10:05:57.957671
9120 10:05:57.960107 [Calibration Summary] 3200 Mbps
9121 10:05:57.960531 CH 0, Rank 0
9122 10:05:57.963210 SW Impedance : PASS
9123 10:05:57.963668 DUTY Scan : NO K
9124 10:05:57.966947 ZQ Calibration : PASS
9125 10:05:57.969939 Jitter Meter : NO K
9126 10:05:57.970364 CBT Training : PASS
9127 10:05:57.972933 Write leveling : PASS
9128 10:05:57.976292 RX DQS gating : PASS
9129 10:05:57.976716 RX DQ/DQS(RDDQC) : PASS
9130 10:05:57.979456 TX DQ/DQS : PASS
9131 10:05:57.982852 RX DATLAT : PASS
9132 10:05:57.983276 RX DQ/DQS(Engine): PASS
9133 10:05:57.986447 TX OE : PASS
9134 10:05:57.986876 All Pass.
9135 10:05:57.987210
9136 10:05:57.990123 CH 0, Rank 1
9137 10:05:57.990545 SW Impedance : PASS
9138 10:05:57.992983 DUTY Scan : NO K
9139 10:05:57.996065 ZQ Calibration : PASS
9140 10:05:57.996488 Jitter Meter : NO K
9141 10:05:57.999823 CBT Training : PASS
9142 10:05:58.000248 Write leveling : PASS
9143 10:05:58.002775 RX DQS gating : PASS
9144 10:05:58.006147 RX DQ/DQS(RDDQC) : PASS
9145 10:05:58.006568 TX DQ/DQS : PASS
9146 10:05:58.009471 RX DATLAT : PASS
9147 10:05:58.012982 RX DQ/DQS(Engine): PASS
9148 10:05:58.013404 TX OE : PASS
9149 10:05:58.016742 All Pass.
9150 10:05:58.017163
9151 10:05:58.017499 CH 1, Rank 0
9152 10:05:58.019544 SW Impedance : PASS
9153 10:05:58.019965 DUTY Scan : NO K
9154 10:05:58.022918 ZQ Calibration : PASS
9155 10:05:58.026458 Jitter Meter : NO K
9156 10:05:58.026884 CBT Training : PASS
9157 10:05:58.029407 Write leveling : PASS
9158 10:05:58.032879 RX DQS gating : PASS
9159 10:05:58.033417 RX DQ/DQS(RDDQC) : PASS
9160 10:05:58.036032 TX DQ/DQS : PASS
9161 10:05:58.039125 RX DATLAT : PASS
9162 10:05:58.039697 RX DQ/DQS(Engine): PASS
9163 10:05:58.042526 TX OE : PASS
9164 10:05:58.042947 All Pass.
9165 10:05:58.043303
9166 10:05:58.046138 CH 1, Rank 1
9167 10:05:58.046700 SW Impedance : PASS
9168 10:05:58.049737 DUTY Scan : NO K
9169 10:05:58.052685 ZQ Calibration : PASS
9170 10:05:58.053107 Jitter Meter : NO K
9171 10:05:58.056031 CBT Training : PASS
9172 10:05:58.059599 Write leveling : PASS
9173 10:05:58.060261 RX DQS gating : PASS
9174 10:05:58.062530 RX DQ/DQS(RDDQC) : PASS
9175 10:05:58.063065 TX DQ/DQS : PASS
9176 10:05:58.066075 RX DATLAT : PASS
9177 10:05:58.069298 RX DQ/DQS(Engine): PASS
9178 10:05:58.069797 TX OE : PASS
9179 10:05:58.072376 All Pass.
9180 10:05:58.072817
9181 10:05:58.073149 DramC Write-DBI on
9182 10:05:58.076024 PER_BANK_REFRESH: Hybrid Mode
9183 10:05:58.078817 TX_TRACKING: ON
9184 10:05:58.086054 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9185 10:05:58.095845 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9186 10:05:58.102100 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9187 10:05:58.105270 [FAST_K] Save calibration result to emmc
9188 10:05:58.108667 sync common calibartion params.
9189 10:05:58.109121 sync cbt_mode0:1, 1:1
9190 10:05:58.112590 dram_init: ddr_geometry: 2
9191 10:05:58.115690 dram_init: ddr_geometry: 2
9192 10:05:58.119071 dram_init: ddr_geometry: 2
9193 10:05:58.119617 0:dram_rank_size:100000000
9194 10:05:58.121967 1:dram_rank_size:100000000
9195 10:05:58.129319 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9196 10:05:58.129744 DFS_SHUFFLE_HW_MODE: ON
9197 10:05:58.132307 dramc_set_vcore_voltage set vcore to 725000
9198 10:05:58.135771 Read voltage for 1600, 0
9199 10:05:58.136277 Vio18 = 0
9200 10:05:58.138854 Vcore = 725000
9201 10:05:58.139291 Vdram = 0
9202 10:05:58.139668 Vddq = 0
9203 10:05:58.142310 Vmddr = 0
9204 10:05:58.142777 switch to 3200 Mbps bootup
9205 10:05:58.145750 [DramcRunTimeConfig]
9206 10:05:58.146292 PHYPLL
9207 10:05:58.149181 DPM_CONTROL_AFTERK: ON
9208 10:05:58.149600 PER_BANK_REFRESH: ON
9209 10:05:58.152103 REFRESH_OVERHEAD_REDUCTION: ON
9210 10:05:58.155689 CMD_PICG_NEW_MODE: OFF
9211 10:05:58.156103 XRTWTW_NEW_MODE: ON
9212 10:05:58.158777 XRTRTR_NEW_MODE: ON
9213 10:05:58.159191 TX_TRACKING: ON
9214 10:05:58.162247 RDSEL_TRACKING: OFF
9215 10:05:58.165542 DQS Precalculation for DVFS: ON
9216 10:05:58.165958 RX_TRACKING: OFF
9217 10:05:58.169348 HW_GATING DBG: ON
9218 10:05:58.169876 ZQCS_ENABLE_LP4: ON
9219 10:05:58.172073 RX_PICG_NEW_MODE: ON
9220 10:05:58.172578 TX_PICG_NEW_MODE: ON
9221 10:05:58.175849 ENABLE_RX_DCM_DPHY: ON
9222 10:05:58.178820 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9223 10:05:58.181730 DUMMY_READ_FOR_TRACKING: OFF
9224 10:05:58.186103 !!! SPM_CONTROL_AFTERK: OFF
9225 10:05:58.186560 !!! SPM could not control APHY
9226 10:05:58.188995 IMPEDANCE_TRACKING: ON
9227 10:05:58.189662 TEMP_SENSOR: ON
9228 10:05:58.192296 HW_SAVE_FOR_SR: OFF
9229 10:05:58.195093 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9230 10:05:58.197965 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9231 10:05:58.201465 Read ODT Tracking: ON
9232 10:05:58.201597 Refresh Rate DeBounce: ON
9233 10:05:58.204987 DFS_NO_QUEUE_FLUSH: ON
9234 10:05:58.208026 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9235 10:05:58.211435 ENABLE_DFS_RUNTIME_MRW: OFF
9236 10:05:58.211573 DDR_RESERVE_NEW_MODE: ON
9237 10:05:58.214627 MR_CBT_SWITCH_FREQ: ON
9238 10:05:58.217737 =========================
9239 10:05:58.236232 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9240 10:05:58.239195 dram_init: ddr_geometry: 2
9241 10:05:58.257649 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9242 10:05:58.261348 dram_init: dram init end (result: 0)
9243 10:05:58.268005 DRAM-K: Full calibration passed in 24582 msecs
9244 10:05:58.270880 MRC: failed to locate region type 0.
9245 10:05:58.271472 DRAM rank0 size:0x100000000,
9246 10:05:58.274325 DRAM rank1 size=0x100000000
9247 10:05:58.284228 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9248 10:05:58.290470 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9249 10:05:58.297270 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9250 10:05:58.304193 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9251 10:05:58.307152 DRAM rank0 size:0x100000000,
9252 10:05:58.310189 DRAM rank1 size=0x100000000
9253 10:05:58.310464 CBMEM:
9254 10:05:58.313749 IMD: root @ 0xfffff000 254 entries.
9255 10:05:58.316814 IMD: root @ 0xffffec00 62 entries.
9256 10:05:58.320377 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9257 10:05:58.323495 WARNING: RO_VPD is uninitialized or empty.
9258 10:05:58.330378 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9259 10:05:58.337250 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9260 10:05:58.349921 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9261 10:05:58.361756 BS: romstage times (exec / console): total (unknown) / 24088 ms
9262 10:05:58.361909
9263 10:05:58.362005
9264 10:05:58.371541 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9265 10:05:58.374752 ARM64: Exception handlers installed.
9266 10:05:58.378386 ARM64: Testing exception
9267 10:05:58.381368 ARM64: Done test exception
9268 10:05:58.381449 Enumerating buses...
9269 10:05:58.384912 Show all devs... Before device enumeration.
9270 10:05:58.387944 Root Device: enabled 1
9271 10:05:58.391365 CPU_CLUSTER: 0: enabled 1
9272 10:05:58.391450 CPU: 00: enabled 1
9273 10:05:58.394797 Compare with tree...
9274 10:05:58.394880 Root Device: enabled 1
9275 10:05:58.397992 CPU_CLUSTER: 0: enabled 1
9276 10:05:58.401451 CPU: 00: enabled 1
9277 10:05:58.401535 Root Device scanning...
9278 10:05:58.404937 scan_static_bus for Root Device
9279 10:05:58.408072 CPU_CLUSTER: 0 enabled
9280 10:05:58.411524 scan_static_bus for Root Device done
9281 10:05:58.415218 scan_bus: bus Root Device finished in 8 msecs
9282 10:05:58.415365 done
9283 10:05:58.421201 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9284 10:05:58.424775 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9285 10:05:58.431547 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9286 10:05:58.434960 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9287 10:05:58.437718 Allocating resources...
9288 10:05:58.441250 Reading resources...
9289 10:05:58.444638 Root Device read_resources bus 0 link: 0
9290 10:05:58.444822 DRAM rank0 size:0x100000000,
9291 10:05:58.447614 DRAM rank1 size=0x100000000
9292 10:05:58.451184 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9293 10:05:58.454362 CPU: 00 missing read_resources
9294 10:05:58.461725 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9295 10:05:58.464770 Root Device read_resources bus 0 link: 0 done
9296 10:05:58.465167 Done reading resources.
9297 10:05:58.471424 Show resources in subtree (Root Device)...After reading.
9298 10:05:58.474672 Root Device child on link 0 CPU_CLUSTER: 0
9299 10:05:58.477534 CPU_CLUSTER: 0 child on link 0 CPU: 00
9300 10:05:58.487800 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9301 10:05:58.488137 CPU: 00
9302 10:05:58.490688 Root Device assign_resources, bus 0 link: 0
9303 10:05:58.494354 CPU_CLUSTER: 0 missing set_resources
9304 10:05:58.500758 Root Device assign_resources, bus 0 link: 0 done
9305 10:05:58.501082 Done setting resources.
9306 10:05:58.507385 Show resources in subtree (Root Device)...After assigning values.
9307 10:05:58.511075 Root Device child on link 0 CPU_CLUSTER: 0
9308 10:05:58.514186 CPU_CLUSTER: 0 child on link 0 CPU: 00
9309 10:05:58.524582 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9310 10:05:58.524913 CPU: 00
9311 10:05:58.527747 Done allocating resources.
9312 10:05:58.531407 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9313 10:05:58.533955 Enabling resources...
9314 10:05:58.534274 done.
9315 10:05:58.540706 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9316 10:05:58.541041 Initializing devices...
9317 10:05:58.544106 Root Device init
9318 10:05:58.544433 init hardware done!
9319 10:05:58.547654 0x00000018: ctrlr->caps
9320 10:05:58.550677 52.000 MHz: ctrlr->f_max
9321 10:05:58.551006 0.400 MHz: ctrlr->f_min
9322 10:05:58.554449 0x40ff8080: ctrlr->voltages
9323 10:05:58.554770 sclk: 390625
9324 10:05:58.557559 Bus Width = 1
9325 10:05:58.557878 sclk: 390625
9326 10:05:58.560548 Bus Width = 1
9327 10:05:58.560874 Early init status = 3
9328 10:05:58.567404 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9329 10:05:58.570827 in-header: 03 fc 00 00 01 00 00 00
9330 10:05:58.571141 in-data: 00
9331 10:05:58.577458 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9332 10:05:58.580645 in-header: 03 fd 00 00 00 00 00 00
9333 10:05:58.583729 in-data:
9334 10:05:58.587393 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9335 10:05:58.590473 in-header: 03 fc 00 00 01 00 00 00
9336 10:05:58.593913 in-data: 00
9337 10:05:58.597412 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9338 10:05:58.601698 in-header: 03 fd 00 00 00 00 00 00
9339 10:05:58.605319 in-data:
9340 10:05:58.608252 [SSUSB] Setting up USB HOST controller...
9341 10:05:58.611573 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9342 10:05:58.614674 [SSUSB] phy power-on done.
9343 10:05:58.617996 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9344 10:05:58.625208 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9345 10:05:58.628001 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9346 10:05:58.634615 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9347 10:05:58.641373 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9348 10:05:58.647889 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9349 10:05:58.654796 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9350 10:05:58.661438 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9351 10:05:58.664494 SPM: binary array size = 0x9dc
9352 10:05:58.668046 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9353 10:05:58.674837 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9354 10:05:58.681069 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9355 10:05:58.684715 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9356 10:05:58.691124 configure_display: Starting display init
9357 10:05:58.724523 anx7625_power_on_init: Init interface.
9358 10:05:58.727979 anx7625_disable_pd_protocol: Disabled PD feature.
9359 10:05:58.731110 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9360 10:05:58.759419 anx7625_start_dp_work: Secure OCM version=00
9361 10:05:58.762439 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9362 10:05:58.777542 sp_tx_get_edid_block: EDID Block = 1
9363 10:05:58.879719 Extracted contents:
9364 10:05:58.883119 header: 00 ff ff ff ff ff ff 00
9365 10:05:58.886628 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9366 10:05:58.889701 version: 01 04
9367 10:05:58.893001 basic params: 95 1f 11 78 0a
9368 10:05:58.896626 chroma info: 76 90 94 55 54 90 27 21 50 54
9369 10:05:58.899342 established: 00 00 00
9370 10:05:58.906448 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9371 10:05:58.909425 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9372 10:05:58.916140 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9373 10:05:58.922581 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9374 10:05:58.929790 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9375 10:05:58.932797 extensions: 00
9376 10:05:58.932910 checksum: fb
9377 10:05:58.933017
9378 10:05:58.935797 Manufacturer: IVO Model 57d Serial Number 0
9379 10:05:58.939058 Made week 0 of 2020
9380 10:05:58.939173 EDID version: 1.4
9381 10:05:58.942736 Digital display
9382 10:05:58.945812 6 bits per primary color channel
9383 10:05:58.945926 DisplayPort interface
9384 10:05:58.948977 Maximum image size: 31 cm x 17 cm
9385 10:05:58.952420 Gamma: 220%
9386 10:05:58.952527 Check DPMS levels
9387 10:05:58.956021 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9388 10:05:58.962522 First detailed timing is preferred timing
9389 10:05:58.962605 Established timings supported:
9390 10:05:58.965817 Standard timings supported:
9391 10:05:58.968850 Detailed timings
9392 10:05:58.972587 Hex of detail: 383680a07038204018303c0035ae10000019
9393 10:05:58.979003 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9394 10:05:58.982395 0780 0798 07c8 0820 hborder 0
9395 10:05:58.985250 0438 043b 0447 0458 vborder 0
9396 10:05:58.988765 -hsync -vsync
9397 10:05:58.988910 Did detailed timing
9398 10:05:58.995497 Hex of detail: 000000000000000000000000000000000000
9399 10:05:58.998851 Manufacturer-specified data, tag 0
9400 10:05:59.002319 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9401 10:05:59.005330 ASCII string: InfoVision
9402 10:05:59.008657 Hex of detail: 000000fe00523134304e574635205248200a
9403 10:05:59.011878 ASCII string: R140NWF5 RH
9404 10:05:59.012013 Checksum
9405 10:05:59.015667 Checksum: 0xfb (valid)
9406 10:05:59.018627 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9407 10:05:59.021884 DSI data_rate: 832800000 bps
9408 10:05:59.028802 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9409 10:05:59.031878 anx7625_parse_edid: pixelclock(138800).
9410 10:05:59.035265 hactive(1920), hsync(48), hfp(24), hbp(88)
9411 10:05:59.038329 vactive(1080), vsync(12), vfp(3), vbp(17)
9412 10:05:59.041576 anx7625_dsi_config: config dsi.
9413 10:05:59.048233 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9414 10:05:59.061670 anx7625_dsi_config: success to config DSI
9415 10:05:59.064988 anx7625_dp_start: MIPI phy setup OK.
9416 10:05:59.068553 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9417 10:05:59.072125 mtk_ddp_mode_set invalid vrefresh 60
9418 10:05:59.074842 main_disp_path_setup
9419 10:05:59.075069 ovl_layer_smi_id_en
9420 10:05:59.078454 ovl_layer_smi_id_en
9421 10:05:59.078570 ccorr_config
9422 10:05:59.078687 aal_config
9423 10:05:59.081469 gamma_config
9424 10:05:59.081556 postmask_config
9425 10:05:59.084880 dither_config
9426 10:05:59.088173 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9427 10:05:59.094701 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9428 10:05:59.098336 Root Device init finished in 551 msecs
9429 10:05:59.101352 CPU_CLUSTER: 0 init
9430 10:05:59.108405 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9431 10:05:59.114446 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9432 10:05:59.114601 APU_MBOX 0x190000b0 = 0x10001
9433 10:05:59.118337 APU_MBOX 0x190001b0 = 0x10001
9434 10:05:59.121239 APU_MBOX 0x190005b0 = 0x10001
9435 10:05:59.124875 APU_MBOX 0x190006b0 = 0x10001
9436 10:05:59.131182 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9437 10:05:59.141054 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9438 10:05:59.153612 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9439 10:05:59.160275 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9440 10:05:59.171804 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9441 10:05:59.180648 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9442 10:05:59.184394 CPU_CLUSTER: 0 init finished in 81 msecs
9443 10:05:59.187333 Devices initialized
9444 10:05:59.190827 Show all devs... After init.
9445 10:05:59.191065 Root Device: enabled 1
9446 10:05:59.194174 CPU_CLUSTER: 0: enabled 1
9447 10:05:59.197031 CPU: 00: enabled 1
9448 10:05:59.200760 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9449 10:05:59.204316 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9450 10:05:59.207072 ELOG: NV offset 0x57f000 size 0x1000
9451 10:05:59.214305 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9452 10:05:59.220521 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9453 10:05:59.223502 ELOG: Event(17) added with size 13 at 2023-06-10 10:06:01 UTC
9454 10:05:59.230038 out: cmd=0x121: 03 db 21 01 00 00 00 00
9455 10:05:59.233566 in-header: 03 ce 00 00 2c 00 00 00
9456 10:05:59.243491 in-data: 91 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9457 10:05:59.250323 ELOG: Event(A1) added with size 10 at 2023-06-10 10:06:01 UTC
9458 10:05:59.257009 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9459 10:05:59.263711 ELOG: Event(A0) added with size 9 at 2023-06-10 10:06:01 UTC
9460 10:05:59.266664 elog_add_boot_reason: Logged dev mode boot
9461 10:05:59.273775 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9462 10:05:59.274027 Finalize devices...
9463 10:05:59.277018 Devices finalized
9464 10:05:59.279970 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9465 10:05:59.283608 Writing coreboot table at 0xffe64000
9466 10:05:59.286522 0. 000000000010a000-0000000000113fff: RAMSTAGE
9467 10:05:59.293503 1. 0000000040000000-00000000400fffff: RAM
9468 10:05:59.296881 2. 0000000040100000-000000004032afff: RAMSTAGE
9469 10:05:59.300016 3. 000000004032b000-00000000545fffff: RAM
9470 10:05:59.303161 4. 0000000054600000-000000005465ffff: BL31
9471 10:05:59.306671 5. 0000000054660000-00000000ffe63fff: RAM
9472 10:05:59.313051 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9473 10:05:59.316454 7. 0000000100000000-000000023fffffff: RAM
9474 10:05:59.319790 Passing 5 GPIOs to payload:
9475 10:05:59.322910 NAME | PORT | POLARITY | VALUE
9476 10:05:59.329829 EC in RW | 0x000000aa | low | undefined
9477 10:05:59.332878 EC interrupt | 0x00000005 | low | undefined
9478 10:05:59.336587 TPM interrupt | 0x000000ab | high | undefined
9479 10:05:59.343073 SD card detect | 0x00000011 | high | undefined
9480 10:05:59.346382 speaker enable | 0x00000093 | high | undefined
9481 10:05:59.349508 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9482 10:05:59.353388 in-header: 03 f9 00 00 02 00 00 00
9483 10:05:59.355832 in-data: 02 00
9484 10:05:59.359552 ADC[4]: Raw value=900590 ID=7
9485 10:05:59.359792 ADC[3]: Raw value=213336 ID=1
9486 10:05:59.363267 RAM Code: 0x71
9487 10:05:59.366301 ADC[6]: Raw value=74926 ID=0
9488 10:05:59.366541 ADC[5]: Raw value=212229 ID=1
9489 10:05:59.369315 SKU Code: 0x1
9490 10:05:59.376282 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9491 10:05:59.376523 coreboot table: 964 bytes.
9492 10:05:59.379107 IMD ROOT 0. 0xfffff000 0x00001000
9493 10:05:59.382738 IMD SMALL 1. 0xffffe000 0x00001000
9494 10:05:59.385727 RO MCACHE 2. 0xffffc000 0x00001104
9495 10:05:59.389314 CONSOLE 3. 0xfff7c000 0x00080000
9496 10:05:59.392491 FMAP 4. 0xfff7b000 0x00000452
9497 10:05:59.396007 TIME STAMP 5. 0xfff7a000 0x00000910
9498 10:05:59.399011 VBOOT WORK 6. 0xfff66000 0x00014000
9499 10:05:59.402452 RAMOOPS 7. 0xffe66000 0x00100000
9500 10:05:59.405949 COREBOOT 8. 0xffe64000 0x00002000
9501 10:05:59.409109 IMD small region:
9502 10:05:59.412610 IMD ROOT 0. 0xffffec00 0x00000400
9503 10:05:59.415455 VPD 1. 0xffffeba0 0x0000004c
9504 10:05:59.419169 MMC STATUS 2. 0xffffeb80 0x00000004
9505 10:05:59.422558 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9506 10:05:59.425537 Probing TPM: done!
9507 10:05:59.429071 Connected to device vid:did:rid of 1ae0:0028:00
9508 10:05:59.440277 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9509 10:05:59.443114 Initialized TPM device CR50 revision 0
9510 10:05:59.446727 Checking cr50 for pending updates
9511 10:05:59.450503 Reading cr50 TPM mode
9512 10:05:59.459192 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9513 10:05:59.465433 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9514 10:05:59.505566 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9515 10:05:59.509151 Checking segment from ROM address 0x40100000
9516 10:05:59.512291 Checking segment from ROM address 0x4010001c
9517 10:05:59.519485 Loading segment from ROM address 0x40100000
9518 10:05:59.519586 code (compression=0)
9519 10:05:59.529345 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9520 10:05:59.535922 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9521 10:05:59.536007 it's not compressed!
9522 10:05:59.542679 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9523 10:05:59.549621 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9524 10:05:59.566327 Loading segment from ROM address 0x4010001c
9525 10:05:59.566794 Entry Point 0x80000000
9526 10:05:59.570061 Loaded segments
9527 10:05:59.573117 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9528 10:05:59.579482 Jumping to boot code at 0x80000000(0xffe64000)
9529 10:05:59.586400 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9530 10:05:59.593277 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9531 10:05:59.600852 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9532 10:05:59.604312 Checking segment from ROM address 0x40100000
9533 10:05:59.607729 Checking segment from ROM address 0x4010001c
9534 10:05:59.613973 Loading segment from ROM address 0x40100000
9535 10:05:59.614579 code (compression=1)
9536 10:05:59.620967 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9537 10:05:59.630932 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9538 10:05:59.631471 using LZMA
9539 10:05:59.639136 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9540 10:05:59.645633 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9541 10:05:59.649415 Loading segment from ROM address 0x4010001c
9542 10:05:59.649828 Entry Point 0x54601000
9543 10:05:59.653265 Loaded segments
9544 10:05:59.655918 NOTICE: MT8192 bl31_setup
9545 10:05:59.663066 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9546 10:05:59.666209 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9547 10:05:59.669767 WARNING: region 0:
9548 10:05:59.673268 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9549 10:05:59.673696 WARNING: region 1:
9550 10:05:59.679492 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9551 10:05:59.683063 WARNING: region 2:
9552 10:05:59.686682 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9553 10:05:59.690122 WARNING: region 3:
9554 10:05:59.692940 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9555 10:05:59.696347 WARNING: region 4:
9556 10:05:59.702740 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9557 10:05:59.703158 WARNING: region 5:
9558 10:05:59.706362 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9559 10:05:59.709513 WARNING: region 6:
9560 10:05:59.712951 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9561 10:05:59.713347 WARNING: region 7:
9562 10:05:59.719394 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9563 10:05:59.726452 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9564 10:05:59.729993 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9565 10:05:59.732824 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9566 10:05:59.739799 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9567 10:05:59.742773 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9568 10:05:59.746294 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9569 10:05:59.752892 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9570 10:05:59.756548 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9571 10:05:59.759654 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9572 10:05:59.766552 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9573 10:05:59.769845 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9574 10:05:59.776548 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9575 10:05:59.779543 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9576 10:05:59.783133 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9577 10:05:59.790335 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9578 10:05:59.793224 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9579 10:05:59.796632 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9580 10:05:59.802931 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9581 10:05:59.806702 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9582 10:05:59.809744 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9583 10:05:59.816801 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9584 10:05:59.819712 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9585 10:05:59.826218 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9586 10:05:59.829811 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9587 10:05:59.836355 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9588 10:05:59.839649 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9589 10:05:59.843290 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9590 10:05:59.849909 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9591 10:05:59.853487 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9592 10:05:59.856453 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9593 10:05:59.863107 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9594 10:05:59.866856 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9595 10:05:59.869811 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9596 10:05:59.876668 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9597 10:05:59.879653 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9598 10:05:59.883447 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9599 10:05:59.886675 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9600 10:05:59.893385 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9601 10:05:59.896462 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9602 10:05:59.899775 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9603 10:05:59.903101 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9604 10:05:59.909380 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9605 10:05:59.913378 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9606 10:05:59.916417 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9607 10:05:59.920116 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9608 10:05:59.926388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9609 10:05:59.929900 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9610 10:05:59.932923 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9611 10:05:59.939567 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9612 10:05:59.943092 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9613 10:05:59.949879 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9614 10:05:59.952627 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9615 10:05:59.956250 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9616 10:05:59.962740 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9617 10:05:59.966387 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9618 10:05:59.973082 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9619 10:05:59.976457 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9620 10:05:59.979550 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9621 10:05:59.986722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9622 10:05:59.989299 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9623 10:05:59.996027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9624 10:05:59.999560 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9625 10:06:00.005969 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9626 10:06:00.009637 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9627 10:06:00.015932 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9628 10:06:00.019563 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9629 10:06:00.023139 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9630 10:06:00.029678 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9631 10:06:00.032803 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9632 10:06:00.039321 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9633 10:06:00.042337 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9634 10:06:00.049731 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9635 10:06:00.053119 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9636 10:06:00.055989 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9637 10:06:00.062869 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9638 10:06:00.065952 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9639 10:06:00.072619 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9640 10:06:00.075699 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9641 10:06:00.082706 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9642 10:06:00.086565 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9643 10:06:00.093123 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9644 10:06:00.096257 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9645 10:06:00.100016 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9646 10:06:00.106441 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9647 10:06:00.109796 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9648 10:06:00.116505 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9649 10:06:00.119912 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9650 10:06:00.122781 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9651 10:06:00.129369 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9652 10:06:00.132964 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9653 10:06:00.139792 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9654 10:06:00.142660 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9655 10:06:00.149879 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9656 10:06:00.152733 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9657 10:06:00.159426 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9658 10:06:00.162923 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9659 10:06:00.166476 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9660 10:06:00.169434 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9661 10:06:00.176241 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9662 10:06:00.179591 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9663 10:06:00.182494 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9664 10:06:00.189232 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9665 10:06:00.192439 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9666 10:06:00.196020 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9667 10:06:00.202739 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9668 10:06:00.205826 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9669 10:06:00.212805 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9670 10:06:00.215734 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9671 10:06:00.219128 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9672 10:06:00.226322 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9673 10:06:00.229467 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9674 10:06:00.236718 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9675 10:06:00.239472 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9676 10:06:00.243063 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9677 10:06:00.250223 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9678 10:06:00.252964 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9679 10:06:00.256126 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9680 10:06:00.263139 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9681 10:06:00.266334 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9682 10:06:00.269392 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9683 10:06:00.276361 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9684 10:06:00.279851 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9685 10:06:00.282805 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9686 10:06:00.286400 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9687 10:06:00.293306 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9688 10:06:00.295994 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9689 10:06:00.299517 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9690 10:06:00.306407 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9691 10:06:00.309336 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9692 10:06:00.316286 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9693 10:06:00.319896 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9694 10:06:00.322574 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9695 10:06:00.329386 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9696 10:06:00.333443 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9697 10:06:00.339751 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9698 10:06:00.342530 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9699 10:06:00.345965 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9700 10:06:00.352815 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9701 10:06:00.356577 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9702 10:06:00.363114 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9703 10:06:00.366593 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9704 10:06:00.369490 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9705 10:06:00.376307 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9706 10:06:00.379127 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9707 10:06:00.382740 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9708 10:06:00.389555 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9709 10:06:00.393094 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9710 10:06:00.399043 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9711 10:06:00.402479 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9712 10:06:00.406237 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9713 10:06:00.412689 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9714 10:06:00.415929 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9715 10:06:00.422933 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9716 10:06:00.425599 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9717 10:06:00.429077 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9718 10:06:00.436095 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9719 10:06:00.439045 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9720 10:06:00.445752 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9721 10:06:00.449030 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9722 10:06:00.452563 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9723 10:06:00.458658 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9724 10:06:00.462151 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9725 10:06:00.468698 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9726 10:06:00.472246 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9727 10:06:00.475732 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9728 10:06:00.482083 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9729 10:06:00.485128 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9730 10:06:00.488717 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9731 10:06:00.495218 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9732 10:06:00.498181 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9733 10:06:00.504972 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9734 10:06:00.508565 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9735 10:06:00.511607 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9736 10:06:00.518310 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9737 10:06:00.521874 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9738 10:06:00.528215 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9739 10:06:00.531415 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9740 10:06:00.534981 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9741 10:06:00.541489 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9742 10:06:00.545186 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9743 10:06:00.548644 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9744 10:06:00.555071 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9745 10:06:00.558560 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9746 10:06:00.564866 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9747 10:06:00.568460 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9748 10:06:00.571515 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9749 10:06:00.578074 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9750 10:06:00.581479 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9751 10:06:00.588234 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9752 10:06:00.591892 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9753 10:06:00.594758 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9754 10:06:00.601356 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9755 10:06:00.605016 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9756 10:06:00.611625 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9757 10:06:00.615425 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9758 10:06:00.621479 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9759 10:06:00.625048 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9760 10:06:00.628784 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9761 10:06:00.635059 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9762 10:06:00.638052 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9763 10:06:00.645463 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9764 10:06:00.648167 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9765 10:06:00.651719 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9766 10:06:00.658299 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9767 10:06:00.661575 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9768 10:06:00.667977 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9769 10:06:00.671568 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9770 10:06:00.678293 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9771 10:06:00.681728 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9772 10:06:00.685087 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9773 10:06:00.691620 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9774 10:06:00.694773 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9775 10:06:00.701613 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9776 10:06:00.704557 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9777 10:06:00.707869 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9778 10:06:00.714358 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9779 10:06:00.718140 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9780 10:06:00.724299 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9781 10:06:00.727854 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9782 10:06:00.734172 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9783 10:06:00.737212 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9784 10:06:00.740686 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9785 10:06:00.747615 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9786 10:06:00.751040 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9787 10:06:00.757382 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9788 10:06:00.760831 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9789 10:06:00.767699 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9790 10:06:00.770560 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9791 10:06:00.773858 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9792 10:06:00.780566 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9793 10:06:00.784129 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9794 10:06:00.787624 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9795 10:06:00.791157 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9796 10:06:00.793957 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9797 10:06:00.800642 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9798 10:06:00.803753 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9799 10:06:00.810309 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9800 10:06:00.813806 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9801 10:06:00.817328 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9802 10:06:00.823569 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9803 10:06:00.827316 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9804 10:06:00.830364 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9805 10:06:00.837639 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9806 10:06:00.840493 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9807 10:06:00.844173 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9808 10:06:00.850344 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9809 10:06:00.853851 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9810 10:06:00.860735 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9811 10:06:00.863676 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9812 10:06:00.867185 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9813 10:06:00.873555 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9814 10:06:00.877242 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9815 10:06:00.884135 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9816 10:06:00.887249 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9817 10:06:00.890243 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9818 10:06:00.897339 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9819 10:06:00.900334 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9820 10:06:00.903836 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9821 10:06:00.910433 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9822 10:06:00.914010 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9823 10:06:00.916847 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9824 10:06:00.923573 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9825 10:06:00.927266 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9826 10:06:00.930188 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9827 10:06:00.936867 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9828 10:06:00.940415 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9829 10:06:00.946863 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9830 10:06:00.949749 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9831 10:06:00.953071 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9832 10:06:00.959749 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9833 10:06:00.962997 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9834 10:06:00.966615 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9835 10:06:00.970234 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9836 10:06:00.972972 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9837 10:06:00.980209 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9838 10:06:00.982955 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9839 10:06:00.986861 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9840 10:06:00.989871 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9841 10:06:00.996306 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9842 10:06:00.999737 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9843 10:06:01.002844 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9844 10:06:01.009538 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9845 10:06:01.012881 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9846 10:06:01.016582 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9847 10:06:01.022781 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9848 10:06:01.026014 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9849 10:06:01.032764 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9850 10:06:01.036256 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9851 10:06:01.043066 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9852 10:06:01.045980 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9853 10:06:01.049514 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9854 10:06:01.055700 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9855 10:06:01.059418 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9856 10:06:01.066443 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9857 10:06:01.069374 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9858 10:06:01.072827 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9859 10:06:01.078878 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9860 10:06:01.082728 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9861 10:06:01.085903 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9862 10:06:01.092745 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9863 10:06:01.095956 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9864 10:06:01.102488 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9865 10:06:01.106104 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9866 10:06:01.112283 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9867 10:06:01.115734 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9868 10:06:01.118912 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9869 10:06:01.125490 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9870 10:06:01.128869 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9871 10:06:01.135675 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9872 10:06:01.139237 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9873 10:06:01.142119 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9874 10:06:01.149019 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9875 10:06:01.152460 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9876 10:06:01.158941 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9877 10:06:01.162499 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9878 10:06:01.165392 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9879 10:06:01.172648 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9880 10:06:01.175527 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9881 10:06:01.182402 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9882 10:06:01.185567 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9883 10:06:01.192608 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9884 10:06:01.195331 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9885 10:06:01.199147 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9886 10:06:01.205624 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9887 10:06:01.208852 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9888 10:06:01.215438 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9889 10:06:01.218875 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9890 10:06:01.222135 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9891 10:06:01.228749 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9892 10:06:01.232051 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9893 10:06:01.238717 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9894 10:06:01.241599 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9895 10:06:01.245171 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9896 10:06:01.251902 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9897 10:06:01.255553 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9898 10:06:01.261650 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9899 10:06:01.265028 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9900 10:06:01.268364 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9901 10:06:01.275218 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9902 10:06:01.278948 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9903 10:06:01.284968 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9904 10:06:01.288357 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9905 10:06:01.295207 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9906 10:06:01.298378 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9907 10:06:01.301794 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9908 10:06:01.308568 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9909 10:06:01.311501 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9910 10:06:01.318685 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9911 10:06:01.321468 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9912 10:06:01.325349 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9913 10:06:01.331897 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9914 10:06:01.334954 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9915 10:06:01.341388 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9916 10:06:01.344894 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9917 10:06:01.347906 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9918 10:06:01.354997 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9919 10:06:01.357890 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9920 10:06:01.364999 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9921 10:06:01.368076 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9922 10:06:01.374868 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9923 10:06:01.377980 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9924 10:06:01.381177 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9925 10:06:01.387946 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9926 10:06:01.391264 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9927 10:06:01.397855 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9928 10:06:01.401168 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9929 10:06:01.407503 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9930 10:06:01.411084 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9931 10:06:01.417927 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9932 10:06:01.420498 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9933 10:06:01.424074 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9934 10:06:01.430687 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9935 10:06:01.433702 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9936 10:06:01.440844 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9937 10:06:01.443884 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9938 10:06:01.450420 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9939 10:06:01.454148 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9940 10:06:01.457119 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9941 10:06:01.463939 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9942 10:06:01.467152 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9943 10:06:01.474110 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9944 10:06:01.477004 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9945 10:06:01.483621 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9946 10:06:01.487086 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9947 10:06:01.493731 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9948 10:06:01.497245 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9949 10:06:01.500245 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9950 10:06:01.506802 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9951 10:06:01.510296 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9952 10:06:01.516807 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9953 10:06:01.520258 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9954 10:06:01.526850 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9955 10:06:01.530538 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9956 10:06:01.533536 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9957 10:06:01.540142 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9958 10:06:01.543587 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9959 10:06:01.550300 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9960 10:06:01.553246 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9961 10:06:01.559936 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9962 10:06:01.563584 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9963 10:06:01.570231 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9964 10:06:01.573389 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9965 10:06:01.576441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9966 10:06:01.583332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9967 10:06:01.586934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9968 10:06:01.593277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9969 10:06:01.596632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9970 10:06:01.603200 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9971 10:06:01.606614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9972 10:06:01.609599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9973 10:06:01.616565 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9974 10:06:01.619511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9975 10:06:01.626467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9976 10:06:01.629782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9977 10:06:01.636470 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9978 10:06:01.639384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9979 10:06:01.646033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9980 10:06:01.649502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9981 10:06:01.656153 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9982 10:06:01.659215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9983 10:06:01.665944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9984 10:06:01.669464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9985 10:06:01.676289 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9986 10:06:01.679068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9987 10:06:01.685678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9988 10:06:01.689266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9989 10:06:01.695548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9990 10:06:01.698850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9991 10:06:01.705610 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9992 10:06:01.709068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9993 10:06:01.715545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9994 10:06:01.719027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9995 10:06:01.725569 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9996 10:06:01.729151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9997 10:06:01.735529 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9998 10:06:01.735610 INFO: [APUAPC] vio 0
9999 10:06:01.742324 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10000 10:06:01.745889 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10001 10:06:01.748888 INFO: [APUAPC] D0_APC_0: 0x400510
10002 10:06:01.752307 INFO: [APUAPC] D0_APC_1: 0x0
10003 10:06:01.755867 INFO: [APUAPC] D0_APC_2: 0x1540
10004 10:06:01.758828 INFO: [APUAPC] D0_APC_3: 0x0
10005 10:06:01.761964 INFO: [APUAPC] D1_APC_0: 0xffffffff
10006 10:06:01.765562 INFO: [APUAPC] D1_APC_1: 0xffffffff
10007 10:06:01.768665 INFO: [APUAPC] D1_APC_2: 0x3fffff
10008 10:06:01.772405 INFO: [APUAPC] D1_APC_3: 0x0
10009 10:06:01.775444 INFO: [APUAPC] D2_APC_0: 0xffffffff
10010 10:06:01.778846 INFO: [APUAPC] D2_APC_1: 0xffffffff
10011 10:06:01.782019 INFO: [APUAPC] D2_APC_2: 0x3fffff
10012 10:06:01.785602 INFO: [APUAPC] D2_APC_3: 0x0
10013 10:06:01.788762 INFO: [APUAPC] D3_APC_0: 0xffffffff
10014 10:06:01.792157 INFO: [APUAPC] D3_APC_1: 0xffffffff
10015 10:06:01.795697 INFO: [APUAPC] D3_APC_2: 0x3fffff
10016 10:06:01.798561 INFO: [APUAPC] D3_APC_3: 0x0
10017 10:06:01.802502 INFO: [APUAPC] D4_APC_0: 0xffffffff
10018 10:06:01.805424 INFO: [APUAPC] D4_APC_1: 0xffffffff
10019 10:06:01.808452 INFO: [APUAPC] D4_APC_2: 0x3fffff
10020 10:06:01.808533 INFO: [APUAPC] D4_APC_3: 0x0
10021 10:06:01.815406 INFO: [APUAPC] D5_APC_0: 0xffffffff
10022 10:06:01.818312 INFO: [APUAPC] D5_APC_1: 0xffffffff
10023 10:06:01.821904 INFO: [APUAPC] D5_APC_2: 0x3fffff
10024 10:06:01.821985 INFO: [APUAPC] D5_APC_3: 0x0
10025 10:06:01.825305 INFO: [APUAPC] D6_APC_0: 0xffffffff
10026 10:06:01.828457 INFO: [APUAPC] D6_APC_1: 0xffffffff
10027 10:06:01.831768 INFO: [APUAPC] D6_APC_2: 0x3fffff
10028 10:06:01.835229 INFO: [APUAPC] D6_APC_3: 0x0
10029 10:06:01.838668 INFO: [APUAPC] D7_APC_0: 0xffffffff
10030 10:06:01.841763 INFO: [APUAPC] D7_APC_1: 0xffffffff
10031 10:06:01.844896 INFO: [APUAPC] D7_APC_2: 0x3fffff
10032 10:06:01.848462 INFO: [APUAPC] D7_APC_3: 0x0
10033 10:06:01.851558 INFO: [APUAPC] D8_APC_0: 0xffffffff
10034 10:06:01.855022 INFO: [APUAPC] D8_APC_1: 0xffffffff
10035 10:06:01.858306 INFO: [APUAPC] D8_APC_2: 0x3fffff
10036 10:06:01.861947 INFO: [APUAPC] D8_APC_3: 0x0
10037 10:06:01.865019 INFO: [APUAPC] D9_APC_0: 0xffffffff
10038 10:06:01.868187 INFO: [APUAPC] D9_APC_1: 0xffffffff
10039 10:06:01.871708 INFO: [APUAPC] D9_APC_2: 0x3fffff
10040 10:06:01.874719 INFO: [APUAPC] D9_APC_3: 0x0
10041 10:06:01.877991 INFO: [APUAPC] D10_APC_0: 0xffffffff
10042 10:06:01.881472 INFO: [APUAPC] D10_APC_1: 0xffffffff
10043 10:06:01.884927 INFO: [APUAPC] D10_APC_2: 0x3fffff
10044 10:06:01.888069 INFO: [APUAPC] D10_APC_3: 0x0
10045 10:06:01.891199 INFO: [APUAPC] D11_APC_0: 0xffffffff
10046 10:06:01.894690 INFO: [APUAPC] D11_APC_1: 0xffffffff
10047 10:06:01.898107 INFO: [APUAPC] D11_APC_2: 0x3fffff
10048 10:06:01.901096 INFO: [APUAPC] D11_APC_3: 0x0
10049 10:06:01.904867 INFO: [APUAPC] D12_APC_0: 0xffffffff
10050 10:06:01.907773 INFO: [APUAPC] D12_APC_1: 0xffffffff
10051 10:06:01.911480 INFO: [APUAPC] D12_APC_2: 0x3fffff
10052 10:06:01.914519 INFO: [APUAPC] D12_APC_3: 0x0
10053 10:06:01.918021 INFO: [APUAPC] D13_APC_0: 0xffffffff
10054 10:06:01.921192 INFO: [APUAPC] D13_APC_1: 0xffffffff
10055 10:06:01.924484 INFO: [APUAPC] D13_APC_2: 0x3fffff
10056 10:06:01.928106 INFO: [APUAPC] D13_APC_3: 0x0
10057 10:06:01.931610 INFO: [APUAPC] D14_APC_0: 0xffffffff
10058 10:06:01.934344 INFO: [APUAPC] D14_APC_1: 0xffffffff
10059 10:06:01.937848 INFO: [APUAPC] D14_APC_2: 0x3fffff
10060 10:06:01.941493 INFO: [APUAPC] D14_APC_3: 0x0
10061 10:06:01.944627 INFO: [APUAPC] D15_APC_0: 0xffffffff
10062 10:06:01.948102 INFO: [APUAPC] D15_APC_1: 0xffffffff
10063 10:06:01.951234 INFO: [APUAPC] D15_APC_2: 0x3fffff
10064 10:06:01.954301 INFO: [APUAPC] D15_APC_3: 0x0
10065 10:06:01.957706 INFO: [APUAPC] APC_CON: 0x4
10066 10:06:01.961148 INFO: [NOCDAPC] D0_APC_0: 0x0
10067 10:06:01.964725 INFO: [NOCDAPC] D0_APC_1: 0x0
10068 10:06:01.967675 INFO: [NOCDAPC] D1_APC_0: 0x0
10069 10:06:01.971404 INFO: [NOCDAPC] D1_APC_1: 0xfff
10070 10:06:01.974561 INFO: [NOCDAPC] D2_APC_0: 0x0
10071 10:06:01.974658 INFO: [NOCDAPC] D2_APC_1: 0xfff
10072 10:06:01.977729 INFO: [NOCDAPC] D3_APC_0: 0x0
10073 10:06:01.981235 INFO: [NOCDAPC] D3_APC_1: 0xfff
10074 10:06:01.984389 INFO: [NOCDAPC] D4_APC_0: 0x0
10075 10:06:01.987664 INFO: [NOCDAPC] D4_APC_1: 0xfff
10076 10:06:01.990852 INFO: [NOCDAPC] D5_APC_0: 0x0
10077 10:06:01.994417 INFO: [NOCDAPC] D5_APC_1: 0xfff
10078 10:06:01.997996 INFO: [NOCDAPC] D6_APC_0: 0x0
10079 10:06:02.000833 INFO: [NOCDAPC] D6_APC_1: 0xfff
10080 10:06:02.004859 INFO: [NOCDAPC] D7_APC_0: 0x0
10081 10:06:02.008040 INFO: [NOCDAPC] D7_APC_1: 0xfff
10082 10:06:02.008124 INFO: [NOCDAPC] D8_APC_0: 0x0
10083 10:06:02.011276 INFO: [NOCDAPC] D8_APC_1: 0xfff
10084 10:06:02.014147 INFO: [NOCDAPC] D9_APC_0: 0x0
10085 10:06:02.017722 INFO: [NOCDAPC] D9_APC_1: 0xfff
10086 10:06:02.020765 INFO: [NOCDAPC] D10_APC_0: 0x0
10087 10:06:02.024428 INFO: [NOCDAPC] D10_APC_1: 0xfff
10088 10:06:02.027856 INFO: [NOCDAPC] D11_APC_0: 0x0
10089 10:06:02.031213 INFO: [NOCDAPC] D11_APC_1: 0xfff
10090 10:06:02.034301 INFO: [NOCDAPC] D12_APC_0: 0x0
10091 10:06:02.037780 INFO: [NOCDAPC] D12_APC_1: 0xfff
10092 10:06:02.041365 INFO: [NOCDAPC] D13_APC_0: 0x0
10093 10:06:02.044286 INFO: [NOCDAPC] D13_APC_1: 0xfff
10094 10:06:02.047762 INFO: [NOCDAPC] D14_APC_0: 0x0
10095 10:06:02.050849 INFO: [NOCDAPC] D14_APC_1: 0xfff
10096 10:06:02.050942 INFO: [NOCDAPC] D15_APC_0: 0x0
10097 10:06:02.054106 INFO: [NOCDAPC] D15_APC_1: 0xfff
10098 10:06:02.057490 INFO: [NOCDAPC] APC_CON: 0x4
10099 10:06:02.061202 INFO: [APUAPC] set_apusys_apc done
10100 10:06:02.064084 INFO: [DEVAPC] devapc_init done
10101 10:06:02.067532 INFO: GICv3 without legacy support detected.
10102 10:06:02.074255 INFO: ARM GICv3 driver initialized in EL3
10103 10:06:02.077349 INFO: Maximum SPI INTID supported: 639
10104 10:06:02.080968 INFO: BL31: Initializing runtime services
10105 10:06:02.087610 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10106 10:06:02.090481 INFO: SPM: enable CPC mode
10107 10:06:02.094006 INFO: mcdi ready for mcusys-off-idle and system suspend
10108 10:06:02.100456 INFO: BL31: Preparing for EL3 exit to normal world
10109 10:06:02.103661 INFO: Entry point address = 0x80000000
10110 10:06:02.103754 INFO: SPSR = 0x8
10111 10:06:02.110468
10112 10:06:02.110566
10113 10:06:02.110632
10114 10:06:02.113960 Starting depthcharge on Spherion...
10115 10:06:02.114077
10116 10:06:02.114178 Wipe memory regions:
10117 10:06:02.114270
10118 10:06:02.115242 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10119 10:06:02.115424 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10120 10:06:02.115540 Setting prompt string to ['asurada:']
10121 10:06:02.115659 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10122 10:06:02.117187 [0x00000040000000, 0x00000054600000)
10123 10:06:02.239331
10124 10:06:02.239484 [0x00000054660000, 0x00000080000000)
10125 10:06:02.500201
10126 10:06:02.500340 [0x000000821a7280, 0x000000ffe64000)
10127 10:06:03.244751
10128 10:06:03.244895 [0x00000100000000, 0x00000240000000)
10129 10:06:05.135587
10130 10:06:05.138240 Initializing XHCI USB controller at 0x11200000.
10131 10:06:06.176291
10132 10:06:06.179069 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10133 10:06:06.179184
10134 10:06:06.179274
10135 10:06:06.179384
10136 10:06:06.179691 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10138 10:06:06.280048 asurada: tftpboot 192.168.201.1 10670699/tftp-deploy-9imtukcw/kernel/image.itb 10670699/tftp-deploy-9imtukcw/kernel/cmdline
10139 10:06:06.280250 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10140 10:06:06.280363 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10141 10:06:06.284375 tftpboot 192.168.201.1 10670699/tftp-deploy-9imtukcw/kernel/image.itp-deploy-9imtukcw/kernel/cmdline
10142 10:06:06.284489
10143 10:06:06.284583 Waiting for link
10144 10:06:06.444809
10145 10:06:06.444958 R8152: Initializing
10146 10:06:06.445038
10147 10:06:06.448516 Version 6 (ocp_data = 5c30)
10148 10:06:06.448622
10149 10:06:06.451243 R8152: Done initializing
10150 10:06:06.451355
10151 10:06:06.451460 Adding net device
10152 10:06:08.323419
10153 10:06:08.323565 done.
10154 10:06:08.323631
10155 10:06:08.323691 MAC: 00:24:32:30:78:52
10156 10:06:08.323750
10157 10:06:08.326208 Sending DHCP discover... done.
10158 10:06:08.326289
10159 10:06:16.399284 Waiting for reply... done.
10160 10:06:16.399835
10161 10:06:16.400176 Sending DHCP request... done.
10162 10:06:16.402173
10163 10:06:16.407443 Waiting for reply... done.
10164 10:06:16.407867
10165 10:06:16.408330 My ip is 192.168.201.14
10166 10:06:16.408655
10167 10:06:16.410747 The DHCP server ip is 192.168.201.1
10168 10:06:16.411169
10169 10:06:16.416779 TFTP server IP predefined by user: 192.168.201.1
10170 10:06:16.417210
10171 10:06:16.423599 Bootfile predefined by user: 10670699/tftp-deploy-9imtukcw/kernel/image.itb
10172 10:06:16.424026
10173 10:06:16.426781 Sending tftp read request... done.
10174 10:06:16.427251
10175 10:06:16.432527 Waiting for the transfer...
10176 10:06:16.432954
10177 10:06:17.149241 00000000 ################################################################
10178 10:06:17.149871
10179 10:06:17.813657 00080000 ################################################################
10180 10:06:17.814285
10181 10:06:18.427558 00100000 ################################################################
10182 10:06:18.427697
10183 10:06:19.072662 00180000 ################################################################
10184 10:06:19.072843
10185 10:06:19.705316 00200000 ################################################################
10186 10:06:19.705451
10187 10:06:20.349306 00280000 ################################################################
10188 10:06:20.349458
10189 10:06:20.986439 00300000 ################################################################
10190 10:06:20.986607
10191 10:06:21.624110 00380000 ################################################################
10192 10:06:21.624246
10193 10:06:22.266067 00400000 ################################################################
10194 10:06:22.266230
10195 10:06:22.906228 00480000 ################################################################
10196 10:06:22.906392
10197 10:06:23.530111 00500000 ################################################################
10198 10:06:23.530247
10199 10:06:24.158234 00580000 ################################################################
10200 10:06:24.158367
10201 10:06:24.775422 00600000 ################################################################
10202 10:06:24.775555
10203 10:06:25.376240 00680000 ################################################################
10204 10:06:25.376378
10205 10:06:26.007843 00700000 ################################################################
10206 10:06:26.008018
10207 10:06:26.652516 00780000 ################################################################
10208 10:06:26.652676
10209 10:06:27.273998 00800000 ################################################################
10210 10:06:27.274168
10211 10:06:27.892001 00880000 ################################################################
10212 10:06:27.892177
10213 10:06:28.517616 00900000 ################################################################
10214 10:06:28.517787
10215 10:06:29.148078 00980000 ################################################################
10216 10:06:29.148264
10217 10:06:29.770800 00a00000 ################################################################
10218 10:06:29.770968
10219 10:06:30.400349 00a80000 ################################################################
10220 10:06:30.400507
10221 10:06:31.040013 00b00000 ################################################################
10222 10:06:31.040163
10223 10:06:31.679130 00b80000 ################################################################
10224 10:06:31.679313
10225 10:06:32.317401 00c00000 ################################################################
10226 10:06:32.317555
10227 10:06:32.965010 00c80000 ################################################################
10228 10:06:32.965147
10229 10:06:33.607103 00d00000 ################################################################
10230 10:06:33.607286
10231 10:06:34.243401 00d80000 ################################################################
10232 10:06:34.243537
10233 10:06:34.893117 00e00000 ################################################################
10234 10:06:34.893316
10235 10:06:35.539065 00e80000 ################################################################
10236 10:06:35.539268
10237 10:06:36.189993 00f00000 ################################################################
10238 10:06:36.190154
10239 10:06:36.789484 00f80000 ################################################################
10240 10:06:36.789616
10241 10:06:37.469046 01000000 ################################################################
10242 10:06:37.469541
10243 10:06:38.123911 01080000 ################################################################
10244 10:06:38.124082
10245 10:06:38.768925 01100000 ################################################################
10246 10:06:38.769064
10247 10:06:39.412715 01180000 ################################################################
10248 10:06:39.412889
10249 10:06:40.060505 01200000 ################################################################
10250 10:06:40.060682
10251 10:06:40.710631 01280000 ################################################################
10252 10:06:40.710806
10253 10:06:41.355957 01300000 ################################################################
10254 10:06:41.356121
10255 10:06:41.995651 01380000 ################################################################
10256 10:06:41.995832
10257 10:06:42.638930 01400000 ################################################################
10258 10:06:42.639128
10259 10:06:43.281203 01480000 ################################################################
10260 10:06:43.281356
10261 10:06:43.919427 01500000 ################################################################
10262 10:06:43.919583
10263 10:06:44.573363 01580000 ################################################################
10264 10:06:44.573546
10265 10:06:45.213742 01600000 ################################################################
10266 10:06:45.213892
10267 10:06:45.853667 01680000 ################################################################
10268 10:06:45.853799
10269 10:06:46.485887 01700000 ################################################################
10270 10:06:46.486024
10271 10:06:47.029479 01780000 ################################################################
10272 10:06:47.029627
10273 10:06:47.551065 01800000 ################################################################
10274 10:06:47.551218
10275 10:06:48.106504 01880000 ################################################################
10276 10:06:48.106640
10277 10:06:48.648375 01900000 ################################################################
10278 10:06:48.648545
10279 10:06:49.188629 01980000 ################################################################
10280 10:06:49.188766
10281 10:06:49.737921 01a00000 ################################################################
10282 10:06:49.738082
10283 10:06:50.271900 01a80000 ################################################################
10284 10:06:50.272086
10285 10:06:50.719072 01b00000 #################################################### done.
10286 10:06:50.719236
10287 10:06:50.722092 The bootfile was 28736306 bytes long.
10288 10:06:50.722177
10289 10:06:50.725944 Sending tftp read request... done.
10290 10:06:50.726025
10291 10:06:50.726115 Waiting for the transfer...
10292 10:06:50.726193
10293 10:06:50.728955 00000000 # done.
10294 10:06:50.729045
10295 10:06:50.735794 Command line loaded dynamically from TFTP file: 10670699/tftp-deploy-9imtukcw/kernel/cmdline
10296 10:06:50.735878
10297 10:06:50.755767 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10670699/extract-nfsrootfs-1ly9ggbb,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10298 10:06:50.755858
10299 10:06:50.758760 Loading FIT.
10300 10:06:50.758842
10301 10:06:50.761800 Image ramdisk-1 has 18600031 bytes.
10302 10:06:50.761899
10303 10:06:50.761988 Image fdt-1 has 46924 bytes.
10304 10:06:50.762061
10305 10:06:50.765298 Image kernel-1 has 10087317 bytes.
10306 10:06:50.765398
10307 10:06:50.775013 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10308 10:06:50.775096
10309 10:06:50.792032 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10310 10:06:50.792123
10311 10:06:50.798775 Choosing best match conf-1 for compat google,spherion-rev2.
10312 10:06:50.802264
10313 10:06:50.806088 Connected to device vid:did:rid of 1ae0:0028:00
10314 10:06:50.813738
10315 10:06:50.817012 tpm_get_response: command 0x17b, return code 0x0
10316 10:06:50.817095
10317 10:06:50.820370 ec_init: CrosEC protocol v3 supported (256, 248)
10318 10:06:50.824625
10319 10:06:50.827783 tpm_cleanup: add release locality here.
10320 10:06:50.827866
10321 10:06:50.827931 Shutting down all USB controllers.
10322 10:06:50.830810
10323 10:06:50.830891 Removing current net device
10324 10:06:50.830956
10325 10:06:50.837659 Exiting depthcharge with code 4 at timestamp: 78129525
10326 10:06:50.837740
10327 10:06:50.841449 LZMA decompressing kernel-1 to 0x821a6718
10328 10:06:50.841529
10329 10:06:50.844564 LZMA decompressing kernel-1 to 0x40000000
10330 10:06:52.111926
10331 10:06:52.112100 jumping to kernel
10332 10:06:52.112527 end: 2.2.4 bootloader-commands (duration 00:00:50) [common]
10333 10:06:52.112629 start: 2.2.5 auto-login-action (timeout 00:03:35) [common]
10334 10:06:52.112704 Setting prompt string to ['Linux version [0-9]']
10335 10:06:52.112776 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10336 10:06:52.112845 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10337 10:06:52.193607
10338 10:06:52.196980 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10339 10:06:52.200707 start: 2.2.5.1 login-action (timeout 00:03:35) [common]
10340 10:06:52.200800 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10341 10:06:52.200889 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10342 10:06:52.200966 Using line separator: #'\n'#
10343 10:06:52.201026 No login prompt set.
10344 10:06:52.201107 Parsing kernel messages
10345 10:06:52.201191 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10346 10:06:52.201355 [login-action] Waiting for messages, (timeout 00:03:35)
10347 10:06:52.220310 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j19381-arm64-gcc-10-defconfig-arm64-chromebook-d6qsg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023
10348 10:06:52.223259 [ 0.000000] random: crng init done
10349 10:06:52.227055 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10350 10:06:52.230048 [ 0.000000] efi: UEFI not found.
10351 10:06:52.239954 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10352 10:06:52.246563 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10353 10:06:52.256124 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10354 10:06:52.266928 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10355 10:06:52.272987 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10356 10:06:52.276566 [ 0.000000] printk: bootconsole [mtk8250] enabled
10357 10:06:52.285030 [ 0.000000] NUMA: No NUMA configuration found
10358 10:06:52.291902 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10359 10:06:52.297985 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10360 10:06:52.298099 [ 0.000000] Zone ranges:
10361 10:06:52.305118 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10362 10:06:52.308028 [ 0.000000] DMA32 empty
10363 10:06:52.315227 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10364 10:06:52.318311 [ 0.000000] Movable zone start for each node
10365 10:06:52.321321 [ 0.000000] Early memory node ranges
10366 10:06:52.327841 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10367 10:06:52.334622 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10368 10:06:52.341369 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10369 10:06:52.347751 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10370 10:06:52.354685 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10371 10:06:52.360804 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10372 10:06:52.417650 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10373 10:06:52.424376 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10374 10:06:52.430998 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10375 10:06:52.434753 [ 0.000000] psci: probing for conduit method from DT.
10376 10:06:52.440997 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10377 10:06:52.444224 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10378 10:06:52.451122 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10379 10:06:52.454460 [ 0.000000] psci: SMC Calling Convention v1.2
10380 10:06:52.460466 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10381 10:06:52.464008 [ 0.000000] Detected VIPT I-cache on CPU0
10382 10:06:52.470515 [ 0.000000] CPU features: detected: GIC system register CPU interface
10383 10:06:52.477238 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10384 10:06:52.483816 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10385 10:06:52.490496 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10386 10:06:52.500708 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10387 10:06:52.507048 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10388 10:06:52.510494 [ 0.000000] alternatives: applying boot alternatives
10389 10:06:52.516835 [ 0.000000] Fallback order for Node 0: 0
10390 10:06:52.523525 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10391 10:06:52.527148 [ 0.000000] Policy zone: Normal
10392 10:06:52.546628 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10670699/extract-nfsrootfs-1ly9ggbb,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10393 10:06:52.556317 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10394 10:06:52.568492 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10395 10:06:52.578109 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10396 10:06:52.584627 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10397 10:06:52.588214 <6>[ 0.000000] software IO TLB: area num 8.
10398 10:06:52.644482 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10399 10:06:52.793963 <6>[ 0.000000] Memory: 7954780K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397988K reserved, 32768K cma-reserved)
10400 10:06:52.800620 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10401 10:06:52.807222 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10402 10:06:52.810734 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10403 10:06:52.817163 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10404 10:06:52.823876 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10405 10:06:52.826935 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10406 10:06:52.837012 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10407 10:06:52.843702 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10408 10:06:52.850252 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10409 10:06:52.856447 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10410 10:06:52.860182 <6>[ 0.000000] GICv3: 608 SPIs implemented
10411 10:06:52.863182 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10412 10:06:52.869875 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10413 10:06:52.873311 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10414 10:06:52.880030 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10415 10:06:52.893152 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10416 10:06:52.905936 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10417 10:06:52.913107 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10418 10:06:52.920775 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10419 10:06:52.933652 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10420 10:06:52.940314 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10421 10:06:52.946919 <6>[ 0.009174] Console: colour dummy device 80x25
10422 10:06:52.956660 <6>[ 0.013902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10423 10:06:52.963567 <6>[ 0.024345] pid_max: default: 32768 minimum: 301
10424 10:06:52.967011 <6>[ 0.029217] LSM: Security Framework initializing
10425 10:06:52.973776 <6>[ 0.034155] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10426 10:06:52.983543 <6>[ 0.042016] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10427 10:06:52.990198 <6>[ 0.051446] cblist_init_generic: Setting adjustable number of callback queues.
10428 10:06:52.996793 <6>[ 0.058899] cblist_init_generic: Setting shift to 3 and lim to 1.
10429 10:06:53.003138 <6>[ 0.065237] cblist_init_generic: Setting shift to 3 and lim to 1.
10430 10:06:53.009636 <6>[ 0.071642] rcu: Hierarchical SRCU implementation.
10431 10:06:53.013599 <6>[ 0.076657] rcu: Max phase no-delay instances is 1000.
10432 10:06:53.021426 <6>[ 0.083676] EFI services will not be available.
10433 10:06:53.024918 <6>[ 0.088647] smp: Bringing up secondary CPUs ...
10434 10:06:53.033884 <6>[ 0.093701] Detected VIPT I-cache on CPU1
10435 10:06:53.040299 <6>[ 0.093773] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10436 10:06:53.046885 <6>[ 0.093803] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10437 10:06:53.050614 <6>[ 0.094135] Detected VIPT I-cache on CPU2
10438 10:06:53.060187 <6>[ 0.094183] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10439 10:06:53.067196 <6>[ 0.094197] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10440 10:06:53.070130 <6>[ 0.094455] Detected VIPT I-cache on CPU3
10441 10:06:53.077015 <6>[ 0.094503] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10442 10:06:53.083330 <6>[ 0.094517] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10443 10:06:53.086997 <6>[ 0.094822] CPU features: detected: Spectre-v4
10444 10:06:53.093041 <6>[ 0.094828] CPU features: detected: Spectre-BHB
10445 10:06:53.096603 <6>[ 0.094834] Detected PIPT I-cache on CPU4
10446 10:06:53.103143 <6>[ 0.094891] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10447 10:06:53.109805 <6>[ 0.094907] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10448 10:06:53.116365 <6>[ 0.095200] Detected PIPT I-cache on CPU5
10449 10:06:53.122973 <6>[ 0.095265] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10450 10:06:53.129902 <6>[ 0.095281] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10451 10:06:53.133378 <6>[ 0.095563] Detected PIPT I-cache on CPU6
10452 10:06:53.139975 <6>[ 0.095627] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10453 10:06:53.146365 <6>[ 0.095643] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10454 10:06:53.153243 <6>[ 0.095940] Detected PIPT I-cache on CPU7
10455 10:06:53.159850 <6>[ 0.096005] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10456 10:06:53.166669 <6>[ 0.096021] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10457 10:06:53.169800 <6>[ 0.096068] smp: Brought up 1 node, 8 CPUs
10458 10:06:53.175970 <6>[ 0.237508] SMP: Total of 8 processors activated.
10459 10:06:53.179545 <6>[ 0.242429] CPU features: detected: 32-bit EL0 Support
10460 10:06:53.189511 <6>[ 0.247792] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10461 10:06:53.196154 <6>[ 0.256592] CPU features: detected: Common not Private translations
10462 10:06:53.199250 <6>[ 0.263068] CPU features: detected: CRC32 instructions
10463 10:06:53.206067 <6>[ 0.268420] CPU features: detected: RCpc load-acquire (LDAPR)
10464 10:06:53.212859 <6>[ 0.274380] CPU features: detected: LSE atomic instructions
10465 10:06:53.219673 <6>[ 0.280161] CPU features: detected: Privileged Access Never
10466 10:06:53.222494 <6>[ 0.285941] CPU features: detected: RAS Extension Support
10467 10:06:53.232622 <6>[ 0.291584] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10468 10:06:53.235712 <6>[ 0.298849] CPU: All CPU(s) started at EL2
10469 10:06:53.242857 <6>[ 0.303165] alternatives: applying system-wide alternatives
10470 10:06:53.251618 <6>[ 0.313880] devtmpfs: initialized
10471 10:06:53.263876 <6>[ 0.322690] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10472 10:06:53.273602 <6>[ 0.332654] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10473 10:06:53.280192 <6>[ 0.340801] pinctrl core: initialized pinctrl subsystem
10474 10:06:53.283292 <6>[ 0.347464] DMI not present or invalid.
10475 10:06:53.290251 <6>[ 0.351870] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10476 10:06:53.299907 <6>[ 0.358743] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10477 10:06:53.306699 <6>[ 0.366322] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10478 10:06:53.316529 <6>[ 0.374543] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10479 10:06:53.319852 <6>[ 0.382782] audit: initializing netlink subsys (disabled)
10480 10:06:53.330119 <5>[ 0.388477] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10481 10:06:53.336118 <6>[ 0.389180] thermal_sys: Registered thermal governor 'step_wise'
10482 10:06:53.343110 <6>[ 0.396443] thermal_sys: Registered thermal governor 'power_allocator'
10483 10:06:53.346123 <6>[ 0.402697] cpuidle: using governor menu
10484 10:06:53.353360 <6>[ 0.413659] NET: Registered PF_QIPCRTR protocol family
10485 10:06:53.359473 <6>[ 0.419150] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10486 10:06:53.365865 <6>[ 0.426254] ASID allocator initialised with 32768 entries
10487 10:06:53.369462 <6>[ 0.432806] Serial: AMBA PL011 UART driver
10488 10:06:53.378884 <4>[ 0.441471] Trying to register duplicate clock ID: 134
10489 10:06:53.433052 <6>[ 0.498423] KASLR enabled
10490 10:06:53.447439 <6>[ 0.506160] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10491 10:06:53.453521 <6>[ 0.513167] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10492 10:06:53.460570 <6>[ 0.519658] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10493 10:06:53.467225 <6>[ 0.526663] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10494 10:06:53.473991 <6>[ 0.533149] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10495 10:06:53.480138 <6>[ 0.540155] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10496 10:06:53.486753 <6>[ 0.546643] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10497 10:06:53.493577 <6>[ 0.553647] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10498 10:06:53.497092 <6>[ 0.561155] ACPI: Interpreter disabled.
10499 10:06:53.505017 <6>[ 0.567525] iommu: Default domain type: Translated
10500 10:06:53.512148 <6>[ 0.572640] iommu: DMA domain TLB invalidation policy: strict mode
10501 10:06:53.515126 <5>[ 0.579294] SCSI subsystem initialized
10502 10:06:53.521763 <6>[ 0.583458] usbcore: registered new interface driver usbfs
10503 10:06:53.528276 <6>[ 0.589192] usbcore: registered new interface driver hub
10504 10:06:53.532012 <6>[ 0.594742] usbcore: registered new device driver usb
10505 10:06:53.538475 <6>[ 0.600818] pps_core: LinuxPPS API ver. 1 registered
10506 10:06:53.548116 <6>[ 0.606008] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10507 10:06:53.551805 <6>[ 0.615352] PTP clock support registered
10508 10:06:53.554777 <6>[ 0.619590] EDAC MC: Ver: 3.0.0
10509 10:06:53.562557 <6>[ 0.624721] FPGA manager framework
10510 10:06:53.568776 <6>[ 0.628397] Advanced Linux Sound Architecture Driver Initialized.
10511 10:06:53.572499 <6>[ 0.635168] vgaarb: loaded
10512 10:06:53.578846 <6>[ 0.638349] clocksource: Switched to clocksource arch_sys_counter
10513 10:06:53.582036 <5>[ 0.644787] VFS: Disk quotas dquot_6.6.0
10514 10:06:53.588782 <6>[ 0.648969] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10515 10:06:53.591777 <6>[ 0.656154] pnp: PnP ACPI: disabled
10516 10:06:53.600309 <6>[ 0.662797] NET: Registered PF_INET protocol family
10517 10:06:53.610657 <6>[ 0.668373] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10518 10:06:53.621189 <6>[ 0.680653] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10519 10:06:53.631418 <6>[ 0.689465] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10520 10:06:53.638039 <6>[ 0.697437] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10521 10:06:53.647852 <6>[ 0.706138] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10522 10:06:53.654338 <6>[ 0.715891] TCP: Hash tables configured (established 65536 bind 65536)
10523 10:06:53.661558 <6>[ 0.722743] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10524 10:06:53.671013 <6>[ 0.729941] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10525 10:06:53.674764 <6>[ 0.737635] NET: Registered PF_UNIX/PF_LOCAL protocol family
10526 10:06:53.681276 <6>[ 0.743795] RPC: Registered named UNIX socket transport module.
10527 10:06:53.688056 <6>[ 0.749945] RPC: Registered udp transport module.
10528 10:06:53.691823 <6>[ 0.754874] RPC: Registered tcp transport module.
10529 10:06:53.697721 <6>[ 0.759807] RPC: Registered tcp NFSv4.1 backchannel transport module.
10530 10:06:53.704402 <6>[ 0.766476] PCI: CLS 0 bytes, default 64
10531 10:06:53.707949 <6>[ 0.770824] Unpacking initramfs...
10532 10:06:53.724095 <6>[ 0.782990] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10533 10:06:53.734209 <6>[ 0.791639] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10534 10:06:53.737186 <6>[ 0.800423] kvm [1]: IPA Size Limit: 40 bits
10535 10:06:53.743704 <6>[ 0.804951] kvm [1]: GICv3: no GICV resource entry
10536 10:06:53.747263 <6>[ 0.809972] kvm [1]: disabling GICv2 emulation
10537 10:06:53.753742 <6>[ 0.814660] kvm [1]: GIC system register CPU interface enabled
10538 10:06:53.756807 <6>[ 0.820820] kvm [1]: vgic interrupt IRQ18
10539 10:06:53.763501 <6>[ 0.825185] kvm [1]: VHE mode initialized successfully
10540 10:06:53.770598 <5>[ 0.831708] Initialise system trusted keyrings
10541 10:06:53.776693 <6>[ 0.836530] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10542 10:06:53.784208 <6>[ 0.846611] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10543 10:06:53.791061 <5>[ 0.853043] NFS: Registering the id_resolver key type
10544 10:06:53.794324 <5>[ 0.858348] Key type id_resolver registered
10545 10:06:53.800740 <5>[ 0.862764] Key type id_legacy registered
10546 10:06:53.807591 <6>[ 0.867042] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10547 10:06:53.814006 <6>[ 0.873966] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10548 10:06:53.820939 <6>[ 0.881688] 9p: Installing v9fs 9p2000 file system support
10549 10:06:53.857450 <5>[ 0.919869] Key type asymmetric registered
10550 10:06:53.860912 <5>[ 0.924199] Asymmetric key parser 'x509' registered
10551 10:06:53.870938 <6>[ 0.929355] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10552 10:06:53.873779 <6>[ 0.936969] io scheduler mq-deadline registered
10553 10:06:53.877467 <6>[ 0.941730] io scheduler kyber registered
10554 10:06:53.896313 <6>[ 0.958643] EINJ: ACPI disabled.
10555 10:06:53.927649 <4>[ 0.983789] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10556 10:06:53.938190 <4>[ 0.994440] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10557 10:06:53.952922 <6>[ 1.015278] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10558 10:06:53.960653 <6>[ 1.023249] printk: console [ttyS0] disabled
10559 10:06:53.988929 <6>[ 1.047892] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10560 10:06:53.995225 <6>[ 1.057372] printk: console [ttyS0] enabled
10561 10:06:53.998985 <6>[ 1.057372] printk: console [ttyS0] enabled
10562 10:06:54.005652 <6>[ 1.066265] printk: bootconsole [mtk8250] disabled
10563 10:06:54.008757 <6>[ 1.066265] printk: bootconsole [mtk8250] disabled
10564 10:06:54.015325 <6>[ 1.077454] SuperH (H)SCI(F) driver initialized
10565 10:06:54.018225 <6>[ 1.082726] msm_serial: driver initialized
10566 10:06:54.032659 <6>[ 1.091636] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10567 10:06:54.042561 <6>[ 1.100183] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10568 10:06:54.049345 <6>[ 1.108724] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10569 10:06:54.058857 <6>[ 1.117353] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10570 10:06:54.066031 <6>[ 1.126060] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10571 10:06:54.075700 <6>[ 1.134784] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10572 10:06:54.085632 <6>[ 1.143327] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10573 10:06:54.092370 <6>[ 1.152134] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10574 10:06:54.102390 <6>[ 1.160682] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10575 10:06:54.114010 <6>[ 1.176168] loop: module loaded
10576 10:06:54.120132 <6>[ 1.182189] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10577 10:06:54.143364 <4>[ 1.205687] mtk-pmic-keys: Failed to locate of_node [id: -1]
10578 10:06:54.149965 <6>[ 1.212685] megasas: 07.719.03.00-rc1
10579 10:06:54.159768 <6>[ 1.222254] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10580 10:06:54.171640 <6>[ 1.233727] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10581 10:06:54.188084 <6>[ 1.250409] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10582 10:06:54.248737 <6>[ 1.304607] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10583 10:06:54.483872 <6>[ 1.546569] Freeing initrd memory: 18160K
10584 10:06:54.495242 <6>[ 1.558017] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10585 10:06:54.506401 <6>[ 1.568873] tun: Universal TUN/TAP device driver, 1.6
10586 10:06:54.509543 <6>[ 1.574930] thunder_xcv, ver 1.0
10587 10:06:54.513182 <6>[ 1.578431] thunder_bgx, ver 1.0
10588 10:06:54.516281 <6>[ 1.581921] nicpf, ver 1.0
10589 10:06:54.526570 <6>[ 1.585911] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10590 10:06:54.530382 <6>[ 1.593386] hns3: Copyright (c) 2017 Huawei Corporation.
10591 10:06:54.533381 <6>[ 1.598972] hclge is initializing
10592 10:06:54.540060 <6>[ 1.602552] e1000: Intel(R) PRO/1000 Network Driver
10593 10:06:54.546614 <6>[ 1.607680] e1000: Copyright (c) 1999-2006 Intel Corporation.
10594 10:06:54.549847 <6>[ 1.613696] e1000e: Intel(R) PRO/1000 Network Driver
10595 10:06:54.556487 <6>[ 1.618912] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10596 10:06:54.563305 <6>[ 1.625096] igb: Intel(R) Gigabit Ethernet Network Driver
10597 10:06:54.570157 <6>[ 1.630746] igb: Copyright (c) 2007-2014 Intel Corporation.
10598 10:06:54.576663 <6>[ 1.636581] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10599 10:06:54.583140 <6>[ 1.643098] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10600 10:06:54.586526 <6>[ 1.649560] sky2: driver version 1.30
10601 10:06:54.593183 <6>[ 1.654528] VFIO - User Level meta-driver version: 0.3
10602 10:06:54.600222 <6>[ 1.662746] usbcore: registered new interface driver usb-storage
10603 10:06:54.607000 <6>[ 1.669186] usbcore: registered new device driver onboard-usb-hub
10604 10:06:54.616103 <6>[ 1.678224] mt6397-rtc mt6359-rtc: registered as rtc0
10605 10:06:54.625505 <6>[ 1.683689] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-10T10:06:56 UTC (1686391616)
10606 10:06:54.629120 <6>[ 1.693239] i2c_dev: i2c /dev entries driver
10607 10:06:54.645830 <6>[ 1.704784] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10608 10:06:54.652281 <6>[ 1.714976] sdhci: Secure Digital Host Controller Interface driver
10609 10:06:54.659522 <6>[ 1.721413] sdhci: Copyright(c) Pierre Ossman
10610 10:06:54.666048 <6>[ 1.726803] Synopsys Designware Multimedia Card Interface Driver
10611 10:06:54.668998 <6>[ 1.733402] mmc0: CQHCI version 5.10
10612 10:06:54.675877 <6>[ 1.733956] sdhci-pltfm: SDHCI platform and OF driver helper
10613 10:06:54.682886 <6>[ 1.745336] ledtrig-cpu: registered to indicate activity on CPUs
10614 10:06:54.693200 <6>[ 1.752641] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10615 10:06:54.696529 <6>[ 1.760027] usbcore: registered new interface driver usbhid
10616 10:06:54.703814 <6>[ 1.765858] usbhid: USB HID core driver
10617 10:06:54.709689 <6>[ 1.770101] spi_master spi0: will run message pump with realtime priority
10618 10:06:54.758539 <6>[ 1.814500] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10619 10:06:54.777377 <6>[ 1.829739] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10620 10:06:54.780861 <6>[ 1.843322] mmc0: Command Queue Engine enabled
10621 10:06:54.788160 <6>[ 1.844878] cros-ec-spi spi0.0: Chrome EC device registered
10622 10:06:54.791707 <6>[ 1.848074] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10623 10:06:54.798916 <6>[ 1.861470] mmcblk0: mmc0:0001 DA4128 116 GiB
10624 10:06:54.809398 <6>[ 1.871759] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10625 10:06:54.819694 <6>[ 1.872356] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10626 10:06:54.825698 <6>[ 1.878852] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10627 10:06:54.829454 <6>[ 1.889153] NET: Registered PF_PACKET protocol family
10628 10:06:54.836210 <6>[ 1.892933] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10629 10:06:54.839222 <6>[ 1.897659] 9pnet: Installing 9P2000 support
10630 10:06:54.846027 <6>[ 1.903534] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10631 10:06:54.848954 <5>[ 1.907355] Key type dns_resolver registered
10632 10:06:54.856508 <6>[ 1.918963] registered taskstats version 1
10633 10:06:54.860094 <5>[ 1.923373] Loading compiled-in X.509 certificates
10634 10:06:54.894854 <4>[ 1.950803] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10635 10:06:54.904775 <4>[ 1.961509] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10636 10:06:54.915365 <3>[ 1.974208] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10637 10:06:54.927206 <6>[ 1.989638] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10638 10:06:54.934457 <6>[ 1.996526] xhci-mtk 11200000.usb: xHCI Host Controller
10639 10:06:54.940494 <6>[ 2.002046] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10640 10:06:54.950831 <6>[ 2.009904] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10641 10:06:54.958076 <6>[ 2.019338] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10642 10:06:54.964374 <6>[ 2.025446] xhci-mtk 11200000.usb: xHCI Host Controller
10643 10:06:54.970839 <6>[ 2.030932] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10644 10:06:54.977470 <6>[ 2.038582] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10645 10:06:54.984191 <6>[ 2.046321] hub 1-0:1.0: USB hub found
10646 10:06:54.988010 <6>[ 2.050359] hub 1-0:1.0: 1 port detected
10647 10:06:54.994094 <6>[ 2.054701] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10648 10:06:55.001197 <6>[ 2.063421] hub 2-0:1.0: USB hub found
10649 10:06:55.004204 <6>[ 2.067453] hub 2-0:1.0: 1 port detected
10650 10:06:55.011812 <6>[ 2.074441] mtk-msdc 11f70000.mmc: Got CD GPIO
10651 10:06:55.029932 <6>[ 2.089048] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10652 10:06:55.036534 <6>[ 2.097081] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10653 10:06:55.046949 <4>[ 2.105063] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10654 10:06:55.056837 <6>[ 2.114717] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10655 10:06:55.063218 <6>[ 2.122798] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10656 10:06:55.069708 <6>[ 2.130840] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10657 10:06:55.079762 <6>[ 2.138757] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10658 10:06:55.086478 <6>[ 2.146582] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10659 10:06:55.096302 <6>[ 2.154405] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10660 10:06:55.106132 <6>[ 2.165045] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10661 10:06:55.113017 <6>[ 2.173413] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10662 10:06:55.123027 <6>[ 2.181774] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10663 10:06:55.129586 <6>[ 2.190117] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10664 10:06:55.139281 <6>[ 2.198463] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10665 10:06:55.146253 <6>[ 2.206806] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10666 10:06:55.155919 <6>[ 2.215150] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10667 10:06:55.166279 <6>[ 2.223499] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10668 10:06:55.172683 <6>[ 2.231843] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10669 10:06:55.182255 <6>[ 2.240190] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10670 10:06:55.188929 <6>[ 2.248537] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10671 10:06:55.198881 <6>[ 2.256881] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10672 10:06:55.206094 <6>[ 2.265224] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10673 10:06:55.215336 <6>[ 2.273568] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10674 10:06:55.221985 <6>[ 2.281913] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10675 10:06:55.229233 <6>[ 2.290836] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10676 10:06:55.235536 <6>[ 2.298345] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10677 10:06:55.242803 <6>[ 2.305427] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10678 10:06:55.253710 <6>[ 2.312557] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10679 10:06:55.259765 <6>[ 2.319857] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10680 10:06:55.269777 <6>[ 2.326850] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10681 10:06:55.276454 <6>[ 2.336013] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10682 10:06:55.286617 <6>[ 2.345140] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10683 10:06:55.296396 <6>[ 2.354441] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10684 10:06:55.306247 <6>[ 2.363917] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10685 10:06:55.316143 <6>[ 2.373392] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10686 10:06:55.322686 <6>[ 2.382518] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10687 10:06:55.332581 <6>[ 2.391997] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10688 10:06:55.343016 <6>[ 2.401124] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10689 10:06:55.352718 <6>[ 2.410427] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10690 10:06:55.362645 <6>[ 2.420593] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10691 10:06:55.372827 <6>[ 2.432071] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10692 10:06:55.379281 <6>[ 2.441997] Trying to probe devices needed for running init ...
10693 10:06:55.395994 <6>[ 2.454816] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10694 10:06:55.424040 <6>[ 2.486514] hub 2-1:1.0: USB hub found
10695 10:06:55.427345 <6>[ 2.490975] hub 2-1:1.0: 3 ports detected
10696 10:06:55.547214 <6>[ 2.606594] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10697 10:06:55.700560 <6>[ 2.762897] hub 1-1:1.0: USB hub found
10698 10:06:55.703508 <6>[ 2.767285] hub 1-1:1.0: 4 ports detected
10699 10:06:55.783509 <6>[ 2.842865] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10700 10:06:56.023215 <6>[ 3.082672] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10701 10:06:56.156394 <6>[ 3.218930] hub 1-1.4:1.0: USB hub found
10702 10:06:56.159291 <6>[ 3.223618] hub 1-1.4:1.0: 2 ports detected
10703 10:06:56.455104 <6>[ 3.514621] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10704 10:06:56.647079 <6>[ 3.706623] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10705 10:07:07.664013 <6>[ 14.731198] ALSA device list:
10706 10:07:07.670373 <6>[ 14.734455] No soundcards found.
10707 10:07:07.683163 <6>[ 14.746837] Freeing unused kernel memory: 8384K
10708 10:07:07.686116 <6>[ 14.751773] Run /init as init process
10709 10:07:07.696653 Loading, please wait...
10710 10:07:07.725180 Starting systemd-udevd version 252.6-1
10711 10:07:08.133587 <6>[ 15.194289] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10712 10:07:08.145174 <6>[ 15.208911] remoteproc remoteproc0: scp is available
10713 10:07:08.154878 <4>[ 15.215143] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10714 10:07:08.161282 <6>[ 15.225191] remoteproc remoteproc0: powering up scp
10715 10:07:08.171345 <4>[ 15.231772] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10716 10:07:08.181527 <6>[ 15.233523] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10717 10:07:08.187955 <3>[ 15.241668] remoteproc remoteproc0: request_firmware failed: -2
10718 10:07:08.194265 <6>[ 15.249290] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10719 10:07:08.200851 <6>[ 15.263560] usbcore: registered new interface driver r8152
10720 10:07:08.204459 <6>[ 15.264519] mc: Linux media interface: v0.10
10721 10:07:08.214529 <6>[ 15.264700] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10722 10:07:08.221136 <3>[ 15.270296] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 10:07:08.230884 <4>[ 15.271833] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10724 10:07:08.237693 <4>[ 15.271964] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10725 10:07:08.244301 <6>[ 15.272157] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10726 10:07:08.254474 <4>[ 15.296713] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10727 10:07:08.258218 <4>[ 15.296713] Fallback method does not support PEC.
10728 10:07:08.264853 <3>[ 15.298584] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 10:07:08.271628 <6>[ 15.314735] videodev: Linux video capture interface: v2.00
10730 10:07:08.281666 <3>[ 15.324927] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10731 10:07:08.288878 <3>[ 15.327213] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 10:07:08.298443 <3>[ 15.345907] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10733 10:07:08.305067 <3>[ 15.349918] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 10:07:08.311514 <6>[ 15.350965] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10735 10:07:08.321882 <4>[ 15.378045] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10736 10:07:08.331224 <6>[ 15.382062] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10737 10:07:08.337941 <3>[ 15.382148] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10738 10:07:08.348156 <3>[ 15.382159] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 10:07:08.354724 <3>[ 15.382170] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10740 10:07:08.364538 <3>[ 15.382178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 10:07:08.371503 <3>[ 15.382230] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10742 10:07:08.381072 <3>[ 15.382276] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 10:07:08.387747 <3>[ 15.382282] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 10:07:08.394220 <3>[ 15.382288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 10:07:08.404015 <3>[ 15.382335] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 10:07:08.411080 <3>[ 15.382358] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10747 10:07:08.420701 <3>[ 15.382364] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 10:07:08.427497 <3>[ 15.382371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 10:07:08.437298 <3>[ 15.382377] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10750 10:07:08.444309 <3>[ 15.382404] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 10:07:08.454055 <4>[ 15.390903] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10752 10:07:08.460556 <6>[ 15.391747] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10753 10:07:08.463485 <6>[ 15.391754] pci_bus 0000:00: root bus resource [bus 00-ff]
10754 10:07:08.473829 <6>[ 15.391761] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10755 10:07:08.483708 <6>[ 15.391767] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10756 10:07:08.487050 <6>[ 15.391802] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10757 10:07:08.496587 <6>[ 15.391827] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10758 10:07:08.500042 <6>[ 15.391925] pci 0000:00:00.0: supports D1 D2
10759 10:07:08.506694 <6>[ 15.391929] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10760 10:07:08.516748 <6>[ 15.393642] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10761 10:07:08.523412 <6>[ 15.393756] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10762 10:07:08.530264 <6>[ 15.393788] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10763 10:07:08.536439 <6>[ 15.393810] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10764 10:07:08.543012 <6>[ 15.393828] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10765 10:07:08.549822 <6>[ 15.393957] pci 0000:01:00.0: supports D1 D2
10766 10:07:08.556508 <6>[ 15.393960] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10767 10:07:08.562936 <6>[ 15.406461] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10768 10:07:08.572732 <6>[ 15.416178] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10769 10:07:08.579242 <6>[ 15.416425] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10770 10:07:08.589500 <6>[ 15.425045] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10771 10:07:08.599561 <6>[ 15.432532] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10772 10:07:08.606239 <6>[ 15.432548] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10773 10:07:08.609237 <6>[ 15.454550] r8152 2-1.3:1.0 eth0: v1.12.13
10774 10:07:08.619296 <6>[ 15.456803] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10775 10:07:08.625899 <6>[ 15.457311] usbcore: registered new interface driver cdc_ether
10776 10:07:08.628983 <6>[ 15.465517] usbcore: registered new interface driver r8153_ecm
10777 10:07:08.639234 <6>[ 15.473219] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10778 10:07:08.642078 <6>[ 15.490625] Bluetooth: Core ver 2.22
10779 10:07:08.648969 <6>[ 15.492489] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10780 10:07:08.652480 <6>[ 15.497452] pci 0000:00:00.0: PCI bridge to [bus 01]
10781 10:07:08.658582 <6>[ 15.505580] NET: Registered PF_BLUETOOTH protocol family
10782 10:07:08.665923 <6>[ 15.506936] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10783 10:07:08.678563 <6>[ 15.508611] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10784 10:07:08.685625 <6>[ 15.508758] usbcore: registered new interface driver uvcvideo
10785 10:07:08.691784 <6>[ 15.513609] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10786 10:07:08.698348 <6>[ 15.521686] Bluetooth: HCI device and connection manager initialized
10787 10:07:08.705036 <6>[ 15.528760] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10788 10:07:08.712059 <6>[ 15.534298] Bluetooth: HCI socket layer initialized
10789 10:07:08.714985 <6>[ 15.542323] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10790 10:07:08.721957 <6>[ 15.551330] Bluetooth: L2CAP socket layer initialized
10791 10:07:08.728254 <6>[ 15.551340] Bluetooth: SCO socket layer initialized
10792 10:07:08.735188 <6>[ 15.551972] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10793 10:07:08.737977 <6>[ 15.557856] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10794 10:07:08.744779 <6>[ 15.599216] usbcore: registered new interface driver btusb
10795 10:07:08.754364 <4>[ 15.600370] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10796 10:07:08.761585 <3>[ 15.600381] Bluetooth: hci0: Failed to load firmware file (-2)
10797 10:07:08.767651 <3>[ 15.600384] Bluetooth: hci0: Failed to set up firmware (-2)
10798 10:07:08.777978 <4>[ 15.600388] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10799 10:07:08.799616 <5>[ 15.860472] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10800 10:07:08.821444 <5>[ 15.882280] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10801 10:07:08.827814 <4>[ 15.889196] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10802 10:07:08.834818 <6>[ 15.898098] cfg80211: failed to load regulatory.db
10803 10:07:08.878602 <6>[ 15.939361] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10804 10:07:08.884720 <6>[ 15.946911] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10805 10:07:08.909290 <6>[ 15.973672] mt7921e 0000:01:00.0: ASIC revision: 79610010
10806 10:07:09.017029 <4>[ 16.074723] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10807 10:07:09.027895 Begin: Loading essential drivers ... done.
10808 10:07:09.031431 Begin: Running /scripts/init-premount ... done.
10809 10:07:09.037779 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10810 10:07:09.047528 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10811 10:07:09.050852 Device /sys/class/net/enx002432307852 found
10812 10:07:09.050932 done.
10813 10:07:09.062369 Begin: Waiting up to 180 secs for any network device to become available ... done.
10814 10:07:09.089671 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10815 10:07:09.138952 <4>[ 16.196711] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10816 10:07:09.259098 <4>[ 16.316287] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10817 10:07:09.374276 <4>[ 16.432043] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10818 10:07:09.490602 <4>[ 16.547970] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10819 10:07:09.606385 <4>[ 16.663980] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10820 10:07:09.722032 <4>[ 16.779883] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10821 10:07:09.838373 <4>[ 16.895772] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10822 10:07:09.954254 <4>[ 17.011794] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10823 10:07:10.041056 <6>[ 17.105050] r8152 2-1.3:1.0 enx002432307852: carrier on
10824 10:07:10.070157 <4>[ 17.127593] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10825 10:07:10.119742 IP-Config: no response after 2 secs - giving up
10826 10:07:10.165835 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10827 10:07:10.172714 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10828 10:07:10.179374 address: 192.168.201.14 broad<3>[ 17.242625] mt7921e 0000:01:00.0: hardware init failed
10829 10:07:10.185769 cast: 192.168.201.255 netmask: 255.255.255.0
10830 10:07:10.192101 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10831 10:07:10.199047 host : mt8192-asurada-spherion-r0-cbg-3
10832 10:07:10.205255 domain : lava-rack
10833 10:07:10.208723 rootserver: 192.168.201.1 rootpath:
10834 10:07:10.209240 filename :
10835 10:07:10.264882 done.
10836 10:07:10.273329 Begin: Running /scripts/nfs-bottom ... done.
10837 10:07:10.292352 Begin: Running /scripts/init-bottom ... done.
10838 10:07:11.585429 <6>[ 18.649531] NET: Registered PF_INET6 protocol family
10839 10:07:11.592237 <6>[ 18.656425] Segment Routing with IPv6
10840 10:07:11.595961 <6>[ 18.660389] In-situ OAM (IOAM) with IPv6
10841 10:07:11.784883 <30>[ 18.822217] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10842 10:07:11.791580 <30>[ 18.854669] systemd[1]: Detected architecture arm64.
10843 10:07:11.802090
10844 10:07:11.804805 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10845 10:07:11.805272
10846 10:07:11.832226 <30>[ 18.896551] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10847 10:07:12.661478 <30>[ 19.722395] systemd[1]: Queued start job for default target graphical.target.
10848 10:07:12.707795 <30>[ 19.768758] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10849 10:07:12.714820 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10850 10:07:12.734554 <30>[ 19.795437] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10851 10:07:12.741320 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10852 10:07:12.763405 <30>[ 19.824059] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10853 10:07:12.772900 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10854 10:07:12.790062 <30>[ 19.851255] systemd[1]: Created slice user.slice - User and Session Slice.
10855 10:07:12.796880 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10856 10:07:12.817654 <30>[ 19.874854] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10857 10:07:12.824191 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10858 10:07:12.845118 <30>[ 19.902813] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10859 10:07:12.851726 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10860 10:07:12.880077 <30>[ 19.931077] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10861 10:07:12.889640 <30>[ 19.950920] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10862 10:07:12.896256 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10863 10:07:12.913555 <30>[ 19.974965] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10864 10:07:12.923701 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10865 10:07:12.938444 <30>[ 20.003001] systemd[1]: Reached target paths.target - Path Units.
10866 10:07:12.945394 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10867 10:07:12.965819 <30>[ 20.026954] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10868 10:07:12.972190 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10869 10:07:12.986167 <30>[ 20.050638] systemd[1]: Reached target slices.target - Slice Units.
10870 10:07:12.996116 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10871 10:07:13.010127 <30>[ 20.074971] systemd[1]: Reached target swap.target - Swaps.
10872 10:07:13.017021 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10873 10:07:13.037448 <30>[ 20.098730] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10874 10:07:13.047122 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10875 10:07:13.065619 <30>[ 20.127286] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10876 10:07:13.075629 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10877 10:07:13.095182 <30>[ 20.156499] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10878 10:07:13.105407 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10879 10:07:13.122601 <30>[ 20.183835] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10880 10:07:13.132471 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10881 10:07:13.149294 <30>[ 20.210948] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10882 10:07:13.155898 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10883 10:07:13.174364 <30>[ 20.235831] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10884 10:07:13.184641 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10885 10:07:13.204125 <30>[ 20.265323] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10886 10:07:13.213514 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10887 10:07:13.230291 <30>[ 20.291379] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10888 10:07:13.239574 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10889 10:07:13.297984 <30>[ 20.358908] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10890 10:07:13.304252 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10891 10:07:13.323788 <30>[ 20.385126] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10892 10:07:13.330161 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10893 10:07:13.385694 <30>[ 20.447033] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10894 10:07:13.392216 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10895 10:07:13.419924 <30>[ 20.474976] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10896 10:07:13.432594 <30>[ 20.494177] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10897 10:07:13.442395 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10898 10:07:13.464552 <30>[ 20.525828] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10899 10:07:13.471208 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10900 10:07:13.510179 <30>[ 20.571238] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10901 10:07:13.516616 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10902 10:07:13.539987 <30>[ 20.601723] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10903 10:07:13.553459 Starting [0;1;39mmodprobe@drm.service[0m - Load Kerne<6>[ 20.614571] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10904 10:07:13.556557 l Module drm...
10905 10:07:13.585754 <30>[ 20.647300] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10906 10:07:13.592518 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10907 10:07:13.616088 <30>[ 20.677673] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10908 10:07:13.623211 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10909 10:07:13.644516 <30>[ 20.705716] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10910 10:07:13.653930 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kern<6>[ 20.718987] fuse: init (API version 7.37)
10911 10:07:13.654045 el Module loop...
10912 10:07:13.678221 <30>[ 20.739845] systemd[1]: Starting systemd-journald.service - Journal Service...
10913 10:07:13.685206 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10914 10:07:13.710379 <30>[ 20.771665] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10915 10:07:13.716948 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10916 10:07:13.743910 <30>[ 20.801896] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10917 10:07:13.750371 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10918 10:07:13.773038 <30>[ 20.834079] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10919 10:07:13.782732 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10920 10:07:13.804603 <30>[ 20.866140] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10921 10:07:13.811366 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10922 10:07:13.831600 <30>[ 20.895319] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10923 10:07:13.841537 <3>[ 20.898992] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 10:07:13.851138 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10925 10:07:13.869890 <30>[ 20.931099] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10926 10:07:13.879907 <3>[ 20.934550] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 10:07:13.886495 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10928 10:07:13.905739 <30>[ 20.967130] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10929 10:07:13.912540 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10930 10:07:13.929598 <3>[ 20.990224] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 10:07:13.938960 <30>[ 20.999972] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10932 10:07:13.949047 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10933 10:07:13.959843 <3>[ 21.021057] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 10:07:13.970156 <30>[ 21.031667] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10935 10:07:13.976846 <30>[ 21.039539] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10936 10:07:13.993630 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Modu<3>[ 21.054329] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 10:07:13.997081 le configfs.
10938 10:07:14.014563 <30>[ 21.075531] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10939 10:07:14.021808 <30>[ 21.083334] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10940 10:07:14.031463 <3>[ 21.085825] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 10:07:14.038113 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10942 10:07:14.054950 <30>[ 21.119577] systemd[1]: modprobe@drm.service: Deactivated successfully.
10943 10:07:14.065873 <30>[ 21.127215] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10944 10:07:14.078747 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 21.139234] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 10:07:14.082662 rm.service[0m - Load Kernel Module drm.
10946 10:07:14.102407 <30>[ 21.163600] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10947 10:07:14.109093 <3>[ 21.169250] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 10:07:14.119138 <30>[ 21.171664] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10949 10:07:14.126168 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10950 10:07:14.141191 <3>[ 21.202904] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 10:07:14.151837 <30>[ 21.213076] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10952 10:07:14.159005 <30>[ 21.220663] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10953 10:07:14.175928 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Mo<3>[ 21.235156] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 10:07:14.176039 dule fuse.
10955 10:07:14.195010 <30>[ 21.256163] systemd[1]: modprobe@loop.service: Deactivated successfully.
10956 10:07:14.201958 <30>[ 21.263648] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10957 10:07:14.208587 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10958 10:07:14.229986 <30>[ 21.291652] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10959 10:07:14.236608 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10960 10:07:14.257987 <30>[ 21.319145] systemd[1]: Started systemd-journald.service - Journal Service.
10961 10:07:14.264533 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10962 10:07:14.283480 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10963 10:07:14.302345 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10964 10:07:14.322618 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10965 10:07:14.369883 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10966 10:07:14.392049 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10967 10:07:14.430309 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10968 10:07:14.453141 <4>[ 21.507643] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10969 10:07:14.462618 <3>[ 21.523329] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10970 10:07:14.469083 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10971 10:07:14.495102 <46>[ 21.556598] systemd-journald[299]: Received client request to flush runtime journal.
10972 10:07:14.501788 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10973 10:07:14.533291 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10974 10:07:14.813848 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10975 10:07:14.833747 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10976 10:07:14.853671 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10977 10:07:14.869924 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10978 10:07:15.269726 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10979 10:07:15.890768 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10980 10:07:15.913395 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10981 10:07:15.957640 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10982 10:07:16.054507 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10983 10:07:16.073575 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10984 10:07:16.089249 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10985 10:07:16.145650 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
10986 10:07:16.170626 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10987 10:07:16.229923 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10988 10:07:16.254357 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
10989 10:07:16.269623 See 'systemctl status systemd-binfmt.service' for details.
10990 10:07:16.463654 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10991 10:07:16.542273 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10992 10:07:16.604834 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10993 10:07:16.676661 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10994 10:07:17.058346 <6>[ 24.123408] remoteproc remoteproc0: powering up scp
10995 10:07:17.069035 <4>[ 24.130975] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10996 10:07:17.076079 <3>[ 24.140875] remoteproc remoteproc0: request_firmware failed: -2
10997 10:07:17.085550 <3>[ 24.147067] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10998 10:07:17.092085 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10999 10:07:17.109245 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11000 10:07:17.125604 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11001 10:07:17.174031 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11002 10:07:17.202588 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11003 10:07:17.224211 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11004 10:07:17.241717 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11005 10:07:17.262653 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11006 10:07:17.288440 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11007 10:07:17.348217 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11008 10:07:17.397032 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11009 10:07:17.429364 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11010 10:07:17.452712 [[0;32m OK [0m] Started [0;1;39msystemd-tim<46>[ 24.513847] systemd-journald[299]: Time jumped backwards, rotating.
11011 10:07:17.455666 esyncd.…0m - Network Time Synchronization.
11012 10:07:17.477871 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11013 10:07:17.497531 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11014 10:07:17.513108 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11015 10:07:18.210603 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11016 10:07:18.535156 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11017 10:07:18.552963 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11018 10:07:18.894583 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11019 10:07:18.916001 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11020 10:07:18.933335 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11021 10:07:19.272896 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11022 10:07:19.289146 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11023 10:07:19.304671 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11024 10:07:19.345926 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11025 10:07:19.384635 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11026 10:07:19.457603 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11027 10:07:19.481852 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11028 10:07:19.650254 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11029 10:07:19.689170 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11030 10:07:19.712015 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11031 10:07:19.733084 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11032 10:07:19.751356 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11033 10:07:19.774344 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11034 10:07:19.799639 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11035 10:07:19.827813 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11036 10:07:19.844640 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11037 10:07:19.893617 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11038 10:07:19.912667 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11039 10:07:19.964385 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11040 10:07:20.060088 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11041 10:07:20.175526
11042 10:07:20.175669
11043 10:07:20.178835 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11044 10:07:20.178919
11045 10:07:20.181792 debian-bookworm-arm64 login: root (automatic login)
11046 10:07:20.181875
11047 10:07:20.181939
11048 10:07:20.449832 Linux debian-bookworm-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023 aarch64
11049 10:07:20.449976
11050 10:07:20.456138 The programs included with the Debian GNU/Linux system are free software;
11051 10:07:20.462719 the exact distribution terms for each program are described in the
11052 10:07:20.466352 individual files in /usr/share/doc/*/copyright.
11053 10:07:20.466434
11054 10:07:20.473025 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11055 10:07:20.476014 permitted by applicable law.
11056 10:07:21.470297 Matched prompt #10: / #
11058 10:07:21.470590 Setting prompt string to ['/ #']
11059 10:07:21.470686 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11061 10:07:21.470881 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11062 10:07:21.470969 start: 2.2.6 expect-shell-connection (timeout 00:03:06) [common]
11063 10:07:21.471042 Setting prompt string to ['/ #']
11064 10:07:21.471103 Forcing a shell prompt, looking for ['/ #']
11066 10:07:21.521322 / #
11067 10:07:21.521441 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11068 10:07:21.521521 Waiting using forced prompt support (timeout 00:02:30)
11069 10:07:21.526347
11070 10:07:21.526621 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11071 10:07:21.526735 start: 2.2.7 export-device-env (timeout 00:03:06) [common]
11073 10:07:21.627214 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10670699/extract-nfsrootfs-1ly9ggbb'
11074 10:07:21.632738 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10670699/extract-nfsrootfs-1ly9ggbb'
11076 10:07:21.733205 / # export NFS_SERVER_IP='192.168.201.1'
11077 10:07:21.738778 export NFS_SERVER_IP='192.168.201.1'
11078 10:07:21.739067 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11079 10:07:21.739173 end: 2.2 depthcharge-retry (duration 00:01:54) [common]
11080 10:07:21.739269 end: 2 depthcharge-action (duration 00:01:54) [common]
11081 10:07:21.739365 start: 3 lava-test-retry (timeout 00:07:22) [common]
11082 10:07:21.739488 start: 3.1 lava-test-shell (timeout 00:07:22) [common]
11083 10:07:21.739564 Using namespace: common
11085 10:07:21.839901 / # #
11086 10:07:21.840046 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11087 10:07:21.844819 #
11088 10:07:21.845085 Using /lava-10670699
11090 10:07:21.945501 / # export SHELL=/bin/bash
11091 10:07:21.951026 export SHELL=/bin/bash
11093 10:07:22.051529 / # . /lava-10670699/environment
11094 10:07:22.056956 . /lava-10670699/environment
11096 10:07:22.163204 / # /lava-10670699/bin/lava-test-runner /lava-10670699/0
11097 10:07:22.163424 Test shell timeout: 10s (minimum of the action and connection timeout)
11098 10:07:22.168519 /lava-10670699/bin/lava-test-runner /lava-10670699/0
11099 10:07:22.418593 + export TESTRUN_ID=0_timesync-off
11100 10:07:22.421652 + TESTRUN_ID=0_timesync-off
11101 10:07:22.425139 + cd /lava-10670699/0/tests/0_timesync-off
11102 10:07:22.428542 ++ cat uuid
11103 10:07:22.432645 + UUID=10670699_1.6.2.3.1
11104 10:07:22.432727 + set +x
11105 10:07:22.439808 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10670699_1.6.2.3.1>
11106 10:07:22.440063 Received signal: <STARTRUN> 0_timesync-off 10670699_1.6.2.3.1
11107 10:07:22.440140 Starting test lava.0_timesync-off (10670699_1.6.2.3.1)
11108 10:07:22.440225 Skipping test definition patterns.
11109 10:07:22.442835 + systemctl stop systemd-timesyncd
11110 10:07:22.499315 + set +x
11111 10:07:22.502487 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10670699_1.6.2.3.1>
11112 10:07:22.502744 Received signal: <ENDRUN> 0_timesync-off 10670699_1.6.2.3.1
11113 10:07:22.502833 Ending use of test pattern.
11114 10:07:22.502896 Ending test lava.0_timesync-off (10670699_1.6.2.3.1), duration 0.06
11116 10:07:22.572903 + export TESTRUN_ID=1_kselftest-alsa
11117 10:07:22.576321 + TESTRUN_ID=1_kselftest-alsa
11118 10:07:22.582372 + cd /lava-10670699/0/tests/1_kselftest-alsa
11119 10:07:22.582458 ++ cat uuid
11120 10:07:22.588023 + UUID=10670699_1.6.2.3.5
11121 10:07:22.588106 + set +x
11122 10:07:22.594931 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 10670699_1.6.2.3.5>
11123 10:07:22.595187 Received signal: <STARTRUN> 1_kselftest-alsa 10670699_1.6.2.3.5
11124 10:07:22.595258 Starting test lava.1_kselftest-alsa (10670699_1.6.2.3.5)
11125 10:07:22.595342 Skipping test definition patterns.
11126 10:07:22.598444 + cd ./automated/linux/kselftest/
11127 10:07:22.624393 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11128 10:07:22.665051 INFO: install_deps skipped
11129 10:07:23.148132 --2023-06-10 10:07:23-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11130 10:07:23.156584 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11131 10:07:23.289573 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11132 10:07:23.422923 HTTP request sent, awaiting response... 200 OK
11133 10:07:23.425710 Length: 2883260 (2.7M) [application/octet-stream]
11134 10:07:23.429078 Saving to: 'kselftest.tar.xz'
11135 10:07:23.429164
11136 10:07:23.429234
11137 10:07:23.688769 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11138 10:07:23.968032 kselftest.tar.xz 1%[ ] 47.81K 180KB/s
11139 10:07:24.221408 kselftest.tar.xz 7%[> ] 197.70K 364KB/s
11140 10:07:24.487336 kselftest.tar.xz 17%[==> ] 505.96K 634KB/s
11141 10:07:24.753764 kselftest.tar.xz 28%[====> ] 804.33K 756KB/s
11142 10:07:25.022268 kselftest.tar.xz 39%[======> ] 1.10M 844KB/s
11143 10:07:25.288674 kselftest.tar.xz 45%[========> ] 1.25M 801KB/s
11144 10:07:25.555020 kselftest.tar.xz 59%[==========> ] 1.64M 901KB/s
11145 10:07:25.795007 kselftest.tar.xz 68%[============> ] 1.88M 903KB/s
11146 10:07:26.016859 kselftest.tar.xz 77%[==============> ] 2.13M 921KB/s
11147 10:07:26.221656 kselftest.tar.xz 86%[================> ] 2.39M 943KB/s
11148 10:07:26.370296 kselftest.tar.xz 91%[=================> ] 2.53M 925KB/s
11149 10:07:26.377270 kselftest.tar.xz 100%[===================>] 2.75M 955KB/s in 2.9s
11150 10:07:26.377360
11151 10:07:26.626558 2023-06-10 10:07:26 (955 KB/s) - 'kselftest.tar.xz' saved [2883260/2883260]
11152 10:07:26.626712
11153 10:07:32.240803 skiplist:
11154 10:07:32.243567 ========================================
11155 10:07:32.246735 ========================================
11156 10:07:32.291563 alsa:mixer-test
11157 10:07:32.311513 ============== Tests to run ===============
11158 10:07:32.311608 alsa:mixer-test
11159 10:07:32.317966 ===========End Tests to run ===============
11160 10:07:32.418897 <12>[ 39.485535] kselftest: Running tests in alsa
11161 10:07:32.429498 TAP version 13
11162 10:07:32.447036 1..1
11163 10:07:32.465141 # selftests: alsa: mixer-test
11164 10:07:32.927604 # TAP version 13
11165 10:07:32.927758 # 1..0
11166 10:07:32.934218 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11167 10:07:32.937236 ok 1 selftests: alsa: mixer-test
11168 10:07:33.604458 alsa_mixer-test pass
11169 10:07:33.636358 + ../../utils/send-to-lava.sh ./output/result.txt
11170 10:07:33.703275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11171 10:07:33.703466 + set +x
11172 10:07:33.703751 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11174 10:07:33.710249 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 10670699_1.6.2.3.5>
11175 10:07:33.710525 Received signal: <ENDRUN> 1_kselftest-alsa 10670699_1.6.2.3.5
11176 10:07:33.710607 Ending use of test pattern.
11177 10:07:33.710705 Ending test lava.1_kselftest-alsa (10670699_1.6.2.3.5), duration 11.12
11179 10:07:33.713251 <LAVA_TEST_RUNNER EXIT>
11180 10:07:33.713524 ok: lava_test_shell seems to have completed
11181 10:07:33.713664 alsa_mixer-test: pass
11182 10:07:33.713796 end: 3.1 lava-test-shell (duration 00:00:12) [common]
11183 10:07:33.713920 end: 3 lava-test-retry (duration 00:00:12) [common]
11184 10:07:33.714051 start: 4 finalize (timeout 00:07:10) [common]
11185 10:07:33.714180 start: 4.1 power-off (timeout 00:00:30) [common]
11186 10:07:33.714472 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11187 10:07:33.790808 >> Command sent successfully.
11188 10:07:33.796094 Returned 0 in 0 seconds
11189 10:07:33.896808 end: 4.1 power-off (duration 00:00:00) [common]
11191 10:07:33.897248 start: 4.2 read-feedback (timeout 00:07:10) [common]
11192 10:07:33.897549 Listened to connection for namespace 'common' for up to 1s
11193 10:07:34.898471 Finalising connection for namespace 'common'
11194 10:07:34.898670 Disconnecting from shell: Finalise
11195 10:07:34.898754 / #
11196 10:07:34.999064 end: 4.2 read-feedback (duration 00:00:01) [common]
11197 10:07:34.999287 end: 4 finalize (duration 00:00:01) [common]
11198 10:07:34.999445 Cleaning after the job
11199 10:07:34.999547 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/ramdisk
11200 10:07:35.001995 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/kernel
11201 10:07:35.011435 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/dtb
11202 10:07:35.011693 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/nfsrootfs
11203 10:07:35.091794 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670699/tftp-deploy-9imtukcw/modules
11204 10:07:35.097791 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10670699
11205 10:07:35.699345 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10670699
11206 10:07:35.699567 Job finished correctly