Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 29
- Errors: 0
1 10:00:50.919124 lava-dispatcher, installed at version: 2023.05.1
2 10:00:50.919320 start: 0 validate
3 10:00:50.919443 Start time: 2023-06-10 10:00:50.919436+00:00 (UTC)
4 10:00:50.919552 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:00:50.919675 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 10:00:51.190102 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:00:51.190897 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:01:03.711531 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:01:03.711704 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:01:03.978699 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:01:03.979430 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:01:04.244254 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:01:04.244938 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:01:06.760876 validate duration: 15.84
16 10:01:06.761137 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:01:06.761230 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:01:06.761316 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:01:06.761445 Not decompressing ramdisk as can be used compressed.
20 10:01:06.761525 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 10:01:06.761587 saving as /var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/ramdisk/initrd.cpio.gz
22 10:01:06.761647 total size: 4665601 (4MB)
23 10:01:07.019726 progress 0% (0MB)
24 10:01:07.021307 progress 5% (0MB)
25 10:01:07.022550 progress 10% (0MB)
26 10:01:07.023878 progress 15% (0MB)
27 10:01:07.025206 progress 20% (0MB)
28 10:01:07.026472 progress 25% (1MB)
29 10:01:07.027760 progress 30% (1MB)
30 10:01:07.029039 progress 35% (1MB)
31 10:01:07.030244 progress 40% (1MB)
32 10:01:07.031716 progress 45% (2MB)
33 10:01:07.033040 progress 50% (2MB)
34 10:01:07.034298 progress 55% (2MB)
35 10:01:07.035573 progress 60% (2MB)
36 10:01:07.036958 progress 65% (2MB)
37 10:01:07.038214 progress 70% (3MB)
38 10:01:07.039532 progress 75% (3MB)
39 10:01:07.040809 progress 80% (3MB)
40 10:01:07.042175 progress 85% (3MB)
41 10:01:07.043407 progress 90% (4MB)
42 10:01:07.044700 progress 95% (4MB)
43 10:01:07.045916 progress 100% (4MB)
44 10:01:07.046096 4MB downloaded in 0.28s (15.64MB/s)
45 10:01:07.046269 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:01:07.046545 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:01:07.046658 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:01:07.046770 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:01:07.046930 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:01:07.046999 saving as /var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/kernel/Image
52 10:01:07.047058 total size: 45746688 (43MB)
53 10:01:07.047116 No compression specified
54 10:01:07.048225 progress 0% (0MB)
55 10:01:07.059517 progress 5% (2MB)
56 10:01:07.071194 progress 10% (4MB)
57 10:01:07.083085 progress 15% (6MB)
58 10:01:07.094712 progress 20% (8MB)
59 10:01:07.106455 progress 25% (10MB)
60 10:01:07.118260 progress 30% (13MB)
61 10:01:07.129894 progress 35% (15MB)
62 10:01:07.141666 progress 40% (17MB)
63 10:01:07.153242 progress 45% (19MB)
64 10:01:07.164851 progress 50% (21MB)
65 10:01:07.176340 progress 55% (24MB)
66 10:01:07.187821 progress 60% (26MB)
67 10:01:07.199371 progress 65% (28MB)
68 10:01:07.211052 progress 70% (30MB)
69 10:01:07.223096 progress 75% (32MB)
70 10:01:07.234615 progress 80% (34MB)
71 10:01:07.246382 progress 85% (37MB)
72 10:01:07.258080 progress 90% (39MB)
73 10:01:07.269552 progress 95% (41MB)
74 10:01:07.281001 progress 100% (43MB)
75 10:01:07.281177 43MB downloaded in 0.23s (186.35MB/s)
76 10:01:07.281330 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:01:07.281560 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:01:07.281649 start: 1.3 download-retry (timeout 00:09:59) [common]
80 10:01:07.281735 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 10:01:07.281870 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 10:01:07.281938 saving as /var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/dtb/mt8192-asurada-spherion-r0.dtb
83 10:01:07.281999 total size: 46924 (0MB)
84 10:01:07.282058 No compression specified
85 10:01:07.283151 progress 69% (0MB)
86 10:01:07.283417 progress 100% (0MB)
87 10:01:07.283569 0MB downloaded in 0.00s (28.55MB/s)
88 10:01:07.283687 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:01:07.283907 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:01:07.283990 start: 1.4 download-retry (timeout 00:09:59) [common]
92 10:01:07.284078 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 10:01:07.284183 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 10:01:07.284249 saving as /var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/nfsrootfs/full.rootfs.tar
95 10:01:07.284307 total size: 200770336 (191MB)
96 10:01:07.284365 Using unxz to decompress xz
97 10:01:07.287862 progress 0% (0MB)
98 10:01:07.823733 progress 5% (9MB)
99 10:01:08.357033 progress 10% (19MB)
100 10:01:08.943449 progress 15% (28MB)
101 10:01:09.309545 progress 20% (38MB)
102 10:01:09.638907 progress 25% (47MB)
103 10:01:10.245498 progress 30% (57MB)
104 10:01:10.811435 progress 35% (67MB)
105 10:01:11.402496 progress 40% (76MB)
106 10:01:11.986838 progress 45% (86MB)
107 10:01:12.565834 progress 50% (95MB)
108 10:01:13.190949 progress 55% (105MB)
109 10:01:13.852322 progress 60% (114MB)
110 10:01:13.991595 progress 65% (124MB)
111 10:01:14.139543 progress 70% (134MB)
112 10:01:14.237644 progress 75% (143MB)
113 10:01:14.318830 progress 80% (153MB)
114 10:01:14.395576 progress 85% (162MB)
115 10:01:14.500434 progress 90% (172MB)
116 10:01:14.786412 progress 95% (181MB)
117 10:01:15.357464 progress 100% (191MB)
118 10:01:15.362027 191MB downloaded in 8.08s (23.70MB/s)
119 10:01:15.362322 end: 1.4.1 http-download (duration 00:00:08) [common]
121 10:01:15.362581 end: 1.4 download-retry (duration 00:00:08) [common]
122 10:01:15.362671 start: 1.5 download-retry (timeout 00:09:51) [common]
123 10:01:15.362757 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 10:01:15.362902 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:01:15.362999 saving as /var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/modules/modules.tar
126 10:01:15.363064 total size: 8540248 (8MB)
127 10:01:15.363126 Using unxz to decompress xz
128 10:01:15.366761 progress 0% (0MB)
129 10:01:15.388951 progress 5% (0MB)
130 10:01:15.413507 progress 10% (0MB)
131 10:01:15.437481 progress 15% (1MB)
132 10:01:15.462587 progress 20% (1MB)
133 10:01:15.486983 progress 25% (2MB)
134 10:01:15.509693 progress 30% (2MB)
135 10:01:15.535321 progress 35% (2MB)
136 10:01:15.559676 progress 40% (3MB)
137 10:01:15.583021 progress 45% (3MB)
138 10:01:15.610062 progress 50% (4MB)
139 10:01:15.634849 progress 55% (4MB)
140 10:01:15.660039 progress 60% (4MB)
141 10:01:15.685158 progress 65% (5MB)
142 10:01:15.709865 progress 70% (5MB)
143 10:01:15.733942 progress 75% (6MB)
144 10:01:15.757133 progress 80% (6MB)
145 10:01:15.781321 progress 85% (6MB)
146 10:01:15.811048 progress 90% (7MB)
147 10:01:15.837715 progress 95% (7MB)
148 10:01:15.863839 progress 100% (8MB)
149 10:01:15.869174 8MB downloaded in 0.51s (16.09MB/s)
150 10:01:15.869461 end: 1.5.1 http-download (duration 00:00:01) [common]
152 10:01:15.869724 end: 1.5 download-retry (duration 00:00:01) [common]
153 10:01:15.869815 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 10:01:15.869906 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 10:01:19.078565 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10670666/extract-nfsrootfs-8_8v8c5l
156 10:01:19.078768 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 10:01:19.078867 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 10:01:19.079029 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5
159 10:01:19.079153 makedir: /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin
160 10:01:19.079250 makedir: /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/tests
161 10:01:19.079344 makedir: /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/results
162 10:01:19.079443 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-add-keys
163 10:01:19.079580 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-add-sources
164 10:01:19.079702 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-background-process-start
165 10:01:19.079823 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-background-process-stop
166 10:01:19.079943 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-common-functions
167 10:01:19.080067 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-echo-ipv4
168 10:01:19.080186 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-install-packages
169 10:01:19.080302 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-installed-packages
170 10:01:19.080417 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-os-build
171 10:01:19.080533 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-probe-channel
172 10:01:19.080651 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-probe-ip
173 10:01:19.080769 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-target-ip
174 10:01:19.080887 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-target-mac
175 10:01:19.081002 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-target-storage
176 10:01:19.081122 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-test-case
177 10:01:19.081240 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-test-event
178 10:01:19.081356 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-test-feedback
179 10:01:19.081473 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-test-raise
180 10:01:19.081588 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-test-reference
181 10:01:19.081704 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-test-runner
182 10:01:19.081821 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-test-set
183 10:01:19.081936 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-test-shell
184 10:01:19.082053 Updating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-add-keys (debian)
185 10:01:19.082195 Updating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-add-sources (debian)
186 10:01:19.082329 Updating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-install-packages (debian)
187 10:01:19.082473 Updating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-installed-packages (debian)
188 10:01:19.082608 Updating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/bin/lava-os-build (debian)
189 10:01:19.082722 Creating /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/environment
190 10:01:19.082817 LAVA metadata
191 10:01:19.082885 - LAVA_JOB_ID=10670666
192 10:01:19.082945 - LAVA_DISPATCHER_IP=192.168.201.1
193 10:01:19.083044 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 10:01:19.083108 skipped lava-vland-overlay
195 10:01:19.083179 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 10:01:19.083256 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 10:01:19.083314 skipped lava-multinode-overlay
198 10:01:19.083384 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 10:01:19.083460 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 10:01:19.083541 Loading test definitions
201 10:01:19.083691 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 10:01:19.083765 Using /lava-10670666 at stage 0
203 10:01:19.084143 uuid=10670666_1.6.2.3.1 testdef=None
204 10:01:19.084233 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 10:01:19.084317 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 10:01:19.084753 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 10:01:19.084966 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 10:01:19.085500 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 10:01:19.085727 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 10:01:19.086258 runner path: /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/0/tests/0_timesync-off test_uuid 10670666_1.6.2.3.1
213 10:01:19.086406 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 10:01:19.086623 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 10:01:19.086693 Using /lava-10670666 at stage 0
217 10:01:19.086785 Fetching tests from https://github.com/kernelci/test-definitions.git
218 10:01:19.086859 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/0/tests/1_kselftest-arm64'
219 10:01:31.039060 Running '/usr/bin/git checkout kernelci.org
220 10:01:31.092771 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 10:01:31.093466 uuid=10670666_1.6.2.3.5 testdef=None
222 10:01:31.093613 end: 1.6.2.3.5 git-repo-action (duration 00:00:12) [common]
224 10:01:31.093873 start: 1.6.2.3.6 test-overlay (timeout 00:09:36) [common]
225 10:01:31.094589 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 10:01:31.094822 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:36) [common]
228 10:01:31.095746 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 10:01:31.095978 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:36) [common]
231 10:01:31.096906 runner path: /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/0/tests/1_kselftest-arm64 test_uuid 10670666_1.6.2.3.5
232 10:01:31.096996 BOARD='mt8192-asurada-spherion-r0'
233 10:01:31.097058 BRANCH='cip'
234 10:01:31.097115 SKIPFILE='/dev/null'
235 10:01:31.097171 SKIP_INSTALL='True'
236 10:01:31.097224 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 10:01:31.097279 TST_CASENAME=''
238 10:01:31.097331 TST_CMDFILES='arm64'
239 10:01:31.097466 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 10:01:31.097664 Creating lava-test-runner.conf files
242 10:01:31.097725 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10670666/lava-overlay-09nlzfr5/lava-10670666/0 for stage 0
243 10:01:31.097841 - 0_timesync-off
244 10:01:31.097910 - 1_kselftest-arm64
245 10:01:31.098002 end: 1.6.2.3 test-definition (duration 00:00:12) [common]
246 10:01:31.098090 start: 1.6.2.4 compress-overlay (timeout 00:09:36) [common]
247 10:01:38.576341 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 10:01:38.576497 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:28) [common]
249 10:01:38.576590 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 10:01:38.576690 end: 1.6.2 lava-overlay (duration 00:00:19) [common]
251 10:01:38.576779 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:28) [common]
252 10:01:38.691373 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 10:01:38.691726 start: 1.6.4 extract-modules (timeout 00:09:28) [common]
254 10:01:38.691842 extracting modules file /var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670666/extract-nfsrootfs-8_8v8c5l
255 10:01:38.889640 extracting modules file /var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670666/extract-overlay-ramdisk-9bzhxkxz/ramdisk
256 10:01:39.091910 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 10:01:39.092139 start: 1.6.5 apply-overlay-tftp (timeout 00:09:28) [common]
258 10:01:39.092233 [common] Applying overlay to NFS
259 10:01:39.092305 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670666/compress-overlay-1jfka_58/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10670666/extract-nfsrootfs-8_8v8c5l
260 10:01:39.981587 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 10:01:39.981763 start: 1.6.6 configure-preseed-file (timeout 00:09:27) [common]
262 10:01:39.981861 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 10:01:39.981948 start: 1.6.7 compress-ramdisk (timeout 00:09:27) [common]
264 10:01:39.982027 Building ramdisk /var/lib/lava/dispatcher/tmp/10670666/extract-overlay-ramdisk-9bzhxkxz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10670666/extract-overlay-ramdisk-9bzhxkxz/ramdisk
265 10:01:40.293948 >> 117806 blocks
266 10:01:42.197168 rename /var/lib/lava/dispatcher/tmp/10670666/extract-overlay-ramdisk-9bzhxkxz/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/ramdisk/ramdisk.cpio.gz
267 10:01:42.197597 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 10:01:42.197710 start: 1.6.8 prepare-kernel (timeout 00:09:25) [common]
269 10:01:42.197807 start: 1.6.8.1 prepare-fit (timeout 00:09:25) [common]
270 10:01:42.197906 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/kernel/Image'
271 10:01:54.238592 Returned 0 in 12 seconds
272 10:01:54.339197 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/kernel/image.itb
273 10:01:54.665735 output: FIT description: Kernel Image image with one or more FDT blobs
274 10:01:54.666093 output: Created: Sat Jun 10 11:01:54 2023
275 10:01:54.666167 output: Image 0 (kernel-1)
276 10:01:54.666231 output: Description:
277 10:01:54.666293 output: Created: Sat Jun 10 11:01:54 2023
278 10:01:54.666354 output: Type: Kernel Image
279 10:01:54.666411 output: Compression: lzma compressed
280 10:01:54.666467 output: Data Size: 10087317 Bytes = 9850.90 KiB = 9.62 MiB
281 10:01:54.666522 output: Architecture: AArch64
282 10:01:54.666576 output: OS: Linux
283 10:01:54.666631 output: Load Address: 0x00000000
284 10:01:54.666687 output: Entry Point: 0x00000000
285 10:01:54.666742 output: Hash algo: crc32
286 10:01:54.666793 output: Hash value: c9e456fd
287 10:01:54.666844 output: Image 1 (fdt-1)
288 10:01:54.666895 output: Description: mt8192-asurada-spherion-r0
289 10:01:54.666946 output: Created: Sat Jun 10 11:01:54 2023
290 10:01:54.666997 output: Type: Flat Device Tree
291 10:01:54.667048 output: Compression: uncompressed
292 10:01:54.667098 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 10:01:54.667149 output: Architecture: AArch64
294 10:01:54.667199 output: Hash algo: crc32
295 10:01:54.667250 output: Hash value: 1df858fa
296 10:01:54.667300 output: Image 2 (ramdisk-1)
297 10:01:54.667350 output: Description: unavailable
298 10:01:54.667401 output: Created: Sat Jun 10 11:01:54 2023
299 10:01:54.667451 output: Type: RAMDisk Image
300 10:01:54.667502 output: Compression: Unknown Compression
301 10:01:54.667552 output: Data Size: 17637611 Bytes = 17224.23 KiB = 16.82 MiB
302 10:01:54.667603 output: Architecture: AArch64
303 10:01:54.667654 output: OS: Linux
304 10:01:54.667704 output: Load Address: unavailable
305 10:01:54.667755 output: Entry Point: unavailable
306 10:01:54.667805 output: Hash algo: crc32
307 10:01:54.667855 output: Hash value: ad8fe73b
308 10:01:54.667905 output: Default Configuration: 'conf-1'
309 10:01:54.667956 output: Configuration 0 (conf-1)
310 10:01:54.668006 output: Description: mt8192-asurada-spherion-r0
311 10:01:54.668101 output: Kernel: kernel-1
312 10:01:54.668153 output: Init Ramdisk: ramdisk-1
313 10:01:54.668203 output: FDT: fdt-1
314 10:01:54.668253 output: Loadables: kernel-1
315 10:01:54.668304 output:
316 10:01:54.668495 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 10:01:54.668590 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 10:01:54.668690 end: 1.6 prepare-tftp-overlay (duration 00:00:39) [common]
319 10:01:54.668783 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:12) [common]
320 10:01:54.668862 No LXC device requested
321 10:01:54.668938 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 10:01:54.669027 start: 1.8 deploy-device-env (timeout 00:09:12) [common]
323 10:01:54.669102 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 10:01:54.669167 Checking files for TFTP limit of 4294967296 bytes.
325 10:01:54.669664 end: 1 tftp-deploy (duration 00:00:48) [common]
326 10:01:54.669774 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 10:01:54.669867 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 10:01:54.669989 substitutions:
329 10:01:54.670056 - {DTB}: 10670666/tftp-deploy-xbw76tuq/dtb/mt8192-asurada-spherion-r0.dtb
330 10:01:54.670120 - {INITRD}: 10670666/tftp-deploy-xbw76tuq/ramdisk/ramdisk.cpio.gz
331 10:01:54.670177 - {KERNEL}: 10670666/tftp-deploy-xbw76tuq/kernel/Image
332 10:01:54.670234 - {LAVA_MAC}: None
333 10:01:54.670289 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10670666/extract-nfsrootfs-8_8v8c5l
334 10:01:54.670344 - {NFS_SERVER_IP}: 192.168.201.1
335 10:01:54.670397 - {PRESEED_CONFIG}: None
336 10:01:54.670450 - {PRESEED_LOCAL}: None
337 10:01:54.670502 - {RAMDISK}: 10670666/tftp-deploy-xbw76tuq/ramdisk/ramdisk.cpio.gz
338 10:01:54.670554 - {ROOT_PART}: None
339 10:01:54.670606 - {ROOT}: None
340 10:01:54.670659 - {SERVER_IP}: 192.168.201.1
341 10:01:54.670711 - {TEE}: None
342 10:01:54.670763 Parsed boot commands:
343 10:01:54.670815 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 10:01:54.670986 Parsed boot commands: tftpboot 192.168.201.1 10670666/tftp-deploy-xbw76tuq/kernel/image.itb 10670666/tftp-deploy-xbw76tuq/kernel/cmdline
345 10:01:54.671077 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 10:01:54.671160 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 10:01:54.671246 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 10:01:54.671330 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 10:01:54.671397 Not connected, no need to disconnect.
350 10:01:54.671468 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 10:01:54.671549 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 10:01:54.671615 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
353 10:01:54.675109 Setting prompt string to ['lava-test: # ']
354 10:01:54.675450 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 10:01:54.675559 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 10:01:54.675653 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 10:01:54.675738 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 10:01:54.675932 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 10:01:59.820182 >> Command sent successfully.
360 10:01:59.830231 Returned 0 in 5 seconds
361 10:01:59.931445 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 10:01:59.932869 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 10:01:59.933441 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 10:01:59.933911 Setting prompt string to 'Starting depthcharge on Spherion...'
366 10:01:59.934253 Changing prompt to 'Starting depthcharge on Spherion...'
367 10:01:59.934620 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 10:01:59.935945 [Enter `^Ec?' for help]
369 10:02:00.098099
370 10:02:00.098608
371 10:02:00.098942 F0: 102B 0000
372 10:02:00.099255
373 10:02:00.100773 F3: 1001 0000 [0200]
374 10:02:00.101205
375 10:02:00.101540 F3: 1001 0000
376 10:02:00.101852
377 10:02:00.102147 F7: 102D 0000
378 10:02:00.102439
379 10:02:00.104133 F1: 0000 0000
380 10:02:00.104556
381 10:02:00.104929 V0: 0000 0000 [0001]
382 10:02:00.105345
383 10:02:00.107278 00: 0007 8000
384 10:02:00.107718
385 10:02:00.108090 01: 0000 0000
386 10:02:00.108422
387 10:02:00.108724 BP: 0C00 0209 [0000]
388 10:02:00.110950
389 10:02:00.111372 G0: 1182 0000
390 10:02:00.111703
391 10:02:00.112015 EC: 0000 0021 [4000]
392 10:02:00.112353
393 10:02:00.114608 S7: 0000 0000 [0000]
394 10:02:00.115052
395 10:02:00.115384 CC: 0000 0000 [0001]
396 10:02:00.115690
397 10:02:00.117920 T0: 0000 0040 [010F]
398 10:02:00.118344
399 10:02:00.118677 Jump to BL
400 10:02:00.118985
401 10:02:00.144107
402 10:02:00.144548
403 10:02:00.144883
404 10:02:00.151514 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 10:02:00.155041 ARM64: Exception handlers installed.
406 10:02:00.158831 ARM64: Testing exception
407 10:02:00.162176 ARM64: Done test exception
408 10:02:00.170353 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 10:02:00.177077 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 10:02:00.183762 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 10:02:00.194973 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 10:02:00.201602 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 10:02:00.211392 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 10:02:00.221596 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 10:02:00.228463 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 10:02:00.247171 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 10:02:00.250133 WDT: Last reset was cold boot
418 10:02:00.253426 SPI1(PAD0) initialized at 2873684 Hz
419 10:02:00.257529 SPI5(PAD0) initialized at 992727 Hz
420 10:02:00.260503 VBOOT: Loading verstage.
421 10:02:00.266761 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 10:02:00.270017 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 10:02:00.274384 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 10:02:00.276822 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 10:02:00.284238 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 10:02:00.291871 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 10:02:00.301899 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 10:02:00.302433
429 10:02:00.302770
430 10:02:00.312320 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 10:02:00.314906 ARM64: Exception handlers installed.
432 10:02:00.318783 ARM64: Testing exception
433 10:02:00.319355 ARM64: Done test exception
434 10:02:00.325484 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 10:02:00.329233 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 10:02:00.342970 Probing TPM: . done!
437 10:02:00.343482 TPM ready after 0 ms
438 10:02:00.350469 Connected to device vid:did:rid of 1ae0:0028:00
439 10:02:00.356699 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 10:02:00.415185 Initialized TPM device CR50 revision 0
441 10:02:00.426851 tlcl_send_startup: Startup return code is 0
442 10:02:00.427411 TPM: setup succeeded
443 10:02:00.438354 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 10:02:00.447285 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 10:02:00.459755 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 10:02:00.469347 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 10:02:00.472677 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 10:02:00.478284 in-header: 03 07 00 00 08 00 00 00
449 10:02:00.481688 in-data: aa e4 47 04 13 02 00 00
450 10:02:00.485901 Chrome EC: UHEPI supported
451 10:02:00.492684 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 10:02:00.496204 in-header: 03 95 00 00 08 00 00 00
453 10:02:00.499746 in-data: 18 20 20 08 00 00 00 00
454 10:02:00.500252 Phase 1
455 10:02:00.503146 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 10:02:00.510818 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 10:02:00.514025 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 10:02:00.517598 Recovery requested (1009000e)
459 10:02:00.527127 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 10:02:00.532501 tlcl_extend: response is 0
461 10:02:00.541767 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 10:02:00.547739 tlcl_extend: response is 0
463 10:02:00.554847 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 10:02:00.574479 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 10:02:00.581099 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 10:02:00.581622
467 10:02:00.581964
468 10:02:00.591357 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 10:02:00.594367 ARM64: Exception handlers installed.
470 10:02:00.597700 ARM64: Testing exception
471 10:02:00.598337 ARM64: Done test exception
472 10:02:00.620193 pmic_efuse_setting: Set efuses in 11 msecs
473 10:02:00.623229 pmwrap_interface_init: Select PMIF_VLD_RDY
474 10:02:00.629867 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 10:02:00.633102 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 10:02:00.639862 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 10:02:00.643604 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 10:02:00.647262 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 10:02:00.655108 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 10:02:00.658261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 10:02:00.661894 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 10:02:00.665726 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 10:02:00.672787 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 10:02:00.676296 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 10:02:00.680471 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 10:02:00.683715 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 10:02:00.692496 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 10:02:00.695867 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 10:02:00.703434 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 10:02:00.710470 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 10:02:00.714585 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 10:02:00.721215 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 10:02:00.725848 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 10:02:00.732871 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 10:02:00.736801 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 10:02:00.743766 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 10:02:00.747452 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 10:02:00.751973 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 10:02:00.758873 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 10:02:00.765700 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 10:02:00.769070 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 10:02:00.772954 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 10:02:00.776857 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 10:02:00.783961 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 10:02:00.787433 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 10:02:00.794980 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 10:02:00.798644 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 10:02:00.801743 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 10:02:00.809590 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 10:02:00.813469 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 10:02:00.817427 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 10:02:00.824136 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 10:02:00.828169 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 10:02:00.831634 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 10:02:00.835584 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 10:02:00.838998 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 10:02:00.846628 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 10:02:00.850151 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 10:02:00.853712 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 10:02:00.857777 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 10:02:00.861040 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 10:02:00.864818 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 10:02:00.871711 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 10:02:00.875293 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 10:02:00.883273 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 10:02:00.890535 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 10:02:00.894452 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 10:02:00.905146 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 10:02:00.912759 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 10:02:00.916232 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 10:02:00.919988 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 10:02:00.923803 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 10:02:00.932857 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x4
534 10:02:00.939353 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 10:02:00.943066 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 10:02:00.946795 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 10:02:00.956977 [RTC]rtc_get_frequency_meter,154: input=15, output=853
538 10:02:00.966535 [RTC]rtc_get_frequency_meter,154: input=7, output=724
539 10:02:00.976593 [RTC]rtc_get_frequency_meter,154: input=11, output=789
540 10:02:00.985187 [RTC]rtc_get_frequency_meter,154: input=13, output=820
541 10:02:00.994535 [RTC]rtc_get_frequency_meter,154: input=12, output=805
542 10:02:01.003937 [RTC]rtc_get_frequency_meter,154: input=11, output=789
543 10:02:01.014221 [RTC]rtc_get_frequency_meter,154: input=12, output=805
544 10:02:01.017642 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 10:02:01.024710 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 10:02:01.028650 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 10:02:01.032173 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 10:02:01.035844 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 10:02:01.039804 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 10:02:01.043218 ADC[4]: Raw value=905541 ID=7
551 10:02:01.046870 ADC[3]: Raw value=213546 ID=1
552 10:02:01.046969 RAM Code: 0x71
553 10:02:01.050370 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 10:02:01.057461 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 10:02:01.065080 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 10:02:01.072658 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 10:02:01.076219 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 10:02:01.080002 in-header: 03 07 00 00 08 00 00 00
559 10:02:01.080097 in-data: aa e4 47 04 13 02 00 00
560 10:02:01.084387 Chrome EC: UHEPI supported
561 10:02:01.090859 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 10:02:01.094055 in-header: 03 95 00 00 08 00 00 00
563 10:02:01.098227 in-data: 18 20 20 08 00 00 00 00
564 10:02:01.101562 MRC: failed to locate region type 0.
565 10:02:01.109605 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 10:02:01.109713 DRAM-K: Running full calibration
567 10:02:01.116587 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 10:02:01.120484 header.status = 0x0
569 10:02:01.124718 header.version = 0x6 (expected: 0x6)
570 10:02:01.124822 header.size = 0xd00 (expected: 0xd00)
571 10:02:01.127868 header.flags = 0x0
572 10:02:01.134583 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 10:02:01.151748 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 10:02:01.159498 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 10:02:01.159612 dram_init: ddr_geometry: 2
576 10:02:01.162851 [EMI] MDL number = 2
577 10:02:01.166447 [EMI] Get MDL freq = 0
578 10:02:01.166548 dram_init: ddr_type: 0
579 10:02:01.170637 is_discrete_lpddr4: 1
580 10:02:01.174256 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 10:02:01.174355
582 10:02:01.174455
583 10:02:01.174544 [Bian_co] ETT version 0.0.0.1
584 10:02:01.181376 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 10:02:01.181456
586 10:02:01.185472 dramc_set_vcore_voltage set vcore to 650000
587 10:02:01.185571 Read voltage for 800, 4
588 10:02:01.188556 Vio18 = 0
589 10:02:01.188630 Vcore = 650000
590 10:02:01.188704 Vdram = 0
591 10:02:01.191863 Vddq = 0
592 10:02:01.191956 Vmddr = 0
593 10:02:01.195278 dram_init: config_dvfs: 1
594 10:02:01.198292 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 10:02:01.205177 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 10:02:01.209424 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 10:02:01.212542 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 10:02:01.216119 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 10:02:01.220291 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 10:02:01.220374 MEM_TYPE=3, freq_sel=18
601 10:02:01.223362 sv_algorithm_assistance_LP4_1600
602 10:02:01.226672 ============ PULL DRAM RESETB DOWN ============
603 10:02:01.233824 ========== PULL DRAM RESETB DOWN end =========
604 10:02:01.236861 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 10:02:01.240398 ===================================
606 10:02:01.244250 LPDDR4 DRAM CONFIGURATION
607 10:02:01.247442 ===================================
608 10:02:01.247524 EX_ROW_EN[0] = 0x0
609 10:02:01.250490 EX_ROW_EN[1] = 0x0
610 10:02:01.250572 LP4Y_EN = 0x0
611 10:02:01.254047 WORK_FSP = 0x0
612 10:02:01.254129 WL = 0x2
613 10:02:01.257286 RL = 0x2
614 10:02:01.257368 BL = 0x2
615 10:02:01.260939 RPST = 0x0
616 10:02:01.261021 RD_PRE = 0x0
617 10:02:01.264553 WR_PRE = 0x1
618 10:02:01.264634 WR_PST = 0x0
619 10:02:01.267587 DBI_WR = 0x0
620 10:02:01.267669 DBI_RD = 0x0
621 10:02:01.270793 OTF = 0x1
622 10:02:01.274293 ===================================
623 10:02:01.277323 ===================================
624 10:02:01.277405 ANA top config
625 10:02:01.280912 ===================================
626 10:02:01.283980 DLL_ASYNC_EN = 0
627 10:02:01.287930 ALL_SLAVE_EN = 1
628 10:02:01.290630 NEW_RANK_MODE = 1
629 10:02:01.290717 DLL_IDLE_MODE = 1
630 10:02:01.293909 LP45_APHY_COMB_EN = 1
631 10:02:01.297560 TX_ODT_DIS = 1
632 10:02:01.301152 NEW_8X_MODE = 1
633 10:02:01.304000 ===================================
634 10:02:01.307633 ===================================
635 10:02:01.311260 data_rate = 1600
636 10:02:01.311342 CKR = 1
637 10:02:01.313951 DQ_P2S_RATIO = 8
638 10:02:01.317145 ===================================
639 10:02:01.320856 CA_P2S_RATIO = 8
640 10:02:01.324586 DQ_CA_OPEN = 0
641 10:02:01.327969 DQ_SEMI_OPEN = 0
642 10:02:01.328092 CA_SEMI_OPEN = 0
643 10:02:01.331350 CA_FULL_RATE = 0
644 10:02:01.334414 DQ_CKDIV4_EN = 1
645 10:02:01.337795 CA_CKDIV4_EN = 1
646 10:02:01.342091 CA_PREDIV_EN = 0
647 10:02:01.344482 PH8_DLY = 0
648 10:02:01.344561 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 10:02:01.347719 DQ_AAMCK_DIV = 4
650 10:02:01.351306 CA_AAMCK_DIV = 4
651 10:02:01.354576 CA_ADMCK_DIV = 4
652 10:02:01.357414 DQ_TRACK_CA_EN = 0
653 10:02:01.361011 CA_PICK = 800
654 10:02:01.361082 CA_MCKIO = 800
655 10:02:01.364420 MCKIO_SEMI = 0
656 10:02:01.367958 PLL_FREQ = 3068
657 10:02:01.371711 DQ_UI_PI_RATIO = 32
658 10:02:01.375453 CA_UI_PI_RATIO = 0
659 10:02:01.379147 ===================================
660 10:02:01.379219 ===================================
661 10:02:01.382885 memory_type:LPDDR4
662 10:02:01.386747 GP_NUM : 10
663 10:02:01.386815 SRAM_EN : 1
664 10:02:01.389986 MD32_EN : 0
665 10:02:01.394240 ===================================
666 10:02:01.394314 [ANA_INIT] >>>>>>>>>>>>>>
667 10:02:01.397880 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 10:02:01.402063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 10:02:01.404911 ===================================
670 10:02:01.407909 data_rate = 1600,PCW = 0X7600
671 10:02:01.411408 ===================================
672 10:02:01.414828 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 10:02:01.418040 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 10:02:01.425232 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 10:02:01.428180 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 10:02:01.431487 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 10:02:01.434971 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 10:02:01.438732 [ANA_INIT] flow start
679 10:02:01.441871 [ANA_INIT] PLL >>>>>>>>
680 10:02:01.441949 [ANA_INIT] PLL <<<<<<<<
681 10:02:01.445437 [ANA_INIT] MIDPI >>>>>>>>
682 10:02:01.448174 [ANA_INIT] MIDPI <<<<<<<<
683 10:02:01.451395 [ANA_INIT] DLL >>>>>>>>
684 10:02:01.451463 [ANA_INIT] flow end
685 10:02:01.454460 ============ LP4 DIFF to SE enter ============
686 10:02:01.461145 ============ LP4 DIFF to SE exit ============
687 10:02:01.461222 [ANA_INIT] <<<<<<<<<<<<<
688 10:02:01.464548 [Flow] Enable top DCM control >>>>>
689 10:02:01.468210 [Flow] Enable top DCM control <<<<<
690 10:02:01.471432 Enable DLL master slave shuffle
691 10:02:01.477724 ==============================================================
692 10:02:01.477828 Gating Mode config
693 10:02:01.484856 ==============================================================
694 10:02:01.488012 Config description:
695 10:02:01.498126 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 10:02:01.504910 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 10:02:01.507542 SELPH_MODE 0: By rank 1: By Phase
698 10:02:01.514189 ==============================================================
699 10:02:01.517833 GAT_TRACK_EN = 1
700 10:02:01.517910 RX_GATING_MODE = 2
701 10:02:01.520821 RX_GATING_TRACK_MODE = 2
702 10:02:01.524455 SELPH_MODE = 1
703 10:02:01.527750 PICG_EARLY_EN = 1
704 10:02:01.530928 VALID_LAT_VALUE = 1
705 10:02:01.537544 ==============================================================
706 10:02:01.541123 Enter into Gating configuration >>>>
707 10:02:01.544449 Exit from Gating configuration <<<<
708 10:02:01.547864 Enter into DVFS_PRE_config >>>>>
709 10:02:01.557330 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 10:02:01.560948 Exit from DVFS_PRE_config <<<<<
711 10:02:01.563999 Enter into PICG configuration >>>>
712 10:02:01.567585 Exit from PICG configuration <<<<
713 10:02:01.570643 [RX_INPUT] configuration >>>>>
714 10:02:01.574294 [RX_INPUT] configuration <<<<<
715 10:02:01.577299 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 10:02:01.584323 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 10:02:01.590950 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 10:02:01.594210 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 10:02:01.600531 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 10:02:01.607203 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 10:02:01.610839 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 10:02:01.617460 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 10:02:01.620521 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 10:02:01.624158 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 10:02:01.627237 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 10:02:01.634610 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 10:02:01.637055 ===================================
728 10:02:01.637131 LPDDR4 DRAM CONFIGURATION
729 10:02:01.641244 ===================================
730 10:02:01.643869 EX_ROW_EN[0] = 0x0
731 10:02:01.647229 EX_ROW_EN[1] = 0x0
732 10:02:01.647305 LP4Y_EN = 0x0
733 10:02:01.650269 WORK_FSP = 0x0
734 10:02:01.650341 WL = 0x2
735 10:02:01.653993 RL = 0x2
736 10:02:01.654098 BL = 0x2
737 10:02:01.657617 RPST = 0x0
738 10:02:01.657694 RD_PRE = 0x0
739 10:02:01.660682 WR_PRE = 0x1
740 10:02:01.660755 WR_PST = 0x0
741 10:02:01.663886 DBI_WR = 0x0
742 10:02:01.663956 DBI_RD = 0x0
743 10:02:01.667329 OTF = 0x1
744 10:02:01.670495 ===================================
745 10:02:01.673706 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 10:02:01.676763 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 10:02:01.683976 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 10:02:01.686714 ===================================
749 10:02:01.686793 LPDDR4 DRAM CONFIGURATION
750 10:02:01.690321 ===================================
751 10:02:01.693777 EX_ROW_EN[0] = 0x10
752 10:02:01.696473 EX_ROW_EN[1] = 0x0
753 10:02:01.696572 LP4Y_EN = 0x0
754 10:02:01.700342 WORK_FSP = 0x0
755 10:02:01.700425 WL = 0x2
756 10:02:01.703215 RL = 0x2
757 10:02:01.703298 BL = 0x2
758 10:02:01.706541 RPST = 0x0
759 10:02:01.706616 RD_PRE = 0x0
760 10:02:01.710033 WR_PRE = 0x1
761 10:02:01.710106 WR_PST = 0x0
762 10:02:01.713197 DBI_WR = 0x0
763 10:02:01.713266 DBI_RD = 0x0
764 10:02:01.716360 OTF = 0x1
765 10:02:01.719958 ===================================
766 10:02:01.726556 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 10:02:01.729569 nWR fixed to 40
768 10:02:01.732876 [ModeRegInit_LP4] CH0 RK0
769 10:02:01.732952 [ModeRegInit_LP4] CH0 RK1
770 10:02:01.736255 [ModeRegInit_LP4] CH1 RK0
771 10:02:01.739960 [ModeRegInit_LP4] CH1 RK1
772 10:02:01.740060 match AC timing 13
773 10:02:01.746413 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 10:02:01.749331 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 10:02:01.752851 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 10:02:01.759558 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 10:02:01.762763 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 10:02:01.762839 [EMI DOE] emi_dcm 0
779 10:02:01.769205 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 10:02:01.769280 ==
781 10:02:01.772397 Dram Type= 6, Freq= 0, CH_0, rank 0
782 10:02:01.775987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 10:02:01.776085 ==
784 10:02:01.783067 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 10:02:01.788965 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 10:02:01.796457 [CA 0] Center 37 (7~68) winsize 62
787 10:02:01.799960 [CA 1] Center 37 (6~68) winsize 63
788 10:02:01.803285 [CA 2] Center 34 (4~65) winsize 62
789 10:02:01.806629 [CA 3] Center 34 (4~65) winsize 62
790 10:02:01.810744 [CA 4] Center 33 (3~64) winsize 62
791 10:02:01.813541 [CA 5] Center 33 (3~64) winsize 62
792 10:02:01.813612
793 10:02:01.816870 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 10:02:01.816936
795 10:02:01.820376 [CATrainingPosCal] consider 1 rank data
796 10:02:01.823320 u2DelayCellTimex100 = 270/100 ps
797 10:02:01.826530 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 10:02:01.833543 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 10:02:01.836961 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 10:02:01.839923 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 10:02:01.843613 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 10:02:01.846341 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 10:02:01.846423
804 10:02:01.849627 CA PerBit enable=1, Macro0, CA PI delay=33
805 10:02:01.849709
806 10:02:01.853350 [CBTSetCACLKResult] CA Dly = 33
807 10:02:01.853434 CS Dly: 5 (0~36)
808 10:02:01.856410 ==
809 10:02:01.859924 Dram Type= 6, Freq= 0, CH_0, rank 1
810 10:02:01.863580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 10:02:01.863663 ==
812 10:02:01.866342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 10:02:01.873153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 10:02:01.883011 [CA 0] Center 38 (7~69) winsize 63
815 10:02:01.886386 [CA 1] Center 37 (7~68) winsize 62
816 10:02:01.889644 [CA 2] Center 35 (4~66) winsize 63
817 10:02:01.893070 [CA 3] Center 34 (4~65) winsize 62
818 10:02:01.896378 [CA 4] Center 34 (3~65) winsize 63
819 10:02:01.900246 [CA 5] Center 33 (3~64) winsize 62
820 10:02:01.900329
821 10:02:01.903486 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 10:02:01.903567
823 10:02:01.906373 [CATrainingPosCal] consider 2 rank data
824 10:02:01.909933 u2DelayCellTimex100 = 270/100 ps
825 10:02:01.913139 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 10:02:01.916913 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 10:02:01.923320 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 10:02:01.926731 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 10:02:01.930282 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 10:02:01.933084 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 10:02:01.933166
832 10:02:01.936940 CA PerBit enable=1, Macro0, CA PI delay=33
833 10:02:01.937022
834 10:02:01.940255 [CBTSetCACLKResult] CA Dly = 33
835 10:02:01.940338 CS Dly: 6 (0~38)
836 10:02:01.940403
837 10:02:01.944078 ----->DramcWriteLeveling(PI) begin...
838 10:02:01.944174 ==
839 10:02:01.946575 Dram Type= 6, Freq= 0, CH_0, rank 0
840 10:02:01.954343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 10:02:01.954425 ==
842 10:02:01.954490 Write leveling (Byte 0): 30 => 30
843 10:02:01.957644 Write leveling (Byte 1): 27 => 27
844 10:02:01.961359 DramcWriteLeveling(PI) end<-----
845 10:02:01.961441
846 10:02:01.961506 ==
847 10:02:01.965451 Dram Type= 6, Freq= 0, CH_0, rank 0
848 10:02:01.968209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 10:02:01.968292 ==
850 10:02:01.971364 [Gating] SW mode calibration
851 10:02:01.978567 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 10:02:01.985294 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 10:02:01.988742 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 10:02:01.991985 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 10:02:01.999174 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 10:02:02.002097 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 10:02:02.005761 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 10:02:02.012099 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 10:02:02.015167 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 10:02:02.018939 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 10:02:02.025122 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 10:02:02.028946 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 10:02:02.031899 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 10:02:02.038597 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 10:02:02.041825 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 10:02:02.045300 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 10:02:02.051654 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 10:02:02.054832 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 10:02:02.058449 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 10:02:02.064917 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 10:02:02.068250 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 10:02:02.071352 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 10:02:02.078351 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 10:02:02.081329 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 10:02:02.085155 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 10:02:02.091472 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 10:02:02.094722 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 10:02:02.097782 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 10:02:02.105392 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
880 10:02:02.107851 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
881 10:02:02.111471 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 10:02:02.114934 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 10:02:02.121367 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 10:02:02.124444 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 10:02:02.127968 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 10:02:02.134751 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
887 10:02:02.138004 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
888 10:02:02.141102 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
889 10:02:02.147859 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 10:02:02.151011 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 10:02:02.154815 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 10:02:02.161069 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 10:02:02.164515 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 10:02:02.167826 0 11 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
895 10:02:02.174735 0 11 8 | B1->B0 | 2929 4343 | 0 0 | (0 0) (0 0)
896 10:02:02.177685 0 11 12 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
897 10:02:02.181235 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 10:02:02.187921 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 10:02:02.191262 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 10:02:02.194383 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 10:02:02.201037 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 10:02:02.204976 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 10:02:02.207699 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 10:02:02.214054 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 10:02:02.217572 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 10:02:02.221143 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 10:02:02.227447 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 10:02:02.231061 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 10:02:02.234354 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 10:02:02.240963 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 10:02:02.244244 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 10:02:02.247488 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 10:02:02.251226 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 10:02:02.257304 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 10:02:02.260558 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 10:02:02.264325 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 10:02:02.270621 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 10:02:02.274201 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 10:02:02.277937 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 10:02:02.280561 Total UI for P1: 0, mck2ui 16
921 10:02:02.284053 best dqsien dly found for B0: ( 0, 14, 4)
922 10:02:02.290649 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
923 10:02:02.294134 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 10:02:02.298086 Total UI for P1: 0, mck2ui 16
925 10:02:02.300936 best dqsien dly found for B1: ( 0, 14, 10)
926 10:02:02.304085 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
927 10:02:02.307492 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 10:02:02.307573
929 10:02:02.310573 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
930 10:02:02.313912 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 10:02:02.317633 [Gating] SW calibration Done
932 10:02:02.317717 ==
933 10:02:02.321232 Dram Type= 6, Freq= 0, CH_0, rank 0
934 10:02:02.324393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 10:02:02.324475 ==
936 10:02:02.327894 RX Vref Scan: 0
937 10:02:02.327992
938 10:02:02.331223 RX Vref 0 -> 0, step: 1
939 10:02:02.331305
940 10:02:02.331369 RX Delay -130 -> 252, step: 16
941 10:02:02.338503 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 10:02:02.341050 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
943 10:02:02.344714 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 10:02:02.347747 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 10:02:02.351321 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
946 10:02:02.357798 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
947 10:02:02.361206 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
948 10:02:02.364299 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
949 10:02:02.367650 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
950 10:02:02.370997 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
951 10:02:02.377338 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
952 10:02:02.380631 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
953 10:02:02.384094 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
954 10:02:02.387512 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
955 10:02:02.393634 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 10:02:02.397021 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
957 10:02:02.397101 ==
958 10:02:02.400356 Dram Type= 6, Freq= 0, CH_0, rank 0
959 10:02:02.404040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 10:02:02.404123 ==
961 10:02:02.407220 DQS Delay:
962 10:02:02.407300 DQS0 = 0, DQS1 = 0
963 10:02:02.407365 DQM Delay:
964 10:02:02.410639 DQM0 = 87, DQM1 = 76
965 10:02:02.410721 DQ Delay:
966 10:02:02.414074 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
967 10:02:02.417185 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
968 10:02:02.420260 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
969 10:02:02.423498 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
970 10:02:02.423579
971 10:02:02.423643
972 10:02:02.423700 ==
973 10:02:02.427052 Dram Type= 6, Freq= 0, CH_0, rank 0
974 10:02:02.433510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 10:02:02.433593 ==
976 10:02:02.433657
977 10:02:02.433714
978 10:02:02.433769 TX Vref Scan disable
979 10:02:02.437254 == TX Byte 0 ==
980 10:02:02.441075 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
981 10:02:02.447131 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
982 10:02:02.447213 == TX Byte 1 ==
983 10:02:02.450552 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
984 10:02:02.457830 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
985 10:02:02.457911 ==
986 10:02:02.460828 Dram Type= 6, Freq= 0, CH_0, rank 0
987 10:02:02.463771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 10:02:02.463853 ==
989 10:02:02.476708 TX Vref=22, minBit 1, minWin=26, winSum=434
990 10:02:02.479749 TX Vref=24, minBit 0, minWin=27, winSum=442
991 10:02:02.483262 TX Vref=26, minBit 1, minWin=27, winSum=443
992 10:02:02.486569 TX Vref=28, minBit 1, minWin=27, winSum=447
993 10:02:02.489887 TX Vref=30, minBit 1, minWin=27, winSum=450
994 10:02:02.496816 TX Vref=32, minBit 2, minWin=27, winSum=447
995 10:02:02.499887 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 30
996 10:02:02.499969
997 10:02:02.503330 Final TX Range 1 Vref 30
998 10:02:02.503411
999 10:02:02.503475 ==
1000 10:02:02.506370 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 10:02:02.509956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 10:02:02.510038 ==
1003 10:02:02.510102
1004 10:02:02.513334
1005 10:02:02.513415 TX Vref Scan disable
1006 10:02:02.516681 == TX Byte 0 ==
1007 10:02:02.519886 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1008 10:02:02.526374 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1009 10:02:02.526455 == TX Byte 1 ==
1010 10:02:02.530211 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1011 10:02:02.536886 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1012 10:02:02.536969
1013 10:02:02.537033 [DATLAT]
1014 10:02:02.537097 Freq=800, CH0 RK0
1015 10:02:02.537170
1016 10:02:02.539717 DATLAT Default: 0xa
1017 10:02:02.539815 0, 0xFFFF, sum = 0
1018 10:02:02.543053 1, 0xFFFF, sum = 0
1019 10:02:02.546366 2, 0xFFFF, sum = 0
1020 10:02:02.546448 3, 0xFFFF, sum = 0
1021 10:02:02.549581 4, 0xFFFF, sum = 0
1022 10:02:02.549664 5, 0xFFFF, sum = 0
1023 10:02:02.553191 6, 0xFFFF, sum = 0
1024 10:02:02.553274 7, 0xFFFF, sum = 0
1025 10:02:02.556523 8, 0x0, sum = 1
1026 10:02:02.556604 9, 0x0, sum = 2
1027 10:02:02.556668 10, 0x0, sum = 3
1028 10:02:02.559474 11, 0x0, sum = 4
1029 10:02:02.559555 best_step = 9
1030 10:02:02.559617
1031 10:02:02.559675 ==
1032 10:02:02.563003 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 10:02:02.569614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 10:02:02.569695 ==
1035 10:02:02.569757 RX Vref Scan: 1
1036 10:02:02.569815
1037 10:02:02.573040 Set Vref Range= 32 -> 127
1038 10:02:02.573119
1039 10:02:02.576695 RX Vref 32 -> 127, step: 1
1040 10:02:02.576775
1041 10:02:02.579636 RX Delay -95 -> 252, step: 8
1042 10:02:02.579715
1043 10:02:02.583306 Set Vref, RX VrefLevel [Byte0]: 32
1044 10:02:02.586419 [Byte1]: 32
1045 10:02:02.586514
1046 10:02:02.589532 Set Vref, RX VrefLevel [Byte0]: 33
1047 10:02:02.593032 [Byte1]: 33
1048 10:02:02.593112
1049 10:02:02.595912 Set Vref, RX VrefLevel [Byte0]: 34
1050 10:02:02.599580 [Byte1]: 34
1051 10:02:02.599660
1052 10:02:02.602768 Set Vref, RX VrefLevel [Byte0]: 35
1053 10:02:02.606229 [Byte1]: 35
1054 10:02:02.610245
1055 10:02:02.610324 Set Vref, RX VrefLevel [Byte0]: 36
1056 10:02:02.613954 [Byte1]: 36
1057 10:02:02.617871
1058 10:02:02.617966 Set Vref, RX VrefLevel [Byte0]: 37
1059 10:02:02.621611 [Byte1]: 37
1060 10:02:02.625963
1061 10:02:02.626043 Set Vref, RX VrefLevel [Byte0]: 38
1062 10:02:02.629110 [Byte1]: 38
1063 10:02:02.633200
1064 10:02:02.633281 Set Vref, RX VrefLevel [Byte0]: 39
1065 10:02:02.636412 [Byte1]: 39
1066 10:02:02.640934
1067 10:02:02.641014 Set Vref, RX VrefLevel [Byte0]: 40
1068 10:02:02.644663 [Byte1]: 40
1069 10:02:02.648407
1070 10:02:02.648490 Set Vref, RX VrefLevel [Byte0]: 41
1071 10:02:02.652091 [Byte1]: 41
1072 10:02:02.655963
1073 10:02:02.656068 Set Vref, RX VrefLevel [Byte0]: 42
1074 10:02:02.659268 [Byte1]: 42
1075 10:02:02.663268
1076 10:02:02.663349 Set Vref, RX VrefLevel [Byte0]: 43
1077 10:02:02.666820 [Byte1]: 43
1078 10:02:02.670967
1079 10:02:02.671046 Set Vref, RX VrefLevel [Byte0]: 44
1080 10:02:02.674097 [Byte1]: 44
1081 10:02:02.678667
1082 10:02:02.678747 Set Vref, RX VrefLevel [Byte0]: 45
1083 10:02:02.682128 [Byte1]: 45
1084 10:02:02.686389
1085 10:02:02.686470 Set Vref, RX VrefLevel [Byte0]: 46
1086 10:02:02.689546 [Byte1]: 46
1087 10:02:02.693539
1088 10:02:02.693620 Set Vref, RX VrefLevel [Byte0]: 47
1089 10:02:02.697185 [Byte1]: 47
1090 10:02:02.701451
1091 10:02:02.701558 Set Vref, RX VrefLevel [Byte0]: 48
1092 10:02:02.704415 [Byte1]: 48
1093 10:02:02.709461
1094 10:02:02.709543 Set Vref, RX VrefLevel [Byte0]: 49
1095 10:02:02.712047 [Byte1]: 49
1096 10:02:02.716597
1097 10:02:02.716678 Set Vref, RX VrefLevel [Byte0]: 50
1098 10:02:02.719780 [Byte1]: 50
1099 10:02:02.723870
1100 10:02:02.723950 Set Vref, RX VrefLevel [Byte0]: 51
1101 10:02:02.727519 [Byte1]: 51
1102 10:02:02.731735
1103 10:02:02.731816 Set Vref, RX VrefLevel [Byte0]: 52
1104 10:02:02.734938 [Byte1]: 52
1105 10:02:02.739459
1106 10:02:02.739552 Set Vref, RX VrefLevel [Byte0]: 53
1107 10:02:02.742920 [Byte1]: 53
1108 10:02:02.746828
1109 10:02:02.746911 Set Vref, RX VrefLevel [Byte0]: 54
1110 10:02:02.750280 [Byte1]: 54
1111 10:02:02.754159
1112 10:02:02.754240 Set Vref, RX VrefLevel [Byte0]: 55
1113 10:02:02.757536 [Byte1]: 55
1114 10:02:02.761790
1115 10:02:02.761888 Set Vref, RX VrefLevel [Byte0]: 56
1116 10:02:02.765195 [Byte1]: 56
1117 10:02:02.769934
1118 10:02:02.770014 Set Vref, RX VrefLevel [Byte0]: 57
1119 10:02:02.773513 [Byte1]: 57
1120 10:02:02.777847
1121 10:02:02.777929 Set Vref, RX VrefLevel [Byte0]: 58
1122 10:02:02.780788 [Byte1]: 58
1123 10:02:02.784888
1124 10:02:02.784969 Set Vref, RX VrefLevel [Byte0]: 59
1125 10:02:02.788949 [Byte1]: 59
1126 10:02:02.792577
1127 10:02:02.792658 Set Vref, RX VrefLevel [Byte0]: 60
1128 10:02:02.795716 [Byte1]: 60
1129 10:02:02.800327
1130 10:02:02.800411 Set Vref, RX VrefLevel [Byte0]: 61
1131 10:02:02.803358 [Byte1]: 61
1132 10:02:02.807584
1133 10:02:02.807668 Set Vref, RX VrefLevel [Byte0]: 62
1134 10:02:02.811043 [Byte1]: 62
1135 10:02:02.815271
1136 10:02:02.815352 Set Vref, RX VrefLevel [Byte0]: 63
1137 10:02:02.818485 [Byte1]: 63
1138 10:02:02.822603
1139 10:02:02.822684 Set Vref, RX VrefLevel [Byte0]: 64
1140 10:02:02.826246 [Byte1]: 64
1141 10:02:02.830762
1142 10:02:02.830843 Set Vref, RX VrefLevel [Byte0]: 65
1143 10:02:02.833665 [Byte1]: 65
1144 10:02:02.837977
1145 10:02:02.838060 Set Vref, RX VrefLevel [Byte0]: 66
1146 10:02:02.841325 [Byte1]: 66
1147 10:02:02.845592
1148 10:02:02.845672 Set Vref, RX VrefLevel [Byte0]: 67
1149 10:02:02.848895 [Byte1]: 67
1150 10:02:02.853404
1151 10:02:02.853484 Set Vref, RX VrefLevel [Byte0]: 68
1152 10:02:02.856454 [Byte1]: 68
1153 10:02:02.860721
1154 10:02:02.860803 Set Vref, RX VrefLevel [Byte0]: 69
1155 10:02:02.864361 [Byte1]: 69
1156 10:02:02.868666
1157 10:02:02.868746 Set Vref, RX VrefLevel [Byte0]: 70
1158 10:02:02.871942 [Byte1]: 70
1159 10:02:02.876187
1160 10:02:02.876267 Set Vref, RX VrefLevel [Byte0]: 71
1161 10:02:02.879295 [Byte1]: 71
1162 10:02:02.883461
1163 10:02:02.883541 Set Vref, RX VrefLevel [Byte0]: 72
1164 10:02:02.887018 [Byte1]: 72
1165 10:02:02.891356
1166 10:02:02.891436 Set Vref, RX VrefLevel [Byte0]: 73
1167 10:02:02.894441 [Byte1]: 73
1168 10:02:02.898471
1169 10:02:02.898551 Final RX Vref Byte 0 = 57 to rank0
1170 10:02:02.902169 Final RX Vref Byte 1 = 60 to rank0
1171 10:02:02.905343 Final RX Vref Byte 0 = 57 to rank1
1172 10:02:02.908737 Final RX Vref Byte 1 = 60 to rank1==
1173 10:02:02.912413 Dram Type= 6, Freq= 0, CH_0, rank 0
1174 10:02:02.918589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1175 10:02:02.918671 ==
1176 10:02:02.918736 DQS Delay:
1177 10:02:02.918795 DQS0 = 0, DQS1 = 0
1178 10:02:02.922247 DQM Delay:
1179 10:02:02.922328 DQM0 = 88, DQM1 = 76
1180 10:02:02.925301 DQ Delay:
1181 10:02:02.928339 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1182 10:02:02.931798 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1183 10:02:02.935253 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1184 10:02:02.938498 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1185 10:02:02.938579
1186 10:02:02.938660
1187 10:02:02.945356 [DQSOSCAuto] RK0, (LSB)MR18= 0x332c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
1188 10:02:02.948407 CH0 RK0: MR19=606, MR18=332C
1189 10:02:02.954993 CH0_RK0: MR19=0x606, MR18=0x332C, DQSOSC=396, MR23=63, INC=94, DEC=62
1190 10:02:02.955074
1191 10:02:02.958177 ----->DramcWriteLeveling(PI) begin...
1192 10:02:02.958259 ==
1193 10:02:02.961706 Dram Type= 6, Freq= 0, CH_0, rank 1
1194 10:02:02.965393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1195 10:02:02.965474 ==
1196 10:02:02.968395 Write leveling (Byte 0): 30 => 30
1197 10:02:02.971557 Write leveling (Byte 1): 26 => 26
1198 10:02:02.974793 DramcWriteLeveling(PI) end<-----
1199 10:02:02.974873
1200 10:02:02.974936 ==
1201 10:02:02.978023 Dram Type= 6, Freq= 0, CH_0, rank 1
1202 10:02:02.981311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1203 10:02:02.981392 ==
1204 10:02:02.984706 [Gating] SW mode calibration
1205 10:02:02.991475 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1206 10:02:02.998135 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1207 10:02:03.001562 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1208 10:02:03.008393 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1209 10:02:03.052019 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 10:02:03.052152 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 10:02:03.052685 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 10:02:03.052946 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 10:02:03.053017 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 10:02:03.053579 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 10:02:03.053660 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 10:02:03.054076 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 10:02:03.054644 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 10:02:03.055072 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 10:02:03.096175 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 10:02:03.096257 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 10:02:03.096502 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 10:02:03.096580 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 10:02:03.097004 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1224 10:02:03.097650 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1225 10:02:03.097731 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1226 10:02:03.098182 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 10:02:03.098440 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 10:02:03.098507 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 10:02:03.115758 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 10:02:03.115840 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 10:02:03.116094 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 10:02:03.116806 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1233 10:02:03.119401 0 9 8 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
1234 10:02:03.122858 0 9 12 | B1->B0 | 302f 3434 | 1 1 | (1 1) (1 1)
1235 10:02:03.126012 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 10:02:03.129302 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 10:02:03.132701 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 10:02:03.138994 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 10:02:03.142382 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 10:02:03.145699 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1241 10:02:03.152412 0 10 8 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
1242 10:02:03.155675 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 10:02:03.158909 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 10:02:03.165583 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 10:02:03.168893 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 10:02:03.172488 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 10:02:03.179218 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 10:02:03.181758 0 11 4 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
1249 10:02:03.185599 0 11 8 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
1250 10:02:03.192306 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1251 10:02:03.195785 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 10:02:03.199089 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 10:02:03.202887 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 10:02:03.210334 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 10:02:03.213967 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 10:02:03.216940 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 10:02:03.220297 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1258 10:02:03.227264 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 10:02:03.230602 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 10:02:03.234061 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 10:02:03.240811 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 10:02:03.244177 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 10:02:03.247262 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 10:02:03.254379 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 10:02:03.257644 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 10:02:03.260499 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 10:02:03.267183 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 10:02:03.270838 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 10:02:03.274155 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 10:02:03.277459 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 10:02:03.284024 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1272 10:02:03.287312 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1273 10:02:03.290853 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1274 10:02:03.297570 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 10:02:03.300448 Total UI for P1: 0, mck2ui 16
1276 10:02:03.303904 best dqsien dly found for B0: ( 0, 14, 4)
1277 10:02:03.303985 Total UI for P1: 0, mck2ui 16
1278 10:02:03.310557 best dqsien dly found for B1: ( 0, 14, 10)
1279 10:02:03.313718 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1280 10:02:03.316987 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1281 10:02:03.317067
1282 10:02:03.320782 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1283 10:02:03.323819 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1284 10:02:03.327292 [Gating] SW calibration Done
1285 10:02:03.327372 ==
1286 10:02:03.330230 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 10:02:03.333652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 10:02:03.333733 ==
1289 10:02:03.336887 RX Vref Scan: 0
1290 10:02:03.336968
1291 10:02:03.337032 RX Vref 0 -> 0, step: 1
1292 10:02:03.337090
1293 10:02:03.340491 RX Delay -130 -> 252, step: 16
1294 10:02:03.347057 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1295 10:02:03.350502 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1296 10:02:03.353632 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1297 10:02:03.356831 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1298 10:02:03.360405 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1299 10:02:03.367506 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1300 10:02:03.370277 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1301 10:02:03.373752 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1302 10:02:03.377081 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1303 10:02:03.379870 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1304 10:02:03.386620 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1305 10:02:03.390063 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1306 10:02:03.393393 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1307 10:02:03.396483 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1308 10:02:03.400187 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1309 10:02:03.406733 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1310 10:02:03.406814 ==
1311 10:02:03.409804 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 10:02:03.413977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 10:02:03.414058 ==
1314 10:02:03.414138 DQS Delay:
1315 10:02:03.416470 DQS0 = 0, DQS1 = 0
1316 10:02:03.416551 DQM Delay:
1317 10:02:03.419626 DQM0 = 86, DQM1 = 77
1318 10:02:03.419707 DQ Delay:
1319 10:02:03.423249 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1320 10:02:03.426679 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1321 10:02:03.429972 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1322 10:02:03.433245 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1323 10:02:03.433326
1324 10:02:03.433389
1325 10:02:03.433446 ==
1326 10:02:03.436633 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 10:02:03.439996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 10:02:03.442827 ==
1329 10:02:03.442908
1330 10:02:03.442971
1331 10:02:03.443030 TX Vref Scan disable
1332 10:02:03.446486 == TX Byte 0 ==
1333 10:02:03.449687 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1334 10:02:03.453069 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1335 10:02:03.456277 == TX Byte 1 ==
1336 10:02:03.459838 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1337 10:02:03.462654 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1338 10:02:03.466439 ==
1339 10:02:03.469573 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 10:02:03.472551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 10:02:03.472633 ==
1342 10:02:03.485113 TX Vref=22, minBit 0, minWin=27, winSum=441
1343 10:02:03.488490 TX Vref=24, minBit 1, minWin=27, winSum=444
1344 10:02:03.491914 TX Vref=26, minBit 1, minWin=27, winSum=447
1345 10:02:03.495452 TX Vref=28, minBit 6, minWin=27, winSum=451
1346 10:02:03.498467 TX Vref=30, minBit 2, minWin=27, winSum=447
1347 10:02:03.505110 TX Vref=32, minBit 1, minWin=27, winSum=450
1348 10:02:03.508602 [TxChooseVref] Worse bit 6, Min win 27, Win sum 451, Final Vref 28
1349 10:02:03.508683
1350 10:02:03.511694 Final TX Range 1 Vref 28
1351 10:02:03.511776
1352 10:02:03.511839 ==
1353 10:02:03.515183 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 10:02:03.518828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 10:02:03.521606 ==
1356 10:02:03.521687
1357 10:02:03.521751
1358 10:02:03.521809 TX Vref Scan disable
1359 10:02:03.525546 == TX Byte 0 ==
1360 10:02:03.528740 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1361 10:02:03.535384 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1362 10:02:03.535466 == TX Byte 1 ==
1363 10:02:03.538218 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1364 10:02:03.545059 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1365 10:02:03.545139
1366 10:02:03.545201 [DATLAT]
1367 10:02:03.545258 Freq=800, CH0 RK1
1368 10:02:03.545314
1369 10:02:03.548267 DATLAT Default: 0x9
1370 10:02:03.548345 0, 0xFFFF, sum = 0
1371 10:02:03.551782 1, 0xFFFF, sum = 0
1372 10:02:03.551862 2, 0xFFFF, sum = 0
1373 10:02:03.555076 3, 0xFFFF, sum = 0
1374 10:02:03.558248 4, 0xFFFF, sum = 0
1375 10:02:03.558329 5, 0xFFFF, sum = 0
1376 10:02:03.561493 6, 0xFFFF, sum = 0
1377 10:02:03.561574 7, 0xFFFF, sum = 0
1378 10:02:03.565353 8, 0xFFFF, sum = 0
1379 10:02:03.565434 9, 0x0, sum = 1
1380 10:02:03.568469 10, 0x0, sum = 2
1381 10:02:03.568549 11, 0x0, sum = 3
1382 10:02:03.568612 12, 0x0, sum = 4
1383 10:02:03.571858 best_step = 10
1384 10:02:03.571937
1385 10:02:03.571999 ==
1386 10:02:03.574861 Dram Type= 6, Freq= 0, CH_0, rank 1
1387 10:02:03.578080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1388 10:02:03.578160 ==
1389 10:02:03.581451 RX Vref Scan: 0
1390 10:02:03.581529
1391 10:02:03.581591 RX Vref 0 -> 0, step: 1
1392 10:02:03.584881
1393 10:02:03.584961 RX Delay -95 -> 252, step: 8
1394 10:02:03.591819 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1395 10:02:03.595122 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1396 10:02:03.599102 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1397 10:02:03.601526 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1398 10:02:03.605118 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1399 10:02:03.611669 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1400 10:02:03.614882 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1401 10:02:03.618219 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1402 10:02:03.622212 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1403 10:02:03.625040 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1404 10:02:03.631310 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1405 10:02:03.634872 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1406 10:02:03.638531 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1407 10:02:03.641684 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1408 10:02:03.648796 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1409 10:02:03.651525 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1410 10:02:03.651604 ==
1411 10:02:03.655245 Dram Type= 6, Freq= 0, CH_0, rank 1
1412 10:02:03.658351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1413 10:02:03.658432 ==
1414 10:02:03.658494 DQS Delay:
1415 10:02:03.661673 DQS0 = 0, DQS1 = 0
1416 10:02:03.661753 DQM Delay:
1417 10:02:03.664946 DQM0 = 86, DQM1 = 77
1418 10:02:03.665025 DQ Delay:
1419 10:02:03.668433 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1420 10:02:03.671484 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1421 10:02:03.674619 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1422 10:02:03.678056 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1423 10:02:03.678136
1424 10:02:03.678197
1425 10:02:03.687942 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1426 10:02:03.688023 CH0 RK1: MR19=606, MR18=2D28
1427 10:02:03.694657 CH0_RK1: MR19=0x606, MR18=0x2D28, DQSOSC=398, MR23=63, INC=93, DEC=62
1428 10:02:03.698003 [RxdqsGatingPostProcess] freq 800
1429 10:02:03.704507 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1430 10:02:03.707952 Pre-setting of DQS Precalculation
1431 10:02:03.711168 [DualRankRxdatlatCal] RK0: 9, RK1: 10, Final_Datlat 10
1432 10:02:03.711248 ==
1433 10:02:03.714842 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 10:02:03.717972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 10:02:03.721101 ==
1436 10:02:03.724628 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1437 10:02:03.730991 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1438 10:02:03.740753 [CA 0] Center 36 (6~67) winsize 62
1439 10:02:03.743661 [CA 1] Center 37 (6~68) winsize 63
1440 10:02:03.746898 [CA 2] Center 35 (5~65) winsize 61
1441 10:02:03.750552 [CA 3] Center 34 (4~65) winsize 62
1442 10:02:03.753553 [CA 4] Center 34 (4~65) winsize 62
1443 10:02:03.756986 [CA 5] Center 34 (3~65) winsize 63
1444 10:02:03.757065
1445 10:02:03.760589 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1446 10:02:03.760668
1447 10:02:03.763607 [CATrainingPosCal] consider 1 rank data
1448 10:02:03.766579 u2DelayCellTimex100 = 270/100 ps
1449 10:02:03.770252 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1450 10:02:03.773200 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1451 10:02:03.780354 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1452 10:02:03.783439 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1453 10:02:03.786678 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1454 10:02:03.790252 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1455 10:02:03.790333
1456 10:02:03.793842 CA PerBit enable=1, Macro0, CA PI delay=34
1457 10:02:03.793923
1458 10:02:03.797390 [CBTSetCACLKResult] CA Dly = 34
1459 10:02:03.797471 CS Dly: 4 (0~35)
1460 10:02:03.800292 ==
1461 10:02:03.800373 Dram Type= 6, Freq= 0, CH_1, rank 1
1462 10:02:03.806661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1463 10:02:03.806743 ==
1464 10:02:03.809780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1465 10:02:03.816397 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1466 10:02:03.826205 [CA 0] Center 36 (6~67) winsize 62
1467 10:02:03.829475 [CA 1] Center 37 (6~68) winsize 63
1468 10:02:03.832848 [CA 2] Center 34 (4~65) winsize 62
1469 10:02:03.836174 [CA 3] Center 34 (3~65) winsize 63
1470 10:02:03.839243 [CA 4] Center 34 (3~65) winsize 63
1471 10:02:03.842589 [CA 5] Center 33 (3~64) winsize 62
1472 10:02:03.842670
1473 10:02:03.845832 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1474 10:02:03.845914
1475 10:02:03.849247 [CATrainingPosCal] consider 2 rank data
1476 10:02:03.853491 u2DelayCellTimex100 = 270/100 ps
1477 10:02:03.856077 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1478 10:02:03.859516 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1479 10:02:03.863343 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1480 10:02:03.866977 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1481 10:02:03.870207 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1482 10:02:03.877458 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1483 10:02:03.877540
1484 10:02:03.881561 CA PerBit enable=1, Macro0, CA PI delay=33
1485 10:02:03.881642
1486 10:02:03.881705 [CBTSetCACLKResult] CA Dly = 33
1487 10:02:03.884895 CS Dly: 5 (0~37)
1488 10:02:03.884976
1489 10:02:03.888634 ----->DramcWriteLeveling(PI) begin...
1490 10:02:03.888717 ==
1491 10:02:03.892277 Dram Type= 6, Freq= 0, CH_1, rank 0
1492 10:02:03.896640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1493 10:02:03.896740 ==
1494 10:02:03.899149 Write leveling (Byte 0): 28 => 28
1495 10:02:03.902343 Write leveling (Byte 1): 28 => 28
1496 10:02:03.906104 DramcWriteLeveling(PI) end<-----
1497 10:02:03.906185
1498 10:02:03.906249 ==
1499 10:02:03.909021 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 10:02:03.912339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1501 10:02:03.912421 ==
1502 10:02:03.915586 [Gating] SW mode calibration
1503 10:02:03.922536 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1504 10:02:03.929210 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1505 10:02:03.932304 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1506 10:02:03.935795 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1507 10:02:03.942208 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 10:02:03.945572 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 10:02:03.949175 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 10:02:03.955886 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 10:02:03.958469 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 10:02:03.962389 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 10:02:03.968436 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 10:02:03.972066 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 10:02:03.975406 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 10:02:03.982082 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 10:02:03.985221 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 10:02:03.988407 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 10:02:03.994978 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 10:02:03.999256 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 10:02:04.001827 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1522 10:02:04.008898 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1523 10:02:04.011602 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 10:02:04.014776 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 10:02:04.021774 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 10:02:04.025212 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 10:02:04.027990 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 10:02:04.031950 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 10:02:04.038159 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 10:02:04.041672 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
1531 10:02:04.044749 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1532 10:02:04.051465 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 10:02:04.055121 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 10:02:04.058136 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 10:02:04.064472 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 10:02:04.067900 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 10:02:04.071081 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 10:02:04.077680 0 10 4 | B1->B0 | 3232 3030 | 0 0 | (0 1) (0 0)
1539 10:02:04.081493 0 10 8 | B1->B0 | 2525 2424 | 0 0 | (1 0) (1 0)
1540 10:02:04.084777 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 10:02:04.091340 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 10:02:04.094425 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 10:02:04.097975 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 10:02:04.104273 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 10:02:04.107709 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 10:02:04.111197 0 11 4 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (1 1)
1547 10:02:04.117746 0 11 8 | B1->B0 | 3e3e 4444 | 0 0 | (0 0) (0 0)
1548 10:02:04.121396 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 10:02:04.124557 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 10:02:04.130895 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 10:02:04.134259 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 10:02:04.137527 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 10:02:04.144148 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 10:02:04.147595 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1555 10:02:04.151246 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 10:02:04.158177 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 10:02:04.160940 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 10:02:04.164719 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 10:02:04.170975 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 10:02:04.174543 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 10:02:04.177652 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 10:02:04.184015 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 10:02:04.187804 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 10:02:04.191257 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 10:02:04.197808 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 10:02:04.200822 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 10:02:04.204444 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 10:02:04.207478 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 10:02:04.214407 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 10:02:04.217316 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1571 10:02:04.220542 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1572 10:02:04.227499 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 10:02:04.230393 Total UI for P1: 0, mck2ui 16
1574 10:02:04.234052 best dqsien dly found for B0: ( 0, 14, 6)
1575 10:02:04.234134 Total UI for P1: 0, mck2ui 16
1576 10:02:04.241007 best dqsien dly found for B1: ( 0, 14, 6)
1577 10:02:04.244098 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1578 10:02:04.247548 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1579 10:02:04.247630
1580 10:02:04.250555 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1581 10:02:04.254102 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1582 10:02:04.257884 [Gating] SW calibration Done
1583 10:02:04.257966 ==
1584 10:02:04.260699 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 10:02:04.264104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 10:02:04.264186 ==
1587 10:02:04.266993 RX Vref Scan: 0
1588 10:02:04.267074
1589 10:02:04.267138 RX Vref 0 -> 0, step: 1
1590 10:02:04.267196
1591 10:02:04.270768 RX Delay -130 -> 252, step: 16
1592 10:02:04.274094 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1593 10:02:04.280430 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1594 10:02:04.283803 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1595 10:02:04.287748 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1596 10:02:04.290551 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1597 10:02:04.293763 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1598 10:02:04.300384 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1599 10:02:04.303372 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1600 10:02:04.306930 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1601 10:02:04.309931 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1602 10:02:04.313522 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1603 10:02:04.320589 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1604 10:02:04.323708 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1605 10:02:04.327422 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1606 10:02:04.330435 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1607 10:02:04.337142 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1608 10:02:04.337224 ==
1609 10:02:04.340191 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 10:02:04.343559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 10:02:04.343641 ==
1612 10:02:04.343706 DQS Delay:
1613 10:02:04.348286 DQS0 = 0, DQS1 = 0
1614 10:02:04.348368 DQM Delay:
1615 10:02:04.350016 DQM0 = 85, DQM1 = 79
1616 10:02:04.350096 DQ Delay:
1617 10:02:04.353460 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1618 10:02:04.356592 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1619 10:02:04.359965 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1620 10:02:04.363801 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1621 10:02:04.363883
1622 10:02:04.363947
1623 10:02:04.364006 ==
1624 10:02:04.366720 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 10:02:04.369934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 10:02:04.370017 ==
1627 10:02:04.370081
1628 10:02:04.370166
1629 10:02:04.373239 TX Vref Scan disable
1630 10:02:04.376847 == TX Byte 0 ==
1631 10:02:04.380325 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1632 10:02:04.383329 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1633 10:02:04.387442 == TX Byte 1 ==
1634 10:02:04.390061 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1635 10:02:04.393364 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1636 10:02:04.393448 ==
1637 10:02:04.396793 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 10:02:04.403437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 10:02:04.403522 ==
1640 10:02:04.414957 TX Vref=22, minBit 5, minWin=26, winSum=438
1641 10:02:04.417950 TX Vref=24, minBit 1, minWin=27, winSum=446
1642 10:02:04.421575 TX Vref=26, minBit 3, minWin=27, winSum=453
1643 10:02:04.424516 TX Vref=28, minBit 2, minWin=27, winSum=455
1644 10:02:04.428582 TX Vref=30, minBit 2, minWin=27, winSum=450
1645 10:02:04.435227 TX Vref=32, minBit 1, minWin=27, winSum=451
1646 10:02:04.437999 [TxChooseVref] Worse bit 2, Min win 27, Win sum 455, Final Vref 28
1647 10:02:04.438083
1648 10:02:04.441701 Final TX Range 1 Vref 28
1649 10:02:04.441786
1650 10:02:04.441869 ==
1651 10:02:04.445368 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 10:02:04.448953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 10:02:04.449038 ==
1654 10:02:04.449121
1655 10:02:04.449211
1656 10:02:04.452377 TX Vref Scan disable
1657 10:02:04.455205 == TX Byte 0 ==
1658 10:02:04.458550 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1659 10:02:04.462048 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1660 10:02:04.465153 == TX Byte 1 ==
1661 10:02:04.468363 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1662 10:02:04.472228 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1663 10:02:04.472312
1664 10:02:04.475103 [DATLAT]
1665 10:02:04.475187 Freq=800, CH1 RK0
1666 10:02:04.475271
1667 10:02:04.478378 DATLAT Default: 0xa
1668 10:02:04.478461 0, 0xFFFF, sum = 0
1669 10:02:04.481790 1, 0xFFFF, sum = 0
1670 10:02:04.481875 2, 0xFFFF, sum = 0
1671 10:02:04.484782 3, 0xFFFF, sum = 0
1672 10:02:04.484867 4, 0xFFFF, sum = 0
1673 10:02:04.488622 5, 0xFFFF, sum = 0
1674 10:02:04.488707 6, 0xFFFF, sum = 0
1675 10:02:04.491602 7, 0xFFFF, sum = 0
1676 10:02:04.491687 8, 0xFFFF, sum = 0
1677 10:02:04.495131 9, 0x0, sum = 1
1678 10:02:04.495216 10, 0x0, sum = 2
1679 10:02:04.498206 11, 0x0, sum = 3
1680 10:02:04.498291 12, 0x0, sum = 4
1681 10:02:04.501396 best_step = 10
1682 10:02:04.501479
1683 10:02:04.501563 ==
1684 10:02:04.505446 Dram Type= 6, Freq= 0, CH_1, rank 0
1685 10:02:04.508166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1686 10:02:04.508250 ==
1687 10:02:04.511987 RX Vref Scan: 1
1688 10:02:04.512126
1689 10:02:04.512209 Set Vref Range= 32 -> 127
1690 10:02:04.512289
1691 10:02:04.515118 RX Vref 32 -> 127, step: 1
1692 10:02:04.515202
1693 10:02:04.518030 RX Delay -95 -> 252, step: 8
1694 10:02:04.518113
1695 10:02:04.521795 Set Vref, RX VrefLevel [Byte0]: 32
1696 10:02:04.524640 [Byte1]: 32
1697 10:02:04.524723
1698 10:02:04.527988 Set Vref, RX VrefLevel [Byte0]: 33
1699 10:02:04.531489 [Byte1]: 33
1700 10:02:04.535511
1701 10:02:04.535604 Set Vref, RX VrefLevel [Byte0]: 34
1702 10:02:04.538403 [Byte1]: 34
1703 10:02:04.542676
1704 10:02:04.542759 Set Vref, RX VrefLevel [Byte0]: 35
1705 10:02:04.545617 [Byte1]: 35
1706 10:02:04.550246
1707 10:02:04.550329 Set Vref, RX VrefLevel [Byte0]: 36
1708 10:02:04.553736 [Byte1]: 36
1709 10:02:04.559094
1710 10:02:04.559178 Set Vref, RX VrefLevel [Byte0]: 37
1711 10:02:04.561112 [Byte1]: 37
1712 10:02:04.565200
1713 10:02:04.565284 Set Vref, RX VrefLevel [Byte0]: 38
1714 10:02:04.569068 [Byte1]: 38
1715 10:02:04.573126
1716 10:02:04.573209 Set Vref, RX VrefLevel [Byte0]: 39
1717 10:02:04.576620 [Byte1]: 39
1718 10:02:04.580706
1719 10:02:04.580788 Set Vref, RX VrefLevel [Byte0]: 40
1720 10:02:04.584356 [Byte1]: 40
1721 10:02:04.588411
1722 10:02:04.588494 Set Vref, RX VrefLevel [Byte0]: 41
1723 10:02:04.591564 [Byte1]: 41
1724 10:02:04.595611
1725 10:02:04.595718 Set Vref, RX VrefLevel [Byte0]: 42
1726 10:02:04.599538 [Byte1]: 42
1727 10:02:04.603310
1728 10:02:04.603393 Set Vref, RX VrefLevel [Byte0]: 43
1729 10:02:04.606792 [Byte1]: 43
1730 10:02:04.610999
1731 10:02:04.611083 Set Vref, RX VrefLevel [Byte0]: 44
1732 10:02:04.614412 [Byte1]: 44
1733 10:02:04.618479
1734 10:02:04.618563 Set Vref, RX VrefLevel [Byte0]: 45
1735 10:02:04.621904 [Byte1]: 45
1736 10:02:04.626371
1737 10:02:04.626455 Set Vref, RX VrefLevel [Byte0]: 46
1738 10:02:04.632555 [Byte1]: 46
1739 10:02:04.632640
1740 10:02:04.635706 Set Vref, RX VrefLevel [Byte0]: 47
1741 10:02:04.639145 [Byte1]: 47
1742 10:02:04.639229
1743 10:02:04.642545 Set Vref, RX VrefLevel [Byte0]: 48
1744 10:02:04.645933 [Byte1]: 48
1745 10:02:04.646017
1746 10:02:04.649473 Set Vref, RX VrefLevel [Byte0]: 49
1747 10:02:04.652580 [Byte1]: 49
1748 10:02:04.656822
1749 10:02:04.656905 Set Vref, RX VrefLevel [Byte0]: 50
1750 10:02:04.659661 [Byte1]: 50
1751 10:02:04.663944
1752 10:02:04.664050 Set Vref, RX VrefLevel [Byte0]: 51
1753 10:02:04.667295 [Byte1]: 51
1754 10:02:04.672266
1755 10:02:04.672348 Set Vref, RX VrefLevel [Byte0]: 52
1756 10:02:04.675026 [Byte1]: 52
1757 10:02:04.679635
1758 10:02:04.679716 Set Vref, RX VrefLevel [Byte0]: 53
1759 10:02:04.682497 [Byte1]: 53
1760 10:02:04.687157
1761 10:02:04.687269 Set Vref, RX VrefLevel [Byte0]: 54
1762 10:02:04.690364 [Byte1]: 54
1763 10:02:04.694952
1764 10:02:04.695039 Set Vref, RX VrefLevel [Byte0]: 55
1765 10:02:04.697864 [Byte1]: 55
1766 10:02:04.701859
1767 10:02:04.701940 Set Vref, RX VrefLevel [Byte0]: 56
1768 10:02:04.705360 [Byte1]: 56
1769 10:02:04.709597
1770 10:02:04.709678 Set Vref, RX VrefLevel [Byte0]: 57
1771 10:02:04.712880 [Byte1]: 57
1772 10:02:04.717156
1773 10:02:04.717237 Set Vref, RX VrefLevel [Byte0]: 58
1774 10:02:04.720436 [Byte1]: 58
1775 10:02:04.725090
1776 10:02:04.725171 Set Vref, RX VrefLevel [Byte0]: 59
1777 10:02:04.728213 [Byte1]: 59
1778 10:02:04.732849
1779 10:02:04.732930 Set Vref, RX VrefLevel [Byte0]: 60
1780 10:02:04.735920 [Byte1]: 60
1781 10:02:04.739984
1782 10:02:04.740102 Set Vref, RX VrefLevel [Byte0]: 61
1783 10:02:04.743394 [Byte1]: 61
1784 10:02:04.747637
1785 10:02:04.747744 Set Vref, RX VrefLevel [Byte0]: 62
1786 10:02:04.751376 [Byte1]: 62
1787 10:02:04.755304
1788 10:02:04.755385 Set Vref, RX VrefLevel [Byte0]: 63
1789 10:02:04.758595 [Byte1]: 63
1790 10:02:04.762711
1791 10:02:04.762792 Set Vref, RX VrefLevel [Byte0]: 64
1792 10:02:04.766687 [Byte1]: 64
1793 10:02:04.770726
1794 10:02:04.770807 Set Vref, RX VrefLevel [Byte0]: 65
1795 10:02:04.773680 [Byte1]: 65
1796 10:02:04.778282
1797 10:02:04.778363 Set Vref, RX VrefLevel [Byte0]: 66
1798 10:02:04.781472 [Byte1]: 66
1799 10:02:04.785887
1800 10:02:04.785968 Set Vref, RX VrefLevel [Byte0]: 67
1801 10:02:04.788708 [Byte1]: 67
1802 10:02:04.793119
1803 10:02:04.793200 Set Vref, RX VrefLevel [Byte0]: 68
1804 10:02:04.796490 [Byte1]: 68
1805 10:02:04.800826
1806 10:02:04.800914 Set Vref, RX VrefLevel [Byte0]: 69
1807 10:02:04.803962 [Byte1]: 69
1808 10:02:04.808242
1809 10:02:04.808324 Set Vref, RX VrefLevel [Byte0]: 70
1810 10:02:04.811730 [Byte1]: 70
1811 10:02:04.816370
1812 10:02:04.816451 Set Vref, RX VrefLevel [Byte0]: 71
1813 10:02:04.819530 [Byte1]: 71
1814 10:02:04.823872
1815 10:02:04.823982 Set Vref, RX VrefLevel [Byte0]: 72
1816 10:02:04.826808 [Byte1]: 72
1817 10:02:04.831276
1818 10:02:04.831358 Set Vref, RX VrefLevel [Byte0]: 73
1819 10:02:04.834357 [Byte1]: 73
1820 10:02:04.838724
1821 10:02:04.838805 Set Vref, RX VrefLevel [Byte0]: 74
1822 10:02:04.841837 [Byte1]: 74
1823 10:02:04.846403
1824 10:02:04.846488 Final RX Vref Byte 0 = 55 to rank0
1825 10:02:04.849738 Final RX Vref Byte 1 = 56 to rank0
1826 10:02:04.853202 Final RX Vref Byte 0 = 55 to rank1
1827 10:02:04.856013 Final RX Vref Byte 1 = 56 to rank1==
1828 10:02:04.859653 Dram Type= 6, Freq= 0, CH_1, rank 0
1829 10:02:04.866471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1830 10:02:04.866553 ==
1831 10:02:04.866618 DQS Delay:
1832 10:02:04.869499 DQS0 = 0, DQS1 = 0
1833 10:02:04.869580 DQM Delay:
1834 10:02:04.869649 DQM0 = 85, DQM1 = 79
1835 10:02:04.872920 DQ Delay:
1836 10:02:04.876538 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1837 10:02:04.879929 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1838 10:02:04.882910 DQ8 =64, DQ9 =72, DQ10 =76, DQ11 =72
1839 10:02:04.886038 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =84
1840 10:02:04.886121
1841 10:02:04.886185
1842 10:02:04.893167 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c2f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1843 10:02:04.896275 CH1 RK0: MR19=606, MR18=1C2F
1844 10:02:04.902331 CH1_RK0: MR19=0x606, MR18=0x1C2F, DQSOSC=397, MR23=63, INC=93, DEC=62
1845 10:02:04.902413
1846 10:02:04.905990 ----->DramcWriteLeveling(PI) begin...
1847 10:02:04.906074 ==
1848 10:02:04.909093 Dram Type= 6, Freq= 0, CH_1, rank 1
1849 10:02:04.912138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1850 10:02:04.912221 ==
1851 10:02:04.915478 Write leveling (Byte 0): 26 => 26
1852 10:02:04.919331 Write leveling (Byte 1): 31 => 31
1853 10:02:04.922252 DramcWriteLeveling(PI) end<-----
1854 10:02:04.922334
1855 10:02:04.922398 ==
1856 10:02:04.925573 Dram Type= 6, Freq= 0, CH_1, rank 1
1857 10:02:04.929025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1858 10:02:04.929108 ==
1859 10:02:04.932260 [Gating] SW mode calibration
1860 10:02:04.938733 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1861 10:02:04.945863 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1862 10:02:04.949210 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1863 10:02:04.955983 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1864 10:02:04.958825 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1865 10:02:04.962409 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 10:02:04.968765 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 10:02:04.972457 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 10:02:04.975730 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 10:02:04.982708 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 10:02:04.985833 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 10:02:04.988808 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 10:02:04.995299 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 10:02:04.999112 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 10:02:05.002446 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 10:02:05.005778 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 10:02:05.012602 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 10:02:05.015430 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 10:02:05.018776 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1879 10:02:05.025278 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1880 10:02:05.028489 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 10:02:05.031673 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 10:02:05.038797 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 10:02:05.041576 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 10:02:05.045343 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 10:02:05.052094 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 10:02:05.055422 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 10:02:05.058802 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1888 10:02:05.064932 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1889 10:02:05.068270 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 10:02:05.071482 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 10:02:05.078111 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 10:02:05.081805 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 10:02:05.085074 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 10:02:05.092164 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1895 10:02:05.095334 0 10 4 | B1->B0 | 3333 2626 | 1 0 | (1 1) (1 0)
1896 10:02:05.098423 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1897 10:02:05.104759 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 10:02:05.108001 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 10:02:05.111725 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 10:02:05.117896 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 10:02:05.121782 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 10:02:05.124733 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 10:02:05.131808 0 11 4 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
1904 10:02:05.134767 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 10:02:05.138029 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 10:02:05.144591 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 10:02:05.148309 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 10:02:05.151058 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 10:02:05.154737 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 10:02:05.161414 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1911 10:02:05.164766 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1912 10:02:05.167963 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 10:02:05.175403 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 10:02:05.178649 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 10:02:05.181623 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 10:02:05.188001 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 10:02:05.191457 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 10:02:05.194606 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 10:02:05.201178 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 10:02:05.204399 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 10:02:05.208018 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 10:02:05.214825 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 10:02:05.217853 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 10:02:05.221181 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 10:02:05.227842 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 10:02:05.231143 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1927 10:02:05.234808 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1928 10:02:05.237907 Total UI for P1: 0, mck2ui 16
1929 10:02:05.240883 best dqsien dly found for B0: ( 0, 14, 0)
1930 10:02:05.247693 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1931 10:02:05.251015 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 10:02:05.254553 Total UI for P1: 0, mck2ui 16
1933 10:02:05.257497 best dqsien dly found for B1: ( 0, 14, 6)
1934 10:02:05.261058 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1935 10:02:05.264486 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1936 10:02:05.264557
1937 10:02:05.267501 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1938 10:02:05.270774 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1939 10:02:05.274493 [Gating] SW calibration Done
1940 10:02:05.274574 ==
1941 10:02:05.277608 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 10:02:05.281626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 10:02:05.281693 ==
1944 10:02:05.284119 RX Vref Scan: 0
1945 10:02:05.284184
1946 10:02:05.287951 RX Vref 0 -> 0, step: 1
1947 10:02:05.288020
1948 10:02:05.288112 RX Delay -130 -> 252, step: 16
1949 10:02:05.294296 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1950 10:02:05.297385 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1951 10:02:05.300898 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1952 10:02:05.304508 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1953 10:02:05.310777 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1954 10:02:05.314065 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1955 10:02:05.317748 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1956 10:02:05.320718 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1957 10:02:05.324557 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1958 10:02:05.327249 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1959 10:02:05.334823 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1960 10:02:05.337251 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1961 10:02:05.340161 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1962 10:02:05.343457 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1963 10:02:05.350456 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1964 10:02:05.353672 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1965 10:02:05.353742 ==
1966 10:02:05.357135 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 10:02:05.360416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 10:02:05.360520 ==
1969 10:02:05.363623 DQS Delay:
1970 10:02:05.363693 DQS0 = 0, DQS1 = 0
1971 10:02:05.363753 DQM Delay:
1972 10:02:05.367137 DQM0 = 81, DQM1 = 80
1973 10:02:05.367208 DQ Delay:
1974 10:02:05.370723 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1975 10:02:05.373976 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1976 10:02:05.377006 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1977 10:02:05.379959 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1978 10:02:05.380088
1979 10:02:05.380148
1980 10:02:05.380211 ==
1981 10:02:05.383482 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 10:02:05.390082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 10:02:05.390158 ==
1984 10:02:05.390219
1985 10:02:05.390274
1986 10:02:05.390328 TX Vref Scan disable
1987 10:02:05.393944 == TX Byte 0 ==
1988 10:02:05.396974 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1989 10:02:05.403215 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1990 10:02:05.403287 == TX Byte 1 ==
1991 10:02:05.407003 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1992 10:02:05.413629 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1993 10:02:05.413704 ==
1994 10:02:05.416905 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 10:02:05.420215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 10:02:05.420284 ==
1997 10:02:05.432992 TX Vref=22, minBit 0, minWin=27, winSum=448
1998 10:02:05.436524 TX Vref=24, minBit 0, minWin=27, winSum=446
1999 10:02:05.439441 TX Vref=26, minBit 1, minWin=27, winSum=451
2000 10:02:05.442958 TX Vref=28, minBit 0, minWin=28, winSum=456
2001 10:02:05.446518 TX Vref=30, minBit 1, minWin=28, winSum=455
2002 10:02:05.452928 TX Vref=32, minBit 2, minWin=27, winSum=454
2003 10:02:05.456165 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 28
2004 10:02:05.456235
2005 10:02:05.459747 Final TX Range 1 Vref 28
2006 10:02:05.459813
2007 10:02:05.459872 ==
2008 10:02:05.463356 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 10:02:05.466108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 10:02:05.466178 ==
2011 10:02:05.469808
2012 10:02:05.469877
2013 10:02:05.469941 TX Vref Scan disable
2014 10:02:05.473174 == TX Byte 0 ==
2015 10:02:05.476530 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2016 10:02:05.483260 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2017 10:02:05.483342 == TX Byte 1 ==
2018 10:02:05.486455 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2019 10:02:05.493239 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2020 10:02:05.493316
2021 10:02:05.493377 [DATLAT]
2022 10:02:05.493434 Freq=800, CH1 RK1
2023 10:02:05.493488
2024 10:02:05.496120 DATLAT Default: 0xa
2025 10:02:05.496185 0, 0xFFFF, sum = 0
2026 10:02:05.499381 1, 0xFFFF, sum = 0
2027 10:02:05.502810 2, 0xFFFF, sum = 0
2028 10:02:05.502880 3, 0xFFFF, sum = 0
2029 10:02:05.506001 4, 0xFFFF, sum = 0
2030 10:02:05.506070 5, 0xFFFF, sum = 0
2031 10:02:05.509473 6, 0xFFFF, sum = 0
2032 10:02:05.509543 7, 0xFFFF, sum = 0
2033 10:02:05.513002 8, 0xFFFF, sum = 0
2034 10:02:05.513084 9, 0x0, sum = 1
2035 10:02:05.515804 10, 0x0, sum = 2
2036 10:02:05.515875 11, 0x0, sum = 3
2037 10:02:05.519335 12, 0x0, sum = 4
2038 10:02:05.519414 best_step = 10
2039 10:02:05.519474
2040 10:02:05.519531 ==
2041 10:02:05.522706 Dram Type= 6, Freq= 0, CH_1, rank 1
2042 10:02:05.525905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2043 10:02:05.525980 ==
2044 10:02:05.529054 RX Vref Scan: 0
2045 10:02:05.529130
2046 10:02:05.532235 RX Vref 0 -> 0, step: 1
2047 10:02:05.532343
2048 10:02:05.532436 RX Delay -95 -> 252, step: 8
2049 10:02:05.540024 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2050 10:02:05.543221 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2051 10:02:05.546484 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2052 10:02:05.549558 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2053 10:02:05.553021 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
2054 10:02:05.559560 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2055 10:02:05.562967 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2056 10:02:05.566390 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2057 10:02:05.569619 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2058 10:02:05.572748 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2059 10:02:05.579345 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2060 10:02:05.583244 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2061 10:02:05.586320 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2062 10:02:05.589882 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2063 10:02:05.596449 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2064 10:02:05.599351 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2065 10:02:05.599431 ==
2066 10:02:05.602941 Dram Type= 6, Freq= 0, CH_1, rank 1
2067 10:02:05.606085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2068 10:02:05.606190 ==
2069 10:02:05.609580 DQS Delay:
2070 10:02:05.609660 DQS0 = 0, DQS1 = 0
2071 10:02:05.609723 DQM Delay:
2072 10:02:05.612476 DQM0 = 86, DQM1 = 81
2073 10:02:05.612556 DQ Delay:
2074 10:02:05.616732 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2075 10:02:05.619136 DQ4 =88, DQ5 =96, DQ6 =92, DQ7 =84
2076 10:02:05.622716 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =72
2077 10:02:05.625580 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2078 10:02:05.625660
2079 10:02:05.625722
2080 10:02:05.635936 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 403 ps
2081 10:02:05.636020 CH1 RK1: MR19=606, MR18=1B37
2082 10:02:05.642245 CH1_RK1: MR19=0x606, MR18=0x1B37, DQSOSC=395, MR23=63, INC=94, DEC=63
2083 10:02:05.645845 [RxdqsGatingPostProcess] freq 800
2084 10:02:05.652366 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2085 10:02:05.655602 Pre-setting of DQS Precalculation
2086 10:02:05.658726 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2087 10:02:05.668753 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2088 10:02:05.675566 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2089 10:02:05.675646
2090 10:02:05.675710
2091 10:02:05.679128 [Calibration Summary] 1600 Mbps
2092 10:02:05.679208 CH 0, Rank 0
2093 10:02:05.682450 SW Impedance : PASS
2094 10:02:05.682531 DUTY Scan : NO K
2095 10:02:05.685536 ZQ Calibration : PASS
2096 10:02:05.688791 Jitter Meter : NO K
2097 10:02:05.688872 CBT Training : PASS
2098 10:02:05.691972 Write leveling : PASS
2099 10:02:05.695335 RX DQS gating : PASS
2100 10:02:05.695415 RX DQ/DQS(RDDQC) : PASS
2101 10:02:05.698483 TX DQ/DQS : PASS
2102 10:02:05.698565 RX DATLAT : PASS
2103 10:02:05.702301 RX DQ/DQS(Engine): PASS
2104 10:02:05.705647 TX OE : NO K
2105 10:02:05.705729 All Pass.
2106 10:02:05.705792
2107 10:02:05.705850 CH 0, Rank 1
2108 10:02:05.708565 SW Impedance : PASS
2109 10:02:05.712060 DUTY Scan : NO K
2110 10:02:05.712155 ZQ Calibration : PASS
2111 10:02:05.715581 Jitter Meter : NO K
2112 10:02:05.718621 CBT Training : PASS
2113 10:02:05.718703 Write leveling : PASS
2114 10:02:05.722107 RX DQS gating : PASS
2115 10:02:05.725155 RX DQ/DQS(RDDQC) : PASS
2116 10:02:05.725235 TX DQ/DQS : PASS
2117 10:02:05.728475 RX DATLAT : PASS
2118 10:02:05.732192 RX DQ/DQS(Engine): PASS
2119 10:02:05.732273 TX OE : NO K
2120 10:02:05.732337 All Pass.
2121 10:02:05.735457
2122 10:02:05.735537 CH 1, Rank 0
2123 10:02:05.738934 SW Impedance : PASS
2124 10:02:05.739014 DUTY Scan : NO K
2125 10:02:05.742210 ZQ Calibration : PASS
2126 10:02:05.745628 Jitter Meter : NO K
2127 10:02:05.745734 CBT Training : PASS
2128 10:02:05.748725 Write leveling : PASS
2129 10:02:05.748814 RX DQS gating : PASS
2130 10:02:05.752289 RX DQ/DQS(RDDQC) : PASS
2131 10:02:05.755203 TX DQ/DQS : PASS
2132 10:02:05.755278 RX DATLAT : PASS
2133 10:02:05.758956 RX DQ/DQS(Engine): PASS
2134 10:02:05.761976 TX OE : NO K
2135 10:02:05.762047 All Pass.
2136 10:02:05.762118
2137 10:02:05.762178 CH 1, Rank 1
2138 10:02:05.764907 SW Impedance : PASS
2139 10:02:05.768502 DUTY Scan : NO K
2140 10:02:05.768597 ZQ Calibration : PASS
2141 10:02:05.771789 Jitter Meter : NO K
2142 10:02:05.775056 CBT Training : PASS
2143 10:02:05.775125 Write leveling : PASS
2144 10:02:05.778150 RX DQS gating : PASS
2145 10:02:05.781531 RX DQ/DQS(RDDQC) : PASS
2146 10:02:05.781626 TX DQ/DQS : PASS
2147 10:02:05.785033 RX DATLAT : PASS
2148 10:02:05.788012 RX DQ/DQS(Engine): PASS
2149 10:02:05.788099 TX OE : NO K
2150 10:02:05.791645 All Pass.
2151 10:02:05.791713
2152 10:02:05.791786 DramC Write-DBI off
2153 10:02:05.794550 PER_BANK_REFRESH: Hybrid Mode
2154 10:02:05.794626 TX_TRACKING: ON
2155 10:02:05.798142 [GetDramInforAfterCalByMRR] Vendor 6.
2156 10:02:05.804586 [GetDramInforAfterCalByMRR] Revision 606.
2157 10:02:05.807987 [GetDramInforAfterCalByMRR] Revision 2 0.
2158 10:02:05.808093 MR0 0x3b3b
2159 10:02:05.808182 MR8 0x5151
2160 10:02:05.811422 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2161 10:02:05.811516
2162 10:02:05.814458 MR0 0x3b3b
2163 10:02:05.814529 MR8 0x5151
2164 10:02:05.818031 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2165 10:02:05.818100
2166 10:02:05.828588 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2167 10:02:05.832281 [FAST_K] Save calibration result to emmc
2168 10:02:05.834656 [FAST_K] Save calibration result to emmc
2169 10:02:05.838166 dram_init: config_dvfs: 1
2170 10:02:05.841304 dramc_set_vcore_voltage set vcore to 662500
2171 10:02:05.844575 Read voltage for 1200, 2
2172 10:02:05.844648 Vio18 = 0
2173 10:02:05.844710 Vcore = 662500
2174 10:02:05.847754 Vdram = 0
2175 10:02:05.847847 Vddq = 0
2176 10:02:05.847942 Vmddr = 0
2177 10:02:05.854504 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2178 10:02:05.857884 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2179 10:02:05.861107 MEM_TYPE=3, freq_sel=15
2180 10:02:05.864381 sv_algorithm_assistance_LP4_1600
2181 10:02:05.867787 ============ PULL DRAM RESETB DOWN ============
2182 10:02:05.871294 ========== PULL DRAM RESETB DOWN end =========
2183 10:02:05.877682 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2184 10:02:05.880985 ===================================
2185 10:02:05.884105 LPDDR4 DRAM CONFIGURATION
2186 10:02:05.884188 ===================================
2187 10:02:05.887273 EX_ROW_EN[0] = 0x0
2188 10:02:05.891121 EX_ROW_EN[1] = 0x0
2189 10:02:05.891191 LP4Y_EN = 0x0
2190 10:02:05.894137 WORK_FSP = 0x0
2191 10:02:05.894206 WL = 0x4
2192 10:02:05.897665 RL = 0x4
2193 10:02:05.897759 BL = 0x2
2194 10:02:05.900644 RPST = 0x0
2195 10:02:05.900714 RD_PRE = 0x0
2196 10:02:05.904691 WR_PRE = 0x1
2197 10:02:05.904774 WR_PST = 0x0
2198 10:02:05.907492 DBI_WR = 0x0
2199 10:02:05.907594 DBI_RD = 0x0
2200 10:02:05.910512 OTF = 0x1
2201 10:02:05.914038 ===================================
2202 10:02:05.917217 ===================================
2203 10:02:05.917314 ANA top config
2204 10:02:05.920610 ===================================
2205 10:02:05.924219 DLL_ASYNC_EN = 0
2206 10:02:05.927185 ALL_SLAVE_EN = 0
2207 10:02:05.930562 NEW_RANK_MODE = 1
2208 10:02:05.930660 DLL_IDLE_MODE = 1
2209 10:02:05.934032 LP45_APHY_COMB_EN = 1
2210 10:02:05.937085 TX_ODT_DIS = 1
2211 10:02:05.940290 NEW_8X_MODE = 1
2212 10:02:05.944177 ===================================
2213 10:02:05.947312 ===================================
2214 10:02:05.950678 data_rate = 2400
2215 10:02:05.950778 CKR = 1
2216 10:02:05.954098 DQ_P2S_RATIO = 8
2217 10:02:05.957075 ===================================
2218 10:02:05.960975 CA_P2S_RATIO = 8
2219 10:02:05.963915 DQ_CA_OPEN = 0
2220 10:02:05.967600 DQ_SEMI_OPEN = 0
2221 10:02:05.970386 CA_SEMI_OPEN = 0
2222 10:02:05.970464 CA_FULL_RATE = 0
2223 10:02:05.973972 DQ_CKDIV4_EN = 0
2224 10:02:05.976975 CA_CKDIV4_EN = 0
2225 10:02:05.980484 CA_PREDIV_EN = 0
2226 10:02:05.983781 PH8_DLY = 17
2227 10:02:05.987480 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2228 10:02:05.987562 DQ_AAMCK_DIV = 4
2229 10:02:05.990749 CA_AAMCK_DIV = 4
2230 10:02:05.993852 CA_ADMCK_DIV = 4
2231 10:02:05.996930 DQ_TRACK_CA_EN = 0
2232 10:02:06.000059 CA_PICK = 1200
2233 10:02:06.003515 CA_MCKIO = 1200
2234 10:02:06.007279 MCKIO_SEMI = 0
2235 10:02:06.010057 PLL_FREQ = 2366
2236 10:02:06.010139 DQ_UI_PI_RATIO = 32
2237 10:02:06.013236 CA_UI_PI_RATIO = 0
2238 10:02:06.016515 ===================================
2239 10:02:06.020135 ===================================
2240 10:02:06.023236 memory_type:LPDDR4
2241 10:02:06.026675 GP_NUM : 10
2242 10:02:06.026757 SRAM_EN : 1
2243 10:02:06.030296 MD32_EN : 0
2244 10:02:06.033403 ===================================
2245 10:02:06.033485 [ANA_INIT] >>>>>>>>>>>>>>
2246 10:02:06.036802 <<<<<< [CONFIGURE PHASE]: ANA_TX
2247 10:02:06.039869 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2248 10:02:06.043323 ===================================
2249 10:02:06.046924 data_rate = 2400,PCW = 0X5b00
2250 10:02:06.050307 ===================================
2251 10:02:06.053414 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2252 10:02:06.059958 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2253 10:02:06.066652 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2254 10:02:06.070070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2255 10:02:06.073115 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2256 10:02:06.076694 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2257 10:02:06.080226 [ANA_INIT] flow start
2258 10:02:06.080307 [ANA_INIT] PLL >>>>>>>>
2259 10:02:06.083244 [ANA_INIT] PLL <<<<<<<<
2260 10:02:06.086650 [ANA_INIT] MIDPI >>>>>>>>
2261 10:02:06.086731 [ANA_INIT] MIDPI <<<<<<<<
2262 10:02:06.090076 [ANA_INIT] DLL >>>>>>>>
2263 10:02:06.093118 [ANA_INIT] DLL <<<<<<<<
2264 10:02:06.093200 [ANA_INIT] flow end
2265 10:02:06.099832 ============ LP4 DIFF to SE enter ============
2266 10:02:06.102978 ============ LP4 DIFF to SE exit ============
2267 10:02:06.106497 [ANA_INIT] <<<<<<<<<<<<<
2268 10:02:06.109901 [Flow] Enable top DCM control >>>>>
2269 10:02:06.112868 [Flow] Enable top DCM control <<<<<
2270 10:02:06.112950 Enable DLL master slave shuffle
2271 10:02:06.119974 ==============================================================
2272 10:02:06.123193 Gating Mode config
2273 10:02:06.126220 ==============================================================
2274 10:02:06.129346 Config description:
2275 10:02:06.139663 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2276 10:02:06.146772 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2277 10:02:06.149812 SELPH_MODE 0: By rank 1: By Phase
2278 10:02:06.156462 ==============================================================
2279 10:02:06.159312 GAT_TRACK_EN = 1
2280 10:02:06.162769 RX_GATING_MODE = 2
2281 10:02:06.166438 RX_GATING_TRACK_MODE = 2
2282 10:02:06.169144 SELPH_MODE = 1
2283 10:02:06.169228 PICG_EARLY_EN = 1
2284 10:02:06.172686 VALID_LAT_VALUE = 1
2285 10:02:06.179181 ==============================================================
2286 10:02:06.182524 Enter into Gating configuration >>>>
2287 10:02:06.186037 Exit from Gating configuration <<<<
2288 10:02:06.189274 Enter into DVFS_PRE_config >>>>>
2289 10:02:06.199089 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2290 10:02:06.202337 Exit from DVFS_PRE_config <<<<<
2291 10:02:06.205718 Enter into PICG configuration >>>>
2292 10:02:06.209269 Exit from PICG configuration <<<<
2293 10:02:06.212702 [RX_INPUT] configuration >>>>>
2294 10:02:06.215575 [RX_INPUT] configuration <<<<<
2295 10:02:06.219031 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2296 10:02:06.225969 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2297 10:02:06.232289 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2298 10:02:06.239061 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2299 10:02:06.245389 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2300 10:02:06.252519 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2301 10:02:06.255588 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2302 10:02:06.258815 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2303 10:02:06.261834 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2304 10:02:06.265318 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2305 10:02:06.272308 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2306 10:02:06.275256 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2307 10:02:06.278400 ===================================
2308 10:02:06.281813 LPDDR4 DRAM CONFIGURATION
2309 10:02:06.285172 ===================================
2310 10:02:06.285240 EX_ROW_EN[0] = 0x0
2311 10:02:06.288634 EX_ROW_EN[1] = 0x0
2312 10:02:06.288699 LP4Y_EN = 0x0
2313 10:02:06.292034 WORK_FSP = 0x0
2314 10:02:06.292099 WL = 0x4
2315 10:02:06.295253 RL = 0x4
2316 10:02:06.295319 BL = 0x2
2317 10:02:06.298277 RPST = 0x0
2318 10:02:06.301975 RD_PRE = 0x0
2319 10:02:06.302039 WR_PRE = 0x1
2320 10:02:06.305045 WR_PST = 0x0
2321 10:02:06.305109 DBI_WR = 0x0
2322 10:02:06.308659 DBI_RD = 0x0
2323 10:02:06.308725 OTF = 0x1
2324 10:02:06.312397 ===================================
2325 10:02:06.315078 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2326 10:02:06.321661 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2327 10:02:06.325004 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2328 10:02:06.328744 ===================================
2329 10:02:06.331979 LPDDR4 DRAM CONFIGURATION
2330 10:02:06.334945 ===================================
2331 10:02:06.335023 EX_ROW_EN[0] = 0x10
2332 10:02:06.338537 EX_ROW_EN[1] = 0x0
2333 10:02:06.338608 LP4Y_EN = 0x0
2334 10:02:06.341916 WORK_FSP = 0x0
2335 10:02:06.341988 WL = 0x4
2336 10:02:06.345199 RL = 0x4
2337 10:02:06.345273 BL = 0x2
2338 10:02:06.348244 RPST = 0x0
2339 10:02:06.348310 RD_PRE = 0x0
2340 10:02:06.351538 WR_PRE = 0x1
2341 10:02:06.354644 WR_PST = 0x0
2342 10:02:06.354714 DBI_WR = 0x0
2343 10:02:06.358976 DBI_RD = 0x0
2344 10:02:06.359043 OTF = 0x1
2345 10:02:06.361601 ===================================
2346 10:02:06.367977 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2347 10:02:06.368088 ==
2348 10:02:06.371473 Dram Type= 6, Freq= 0, CH_0, rank 0
2349 10:02:06.374750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2350 10:02:06.374821 ==
2351 10:02:06.377931 [Duty_Offset_Calibration]
2352 10:02:06.378002 B0:2 B1:0 CA:4
2353 10:02:06.381496
2354 10:02:06.384627 [DutyScan_Calibration_Flow] k_type=0
2355 10:02:06.391906
2356 10:02:06.391973 ==CLK 0==
2357 10:02:06.395309 Final CLK duty delay cell = -4
2358 10:02:06.398411 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2359 10:02:06.401849 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2360 10:02:06.405465 [-4] AVG Duty = 4953%(X100)
2361 10:02:06.405528
2362 10:02:06.408302 CH0 CLK Duty spec in!! Max-Min= 218%
2363 10:02:06.411464 [DutyScan_Calibration_Flow] ====Done====
2364 10:02:06.411529
2365 10:02:06.414893 [DutyScan_Calibration_Flow] k_type=1
2366 10:02:06.431272
2367 10:02:06.431341 ==DQS 0 ==
2368 10:02:06.434463 Final DQS duty delay cell = 0
2369 10:02:06.437852 [0] MAX Duty = 5156%(X100), DQS PI = 6
2370 10:02:06.441381 [0] MIN Duty = 5093%(X100), DQS PI = 0
2371 10:02:06.441457 [0] AVG Duty = 5124%(X100)
2372 10:02:06.444216
2373 10:02:06.444289 ==DQS 1 ==
2374 10:02:06.448013 Final DQS duty delay cell = 0
2375 10:02:06.451013 [0] MAX Duty = 5125%(X100), DQS PI = 4
2376 10:02:06.454270 [0] MIN Duty = 5000%(X100), DQS PI = 0
2377 10:02:06.454337 [0] AVG Duty = 5062%(X100)
2378 10:02:06.454399
2379 10:02:06.458093 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2380 10:02:06.461242
2381 10:02:06.464449 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2382 10:02:06.467746 [DutyScan_Calibration_Flow] ====Done====
2383 10:02:06.467815
2384 10:02:06.470997 [DutyScan_Calibration_Flow] k_type=3
2385 10:02:06.487399
2386 10:02:06.487472 ==DQM 0 ==
2387 10:02:06.490578 Final DQM duty delay cell = 0
2388 10:02:06.494258 [0] MAX Duty = 5125%(X100), DQS PI = 20
2389 10:02:06.497521 [0] MIN Duty = 4844%(X100), DQS PI = 54
2390 10:02:06.500563 [0] AVG Duty = 4984%(X100)
2391 10:02:06.500627
2392 10:02:06.500685 ==DQM 1 ==
2393 10:02:06.504347 Final DQM duty delay cell = 0
2394 10:02:06.507235 [0] MAX Duty = 4969%(X100), DQS PI = 2
2395 10:02:06.510474 [0] MIN Duty = 4876%(X100), DQS PI = 26
2396 10:02:06.514044 [0] AVG Duty = 4922%(X100)
2397 10:02:06.514110
2398 10:02:06.517412 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2399 10:02:06.517477
2400 10:02:06.521037 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2401 10:02:06.523629 [DutyScan_Calibration_Flow] ====Done====
2402 10:02:06.523692
2403 10:02:06.526877 [DutyScan_Calibration_Flow] k_type=2
2404 10:02:06.543928
2405 10:02:06.544009 ==DQ 0 ==
2406 10:02:06.547438 Final DQ duty delay cell = 0
2407 10:02:06.550561 [0] MAX Duty = 5125%(X100), DQS PI = 18
2408 10:02:06.553944 [0] MIN Duty = 5000%(X100), DQS PI = 8
2409 10:02:06.554055 [0] AVG Duty = 5062%(X100)
2410 10:02:06.556984
2411 10:02:06.557065 ==DQ 1 ==
2412 10:02:06.560238 Final DQ duty delay cell = 0
2413 10:02:06.563917 [0] MAX Duty = 5156%(X100), DQS PI = 6
2414 10:02:06.567134 [0] MIN Duty = 4938%(X100), DQS PI = 14
2415 10:02:06.567213 [0] AVG Duty = 5047%(X100)
2416 10:02:06.567276
2417 10:02:06.570323 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2418 10:02:06.573943
2419 10:02:06.577045 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2420 10:02:06.580562 [DutyScan_Calibration_Flow] ====Done====
2421 10:02:06.580641 ==
2422 10:02:06.583637 Dram Type= 6, Freq= 0, CH_1, rank 0
2423 10:02:06.586674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2424 10:02:06.586747 ==
2425 10:02:06.590398 [Duty_Offset_Calibration]
2426 10:02:06.590469 B0:0 B1:-1 CA:3
2427 10:02:06.590532
2428 10:02:06.594165 [DutyScan_Calibration_Flow] k_type=0
2429 10:02:06.603113
2430 10:02:06.603178 ==CLK 0==
2431 10:02:06.605983 Final CLK duty delay cell = -4
2432 10:02:06.609405 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2433 10:02:06.612894 [-4] MIN Duty = 4844%(X100), DQS PI = 4
2434 10:02:06.616747 [-4] AVG Duty = 4937%(X100)
2435 10:02:06.616814
2436 10:02:06.619947 CH1 CLK Duty spec in!! Max-Min= 187%
2437 10:02:06.623072 [DutyScan_Calibration_Flow] ====Done====
2438 10:02:06.623137
2439 10:02:06.625998 [DutyScan_Calibration_Flow] k_type=1
2440 10:02:06.642466
2441 10:02:06.642544 ==DQS 0 ==
2442 10:02:06.645753 Final DQS duty delay cell = 0
2443 10:02:06.648945 [0] MAX Duty = 5156%(X100), DQS PI = 50
2444 10:02:06.652437 [0] MIN Duty = 4907%(X100), DQS PI = 6
2445 10:02:06.655961 [0] AVG Duty = 5031%(X100)
2446 10:02:06.656028
2447 10:02:06.656133 ==DQS 1 ==
2448 10:02:06.658915 Final DQS duty delay cell = 0
2449 10:02:06.662185 [0] MAX Duty = 5156%(X100), DQS PI = 0
2450 10:02:06.665372 [0] MIN Duty = 5000%(X100), DQS PI = 58
2451 10:02:06.669250 [0] AVG Duty = 5078%(X100)
2452 10:02:06.669331
2453 10:02:06.672068 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2454 10:02:06.672148
2455 10:02:06.675304 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2456 10:02:06.678705 [DutyScan_Calibration_Flow] ====Done====
2457 10:02:06.678784
2458 10:02:06.681990 [DutyScan_Calibration_Flow] k_type=3
2459 10:02:06.698697
2460 10:02:06.698776 ==DQM 0 ==
2461 10:02:06.702515 Final DQM duty delay cell = 0
2462 10:02:06.705538 [0] MAX Duty = 5031%(X100), DQS PI = 60
2463 10:02:06.708841 [0] MIN Duty = 4813%(X100), DQS PI = 6
2464 10:02:06.708921 [0] AVG Duty = 4922%(X100)
2465 10:02:06.712210
2466 10:02:06.712290 ==DQM 1 ==
2467 10:02:06.715735 Final DQM duty delay cell = 0
2468 10:02:06.718924 [0] MAX Duty = 4969%(X100), DQS PI = 0
2469 10:02:06.722265 [0] MIN Duty = 4844%(X100), DQS PI = 28
2470 10:02:06.722346 [0] AVG Duty = 4906%(X100)
2471 10:02:06.725411
2472 10:02:06.728895 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2473 10:02:06.728976
2474 10:02:06.731884 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2475 10:02:06.735122 [DutyScan_Calibration_Flow] ====Done====
2476 10:02:06.735204
2477 10:02:06.738408 [DutyScan_Calibration_Flow] k_type=2
2478 10:02:06.754540
2479 10:02:06.754621 ==DQ 0 ==
2480 10:02:06.757915 Final DQ duty delay cell = -4
2481 10:02:06.761076 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2482 10:02:06.764183 [-4] MIN Duty = 4876%(X100), DQS PI = 2
2483 10:02:06.767843 [-4] AVG Duty = 4953%(X100)
2484 10:02:06.767923
2485 10:02:06.767987 ==DQ 1 ==
2486 10:02:06.770924 Final DQ duty delay cell = 0
2487 10:02:06.774519 [0] MAX Duty = 5031%(X100), DQS PI = 2
2488 10:02:06.778137 [0] MIN Duty = 4876%(X100), DQS PI = 30
2489 10:02:06.778218 [0] AVG Duty = 4953%(X100)
2490 10:02:06.781377
2491 10:02:06.785202 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2492 10:02:06.785283
2493 10:02:06.788575 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2494 10:02:06.791459 [DutyScan_Calibration_Flow] ====Done====
2495 10:02:06.794543 nWR fixed to 30
2496 10:02:06.794625 [ModeRegInit_LP4] CH0 RK0
2497 10:02:06.798019 [ModeRegInit_LP4] CH0 RK1
2498 10:02:06.800998 [ModeRegInit_LP4] CH1 RK0
2499 10:02:06.804299 [ModeRegInit_LP4] CH1 RK1
2500 10:02:06.804381 match AC timing 7
2501 10:02:06.808069 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2502 10:02:06.814073 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2503 10:02:06.817885 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2504 10:02:06.824787 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2505 10:02:06.827623 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2506 10:02:06.827705 ==
2507 10:02:06.831636 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 10:02:06.834465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 10:02:06.834559 ==
2510 10:02:06.841475 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2511 10:02:06.847505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2512 10:02:06.854782 [CA 0] Center 39 (9~70) winsize 62
2513 10:02:06.858160 [CA 1] Center 39 (9~69) winsize 61
2514 10:02:06.860970 [CA 2] Center 35 (5~66) winsize 62
2515 10:02:06.864302 [CA 3] Center 35 (5~66) winsize 62
2516 10:02:06.867912 [CA 4] Center 33 (3~64) winsize 62
2517 10:02:06.871049 [CA 5] Center 33 (3~64) winsize 62
2518 10:02:06.871130
2519 10:02:06.874651 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2520 10:02:06.874732
2521 10:02:06.877714 [CATrainingPosCal] consider 1 rank data
2522 10:02:06.880841 u2DelayCellTimex100 = 270/100 ps
2523 10:02:06.884211 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2524 10:02:06.891005 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2525 10:02:06.894413 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2526 10:02:06.897561 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2527 10:02:06.900640 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2528 10:02:06.904397 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2529 10:02:06.904503
2530 10:02:06.907587 CA PerBit enable=1, Macro0, CA PI delay=33
2531 10:02:06.907684
2532 10:02:06.910910 [CBTSetCACLKResult] CA Dly = 33
2533 10:02:06.910991 CS Dly: 7 (0~38)
2534 10:02:06.914239 ==
2535 10:02:06.917300 Dram Type= 6, Freq= 0, CH_0, rank 1
2536 10:02:06.921438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2537 10:02:06.921520 ==
2538 10:02:06.927352 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2539 10:02:06.930621 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2540 10:02:06.940478 [CA 0] Center 39 (9~70) winsize 62
2541 10:02:06.943774 [CA 1] Center 39 (9~70) winsize 62
2542 10:02:06.947168 [CA 2] Center 35 (5~66) winsize 62
2543 10:02:06.950242 [CA 3] Center 35 (5~66) winsize 62
2544 10:02:06.953971 [CA 4] Center 34 (4~65) winsize 62
2545 10:02:06.957215 [CA 5] Center 33 (3~64) winsize 62
2546 10:02:06.957296
2547 10:02:06.960013 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2548 10:02:06.960103
2549 10:02:06.963237 [CATrainingPosCal] consider 2 rank data
2550 10:02:06.966497 u2DelayCellTimex100 = 270/100 ps
2551 10:02:06.970108 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2552 10:02:06.976883 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2553 10:02:06.980362 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2554 10:02:06.983162 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2555 10:02:06.986486 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2556 10:02:06.989809 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2557 10:02:06.989890
2558 10:02:06.993540 CA PerBit enable=1, Macro0, CA PI delay=33
2559 10:02:06.993621
2560 10:02:06.996768 [CBTSetCACLKResult] CA Dly = 33
2561 10:02:07.000658 CS Dly: 8 (0~41)
2562 10:02:07.000739
2563 10:02:07.003184 ----->DramcWriteLeveling(PI) begin...
2564 10:02:07.003266 ==
2565 10:02:07.006639 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 10:02:07.009592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 10:02:07.009673 ==
2568 10:02:07.013059 Write leveling (Byte 0): 30 => 30
2569 10:02:07.016208 Write leveling (Byte 1): 29 => 29
2570 10:02:07.019676 DramcWriteLeveling(PI) end<-----
2571 10:02:07.019757
2572 10:02:07.019822 ==
2573 10:02:07.023034 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 10:02:07.026424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 10:02:07.026505 ==
2576 10:02:07.029900 [Gating] SW mode calibration
2577 10:02:07.036367 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2578 10:02:07.043039 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2579 10:02:07.046015 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2580 10:02:07.049370 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2581 10:02:07.056335 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 10:02:07.059481 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 10:02:07.063241 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 10:02:07.069559 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 10:02:07.072585 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
2586 10:02:07.075947 0 15 28 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
2587 10:02:07.082727 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2588 10:02:07.085881 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 10:02:07.089428 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 10:02:07.095975 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 10:02:07.099369 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 10:02:07.103004 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 10:02:07.109661 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2594 10:02:07.112261 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2595 10:02:07.115988 1 1 0 | B1->B0 | 2d2c 4646 | 1 0 | (0 0) (0 0)
2596 10:02:07.122576 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 10:02:07.125650 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 10:02:07.129250 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 10:02:07.135978 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 10:02:07.138948 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 10:02:07.142441 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 10:02:07.145510 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2603 10:02:07.152156 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2604 10:02:07.155720 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 10:02:07.159045 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 10:02:07.165929 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 10:02:07.169097 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 10:02:07.172006 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 10:02:07.178829 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 10:02:07.182655 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 10:02:07.185724 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 10:02:07.192199 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 10:02:07.195344 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 10:02:07.198722 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 10:02:07.206108 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 10:02:07.209332 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 10:02:07.212167 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2618 10:02:07.218618 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2619 10:02:07.221896 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2620 10:02:07.225185 Total UI for P1: 0, mck2ui 16
2621 10:02:07.228816 best dqsien dly found for B0: ( 1, 3, 26)
2622 10:02:07.232202 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 10:02:07.235348 Total UI for P1: 0, mck2ui 16
2624 10:02:07.238727 best dqsien dly found for B1: ( 1, 4, 0)
2625 10:02:07.241869 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2626 10:02:07.244873 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2627 10:02:07.244954
2628 10:02:07.251636 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2629 10:02:07.254701 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2630 10:02:07.254782 [Gating] SW calibration Done
2631 10:02:07.258135 ==
2632 10:02:07.261399 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 10:02:07.265119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 10:02:07.265200 ==
2635 10:02:07.265264 RX Vref Scan: 0
2636 10:02:07.265324
2637 10:02:07.268453 RX Vref 0 -> 0, step: 1
2638 10:02:07.268534
2639 10:02:07.271612 RX Delay -40 -> 252, step: 8
2640 10:02:07.275114 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2641 10:02:07.278258 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2642 10:02:07.284756 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2643 10:02:07.288607 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2644 10:02:07.291775 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2645 10:02:07.294889 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2646 10:02:07.298071 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2647 10:02:07.305011 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2648 10:02:07.308792 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2649 10:02:07.311223 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2650 10:02:07.314441 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2651 10:02:07.317891 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2652 10:02:07.324599 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2653 10:02:07.327883 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2654 10:02:07.331142 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2655 10:02:07.334452 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2656 10:02:07.334533 ==
2657 10:02:07.338035 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 10:02:07.344476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 10:02:07.344557 ==
2660 10:02:07.344638 DQS Delay:
2661 10:02:07.344712 DQS0 = 0, DQS1 = 0
2662 10:02:07.347417 DQM Delay:
2663 10:02:07.347497 DQM0 = 118, DQM1 = 107
2664 10:02:07.350832 DQ Delay:
2665 10:02:07.354434 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2666 10:02:07.357508 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
2667 10:02:07.360876 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2668 10:02:07.364059 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2669 10:02:07.364153
2670 10:02:07.364217
2671 10:02:07.364276 ==
2672 10:02:07.367550 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 10:02:07.370689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 10:02:07.370771 ==
2675 10:02:07.370834
2676 10:02:07.374210
2677 10:02:07.374290 TX Vref Scan disable
2678 10:02:07.377949 == TX Byte 0 ==
2679 10:02:07.381117 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2680 10:02:07.384147 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2681 10:02:07.387396 == TX Byte 1 ==
2682 10:02:07.391036 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2683 10:02:07.394181 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2684 10:02:07.394263 ==
2685 10:02:07.397475 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 10:02:07.403947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 10:02:07.404033 ==
2688 10:02:07.414910 TX Vref=22, minBit 0, minWin=25, winSum=411
2689 10:02:07.417726 TX Vref=24, minBit 1, minWin=25, winSum=417
2690 10:02:07.422289 TX Vref=26, minBit 0, minWin=26, winSum=425
2691 10:02:07.424957 TX Vref=28, minBit 1, minWin=25, winSum=427
2692 10:02:07.428125 TX Vref=30, minBit 3, minWin=25, winSum=427
2693 10:02:07.434367 TX Vref=32, minBit 0, minWin=26, winSum=427
2694 10:02:07.437767 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 32
2695 10:02:07.437850
2696 10:02:07.440777 Final TX Range 1 Vref 32
2697 10:02:07.440858
2698 10:02:07.440922 ==
2699 10:02:07.444380 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 10:02:07.447398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 10:02:07.450982 ==
2702 10:02:07.451063
2703 10:02:07.451127
2704 10:02:07.451185 TX Vref Scan disable
2705 10:02:07.454440 == TX Byte 0 ==
2706 10:02:07.457525 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2707 10:02:07.464105 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2708 10:02:07.464186 == TX Byte 1 ==
2709 10:02:07.467420 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2710 10:02:07.474248 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2711 10:02:07.474330
2712 10:02:07.474393 [DATLAT]
2713 10:02:07.474452 Freq=1200, CH0 RK0
2714 10:02:07.474509
2715 10:02:07.477239 DATLAT Default: 0xd
2716 10:02:07.477321 0, 0xFFFF, sum = 0
2717 10:02:07.480712 1, 0xFFFF, sum = 0
2718 10:02:07.484333 2, 0xFFFF, sum = 0
2719 10:02:07.484415 3, 0xFFFF, sum = 0
2720 10:02:07.487221 4, 0xFFFF, sum = 0
2721 10:02:07.487304 5, 0xFFFF, sum = 0
2722 10:02:07.490673 6, 0xFFFF, sum = 0
2723 10:02:07.490756 7, 0xFFFF, sum = 0
2724 10:02:07.494279 8, 0xFFFF, sum = 0
2725 10:02:07.494361 9, 0xFFFF, sum = 0
2726 10:02:07.497302 10, 0xFFFF, sum = 0
2727 10:02:07.497385 11, 0xFFFF, sum = 0
2728 10:02:07.501095 12, 0x0, sum = 1
2729 10:02:07.501177 13, 0x0, sum = 2
2730 10:02:07.504216 14, 0x0, sum = 3
2731 10:02:07.504298 15, 0x0, sum = 4
2732 10:02:07.507100 best_step = 13
2733 10:02:07.507181
2734 10:02:07.507244 ==
2735 10:02:07.510357 Dram Type= 6, Freq= 0, CH_0, rank 0
2736 10:02:07.514081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2737 10:02:07.514163 ==
2738 10:02:07.514227 RX Vref Scan: 1
2739 10:02:07.517221
2740 10:02:07.517302 Set Vref Range= 32 -> 127
2741 10:02:07.517366
2742 10:02:07.520572 RX Vref 32 -> 127, step: 1
2743 10:02:07.520653
2744 10:02:07.523586 RX Delay -21 -> 252, step: 4
2745 10:02:07.523667
2746 10:02:07.527145 Set Vref, RX VrefLevel [Byte0]: 32
2747 10:02:07.530507 [Byte1]: 32
2748 10:02:07.530588
2749 10:02:07.533646 Set Vref, RX VrefLevel [Byte0]: 33
2750 10:02:07.536957 [Byte1]: 33
2751 10:02:07.540651
2752 10:02:07.540731 Set Vref, RX VrefLevel [Byte0]: 34
2753 10:02:07.544199 [Byte1]: 34
2754 10:02:07.548710
2755 10:02:07.548792 Set Vref, RX VrefLevel [Byte0]: 35
2756 10:02:07.551784 [Byte1]: 35
2757 10:02:07.556410
2758 10:02:07.556491 Set Vref, RX VrefLevel [Byte0]: 36
2759 10:02:07.560040 [Byte1]: 36
2760 10:02:07.564517
2761 10:02:07.564598 Set Vref, RX VrefLevel [Byte0]: 37
2762 10:02:07.567744 [Byte1]: 37
2763 10:02:07.572780
2764 10:02:07.572862 Set Vref, RX VrefLevel [Byte0]: 38
2765 10:02:07.575993 [Byte1]: 38
2766 10:02:07.580573
2767 10:02:07.580655 Set Vref, RX VrefLevel [Byte0]: 39
2768 10:02:07.583620 [Byte1]: 39
2769 10:02:07.588571
2770 10:02:07.588652 Set Vref, RX VrefLevel [Byte0]: 40
2771 10:02:07.591530 [Byte1]: 40
2772 10:02:07.595982
2773 10:02:07.596098 Set Vref, RX VrefLevel [Byte0]: 41
2774 10:02:07.599613 [Byte1]: 41
2775 10:02:07.604010
2776 10:02:07.604125 Set Vref, RX VrefLevel [Byte0]: 42
2777 10:02:07.607447 [Byte1]: 42
2778 10:02:07.612198
2779 10:02:07.612280 Set Vref, RX VrefLevel [Byte0]: 43
2780 10:02:07.615130 [Byte1]: 43
2781 10:02:07.620451
2782 10:02:07.620533 Set Vref, RX VrefLevel [Byte0]: 44
2783 10:02:07.623521 [Byte1]: 44
2784 10:02:07.627866
2785 10:02:07.627947 Set Vref, RX VrefLevel [Byte0]: 45
2786 10:02:07.631132 [Byte1]: 45
2787 10:02:07.636014
2788 10:02:07.636117 Set Vref, RX VrefLevel [Byte0]: 46
2789 10:02:07.639348 [Byte1]: 46
2790 10:02:07.643973
2791 10:02:07.644091 Set Vref, RX VrefLevel [Byte0]: 47
2792 10:02:07.647144 [Byte1]: 47
2793 10:02:07.651614
2794 10:02:07.651696 Set Vref, RX VrefLevel [Byte0]: 48
2795 10:02:07.655018 [Byte1]: 48
2796 10:02:07.659974
2797 10:02:07.660094 Set Vref, RX VrefLevel [Byte0]: 49
2798 10:02:07.663078 [Byte1]: 49
2799 10:02:07.667577
2800 10:02:07.667659 Set Vref, RX VrefLevel [Byte0]: 50
2801 10:02:07.670634 [Byte1]: 50
2802 10:02:07.675340
2803 10:02:07.675425 Set Vref, RX VrefLevel [Byte0]: 51
2804 10:02:07.679091 [Byte1]: 51
2805 10:02:07.683722
2806 10:02:07.683803 Set Vref, RX VrefLevel [Byte0]: 52
2807 10:02:07.686696 [Byte1]: 52
2808 10:02:07.691016
2809 10:02:07.691097 Set Vref, RX VrefLevel [Byte0]: 53
2810 10:02:07.694648 [Byte1]: 53
2811 10:02:07.699455
2812 10:02:07.699536 Set Vref, RX VrefLevel [Byte0]: 54
2813 10:02:07.702911 [Byte1]: 54
2814 10:02:07.707439
2815 10:02:07.707521 Set Vref, RX VrefLevel [Byte0]: 55
2816 10:02:07.710834 [Byte1]: 55
2817 10:02:07.715204
2818 10:02:07.715286 Set Vref, RX VrefLevel [Byte0]: 56
2819 10:02:07.718302 [Byte1]: 56
2820 10:02:07.722769
2821 10:02:07.722875 Set Vref, RX VrefLevel [Byte0]: 57
2822 10:02:07.726698 [Byte1]: 57
2823 10:02:07.730856
2824 10:02:07.730938 Set Vref, RX VrefLevel [Byte0]: 58
2825 10:02:07.734390 [Byte1]: 58
2826 10:02:07.739080
2827 10:02:07.739162 Set Vref, RX VrefLevel [Byte0]: 59
2828 10:02:07.742353 [Byte1]: 59
2829 10:02:07.746625
2830 10:02:07.746706 Set Vref, RX VrefLevel [Byte0]: 60
2831 10:02:07.749900 [Byte1]: 60
2832 10:02:07.754828
2833 10:02:07.754909 Set Vref, RX VrefLevel [Byte0]: 61
2834 10:02:07.757819 [Byte1]: 61
2835 10:02:07.762647
2836 10:02:07.762729 Set Vref, RX VrefLevel [Byte0]: 62
2837 10:02:07.765872 [Byte1]: 62
2838 10:02:07.770477
2839 10:02:07.770558 Set Vref, RX VrefLevel [Byte0]: 63
2840 10:02:07.773937 [Byte1]: 63
2841 10:02:07.778327
2842 10:02:07.778408 Set Vref, RX VrefLevel [Byte0]: 64
2843 10:02:07.782000 [Byte1]: 64
2844 10:02:07.786553
2845 10:02:07.786635 Set Vref, RX VrefLevel [Byte0]: 65
2846 10:02:07.789827 [Byte1]: 65
2847 10:02:07.794560
2848 10:02:07.794642 Set Vref, RX VrefLevel [Byte0]: 66
2849 10:02:07.797784 [Byte1]: 66
2850 10:02:07.802203
2851 10:02:07.802285 Set Vref, RX VrefLevel [Byte0]: 67
2852 10:02:07.805487 [Byte1]: 67
2853 10:02:07.810161
2854 10:02:07.810243 Set Vref, RX VrefLevel [Byte0]: 68
2855 10:02:07.813311 [Byte1]: 68
2856 10:02:07.818179
2857 10:02:07.818261 Final RX Vref Byte 0 = 54 to rank0
2858 10:02:07.821697 Final RX Vref Byte 1 = 59 to rank0
2859 10:02:07.825203 Final RX Vref Byte 0 = 54 to rank1
2860 10:02:07.828345 Final RX Vref Byte 1 = 59 to rank1==
2861 10:02:07.831394 Dram Type= 6, Freq= 0, CH_0, rank 0
2862 10:02:07.837881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2863 10:02:07.837964 ==
2864 10:02:07.838029 DQS Delay:
2865 10:02:07.838089 DQS0 = 0, DQS1 = 0
2866 10:02:07.841241 DQM Delay:
2867 10:02:07.841322 DQM0 = 117, DQM1 = 105
2868 10:02:07.844639 DQ Delay:
2869 10:02:07.847852 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2870 10:02:07.851442 DQ4 =120, DQ5 =110, DQ6 =124, DQ7 =122
2871 10:02:07.854551 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2872 10:02:07.858097 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2873 10:02:07.858179
2874 10:02:07.858244
2875 10:02:07.864633 [DQSOSCAuto] RK0, (LSB)MR18= 0x3fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2876 10:02:07.867984 CH0 RK0: MR19=403, MR18=3FE
2877 10:02:07.874395 CH0_RK0: MR19=0x403, MR18=0x3FE, DQSOSC=408, MR23=63, INC=39, DEC=26
2878 10:02:07.874477
2879 10:02:07.878259 ----->DramcWriteLeveling(PI) begin...
2880 10:02:07.878342 ==
2881 10:02:07.880990 Dram Type= 6, Freq= 0, CH_0, rank 1
2882 10:02:07.884771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2883 10:02:07.884854 ==
2884 10:02:07.888637 Write leveling (Byte 0): 33 => 33
2885 10:02:07.891621 Write leveling (Byte 1): 27 => 27
2886 10:02:07.894810 DramcWriteLeveling(PI) end<-----
2887 10:02:07.894892
2888 10:02:07.894956 ==
2889 10:02:07.898015 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 10:02:07.904547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 10:02:07.904630 ==
2892 10:02:07.904695 [Gating] SW mode calibration
2893 10:02:07.914587 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2894 10:02:07.917883 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2895 10:02:07.921266 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2896 10:02:07.927717 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2897 10:02:07.931429 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 10:02:07.934284 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 10:02:07.940790 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 10:02:07.944036 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 10:02:07.948314 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2902 10:02:07.954225 0 15 28 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
2903 10:02:07.957487 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2904 10:02:07.961156 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 10:02:07.967900 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 10:02:07.970732 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 10:02:07.974020 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 10:02:07.981080 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 10:02:07.984378 1 0 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2910 10:02:07.987562 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2911 10:02:07.994636 1 1 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2912 10:02:07.997369 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 10:02:08.000633 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 10:02:08.007597 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 10:02:08.011005 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 10:02:08.014528 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 10:02:08.020772 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2918 10:02:08.024226 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2919 10:02:08.027236 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2920 10:02:08.034639 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2921 10:02:08.037288 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 10:02:08.040582 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 10:02:08.047333 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 10:02:08.050675 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 10:02:08.054702 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 10:02:08.061383 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 10:02:08.063948 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 10:02:08.067150 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 10:02:08.073528 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 10:02:08.076771 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 10:02:08.081123 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 10:02:08.083948 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 10:02:08.090111 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2934 10:02:08.093779 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2935 10:02:08.097113 Total UI for P1: 0, mck2ui 16
2936 10:02:08.100290 best dqsien dly found for B0: ( 1, 3, 24)
2937 10:02:08.103356 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2938 10:02:08.110198 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2939 10:02:08.113501 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 10:02:08.116578 Total UI for P1: 0, mck2ui 16
2941 10:02:08.120345 best dqsien dly found for B1: ( 1, 4, 2)
2942 10:02:08.123215 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2943 10:02:08.126762 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2944 10:02:08.126846
2945 10:02:08.129717 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2946 10:02:08.133485 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2947 10:02:08.136482 [Gating] SW calibration Done
2948 10:02:08.136590 ==
2949 10:02:08.139758 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 10:02:08.146639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 10:02:08.146722 ==
2952 10:02:08.146788 RX Vref Scan: 0
2953 10:02:08.146851
2954 10:02:08.149531 RX Vref 0 -> 0, step: 1
2955 10:02:08.149628
2956 10:02:08.153227 RX Delay -40 -> 252, step: 8
2957 10:02:08.156274 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2958 10:02:08.160042 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2959 10:02:08.163167 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2960 10:02:08.169827 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2961 10:02:08.173346 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2962 10:02:08.176858 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2963 10:02:08.179437 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2964 10:02:08.182624 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2965 10:02:08.186095 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2966 10:02:08.192444 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2967 10:02:08.195956 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2968 10:02:08.199449 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2969 10:02:08.202692 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2970 10:02:08.209292 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2971 10:02:08.212753 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2972 10:02:08.215967 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2973 10:02:08.216072 ==
2974 10:02:08.219228 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 10:02:08.222306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 10:02:08.222389 ==
2977 10:02:08.226070 DQS Delay:
2978 10:02:08.226155 DQS0 = 0, DQS1 = 0
2979 10:02:08.228914 DQM Delay:
2980 10:02:08.228995 DQM0 = 117, DQM1 = 109
2981 10:02:08.229063 DQ Delay:
2982 10:02:08.235713 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111
2983 10:02:08.238976 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2984 10:02:08.242276 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2985 10:02:08.245600 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =115
2986 10:02:08.245685
2987 10:02:08.245810
2988 10:02:08.245920 ==
2989 10:02:08.249047 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 10:02:08.252428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 10:02:08.252512 ==
2992 10:02:08.252577
2993 10:02:08.252636
2994 10:02:08.255537 TX Vref Scan disable
2995 10:02:08.258814 == TX Byte 0 ==
2996 10:02:08.261937 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2997 10:02:08.265794 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2998 10:02:08.268838 == TX Byte 1 ==
2999 10:02:08.272191 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3000 10:02:08.275128 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3001 10:02:08.275210 ==
3002 10:02:08.279014 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 10:02:08.285420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 10:02:08.285503 ==
3005 10:02:08.296311 TX Vref=22, minBit 12, minWin=25, winSum=416
3006 10:02:08.300198 TX Vref=24, minBit 13, minWin=25, winSum=422
3007 10:02:08.302634 TX Vref=26, minBit 12, minWin=25, winSum=425
3008 10:02:08.305929 TX Vref=28, minBit 12, minWin=26, winSum=428
3009 10:02:08.309434 TX Vref=30, minBit 5, minWin=26, winSum=428
3010 10:02:08.315671 TX Vref=32, minBit 14, minWin=25, winSum=426
3011 10:02:08.319060 [TxChooseVref] Worse bit 12, Min win 26, Win sum 428, Final Vref 28
3012 10:02:08.322581
3013 10:02:08.322663 Final TX Range 1 Vref 28
3014 10:02:08.322728
3015 10:02:08.322787 ==
3016 10:02:08.326114 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 10:02:08.332274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 10:02:08.332355 ==
3019 10:02:08.332421
3020 10:02:08.332480
3021 10:02:08.332537 TX Vref Scan disable
3022 10:02:08.336020 == TX Byte 0 ==
3023 10:02:08.339585 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3024 10:02:08.346567 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3025 10:02:08.346642 == TX Byte 1 ==
3026 10:02:08.349980 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3027 10:02:08.353039 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3028 10:02:08.356464
3029 10:02:08.356538 [DATLAT]
3030 10:02:08.356601 Freq=1200, CH0 RK1
3031 10:02:08.356661
3032 10:02:08.359990 DATLAT Default: 0xd
3033 10:02:08.360128 0, 0xFFFF, sum = 0
3034 10:02:08.362621 1, 0xFFFF, sum = 0
3035 10:02:08.362720 2, 0xFFFF, sum = 0
3036 10:02:08.365981 3, 0xFFFF, sum = 0
3037 10:02:08.369601 4, 0xFFFF, sum = 0
3038 10:02:08.369671 5, 0xFFFF, sum = 0
3039 10:02:08.373064 6, 0xFFFF, sum = 0
3040 10:02:08.373134 7, 0xFFFF, sum = 0
3041 10:02:08.376663 8, 0xFFFF, sum = 0
3042 10:02:08.376736 9, 0xFFFF, sum = 0
3043 10:02:08.379763 10, 0xFFFF, sum = 0
3044 10:02:08.379837 11, 0xFFFF, sum = 0
3045 10:02:08.382746 12, 0x0, sum = 1
3046 10:02:08.382821 13, 0x0, sum = 2
3047 10:02:08.386078 14, 0x0, sum = 3
3048 10:02:08.386148 15, 0x0, sum = 4
3049 10:02:08.386208 best_step = 13
3050 10:02:08.389417
3051 10:02:08.389487 ==
3052 10:02:08.392904 Dram Type= 6, Freq= 0, CH_0, rank 1
3053 10:02:08.396192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 10:02:08.396258 ==
3055 10:02:08.396319 RX Vref Scan: 0
3056 10:02:08.396378
3057 10:02:08.399415 RX Vref 0 -> 0, step: 1
3058 10:02:08.399478
3059 10:02:08.402921 RX Delay -21 -> 252, step: 4
3060 10:02:08.406073 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3061 10:02:08.412605 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3062 10:02:08.415828 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3063 10:02:08.419695 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3064 10:02:08.423112 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3065 10:02:08.426038 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3066 10:02:08.432329 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3067 10:02:08.436017 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3068 10:02:08.439320 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3069 10:02:08.442524 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3070 10:02:08.445687 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3071 10:02:08.452537 iDelay=195, Bit 11, Center 100 (31 ~ 170) 140
3072 10:02:08.455994 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3073 10:02:08.459214 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3074 10:02:08.462314 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3075 10:02:08.465654 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3076 10:02:08.469103 ==
3077 10:02:08.472211 Dram Type= 6, Freq= 0, CH_0, rank 1
3078 10:02:08.475617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 10:02:08.475693 ==
3080 10:02:08.475755 DQS Delay:
3081 10:02:08.478941 DQS0 = 0, DQS1 = 0
3082 10:02:08.479008 DQM Delay:
3083 10:02:08.482267 DQM0 = 116, DQM1 = 106
3084 10:02:08.482333 DQ Delay:
3085 10:02:08.485997 DQ0 =114, DQ1 =118, DQ2 =112, DQ3 =112
3086 10:02:08.489098 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
3087 10:02:08.492057 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3088 10:02:08.495423 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3089 10:02:08.495491
3090 10:02:08.495552
3091 10:02:08.505375 [DQSOSCAuto] RK1, (LSB)MR18= 0xfefb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
3092 10:02:08.509085 CH0 RK1: MR19=303, MR18=FEFB
3093 10:02:08.511988 CH0_RK1: MR19=0x303, MR18=0xFEFB, DQSOSC=410, MR23=63, INC=39, DEC=26
3094 10:02:08.515321 [RxdqsGatingPostProcess] freq 1200
3095 10:02:08.521889 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3096 10:02:08.525325 best DQS0 dly(2T, 0.5T) = (0, 11)
3097 10:02:08.529062 best DQS1 dly(2T, 0.5T) = (0, 12)
3098 10:02:08.532000 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3099 10:02:08.535167 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3100 10:02:08.538790 best DQS0 dly(2T, 0.5T) = (0, 11)
3101 10:02:08.542344 best DQS1 dly(2T, 0.5T) = (0, 12)
3102 10:02:08.545336 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3103 10:02:08.548256 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3104 10:02:08.551358 Pre-setting of DQS Precalculation
3105 10:02:08.555164 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3106 10:02:08.555233 ==
3107 10:02:08.558363 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 10:02:08.561373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 10:02:08.561442 ==
3110 10:02:08.567999 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3111 10:02:08.574815 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3112 10:02:08.582286 [CA 0] Center 38 (8~68) winsize 61
3113 10:02:08.585958 [CA 1] Center 37 (7~68) winsize 62
3114 10:02:08.589228 [CA 2] Center 35 (5~65) winsize 61
3115 10:02:08.592500 [CA 3] Center 34 (4~64) winsize 61
3116 10:02:08.595745 [CA 4] Center 34 (4~65) winsize 62
3117 10:02:08.599087 [CA 5] Center 33 (3~64) winsize 62
3118 10:02:08.599156
3119 10:02:08.602286 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3120 10:02:08.602373
3121 10:02:08.606193 [CATrainingPosCal] consider 1 rank data
3122 10:02:08.608994 u2DelayCellTimex100 = 270/100 ps
3123 10:02:08.612221 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3124 10:02:08.615787 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3125 10:02:08.622892 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3126 10:02:08.626038 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3127 10:02:08.629502 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3128 10:02:08.632930 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3129 10:02:08.633005
3130 10:02:08.635971 CA PerBit enable=1, Macro0, CA PI delay=33
3131 10:02:08.636048
3132 10:02:08.639060 [CBTSetCACLKResult] CA Dly = 33
3133 10:02:08.639129 CS Dly: 5 (0~36)
3134 10:02:08.639194 ==
3135 10:02:08.642581 Dram Type= 6, Freq= 0, CH_1, rank 1
3136 10:02:08.649251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 10:02:08.649325 ==
3138 10:02:08.652352 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3139 10:02:08.659027 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3140 10:02:08.668627 [CA 0] Center 37 (7~68) winsize 62
3141 10:02:08.671646 [CA 1] Center 38 (8~68) winsize 61
3142 10:02:08.674789 [CA 2] Center 34 (4~65) winsize 62
3143 10:02:08.678141 [CA 3] Center 33 (3~64) winsize 62
3144 10:02:08.681368 [CA 4] Center 33 (3~64) winsize 62
3145 10:02:08.684743 [CA 5] Center 33 (3~64) winsize 62
3146 10:02:08.684818
3147 10:02:08.688132 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3148 10:02:08.688208
3149 10:02:08.691685 [CATrainingPosCal] consider 2 rank data
3150 10:02:08.694475 u2DelayCellTimex100 = 270/100 ps
3151 10:02:08.697979 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3152 10:02:08.704730 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3153 10:02:08.707859 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3154 10:02:08.711561 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 10:02:08.714848 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3156 10:02:08.717841 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3157 10:02:08.717909
3158 10:02:08.721080 CA PerBit enable=1, Macro0, CA PI delay=33
3159 10:02:08.721150
3160 10:02:08.724621 [CBTSetCACLKResult] CA Dly = 33
3161 10:02:08.724691 CS Dly: 6 (0~39)
3162 10:02:08.724753
3163 10:02:08.728137 ----->DramcWriteLeveling(PI) begin...
3164 10:02:08.731243 ==
3165 10:02:08.734525 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 10:02:08.737546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 10:02:08.737614 ==
3168 10:02:08.740845 Write leveling (Byte 0): 27 => 27
3169 10:02:08.745069 Write leveling (Byte 1): 28 => 28
3170 10:02:08.747591 DramcWriteLeveling(PI) end<-----
3171 10:02:08.747665
3172 10:02:08.747725 ==
3173 10:02:08.750987 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 10:02:08.754367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 10:02:08.754437 ==
3176 10:02:08.757906 [Gating] SW mode calibration
3177 10:02:08.764485 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3178 10:02:08.770775 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3179 10:02:08.774326 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3180 10:02:08.777654 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 10:02:08.784098 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 10:02:08.787228 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 10:02:08.790780 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 10:02:08.797353 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 10:02:08.800839 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3186 10:02:08.804687 0 15 28 | B1->B0 | 2a2a 2424 | 1 0 | (1 0) (1 0)
3187 10:02:08.810948 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 10:02:08.814118 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 10:02:08.817328 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 10:02:08.823848 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 10:02:08.827123 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 10:02:08.831197 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 10:02:08.837263 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
3194 10:02:08.840389 1 0 28 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
3195 10:02:08.844010 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 10:02:08.847402 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 10:02:08.853949 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 10:02:08.857430 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 10:02:08.860173 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 10:02:08.866615 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 10:02:08.870302 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3202 10:02:08.873623 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3203 10:02:08.879984 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 10:02:08.883745 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 10:02:08.886684 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 10:02:08.893350 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 10:02:08.896805 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 10:02:08.900150 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 10:02:08.906750 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 10:02:08.909863 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 10:02:08.913988 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 10:02:08.920294 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 10:02:08.923385 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 10:02:08.926569 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 10:02:08.933328 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 10:02:08.936665 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 10:02:08.939620 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3218 10:02:08.946452 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3219 10:02:08.949288 Total UI for P1: 0, mck2ui 16
3220 10:02:08.953000 best dqsien dly found for B0: ( 1, 3, 24)
3221 10:02:08.955835 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 10:02:08.959647 Total UI for P1: 0, mck2ui 16
3223 10:02:08.962861 best dqsien dly found for B1: ( 1, 3, 28)
3224 10:02:08.965878 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3225 10:02:08.969168 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3226 10:02:08.969250
3227 10:02:08.972775 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3228 10:02:08.975919 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3229 10:02:08.979532 [Gating] SW calibration Done
3230 10:02:08.979614 ==
3231 10:02:08.982601 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 10:02:08.989008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 10:02:08.989090 ==
3234 10:02:08.989155 RX Vref Scan: 0
3235 10:02:08.989217
3236 10:02:08.992404 RX Vref 0 -> 0, step: 1
3237 10:02:08.992485
3238 10:02:08.995889 RX Delay -40 -> 252, step: 8
3239 10:02:08.999478 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3240 10:02:09.002419 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3241 10:02:09.005857 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3242 10:02:09.009265 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3243 10:02:09.016208 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3244 10:02:09.019427 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3245 10:02:09.022210 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3246 10:02:09.026327 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3247 10:02:09.029560 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3248 10:02:09.035834 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3249 10:02:09.038634 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3250 10:02:09.042461 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3251 10:02:09.045505 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3252 10:02:09.052317 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3253 10:02:09.055689 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3254 10:02:09.059245 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3255 10:02:09.059322 ==
3256 10:02:09.062110 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 10:02:09.065456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 10:02:09.065530 ==
3259 10:02:09.069023 DQS Delay:
3260 10:02:09.069131 DQS0 = 0, DQS1 = 0
3261 10:02:09.072066 DQM Delay:
3262 10:02:09.072177 DQM0 = 115, DQM1 = 112
3263 10:02:09.072277 DQ Delay:
3264 10:02:09.075602 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3265 10:02:09.082196 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3266 10:02:09.085486 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3267 10:02:09.088968 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3268 10:02:09.089061
3269 10:02:09.089126
3270 10:02:09.089185 ==
3271 10:02:09.091801 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 10:02:09.095223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 10:02:09.095323 ==
3274 10:02:09.095412
3275 10:02:09.095504
3276 10:02:09.098914 TX Vref Scan disable
3277 10:02:09.102187 == TX Byte 0 ==
3278 10:02:09.104953 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3279 10:02:09.108462 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3280 10:02:09.111604 == TX Byte 1 ==
3281 10:02:09.114898 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3282 10:02:09.119130 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3283 10:02:09.119214 ==
3284 10:02:09.121400 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 10:02:09.124844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 10:02:09.128305 ==
3287 10:02:09.138485 TX Vref=22, minBit 11, minWin=24, winSum=409
3288 10:02:09.141629 TX Vref=24, minBit 1, minWin=25, winSum=418
3289 10:02:09.144567 TX Vref=26, minBit 3, minWin=25, winSum=424
3290 10:02:09.148306 TX Vref=28, minBit 9, minWin=25, winSum=432
3291 10:02:09.151308 TX Vref=30, minBit 9, minWin=26, winSum=432
3292 10:02:09.158149 TX Vref=32, minBit 1, minWin=26, winSum=427
3293 10:02:09.161474 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 30
3294 10:02:09.161557
3295 10:02:09.164464 Final TX Range 1 Vref 30
3296 10:02:09.164547
3297 10:02:09.164612 ==
3298 10:02:09.167674 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 10:02:09.171281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 10:02:09.174492 ==
3301 10:02:09.174573
3302 10:02:09.174637
3303 10:02:09.174696 TX Vref Scan disable
3304 10:02:09.178234 == TX Byte 0 ==
3305 10:02:09.181196 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3306 10:02:09.187905 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3307 10:02:09.187988 == TX Byte 1 ==
3308 10:02:09.191109 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3309 10:02:09.194506 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3310 10:02:09.198088
3311 10:02:09.198170 [DATLAT]
3312 10:02:09.198234 Freq=1200, CH1 RK0
3313 10:02:09.198295
3314 10:02:09.201160 DATLAT Default: 0xd
3315 10:02:09.201244 0, 0xFFFF, sum = 0
3316 10:02:09.204476 1, 0xFFFF, sum = 0
3317 10:02:09.204548 2, 0xFFFF, sum = 0
3318 10:02:09.207774 3, 0xFFFF, sum = 0
3319 10:02:09.211660 4, 0xFFFF, sum = 0
3320 10:02:09.211738 5, 0xFFFF, sum = 0
3321 10:02:09.214674 6, 0xFFFF, sum = 0
3322 10:02:09.214743 7, 0xFFFF, sum = 0
3323 10:02:09.217829 8, 0xFFFF, sum = 0
3324 10:02:09.217903 9, 0xFFFF, sum = 0
3325 10:02:09.221291 10, 0xFFFF, sum = 0
3326 10:02:09.221361 11, 0xFFFF, sum = 0
3327 10:02:09.225411 12, 0x0, sum = 1
3328 10:02:09.225482 13, 0x0, sum = 2
3329 10:02:09.227884 14, 0x0, sum = 3
3330 10:02:09.227956 15, 0x0, sum = 4
3331 10:02:09.231128 best_step = 13
3332 10:02:09.231202
3333 10:02:09.231262 ==
3334 10:02:09.234271 Dram Type= 6, Freq= 0, CH_1, rank 0
3335 10:02:09.237989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3336 10:02:09.238062 ==
3337 10:02:09.238124 RX Vref Scan: 1
3338 10:02:09.238181
3339 10:02:09.241077 Set Vref Range= 32 -> 127
3340 10:02:09.241144
3341 10:02:09.244296 RX Vref 32 -> 127, step: 1
3342 10:02:09.244367
3343 10:02:09.247673 RX Delay -13 -> 252, step: 4
3344 10:02:09.247747
3345 10:02:09.250706 Set Vref, RX VrefLevel [Byte0]: 32
3346 10:02:09.254360 [Byte1]: 32
3347 10:02:09.254429
3348 10:02:09.257750 Set Vref, RX VrefLevel [Byte0]: 33
3349 10:02:09.260917 [Byte1]: 33
3350 10:02:09.264260
3351 10:02:09.264329 Set Vref, RX VrefLevel [Byte0]: 34
3352 10:02:09.267544 [Byte1]: 34
3353 10:02:09.273055
3354 10:02:09.273124 Set Vref, RX VrefLevel [Byte0]: 35
3355 10:02:09.275527 [Byte1]: 35
3356 10:02:09.280179
3357 10:02:09.280249 Set Vref, RX VrefLevel [Byte0]: 36
3358 10:02:09.283475 [Byte1]: 36
3359 10:02:09.287942
3360 10:02:09.288041 Set Vref, RX VrefLevel [Byte0]: 37
3361 10:02:09.291157 [Byte1]: 37
3362 10:02:09.295639
3363 10:02:09.295704 Set Vref, RX VrefLevel [Byte0]: 38
3364 10:02:09.299061 [Byte1]: 38
3365 10:02:09.303659
3366 10:02:09.303726 Set Vref, RX VrefLevel [Byte0]: 39
3367 10:02:09.306855 [Byte1]: 39
3368 10:02:09.311541
3369 10:02:09.311614 Set Vref, RX VrefLevel [Byte0]: 40
3370 10:02:09.314921 [Byte1]: 40
3371 10:02:09.319475
3372 10:02:09.319549 Set Vref, RX VrefLevel [Byte0]: 41
3373 10:02:09.322567 [Byte1]: 41
3374 10:02:09.327172
3375 10:02:09.327243 Set Vref, RX VrefLevel [Byte0]: 42
3376 10:02:09.330906 [Byte1]: 42
3377 10:02:09.336312
3378 10:02:09.336383 Set Vref, RX VrefLevel [Byte0]: 43
3379 10:02:09.338626 [Byte1]: 43
3380 10:02:09.343221
3381 10:02:09.343291 Set Vref, RX VrefLevel [Byte0]: 44
3382 10:02:09.346538 [Byte1]: 44
3383 10:02:09.351085
3384 10:02:09.351159 Set Vref, RX VrefLevel [Byte0]: 45
3385 10:02:09.354552 [Byte1]: 45
3386 10:02:09.359182
3387 10:02:09.359252 Set Vref, RX VrefLevel [Byte0]: 46
3388 10:02:09.362113 [Byte1]: 46
3389 10:02:09.366455
3390 10:02:09.366552 Set Vref, RX VrefLevel [Byte0]: 47
3391 10:02:09.370243 [Byte1]: 47
3392 10:02:09.374883
3393 10:02:09.374954 Set Vref, RX VrefLevel [Byte0]: 48
3394 10:02:09.377740 [Byte1]: 48
3395 10:02:09.382498
3396 10:02:09.382564 Set Vref, RX VrefLevel [Byte0]: 49
3397 10:02:09.385605 [Byte1]: 49
3398 10:02:09.390938
3399 10:02:09.391009 Set Vref, RX VrefLevel [Byte0]: 50
3400 10:02:09.393718 [Byte1]: 50
3401 10:02:09.398556
3402 10:02:09.398621 Set Vref, RX VrefLevel [Byte0]: 51
3403 10:02:09.401566 [Byte1]: 51
3404 10:02:09.406431
3405 10:02:09.406501 Set Vref, RX VrefLevel [Byte0]: 52
3406 10:02:09.409639 [Byte1]: 52
3407 10:02:09.413885
3408 10:02:09.413954 Set Vref, RX VrefLevel [Byte0]: 53
3409 10:02:09.417610 [Byte1]: 53
3410 10:02:09.422207
3411 10:02:09.422277 Set Vref, RX VrefLevel [Byte0]: 54
3412 10:02:09.425532 [Byte1]: 54
3413 10:02:09.429863
3414 10:02:09.429938 Set Vref, RX VrefLevel [Byte0]: 55
3415 10:02:09.433171 [Byte1]: 55
3416 10:02:09.437620
3417 10:02:09.437696 Set Vref, RX VrefLevel [Byte0]: 56
3418 10:02:09.440989 [Byte1]: 56
3419 10:02:09.445370
3420 10:02:09.445442 Set Vref, RX VrefLevel [Byte0]: 57
3421 10:02:09.449197 [Byte1]: 57
3422 10:02:09.453679
3423 10:02:09.453745 Set Vref, RX VrefLevel [Byte0]: 58
3424 10:02:09.457353 [Byte1]: 58
3425 10:02:09.461445
3426 10:02:09.461522 Set Vref, RX VrefLevel [Byte0]: 59
3427 10:02:09.464860 [Byte1]: 59
3428 10:02:09.469079
3429 10:02:09.469184 Set Vref, RX VrefLevel [Byte0]: 60
3430 10:02:09.472845 [Byte1]: 60
3431 10:02:09.477342
3432 10:02:09.477423 Set Vref, RX VrefLevel [Byte0]: 61
3433 10:02:09.480776 [Byte1]: 61
3434 10:02:09.484709
3435 10:02:09.484789 Set Vref, RX VrefLevel [Byte0]: 62
3436 10:02:09.488341 [Byte1]: 62
3437 10:02:09.492921
3438 10:02:09.493002 Set Vref, RX VrefLevel [Byte0]: 63
3439 10:02:09.496237 [Byte1]: 63
3440 10:02:09.501067
3441 10:02:09.501148 Set Vref, RX VrefLevel [Byte0]: 64
3442 10:02:09.503914 [Byte1]: 64
3443 10:02:09.508783
3444 10:02:09.508923 Set Vref, RX VrefLevel [Byte0]: 65
3445 10:02:09.511954 [Byte1]: 65
3446 10:02:09.517030
3447 10:02:09.517107 Final RX Vref Byte 0 = 52 to rank0
3448 10:02:09.519897 Final RX Vref Byte 1 = 53 to rank0
3449 10:02:09.523231 Final RX Vref Byte 0 = 52 to rank1
3450 10:02:09.526380 Final RX Vref Byte 1 = 53 to rank1==
3451 10:02:09.529641 Dram Type= 6, Freq= 0, CH_1, rank 0
3452 10:02:09.536337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3453 10:02:09.536419 ==
3454 10:02:09.536485 DQS Delay:
3455 10:02:09.539651 DQS0 = 0, DQS1 = 0
3456 10:02:09.539740 DQM Delay:
3457 10:02:09.539840 DQM0 = 115, DQM1 = 112
3458 10:02:09.543339 DQ Delay:
3459 10:02:09.546526 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =116
3460 10:02:09.549925 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =112
3461 10:02:09.553098 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3462 10:02:09.556497 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3463 10:02:09.556579
3464 10:02:09.556643
3465 10:02:09.566485 [DQSOSCAuto] RK0, (LSB)MR18= 0xf3ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3466 10:02:09.566568 CH1 RK0: MR19=303, MR18=F3FF
3467 10:02:09.573057 CH1_RK0: MR19=0x303, MR18=0xF3FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3468 10:02:09.573181
3469 10:02:09.576224 ----->DramcWriteLeveling(PI) begin...
3470 10:02:09.576307 ==
3471 10:02:09.579222 Dram Type= 6, Freq= 0, CH_1, rank 1
3472 10:02:09.586457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3473 10:02:09.586540 ==
3474 10:02:09.589778 Write leveling (Byte 0): 24 => 24
3475 10:02:09.589861 Write leveling (Byte 1): 28 => 28
3476 10:02:09.593000 DramcWriteLeveling(PI) end<-----
3477 10:02:09.593082
3478 10:02:09.596280 ==
3479 10:02:09.596363 Dram Type= 6, Freq= 0, CH_1, rank 1
3480 10:02:09.602644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3481 10:02:09.602727 ==
3482 10:02:09.605953 [Gating] SW mode calibration
3483 10:02:09.612491 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3484 10:02:09.615918 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3485 10:02:09.622836 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 10:02:09.625943 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 10:02:09.629327 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 10:02:09.635642 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 10:02:09.638929 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 10:02:09.642546 0 15 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3491 10:02:09.649060 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
3492 10:02:09.652279 0 15 28 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)
3493 10:02:09.655916 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3494 10:02:09.662614 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 10:02:09.665538 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 10:02:09.668926 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 10:02:09.675450 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 10:02:09.679010 1 0 20 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
3499 10:02:09.682247 1 0 24 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
3500 10:02:09.690040 1 0 28 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
3501 10:02:09.692195 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 10:02:09.695755 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 10:02:09.701988 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 10:02:09.705507 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 10:02:09.708498 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 10:02:09.715294 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 10:02:09.718179 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3508 10:02:09.721803 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3509 10:02:09.728469 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 10:02:09.731360 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 10:02:09.735009 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 10:02:09.741825 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 10:02:09.744907 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 10:02:09.748336 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 10:02:09.754950 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 10:02:09.758086 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 10:02:09.761052 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 10:02:09.767883 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 10:02:09.771778 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 10:02:09.774374 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 10:02:09.781398 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 10:02:09.784331 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 10:02:09.787672 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3524 10:02:09.794221 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3525 10:02:09.797500 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 10:02:09.800714 Total UI for P1: 0, mck2ui 16
3527 10:02:09.803730 best dqsien dly found for B0: ( 1, 3, 26)
3528 10:02:09.807566 Total UI for P1: 0, mck2ui 16
3529 10:02:09.810608 best dqsien dly found for B1: ( 1, 3, 26)
3530 10:02:09.813876 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3531 10:02:09.816824 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3532 10:02:09.816906
3533 10:02:09.820495 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3534 10:02:09.823701 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3535 10:02:09.826826 [Gating] SW calibration Done
3536 10:02:09.826907 ==
3537 10:02:09.830086 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 10:02:09.836451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 10:02:09.836534 ==
3540 10:02:09.836599 RX Vref Scan: 0
3541 10:02:09.836659
3542 10:02:09.839907 RX Vref 0 -> 0, step: 1
3543 10:02:09.840023
3544 10:02:09.843498 RX Delay -40 -> 252, step: 8
3545 10:02:09.846461 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3546 10:02:09.849536 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3547 10:02:09.852937 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3548 10:02:09.856751 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3549 10:02:09.862929 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3550 10:02:09.866701 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3551 10:02:09.869779 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3552 10:02:09.873207 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3553 10:02:09.876591 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3554 10:02:09.882874 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3555 10:02:09.886193 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3556 10:02:09.889706 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3557 10:02:09.892592 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3558 10:02:09.899596 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3559 10:02:09.902558 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3560 10:02:09.907195 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3561 10:02:09.907277 ==
3562 10:02:09.908972 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 10:02:09.912705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 10:02:09.912788 ==
3565 10:02:09.915962 DQS Delay:
3566 10:02:09.916103 DQS0 = 0, DQS1 = 0
3567 10:02:09.918979 DQM Delay:
3568 10:02:09.919088 DQM0 = 115, DQM1 = 112
3569 10:02:09.922417 DQ Delay:
3570 10:02:09.925899 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3571 10:02:09.929249 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3572 10:02:09.931951 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3573 10:02:09.935535 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3574 10:02:09.935617
3575 10:02:09.935690
3576 10:02:09.935752 ==
3577 10:02:09.938660 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 10:02:09.941835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 10:02:09.941926 ==
3580 10:02:09.942035
3581 10:02:09.942134
3582 10:02:09.945563 TX Vref Scan disable
3583 10:02:09.948923 == TX Byte 0 ==
3584 10:02:09.952125 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3585 10:02:09.955147 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3586 10:02:09.959290 == TX Byte 1 ==
3587 10:02:09.961808 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3588 10:02:09.965114 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3589 10:02:09.965197 ==
3590 10:02:09.968388 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 10:02:09.974984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 10:02:09.975066 ==
3593 10:02:09.985505 TX Vref=22, minBit 0, minWin=26, winSum=422
3594 10:02:09.989528 TX Vref=24, minBit 1, minWin=26, winSum=426
3595 10:02:09.992478 TX Vref=26, minBit 1, minWin=26, winSum=431
3596 10:02:09.995735 TX Vref=28, minBit 1, minWin=26, winSum=433
3597 10:02:09.999059 TX Vref=30, minBit 9, minWin=25, winSum=433
3598 10:02:10.005776 TX Vref=32, minBit 0, minWin=26, winSum=433
3599 10:02:10.008847 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 28
3600 10:02:10.008929
3601 10:02:10.012379 Final TX Range 1 Vref 28
3602 10:02:10.012462
3603 10:02:10.012526 ==
3604 10:02:10.015519 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 10:02:10.018920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 10:02:10.021943 ==
3607 10:02:10.022025
3608 10:02:10.022089
3609 10:02:10.022148 TX Vref Scan disable
3610 10:02:10.025914 == TX Byte 0 ==
3611 10:02:10.028872 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3612 10:02:10.035230 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3613 10:02:10.035312 == TX Byte 1 ==
3614 10:02:10.038635 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3615 10:02:10.045187 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3616 10:02:10.045269
3617 10:02:10.045334 [DATLAT]
3618 10:02:10.045394 Freq=1200, CH1 RK1
3619 10:02:10.045452
3620 10:02:10.048245 DATLAT Default: 0xd
3621 10:02:10.051569 0, 0xFFFF, sum = 0
3622 10:02:10.051652 1, 0xFFFF, sum = 0
3623 10:02:10.055310 2, 0xFFFF, sum = 0
3624 10:02:10.055392 3, 0xFFFF, sum = 0
3625 10:02:10.058080 4, 0xFFFF, sum = 0
3626 10:02:10.058164 5, 0xFFFF, sum = 0
3627 10:02:10.061358 6, 0xFFFF, sum = 0
3628 10:02:10.061441 7, 0xFFFF, sum = 0
3629 10:02:10.064832 8, 0xFFFF, sum = 0
3630 10:02:10.064915 9, 0xFFFF, sum = 0
3631 10:02:10.068998 10, 0xFFFF, sum = 0
3632 10:02:10.069081 11, 0xFFFF, sum = 0
3633 10:02:10.072157 12, 0x0, sum = 1
3634 10:02:10.072240 13, 0x0, sum = 2
3635 10:02:10.075315 14, 0x0, sum = 3
3636 10:02:10.075398 15, 0x0, sum = 4
3637 10:02:10.078574 best_step = 13
3638 10:02:10.078655
3639 10:02:10.078718 ==
3640 10:02:10.081371 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 10:02:10.084565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 10:02:10.084648 ==
3643 10:02:10.087679 RX Vref Scan: 0
3644 10:02:10.087761
3645 10:02:10.087825 RX Vref 0 -> 0, step: 1
3646 10:02:10.087886
3647 10:02:10.091835 RX Delay -13 -> 252, step: 4
3648 10:02:10.097873 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3649 10:02:10.101188 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3650 10:02:10.104389 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3651 10:02:10.107774 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3652 10:02:10.114279 iDelay=195, Bit 4, Center 114 (43 ~ 186) 144
3653 10:02:10.117521 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3654 10:02:10.121332 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3655 10:02:10.124104 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3656 10:02:10.127593 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3657 10:02:10.133604 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3658 10:02:10.137496 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3659 10:02:10.140826 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3660 10:02:10.143789 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3661 10:02:10.147232 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3662 10:02:10.153834 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3663 10:02:10.157068 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3664 10:02:10.157150 ==
3665 10:02:10.160221 Dram Type= 6, Freq= 0, CH_1, rank 1
3666 10:02:10.163384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3667 10:02:10.163466 ==
3668 10:02:10.166769 DQS Delay:
3669 10:02:10.166856 DQS0 = 0, DQS1 = 0
3670 10:02:10.166920 DQM Delay:
3671 10:02:10.170300 DQM0 = 114, DQM1 = 111
3672 10:02:10.170381 DQ Delay:
3673 10:02:10.173451 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =112
3674 10:02:10.176672 DQ4 =114, DQ5 =122, DQ6 =120, DQ7 =114
3675 10:02:10.183340 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3676 10:02:10.186335 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =120
3677 10:02:10.186417
3678 10:02:10.186481
3679 10:02:10.193273 [DQSOSCAuto] RK1, (LSB)MR18= 0xf609, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
3680 10:02:10.196314 CH1 RK1: MR19=304, MR18=F609
3681 10:02:10.202913 CH1_RK1: MR19=0x304, MR18=0xF609, DQSOSC=406, MR23=63, INC=39, DEC=26
3682 10:02:10.206572 [RxdqsGatingPostProcess] freq 1200
3683 10:02:10.213389 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3684 10:02:10.216613 best DQS0 dly(2T, 0.5T) = (0, 11)
3685 10:02:10.216695 best DQS1 dly(2T, 0.5T) = (0, 11)
3686 10:02:10.219982 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3687 10:02:10.222488 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3688 10:02:10.225933 best DQS0 dly(2T, 0.5T) = (0, 11)
3689 10:02:10.229453 best DQS1 dly(2T, 0.5T) = (0, 11)
3690 10:02:10.232720 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3691 10:02:10.236042 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3692 10:02:10.239486 Pre-setting of DQS Precalculation
3693 10:02:10.245997 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3694 10:02:10.252382 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3695 10:02:10.259032 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3696 10:02:10.259133
3697 10:02:10.259232
3698 10:02:10.262172 [Calibration Summary] 2400 Mbps
3699 10:02:10.262269 CH 0, Rank 0
3700 10:02:10.265470 SW Impedance : PASS
3701 10:02:10.269070 DUTY Scan : NO K
3702 10:02:10.269147 ZQ Calibration : PASS
3703 10:02:10.272164 Jitter Meter : NO K
3704 10:02:10.275413 CBT Training : PASS
3705 10:02:10.275516 Write leveling : PASS
3706 10:02:10.278454 RX DQS gating : PASS
3707 10:02:10.281826 RX DQ/DQS(RDDQC) : PASS
3708 10:02:10.281897 TX DQ/DQS : PASS
3709 10:02:10.285533 RX DATLAT : PASS
3710 10:02:10.288536 RX DQ/DQS(Engine): PASS
3711 10:02:10.288614 TX OE : NO K
3712 10:02:10.291826 All Pass.
3713 10:02:10.291923
3714 10:02:10.292019 CH 0, Rank 1
3715 10:02:10.295360 SW Impedance : PASS
3716 10:02:10.295435 DUTY Scan : NO K
3717 10:02:10.298290 ZQ Calibration : PASS
3718 10:02:10.301373 Jitter Meter : NO K
3719 10:02:10.301449 CBT Training : PASS
3720 10:02:10.305170 Write leveling : PASS
3721 10:02:10.308166 RX DQS gating : PASS
3722 10:02:10.308262 RX DQ/DQS(RDDQC) : PASS
3723 10:02:10.311710 TX DQ/DQS : PASS
3724 10:02:10.315382 RX DATLAT : PASS
3725 10:02:10.315479 RX DQ/DQS(Engine): PASS
3726 10:02:10.317961 TX OE : NO K
3727 10:02:10.318118 All Pass.
3728 10:02:10.318183
3729 10:02:10.321240 CH 1, Rank 0
3730 10:02:10.321307 SW Impedance : PASS
3731 10:02:10.324485 DUTY Scan : NO K
3732 10:02:10.327874 ZQ Calibration : PASS
3733 10:02:10.327942 Jitter Meter : NO K
3734 10:02:10.331200 CBT Training : PASS
3735 10:02:10.331295 Write leveling : PASS
3736 10:02:10.334843 RX DQS gating : PASS
3737 10:02:10.337906 RX DQ/DQS(RDDQC) : PASS
3738 10:02:10.337979 TX DQ/DQS : PASS
3739 10:02:10.341303 RX DATLAT : PASS
3740 10:02:10.344902 RX DQ/DQS(Engine): PASS
3741 10:02:10.344982 TX OE : NO K
3742 10:02:10.348022 All Pass.
3743 10:02:10.348121
3744 10:02:10.348184 CH 1, Rank 1
3745 10:02:10.351564 SW Impedance : PASS
3746 10:02:10.351644 DUTY Scan : NO K
3747 10:02:10.354646 ZQ Calibration : PASS
3748 10:02:10.357552 Jitter Meter : NO K
3749 10:02:10.357633 CBT Training : PASS
3750 10:02:10.360998 Write leveling : PASS
3751 10:02:10.364195 RX DQS gating : PASS
3752 10:02:10.364302 RX DQ/DQS(RDDQC) : PASS
3753 10:02:10.367395 TX DQ/DQS : PASS
3754 10:02:10.370883 RX DATLAT : PASS
3755 10:02:10.370963 RX DQ/DQS(Engine): PASS
3756 10:02:10.374495 TX OE : NO K
3757 10:02:10.374576 All Pass.
3758 10:02:10.374639
3759 10:02:10.377433 DramC Write-DBI off
3760 10:02:10.380989 PER_BANK_REFRESH: Hybrid Mode
3761 10:02:10.381070 TX_TRACKING: ON
3762 10:02:10.390360 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3763 10:02:10.394065 [FAST_K] Save calibration result to emmc
3764 10:02:10.397630 dramc_set_vcore_voltage set vcore to 650000
3765 10:02:10.400410 Read voltage for 600, 5
3766 10:02:10.400489 Vio18 = 0
3767 10:02:10.400552 Vcore = 650000
3768 10:02:10.403683 Vdram = 0
3769 10:02:10.403762 Vddq = 0
3770 10:02:10.403825 Vmddr = 0
3771 10:02:10.410379 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3772 10:02:10.413742 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3773 10:02:10.416397 MEM_TYPE=3, freq_sel=19
3774 10:02:10.420191 sv_algorithm_assistance_LP4_1600
3775 10:02:10.422995 ============ PULL DRAM RESETB DOWN ============
3776 10:02:10.429738 ========== PULL DRAM RESETB DOWN end =========
3777 10:02:10.432919 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3778 10:02:10.436280 ===================================
3779 10:02:10.439623 LPDDR4 DRAM CONFIGURATION
3780 10:02:10.442714 ===================================
3781 10:02:10.442795 EX_ROW_EN[0] = 0x0
3782 10:02:10.445942 EX_ROW_EN[1] = 0x0
3783 10:02:10.446022 LP4Y_EN = 0x0
3784 10:02:10.449533 WORK_FSP = 0x0
3785 10:02:10.452683 WL = 0x2
3786 10:02:10.452763 RL = 0x2
3787 10:02:10.455823 BL = 0x2
3788 10:02:10.455903 RPST = 0x0
3789 10:02:10.459974 RD_PRE = 0x0
3790 10:02:10.460090 WR_PRE = 0x1
3791 10:02:10.462449 WR_PST = 0x0
3792 10:02:10.462529 DBI_WR = 0x0
3793 10:02:10.466287 DBI_RD = 0x0
3794 10:02:10.466367 OTF = 0x1
3795 10:02:10.469074 ===================================
3796 10:02:10.472722 ===================================
3797 10:02:10.475798 ANA top config
3798 10:02:10.479446 ===================================
3799 10:02:10.479524 DLL_ASYNC_EN = 0
3800 10:02:10.482265 ALL_SLAVE_EN = 1
3801 10:02:10.485495 NEW_RANK_MODE = 1
3802 10:02:10.489056 DLL_IDLE_MODE = 1
3803 10:02:10.492242 LP45_APHY_COMB_EN = 1
3804 10:02:10.492325 TX_ODT_DIS = 1
3805 10:02:10.495540 NEW_8X_MODE = 1
3806 10:02:10.498788 ===================================
3807 10:02:10.501973 ===================================
3808 10:02:10.505267 data_rate = 1200
3809 10:02:10.508786 CKR = 1
3810 10:02:10.511762 DQ_P2S_RATIO = 8
3811 10:02:10.515572 ===================================
3812 10:02:10.518576 CA_P2S_RATIO = 8
3813 10:02:10.518662 DQ_CA_OPEN = 0
3814 10:02:10.521557 DQ_SEMI_OPEN = 0
3815 10:02:10.524773 CA_SEMI_OPEN = 0
3816 10:02:10.528275 CA_FULL_RATE = 0
3817 10:02:10.531744 DQ_CKDIV4_EN = 1
3818 10:02:10.535125 CA_CKDIV4_EN = 1
3819 10:02:10.538470 CA_PREDIV_EN = 0
3820 10:02:10.538552 PH8_DLY = 0
3821 10:02:10.541219 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3822 10:02:10.544669 DQ_AAMCK_DIV = 4
3823 10:02:10.548067 CA_AAMCK_DIV = 4
3824 10:02:10.551559 CA_ADMCK_DIV = 4
3825 10:02:10.554613 DQ_TRACK_CA_EN = 0
3826 10:02:10.554695 CA_PICK = 600
3827 10:02:10.558254 CA_MCKIO = 600
3828 10:02:10.561127 MCKIO_SEMI = 0
3829 10:02:10.564451 PLL_FREQ = 2288
3830 10:02:10.567589 DQ_UI_PI_RATIO = 32
3831 10:02:10.571330 CA_UI_PI_RATIO = 0
3832 10:02:10.574518 ===================================
3833 10:02:10.577525 ===================================
3834 10:02:10.577607 memory_type:LPDDR4
3835 10:02:10.581084 GP_NUM : 10
3836 10:02:10.584477 SRAM_EN : 1
3837 10:02:10.584558 MD32_EN : 0
3838 10:02:10.587559 ===================================
3839 10:02:10.590988 [ANA_INIT] >>>>>>>>>>>>>>
3840 10:02:10.594862 <<<<<< [CONFIGURE PHASE]: ANA_TX
3841 10:02:10.597427 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3842 10:02:10.600751 ===================================
3843 10:02:10.604357 data_rate = 1200,PCW = 0X5800
3844 10:02:10.607128 ===================================
3845 10:02:10.610370 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3846 10:02:10.613822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3847 10:02:10.620758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3848 10:02:10.627217 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3849 10:02:10.630613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3850 10:02:10.633455 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3851 10:02:10.633537 [ANA_INIT] flow start
3852 10:02:10.637117 [ANA_INIT] PLL >>>>>>>>
3853 10:02:10.640633 [ANA_INIT] PLL <<<<<<<<
3854 10:02:10.640715 [ANA_INIT] MIDPI >>>>>>>>
3855 10:02:10.645236 [ANA_INIT] MIDPI <<<<<<<<
3856 10:02:10.646829 [ANA_INIT] DLL >>>>>>>>
3857 10:02:10.646911 [ANA_INIT] flow end
3858 10:02:10.653498 ============ LP4 DIFF to SE enter ============
3859 10:02:10.656357 ============ LP4 DIFF to SE exit ============
3860 10:02:10.660199 [ANA_INIT] <<<<<<<<<<<<<
3861 10:02:10.663233 [Flow] Enable top DCM control >>>>>
3862 10:02:10.666541 [Flow] Enable top DCM control <<<<<
3863 10:02:10.666622 Enable DLL master slave shuffle
3864 10:02:10.673352 ==============================================================
3865 10:02:10.676797 Gating Mode config
3866 10:02:10.680024 ==============================================================
3867 10:02:10.682970 Config description:
3868 10:02:10.693138 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3869 10:02:10.699524 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3870 10:02:10.702965 SELPH_MODE 0: By rank 1: By Phase
3871 10:02:10.709570 ==============================================================
3872 10:02:10.712789 GAT_TRACK_EN = 1
3873 10:02:10.716262 RX_GATING_MODE = 2
3874 10:02:10.719929 RX_GATING_TRACK_MODE = 2
3875 10:02:10.722482 SELPH_MODE = 1
3876 10:02:10.726125 PICG_EARLY_EN = 1
3877 10:02:10.726203 VALID_LAT_VALUE = 1
3878 10:02:10.732645 ==============================================================
3879 10:02:10.735658 Enter into Gating configuration >>>>
3880 10:02:10.739289 Exit from Gating configuration <<<<
3881 10:02:10.742860 Enter into DVFS_PRE_config >>>>>
3882 10:02:10.755770 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3883 10:02:10.755877 Exit from DVFS_PRE_config <<<<<
3884 10:02:10.758828 Enter into PICG configuration >>>>
3885 10:02:10.762088 Exit from PICG configuration <<<<
3886 10:02:10.765187 [RX_INPUT] configuration >>>>>
3887 10:02:10.768610 [RX_INPUT] configuration <<<<<
3888 10:02:10.775011 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3889 10:02:10.778229 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3890 10:02:10.785064 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3891 10:02:10.791468 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3892 10:02:10.797948 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3893 10:02:10.804335 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3894 10:02:10.807954 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3895 10:02:10.811816 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3896 10:02:10.818077 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3897 10:02:10.821335 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3898 10:02:10.824280 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3899 10:02:10.827661 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3900 10:02:10.831187 ===================================
3901 10:02:10.834232 LPDDR4 DRAM CONFIGURATION
3902 10:02:10.837836 ===================================
3903 10:02:10.840713 EX_ROW_EN[0] = 0x0
3904 10:02:10.840797 EX_ROW_EN[1] = 0x0
3905 10:02:10.844691 LP4Y_EN = 0x0
3906 10:02:10.844761 WORK_FSP = 0x0
3907 10:02:10.847500 WL = 0x2
3908 10:02:10.847567 RL = 0x2
3909 10:02:10.850845 BL = 0x2
3910 10:02:10.850941 RPST = 0x0
3911 10:02:10.854182 RD_PRE = 0x0
3912 10:02:10.854275 WR_PRE = 0x1
3913 10:02:10.857365 WR_PST = 0x0
3914 10:02:10.860708 DBI_WR = 0x0
3915 10:02:10.860782 DBI_RD = 0x0
3916 10:02:10.863857 OTF = 0x1
3917 10:02:10.867112 ===================================
3918 10:02:10.870515 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3919 10:02:10.873783 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3920 10:02:10.877372 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3921 10:02:10.880482 ===================================
3922 10:02:10.883682 LPDDR4 DRAM CONFIGURATION
3923 10:02:10.887299 ===================================
3924 10:02:10.890020 EX_ROW_EN[0] = 0x10
3925 10:02:10.890087 EX_ROW_EN[1] = 0x0
3926 10:02:10.893259 LP4Y_EN = 0x0
3927 10:02:10.893330 WORK_FSP = 0x0
3928 10:02:10.896877 WL = 0x2
3929 10:02:10.900004 RL = 0x2
3930 10:02:10.900077 BL = 0x2
3931 10:02:10.903172 RPST = 0x0
3932 10:02:10.903253 RD_PRE = 0x0
3933 10:02:10.906502 WR_PRE = 0x1
3934 10:02:10.906583 WR_PST = 0x0
3935 10:02:10.909825 DBI_WR = 0x0
3936 10:02:10.909906 DBI_RD = 0x0
3937 10:02:10.913792 OTF = 0x1
3938 10:02:10.916628 ===================================
3939 10:02:10.923194 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3940 10:02:10.926174 nWR fixed to 30
3941 10:02:10.926255 [ModeRegInit_LP4] CH0 RK0
3942 10:02:10.929624 [ModeRegInit_LP4] CH0 RK1
3943 10:02:10.933254 [ModeRegInit_LP4] CH1 RK0
3944 10:02:10.936022 [ModeRegInit_LP4] CH1 RK1
3945 10:02:10.936137 match AC timing 17
3946 10:02:10.942622 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3947 10:02:10.946474 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3948 10:02:10.949458 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3949 10:02:10.955812 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3950 10:02:10.959535 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3951 10:02:10.959616 ==
3952 10:02:10.962410 Dram Type= 6, Freq= 0, CH_0, rank 0
3953 10:02:10.965966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3954 10:02:10.966047 ==
3955 10:02:10.972178 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3956 10:02:10.979046 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3957 10:02:10.982625 [CA 0] Center 36 (6~67) winsize 62
3958 10:02:10.985581 [CA 1] Center 36 (6~67) winsize 62
3959 10:02:10.989124 [CA 2] Center 34 (4~65) winsize 62
3960 10:02:10.992158 [CA 3] Center 34 (4~65) winsize 62
3961 10:02:10.995249 [CA 4] Center 33 (3~64) winsize 62
3962 10:02:10.998676 [CA 5] Center 33 (3~64) winsize 62
3963 10:02:10.998757
3964 10:02:11.002410 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3965 10:02:11.002491
3966 10:02:11.005443 [CATrainingPosCal] consider 1 rank data
3967 10:02:11.008353 u2DelayCellTimex100 = 270/100 ps
3968 10:02:11.011724 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3969 10:02:11.015166 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3970 10:02:11.018174 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3971 10:02:11.021999 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3972 10:02:11.025374 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3973 10:02:11.031441 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3974 10:02:11.031522
3975 10:02:11.034795 CA PerBit enable=1, Macro0, CA PI delay=33
3976 10:02:11.034877
3977 10:02:11.038348 [CBTSetCACLKResult] CA Dly = 33
3978 10:02:11.038429 CS Dly: 5 (0~36)
3979 10:02:11.038492 ==
3980 10:02:11.041529 Dram Type= 6, Freq= 0, CH_0, rank 1
3981 10:02:11.044958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 10:02:11.048055 ==
3983 10:02:11.051253 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3984 10:02:11.058172 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3985 10:02:11.061230 [CA 0] Center 36 (6~67) winsize 62
3986 10:02:11.064441 [CA 1] Center 36 (6~67) winsize 62
3987 10:02:11.067524 [CA 2] Center 34 (4~65) winsize 62
3988 10:02:11.071171 [CA 3] Center 34 (4~65) winsize 62
3989 10:02:11.074267 [CA 4] Center 33 (3~64) winsize 62
3990 10:02:11.077563 [CA 5] Center 33 (3~64) winsize 62
3991 10:02:11.077645
3992 10:02:11.081135 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3993 10:02:11.081217
3994 10:02:11.083984 [CATrainingPosCal] consider 2 rank data
3995 10:02:11.087573 u2DelayCellTimex100 = 270/100 ps
3996 10:02:11.090785 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3997 10:02:11.094109 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3998 10:02:11.100841 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3999 10:02:11.103966 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4000 10:02:11.106939 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4001 10:02:11.110462 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4002 10:02:11.110544
4003 10:02:11.113870 CA PerBit enable=1, Macro0, CA PI delay=33
4004 10:02:11.113952
4005 10:02:11.116890 [CBTSetCACLKResult] CA Dly = 33
4006 10:02:11.120183 CS Dly: 5 (0~36)
4007 10:02:11.120265
4008 10:02:11.123506 ----->DramcWriteLeveling(PI) begin...
4009 10:02:11.123589 ==
4010 10:02:11.126920 Dram Type= 6, Freq= 0, CH_0, rank 0
4011 10:02:11.130101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 10:02:11.130183 ==
4013 10:02:11.134207 Write leveling (Byte 0): 33 => 33
4014 10:02:11.137053 Write leveling (Byte 1): 29 => 29
4015 10:02:11.139989 DramcWriteLeveling(PI) end<-----
4016 10:02:11.140107
4017 10:02:11.140177 ==
4018 10:02:11.143131 Dram Type= 6, Freq= 0, CH_0, rank 0
4019 10:02:11.146649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4020 10:02:11.146731 ==
4021 10:02:11.149784 [Gating] SW mode calibration
4022 10:02:11.156527 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4023 10:02:11.162879 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4024 10:02:11.166480 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 10:02:11.169447 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 10:02:11.176598 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4027 10:02:11.179513 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
4028 10:02:11.182574 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
4029 10:02:11.189653 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 10:02:11.192692 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 10:02:11.195637 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 10:02:11.202504 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 10:02:11.206141 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 10:02:11.209073 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 10:02:11.215574 0 10 12 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
4036 10:02:11.218836 0 10 16 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
4037 10:02:11.222229 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 10:02:11.228983 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 10:02:11.232489 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 10:02:11.235747 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 10:02:11.241861 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 10:02:11.245124 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 10:02:11.248592 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 10:02:11.255408 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4045 10:02:11.258569 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 10:02:11.262327 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 10:02:11.268460 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 10:02:11.271446 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 10:02:11.275812 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 10:02:11.281886 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 10:02:11.284785 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 10:02:11.288256 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 10:02:11.294883 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 10:02:11.298096 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 10:02:11.301602 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 10:02:11.307879 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 10:02:11.311057 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 10:02:11.314218 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 10:02:11.320764 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 10:02:11.324026 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 10:02:11.327388 Total UI for P1: 0, mck2ui 16
4062 10:02:11.330913 best dqsien dly found for B0: ( 0, 13, 14)
4063 10:02:11.333945 Total UI for P1: 0, mck2ui 16
4064 10:02:11.337158 best dqsien dly found for B1: ( 0, 13, 14)
4065 10:02:11.341112 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4066 10:02:11.344070 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4067 10:02:11.344152
4068 10:02:11.350808 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4069 10:02:11.353777 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4070 10:02:11.353860 [Gating] SW calibration Done
4071 10:02:11.357002 ==
4072 10:02:11.357084 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 10:02:11.363607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 10:02:11.363705 ==
4075 10:02:11.363770 RX Vref Scan: 0
4076 10:02:11.363830
4077 10:02:11.367167 RX Vref 0 -> 0, step: 1
4078 10:02:11.367249
4079 10:02:11.370616 RX Delay -230 -> 252, step: 16
4080 10:02:11.373852 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4081 10:02:11.377621 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4082 10:02:11.383843 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4083 10:02:11.387638 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4084 10:02:11.390966 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4085 10:02:11.393457 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4086 10:02:11.400114 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4087 10:02:11.403191 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4088 10:02:11.406834 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4089 10:02:11.409823 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4090 10:02:11.413131 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4091 10:02:11.420127 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4092 10:02:11.423389 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4093 10:02:11.426579 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4094 10:02:11.433071 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4095 10:02:11.436709 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4096 10:02:11.436859 ==
4097 10:02:11.439314 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 10:02:11.442835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 10:02:11.442918 ==
4100 10:02:11.445885 DQS Delay:
4101 10:02:11.445967 DQS0 = 0, DQS1 = 0
4102 10:02:11.446032 DQM Delay:
4103 10:02:11.449511 DQM0 = 45, DQM1 = 35
4104 10:02:11.449619 DQ Delay:
4105 10:02:11.452251 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4106 10:02:11.455890 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4107 10:02:11.459088 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =33
4108 10:02:11.462279 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4109 10:02:11.462361
4110 10:02:11.462425
4111 10:02:11.462485 ==
4112 10:02:11.465892 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 10:02:11.472152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 10:02:11.472235 ==
4115 10:02:11.472300
4116 10:02:11.472360
4117 10:02:11.472417 TX Vref Scan disable
4118 10:02:11.476338 == TX Byte 0 ==
4119 10:02:11.479708 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4120 10:02:11.486179 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4121 10:02:11.486261 == TX Byte 1 ==
4122 10:02:11.489330 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4123 10:02:11.496345 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4124 10:02:11.496427 ==
4125 10:02:11.498861 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 10:02:11.502402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 10:02:11.502485 ==
4128 10:02:11.502549
4129 10:02:11.502608
4130 10:02:11.505556 TX Vref Scan disable
4131 10:02:11.509142 == TX Byte 0 ==
4132 10:02:11.511851 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4133 10:02:11.515373 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4134 10:02:11.519109 == TX Byte 1 ==
4135 10:02:11.522360 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4136 10:02:11.525374 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4137 10:02:11.525456
4138 10:02:11.528855 [DATLAT]
4139 10:02:11.528936 Freq=600, CH0 RK0
4140 10:02:11.529001
4141 10:02:11.532269 DATLAT Default: 0x9
4142 10:02:11.532351 0, 0xFFFF, sum = 0
4143 10:02:11.535208 1, 0xFFFF, sum = 0
4144 10:02:11.535290 2, 0xFFFF, sum = 0
4145 10:02:11.538641 3, 0xFFFF, sum = 0
4146 10:02:11.538730 4, 0xFFFF, sum = 0
4147 10:02:11.541793 5, 0xFFFF, sum = 0
4148 10:02:11.541876 6, 0xFFFF, sum = 0
4149 10:02:11.545213 7, 0xFFFF, sum = 0
4150 10:02:11.545295 8, 0x0, sum = 1
4151 10:02:11.548269 9, 0x0, sum = 2
4152 10:02:11.548352 10, 0x0, sum = 3
4153 10:02:11.551488 11, 0x0, sum = 4
4154 10:02:11.551576 best_step = 9
4155 10:02:11.551641
4156 10:02:11.551701 ==
4157 10:02:11.554900 Dram Type= 6, Freq= 0, CH_0, rank 0
4158 10:02:11.561358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 10:02:11.561441 ==
4160 10:02:11.561505 RX Vref Scan: 1
4161 10:02:11.561565
4162 10:02:11.564638 RX Vref 0 -> 0, step: 1
4163 10:02:11.564721
4164 10:02:11.568481 RX Delay -195 -> 252, step: 8
4165 10:02:11.568588
4166 10:02:11.571361 Set Vref, RX VrefLevel [Byte0]: 54
4167 10:02:11.574432 [Byte1]: 59
4168 10:02:11.574514
4169 10:02:11.578068 Final RX Vref Byte 0 = 54 to rank0
4170 10:02:11.580975 Final RX Vref Byte 1 = 59 to rank0
4171 10:02:11.584345 Final RX Vref Byte 0 = 54 to rank1
4172 10:02:11.587983 Final RX Vref Byte 1 = 59 to rank1==
4173 10:02:11.591617 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 10:02:11.594448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 10:02:11.594531 ==
4176 10:02:11.597508 DQS Delay:
4177 10:02:11.597595 DQS0 = 0, DQS1 = 0
4178 10:02:11.597660 DQM Delay:
4179 10:02:11.600701 DQM0 = 41, DQM1 = 33
4180 10:02:11.600783 DQ Delay:
4181 10:02:11.603953 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4182 10:02:11.607222 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4183 10:02:11.610528 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4184 10:02:11.614020 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4185 10:02:11.614102
4186 10:02:11.614166
4187 10:02:11.623850 [DQSOSCAuto] RK0, (LSB)MR18= 0x483f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4188 10:02:11.627460 CH0 RK0: MR19=808, MR18=483F
4189 10:02:11.633804 CH0_RK0: MR19=0x808, MR18=0x483F, DQSOSC=396, MR23=63, INC=167, DEC=111
4190 10:02:11.633886
4191 10:02:11.636892 ----->DramcWriteLeveling(PI) begin...
4192 10:02:11.636976 ==
4193 10:02:11.640543 Dram Type= 6, Freq= 0, CH_0, rank 1
4194 10:02:11.643554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 10:02:11.643636 ==
4196 10:02:11.646937 Write leveling (Byte 0): 33 => 33
4197 10:02:11.650156 Write leveling (Byte 1): 30 => 30
4198 10:02:11.653399 DramcWriteLeveling(PI) end<-----
4199 10:02:11.653481
4200 10:02:11.653545 ==
4201 10:02:11.657356 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 10:02:11.660170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 10:02:11.660253 ==
4204 10:02:11.663333 [Gating] SW mode calibration
4205 10:02:11.670129 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4206 10:02:11.676270 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4207 10:02:11.679870 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 10:02:11.683196 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 10:02:11.689926 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4210 10:02:11.693067 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (0 0) (1 1)
4211 10:02:11.696482 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
4212 10:02:11.703374 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 10:02:11.706130 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 10:02:11.709650 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 10:02:11.716464 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 10:02:11.719311 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 10:02:11.722581 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 10:02:11.729609 0 10 12 | B1->B0 | 2828 3232 | 0 0 | (0 0) (0 0)
4219 10:02:11.732950 0 10 16 | B1->B0 | 3e3e 4545 | 0 1 | (0 0) (0 0)
4220 10:02:11.735864 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 10:02:11.742773 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 10:02:11.745785 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 10:02:11.749285 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 10:02:11.755689 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 10:02:11.759577 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 10:02:11.762700 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4227 10:02:11.768918 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4228 10:02:11.772155 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 10:02:11.775884 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 10:02:11.782464 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 10:02:11.785486 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 10:02:11.788666 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 10:02:11.795480 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 10:02:11.798945 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 10:02:11.801847 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 10:02:11.808681 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 10:02:11.811881 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 10:02:11.815225 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 10:02:11.821691 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 10:02:11.825569 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 10:02:11.828338 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 10:02:11.835315 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 10:02:11.838425 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 10:02:11.841325 Total UI for P1: 0, mck2ui 16
4245 10:02:11.844954 best dqsien dly found for B0: ( 0, 13, 14)
4246 10:02:11.847925 Total UI for P1: 0, mck2ui 16
4247 10:02:11.851472 best dqsien dly found for B1: ( 0, 13, 14)
4248 10:02:11.855026 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4249 10:02:11.857732 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4250 10:02:11.857814
4251 10:02:11.861081 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4252 10:02:11.867649 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4253 10:02:11.867732 [Gating] SW calibration Done
4254 10:02:11.867828 ==
4255 10:02:11.871643 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 10:02:11.877543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 10:02:11.877625 ==
4258 10:02:11.877690 RX Vref Scan: 0
4259 10:02:11.877750
4260 10:02:11.880898 RX Vref 0 -> 0, step: 1
4261 10:02:11.880979
4262 10:02:11.884515 RX Delay -230 -> 252, step: 16
4263 10:02:11.887332 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4264 10:02:11.890635 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4265 10:02:11.897414 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4266 10:02:11.901100 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4267 10:02:11.903899 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4268 10:02:11.907579 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4269 10:02:11.910737 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4270 10:02:11.917109 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4271 10:02:11.920672 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4272 10:02:11.923633 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4273 10:02:11.926939 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4274 10:02:11.933880 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4275 10:02:11.936810 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4276 10:02:11.940689 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4277 10:02:11.943753 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4278 10:02:11.950747 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4279 10:02:11.950829 ==
4280 10:02:11.953435 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 10:02:11.956688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 10:02:11.956771 ==
4283 10:02:11.956836 DQS Delay:
4284 10:02:11.959856 DQS0 = 0, DQS1 = 0
4285 10:02:11.959937 DQM Delay:
4286 10:02:11.963390 DQM0 = 42, DQM1 = 35
4287 10:02:11.963472 DQ Delay:
4288 10:02:11.966669 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4289 10:02:11.969932 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4290 10:02:11.973636 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4291 10:02:11.976470 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4292 10:02:11.976552
4293 10:02:11.976615
4294 10:02:11.976675 ==
4295 10:02:11.979859 Dram Type= 6, Freq= 0, CH_0, rank 1
4296 10:02:11.983056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4297 10:02:11.986244 ==
4298 10:02:11.986325
4299 10:02:11.986389
4300 10:02:11.986448 TX Vref Scan disable
4301 10:02:11.989827 == TX Byte 0 ==
4302 10:02:11.992917 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4303 10:02:11.999967 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4304 10:02:12.000080 == TX Byte 1 ==
4305 10:02:12.003154 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4306 10:02:12.009723 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4307 10:02:12.009806 ==
4308 10:02:12.013253 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 10:02:12.015773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 10:02:12.015856 ==
4311 10:02:12.015920
4312 10:02:12.015980
4313 10:02:12.019316 TX Vref Scan disable
4314 10:02:12.022709 == TX Byte 0 ==
4315 10:02:12.026130 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4316 10:02:12.029378 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4317 10:02:12.032599 == TX Byte 1 ==
4318 10:02:12.035835 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4319 10:02:12.039284 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4320 10:02:12.039366
4321 10:02:12.042816 [DATLAT]
4322 10:02:12.042898 Freq=600, CH0 RK1
4323 10:02:12.042963
4324 10:02:12.045550 DATLAT Default: 0x9
4325 10:02:12.045631 0, 0xFFFF, sum = 0
4326 10:02:12.049278 1, 0xFFFF, sum = 0
4327 10:02:12.049361 2, 0xFFFF, sum = 0
4328 10:02:12.052414 3, 0xFFFF, sum = 0
4329 10:02:12.052497 4, 0xFFFF, sum = 0
4330 10:02:12.055703 5, 0xFFFF, sum = 0
4331 10:02:12.055812 6, 0xFFFF, sum = 0
4332 10:02:12.058690 7, 0xFFFF, sum = 0
4333 10:02:12.058773 8, 0x0, sum = 1
4334 10:02:12.062083 9, 0x0, sum = 2
4335 10:02:12.062166 10, 0x0, sum = 3
4336 10:02:12.065492 11, 0x0, sum = 4
4337 10:02:12.065574 best_step = 9
4338 10:02:12.065639
4339 10:02:12.065698 ==
4340 10:02:12.068677 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 10:02:12.072404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 10:02:12.075253 ==
4343 10:02:12.075335 RX Vref Scan: 0
4344 10:02:12.075400
4345 10:02:12.078471 RX Vref 0 -> 0, step: 1
4346 10:02:12.078577
4347 10:02:12.082001 RX Delay -179 -> 252, step: 8
4348 10:02:12.086461 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4349 10:02:12.088644 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4350 10:02:12.095036 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4351 10:02:12.098069 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4352 10:02:12.101270 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4353 10:02:12.104926 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4354 10:02:12.111596 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4355 10:02:12.114812 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4356 10:02:12.118195 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4357 10:02:12.121383 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4358 10:02:12.127773 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4359 10:02:12.131059 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4360 10:02:12.134138 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4361 10:02:12.137563 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4362 10:02:12.144151 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4363 10:02:12.147549 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4364 10:02:12.147622 ==
4365 10:02:12.150953 Dram Type= 6, Freq= 0, CH_0, rank 1
4366 10:02:12.153975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 10:02:12.154077 ==
4368 10:02:12.157469 DQS Delay:
4369 10:02:12.157568 DQS0 = 0, DQS1 = 0
4370 10:02:12.160816 DQM Delay:
4371 10:02:12.160886 DQM0 = 40, DQM1 = 33
4372 10:02:12.160944 DQ Delay:
4373 10:02:12.164077 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4374 10:02:12.167025 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =44
4375 10:02:12.170637 DQ8 =24, DQ9 =16, DQ10 =40, DQ11 =24
4376 10:02:12.173559 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4377 10:02:12.173628
4378 10:02:12.173685
4379 10:02:12.183838 [DQSOSCAuto] RK1, (LSB)MR18= 0x423c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4380 10:02:12.187285 CH0 RK1: MR19=808, MR18=423C
4381 10:02:12.194003 CH0_RK1: MR19=0x808, MR18=0x423C, DQSOSC=397, MR23=63, INC=166, DEC=110
4382 10:02:12.194075 [RxdqsGatingPostProcess] freq 600
4383 10:02:12.200189 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4384 10:02:12.203365 Pre-setting of DQS Precalculation
4385 10:02:12.207450 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4386 10:02:12.210104 ==
4387 10:02:12.213468 Dram Type= 6, Freq= 0, CH_1, rank 0
4388 10:02:12.216516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 10:02:12.216611 ==
4390 10:02:12.223063 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4391 10:02:12.226320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4392 10:02:12.230604 [CA 0] Center 35 (5~66) winsize 62
4393 10:02:12.233467 [CA 1] Center 35 (5~66) winsize 62
4394 10:02:12.237366 [CA 2] Center 34 (4~65) winsize 62
4395 10:02:12.240284 [CA 3] Center 34 (3~65) winsize 63
4396 10:02:12.243527 [CA 4] Center 34 (4~65) winsize 62
4397 10:02:12.247332 [CA 5] Center 34 (3~65) winsize 63
4398 10:02:12.247405
4399 10:02:12.249912 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4400 10:02:12.249979
4401 10:02:12.253611 [CATrainingPosCal] consider 1 rank data
4402 10:02:12.257005 u2DelayCellTimex100 = 270/100 ps
4403 10:02:12.259825 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4404 10:02:12.266809 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4405 10:02:12.269969 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4406 10:02:12.273139 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4407 10:02:12.276345 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4408 10:02:12.279669 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4409 10:02:12.279738
4410 10:02:12.282973 CA PerBit enable=1, Macro0, CA PI delay=34
4411 10:02:12.283042
4412 10:02:12.286515 [CBTSetCACLKResult] CA Dly = 34
4413 10:02:12.289493 CS Dly: 4 (0~35)
4414 10:02:12.289564 ==
4415 10:02:12.292951 Dram Type= 6, Freq= 0, CH_1, rank 1
4416 10:02:12.296349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 10:02:12.296420 ==
4418 10:02:12.303288 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4419 10:02:12.306180 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4420 10:02:12.310114 [CA 0] Center 35 (5~66) winsize 62
4421 10:02:12.313716 [CA 1] Center 35 (5~66) winsize 62
4422 10:02:12.316916 [CA 2] Center 34 (4~65) winsize 62
4423 10:02:12.320111 [CA 3] Center 34 (3~65) winsize 63
4424 10:02:12.323502 [CA 4] Center 34 (4~65) winsize 62
4425 10:02:12.327111 [CA 5] Center 33 (3~64) winsize 62
4426 10:02:12.327182
4427 10:02:12.330225 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4428 10:02:12.330320
4429 10:02:12.333465 [CATrainingPosCal] consider 2 rank data
4430 10:02:12.337313 u2DelayCellTimex100 = 270/100 ps
4431 10:02:12.340221 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4432 10:02:12.346666 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4433 10:02:12.350126 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4434 10:02:12.353043 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4435 10:02:12.357070 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4436 10:02:12.360288 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4437 10:02:12.360369
4438 10:02:12.363620 CA PerBit enable=1, Macro0, CA PI delay=33
4439 10:02:12.363701
4440 10:02:12.366469 [CBTSetCACLKResult] CA Dly = 33
4441 10:02:12.369837 CS Dly: 4 (0~36)
4442 10:02:12.369917
4443 10:02:12.373114 ----->DramcWriteLeveling(PI) begin...
4444 10:02:12.373197 ==
4445 10:02:12.376273 Dram Type= 6, Freq= 0, CH_1, rank 0
4446 10:02:12.379767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4447 10:02:12.379849 ==
4448 10:02:12.383039 Write leveling (Byte 0): 29 => 29
4449 10:02:12.386631 Write leveling (Byte 1): 29 => 29
4450 10:02:12.389798 DramcWriteLeveling(PI) end<-----
4451 10:02:12.389884
4452 10:02:12.389952 ==
4453 10:02:12.392999 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 10:02:12.396227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 10:02:12.396309 ==
4456 10:02:12.399652 [Gating] SW mode calibration
4457 10:02:12.406522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4458 10:02:12.412992 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4459 10:02:12.415702 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4460 10:02:12.419045 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4461 10:02:12.426081 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4462 10:02:12.429330 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (1 1) (1 1)
4463 10:02:12.432258 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 10:02:12.439118 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 10:02:12.442797 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 10:02:12.445496 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 10:02:12.452761 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 10:02:12.455816 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 10:02:12.458670 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4470 10:02:12.465572 0 10 12 | B1->B0 | 3030 3636 | 0 1 | (0 0) (0 0)
4471 10:02:12.468694 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 10:02:12.471648 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 10:02:12.478391 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 10:02:12.481866 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 10:02:12.485150 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 10:02:12.491715 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 10:02:12.495008 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 10:02:12.498219 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 10:02:12.504703 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 10:02:12.507948 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 10:02:12.511203 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 10:02:12.517826 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 10:02:12.521280 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 10:02:12.524604 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 10:02:12.530958 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 10:02:12.534557 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 10:02:12.537306 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 10:02:12.544153 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 10:02:12.547422 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 10:02:12.554005 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 10:02:12.557197 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 10:02:12.560709 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 10:02:12.564384 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 10:02:12.570544 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4495 10:02:12.574089 Total UI for P1: 0, mck2ui 16
4496 10:02:12.577555 best dqsien dly found for B0: ( 0, 13, 10)
4497 10:02:12.581008 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 10:02:12.583753 Total UI for P1: 0, mck2ui 16
4499 10:02:12.586838 best dqsien dly found for B1: ( 0, 13, 12)
4500 10:02:12.590665 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4501 10:02:12.593388 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4502 10:02:12.593470
4503 10:02:12.597454 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4504 10:02:12.603273 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4505 10:02:12.603356 [Gating] SW calibration Done
4506 10:02:12.606700 ==
4507 10:02:12.606782 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 10:02:12.613644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 10:02:12.613727 ==
4510 10:02:12.613791 RX Vref Scan: 0
4511 10:02:12.613852
4512 10:02:12.617096 RX Vref 0 -> 0, step: 1
4513 10:02:12.617191
4514 10:02:12.620180 RX Delay -230 -> 252, step: 16
4515 10:02:12.623492 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4516 10:02:12.626561 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4517 10:02:12.633178 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4518 10:02:12.636448 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4519 10:02:12.639999 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4520 10:02:12.643088 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4521 10:02:12.649299 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4522 10:02:12.652839 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4523 10:02:12.655804 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4524 10:02:12.659162 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4525 10:02:12.665866 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4526 10:02:12.670231 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4527 10:02:12.672401 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4528 10:02:12.676044 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4529 10:02:12.682375 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4530 10:02:12.685768 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4531 10:02:12.685850 ==
4532 10:02:12.688815 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 10:02:12.692547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 10:02:12.692629 ==
4535 10:02:12.696122 DQS Delay:
4536 10:02:12.696203 DQS0 = 0, DQS1 = 0
4537 10:02:12.696267 DQM Delay:
4538 10:02:12.698728 DQM0 = 43, DQM1 = 38
4539 10:02:12.698816 DQ Delay:
4540 10:02:12.702044 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4541 10:02:12.705751 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4542 10:02:12.708805 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4543 10:02:12.711950 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4544 10:02:12.712056
4545 10:02:12.712135
4546 10:02:12.712195 ==
4547 10:02:12.715561 Dram Type= 6, Freq= 0, CH_1, rank 0
4548 10:02:12.721960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4549 10:02:12.722042 ==
4550 10:02:12.722107
4551 10:02:12.722176
4552 10:02:12.722234 TX Vref Scan disable
4553 10:02:12.725437 == TX Byte 0 ==
4554 10:02:12.728677 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4555 10:02:12.735842 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4556 10:02:12.735924 == TX Byte 1 ==
4557 10:02:12.738975 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4558 10:02:12.745650 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4559 10:02:12.745732 ==
4560 10:02:12.748667 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 10:02:12.751977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 10:02:12.752120 ==
4563 10:02:12.752218
4564 10:02:12.752284
4565 10:02:12.755171 TX Vref Scan disable
4566 10:02:12.758744 == TX Byte 0 ==
4567 10:02:12.761525 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4568 10:02:12.764849 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4569 10:02:12.768313 == TX Byte 1 ==
4570 10:02:12.771653 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4571 10:02:12.775359 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4572 10:02:12.775440
4573 10:02:12.778592 [DATLAT]
4574 10:02:12.778674 Freq=600, CH1 RK0
4575 10:02:12.778738
4576 10:02:12.781236 DATLAT Default: 0x9
4577 10:02:12.781317 0, 0xFFFF, sum = 0
4578 10:02:12.784766 1, 0xFFFF, sum = 0
4579 10:02:12.784854 2, 0xFFFF, sum = 0
4580 10:02:12.787742 3, 0xFFFF, sum = 0
4581 10:02:12.787851 4, 0xFFFF, sum = 0
4582 10:02:12.791356 5, 0xFFFF, sum = 0
4583 10:02:12.791439 6, 0xFFFF, sum = 0
4584 10:02:12.794992 7, 0xFFFF, sum = 0
4585 10:02:12.795075 8, 0x0, sum = 1
4586 10:02:12.798112 9, 0x0, sum = 2
4587 10:02:12.798195 10, 0x0, sum = 3
4588 10:02:12.801090 11, 0x0, sum = 4
4589 10:02:12.801173 best_step = 9
4590 10:02:12.801236
4591 10:02:12.801296 ==
4592 10:02:12.804990 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 10:02:12.807625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 10:02:12.811545 ==
4595 10:02:12.811626 RX Vref Scan: 1
4596 10:02:12.811691
4597 10:02:12.814696 RX Vref 0 -> 0, step: 1
4598 10:02:12.814782
4599 10:02:12.817382 RX Delay -179 -> 252, step: 8
4600 10:02:12.817465
4601 10:02:12.820977 Set Vref, RX VrefLevel [Byte0]: 52
4602 10:02:12.824370 [Byte1]: 53
4603 10:02:12.824452
4604 10:02:12.827111 Final RX Vref Byte 0 = 52 to rank0
4605 10:02:12.831116 Final RX Vref Byte 1 = 53 to rank0
4606 10:02:12.834442 Final RX Vref Byte 0 = 52 to rank1
4607 10:02:12.837236 Final RX Vref Byte 1 = 53 to rank1==
4608 10:02:12.840623 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 10:02:12.843443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 10:02:12.843525 ==
4611 10:02:12.847136 DQS Delay:
4612 10:02:12.847218 DQS0 = 0, DQS1 = 0
4613 10:02:12.847283 DQM Delay:
4614 10:02:12.849987 DQM0 = 41, DQM1 = 35
4615 10:02:12.850069 DQ Delay:
4616 10:02:12.853476 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4617 10:02:12.856530 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4618 10:02:12.860137 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4619 10:02:12.863549 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4620 10:02:12.863631
4621 10:02:12.863695
4622 10:02:12.873196 [DQSOSCAuto] RK0, (LSB)MR18= 0x334c, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4623 10:02:12.876146 CH1 RK0: MR19=808, MR18=334C
4624 10:02:12.882754 CH1_RK0: MR19=0x808, MR18=0x334C, DQSOSC=395, MR23=63, INC=168, DEC=112
4625 10:02:12.882836
4626 10:02:12.886091 ----->DramcWriteLeveling(PI) begin...
4627 10:02:12.886175 ==
4628 10:02:12.890226 Dram Type= 6, Freq= 0, CH_1, rank 1
4629 10:02:12.892685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 10:02:12.892772 ==
4631 10:02:12.896040 Write leveling (Byte 0): 28 => 28
4632 10:02:12.899216 Write leveling (Byte 1): 29 => 29
4633 10:02:12.902576 DramcWriteLeveling(PI) end<-----
4634 10:02:12.902658
4635 10:02:12.902722 ==
4636 10:02:12.906539 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 10:02:12.909003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 10:02:12.909086 ==
4639 10:02:12.912679 [Gating] SW mode calibration
4640 10:02:12.919169 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4641 10:02:12.925575 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4642 10:02:12.928891 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4643 10:02:12.935435 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4644 10:02:12.939271 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4645 10:02:12.942027 0 9 12 | B1->B0 | 2f2f 2b2b | 1 1 | (1 1) (0 1)
4646 10:02:12.948524 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 10:02:12.952195 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 10:02:12.955183 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 10:02:12.962036 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 10:02:12.964968 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 10:02:12.968700 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 10:02:12.974993 0 10 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4653 10:02:12.978313 0 10 12 | B1->B0 | 2626 3b3b | 0 1 | (0 0) (0 0)
4654 10:02:12.981395 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4655 10:02:12.988349 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 10:02:12.991276 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 10:02:12.994565 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 10:02:13.001182 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 10:02:13.004488 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 10:02:13.007659 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 10:02:13.014401 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4662 10:02:13.017697 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 10:02:13.021071 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 10:02:13.027545 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 10:02:13.031244 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 10:02:13.034124 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 10:02:13.040588 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 10:02:13.044028 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 10:02:13.047489 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 10:02:13.053638 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 10:02:13.057108 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 10:02:13.060737 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 10:02:13.066769 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 10:02:13.070136 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 10:02:13.073529 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 10:02:13.080196 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4677 10:02:13.083152 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 10:02:13.086929 Total UI for P1: 0, mck2ui 16
4679 10:02:13.089837 best dqsien dly found for B0: ( 0, 13, 8)
4680 10:02:13.093341 Total UI for P1: 0, mck2ui 16
4681 10:02:13.097548 best dqsien dly found for B1: ( 0, 13, 10)
4682 10:02:13.100489 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4683 10:02:13.103296 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4684 10:02:13.103378
4685 10:02:13.106325 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4686 10:02:13.109797 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4687 10:02:13.112776 [Gating] SW calibration Done
4688 10:02:13.112858 ==
4689 10:02:13.116182 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 10:02:13.122872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 10:02:13.122954 ==
4692 10:02:13.123019 RX Vref Scan: 0
4693 10:02:13.123080
4694 10:02:13.126202 RX Vref 0 -> 0, step: 1
4695 10:02:13.126284
4696 10:02:13.129294 RX Delay -230 -> 252, step: 16
4697 10:02:13.133203 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4698 10:02:13.136596 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4699 10:02:13.139274 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4700 10:02:13.147223 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4701 10:02:13.149215 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4702 10:02:13.152898 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4703 10:02:13.156175 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4704 10:02:13.162598 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4705 10:02:13.166198 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4706 10:02:13.168986 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4707 10:02:13.172762 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4708 10:02:13.175514 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4709 10:02:13.182581 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4710 10:02:13.185659 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4711 10:02:13.188985 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4712 10:02:13.195195 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4713 10:02:13.195277 ==
4714 10:02:13.198413 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 10:02:13.201786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 10:02:13.201868 ==
4717 10:02:13.201932 DQS Delay:
4718 10:02:13.205222 DQS0 = 0, DQS1 = 0
4719 10:02:13.205373 DQM Delay:
4720 10:02:13.208345 DQM0 = 42, DQM1 = 39
4721 10:02:13.208427 DQ Delay:
4722 10:02:13.211779 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4723 10:02:13.215103 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4724 10:02:13.218550 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4725 10:02:13.221725 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4726 10:02:13.221837
4727 10:02:13.221905
4728 10:02:13.221965 ==
4729 10:02:13.224886 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 10:02:13.228300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 10:02:13.228383 ==
4732 10:02:13.231445
4733 10:02:13.231539
4734 10:02:13.231604 TX Vref Scan disable
4735 10:02:13.234823 == TX Byte 0 ==
4736 10:02:13.237799 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4737 10:02:13.241593 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4738 10:02:13.244497 == TX Byte 1 ==
4739 10:02:13.248288 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4740 10:02:13.251483 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4741 10:02:13.254456 ==
4742 10:02:13.257644 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 10:02:13.260808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 10:02:13.260903 ==
4745 10:02:13.260972
4746 10:02:13.261033
4747 10:02:13.264413 TX Vref Scan disable
4748 10:02:13.267486 == TX Byte 0 ==
4749 10:02:13.270969 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4750 10:02:13.273979 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4751 10:02:13.277284 == TX Byte 1 ==
4752 10:02:13.280577 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4753 10:02:13.284497 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4754 10:02:13.284579
4755 10:02:13.284652 [DATLAT]
4756 10:02:13.287192 Freq=600, CH1 RK1
4757 10:02:13.287274
4758 10:02:13.290929 DATLAT Default: 0x9
4759 10:02:13.291011 0, 0xFFFF, sum = 0
4760 10:02:13.294261 1, 0xFFFF, sum = 0
4761 10:02:13.294344 2, 0xFFFF, sum = 0
4762 10:02:13.297351 3, 0xFFFF, sum = 0
4763 10:02:13.297434 4, 0xFFFF, sum = 0
4764 10:02:13.300278 5, 0xFFFF, sum = 0
4765 10:02:13.300361 6, 0xFFFF, sum = 0
4766 10:02:13.303455 7, 0xFFFF, sum = 0
4767 10:02:13.303538 8, 0x0, sum = 1
4768 10:02:13.307397 9, 0x0, sum = 2
4769 10:02:13.307512 10, 0x0, sum = 3
4770 10:02:13.310173 11, 0x0, sum = 4
4771 10:02:13.310255 best_step = 9
4772 10:02:13.310320
4773 10:02:13.310379 ==
4774 10:02:13.313524 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 10:02:13.316895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 10:02:13.316978 ==
4777 10:02:13.321293 RX Vref Scan: 0
4778 10:02:13.321375
4779 10:02:13.323654 RX Vref 0 -> 0, step: 1
4780 10:02:13.323763
4781 10:02:13.323855 RX Delay -179 -> 252, step: 8
4782 10:02:13.331849 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4783 10:02:13.334539 iDelay=205, Bit 1, Center 32 (-131 ~ 196) 328
4784 10:02:13.337949 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4785 10:02:13.341116 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4786 10:02:13.347987 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4787 10:02:13.351158 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4788 10:02:13.354508 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4789 10:02:13.357607 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4790 10:02:13.364409 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4791 10:02:13.367430 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4792 10:02:13.371044 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4793 10:02:13.373836 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4794 10:02:13.380374 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4795 10:02:13.383885 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4796 10:02:13.387473 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4797 10:02:13.390610 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4798 10:02:13.390692 ==
4799 10:02:13.393717 Dram Type= 6, Freq= 0, CH_1, rank 1
4800 10:02:13.400064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4801 10:02:13.400146 ==
4802 10:02:13.400211 DQS Delay:
4803 10:02:13.403390 DQS0 = 0, DQS1 = 0
4804 10:02:13.403471 DQM Delay:
4805 10:02:13.406665 DQM0 = 37, DQM1 = 35
4806 10:02:13.406748 DQ Delay:
4807 10:02:13.410382 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4808 10:02:13.413759 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4809 10:02:13.416957 DQ8 =20, DQ9 =24, DQ10 =40, DQ11 =28
4810 10:02:13.419964 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4811 10:02:13.420104
4812 10:02:13.420170
4813 10:02:13.426624 [DQSOSCAuto] RK1, (LSB)MR18= 0x3359, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4814 10:02:13.429986 CH1 RK1: MR19=808, MR18=3359
4815 10:02:13.436787 CH1_RK1: MR19=0x808, MR18=0x3359, DQSOSC=393, MR23=63, INC=169, DEC=113
4816 10:02:13.439789 [RxdqsGatingPostProcess] freq 600
4817 10:02:13.446639 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4818 10:02:13.449453 Pre-setting of DQS Precalculation
4819 10:02:13.453061 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4820 10:02:13.459378 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4821 10:02:13.465954 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4822 10:02:13.466051
4823 10:02:13.466116
4824 10:02:13.469350 [Calibration Summary] 1200 Mbps
4825 10:02:13.472521 CH 0, Rank 0
4826 10:02:13.472607 SW Impedance : PASS
4827 10:02:13.475900 DUTY Scan : NO K
4828 10:02:13.479506 ZQ Calibration : PASS
4829 10:02:13.479588 Jitter Meter : NO K
4830 10:02:13.482474 CBT Training : PASS
4831 10:02:13.485854 Write leveling : PASS
4832 10:02:13.485961 RX DQS gating : PASS
4833 10:02:13.489026 RX DQ/DQS(RDDQC) : PASS
4834 10:02:13.492738 TX DQ/DQS : PASS
4835 10:02:13.492821 RX DATLAT : PASS
4836 10:02:13.495830 RX DQ/DQS(Engine): PASS
4837 10:02:13.498913 TX OE : NO K
4838 10:02:13.498996 All Pass.
4839 10:02:13.499060
4840 10:02:13.499120 CH 0, Rank 1
4841 10:02:13.502159 SW Impedance : PASS
4842 10:02:13.505506 DUTY Scan : NO K
4843 10:02:13.505589 ZQ Calibration : PASS
4844 10:02:13.508892 Jitter Meter : NO K
4845 10:02:13.512392 CBT Training : PASS
4846 10:02:13.512474 Write leveling : PASS
4847 10:02:13.515803 RX DQS gating : PASS
4848 10:02:13.515884 RX DQ/DQS(RDDQC) : PASS
4849 10:02:13.519515 TX DQ/DQS : PASS
4850 10:02:13.522684 RX DATLAT : PASS
4851 10:02:13.522765 RX DQ/DQS(Engine): PASS
4852 10:02:13.525451 TX OE : NO K
4853 10:02:13.525586 All Pass.
4854 10:02:13.525664
4855 10:02:13.528346 CH 1, Rank 0
4856 10:02:13.528428 SW Impedance : PASS
4857 10:02:13.532452 DUTY Scan : NO K
4858 10:02:13.535799 ZQ Calibration : PASS
4859 10:02:13.535881 Jitter Meter : NO K
4860 10:02:13.538987 CBT Training : PASS
4861 10:02:13.541485 Write leveling : PASS
4862 10:02:13.541568 RX DQS gating : PASS
4863 10:02:13.544948 RX DQ/DQS(RDDQC) : PASS
4864 10:02:13.548725 TX DQ/DQS : PASS
4865 10:02:13.548847 RX DATLAT : PASS
4866 10:02:13.551653 RX DQ/DQS(Engine): PASS
4867 10:02:13.555267 TX OE : NO K
4868 10:02:13.555350 All Pass.
4869 10:02:13.555415
4870 10:02:13.555475 CH 1, Rank 1
4871 10:02:13.558299 SW Impedance : PASS
4872 10:02:13.561586 DUTY Scan : NO K
4873 10:02:13.561669 ZQ Calibration : PASS
4874 10:02:13.565125 Jitter Meter : NO K
4875 10:02:13.568436 CBT Training : PASS
4876 10:02:13.568539 Write leveling : PASS
4877 10:02:13.571705 RX DQS gating : PASS
4878 10:02:13.575182 RX DQ/DQS(RDDQC) : PASS
4879 10:02:13.575267 TX DQ/DQS : PASS
4880 10:02:13.577838 RX DATLAT : PASS
4881 10:02:13.581312 RX DQ/DQS(Engine): PASS
4882 10:02:13.581406 TX OE : NO K
4883 10:02:13.584559 All Pass.
4884 10:02:13.584663
4885 10:02:13.584742 DramC Write-DBI off
4886 10:02:13.587781 PER_BANK_REFRESH: Hybrid Mode
4887 10:02:13.587851 TX_TRACKING: ON
4888 10:02:13.597817 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4889 10:02:13.600962 [FAST_K] Save calibration result to emmc
4890 10:02:13.604155 dramc_set_vcore_voltage set vcore to 662500
4891 10:02:13.607508 Read voltage for 933, 3
4892 10:02:13.607596 Vio18 = 0
4893 10:02:13.611372 Vcore = 662500
4894 10:02:13.611442 Vdram = 0
4895 10:02:13.611504 Vddq = 0
4896 10:02:13.614849 Vmddr = 0
4897 10:02:13.617340 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4898 10:02:13.624052 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4899 10:02:13.624127 MEM_TYPE=3, freq_sel=17
4900 10:02:13.628061 sv_algorithm_assistance_LP4_1600
4901 10:02:13.634066 ============ PULL DRAM RESETB DOWN ============
4902 10:02:13.637689 ========== PULL DRAM RESETB DOWN end =========
4903 10:02:13.640825 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4904 10:02:13.643697 ===================================
4905 10:02:13.647315 LPDDR4 DRAM CONFIGURATION
4906 10:02:13.650580 ===================================
4907 10:02:13.650656 EX_ROW_EN[0] = 0x0
4908 10:02:13.653969 EX_ROW_EN[1] = 0x0
4909 10:02:13.657615 LP4Y_EN = 0x0
4910 10:02:13.657685 WORK_FSP = 0x0
4911 10:02:13.660446 WL = 0x3
4912 10:02:13.660517 RL = 0x3
4913 10:02:13.663673 BL = 0x2
4914 10:02:13.663743 RPST = 0x0
4915 10:02:13.666741 RD_PRE = 0x0
4916 10:02:13.666816 WR_PRE = 0x1
4917 10:02:13.670693 WR_PST = 0x0
4918 10:02:13.670771 DBI_WR = 0x0
4919 10:02:13.673515 DBI_RD = 0x0
4920 10:02:13.673587 OTF = 0x1
4921 10:02:13.676759 ===================================
4922 10:02:13.680347 ===================================
4923 10:02:13.683271 ANA top config
4924 10:02:13.686790 ===================================
4925 10:02:13.689881 DLL_ASYNC_EN = 0
4926 10:02:13.689948 ALL_SLAVE_EN = 1
4927 10:02:13.693541 NEW_RANK_MODE = 1
4928 10:02:13.696767 DLL_IDLE_MODE = 1
4929 10:02:13.699549 LP45_APHY_COMB_EN = 1
4930 10:02:13.699618 TX_ODT_DIS = 1
4931 10:02:13.703439 NEW_8X_MODE = 1
4932 10:02:13.706547 ===================================
4933 10:02:13.709462 ===================================
4934 10:02:13.713374 data_rate = 1866
4935 10:02:13.716324 CKR = 1
4936 10:02:13.719525 DQ_P2S_RATIO = 8
4937 10:02:13.722827 ===================================
4938 10:02:13.725924 CA_P2S_RATIO = 8
4939 10:02:13.729163 DQ_CA_OPEN = 0
4940 10:02:13.729232 DQ_SEMI_OPEN = 0
4941 10:02:13.732794 CA_SEMI_OPEN = 0
4942 10:02:13.735659 CA_FULL_RATE = 0
4943 10:02:13.739397 DQ_CKDIV4_EN = 1
4944 10:02:13.742442 CA_CKDIV4_EN = 1
4945 10:02:13.745695 CA_PREDIV_EN = 0
4946 10:02:13.745772 PH8_DLY = 0
4947 10:02:13.749063 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4948 10:02:13.752723 DQ_AAMCK_DIV = 4
4949 10:02:13.755917 CA_AAMCK_DIV = 4
4950 10:02:13.758886 CA_ADMCK_DIV = 4
4951 10:02:13.762189 DQ_TRACK_CA_EN = 0
4952 10:02:13.762258 CA_PICK = 933
4953 10:02:13.765844 CA_MCKIO = 933
4954 10:02:13.768928 MCKIO_SEMI = 0
4955 10:02:13.772865 PLL_FREQ = 3732
4956 10:02:13.775564 DQ_UI_PI_RATIO = 32
4957 10:02:13.778986 CA_UI_PI_RATIO = 0
4958 10:02:13.782167 ===================================
4959 10:02:13.785692 ===================================
4960 10:02:13.788689 memory_type:LPDDR4
4961 10:02:13.788759 GP_NUM : 10
4962 10:02:13.791899 SRAM_EN : 1
4963 10:02:13.791967 MD32_EN : 0
4964 10:02:13.795338 ===================================
4965 10:02:13.798607 [ANA_INIT] >>>>>>>>>>>>>>
4966 10:02:13.801719 <<<<<< [CONFIGURE PHASE]: ANA_TX
4967 10:02:13.805323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4968 10:02:13.808283 ===================================
4969 10:02:13.811521 data_rate = 1866,PCW = 0X8f00
4970 10:02:13.815059 ===================================
4971 10:02:13.818194 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4972 10:02:13.824980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4973 10:02:13.828315 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4974 10:02:13.835318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4975 10:02:13.837991 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4976 10:02:13.842173 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4977 10:02:13.842247 [ANA_INIT] flow start
4978 10:02:13.844468 [ANA_INIT] PLL >>>>>>>>
4979 10:02:13.847883 [ANA_INIT] PLL <<<<<<<<
4980 10:02:13.847982 [ANA_INIT] MIDPI >>>>>>>>
4981 10:02:13.851138 [ANA_INIT] MIDPI <<<<<<<<
4982 10:02:13.854428 [ANA_INIT] DLL >>>>>>>>
4983 10:02:13.854506 [ANA_INIT] flow end
4984 10:02:13.861306 ============ LP4 DIFF to SE enter ============
4985 10:02:13.864312 ============ LP4 DIFF to SE exit ============
4986 10:02:13.867615 [ANA_INIT] <<<<<<<<<<<<<
4987 10:02:13.870617 [Flow] Enable top DCM control >>>>>
4988 10:02:13.874042 [Flow] Enable top DCM control <<<<<
4989 10:02:13.878062 Enable DLL master slave shuffle
4990 10:02:13.880848 ==============================================================
4991 10:02:13.884131 Gating Mode config
4992 10:02:13.888087 ==============================================================
4993 10:02:13.890374 Config description:
4994 10:02:13.900700 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4995 10:02:13.907419 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4996 10:02:13.910461 SELPH_MODE 0: By rank 1: By Phase
4997 10:02:13.916940 ==============================================================
4998 10:02:13.920274 GAT_TRACK_EN = 1
4999 10:02:13.923796 RX_GATING_MODE = 2
5000 10:02:13.926781 RX_GATING_TRACK_MODE = 2
5001 10:02:13.930439 SELPH_MODE = 1
5002 10:02:13.934015 PICG_EARLY_EN = 1
5003 10:02:13.936768 VALID_LAT_VALUE = 1
5004 10:02:13.940116 ==============================================================
5005 10:02:13.943313 Enter into Gating configuration >>>>
5006 10:02:13.946872 Exit from Gating configuration <<<<
5007 10:02:13.950010 Enter into DVFS_PRE_config >>>>>
5008 10:02:13.962999 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5009 10:02:13.966322 Exit from DVFS_PRE_config <<<<<
5010 10:02:13.969840 Enter into PICG configuration >>>>
5011 10:02:13.969915 Exit from PICG configuration <<<<
5012 10:02:13.972829 [RX_INPUT] configuration >>>>>
5013 10:02:13.975944 [RX_INPUT] configuration <<<<<
5014 10:02:13.983064 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5015 10:02:13.986116 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5016 10:02:13.992579 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5017 10:02:13.999250 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5018 10:02:14.005904 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5019 10:02:14.012271 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5020 10:02:14.015826 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5021 10:02:14.019088 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5022 10:02:14.025543 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5023 10:02:14.029101 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5024 10:02:14.032560 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5025 10:02:14.035448 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5026 10:02:14.039159 ===================================
5027 10:02:14.042021 LPDDR4 DRAM CONFIGURATION
5028 10:02:14.045042 ===================================
5029 10:02:14.048651 EX_ROW_EN[0] = 0x0
5030 10:02:14.048727 EX_ROW_EN[1] = 0x0
5031 10:02:14.051606 LP4Y_EN = 0x0
5032 10:02:14.051705 WORK_FSP = 0x0
5033 10:02:14.055575 WL = 0x3
5034 10:02:14.055648 RL = 0x3
5035 10:02:14.058869 BL = 0x2
5036 10:02:14.061904 RPST = 0x0
5037 10:02:14.061977 RD_PRE = 0x0
5038 10:02:14.065073 WR_PRE = 0x1
5039 10:02:14.065143 WR_PST = 0x0
5040 10:02:14.068505 DBI_WR = 0x0
5041 10:02:14.068578 DBI_RD = 0x0
5042 10:02:14.071511 OTF = 0x1
5043 10:02:14.075001 ===================================
5044 10:02:14.078036 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5045 10:02:14.081493 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5046 10:02:14.087842 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5047 10:02:14.087919 ===================================
5048 10:02:14.091396 LPDDR4 DRAM CONFIGURATION
5049 10:02:14.095272 ===================================
5050 10:02:14.097795 EX_ROW_EN[0] = 0x10
5051 10:02:14.097865 EX_ROW_EN[1] = 0x0
5052 10:02:14.101860 LP4Y_EN = 0x0
5053 10:02:14.101934 WORK_FSP = 0x0
5054 10:02:14.105119 WL = 0x3
5055 10:02:14.107668 RL = 0x3
5056 10:02:14.107740 BL = 0x2
5057 10:02:14.111359 RPST = 0x0
5058 10:02:14.111428 RD_PRE = 0x0
5059 10:02:14.114241 WR_PRE = 0x1
5060 10:02:14.114309 WR_PST = 0x0
5061 10:02:14.117775 DBI_WR = 0x0
5062 10:02:14.117846 DBI_RD = 0x0
5063 10:02:14.120895 OTF = 0x1
5064 10:02:14.124607 ===================================
5065 10:02:14.130915 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5066 10:02:14.134164 nWR fixed to 30
5067 10:02:14.134240 [ModeRegInit_LP4] CH0 RK0
5068 10:02:14.137897 [ModeRegInit_LP4] CH0 RK1
5069 10:02:14.140824 [ModeRegInit_LP4] CH1 RK0
5070 10:02:14.140892 [ModeRegInit_LP4] CH1 RK1
5071 10:02:14.144163 match AC timing 9
5072 10:02:14.147737 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5073 10:02:14.150661 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5074 10:02:14.157906 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5075 10:02:14.161072 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5076 10:02:14.167086 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5077 10:02:14.167157 ==
5078 10:02:14.170307 Dram Type= 6, Freq= 0, CH_0, rank 0
5079 10:02:14.174001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 10:02:14.174075 ==
5081 10:02:14.180278 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5082 10:02:14.187080 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5083 10:02:14.190427 [CA 0] Center 37 (7~68) winsize 62
5084 10:02:14.193439 [CA 1] Center 37 (7~68) winsize 62
5085 10:02:14.197207 [CA 2] Center 34 (4~65) winsize 62
5086 10:02:14.200736 [CA 3] Center 34 (4~65) winsize 62
5087 10:02:14.203759 [CA 4] Center 32 (2~63) winsize 62
5088 10:02:14.207329 [CA 5] Center 32 (2~63) winsize 62
5089 10:02:14.207402
5090 10:02:14.210679 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5091 10:02:14.210748
5092 10:02:14.213569 [CATrainingPosCal] consider 1 rank data
5093 10:02:14.216805 u2DelayCellTimex100 = 270/100 ps
5094 10:02:14.219923 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5095 10:02:14.223102 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5096 10:02:14.226325 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5097 10:02:14.229846 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5098 10:02:14.233252 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5099 10:02:14.236770 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5100 10:02:14.239643
5101 10:02:14.242924 CA PerBit enable=1, Macro0, CA PI delay=32
5102 10:02:14.242998
5103 10:02:14.246169 [CBTSetCACLKResult] CA Dly = 32
5104 10:02:14.246249 CS Dly: 6 (0~37)
5105 10:02:14.246311 ==
5106 10:02:14.249491 Dram Type= 6, Freq= 0, CH_0, rank 1
5107 10:02:14.253279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 10:02:14.255917 ==
5109 10:02:14.259243 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5110 10:02:14.265952 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5111 10:02:14.269286 [CA 0] Center 37 (7~68) winsize 62
5112 10:02:14.272507 [CA 1] Center 37 (7~68) winsize 62
5113 10:02:14.276147 [CA 2] Center 34 (4~65) winsize 62
5114 10:02:14.279543 [CA 3] Center 34 (4~65) winsize 62
5115 10:02:14.282301 [CA 4] Center 33 (2~64) winsize 63
5116 10:02:14.286041 [CA 5] Center 32 (2~63) winsize 62
5117 10:02:14.286109
5118 10:02:14.289007 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5119 10:02:14.289074
5120 10:02:14.292283 [CATrainingPosCal] consider 2 rank data
5121 10:02:14.295760 u2DelayCellTimex100 = 270/100 ps
5122 10:02:14.298902 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5123 10:02:14.302321 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5124 10:02:14.308635 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5125 10:02:14.311890 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5126 10:02:14.315452 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5127 10:02:14.318954 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5128 10:02:14.319029
5129 10:02:14.321716 CA PerBit enable=1, Macro0, CA PI delay=32
5130 10:02:14.321792
5131 10:02:14.325207 [CBTSetCACLKResult] CA Dly = 32
5132 10:02:14.325281 CS Dly: 7 (0~39)
5133 10:02:14.325346
5134 10:02:14.332666 ----->DramcWriteLeveling(PI) begin...
5135 10:02:14.332771 ==
5136 10:02:14.334926 Dram Type= 6, Freq= 0, CH_0, rank 0
5137 10:02:14.338563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5138 10:02:14.338647 ==
5139 10:02:14.341510 Write leveling (Byte 0): 33 => 33
5140 10:02:14.345125 Write leveling (Byte 1): 29 => 29
5141 10:02:14.348506 DramcWriteLeveling(PI) end<-----
5142 10:02:14.348584
5143 10:02:14.348650 ==
5144 10:02:14.351711 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 10:02:14.355092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 10:02:14.355171 ==
5147 10:02:14.357870 [Gating] SW mode calibration
5148 10:02:14.365037 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5149 10:02:14.371869 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5150 10:02:14.374908 0 14 0 | B1->B0 | 2424 3434 | 1 0 | (1 1) (0 0)
5151 10:02:14.378115 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5152 10:02:14.384698 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 10:02:14.387850 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 10:02:14.391241 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 10:02:14.397865 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 10:02:14.401193 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 10:02:14.404422 0 14 28 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (1 1)
5158 10:02:14.411004 0 15 0 | B1->B0 | 3030 2424 | 1 0 | (1 0) (0 0)
5159 10:02:14.414096 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5160 10:02:14.417339 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 10:02:14.424286 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 10:02:14.427582 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 10:02:14.430438 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 10:02:14.437400 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5165 10:02:14.440828 0 15 28 | B1->B0 | 2424 3939 | 0 0 | (0 0) (0 0)
5166 10:02:14.443889 1 0 0 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
5167 10:02:14.450331 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 10:02:14.453582 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 10:02:14.457695 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 10:02:14.463533 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 10:02:14.466556 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 10:02:14.469996 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 10:02:14.477186 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5174 10:02:14.479593 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5175 10:02:14.483218 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 10:02:14.489833 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 10:02:14.493244 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 10:02:14.496403 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 10:02:14.503551 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 10:02:14.506387 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 10:02:14.509768 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 10:02:14.515935 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 10:02:14.519185 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 10:02:14.522438 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 10:02:14.529174 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 10:02:14.532545 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 10:02:14.535705 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 10:02:14.542308 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 10:02:14.546183 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5190 10:02:14.549305 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5191 10:02:14.555341 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 10:02:14.558639 Total UI for P1: 0, mck2ui 16
5193 10:02:14.562185 best dqsien dly found for B0: ( 1, 2, 30)
5194 10:02:14.565276 Total UI for P1: 0, mck2ui 16
5195 10:02:14.568826 best dqsien dly found for B1: ( 1, 3, 2)
5196 10:02:14.571951 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5197 10:02:14.575570 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5198 10:02:14.575647
5199 10:02:14.578547 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5200 10:02:14.581541 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5201 10:02:14.585281 [Gating] SW calibration Done
5202 10:02:14.585358 ==
5203 10:02:14.588360 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 10:02:14.591648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 10:02:14.591724 ==
5206 10:02:14.594885 RX Vref Scan: 0
5207 10:02:14.594964
5208 10:02:14.598079 RX Vref 0 -> 0, step: 1
5209 10:02:14.598155
5210 10:02:14.598215 RX Delay -80 -> 252, step: 8
5211 10:02:14.604648 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5212 10:02:14.608573 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5213 10:02:14.611718 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5214 10:02:14.614864 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5215 10:02:14.618070 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5216 10:02:14.621478 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5217 10:02:14.627752 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5218 10:02:14.631320 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5219 10:02:14.634714 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5220 10:02:14.638289 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5221 10:02:14.641338 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5222 10:02:14.647500 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5223 10:02:14.650816 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5224 10:02:14.654724 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5225 10:02:14.657617 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5226 10:02:14.660901 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5227 10:02:14.660976 ==
5228 10:02:14.664266 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 10:02:14.671116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 10:02:14.671195 ==
5231 10:02:14.671257 DQS Delay:
5232 10:02:14.674468 DQS0 = 0, DQS1 = 0
5233 10:02:14.674547 DQM Delay:
5234 10:02:14.674609 DQM0 = 99, DQM1 = 89
5235 10:02:14.678088 DQ Delay:
5236 10:02:14.680731 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5237 10:02:14.683934 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5238 10:02:14.687761 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5239 10:02:14.690603 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5240 10:02:14.690675
5241 10:02:14.690734
5242 10:02:14.690791 ==
5243 10:02:14.693773 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 10:02:14.697309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 10:02:14.697381 ==
5246 10:02:14.697443
5247 10:02:14.697499
5248 10:02:14.700417 TX Vref Scan disable
5249 10:02:14.703750 == TX Byte 0 ==
5250 10:02:14.707351 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5251 10:02:14.710427 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5252 10:02:14.713879 == TX Byte 1 ==
5253 10:02:14.717012 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5254 10:02:14.720016 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5255 10:02:14.720134 ==
5256 10:02:14.724204 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 10:02:14.730694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 10:02:14.730771 ==
5259 10:02:14.730833
5260 10:02:14.730893
5261 10:02:14.730951 TX Vref Scan disable
5262 10:02:14.735274 == TX Byte 0 ==
5263 10:02:14.737985 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5264 10:02:14.744362 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5265 10:02:14.744439 == TX Byte 1 ==
5266 10:02:14.747164 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5267 10:02:14.754117 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5268 10:02:14.754193
5269 10:02:14.754255 [DATLAT]
5270 10:02:14.754316 Freq=933, CH0 RK0
5271 10:02:14.754375
5272 10:02:14.757066 DATLAT Default: 0xd
5273 10:02:14.761015 0, 0xFFFF, sum = 0
5274 10:02:14.761093 1, 0xFFFF, sum = 0
5275 10:02:14.763496 2, 0xFFFF, sum = 0
5276 10:02:14.763575 3, 0xFFFF, sum = 0
5277 10:02:14.767033 4, 0xFFFF, sum = 0
5278 10:02:14.767109 5, 0xFFFF, sum = 0
5279 10:02:14.770209 6, 0xFFFF, sum = 0
5280 10:02:14.770285 7, 0xFFFF, sum = 0
5281 10:02:14.773751 8, 0xFFFF, sum = 0
5282 10:02:14.773833 9, 0xFFFF, sum = 0
5283 10:02:14.776755 10, 0x0, sum = 1
5284 10:02:14.776831 11, 0x0, sum = 2
5285 10:02:14.780173 12, 0x0, sum = 3
5286 10:02:14.780252 13, 0x0, sum = 4
5287 10:02:14.783663 best_step = 11
5288 10:02:14.783736
5289 10:02:14.783797 ==
5290 10:02:14.786707 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 10:02:14.790045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 10:02:14.790121 ==
5293 10:02:14.790184 RX Vref Scan: 1
5294 10:02:14.793749
5295 10:02:14.793822 RX Vref 0 -> 0, step: 1
5296 10:02:14.793882
5297 10:02:14.796650 RX Delay -61 -> 252, step: 4
5298 10:02:14.796724
5299 10:02:14.799978 Set Vref, RX VrefLevel [Byte0]: 54
5300 10:02:14.803209 [Byte1]: 59
5301 10:02:14.807000
5302 10:02:14.807075 Final RX Vref Byte 0 = 54 to rank0
5303 10:02:14.809848 Final RX Vref Byte 1 = 59 to rank0
5304 10:02:14.813154 Final RX Vref Byte 0 = 54 to rank1
5305 10:02:14.816717 Final RX Vref Byte 1 = 59 to rank1==
5306 10:02:14.819761 Dram Type= 6, Freq= 0, CH_0, rank 0
5307 10:02:14.827489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 10:02:14.827567 ==
5309 10:02:14.827630 DQS Delay:
5310 10:02:14.829523 DQS0 = 0, DQS1 = 0
5311 10:02:14.829598 DQM Delay:
5312 10:02:14.829659 DQM0 = 99, DQM1 = 88
5313 10:02:14.832814 DQ Delay:
5314 10:02:14.836405 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =94
5315 10:02:14.839511 DQ4 =100, DQ5 =92, DQ6 =110, DQ7 =106
5316 10:02:14.842712 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =84
5317 10:02:14.845883 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =94
5318 10:02:14.845957
5319 10:02:14.846017
5320 10:02:14.852469 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5321 10:02:14.855698 CH0 RK0: MR19=505, MR18=1A14
5322 10:02:14.862417 CH0_RK0: MR19=0x505, MR18=0x1A14, DQSOSC=413, MR23=63, INC=63, DEC=42
5323 10:02:14.862492
5324 10:02:14.865779 ----->DramcWriteLeveling(PI) begin...
5325 10:02:14.865854 ==
5326 10:02:14.868901 Dram Type= 6, Freq= 0, CH_0, rank 1
5327 10:02:14.872398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 10:02:14.875519 ==
5329 10:02:14.875592 Write leveling (Byte 0): 31 => 31
5330 10:02:14.878840 Write leveling (Byte 1): 29 => 29
5331 10:02:14.882370 DramcWriteLeveling(PI) end<-----
5332 10:02:14.882438
5333 10:02:14.882497 ==
5334 10:02:14.885474 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 10:02:14.891945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 10:02:14.892052 ==
5337 10:02:14.895473 [Gating] SW mode calibration
5338 10:02:14.902176 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5339 10:02:14.905590 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5340 10:02:14.911852 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
5341 10:02:14.914777 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 10:02:14.918537 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 10:02:14.925057 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 10:02:14.928367 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 10:02:14.931316 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 10:02:14.937896 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
5347 10:02:14.941066 0 14 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
5348 10:02:14.944494 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
5349 10:02:14.951037 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 10:02:14.954888 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 10:02:14.957549 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 10:02:14.964488 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 10:02:14.967883 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 10:02:14.971042 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5355 10:02:14.977640 0 15 28 | B1->B0 | 2828 3f3f | 1 0 | (0 0) (0 0)
5356 10:02:14.980703 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5357 10:02:14.983953 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 10:02:14.991056 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 10:02:14.993898 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 10:02:14.997150 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 10:02:15.003588 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 10:02:15.006824 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 10:02:15.010518 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5364 10:02:15.016652 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5365 10:02:15.020011 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 10:02:15.023197 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 10:02:15.030148 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 10:02:15.033313 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 10:02:15.036700 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 10:02:15.043235 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 10:02:15.046393 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 10:02:15.049708 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 10:02:15.056124 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 10:02:15.059558 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 10:02:15.062912 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 10:02:15.069428 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 10:02:15.072899 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 10:02:15.075754 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5379 10:02:15.082597 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5380 10:02:15.085496 Total UI for P1: 0, mck2ui 16
5381 10:02:15.088944 best dqsien dly found for B0: ( 1, 2, 24)
5382 10:02:15.092743 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5383 10:02:15.095507 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 10:02:15.098908 Total UI for P1: 0, mck2ui 16
5385 10:02:15.102123 best dqsien dly found for B1: ( 1, 2, 30)
5386 10:02:15.105434 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5387 10:02:15.111989 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5388 10:02:15.112079
5389 10:02:15.115428 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5390 10:02:15.118670 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5391 10:02:15.122060 [Gating] SW calibration Done
5392 10:02:15.122131 ==
5393 10:02:15.125228 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 10:02:15.128336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 10:02:15.128407 ==
5396 10:02:15.131705 RX Vref Scan: 0
5397 10:02:15.131800
5398 10:02:15.131887 RX Vref 0 -> 0, step: 1
5399 10:02:15.131971
5400 10:02:15.135240 RX Delay -80 -> 252, step: 8
5401 10:02:15.138558 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5402 10:02:15.145263 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5403 10:02:15.148465 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5404 10:02:15.151676 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5405 10:02:15.155307 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5406 10:02:15.158856 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5407 10:02:15.161435 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5408 10:02:15.168380 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5409 10:02:15.171295 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5410 10:02:15.174634 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5411 10:02:15.178381 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5412 10:02:15.181503 iDelay=200, Bit 11, Center 87 (0 ~ 175) 176
5413 10:02:15.184461 iDelay=200, Bit 12, Center 95 (8 ~ 183) 176
5414 10:02:15.191404 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5415 10:02:15.194548 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5416 10:02:15.197730 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5417 10:02:15.197803 ==
5418 10:02:15.200888 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 10:02:15.204012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 10:02:15.204143 ==
5421 10:02:15.207839 DQS Delay:
5422 10:02:15.207937 DQS0 = 0, DQS1 = 0
5423 10:02:15.210743 DQM Delay:
5424 10:02:15.210836 DQM0 = 97, DQM1 = 91
5425 10:02:15.210922 DQ Delay:
5426 10:02:15.214475 DQ0 =99, DQ1 =103, DQ2 =91, DQ3 =91
5427 10:02:15.217360 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5428 10:02:15.220714 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5429 10:02:15.224275 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5430 10:02:15.227229
5431 10:02:15.227316
5432 10:02:15.227378 ==
5433 10:02:15.230770 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 10:02:15.234528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 10:02:15.234610 ==
5436 10:02:15.234673
5437 10:02:15.234731
5438 10:02:15.237220 TX Vref Scan disable
5439 10:02:15.237300 == TX Byte 0 ==
5440 10:02:15.243565 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5441 10:02:15.247487 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5442 10:02:15.247567 == TX Byte 1 ==
5443 10:02:15.253640 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5444 10:02:15.257488 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5445 10:02:15.257567 ==
5446 10:02:15.260200 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 10:02:15.263154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 10:02:15.263234 ==
5449 10:02:15.263296
5450 10:02:15.263354
5451 10:02:15.266758 TX Vref Scan disable
5452 10:02:15.269977 == TX Byte 0 ==
5453 10:02:15.273172 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5454 10:02:15.276551 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5455 10:02:15.280124 == TX Byte 1 ==
5456 10:02:15.283242 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5457 10:02:15.289991 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5458 10:02:15.290073
5459 10:02:15.290137 [DATLAT]
5460 10:02:15.290196 Freq=933, CH0 RK1
5461 10:02:15.290255
5462 10:02:15.293077 DATLAT Default: 0xb
5463 10:02:15.293159 0, 0xFFFF, sum = 0
5464 10:02:15.295965 1, 0xFFFF, sum = 0
5465 10:02:15.299315 2, 0xFFFF, sum = 0
5466 10:02:15.299398 3, 0xFFFF, sum = 0
5467 10:02:15.302670 4, 0xFFFF, sum = 0
5468 10:02:15.302753 5, 0xFFFF, sum = 0
5469 10:02:15.306327 6, 0xFFFF, sum = 0
5470 10:02:15.306411 7, 0xFFFF, sum = 0
5471 10:02:15.309082 8, 0xFFFF, sum = 0
5472 10:02:15.309166 9, 0xFFFF, sum = 0
5473 10:02:15.312410 10, 0x0, sum = 1
5474 10:02:15.312493 11, 0x0, sum = 2
5475 10:02:15.315990 12, 0x0, sum = 3
5476 10:02:15.316083 13, 0x0, sum = 4
5477 10:02:15.319737 best_step = 11
5478 10:02:15.319818
5479 10:02:15.319882 ==
5480 10:02:15.322765 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 10:02:15.325834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 10:02:15.325916 ==
5483 10:02:15.325981 RX Vref Scan: 0
5484 10:02:15.326042
5485 10:02:15.329115 RX Vref 0 -> 0, step: 1
5486 10:02:15.329197
5487 10:02:15.332898 RX Delay -53 -> 252, step: 4
5488 10:02:15.339004 iDelay=199, Bit 0, Center 94 (7 ~ 182) 176
5489 10:02:15.342564 iDelay=199, Bit 1, Center 98 (7 ~ 190) 184
5490 10:02:15.345697 iDelay=199, Bit 2, Center 92 (3 ~ 182) 180
5491 10:02:15.349005 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5492 10:02:15.352070 iDelay=199, Bit 4, Center 100 (11 ~ 190) 180
5493 10:02:15.355611 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5494 10:02:15.362148 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5495 10:02:15.365983 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5496 10:02:15.368316 iDelay=199, Bit 8, Center 80 (-5 ~ 166) 172
5497 10:02:15.371940 iDelay=199, Bit 9, Center 76 (-9 ~ 162) 172
5498 10:02:15.375017 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5499 10:02:15.381662 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5500 10:02:15.384946 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5501 10:02:15.387856 iDelay=199, Bit 13, Center 94 (3 ~ 186) 184
5502 10:02:15.391703 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5503 10:02:15.394591 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5504 10:02:15.394694 ==
5505 10:02:15.398231 Dram Type= 6, Freq= 0, CH_0, rank 1
5506 10:02:15.404415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 10:02:15.404496 ==
5508 10:02:15.404559 DQS Delay:
5509 10:02:15.407649 DQS0 = 0, DQS1 = 0
5510 10:02:15.407731 DQM Delay:
5511 10:02:15.411151 DQM0 = 96, DQM1 = 89
5512 10:02:15.411232 DQ Delay:
5513 10:02:15.414278 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =94
5514 10:02:15.418345 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =104
5515 10:02:15.421272 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5516 10:02:15.424320 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =94
5517 10:02:15.424401
5518 10:02:15.424464
5519 10:02:15.430988 [DQSOSCAuto] RK1, (LSB)MR18= 0x130f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
5520 10:02:15.434584 CH0 RK1: MR19=505, MR18=130F
5521 10:02:15.441267 CH0_RK1: MR19=0x505, MR18=0x130F, DQSOSC=415, MR23=63, INC=62, DEC=41
5522 10:02:15.444580 [RxdqsGatingPostProcess] freq 933
5523 10:02:15.450789 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5524 10:02:15.453942 best DQS0 dly(2T, 0.5T) = (0, 10)
5525 10:02:15.457596 best DQS1 dly(2T, 0.5T) = (0, 11)
5526 10:02:15.460862 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5527 10:02:15.463726 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5528 10:02:15.463960 best DQS0 dly(2T, 0.5T) = (0, 10)
5529 10:02:15.467761 best DQS1 dly(2T, 0.5T) = (0, 10)
5530 10:02:15.471004 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5531 10:02:15.473929 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5532 10:02:15.476849 Pre-setting of DQS Precalculation
5533 10:02:15.484403 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5534 10:02:15.484893 ==
5535 10:02:15.487366 Dram Type= 6, Freq= 0, CH_1, rank 0
5536 10:02:15.490656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 10:02:15.491224 ==
5538 10:02:15.497203 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5539 10:02:15.503686 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5540 10:02:15.507300 [CA 0] Center 36 (6~67) winsize 62
5541 10:02:15.509977 [CA 1] Center 36 (6~67) winsize 62
5542 10:02:15.513786 [CA 2] Center 34 (4~65) winsize 62
5543 10:02:15.516643 [CA 3] Center 34 (4~64) winsize 61
5544 10:02:15.521061 [CA 4] Center 34 (4~65) winsize 62
5545 10:02:15.523566 [CA 5] Center 33 (3~64) winsize 62
5546 10:02:15.524152
5547 10:02:15.527841 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5548 10:02:15.528463
5549 10:02:15.530053 [CATrainingPosCal] consider 1 rank data
5550 10:02:15.533329 u2DelayCellTimex100 = 270/100 ps
5551 10:02:15.536462 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5552 10:02:15.540386 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5553 10:02:15.543299 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5554 10:02:15.546681 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5555 10:02:15.550009 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5556 10:02:15.552965 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5557 10:02:15.556244
5558 10:02:15.559836 CA PerBit enable=1, Macro0, CA PI delay=33
5559 10:02:15.560414
5560 10:02:15.562775 [CBTSetCACLKResult] CA Dly = 33
5561 10:02:15.563279 CS Dly: 5 (0~36)
5562 10:02:15.563789 ==
5563 10:02:15.566041 Dram Type= 6, Freq= 0, CH_1, rank 1
5564 10:02:15.569569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 10:02:15.572754 ==
5566 10:02:15.576588 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5567 10:02:15.582557 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5568 10:02:15.585976 [CA 0] Center 36 (6~67) winsize 62
5569 10:02:15.589350 [CA 1] Center 37 (6~68) winsize 63
5570 10:02:15.592818 [CA 2] Center 34 (4~65) winsize 62
5571 10:02:15.595867 [CA 3] Center 33 (3~64) winsize 62
5572 10:02:15.599634 [CA 4] Center 34 (4~64) winsize 61
5573 10:02:15.602396 [CA 5] Center 33 (3~64) winsize 62
5574 10:02:15.602947
5575 10:02:15.605754 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5576 10:02:15.606457
5577 10:02:15.608666 [CATrainingPosCal] consider 2 rank data
5578 10:02:15.612353 u2DelayCellTimex100 = 270/100 ps
5579 10:02:15.615408 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5580 10:02:15.619136 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5581 10:02:15.622304 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5582 10:02:15.628854 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5583 10:02:15.632108 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5584 10:02:15.636225 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5585 10:02:15.636773
5586 10:02:15.638393 CA PerBit enable=1, Macro0, CA PI delay=33
5587 10:02:15.638863
5588 10:02:15.641734 [CBTSetCACLKResult] CA Dly = 33
5589 10:02:15.642299 CS Dly: 6 (0~38)
5590 10:02:15.642671
5591 10:02:15.644931 ----->DramcWriteLeveling(PI) begin...
5592 10:02:15.648286 ==
5593 10:02:15.648749 Dram Type= 6, Freq= 0, CH_1, rank 0
5594 10:02:15.655042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5595 10:02:15.655508 ==
5596 10:02:15.659189 Write leveling (Byte 0): 23 => 23
5597 10:02:15.661945 Write leveling (Byte 1): 30 => 30
5598 10:02:15.665192 DramcWriteLeveling(PI) end<-----
5599 10:02:15.665654
5600 10:02:15.666063 ==
5601 10:02:15.668237 Dram Type= 6, Freq= 0, CH_1, rank 0
5602 10:02:15.671573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 10:02:15.671991 ==
5604 10:02:15.674871 [Gating] SW mode calibration
5605 10:02:15.681541 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5606 10:02:15.687714 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5607 10:02:15.691432 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 10:02:15.694201 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 10:02:15.701630 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 10:02:15.704669 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 10:02:15.707894 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 10:02:15.714097 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 10:02:15.717473 0 14 24 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 0)
5614 10:02:15.720920 0 14 28 | B1->B0 | 2b2b 2727 | 0 0 | (1 0) (0 1)
5615 10:02:15.727174 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 10:02:15.731092 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 10:02:15.734339 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 10:02:15.740753 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 10:02:15.744107 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 10:02:15.747417 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 10:02:15.753363 0 15 24 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (0 0)
5622 10:02:15.756577 0 15 28 | B1->B0 | 4040 4343 | 0 0 | (0 0) (0 0)
5623 10:02:15.760749 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 10:02:15.766913 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 10:02:15.769835 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 10:02:15.773505 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 10:02:15.779987 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 10:02:15.783338 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 10:02:15.786491 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5630 10:02:15.793170 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5631 10:02:15.796423 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 10:02:15.800018 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 10:02:15.806335 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 10:02:15.809435 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 10:02:15.813102 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 10:02:15.819611 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 10:02:15.822879 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 10:02:15.825756 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 10:02:15.832453 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 10:02:15.835695 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 10:02:15.839271 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 10:02:15.845806 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 10:02:15.848662 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 10:02:15.852208 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 10:02:15.859426 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 10:02:15.862001 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 10:02:15.865182 Total UI for P1: 0, mck2ui 16
5648 10:02:15.869190 best dqsien dly found for B0: ( 1, 2, 26)
5649 10:02:15.872639 Total UI for P1: 0, mck2ui 16
5650 10:02:15.875568 best dqsien dly found for B1: ( 1, 2, 26)
5651 10:02:15.878994 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5652 10:02:15.881531 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5653 10:02:15.882000
5654 10:02:15.884950 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5655 10:02:15.891722 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5656 10:02:15.892284 [Gating] SW calibration Done
5657 10:02:15.892629 ==
5658 10:02:15.895734 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 10:02:15.901825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 10:02:15.902383 ==
5661 10:02:15.902748 RX Vref Scan: 0
5662 10:02:15.903087
5663 10:02:15.905408 RX Vref 0 -> 0, step: 1
5664 10:02:15.905961
5665 10:02:15.908480 RX Delay -80 -> 252, step: 8
5666 10:02:15.911929 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5667 10:02:15.914971 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5668 10:02:15.918144 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5669 10:02:15.924961 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5670 10:02:15.928024 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5671 10:02:15.931815 iDelay=208, Bit 5, Center 103 (8 ~ 199) 192
5672 10:02:15.934632 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5673 10:02:15.938121 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5674 10:02:15.941062 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5675 10:02:15.947932 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5676 10:02:15.950477 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5677 10:02:15.953857 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5678 10:02:15.957671 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5679 10:02:15.960510 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5680 10:02:15.967277 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5681 10:02:15.970944 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5682 10:02:15.971493 ==
5683 10:02:15.973871 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 10:02:15.977340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 10:02:15.977816 ==
5686 10:02:15.978183 DQS Delay:
5687 10:02:15.981526 DQS0 = 0, DQS1 = 0
5688 10:02:15.982099 DQM Delay:
5689 10:02:15.983489 DQM0 = 97, DQM1 = 93
5690 10:02:15.983952 DQ Delay:
5691 10:02:15.987556 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5692 10:02:15.990365 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =95
5693 10:02:15.993399 DQ8 =79, DQ9 =87, DQ10 =91, DQ11 =87
5694 10:02:15.997323 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5695 10:02:15.997877
5696 10:02:15.998280
5697 10:02:15.998620 ==
5698 10:02:16.000324 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 10:02:16.006998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 10:02:16.007556 ==
5701 10:02:16.007922
5702 10:02:16.008280
5703 10:02:16.008602 TX Vref Scan disable
5704 10:02:16.010344 == TX Byte 0 ==
5705 10:02:16.013948 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5706 10:02:16.020287 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5707 10:02:16.020846 == TX Byte 1 ==
5708 10:02:16.024199 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5709 10:02:16.030304 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5710 10:02:16.030864 ==
5711 10:02:16.033167 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 10:02:16.036720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 10:02:16.037278 ==
5714 10:02:16.037642
5715 10:02:16.037974
5716 10:02:16.040200 TX Vref Scan disable
5717 10:02:16.043923 == TX Byte 0 ==
5718 10:02:16.046892 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5719 10:02:16.050033 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5720 10:02:16.053118 == TX Byte 1 ==
5721 10:02:16.056408 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5722 10:02:16.059768 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5723 10:02:16.060384
5724 10:02:16.060750 [DATLAT]
5725 10:02:16.062918 Freq=933, CH1 RK0
5726 10:02:16.063375
5727 10:02:16.066294 DATLAT Default: 0xd
5728 10:02:16.066753 0, 0xFFFF, sum = 0
5729 10:02:16.070135 1, 0xFFFF, sum = 0
5730 10:02:16.070701 2, 0xFFFF, sum = 0
5731 10:02:16.073224 3, 0xFFFF, sum = 0
5732 10:02:16.073785 4, 0xFFFF, sum = 0
5733 10:02:16.076292 5, 0xFFFF, sum = 0
5734 10:02:16.076879 6, 0xFFFF, sum = 0
5735 10:02:16.079896 7, 0xFFFF, sum = 0
5736 10:02:16.080395 8, 0xFFFF, sum = 0
5737 10:02:16.083333 9, 0xFFFF, sum = 0
5738 10:02:16.083898 10, 0x0, sum = 1
5739 10:02:16.086320 11, 0x0, sum = 2
5740 10:02:16.086887 12, 0x0, sum = 3
5741 10:02:16.089484 13, 0x0, sum = 4
5742 10:02:16.089948 best_step = 11
5743 10:02:16.090308
5744 10:02:16.090641 ==
5745 10:02:16.093177 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 10:02:16.096368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 10:02:16.099086 ==
5748 10:02:16.099501 RX Vref Scan: 1
5749 10:02:16.099829
5750 10:02:16.102855 RX Vref 0 -> 0, step: 1
5751 10:02:16.103366
5752 10:02:16.106693 RX Delay -61 -> 252, step: 4
5753 10:02:16.107379
5754 10:02:16.109261 Set Vref, RX VrefLevel [Byte0]: 52
5755 10:02:16.112715 [Byte1]: 53
5756 10:02:16.113251
5757 10:02:16.116454 Final RX Vref Byte 0 = 52 to rank0
5758 10:02:16.119078 Final RX Vref Byte 1 = 53 to rank0
5759 10:02:16.122858 Final RX Vref Byte 0 = 52 to rank1
5760 10:02:16.126112 Final RX Vref Byte 1 = 53 to rank1==
5761 10:02:16.128741 Dram Type= 6, Freq= 0, CH_1, rank 0
5762 10:02:16.132983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 10:02:16.133509 ==
5764 10:02:16.135551 DQS Delay:
5765 10:02:16.136105 DQS0 = 0, DQS1 = 0
5766 10:02:16.138981 DQM Delay:
5767 10:02:16.139532 DQM0 = 96, DQM1 = 93
5768 10:02:16.139899 DQ Delay:
5769 10:02:16.142400 DQ0 =102, DQ1 =90, DQ2 =86, DQ3 =96
5770 10:02:16.145249 DQ4 =92, DQ5 =106, DQ6 =106, DQ7 =92
5771 10:02:16.148427 DQ8 =82, DQ9 =84, DQ10 =90, DQ11 =86
5772 10:02:16.151824 DQ12 =100, DQ13 =102, DQ14 =100, DQ15 =102
5773 10:02:16.155045
5774 10:02:16.155511
5775 10:02:16.162262 [DQSOSCAuto] RK0, (LSB)MR18= 0xa19, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5776 10:02:16.164595 CH1 RK0: MR19=505, MR18=A19
5777 10:02:16.171764 CH1_RK0: MR19=0x505, MR18=0xA19, DQSOSC=413, MR23=63, INC=63, DEC=42
5778 10:02:16.172377
5779 10:02:16.175134 ----->DramcWriteLeveling(PI) begin...
5780 10:02:16.175602 ==
5781 10:02:16.178146 Dram Type= 6, Freq= 0, CH_1, rank 1
5782 10:02:16.182384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 10:02:16.182942 ==
5784 10:02:16.184702 Write leveling (Byte 0): 24 => 24
5785 10:02:16.188103 Write leveling (Byte 1): 27 => 27
5786 10:02:16.191412 DramcWriteLeveling(PI) end<-----
5787 10:02:16.191963
5788 10:02:16.192372 ==
5789 10:02:16.194743 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 10:02:16.197772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 10:02:16.198329 ==
5792 10:02:16.201274 [Gating] SW mode calibration
5793 10:02:16.207694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5794 10:02:16.214255 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5795 10:02:16.218469 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5796 10:02:16.224191 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 10:02:16.226989 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 10:02:16.230410 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 10:02:16.236972 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 10:02:16.240636 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 10:02:16.243975 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
5802 10:02:16.250108 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5803 10:02:16.253635 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 10:02:16.256616 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 10:02:16.263158 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 10:02:16.266405 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 10:02:16.270168 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 10:02:16.276355 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 10:02:16.280122 0 15 24 | B1->B0 | 2525 3939 | 1 0 | (0 0) (0 0)
5810 10:02:16.283319 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5811 10:02:16.289704 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 10:02:16.293002 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 10:02:16.296541 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 10:02:16.302705 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 10:02:16.305633 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 10:02:16.309618 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 10:02:16.316450 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5818 10:02:16.320129 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5819 10:02:16.322887 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 10:02:16.329280 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 10:02:16.332114 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 10:02:16.335254 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 10:02:16.342045 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 10:02:16.345340 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 10:02:16.348659 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 10:02:16.355027 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 10:02:16.358420 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 10:02:16.362037 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 10:02:16.368615 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 10:02:16.372286 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 10:02:16.374673 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 10:02:16.382018 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5833 10:02:16.384948 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5834 10:02:16.388187 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5835 10:02:16.392187 Total UI for P1: 0, mck2ui 16
5836 10:02:16.394743 best dqsien dly found for B0: ( 1, 2, 22)
5837 10:02:16.401621 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 10:02:16.404604 Total UI for P1: 0, mck2ui 16
5839 10:02:16.408267 best dqsien dly found for B1: ( 1, 2, 26)
5840 10:02:16.411557 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5841 10:02:16.415425 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5842 10:02:16.416173
5843 10:02:16.417631 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5844 10:02:16.421308 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5845 10:02:16.424284 [Gating] SW calibration Done
5846 10:02:16.424739 ==
5847 10:02:16.427955 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 10:02:16.431579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 10:02:16.432073 ==
5850 10:02:16.433936 RX Vref Scan: 0
5851 10:02:16.434390
5852 10:02:16.436983 RX Vref 0 -> 0, step: 1
5853 10:02:16.437445
5854 10:02:16.437768 RX Delay -80 -> 252, step: 8
5855 10:02:16.443936 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5856 10:02:16.447384 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5857 10:02:16.450625 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5858 10:02:16.453800 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5859 10:02:16.456896 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5860 10:02:16.463759 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5861 10:02:16.467079 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5862 10:02:16.470602 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5863 10:02:16.473405 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5864 10:02:16.476625 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5865 10:02:16.483276 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5866 10:02:16.487058 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5867 10:02:16.489884 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5868 10:02:16.493158 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5869 10:02:16.496652 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5870 10:02:16.499919 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5871 10:02:16.502844 ==
5872 10:02:16.506409 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 10:02:16.509659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 10:02:16.510216 ==
5875 10:02:16.510581 DQS Delay:
5876 10:02:16.513524 DQS0 = 0, DQS1 = 0
5877 10:02:16.514081 DQM Delay:
5878 10:02:16.516203 DQM0 = 95, DQM1 = 91
5879 10:02:16.516761 DQ Delay:
5880 10:02:16.519878 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5881 10:02:16.523227 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5882 10:02:16.526312 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =87
5883 10:02:16.529479 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5884 10:02:16.530063
5885 10:02:16.530432
5886 10:02:16.530768 ==
5887 10:02:16.532636 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 10:02:16.536324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 10:02:16.536882 ==
5890 10:02:16.537242
5891 10:02:16.539587
5892 10:02:16.540067 TX Vref Scan disable
5893 10:02:16.542975 == TX Byte 0 ==
5894 10:02:16.545897 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5895 10:02:16.549049 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5896 10:02:16.552183 == TX Byte 1 ==
5897 10:02:16.555980 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5898 10:02:16.558770 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5899 10:02:16.559289 ==
5900 10:02:16.562900 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 10:02:16.568933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 10:02:16.569455 ==
5903 10:02:16.569821
5904 10:02:16.570155
5905 10:02:16.572219 TX Vref Scan disable
5906 10:02:16.572686 == TX Byte 0 ==
5907 10:02:16.578997 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5908 10:02:16.582629 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5909 10:02:16.583188 == TX Byte 1 ==
5910 10:02:16.588738 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5911 10:02:16.591959 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5912 10:02:16.592577
5913 10:02:16.592950 [DATLAT]
5914 10:02:16.595596 Freq=933, CH1 RK1
5915 10:02:16.596194
5916 10:02:16.596563 DATLAT Default: 0xb
5917 10:02:16.599012 0, 0xFFFF, sum = 0
5918 10:02:16.599617 1, 0xFFFF, sum = 0
5919 10:02:16.602364 2, 0xFFFF, sum = 0
5920 10:02:16.602867 3, 0xFFFF, sum = 0
5921 10:02:16.605697 4, 0xFFFF, sum = 0
5922 10:02:16.606259 5, 0xFFFF, sum = 0
5923 10:02:16.608372 6, 0xFFFF, sum = 0
5924 10:02:16.611484 7, 0xFFFF, sum = 0
5925 10:02:16.612092 8, 0xFFFF, sum = 0
5926 10:02:16.615052 9, 0xFFFF, sum = 0
5927 10:02:16.615610 10, 0x0, sum = 1
5928 10:02:16.617950 11, 0x0, sum = 2
5929 10:02:16.618423 12, 0x0, sum = 3
5930 10:02:16.618795 13, 0x0, sum = 4
5931 10:02:16.621465 best_step = 11
5932 10:02:16.621930
5933 10:02:16.622294 ==
5934 10:02:16.625020 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 10:02:16.628286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 10:02:16.628856 ==
5937 10:02:16.631468 RX Vref Scan: 0
5938 10:02:16.632138
5939 10:02:16.634872 RX Vref 0 -> 0, step: 1
5940 10:02:16.635429
5941 10:02:16.635799 RX Delay -61 -> 252, step: 4
5942 10:02:16.642742 iDelay=199, Bit 0, Center 100 (7 ~ 194) 188
5943 10:02:16.646315 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5944 10:02:16.649336 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5945 10:02:16.652265 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5946 10:02:16.655894 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5947 10:02:16.661943 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5948 10:02:16.665370 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5949 10:02:16.668781 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5950 10:02:16.672109 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5951 10:02:16.675359 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5952 10:02:16.678408 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5953 10:02:16.685047 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5954 10:02:16.688206 iDelay=199, Bit 12, Center 102 (15 ~ 190) 176
5955 10:02:16.691951 iDelay=199, Bit 13, Center 102 (11 ~ 194) 184
5956 10:02:16.694802 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5957 10:02:16.701889 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5958 10:02:16.702442 ==
5959 10:02:16.704667 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 10:02:16.708258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 10:02:16.708721 ==
5962 10:02:16.709080 DQS Delay:
5963 10:02:16.711588 DQS0 = 0, DQS1 = 0
5964 10:02:16.712079 DQM Delay:
5965 10:02:16.715226 DQM0 = 95, DQM1 = 92
5966 10:02:16.715758 DQ Delay:
5967 10:02:16.718073 DQ0 =100, DQ1 =94, DQ2 =84, DQ3 =94
5968 10:02:16.721518 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =92
5969 10:02:16.724646 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5970 10:02:16.728109 DQ12 =102, DQ13 =102, DQ14 =96, DQ15 =102
5971 10:02:16.728667
5972 10:02:16.729033
5973 10:02:16.737616 [DQSOSCAuto] RK1, (LSB)MR18= 0x81f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 419 ps
5974 10:02:16.738227 CH1 RK1: MR19=505, MR18=81F
5975 10:02:16.745690 CH1_RK1: MR19=0x505, MR18=0x81F, DQSOSC=412, MR23=63, INC=63, DEC=42
5976 10:02:16.747589 [RxdqsGatingPostProcess] freq 933
5977 10:02:16.754240 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5978 10:02:16.757787 best DQS0 dly(2T, 0.5T) = (0, 10)
5979 10:02:16.760718 best DQS1 dly(2T, 0.5T) = (0, 10)
5980 10:02:16.763997 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5981 10:02:16.767317 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5982 10:02:16.770327 best DQS0 dly(2T, 0.5T) = (0, 10)
5983 10:02:16.770744 best DQS1 dly(2T, 0.5T) = (0, 10)
5984 10:02:16.773900 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5985 10:02:16.777027 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5986 10:02:16.780462 Pre-setting of DQS Precalculation
5987 10:02:16.786783 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5988 10:02:16.793359 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5989 10:02:16.799879 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5990 10:02:16.799993
5991 10:02:16.800094
5992 10:02:16.802974 [Calibration Summary] 1866 Mbps
5993 10:02:16.806102 CH 0, Rank 0
5994 10:02:16.806202 SW Impedance : PASS
5995 10:02:16.809921 DUTY Scan : NO K
5996 10:02:16.813118 ZQ Calibration : PASS
5997 10:02:16.813251 Jitter Meter : NO K
5998 10:02:16.816159 CBT Training : PASS
5999 10:02:16.819215 Write leveling : PASS
6000 10:02:16.819306 RX DQS gating : PASS
6001 10:02:16.822993 RX DQ/DQS(RDDQC) : PASS
6002 10:02:16.826387 TX DQ/DQS : PASS
6003 10:02:16.826496 RX DATLAT : PASS
6004 10:02:16.829127 RX DQ/DQS(Engine): PASS
6005 10:02:16.832816 TX OE : NO K
6006 10:02:16.832984 All Pass.
6007 10:02:16.833061
6008 10:02:16.833134 CH 0, Rank 1
6009 10:02:16.836171 SW Impedance : PASS
6010 10:02:16.839614 DUTY Scan : NO K
6011 10:02:16.839789 ZQ Calibration : PASS
6012 10:02:16.842656 Jitter Meter : NO K
6013 10:02:16.842782 CBT Training : PASS
6014 10:02:16.845974 Write leveling : PASS
6015 10:02:16.849471 RX DQS gating : PASS
6016 10:02:16.849632 RX DQ/DQS(RDDQC) : PASS
6017 10:02:16.852646 TX DQ/DQS : PASS
6018 10:02:16.855562 RX DATLAT : PASS
6019 10:02:16.855757 RX DQ/DQS(Engine): PASS
6020 10:02:16.859732 TX OE : NO K
6021 10:02:16.859900 All Pass.
6022 10:02:16.859992
6023 10:02:16.862876 CH 1, Rank 0
6024 10:02:16.863051 SW Impedance : PASS
6025 10:02:16.865938 DUTY Scan : NO K
6026 10:02:16.869462 ZQ Calibration : PASS
6027 10:02:16.869655 Jitter Meter : NO K
6028 10:02:16.873171 CBT Training : PASS
6029 10:02:16.875571 Write leveling : PASS
6030 10:02:16.875767 RX DQS gating : PASS
6031 10:02:16.879827 RX DQ/DQS(RDDQC) : PASS
6032 10:02:16.882210 TX DQ/DQS : PASS
6033 10:02:16.882444 RX DATLAT : PASS
6034 10:02:16.885364 RX DQ/DQS(Engine): PASS
6035 10:02:16.888767 TX OE : NO K
6036 10:02:16.888937 All Pass.
6037 10:02:16.889072
6038 10:02:16.889195 CH 1, Rank 1
6039 10:02:16.891873 SW Impedance : PASS
6040 10:02:16.895476 DUTY Scan : NO K
6041 10:02:16.895806 ZQ Calibration : PASS
6042 10:02:16.899126 Jitter Meter : NO K
6043 10:02:16.901950 CBT Training : PASS
6044 10:02:16.902341 Write leveling : PASS
6045 10:02:16.905297 RX DQS gating : PASS
6046 10:02:16.908814 RX DQ/DQS(RDDQC) : PASS
6047 10:02:16.909329 TX DQ/DQS : PASS
6048 10:02:16.912571 RX DATLAT : PASS
6049 10:02:16.915851 RX DQ/DQS(Engine): PASS
6050 10:02:16.916439 TX OE : NO K
6051 10:02:16.916810 All Pass.
6052 10:02:16.918509
6053 10:02:16.918967 DramC Write-DBI off
6054 10:02:16.922113 PER_BANK_REFRESH: Hybrid Mode
6055 10:02:16.922672 TX_TRACKING: ON
6056 10:02:16.931886 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6057 10:02:16.934914 [FAST_K] Save calibration result to emmc
6058 10:02:16.938556 dramc_set_vcore_voltage set vcore to 650000
6059 10:02:16.941381 Read voltage for 400, 6
6060 10:02:16.941848 Vio18 = 0
6061 10:02:16.945554 Vcore = 650000
6062 10:02:16.946115 Vdram = 0
6063 10:02:16.946484 Vddq = 0
6064 10:02:16.948326 Vmddr = 0
6065 10:02:16.951765 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6066 10:02:16.957875 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6067 10:02:16.958348 MEM_TYPE=3, freq_sel=20
6068 10:02:16.962197 sv_algorithm_assistance_LP4_800
6069 10:02:16.964512 ============ PULL DRAM RESETB DOWN ============
6070 10:02:16.971097 ========== PULL DRAM RESETB DOWN end =========
6071 10:02:16.974816 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6072 10:02:16.978246 ===================================
6073 10:02:16.981002 LPDDR4 DRAM CONFIGURATION
6074 10:02:16.984208 ===================================
6075 10:02:16.984766 EX_ROW_EN[0] = 0x0
6076 10:02:16.988307 EX_ROW_EN[1] = 0x0
6077 10:02:16.991095 LP4Y_EN = 0x0
6078 10:02:16.991510 WORK_FSP = 0x0
6079 10:02:16.994201 WL = 0x2
6080 10:02:16.994615 RL = 0x2
6081 10:02:16.997739 BL = 0x2
6082 10:02:16.998157 RPST = 0x0
6083 10:02:17.001443 RD_PRE = 0x0
6084 10:02:17.001863 WR_PRE = 0x1
6085 10:02:17.004076 WR_PST = 0x0
6086 10:02:17.004495 DBI_WR = 0x0
6087 10:02:17.007355 DBI_RD = 0x0
6088 10:02:17.007769 OTF = 0x1
6089 10:02:17.010622 ===================================
6090 10:02:17.014272 ===================================
6091 10:02:17.017195 ANA top config
6092 10:02:17.020387 ===================================
6093 10:02:17.023651 DLL_ASYNC_EN = 0
6094 10:02:17.024095 ALL_SLAVE_EN = 1
6095 10:02:17.026956 NEW_RANK_MODE = 1
6096 10:02:17.030295 DLL_IDLE_MODE = 1
6097 10:02:17.034247 LP45_APHY_COMB_EN = 1
6098 10:02:17.034665 TX_ODT_DIS = 1
6099 10:02:17.037064 NEW_8X_MODE = 1
6100 10:02:17.040320 ===================================
6101 10:02:17.043642 ===================================
6102 10:02:17.047230 data_rate = 800
6103 10:02:17.050322 CKR = 1
6104 10:02:17.053586 DQ_P2S_RATIO = 4
6105 10:02:17.056676 ===================================
6106 10:02:17.060145 CA_P2S_RATIO = 4
6107 10:02:17.060582 DQ_CA_OPEN = 0
6108 10:02:17.063573 DQ_SEMI_OPEN = 1
6109 10:02:17.067153 CA_SEMI_OPEN = 1
6110 10:02:17.070302 CA_FULL_RATE = 0
6111 10:02:17.073354 DQ_CKDIV4_EN = 0
6112 10:02:17.076640 CA_CKDIV4_EN = 1
6113 10:02:17.077114 CA_PREDIV_EN = 0
6114 10:02:17.079997 PH8_DLY = 0
6115 10:02:17.082993 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6116 10:02:17.086684 DQ_AAMCK_DIV = 0
6117 10:02:17.089831 CA_AAMCK_DIV = 0
6118 10:02:17.092825 CA_ADMCK_DIV = 4
6119 10:02:17.096398 DQ_TRACK_CA_EN = 0
6120 10:02:17.096984 CA_PICK = 800
6121 10:02:17.099555 CA_MCKIO = 400
6122 10:02:17.102769 MCKIO_SEMI = 400
6123 10:02:17.106143 PLL_FREQ = 3016
6124 10:02:17.109242 DQ_UI_PI_RATIO = 32
6125 10:02:17.112732 CA_UI_PI_RATIO = 32
6126 10:02:17.116006 ===================================
6127 10:02:17.119548 ===================================
6128 10:02:17.122503 memory_type:LPDDR4
6129 10:02:17.122918 GP_NUM : 10
6130 10:02:17.125740 SRAM_EN : 1
6131 10:02:17.126155 MD32_EN : 0
6132 10:02:17.129235 ===================================
6133 10:02:17.132109 [ANA_INIT] >>>>>>>>>>>>>>
6134 10:02:17.135517 <<<<<< [CONFIGURE PHASE]: ANA_TX
6135 10:02:17.139108 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6136 10:02:17.142433 ===================================
6137 10:02:17.145599 data_rate = 800,PCW = 0X7400
6138 10:02:17.149041 ===================================
6139 10:02:17.151798 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6140 10:02:17.158441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6141 10:02:17.168700 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6142 10:02:17.171671 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6143 10:02:17.178335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6144 10:02:17.181917 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6145 10:02:17.182029 [ANA_INIT] flow start
6146 10:02:17.185037 [ANA_INIT] PLL >>>>>>>>
6147 10:02:17.188147 [ANA_INIT] PLL <<<<<<<<
6148 10:02:17.188268 [ANA_INIT] MIDPI >>>>>>>>
6149 10:02:17.191349 [ANA_INIT] MIDPI <<<<<<<<
6150 10:02:17.194924 [ANA_INIT] DLL >>>>>>>>
6151 10:02:17.195011 [ANA_INIT] flow end
6152 10:02:17.201688 ============ LP4 DIFF to SE enter ============
6153 10:02:17.204688 ============ LP4 DIFF to SE exit ============
6154 10:02:17.204790 [ANA_INIT] <<<<<<<<<<<<<
6155 10:02:17.207799 [Flow] Enable top DCM control >>>>>
6156 10:02:17.211307 [Flow] Enable top DCM control <<<<<
6157 10:02:17.214849 Enable DLL master slave shuffle
6158 10:02:17.221175 ==============================================================
6159 10:02:17.224323 Gating Mode config
6160 10:02:17.227726 ==============================================================
6161 10:02:17.231301 Config description:
6162 10:02:17.240704 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6163 10:02:17.247309 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6164 10:02:17.250836 SELPH_MODE 0: By rank 1: By Phase
6165 10:02:17.257101 ==============================================================
6166 10:02:17.260997 GAT_TRACK_EN = 0
6167 10:02:17.263629 RX_GATING_MODE = 2
6168 10:02:17.267554 RX_GATING_TRACK_MODE = 2
6169 10:02:17.270697 SELPH_MODE = 1
6170 10:02:17.273951 PICG_EARLY_EN = 1
6171 10:02:17.274366 VALID_LAT_VALUE = 1
6172 10:02:17.280923 ==============================================================
6173 10:02:17.283951 Enter into Gating configuration >>>>
6174 10:02:17.287451 Exit from Gating configuration <<<<
6175 10:02:17.290753 Enter into DVFS_PRE_config >>>>>
6176 10:02:17.300763 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6177 10:02:17.303469 Exit from DVFS_PRE_config <<<<<
6178 10:02:17.307014 Enter into PICG configuration >>>>
6179 10:02:17.310165 Exit from PICG configuration <<<<
6180 10:02:17.313284 [RX_INPUT] configuration >>>>>
6181 10:02:17.316983 [RX_INPUT] configuration <<<<<
6182 10:02:17.323163 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6183 10:02:17.326663 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6184 10:02:17.333145 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6185 10:02:17.339824 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6186 10:02:17.346370 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6187 10:02:17.353068 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6188 10:02:17.356581 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6189 10:02:17.359685 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6190 10:02:17.362974 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6191 10:02:17.369405 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6192 10:02:17.372579 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6193 10:02:17.376329 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6194 10:02:17.380325 ===================================
6195 10:02:17.382712 LPDDR4 DRAM CONFIGURATION
6196 10:02:17.386190 ===================================
6197 10:02:17.389369 EX_ROW_EN[0] = 0x0
6198 10:02:17.389790 EX_ROW_EN[1] = 0x0
6199 10:02:17.392417 LP4Y_EN = 0x0
6200 10:02:17.392839 WORK_FSP = 0x0
6201 10:02:17.395977 WL = 0x2
6202 10:02:17.396427 RL = 0x2
6203 10:02:17.399307 BL = 0x2
6204 10:02:17.399724 RPST = 0x0
6205 10:02:17.402169 RD_PRE = 0x0
6206 10:02:17.402588 WR_PRE = 0x1
6207 10:02:17.406049 WR_PST = 0x0
6208 10:02:17.406543 DBI_WR = 0x0
6209 10:02:17.409566 DBI_RD = 0x0
6210 10:02:17.411937 OTF = 0x1
6211 10:02:17.415233 ===================================
6212 10:02:17.418177 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6213 10:02:17.421425 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6214 10:02:17.424633 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6215 10:02:17.427907 ===================================
6216 10:02:17.431322 LPDDR4 DRAM CONFIGURATION
6217 10:02:17.434726 ===================================
6218 10:02:17.437811 EX_ROW_EN[0] = 0x10
6219 10:02:17.437893 EX_ROW_EN[1] = 0x0
6220 10:02:17.441439 LP4Y_EN = 0x0
6221 10:02:17.441546 WORK_FSP = 0x0
6222 10:02:17.444901 WL = 0x2
6223 10:02:17.444975 RL = 0x2
6224 10:02:17.448247 BL = 0x2
6225 10:02:17.448316 RPST = 0x0
6226 10:02:17.451087 RD_PRE = 0x0
6227 10:02:17.451181 WR_PRE = 0x1
6228 10:02:17.454569 WR_PST = 0x0
6229 10:02:17.458014 DBI_WR = 0x0
6230 10:02:17.458090 DBI_RD = 0x0
6231 10:02:17.460941 OTF = 0x1
6232 10:02:17.464284 ===================================
6233 10:02:17.467424 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6234 10:02:17.473471 nWR fixed to 30
6235 10:02:17.476272 [ModeRegInit_LP4] CH0 RK0
6236 10:02:17.476353 [ModeRegInit_LP4] CH0 RK1
6237 10:02:17.479806 [ModeRegInit_LP4] CH1 RK0
6238 10:02:17.482913 [ModeRegInit_LP4] CH1 RK1
6239 10:02:17.482995 match AC timing 19
6240 10:02:17.489732 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6241 10:02:17.493151 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6242 10:02:17.496138 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6243 10:02:17.502534 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6244 10:02:17.505780 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6245 10:02:17.505862 ==
6246 10:02:17.509254 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 10:02:17.512247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 10:02:17.512329 ==
6249 10:02:17.519393 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6250 10:02:17.525690 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6251 10:02:17.529143 [CA 0] Center 36 (8~64) winsize 57
6252 10:02:17.532568 [CA 1] Center 36 (8~64) winsize 57
6253 10:02:17.536263 [CA 2] Center 36 (8~64) winsize 57
6254 10:02:17.538982 [CA 3] Center 36 (8~64) winsize 57
6255 10:02:17.542476 [CA 4] Center 36 (8~64) winsize 57
6256 10:02:17.545485 [CA 5] Center 36 (8~64) winsize 57
6257 10:02:17.545597
6258 10:02:17.548761 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6259 10:02:17.548859
6260 10:02:17.551955 [CATrainingPosCal] consider 1 rank data
6261 10:02:17.555524 u2DelayCellTimex100 = 270/100 ps
6262 10:02:17.558648 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 10:02:17.562112 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 10:02:17.564979 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 10:02:17.568187 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 10:02:17.571842 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 10:02:17.574741 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 10:02:17.574848
6269 10:02:17.581989 CA PerBit enable=1, Macro0, CA PI delay=36
6270 10:02:17.582074
6271 10:02:17.582143 [CBTSetCACLKResult] CA Dly = 36
6272 10:02:17.584695 CS Dly: 1 (0~32)
6273 10:02:17.584776 ==
6274 10:02:17.587917 Dram Type= 6, Freq= 0, CH_0, rank 1
6275 10:02:17.591941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 10:02:17.592026 ==
6277 10:02:17.598030 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6278 10:02:17.604438 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6279 10:02:17.607847 [CA 0] Center 36 (8~64) winsize 57
6280 10:02:17.611091 [CA 1] Center 36 (8~64) winsize 57
6281 10:02:17.614094 [CA 2] Center 36 (8~64) winsize 57
6282 10:02:17.617540 [CA 3] Center 36 (8~64) winsize 57
6283 10:02:17.620734 [CA 4] Center 36 (8~64) winsize 57
6284 10:02:17.620816 [CA 5] Center 36 (8~64) winsize 57
6285 10:02:17.624259
6286 10:02:17.627441 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6287 10:02:17.627523
6288 10:02:17.630898 [CATrainingPosCal] consider 2 rank data
6289 10:02:17.634456 u2DelayCellTimex100 = 270/100 ps
6290 10:02:17.637667 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 10:02:17.640661 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 10:02:17.643949 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 10:02:17.647201 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 10:02:17.650502 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 10:02:17.653932 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 10:02:17.654006
6297 10:02:17.657527 CA PerBit enable=1, Macro0, CA PI delay=36
6298 10:02:17.660862
6299 10:02:17.660969 [CBTSetCACLKResult] CA Dly = 36
6300 10:02:17.663463 CS Dly: 1 (0~32)
6301 10:02:17.663538
6302 10:02:17.667053 ----->DramcWriteLeveling(PI) begin...
6303 10:02:17.667154 ==
6304 10:02:17.670308 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 10:02:17.673472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 10:02:17.673547 ==
6307 10:02:17.676919 Write leveling (Byte 0): 40 => 8
6308 10:02:17.680240 Write leveling (Byte 1): 40 => 8
6309 10:02:17.683136 DramcWriteLeveling(PI) end<-----
6310 10:02:17.683211
6311 10:02:17.683282 ==
6312 10:02:17.686831 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 10:02:17.690615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 10:02:17.693337 ==
6315 10:02:17.693418 [Gating] SW mode calibration
6316 10:02:17.703053 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6317 10:02:17.706423 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6318 10:02:17.709836 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6319 10:02:17.716689 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6320 10:02:17.719820 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6321 10:02:17.722672 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6322 10:02:17.729325 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 10:02:17.732667 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 10:02:17.736170 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 10:02:17.742817 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 10:02:17.745819 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6327 10:02:17.749199 Total UI for P1: 0, mck2ui 16
6328 10:02:17.752287 best dqsien dly found for B0: ( 0, 14, 24)
6329 10:02:17.755574 Total UI for P1: 0, mck2ui 16
6330 10:02:17.759313 best dqsien dly found for B1: ( 0, 14, 24)
6331 10:02:17.762094 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6332 10:02:17.765431 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6333 10:02:17.765507
6334 10:02:17.768605 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6335 10:02:17.775512 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6336 10:02:17.775588 [Gating] SW calibration Done
6337 10:02:17.779063 ==
6338 10:02:17.779146 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 10:02:17.785237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 10:02:17.785320 ==
6341 10:02:17.785385 RX Vref Scan: 0
6342 10:02:17.785444
6343 10:02:17.788632 RX Vref 0 -> 0, step: 1
6344 10:02:17.788713
6345 10:02:17.791923 RX Delay -410 -> 252, step: 16
6346 10:02:17.795634 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6347 10:02:17.799119 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6348 10:02:17.805149 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6349 10:02:17.808756 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6350 10:02:17.811700 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6351 10:02:17.818402 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6352 10:02:17.821878 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6353 10:02:17.825143 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6354 10:02:17.828606 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6355 10:02:17.834828 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6356 10:02:17.838195 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6357 10:02:17.841369 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6358 10:02:17.844838 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6359 10:02:17.851340 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6360 10:02:17.854430 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6361 10:02:17.857888 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6362 10:02:17.857970 ==
6363 10:02:17.861291 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 10:02:17.867486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 10:02:17.867568 ==
6366 10:02:17.867647 DQS Delay:
6367 10:02:17.871099 DQS0 = 35, DQS1 = 59
6368 10:02:17.871179 DQM Delay:
6369 10:02:17.871244 DQM0 = 5, DQM1 = 17
6370 10:02:17.874299 DQ Delay:
6371 10:02:17.877648 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6372 10:02:17.877728 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6373 10:02:17.880784 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6374 10:02:17.884610 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6375 10:02:17.884690
6376 10:02:17.887218
6377 10:02:17.887297 ==
6378 10:02:17.890951 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 10:02:17.893875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 10:02:17.893955 ==
6381 10:02:17.894018
6382 10:02:17.894076
6383 10:02:17.897417 TX Vref Scan disable
6384 10:02:17.897497 == TX Byte 0 ==
6385 10:02:17.900385 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 10:02:17.907337 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 10:02:17.907431 == TX Byte 1 ==
6388 10:02:17.910575 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 10:02:17.916650 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 10:02:17.916730 ==
6391 10:02:17.919937 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 10:02:17.923893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 10:02:17.923963 ==
6394 10:02:17.924023
6395 10:02:17.924123
6396 10:02:17.926918 TX Vref Scan disable
6397 10:02:17.926985 == TX Byte 0 ==
6398 10:02:17.933342 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6399 10:02:17.936739 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6400 10:02:17.936828 == TX Byte 1 ==
6401 10:02:17.943184 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 10:02:17.946501 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 10:02:17.946570
6404 10:02:17.946630 [DATLAT]
6405 10:02:17.949620 Freq=400, CH0 RK0
6406 10:02:17.949692
6407 10:02:17.949750 DATLAT Default: 0xf
6408 10:02:17.952952 0, 0xFFFF, sum = 0
6409 10:02:17.953024 1, 0xFFFF, sum = 0
6410 10:02:17.956287 2, 0xFFFF, sum = 0
6411 10:02:17.956364 3, 0xFFFF, sum = 0
6412 10:02:17.959745 4, 0xFFFF, sum = 0
6413 10:02:17.959851 5, 0xFFFF, sum = 0
6414 10:02:17.962800 6, 0xFFFF, sum = 0
6415 10:02:17.962880 7, 0xFFFF, sum = 0
6416 10:02:17.966170 8, 0xFFFF, sum = 0
6417 10:02:17.969349 9, 0xFFFF, sum = 0
6418 10:02:17.969427 10, 0xFFFF, sum = 0
6419 10:02:17.973001 11, 0xFFFF, sum = 0
6420 10:02:17.973104 12, 0xFFFF, sum = 0
6421 10:02:17.976152 13, 0x0, sum = 1
6422 10:02:17.976226 14, 0x0, sum = 2
6423 10:02:17.979425 15, 0x0, sum = 3
6424 10:02:17.979528 16, 0x0, sum = 4
6425 10:02:17.979622 best_step = 14
6426 10:02:17.982424
6427 10:02:17.982522 ==
6428 10:02:17.985752 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 10:02:17.989006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 10:02:17.989072 ==
6431 10:02:17.989128 RX Vref Scan: 1
6432 10:02:17.989184
6433 10:02:17.992576 RX Vref 0 -> 0, step: 1
6434 10:02:17.992639
6435 10:02:17.995575 RX Delay -359 -> 252, step: 8
6436 10:02:17.995642
6437 10:02:17.998726 Set Vref, RX VrefLevel [Byte0]: 54
6438 10:02:18.002252 [Byte1]: 59
6439 10:02:18.006189
6440 10:02:18.006251 Final RX Vref Byte 0 = 54 to rank0
6441 10:02:18.009799 Final RX Vref Byte 1 = 59 to rank0
6442 10:02:18.013070 Final RX Vref Byte 0 = 54 to rank1
6443 10:02:18.016151 Final RX Vref Byte 1 = 59 to rank1==
6444 10:02:18.019675 Dram Type= 6, Freq= 0, CH_0, rank 0
6445 10:02:18.026216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 10:02:18.026289 ==
6447 10:02:18.026348 DQS Delay:
6448 10:02:18.029136 DQS0 = 44, DQS1 = 60
6449 10:02:18.029202 DQM Delay:
6450 10:02:18.032882 DQM0 = 11, DQM1 = 16
6451 10:02:18.032964 DQ Delay:
6452 10:02:18.035744 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6453 10:02:18.039708 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6454 10:02:18.042532 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6455 10:02:18.045953 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6456 10:02:18.046051
6457 10:02:18.046139
6458 10:02:18.052626 [DQSOSCAuto] RK0, (LSB)MR18= 0x968a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6459 10:02:18.055445 CH0 RK0: MR19=C0C, MR18=968A
6460 10:02:18.062171 CH0_RK0: MR19=0xC0C, MR18=0x968A, DQSOSC=391, MR23=63, INC=386, DEC=257
6461 10:02:18.062357 ==
6462 10:02:18.065362 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 10:02:18.068913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 10:02:18.069064 ==
6465 10:02:18.071872 [Gating] SW mode calibration
6466 10:02:18.078982 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6467 10:02:18.085257 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6468 10:02:18.088785 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6469 10:02:18.095649 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6470 10:02:18.098381 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6471 10:02:18.102172 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 10:02:18.108599 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 10:02:18.112241 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 10:02:18.114788 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 10:02:18.121363 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 10:02:18.124622 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 10:02:18.128086 Total UI for P1: 0, mck2ui 16
6478 10:02:18.131169 best dqsien dly found for B0: ( 0, 14, 24)
6479 10:02:18.134803 Total UI for P1: 0, mck2ui 16
6480 10:02:18.137698 best dqsien dly found for B1: ( 0, 14, 24)
6481 10:02:18.141016 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6482 10:02:18.144110 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6483 10:02:18.144244
6484 10:02:18.147547 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6485 10:02:18.150813 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6486 10:02:18.154455 [Gating] SW calibration Done
6487 10:02:18.154554 ==
6488 10:02:18.157450 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 10:02:18.163783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 10:02:18.163886 ==
6491 10:02:18.163985 RX Vref Scan: 0
6492 10:02:18.164105
6493 10:02:18.167107 RX Vref 0 -> 0, step: 1
6494 10:02:18.167178
6495 10:02:18.170973 RX Delay -410 -> 252, step: 16
6496 10:02:18.173720 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6497 10:02:18.177308 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6498 10:02:18.183884 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6499 10:02:18.186948 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6500 10:02:18.190474 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6501 10:02:18.193693 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6502 10:02:18.200365 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6503 10:02:18.203099 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6504 10:02:18.207174 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6505 10:02:18.210312 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6506 10:02:18.216319 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6507 10:02:18.219582 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6508 10:02:18.223074 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6509 10:02:18.229483 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6510 10:02:18.232678 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6511 10:02:18.236277 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6512 10:02:18.236545 ==
6513 10:02:18.239382 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 10:02:18.242812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 10:02:18.246616 ==
6516 10:02:18.246947 DQS Delay:
6517 10:02:18.247227 DQS0 = 35, DQS1 = 59
6518 10:02:18.249892 DQM Delay:
6519 10:02:18.250223 DQM0 = 9, DQM1 = 16
6520 10:02:18.252967 DQ Delay:
6521 10:02:18.253290 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6522 10:02:18.256014 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6523 10:02:18.259558 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6524 10:02:18.263049 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6525 10:02:18.263442
6526 10:02:18.263746
6527 10:02:18.264029 ==
6528 10:02:18.266037 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 10:02:18.272657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 10:02:18.273053 ==
6531 10:02:18.273445
6532 10:02:18.273813
6533 10:02:18.275872 TX Vref Scan disable
6534 10:02:18.276304 == TX Byte 0 ==
6535 10:02:18.278972 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6536 10:02:18.283309 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6537 10:02:18.285836 == TX Byte 1 ==
6538 10:02:18.289755 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6539 10:02:18.292678 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6540 10:02:18.295221 ==
6541 10:02:18.298965 Dram Type= 6, Freq= 0, CH_0, rank 1
6542 10:02:18.301667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6543 10:02:18.301749 ==
6544 10:02:18.301813
6545 10:02:18.301873
6546 10:02:18.305259 TX Vref Scan disable
6547 10:02:18.305340 == TX Byte 0 ==
6548 10:02:18.308382 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6549 10:02:18.314958 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6550 10:02:18.315039 == TX Byte 1 ==
6551 10:02:18.318332 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6552 10:02:18.324587 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6553 10:02:18.324665
6554 10:02:18.324726 [DATLAT]
6555 10:02:18.324786 Freq=400, CH0 RK1
6556 10:02:18.324843
6557 10:02:18.328600 DATLAT Default: 0xe
6558 10:02:18.331605 0, 0xFFFF, sum = 0
6559 10:02:18.331689 1, 0xFFFF, sum = 0
6560 10:02:18.334983 2, 0xFFFF, sum = 0
6561 10:02:18.335066 3, 0xFFFF, sum = 0
6562 10:02:18.338175 4, 0xFFFF, sum = 0
6563 10:02:18.338258 5, 0xFFFF, sum = 0
6564 10:02:18.341309 6, 0xFFFF, sum = 0
6565 10:02:18.341393 7, 0xFFFF, sum = 0
6566 10:02:18.344638 8, 0xFFFF, sum = 0
6567 10:02:18.344721 9, 0xFFFF, sum = 0
6568 10:02:18.348135 10, 0xFFFF, sum = 0
6569 10:02:18.348219 11, 0xFFFF, sum = 0
6570 10:02:18.350936 12, 0xFFFF, sum = 0
6571 10:02:18.351018 13, 0x0, sum = 1
6572 10:02:18.354543 14, 0x0, sum = 2
6573 10:02:18.354626 15, 0x0, sum = 3
6574 10:02:18.357953 16, 0x0, sum = 4
6575 10:02:18.358040 best_step = 14
6576 10:02:18.358105
6577 10:02:18.358165 ==
6578 10:02:18.360869 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 10:02:18.367225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 10:02:18.367312 ==
6581 10:02:18.367396 RX Vref Scan: 0
6582 10:02:18.367474
6583 10:02:18.371066 RX Vref 0 -> 0, step: 1
6584 10:02:18.371165
6585 10:02:18.373751 RX Delay -359 -> 252, step: 8
6586 10:02:18.380627 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6587 10:02:18.383655 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6588 10:02:18.387276 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6589 10:02:18.393740 iDelay=217, Bit 3, Center -36 (-271 ~ 200) 472
6590 10:02:18.396947 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6591 10:02:18.400318 iDelay=217, Bit 5, Center -44 (-279 ~ 192) 472
6592 10:02:18.403640 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6593 10:02:18.410484 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6594 10:02:18.413438 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6595 10:02:18.416722 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6596 10:02:18.420534 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6597 10:02:18.426635 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6598 10:02:18.429865 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6599 10:02:18.433281 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6600 10:02:18.439666 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6601 10:02:18.442905 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6602 10:02:18.442987 ==
6603 10:02:18.446697 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 10:02:18.449765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 10:02:18.449842 ==
6606 10:02:18.453243 DQS Delay:
6607 10:02:18.453323 DQS0 = 44, DQS1 = 60
6608 10:02:18.453407 DQM Delay:
6609 10:02:18.456231 DQM0 = 10, DQM1 = 16
6610 10:02:18.456303 DQ Delay:
6611 10:02:18.459396 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6612 10:02:18.462524 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6613 10:02:18.466427 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6614 10:02:18.469168 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6615 10:02:18.469295
6616 10:02:18.469420
6617 10:02:18.479044 [DQSOSCAuto] RK1, (LSB)MR18= 0x867e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6618 10:02:18.479187 CH0 RK1: MR19=C0C, MR18=867E
6619 10:02:18.485515 CH0_RK1: MR19=0xC0C, MR18=0x867E, DQSOSC=393, MR23=63, INC=382, DEC=254
6620 10:02:18.489270 [RxdqsGatingPostProcess] freq 400
6621 10:02:18.495923 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6622 10:02:18.498989 best DQS0 dly(2T, 0.5T) = (0, 10)
6623 10:02:18.502317 best DQS1 dly(2T, 0.5T) = (0, 10)
6624 10:02:18.505290 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6625 10:02:18.508454 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6626 10:02:18.511955 best DQS0 dly(2T, 0.5T) = (0, 10)
6627 10:02:18.514989 best DQS1 dly(2T, 0.5T) = (0, 10)
6628 10:02:18.518348 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6629 10:02:18.521612 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6630 10:02:18.525334 Pre-setting of DQS Precalculation
6631 10:02:18.528632 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6632 10:02:18.528715 ==
6633 10:02:18.531811 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 10:02:18.535017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 10:02:18.535137 ==
6636 10:02:18.541607 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6637 10:02:18.548127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6638 10:02:18.551757 [CA 0] Center 36 (8~64) winsize 57
6639 10:02:18.554696 [CA 1] Center 36 (8~64) winsize 57
6640 10:02:18.557722 [CA 2] Center 36 (8~64) winsize 57
6641 10:02:18.561018 [CA 3] Center 36 (8~64) winsize 57
6642 10:02:18.564311 [CA 4] Center 36 (8~64) winsize 57
6643 10:02:18.567766 [CA 5] Center 36 (8~64) winsize 57
6644 10:02:18.567877
6645 10:02:18.571506 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6646 10:02:18.571614
6647 10:02:18.574543 [CATrainingPosCal] consider 1 rank data
6648 10:02:18.578040 u2DelayCellTimex100 = 270/100 ps
6649 10:02:18.581088 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 10:02:18.584573 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 10:02:18.587604 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 10:02:18.590968 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 10:02:18.595039 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 10:02:18.597283 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 10:02:18.597355
6656 10:02:18.604073 CA PerBit enable=1, Macro0, CA PI delay=36
6657 10:02:18.604156
6658 10:02:18.607479 [CBTSetCACLKResult] CA Dly = 36
6659 10:02:18.607575 CS Dly: 1 (0~32)
6660 10:02:18.607654 ==
6661 10:02:18.610407 Dram Type= 6, Freq= 0, CH_1, rank 1
6662 10:02:18.613938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 10:02:18.614038 ==
6664 10:02:18.620697 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6665 10:02:18.627028 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6666 10:02:18.630892 [CA 0] Center 36 (8~64) winsize 57
6667 10:02:18.633819 [CA 1] Center 36 (8~64) winsize 57
6668 10:02:18.637332 [CA 2] Center 36 (8~64) winsize 57
6669 10:02:18.640797 [CA 3] Center 36 (8~64) winsize 57
6670 10:02:18.643570 [CA 4] Center 36 (8~64) winsize 57
6671 10:02:18.643640 [CA 5] Center 36 (8~64) winsize 57
6672 10:02:18.646781
6673 10:02:18.650295 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6674 10:02:18.650376
6675 10:02:18.653820 [CATrainingPosCal] consider 2 rank data
6676 10:02:18.656932 u2DelayCellTimex100 = 270/100 ps
6677 10:02:18.659893 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 10:02:18.663608 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 10:02:18.666484 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 10:02:18.670053 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 10:02:18.673372 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 10:02:18.676308 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 10:02:18.676385
6684 10:02:18.682798 CA PerBit enable=1, Macro0, CA PI delay=36
6685 10:02:18.682899
6686 10:02:18.682988 [CBTSetCACLKResult] CA Dly = 36
6687 10:02:18.686366 CS Dly: 1 (0~32)
6688 10:02:18.686450
6689 10:02:18.689701 ----->DramcWriteLeveling(PI) begin...
6690 10:02:18.689777 ==
6691 10:02:18.692716 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 10:02:18.696136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 10:02:18.696208 ==
6694 10:02:18.699399 Write leveling (Byte 0): 40 => 8
6695 10:02:18.703037 Write leveling (Byte 1): 40 => 8
6696 10:02:18.706069 DramcWriteLeveling(PI) end<-----
6697 10:02:18.706141
6698 10:02:18.706201 ==
6699 10:02:18.709435 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 10:02:18.716143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 10:02:18.716241 ==
6702 10:02:18.716334 [Gating] SW mode calibration
6703 10:02:18.726017 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6704 10:02:18.728782 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6705 10:02:18.732692 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6706 10:02:18.738917 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6707 10:02:18.742199 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6708 10:02:18.745672 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6709 10:02:18.752587 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 10:02:18.755471 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 10:02:18.758708 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 10:02:18.765515 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 10:02:18.768941 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6714 10:02:18.772066 Total UI for P1: 0, mck2ui 16
6715 10:02:18.775689 best dqsien dly found for B0: ( 0, 14, 24)
6716 10:02:18.778773 Total UI for P1: 0, mck2ui 16
6717 10:02:18.782056 best dqsien dly found for B1: ( 0, 14, 24)
6718 10:02:18.785375 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6719 10:02:18.788649 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6720 10:02:18.789065
6721 10:02:18.791772 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6722 10:02:18.798603 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6723 10:02:18.799023 [Gating] SW calibration Done
6724 10:02:18.802025 ==
6725 10:02:18.802444 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 10:02:18.808992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 10:02:18.809447 ==
6728 10:02:18.809800 RX Vref Scan: 0
6729 10:02:18.810124
6730 10:02:18.811869 RX Vref 0 -> 0, step: 1
6731 10:02:18.812321
6732 10:02:18.815030 RX Delay -410 -> 252, step: 16
6733 10:02:18.818408 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6734 10:02:18.821748 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6735 10:02:18.828285 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6736 10:02:18.831724 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6737 10:02:18.834945 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6738 10:02:18.838309 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6739 10:02:18.845025 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6740 10:02:18.848095 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6741 10:02:18.851254 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6742 10:02:18.854807 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6743 10:02:18.861404 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6744 10:02:18.864921 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6745 10:02:18.867811 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6746 10:02:18.874476 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6747 10:02:18.877972 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6748 10:02:18.880934 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6749 10:02:18.881312 ==
6750 10:02:18.884082 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 10:02:18.887316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 10:02:18.890984 ==
6753 10:02:18.891281 DQS Delay:
6754 10:02:18.891517 DQS0 = 43, DQS1 = 51
6755 10:02:18.894321 DQM Delay:
6756 10:02:18.894633 DQM0 = 13, DQM1 = 13
6757 10:02:18.897550 DQ Delay:
6758 10:02:18.900615 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6759 10:02:18.900945 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6760 10:02:18.903593 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6761 10:02:18.907387 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6762 10:02:18.907684
6763 10:02:18.907919
6764 10:02:18.910405 ==
6765 10:02:18.913826 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 10:02:18.916885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 10:02:18.917299 ==
6768 10:02:18.917652
6769 10:02:18.917979
6770 10:02:18.920566 TX Vref Scan disable
6771 10:02:18.920864 == TX Byte 0 ==
6772 10:02:18.923743 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 10:02:18.930316 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 10:02:18.930616 == TX Byte 1 ==
6775 10:02:18.933582 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 10:02:18.940218 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 10:02:18.940512 ==
6778 10:02:18.943504 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 10:02:18.946415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 10:02:18.946766 ==
6781 10:02:18.947001
6782 10:02:18.947270
6783 10:02:18.949958 TX Vref Scan disable
6784 10:02:18.950439 == TX Byte 0 ==
6785 10:02:18.956678 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 10:02:18.959609 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 10:02:18.960219 == TX Byte 1 ==
6788 10:02:18.966614 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 10:02:18.969881 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 10:02:18.970297
6791 10:02:18.970620 [DATLAT]
6792 10:02:18.973271 Freq=400, CH1 RK0
6793 10:02:18.973788
6794 10:02:18.974116 DATLAT Default: 0xf
6795 10:02:18.976313 0, 0xFFFF, sum = 0
6796 10:02:18.976733 1, 0xFFFF, sum = 0
6797 10:02:18.979614 2, 0xFFFF, sum = 0
6798 10:02:18.980116 3, 0xFFFF, sum = 0
6799 10:02:18.982776 4, 0xFFFF, sum = 0
6800 10:02:18.983202 5, 0xFFFF, sum = 0
6801 10:02:18.986432 6, 0xFFFF, sum = 0
6802 10:02:18.986913 7, 0xFFFF, sum = 0
6803 10:02:18.989471 8, 0xFFFF, sum = 0
6804 10:02:18.990005 9, 0xFFFF, sum = 0
6805 10:02:18.993203 10, 0xFFFF, sum = 0
6806 10:02:18.996137 11, 0xFFFF, sum = 0
6807 10:02:18.996666 12, 0xFFFF, sum = 0
6808 10:02:18.999291 13, 0x0, sum = 1
6809 10:02:18.999720 14, 0x0, sum = 2
6810 10:02:19.003369 15, 0x0, sum = 3
6811 10:02:19.003902 16, 0x0, sum = 4
6812 10:02:19.004315 best_step = 14
6813 10:02:19.004633
6814 10:02:19.006411 ==
6815 10:02:19.008886 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 10:02:19.012670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 10:02:19.013094 ==
6818 10:02:19.013428 RX Vref Scan: 1
6819 10:02:19.013737
6820 10:02:19.016233 RX Vref 0 -> 0, step: 1
6821 10:02:19.016676
6822 10:02:19.019390 RX Delay -343 -> 252, step: 8
6823 10:02:19.019959
6824 10:02:19.022329 Set Vref, RX VrefLevel [Byte0]: 52
6825 10:02:19.025840 [Byte1]: 53
6826 10:02:19.029223
6827 10:02:19.029668 Final RX Vref Byte 0 = 52 to rank0
6828 10:02:19.032829 Final RX Vref Byte 1 = 53 to rank0
6829 10:02:19.035986 Final RX Vref Byte 0 = 52 to rank1
6830 10:02:19.039296 Final RX Vref Byte 1 = 53 to rank1==
6831 10:02:19.042706 Dram Type= 6, Freq= 0, CH_1, rank 0
6832 10:02:19.048947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 10:02:19.049373 ==
6834 10:02:19.049746 DQS Delay:
6835 10:02:19.052434 DQS0 = 44, DQS1 = 52
6836 10:02:19.053017 DQM Delay:
6837 10:02:19.053395 DQM0 = 11, DQM1 = 12
6838 10:02:19.055808 DQ Delay:
6839 10:02:19.058762 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6840 10:02:19.062240 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6841 10:02:19.062740 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6842 10:02:19.068906 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =16
6843 10:02:19.069350
6844 10:02:19.069707
6845 10:02:19.075294 [DQSOSCAuto] RK0, (LSB)MR18= 0x648b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6846 10:02:19.078759 CH1 RK0: MR19=C0C, MR18=648B
6847 10:02:19.085570 CH1_RK0: MR19=0xC0C, MR18=0x648B, DQSOSC=392, MR23=63, INC=384, DEC=256
6848 10:02:19.085993 ==
6849 10:02:19.089008 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 10:02:19.092302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 10:02:19.092838 ==
6852 10:02:19.095195 [Gating] SW mode calibration
6853 10:02:19.101833 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6854 10:02:19.108282 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6855 10:02:19.111618 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6856 10:02:19.114808 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6857 10:02:19.121716 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6858 10:02:19.124705 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6859 10:02:19.127679 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 10:02:19.134577 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 10:02:19.137808 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 10:02:19.141044 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 10:02:19.147879 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6864 10:02:19.151157 Total UI for P1: 0, mck2ui 16
6865 10:02:19.154065 best dqsien dly found for B0: ( 0, 14, 24)
6866 10:02:19.154148 Total UI for P1: 0, mck2ui 16
6867 10:02:19.161048 best dqsien dly found for B1: ( 0, 14, 24)
6868 10:02:19.164060 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6869 10:02:19.167383 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6870 10:02:19.167479
6871 10:02:19.171273 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6872 10:02:19.173600 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6873 10:02:19.177164 [Gating] SW calibration Done
6874 10:02:19.177245 ==
6875 10:02:19.180725 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 10:02:19.183653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 10:02:19.183762 ==
6878 10:02:19.187067 RX Vref Scan: 0
6879 10:02:19.187172
6880 10:02:19.190448 RX Vref 0 -> 0, step: 1
6881 10:02:19.190528
6882 10:02:19.190592 RX Delay -410 -> 252, step: 16
6883 10:02:19.197557 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6884 10:02:19.200827 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6885 10:02:19.203819 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6886 10:02:19.211058 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6887 10:02:19.213949 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6888 10:02:19.217204 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6889 10:02:19.220374 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6890 10:02:19.227157 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6891 10:02:19.230179 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6892 10:02:19.233369 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6893 10:02:19.236977 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6894 10:02:19.243662 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6895 10:02:19.246702 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6896 10:02:19.250014 iDelay=230, Bit 13, Center -19 (-266 ~ 229) 496
6897 10:02:19.253553 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6898 10:02:19.260066 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6899 10:02:19.260499 ==
6900 10:02:19.263260 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 10:02:19.266830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 10:02:19.267256 ==
6903 10:02:19.269792 DQS Delay:
6904 10:02:19.270334 DQS0 = 43, DQS1 = 51
6905 10:02:19.270817 DQM Delay:
6906 10:02:19.273711 DQM0 = 11, DQM1 = 16
6907 10:02:19.274168 DQ Delay:
6908 10:02:19.276701 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6909 10:02:19.279788 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6910 10:02:19.283281 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6911 10:02:19.286523 DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =24
6912 10:02:19.286952
6913 10:02:19.287295
6914 10:02:19.287683 ==
6915 10:02:19.290062 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 10:02:19.293334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 10:02:19.293795 ==
6918 10:02:19.296765
6919 10:02:19.297172
6920 10:02:19.297494 TX Vref Scan disable
6921 10:02:19.300106 == TX Byte 0 ==
6922 10:02:19.302982 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6923 10:02:19.306333 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6924 10:02:19.309571 == TX Byte 1 ==
6925 10:02:19.313480 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6926 10:02:19.316689 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6927 10:02:19.317203 ==
6928 10:02:19.319627 Dram Type= 6, Freq= 0, CH_1, rank 1
6929 10:02:19.322921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6930 10:02:19.326217 ==
6931 10:02:19.326756
6932 10:02:19.327180
6933 10:02:19.327513 TX Vref Scan disable
6934 10:02:19.329263 == TX Byte 0 ==
6935 10:02:19.332726 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6936 10:02:19.336394 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6937 10:02:19.339272 == TX Byte 1 ==
6938 10:02:19.342405 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6939 10:02:19.345989 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6940 10:02:19.346483
6941 10:02:19.348898 [DATLAT]
6942 10:02:19.349347 Freq=400, CH1 RK1
6943 10:02:19.349678
6944 10:02:19.352639 DATLAT Default: 0xe
6945 10:02:19.353125 0, 0xFFFF, sum = 0
6946 10:02:19.355654 1, 0xFFFF, sum = 0
6947 10:02:19.356133 2, 0xFFFF, sum = 0
6948 10:02:19.359061 3, 0xFFFF, sum = 0
6949 10:02:19.359643 4, 0xFFFF, sum = 0
6950 10:02:19.362224 5, 0xFFFF, sum = 0
6951 10:02:19.362645 6, 0xFFFF, sum = 0
6952 10:02:19.366138 7, 0xFFFF, sum = 0
6953 10:02:19.366659 8, 0xFFFF, sum = 0
6954 10:02:19.369639 9, 0xFFFF, sum = 0
6955 10:02:19.370162 10, 0xFFFF, sum = 0
6956 10:02:19.372415 11, 0xFFFF, sum = 0
6957 10:02:19.375599 12, 0xFFFF, sum = 0
6958 10:02:19.376019 13, 0x0, sum = 1
6959 10:02:19.376384 14, 0x0, sum = 2
6960 10:02:19.379215 15, 0x0, sum = 3
6961 10:02:19.379702 16, 0x0, sum = 4
6962 10:02:19.381982 best_step = 14
6963 10:02:19.382481
6964 10:02:19.382812 ==
6965 10:02:19.385798 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 10:02:19.388858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 10:02:19.389333 ==
6968 10:02:19.391839 RX Vref Scan: 0
6969 10:02:19.392286
6970 10:02:19.392616 RX Vref 0 -> 0, step: 1
6971 10:02:19.395249
6972 10:02:19.395657 RX Delay -343 -> 252, step: 8
6973 10:02:19.403524 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6974 10:02:19.406968 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6975 10:02:19.410470 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6976 10:02:19.416587 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6977 10:02:19.420103 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6978 10:02:19.424224 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6979 10:02:19.426838 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6980 10:02:19.433174 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6981 10:02:19.436668 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6982 10:02:19.440211 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6983 10:02:19.443405 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6984 10:02:19.450281 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6985 10:02:19.452847 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6986 10:02:19.456686 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6987 10:02:19.459597 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6988 10:02:19.466667 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6989 10:02:19.467228 ==
6990 10:02:19.469816 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 10:02:19.472945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 10:02:19.473410 ==
6993 10:02:19.476126 DQS Delay:
6994 10:02:19.476583 DQS0 = 48, DQS1 = 52
6995 10:02:19.476944 DQM Delay:
6996 10:02:19.479840 DQM0 = 12, DQM1 = 9
6997 10:02:19.480342 DQ Delay:
6998 10:02:19.482987 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6999 10:02:19.485902 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
7000 10:02:19.489346 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7001 10:02:19.492485 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7002 10:02:19.492900
7003 10:02:19.493222
7004 10:02:19.502408 [DQSOSCAuto] RK1, (LSB)MR18= 0x6ca5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
7005 10:02:19.502896 CH1 RK1: MR19=C0C, MR18=6CA5
7006 10:02:19.509100 CH1_RK1: MR19=0xC0C, MR18=0x6CA5, DQSOSC=389, MR23=63, INC=390, DEC=260
7007 10:02:19.512731 [RxdqsGatingPostProcess] freq 400
7008 10:02:19.519381 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7009 10:02:19.522177 best DQS0 dly(2T, 0.5T) = (0, 10)
7010 10:02:19.525946 best DQS1 dly(2T, 0.5T) = (0, 10)
7011 10:02:19.529179 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7012 10:02:19.532253 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7013 10:02:19.535424 best DQS0 dly(2T, 0.5T) = (0, 10)
7014 10:02:19.538847 best DQS1 dly(2T, 0.5T) = (0, 10)
7015 10:02:19.542967 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7016 10:02:19.545575 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7017 10:02:19.546143 Pre-setting of DQS Precalculation
7018 10:02:19.551602 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7019 10:02:19.558284 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7020 10:02:19.565166 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7021 10:02:19.565628
7022 10:02:19.565982
7023 10:02:19.568202 [Calibration Summary] 800 Mbps
7024 10:02:19.571801 CH 0, Rank 0
7025 10:02:19.572396 SW Impedance : PASS
7026 10:02:19.574850 DUTY Scan : NO K
7027 10:02:19.578356 ZQ Calibration : PASS
7028 10:02:19.578921 Jitter Meter : NO K
7029 10:02:19.581204 CBT Training : PASS
7030 10:02:19.584508 Write leveling : PASS
7031 10:02:19.584968 RX DQS gating : PASS
7032 10:02:19.587766 RX DQ/DQS(RDDQC) : PASS
7033 10:02:19.591159 TX DQ/DQS : PASS
7034 10:02:19.591619 RX DATLAT : PASS
7035 10:02:19.595167 RX DQ/DQS(Engine): PASS
7036 10:02:19.598019 TX OE : NO K
7037 10:02:19.598533 All Pass.
7038 10:02:19.598868
7039 10:02:19.599175 CH 0, Rank 1
7040 10:02:19.601031 SW Impedance : PASS
7041 10:02:19.604357 DUTY Scan : NO K
7042 10:02:19.604871 ZQ Calibration : PASS
7043 10:02:19.607775 Jitter Meter : NO K
7044 10:02:19.611105 CBT Training : PASS
7045 10:02:19.611615 Write leveling : NO K
7046 10:02:19.614456 RX DQS gating : PASS
7047 10:02:19.618207 RX DQ/DQS(RDDQC) : PASS
7048 10:02:19.618620 TX DQ/DQS : PASS
7049 10:02:19.621134 RX DATLAT : PASS
7050 10:02:19.621671 RX DQ/DQS(Engine): PASS
7051 10:02:19.624644 TX OE : NO K
7052 10:02:19.625160 All Pass.
7053 10:02:19.625492
7054 10:02:19.627205 CH 1, Rank 0
7055 10:02:19.630947 SW Impedance : PASS
7056 10:02:19.631463 DUTY Scan : NO K
7057 10:02:19.634387 ZQ Calibration : PASS
7058 10:02:19.634909 Jitter Meter : NO K
7059 10:02:19.637381 CBT Training : PASS
7060 10:02:19.640675 Write leveling : PASS
7061 10:02:19.641191 RX DQS gating : PASS
7062 10:02:19.644147 RX DQ/DQS(RDDQC) : PASS
7063 10:02:19.647301 TX DQ/DQS : PASS
7064 10:02:19.647818 RX DATLAT : PASS
7065 10:02:19.650330 RX DQ/DQS(Engine): PASS
7066 10:02:19.653781 TX OE : NO K
7067 10:02:19.654300 All Pass.
7068 10:02:19.654630
7069 10:02:19.654930 CH 1, Rank 1
7070 10:02:19.656961 SW Impedance : PASS
7071 10:02:19.660465 DUTY Scan : NO K
7072 10:02:19.660897 ZQ Calibration : PASS
7073 10:02:19.663479 Jitter Meter : NO K
7074 10:02:19.666998 CBT Training : PASS
7075 10:02:19.667559 Write leveling : NO K
7076 10:02:19.670015 RX DQS gating : PASS
7077 10:02:19.673943 RX DQ/DQS(RDDQC) : PASS
7078 10:02:19.674395 TX DQ/DQS : PASS
7079 10:02:19.676766 RX DATLAT : PASS
7080 10:02:19.679805 RX DQ/DQS(Engine): PASS
7081 10:02:19.680320 TX OE : NO K
7082 10:02:19.683165 All Pass.
7083 10:02:19.683627
7084 10:02:19.683956 DramC Write-DBI off
7085 10:02:19.686875 PER_BANK_REFRESH: Hybrid Mode
7086 10:02:19.687499 TX_TRACKING: ON
7087 10:02:19.696236 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7088 10:02:19.700017 [FAST_K] Save calibration result to emmc
7089 10:02:19.703164 dramc_set_vcore_voltage set vcore to 725000
7090 10:02:19.706413 Read voltage for 1600, 0
7091 10:02:19.706842 Vio18 = 0
7092 10:02:19.710190 Vcore = 725000
7093 10:02:19.710612 Vdram = 0
7094 10:02:19.710945 Vddq = 0
7095 10:02:19.712713 Vmddr = 0
7096 10:02:19.716357 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7097 10:02:19.723061 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7098 10:02:19.723485 MEM_TYPE=3, freq_sel=13
7099 10:02:19.726189 sv_algorithm_assistance_LP4_3733
7100 10:02:19.733060 ============ PULL DRAM RESETB DOWN ============
7101 10:02:19.736131 ========== PULL DRAM RESETB DOWN end =========
7102 10:02:19.739273 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7103 10:02:19.742902 ===================================
7104 10:02:19.745501 LPDDR4 DRAM CONFIGURATION
7105 10:02:19.749334 ===================================
7106 10:02:19.752556 EX_ROW_EN[0] = 0x0
7107 10:02:19.752979 EX_ROW_EN[1] = 0x0
7108 10:02:19.755641 LP4Y_EN = 0x0
7109 10:02:19.756110 WORK_FSP = 0x1
7110 10:02:19.758880 WL = 0x5
7111 10:02:19.759302 RL = 0x5
7112 10:02:19.762787 BL = 0x2
7113 10:02:19.763366 RPST = 0x0
7114 10:02:19.765820 RD_PRE = 0x0
7115 10:02:19.766425 WR_PRE = 0x1
7116 10:02:19.768670 WR_PST = 0x1
7117 10:02:19.769117 DBI_WR = 0x0
7118 10:02:19.771882 DBI_RD = 0x0
7119 10:02:19.772347 OTF = 0x1
7120 10:02:19.775166 ===================================
7121 10:02:19.778378 ===================================
7122 10:02:19.781820 ANA top config
7123 10:02:19.785219 ===================================
7124 10:02:19.788399 DLL_ASYNC_EN = 0
7125 10:02:19.788971 ALL_SLAVE_EN = 0
7126 10:02:19.791613 NEW_RANK_MODE = 1
7127 10:02:19.794711 DLL_IDLE_MODE = 1
7128 10:02:19.798278 LP45_APHY_COMB_EN = 1
7129 10:02:19.802024 TX_ODT_DIS = 0
7130 10:02:19.802458 NEW_8X_MODE = 1
7131 10:02:19.805085 ===================================
7132 10:02:19.808146 ===================================
7133 10:02:19.811493 data_rate = 3200
7134 10:02:19.814713 CKR = 1
7135 10:02:19.818333 DQ_P2S_RATIO = 8
7136 10:02:19.821497 ===================================
7137 10:02:19.824546 CA_P2S_RATIO = 8
7138 10:02:19.828272 DQ_CA_OPEN = 0
7139 10:02:19.828540 DQ_SEMI_OPEN = 0
7140 10:02:19.831348 CA_SEMI_OPEN = 0
7141 10:02:19.834708 CA_FULL_RATE = 0
7142 10:02:19.838339 DQ_CKDIV4_EN = 0
7143 10:02:19.841335 CA_CKDIV4_EN = 0
7144 10:02:19.845071 CA_PREDIV_EN = 0
7145 10:02:19.845298 PH8_DLY = 12
7146 10:02:19.847925 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7147 10:02:19.850885 DQ_AAMCK_DIV = 4
7148 10:02:19.854689 CA_AAMCK_DIV = 4
7149 10:02:19.857250 CA_ADMCK_DIV = 4
7150 10:02:19.860879 DQ_TRACK_CA_EN = 0
7151 10:02:19.863896 CA_PICK = 1600
7152 10:02:19.864035 CA_MCKIO = 1600
7153 10:02:19.867444 MCKIO_SEMI = 0
7154 10:02:19.870892 PLL_FREQ = 3068
7155 10:02:19.874027 DQ_UI_PI_RATIO = 32
7156 10:02:19.877748 CA_UI_PI_RATIO = 0
7157 10:02:19.880614 ===================================
7158 10:02:19.884209 ===================================
7159 10:02:19.886976 memory_type:LPDDR4
7160 10:02:19.887074 GP_NUM : 10
7161 10:02:19.890124 SRAM_EN : 1
7162 10:02:19.893983 MD32_EN : 0
7163 10:02:19.897198 ===================================
7164 10:02:19.897281 [ANA_INIT] >>>>>>>>>>>>>>
7165 10:02:19.900292 <<<<<< [CONFIGURE PHASE]: ANA_TX
7166 10:02:19.903374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7167 10:02:19.906734 ===================================
7168 10:02:19.909805 data_rate = 3200,PCW = 0X7600
7169 10:02:19.913081 ===================================
7170 10:02:19.916475 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7171 10:02:19.923347 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7172 10:02:19.926229 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7173 10:02:19.933045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7174 10:02:19.936499 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7175 10:02:19.939680 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7176 10:02:19.942941 [ANA_INIT] flow start
7177 10:02:19.943022 [ANA_INIT] PLL >>>>>>>>
7178 10:02:19.946585 [ANA_INIT] PLL <<<<<<<<
7179 10:02:19.949151 [ANA_INIT] MIDPI >>>>>>>>
7180 10:02:19.949232 [ANA_INIT] MIDPI <<<<<<<<
7181 10:02:19.952559 [ANA_INIT] DLL >>>>>>>>
7182 10:02:19.955669 [ANA_INIT] DLL <<<<<<<<
7183 10:02:19.955777 [ANA_INIT] flow end
7184 10:02:19.962512 ============ LP4 DIFF to SE enter ============
7185 10:02:19.965684 ============ LP4 DIFF to SE exit ============
7186 10:02:19.969557 [ANA_INIT] <<<<<<<<<<<<<
7187 10:02:19.972757 [Flow] Enable top DCM control >>>>>
7188 10:02:19.975448 [Flow] Enable top DCM control <<<<<
7189 10:02:19.975557 Enable DLL master slave shuffle
7190 10:02:19.982522 ==============================================================
7191 10:02:19.985925 Gating Mode config
7192 10:02:19.989056 ==============================================================
7193 10:02:19.992793 Config description:
7194 10:02:20.002103 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7195 10:02:20.008663 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7196 10:02:20.012635 SELPH_MODE 0: By rank 1: By Phase
7197 10:02:20.019337 ==============================================================
7198 10:02:20.022474 GAT_TRACK_EN = 1
7199 10:02:20.025344 RX_GATING_MODE = 2
7200 10:02:20.028648 RX_GATING_TRACK_MODE = 2
7201 10:02:20.032330 SELPH_MODE = 1
7202 10:02:20.035543 PICG_EARLY_EN = 1
7203 10:02:20.035958 VALID_LAT_VALUE = 1
7204 10:02:20.042463 ==============================================================
7205 10:02:20.045119 Enter into Gating configuration >>>>
7206 10:02:20.048650 Exit from Gating configuration <<<<
7207 10:02:20.052013 Enter into DVFS_PRE_config >>>>>
7208 10:02:20.061282 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7209 10:02:20.064948 Exit from DVFS_PRE_config <<<<<
7210 10:02:20.068219 Enter into PICG configuration >>>>
7211 10:02:20.071352 Exit from PICG configuration <<<<
7212 10:02:20.074956 [RX_INPUT] configuration >>>>>
7213 10:02:20.077882 [RX_INPUT] configuration <<<<<
7214 10:02:20.084703 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7215 10:02:20.087407 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7216 10:02:20.094030 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7217 10:02:20.100568 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7218 10:02:20.107469 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7219 10:02:20.113799 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7220 10:02:20.117496 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7221 10:02:20.120221 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7222 10:02:20.123669 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7223 10:02:20.130399 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7224 10:02:20.133635 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7225 10:02:20.137489 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7226 10:02:20.140420 ===================================
7227 10:02:20.143076 LPDDR4 DRAM CONFIGURATION
7228 10:02:20.146497 ===================================
7229 10:02:20.150269 EX_ROW_EN[0] = 0x0
7230 10:02:20.150350 EX_ROW_EN[1] = 0x0
7231 10:02:20.153647 LP4Y_EN = 0x0
7232 10:02:20.153800 WORK_FSP = 0x1
7233 10:02:20.156521 WL = 0x5
7234 10:02:20.156603 RL = 0x5
7235 10:02:20.160094 BL = 0x2
7236 10:02:20.160168 RPST = 0x0
7237 10:02:20.163282 RD_PRE = 0x0
7238 10:02:20.163363 WR_PRE = 0x1
7239 10:02:20.166363 WR_PST = 0x1
7240 10:02:20.166446 DBI_WR = 0x0
7241 10:02:20.169851 DBI_RD = 0x0
7242 10:02:20.169934 OTF = 0x1
7243 10:02:20.173009 ===================================
7244 10:02:20.179906 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7245 10:02:20.183545 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7246 10:02:20.186669 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7247 10:02:20.189992 ===================================
7248 10:02:20.193189 LPDDR4 DRAM CONFIGURATION
7249 10:02:20.196427 ===================================
7250 10:02:20.199415 EX_ROW_EN[0] = 0x10
7251 10:02:20.199493 EX_ROW_EN[1] = 0x0
7252 10:02:20.203172 LP4Y_EN = 0x0
7253 10:02:20.203249 WORK_FSP = 0x1
7254 10:02:20.206032 WL = 0x5
7255 10:02:20.206110 RL = 0x5
7256 10:02:20.209436 BL = 0x2
7257 10:02:20.209515 RPST = 0x0
7258 10:02:20.212860 RD_PRE = 0x0
7259 10:02:20.212940 WR_PRE = 0x1
7260 10:02:20.215911 WR_PST = 0x1
7261 10:02:20.219384 DBI_WR = 0x0
7262 10:02:20.219460 DBI_RD = 0x0
7263 10:02:20.222859 OTF = 0x1
7264 10:02:20.225725 ===================================
7265 10:02:20.229337 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7266 10:02:20.232689 ==
7267 10:02:20.236028 Dram Type= 6, Freq= 0, CH_0, rank 0
7268 10:02:20.239428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7269 10:02:20.239507 ==
7270 10:02:20.242623 [Duty_Offset_Calibration]
7271 10:02:20.242723 B0:2 B1:0 CA:4
7272 10:02:20.242806
7273 10:02:20.245563 [DutyScan_Calibration_Flow] k_type=0
7274 10:02:20.255294
7275 10:02:20.255464 ==CLK 0==
7276 10:02:20.258477 Final CLK duty delay cell = -4
7277 10:02:20.261261 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7278 10:02:20.264439 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7279 10:02:20.268292 [-4] AVG Duty = 4922%(X100)
7280 10:02:20.268418
7281 10:02:20.271729 CH0 CLK Duty spec in!! Max-Min= 218%
7282 10:02:20.274787 [DutyScan_Calibration_Flow] ====Done====
7283 10:02:20.275014
7284 10:02:20.278238 [DutyScan_Calibration_Flow] k_type=1
7285 10:02:20.294261
7286 10:02:20.294665 ==DQS 0 ==
7287 10:02:20.298304 Final DQS duty delay cell = -4
7288 10:02:20.301085 [-4] MAX Duty = 4938%(X100), DQS PI = 46
7289 10:02:20.304703 [-4] MIN Duty = 4782%(X100), DQS PI = 12
7290 10:02:20.307712 [-4] AVG Duty = 4860%(X100)
7291 10:02:20.308178
7292 10:02:20.308614 ==DQS 1 ==
7293 10:02:20.311122 Final DQS duty delay cell = 0
7294 10:02:20.314336 [0] MAX Duty = 5187%(X100), DQS PI = 0
7295 10:02:20.318093 [0] MIN Duty = 4969%(X100), DQS PI = 10
7296 10:02:20.320819 [0] AVG Duty = 5078%(X100)
7297 10:02:20.321243
7298 10:02:20.323961 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7299 10:02:20.324560
7300 10:02:20.327737 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7301 10:02:20.330467 [DutyScan_Calibration_Flow] ====Done====
7302 10:02:20.331046
7303 10:02:20.333806 [DutyScan_Calibration_Flow] k_type=3
7304 10:02:20.351855
7305 10:02:20.352398 ==DQM 0 ==
7306 10:02:20.355833 Final DQM duty delay cell = 0
7307 10:02:20.359062 [0] MAX Duty = 5124%(X100), DQS PI = 20
7308 10:02:20.361874 [0] MIN Duty = 4875%(X100), DQS PI = 54
7309 10:02:20.365347 [0] AVG Duty = 4999%(X100)
7310 10:02:20.365771
7311 10:02:20.366100 ==DQM 1 ==
7312 10:02:20.368151 Final DQM duty delay cell = 0
7313 10:02:20.372102 [0] MAX Duty = 4969%(X100), DQS PI = 2
7314 10:02:20.374984 [0] MIN Duty = 4844%(X100), DQS PI = 16
7315 10:02:20.378455 [0] AVG Duty = 4906%(X100)
7316 10:02:20.378970
7317 10:02:20.381586 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7318 10:02:20.382011
7319 10:02:20.384996 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7320 10:02:20.388420 [DutyScan_Calibration_Flow] ====Done====
7321 10:02:20.388843
7322 10:02:20.391326 [DutyScan_Calibration_Flow] k_type=2
7323 10:02:20.409644
7324 10:02:20.410187 ==DQ 0 ==
7325 10:02:20.412573 Final DQ duty delay cell = 0
7326 10:02:20.416211 [0] MAX Duty = 5156%(X100), DQS PI = 22
7327 10:02:20.419502 [0] MIN Duty = 4938%(X100), DQS PI = 12
7328 10:02:20.422332 [0] AVG Duty = 5047%(X100)
7329 10:02:20.422925
7330 10:02:20.423293 ==DQ 1 ==
7331 10:02:20.425862 Final DQ duty delay cell = 0
7332 10:02:20.429116 [0] MAX Duty = 5187%(X100), DQS PI = 2
7333 10:02:20.432317 [0] MIN Duty = 4938%(X100), DQS PI = 12
7334 10:02:20.432795 [0] AVG Duty = 5062%(X100)
7335 10:02:20.436170
7336 10:02:20.438709 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7337 10:02:20.439172
7338 10:02:20.442312 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7339 10:02:20.445312 [DutyScan_Calibration_Flow] ====Done====
7340 10:02:20.445774 ==
7341 10:02:20.448733 Dram Type= 6, Freq= 0, CH_1, rank 0
7342 10:02:20.452539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7343 10:02:20.453067 ==
7344 10:02:20.455310 [Duty_Offset_Calibration]
7345 10:02:20.455816 B0:0 B1:-1 CA:3
7346 10:02:20.456230
7347 10:02:20.458554 [DutyScan_Calibration_Flow] k_type=0
7348 10:02:20.468851
7349 10:02:20.469273 ==CLK 0==
7350 10:02:20.472198 Final CLK duty delay cell = -4
7351 10:02:20.475537 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7352 10:02:20.478741 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7353 10:02:20.481939 [-4] AVG Duty = 4922%(X100)
7354 10:02:20.482457
7355 10:02:20.485163 CH1 CLK Duty spec in!! Max-Min= 156%
7356 10:02:20.488689 [DutyScan_Calibration_Flow] ====Done====
7357 10:02:20.489102
7358 10:02:20.491807 [DutyScan_Calibration_Flow] k_type=1
7359 10:02:20.507803
7360 10:02:20.507884 ==DQS 0 ==
7361 10:02:20.511021 Final DQS duty delay cell = 0
7362 10:02:20.514156 [0] MAX Duty = 5250%(X100), DQS PI = 28
7363 10:02:20.517144 [0] MIN Duty = 4907%(X100), DQS PI = 58
7364 10:02:20.520510 [0] AVG Duty = 5078%(X100)
7365 10:02:20.520588
7366 10:02:20.520649 ==DQS 1 ==
7367 10:02:20.523946 Final DQS duty delay cell = -4
7368 10:02:20.527073 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7369 10:02:20.530474 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7370 10:02:20.533969 [-4] AVG Duty = 4922%(X100)
7371 10:02:20.534062
7372 10:02:20.536891 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7373 10:02:20.537019
7374 10:02:20.540768 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7375 10:02:20.543489 [DutyScan_Calibration_Flow] ====Done====
7376 10:02:20.543562
7377 10:02:20.546788 [DutyScan_Calibration_Flow] k_type=3
7378 10:02:20.565232
7379 10:02:20.565866 ==DQM 0 ==
7380 10:02:20.568502 Final DQM duty delay cell = 0
7381 10:02:20.571601 [0] MAX Duty = 5062%(X100), DQS PI = 30
7382 10:02:20.574681 [0] MIN Duty = 4782%(X100), DQS PI = 38
7383 10:02:20.578006 [0] AVG Duty = 4922%(X100)
7384 10:02:20.578409
7385 10:02:20.578721 ==DQM 1 ==
7386 10:02:20.581645 Final DQM duty delay cell = 0
7387 10:02:20.584648 [0] MAX Duty = 5000%(X100), DQS PI = 30
7388 10:02:20.588140 [0] MIN Duty = 4813%(X100), DQS PI = 12
7389 10:02:20.591496 [0] AVG Duty = 4906%(X100)
7390 10:02:20.591928
7391 10:02:20.594384 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7392 10:02:20.594790
7393 10:02:20.597781 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7394 10:02:20.601402 [DutyScan_Calibration_Flow] ====Done====
7395 10:02:20.601808
7396 10:02:20.605055 [DutyScan_Calibration_Flow] k_type=2
7397 10:02:20.621082
7398 10:02:20.621483 ==DQ 0 ==
7399 10:02:20.624482 Final DQ duty delay cell = -4
7400 10:02:20.627607 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7401 10:02:20.630897 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7402 10:02:20.634854 [-4] AVG Duty = 4891%(X100)
7403 10:02:20.635266
7404 10:02:20.635582 ==DQ 1 ==
7405 10:02:20.637437 Final DQ duty delay cell = 0
7406 10:02:20.641116 [0] MAX Duty = 5031%(X100), DQS PI = 32
7407 10:02:20.644209 [0] MIN Duty = 4875%(X100), DQS PI = 54
7408 10:02:20.647547 [0] AVG Duty = 4953%(X100)
7409 10:02:20.647949
7410 10:02:20.650476 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7411 10:02:20.650945
7412 10:02:20.653850 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7413 10:02:20.657837 [DutyScan_Calibration_Flow] ====Done====
7414 10:02:20.660654 nWR fixed to 30
7415 10:02:20.664357 [ModeRegInit_LP4] CH0 RK0
7416 10:02:20.664823 [ModeRegInit_LP4] CH0 RK1
7417 10:02:20.667583 [ModeRegInit_LP4] CH1 RK0
7418 10:02:20.670250 [ModeRegInit_LP4] CH1 RK1
7419 10:02:20.670674 match AC timing 5
7420 10:02:20.677107 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7421 10:02:20.680363 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7422 10:02:20.684147 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7423 10:02:20.690163 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7424 10:02:20.693635 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7425 10:02:20.696928 [MiockJmeterHQA]
7426 10:02:20.697398
7427 10:02:20.699882 [DramcMiockJmeter] u1RxGatingPI = 0
7428 10:02:20.700343 0 : 4254, 4027
7429 10:02:20.700734 4 : 4363, 4137
7430 10:02:20.703897 8 : 4252, 4027
7431 10:02:20.704368 12 : 4252, 4027
7432 10:02:20.706512 16 : 4360, 4138
7433 10:02:20.707019 20 : 4252, 4026
7434 10:02:20.709978 24 : 4255, 4030
7435 10:02:20.710408 28 : 4252, 4027
7436 10:02:20.710747 32 : 4363, 4137
7437 10:02:20.713499 36 : 4363, 4138
7438 10:02:20.713928 40 : 4253, 4026
7439 10:02:20.716852 44 : 4252, 4027
7440 10:02:20.717280 48 : 4252, 4026
7441 10:02:20.719860 52 : 4252, 4027
7442 10:02:20.720317 56 : 4254, 4029
7443 10:02:20.723496 60 : 4363, 4137
7444 10:02:20.723923 64 : 4250, 4027
7445 10:02:20.726575 68 : 4250, 4026
7446 10:02:20.727001 72 : 4253, 4026
7447 10:02:20.727339 76 : 4252, 4030
7448 10:02:20.729766 80 : 4250, 4026
7449 10:02:20.730196 84 : 4361, 4137
7450 10:02:20.733283 88 : 4360, 4138
7451 10:02:20.733711 92 : 4250, 4026
7452 10:02:20.736490 96 : 4250, 3059
7453 10:02:20.737005 100 : 4250, 0
7454 10:02:20.737377 104 : 4363, 0
7455 10:02:20.739834 108 : 4253, 0
7456 10:02:20.740300 112 : 4252, 0
7457 10:02:20.742984 116 : 4252, 0
7458 10:02:20.743536 120 : 4361, 0
7459 10:02:20.743927 124 : 4361, 0
7460 10:02:20.746106 128 : 4362, 0
7461 10:02:20.746409 132 : 4250, 0
7462 10:02:20.749231 136 : 4250, 0
7463 10:02:20.749485 140 : 4249, 0
7464 10:02:20.749667 144 : 4250, 0
7465 10:02:20.752647 148 : 4250, 0
7466 10:02:20.752877 152 : 4360, 0
7467 10:02:20.753092 156 : 4361, 0
7468 10:02:20.756229 160 : 4250, 0
7469 10:02:20.756413 164 : 4249, 0
7470 10:02:20.759319 168 : 4250, 0
7471 10:02:20.759504 172 : 4253, 0
7472 10:02:20.759650 176 : 4250, 0
7473 10:02:20.762662 180 : 4360, 0
7474 10:02:20.762846 184 : 4250, 0
7475 10:02:20.766097 188 : 4250, 0
7476 10:02:20.766288 192 : 4250, 0
7477 10:02:20.766435 196 : 4253, 0
7478 10:02:20.768878 200 : 4250, 0
7479 10:02:20.769103 204 : 4360, 0
7480 10:02:20.772189 208 : 4361, 0
7481 10:02:20.772374 212 : 4250, 0
7482 10:02:20.772520 216 : 4249, 0
7483 10:02:20.775895 220 : 4252, 559
7484 10:02:20.776091 224 : 4361, 4114
7485 10:02:20.779234 228 : 4250, 4026
7486 10:02:20.779418 232 : 4250, 4027
7487 10:02:20.782448 236 : 4363, 4140
7488 10:02:20.782632 240 : 4250, 4026
7489 10:02:20.785486 244 : 4250, 4026
7490 10:02:20.785670 248 : 4250, 4027
7491 10:02:20.788758 252 : 4250, 4027
7492 10:02:20.788943 256 : 4250, 4027
7493 10:02:20.792260 260 : 4250, 4026
7494 10:02:20.792445 264 : 4361, 4137
7495 10:02:20.792616 268 : 4250, 4027
7496 10:02:20.795360 272 : 4249, 4027
7497 10:02:20.795546 276 : 4363, 4140
7498 10:02:20.798529 280 : 4250, 4026
7499 10:02:20.798713 284 : 4250, 4027
7500 10:02:20.801782 288 : 4363, 4140
7501 10:02:20.801965 292 : 4249, 4027
7502 10:02:20.805319 296 : 4250, 4026
7503 10:02:20.805505 300 : 4250, 4027
7504 10:02:20.808455 304 : 4252, 4030
7505 10:02:20.808542 308 : 4250, 4027
7506 10:02:20.811577 312 : 4250, 4026
7507 10:02:20.811661 316 : 4361, 4137
7508 10:02:20.814960 320 : 4250, 4027
7509 10:02:20.815043 324 : 4249, 4027
7510 10:02:20.818208 328 : 4361, 4137
7511 10:02:20.818291 332 : 4250, 4018
7512 10:02:20.818356 336 : 4250, 1907
7513 10:02:20.821729
7514 10:02:20.821810 MIOCK jitter meter ch=0
7515 10:02:20.821874
7516 10:02:20.825014 1T = (336-100) = 236 dly cells
7517 10:02:20.831672 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7518 10:02:20.831754 ==
7519 10:02:20.835000 Dram Type= 6, Freq= 0, CH_0, rank 0
7520 10:02:20.837933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7521 10:02:20.838016 ==
7522 10:02:20.844663 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7523 10:02:20.848633 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7524 10:02:20.851034 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7525 10:02:20.857690 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7526 10:02:20.867899 [CA 0] Center 43 (13~74) winsize 62
7527 10:02:20.870992 [CA 1] Center 42 (12~73) winsize 62
7528 10:02:20.874604 [CA 2] Center 37 (8~67) winsize 60
7529 10:02:20.877589 [CA 3] Center 37 (8~67) winsize 60
7530 10:02:20.880659 [CA 4] Center 36 (6~66) winsize 61
7531 10:02:20.884075 [CA 5] Center 35 (5~66) winsize 62
7532 10:02:20.884168
7533 10:02:20.887459 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7534 10:02:20.887556
7535 10:02:20.891351 [CATrainingPosCal] consider 1 rank data
7536 10:02:20.893825 u2DelayCellTimex100 = 275/100 ps
7537 10:02:20.900561 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7538 10:02:20.903863 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7539 10:02:20.906790 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7540 10:02:20.910105 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7541 10:02:20.914184 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7542 10:02:20.917268 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7543 10:02:20.917340
7544 10:02:20.920223 CA PerBit enable=1, Macro0, CA PI delay=35
7545 10:02:20.920315
7546 10:02:20.923555 [CBTSetCACLKResult] CA Dly = 35
7547 10:02:20.926987 CS Dly: 10 (0~41)
7548 10:02:20.929946 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7549 10:02:20.933346 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7550 10:02:20.933424 ==
7551 10:02:20.936619 Dram Type= 6, Freq= 0, CH_0, rank 1
7552 10:02:20.943528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 10:02:20.943611 ==
7554 10:02:20.946875 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7555 10:02:20.953256 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7556 10:02:20.956156 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7557 10:02:20.963026 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7558 10:02:20.970931 [CA 0] Center 44 (14~75) winsize 62
7559 10:02:20.974180 [CA 1] Center 44 (14~74) winsize 61
7560 10:02:20.977228 [CA 2] Center 39 (10~69) winsize 60
7561 10:02:20.980587 [CA 3] Center 39 (10~68) winsize 59
7562 10:02:20.984432 [CA 4] Center 37 (7~67) winsize 61
7563 10:02:20.988209 [CA 5] Center 36 (7~66) winsize 60
7564 10:02:20.988287
7565 10:02:20.990338 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7566 10:02:20.993936
7567 10:02:20.997050 [CATrainingPosCal] consider 2 rank data
7568 10:02:20.997148 u2DelayCellTimex100 = 275/100 ps
7569 10:02:21.003580 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7570 10:02:21.006820 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7571 10:02:21.010468 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7572 10:02:21.013525 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7573 10:02:21.016748 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7574 10:02:21.020265 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7575 10:02:21.020337
7576 10:02:21.023526 CA PerBit enable=1, Macro0, CA PI delay=36
7577 10:02:21.026998
7578 10:02:21.027067 [CBTSetCACLKResult] CA Dly = 36
7579 10:02:21.030612 CS Dly: 11 (0~44)
7580 10:02:21.033783 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7581 10:02:21.036479 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7582 10:02:21.036584
7583 10:02:21.039729 ----->DramcWriteLeveling(PI) begin...
7584 10:02:21.043356 ==
7585 10:02:21.046641 Dram Type= 6, Freq= 0, CH_0, rank 0
7586 10:02:21.049682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7587 10:02:21.049784 ==
7588 10:02:21.053169 Write leveling (Byte 0): 34 => 34
7589 10:02:21.056455 Write leveling (Byte 1): 25 => 25
7590 10:02:21.059647 DramcWriteLeveling(PI) end<-----
7591 10:02:21.059742
7592 10:02:21.059836 ==
7593 10:02:21.062980 Dram Type= 6, Freq= 0, CH_0, rank 0
7594 10:02:21.066110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7595 10:02:21.066208 ==
7596 10:02:21.069608 [Gating] SW mode calibration
7597 10:02:21.076260 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7598 10:02:21.082713 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7599 10:02:21.086491 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 10:02:21.089474 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 10:02:21.095864 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 10:02:21.099323 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7603 10:02:21.102381 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7604 10:02:21.109795 1 4 20 | B1->B0 | 2625 3434 | 1 1 | (0 0) (1 1)
7605 10:02:21.112885 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7606 10:02:21.115560 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7607 10:02:21.122681 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 10:02:21.125757 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7609 10:02:21.128891 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7610 10:02:21.135634 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
7611 10:02:21.138742 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7612 10:02:21.142119 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
7613 10:02:21.148664 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 10:02:21.151827 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 10:02:21.155527 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 10:02:21.161955 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 10:02:21.165098 1 6 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
7618 10:02:21.168893 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7619 10:02:21.175185 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7620 10:02:21.178188 1 6 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7621 10:02:21.182264 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7622 10:02:21.188153 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 10:02:21.191529 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 10:02:21.194902 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 10:02:21.201099 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7626 10:02:21.204689 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7627 10:02:21.208124 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7628 10:02:21.214244 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7629 10:02:21.218543 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 10:02:21.221042 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 10:02:21.228055 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 10:02:21.231171 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 10:02:21.234310 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 10:02:21.241666 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 10:02:21.243999 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 10:02:21.247637 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 10:02:21.254232 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 10:02:21.256995 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 10:02:21.260540 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 10:02:21.267337 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7641 10:02:21.270263 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7642 10:02:21.273698 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7643 10:02:21.280170 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7644 10:02:21.283683 Total UI for P1: 0, mck2ui 16
7645 10:02:21.286591 best dqsien dly found for B0: ( 1, 9, 8)
7646 10:02:21.290049 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7647 10:02:21.293388 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7648 10:02:21.300323 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 10:02:21.303261 Total UI for P1: 0, mck2ui 16
7650 10:02:21.306755 best dqsien dly found for B1: ( 1, 9, 22)
7651 10:02:21.309825 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7652 10:02:21.312867 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7653 10:02:21.312948
7654 10:02:21.316530 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7655 10:02:21.319473 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7656 10:02:21.322961 [Gating] SW calibration Done
7657 10:02:21.323047 ==
7658 10:02:21.326407 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 10:02:21.330003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 10:02:21.330103 ==
7661 10:02:21.333037 RX Vref Scan: 0
7662 10:02:21.333136
7663 10:02:21.336069 RX Vref 0 -> 0, step: 1
7664 10:02:21.336178
7665 10:02:21.336263 RX Delay 0 -> 252, step: 8
7666 10:02:21.342913 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7667 10:02:21.346128 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7668 10:02:21.349626 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7669 10:02:21.352634 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7670 10:02:21.356329 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7671 10:02:21.362839 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7672 10:02:21.366317 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7673 10:02:21.369697 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7674 10:02:21.372526 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7675 10:02:21.375984 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7676 10:02:21.382673 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7677 10:02:21.385827 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7678 10:02:21.389222 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7679 10:02:21.392568 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7680 10:02:21.395670 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7681 10:02:21.402048 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7682 10:02:21.402560 ==
7683 10:02:21.405450 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 10:02:21.408916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 10:02:21.409407 ==
7686 10:02:21.409915 DQS Delay:
7687 10:02:21.411963 DQS0 = 0, DQS1 = 0
7688 10:02:21.412367 DQM Delay:
7689 10:02:21.415707 DQM0 = 131, DQM1 = 127
7690 10:02:21.415783 DQ Delay:
7691 10:02:21.418410 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7692 10:02:21.421776 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7693 10:02:21.424864 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7694 10:02:21.431549 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7695 10:02:21.431625
7696 10:02:21.431686
7697 10:02:21.431744 ==
7698 10:02:21.434721 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 10:02:21.438150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 10:02:21.438218 ==
7701 10:02:21.438276
7702 10:02:21.438332
7703 10:02:21.441412 TX Vref Scan disable
7704 10:02:21.441478 == TX Byte 0 ==
7705 10:02:21.448311 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7706 10:02:21.451139 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7707 10:02:21.455199 == TX Byte 1 ==
7708 10:02:21.457808 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7709 10:02:21.461115 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7710 10:02:21.461208 ==
7711 10:02:21.464775 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 10:02:21.468170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 10:02:21.470967 ==
7714 10:02:21.484714
7715 10:02:21.487871 TX Vref early break, caculate TX vref
7716 10:02:21.490769 TX Vref=16, minBit 1, minWin=21, winSum=353
7717 10:02:21.494068 TX Vref=18, minBit 1, minWin=21, winSum=368
7718 10:02:21.497246 TX Vref=20, minBit 1, minWin=22, winSum=377
7719 10:02:21.500338 TX Vref=22, minBit 1, minWin=22, winSum=391
7720 10:02:21.503606 TX Vref=24, minBit 7, minWin=23, winSum=399
7721 10:02:21.510387 TX Vref=26, minBit 1, minWin=24, winSum=404
7722 10:02:21.513517 TX Vref=28, minBit 1, minWin=24, winSum=405
7723 10:02:21.516986 TX Vref=30, minBit 0, minWin=23, winSum=401
7724 10:02:21.520009 TX Vref=32, minBit 0, minWin=23, winSum=396
7725 10:02:21.523693 TX Vref=34, minBit 0, minWin=23, winSum=385
7726 10:02:21.530561 TX Vref=36, minBit 1, minWin=22, winSum=376
7727 10:02:21.533379 [TxChooseVref] Worse bit 1, Min win 24, Win sum 405, Final Vref 28
7728 10:02:21.533454
7729 10:02:21.537178 Final TX Range 0 Vref 28
7730 10:02:21.537248
7731 10:02:21.537307 ==
7732 10:02:21.540127 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 10:02:21.543362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 10:02:21.546893 ==
7735 10:02:21.546961
7736 10:02:21.547023
7737 10:02:21.547078 TX Vref Scan disable
7738 10:02:21.553256 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7739 10:02:21.553327 == TX Byte 0 ==
7740 10:02:21.556742 u2DelayCellOfst[0]=14 cells (4 PI)
7741 10:02:21.559865 u2DelayCellOfst[1]=17 cells (5 PI)
7742 10:02:21.563830 u2DelayCellOfst[2]=10 cells (3 PI)
7743 10:02:21.566622 u2DelayCellOfst[3]=10 cells (3 PI)
7744 10:02:21.570049 u2DelayCellOfst[4]=10 cells (3 PI)
7745 10:02:21.573467 u2DelayCellOfst[5]=0 cells (0 PI)
7746 10:02:21.576406 u2DelayCellOfst[6]=17 cells (5 PI)
7747 10:02:21.580111 u2DelayCellOfst[7]=17 cells (5 PI)
7748 10:02:21.583471 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7749 10:02:21.586504 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7750 10:02:21.589657 == TX Byte 1 ==
7751 10:02:21.593244 u2DelayCellOfst[8]=0 cells (0 PI)
7752 10:02:21.596112 u2DelayCellOfst[9]=0 cells (0 PI)
7753 10:02:21.599533 u2DelayCellOfst[10]=3 cells (1 PI)
7754 10:02:21.602927 u2DelayCellOfst[11]=0 cells (0 PI)
7755 10:02:21.606323 u2DelayCellOfst[12]=7 cells (2 PI)
7756 10:02:21.609914 u2DelayCellOfst[13]=7 cells (2 PI)
7757 10:02:21.609982 u2DelayCellOfst[14]=14 cells (4 PI)
7758 10:02:21.612729 u2DelayCellOfst[15]=7 cells (2 PI)
7759 10:02:21.619926 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7760 10:02:21.622644 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7761 10:02:21.625851 DramC Write-DBI on
7762 10:02:21.625924 ==
7763 10:02:21.629329 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 10:02:21.632632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 10:02:21.632730 ==
7766 10:02:21.632817
7767 10:02:21.632901
7768 10:02:21.635731 TX Vref Scan disable
7769 10:02:21.635804 == TX Byte 0 ==
7770 10:02:21.642662 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7771 10:02:21.642740 == TX Byte 1 ==
7772 10:02:21.645671 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7773 10:02:21.648916 DramC Write-DBI off
7774 10:02:21.648986
7775 10:02:21.649044 [DATLAT]
7776 10:02:21.652572 Freq=1600, CH0 RK0
7777 10:02:21.652644
7778 10:02:21.652706 DATLAT Default: 0xf
7779 10:02:21.656079 0, 0xFFFF, sum = 0
7780 10:02:21.656160 1, 0xFFFF, sum = 0
7781 10:02:21.659095 2, 0xFFFF, sum = 0
7782 10:02:21.662570 3, 0xFFFF, sum = 0
7783 10:02:21.662654 4, 0xFFFF, sum = 0
7784 10:02:21.665640 5, 0xFFFF, sum = 0
7785 10:02:21.665753 6, 0xFFFF, sum = 0
7786 10:02:21.669404 7, 0xFFFF, sum = 0
7787 10:02:21.669529 8, 0xFFFF, sum = 0
7788 10:02:21.672075 9, 0xFFFF, sum = 0
7789 10:02:21.672199 10, 0xFFFF, sum = 0
7790 10:02:21.675420 11, 0xFFFF, sum = 0
7791 10:02:21.675557 12, 0xFFFF, sum = 0
7792 10:02:21.679376 13, 0xFFFF, sum = 0
7793 10:02:21.679530 14, 0x0, sum = 1
7794 10:02:21.681924 15, 0x0, sum = 2
7795 10:02:21.682109 16, 0x0, sum = 3
7796 10:02:21.686000 17, 0x0, sum = 4
7797 10:02:21.686175 best_step = 15
7798 10:02:21.686312
7799 10:02:21.686438 ==
7800 10:02:21.689353 Dram Type= 6, Freq= 0, CH_0, rank 0
7801 10:02:21.695603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7802 10:02:21.695927 ==
7803 10:02:21.696234 RX Vref Scan: 1
7804 10:02:21.696476
7805 10:02:21.699021 Set Vref Range= 24 -> 127
7806 10:02:21.699345
7807 10:02:21.701876 RX Vref 24 -> 127, step: 1
7808 10:02:21.702279
7809 10:02:21.702626 RX Delay 11 -> 252, step: 4
7810 10:02:21.702952
7811 10:02:21.705723 Set Vref, RX VrefLevel [Byte0]: 24
7812 10:02:21.709477 [Byte1]: 24
7813 10:02:21.712913
7814 10:02:21.713308 Set Vref, RX VrefLevel [Byte0]: 25
7815 10:02:21.716367 [Byte1]: 25
7816 10:02:21.720504
7817 10:02:21.720885 Set Vref, RX VrefLevel [Byte0]: 26
7818 10:02:21.723992 [Byte1]: 26
7819 10:02:21.728096
7820 10:02:21.728463 Set Vref, RX VrefLevel [Byte0]: 27
7821 10:02:21.731681 [Byte1]: 27
7822 10:02:21.736093
7823 10:02:21.736488 Set Vref, RX VrefLevel [Byte0]: 28
7824 10:02:21.739080 [Byte1]: 28
7825 10:02:21.743086
7826 10:02:21.743540 Set Vref, RX VrefLevel [Byte0]: 29
7827 10:02:21.746373 [Byte1]: 29
7828 10:02:21.751043
7829 10:02:21.751397 Set Vref, RX VrefLevel [Byte0]: 30
7830 10:02:21.754057 [Byte1]: 30
7831 10:02:21.758263
7832 10:02:21.758343 Set Vref, RX VrefLevel [Byte0]: 31
7833 10:02:21.761745 [Byte1]: 31
7834 10:02:21.765742
7835 10:02:21.765822 Set Vref, RX VrefLevel [Byte0]: 32
7836 10:02:21.769464 [Byte1]: 32
7837 10:02:21.773560
7838 10:02:21.773639 Set Vref, RX VrefLevel [Byte0]: 33
7839 10:02:21.777008 [Byte1]: 33
7840 10:02:21.781435
7841 10:02:21.781515 Set Vref, RX VrefLevel [Byte0]: 34
7842 10:02:21.784225 [Byte1]: 34
7843 10:02:21.788453
7844 10:02:21.788533 Set Vref, RX VrefLevel [Byte0]: 35
7845 10:02:21.792398 [Byte1]: 35
7846 10:02:21.796622
7847 10:02:21.796702 Set Vref, RX VrefLevel [Byte0]: 36
7848 10:02:21.799394 [Byte1]: 36
7849 10:02:21.803897
7850 10:02:21.803976 Set Vref, RX VrefLevel [Byte0]: 37
7851 10:02:21.807052 [Byte1]: 37
7852 10:02:21.811728
7853 10:02:21.811807 Set Vref, RX VrefLevel [Byte0]: 38
7854 10:02:21.814674 [Byte1]: 38
7855 10:02:21.818974
7856 10:02:21.819081 Set Vref, RX VrefLevel [Byte0]: 39
7857 10:02:21.822227 [Byte1]: 39
7858 10:02:21.826453
7859 10:02:21.826533 Set Vref, RX VrefLevel [Byte0]: 40
7860 10:02:21.830168 [Byte1]: 40
7861 10:02:21.834849
7862 10:02:21.834929 Set Vref, RX VrefLevel [Byte0]: 41
7863 10:02:21.837743 [Byte1]: 41
7864 10:02:21.841991
7865 10:02:21.842070 Set Vref, RX VrefLevel [Byte0]: 42
7866 10:02:21.845515 [Byte1]: 42
7867 10:02:21.849482
7868 10:02:21.849561 Set Vref, RX VrefLevel [Byte0]: 43
7869 10:02:21.852678 [Byte1]: 43
7870 10:02:21.857079
7871 10:02:21.857159 Set Vref, RX VrefLevel [Byte0]: 44
7872 10:02:21.861144 [Byte1]: 44
7873 10:02:21.865024
7874 10:02:21.865104 Set Vref, RX VrefLevel [Byte0]: 45
7875 10:02:21.867810 [Byte1]: 45
7876 10:02:21.872546
7877 10:02:21.872625 Set Vref, RX VrefLevel [Byte0]: 46
7878 10:02:21.875843 [Byte1]: 46
7879 10:02:21.880338
7880 10:02:21.880418 Set Vref, RX VrefLevel [Byte0]: 47
7881 10:02:21.883372 [Byte1]: 47
7882 10:02:21.887788
7883 10:02:21.887868 Set Vref, RX VrefLevel [Byte0]: 48
7884 10:02:21.894144 [Byte1]: 48
7885 10:02:21.894224
7886 10:02:21.897850 Set Vref, RX VrefLevel [Byte0]: 49
7887 10:02:21.900769 [Byte1]: 49
7888 10:02:21.900849
7889 10:02:21.904208 Set Vref, RX VrefLevel [Byte0]: 50
7890 10:02:21.907328 [Byte1]: 50
7891 10:02:21.910991
7892 10:02:21.911071 Set Vref, RX VrefLevel [Byte0]: 51
7893 10:02:21.913927 [Byte1]: 51
7894 10:02:21.919271
7895 10:02:21.919354 Set Vref, RX VrefLevel [Byte0]: 52
7896 10:02:21.921397 [Byte1]: 52
7897 10:02:21.925826
7898 10:02:21.925906 Set Vref, RX VrefLevel [Byte0]: 53
7899 10:02:21.928876 [Byte1]: 53
7900 10:02:21.933328
7901 10:02:21.933408 Set Vref, RX VrefLevel [Byte0]: 54
7902 10:02:21.936932 [Byte1]: 54
7903 10:02:21.941436
7904 10:02:21.941515 Set Vref, RX VrefLevel [Byte0]: 55
7905 10:02:21.944421 [Byte1]: 55
7906 10:02:21.948497
7907 10:02:21.948576 Set Vref, RX VrefLevel [Byte0]: 56
7908 10:02:21.951873 [Byte1]: 56
7909 10:02:21.956295
7910 10:02:21.956375 Set Vref, RX VrefLevel [Byte0]: 57
7911 10:02:21.959374 [Byte1]: 57
7912 10:02:21.963742
7913 10:02:21.963849 Set Vref, RX VrefLevel [Byte0]: 58
7914 10:02:21.967183 [Byte1]: 58
7915 10:02:21.971383
7916 10:02:21.971463 Set Vref, RX VrefLevel [Byte0]: 59
7917 10:02:21.974656 [Byte1]: 59
7918 10:02:21.979890
7919 10:02:21.980338 Set Vref, RX VrefLevel [Byte0]: 60
7920 10:02:21.982576 [Byte1]: 60
7921 10:02:21.986866
7922 10:02:21.987274 Set Vref, RX VrefLevel [Byte0]: 61
7923 10:02:21.990809 [Byte1]: 61
7924 10:02:21.994618
7925 10:02:21.995028 Set Vref, RX VrefLevel [Byte0]: 62
7926 10:02:21.998034 [Byte1]: 62
7927 10:02:22.002254
7928 10:02:22.002667 Set Vref, RX VrefLevel [Byte0]: 63
7929 10:02:22.005159 [Byte1]: 63
7930 10:02:22.009542
7931 10:02:22.009982 Set Vref, RX VrefLevel [Byte0]: 64
7932 10:02:22.013210 [Byte1]: 64
7933 10:02:22.017589
7934 10:02:22.017999 Set Vref, RX VrefLevel [Byte0]: 65
7935 10:02:22.020627 [Byte1]: 65
7936 10:02:22.025288
7937 10:02:22.025710 Set Vref, RX VrefLevel [Byte0]: 66
7938 10:02:22.028132 [Byte1]: 66
7939 10:02:22.032545
7940 10:02:22.032955 Set Vref, RX VrefLevel [Byte0]: 67
7941 10:02:22.035767 [Byte1]: 67
7942 10:02:22.040144
7943 10:02:22.040587 Set Vref, RX VrefLevel [Byte0]: 68
7944 10:02:22.044277 [Byte1]: 68
7945 10:02:22.047640
7946 10:02:22.048076 Set Vref, RX VrefLevel [Byte0]: 69
7947 10:02:22.051120 [Byte1]: 69
7948 10:02:22.055403
7949 10:02:22.059062 Set Vref, RX VrefLevel [Byte0]: 70
7950 10:02:22.059480 [Byte1]: 70
7951 10:02:22.063367
7952 10:02:22.063791 Set Vref, RX VrefLevel [Byte0]: 71
7953 10:02:22.066255 [Byte1]: 71
7954 10:02:22.071024
7955 10:02:22.071461 Set Vref, RX VrefLevel [Byte0]: 72
7956 10:02:22.073868 [Byte1]: 72
7957 10:02:22.079032
7958 10:02:22.079566 Set Vref, RX VrefLevel [Byte0]: 73
7959 10:02:22.081703 [Byte1]: 73
7960 10:02:22.085733
7961 10:02:22.086176 Set Vref, RX VrefLevel [Byte0]: 74
7962 10:02:22.089194 [Byte1]: 74
7963 10:02:22.094086
7964 10:02:22.094609 Set Vref, RX VrefLevel [Byte0]: 75
7965 10:02:22.097021 [Byte1]: 75
7966 10:02:22.101522
7967 10:02:22.102049 Final RX Vref Byte 0 = 56 to rank0
7968 10:02:22.104748 Final RX Vref Byte 1 = 56 to rank0
7969 10:02:22.108387 Final RX Vref Byte 0 = 56 to rank1
7970 10:02:22.110869 Final RX Vref Byte 1 = 56 to rank1==
7971 10:02:22.114437 Dram Type= 6, Freq= 0, CH_0, rank 0
7972 10:02:22.120723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7973 10:02:22.121285 ==
7974 10:02:22.121696 DQS Delay:
7975 10:02:22.123954 DQS0 = 0, DQS1 = 0
7976 10:02:22.124398 DQM Delay:
7977 10:02:22.127164 DQM0 = 128, DQM1 = 124
7978 10:02:22.127582 DQ Delay:
7979 10:02:22.130692 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7980 10:02:22.133862 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =134
7981 10:02:22.137881 DQ8 =112, DQ9 =110, DQ10 =126, DQ11 =120
7982 10:02:22.140470 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =132
7983 10:02:22.140919
7984 10:02:22.141250
7985 10:02:22.141593
7986 10:02:22.143860 [DramC_TX_OE_Calibration] TA2
7987 10:02:22.147383 Original DQ_B0 (3 6) =30, OEN = 27
7988 10:02:22.151043 Original DQ_B1 (3 6) =30, OEN = 27
7989 10:02:22.153854 24, 0x0, End_B0=24 End_B1=24
7990 10:02:22.157366 25, 0x0, End_B0=25 End_B1=25
7991 10:02:22.157896 26, 0x0, End_B0=26 End_B1=26
7992 10:02:22.161062 27, 0x0, End_B0=27 End_B1=27
7993 10:02:22.163510 28, 0x0, End_B0=28 End_B1=28
7994 10:02:22.166842 29, 0x0, End_B0=29 End_B1=29
7995 10:02:22.167289 30, 0x0, End_B0=30 End_B1=30
7996 10:02:22.170091 31, 0x5151, End_B0=30 End_B1=30
7997 10:02:22.173589 Byte0 end_step=30 best_step=27
7998 10:02:22.176695 Byte1 end_step=30 best_step=27
7999 10:02:22.180515 Byte0 TX OE(2T, 0.5T) = (3, 3)
8000 10:02:22.183526 Byte1 TX OE(2T, 0.5T) = (3, 3)
8001 10:02:22.184120
8002 10:02:22.184485
8003 10:02:22.189738 [DQSOSCAuto] RK0, (LSB)MR18= 0x1411, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
8004 10:02:22.192746 CH0 RK0: MR19=303, MR18=1411
8005 10:02:22.199382 CH0_RK0: MR19=0x303, MR18=0x1411, DQSOSC=399, MR23=63, INC=23, DEC=15
8006 10:02:22.199464
8007 10:02:22.203043 ----->DramcWriteLeveling(PI) begin...
8008 10:02:22.203126 ==
8009 10:02:22.206046 Dram Type= 6, Freq= 0, CH_0, rank 1
8010 10:02:22.209353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8011 10:02:22.212470 ==
8012 10:02:22.212550 Write leveling (Byte 0): 34 => 34
8013 10:02:22.215992 Write leveling (Byte 1): 27 => 27
8014 10:02:22.219031 DramcWriteLeveling(PI) end<-----
8015 10:02:22.219118
8016 10:02:22.219185 ==
8017 10:02:22.222440 Dram Type= 6, Freq= 0, CH_0, rank 1
8018 10:02:22.229114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8019 10:02:22.229214 ==
8020 10:02:22.232591 [Gating] SW mode calibration
8021 10:02:22.238739 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8022 10:02:22.242250 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8023 10:02:22.248751 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 10:02:22.252191 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 10:02:22.255718 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
8026 10:02:22.262364 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8027 10:02:22.265427 1 4 16 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
8028 10:02:22.268640 1 4 20 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8029 10:02:22.275293 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8030 10:02:22.279007 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8031 10:02:22.282064 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8032 10:02:22.288703 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8033 10:02:22.292099 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8034 10:02:22.295312 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
8035 10:02:22.302007 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8036 10:02:22.305340 1 5 20 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
8037 10:02:22.308808 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 10:02:22.315290 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 10:02:22.318002 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 10:02:22.321482 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8041 10:02:22.327604 1 6 8 | B1->B0 | 2323 3f3f | 0 1 | (0 0) (0 0)
8042 10:02:22.331089 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8043 10:02:22.334842 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
8044 10:02:22.341524 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
8045 10:02:22.344197 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 10:02:22.347763 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 10:02:22.353771 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 10:02:22.357445 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 10:02:22.360542 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8050 10:02:22.367111 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8051 10:02:22.370509 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8052 10:02:22.373762 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8053 10:02:22.380904 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 10:02:22.383777 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 10:02:22.386742 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 10:02:22.393628 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 10:02:22.397047 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 10:02:22.400284 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 10:02:22.406590 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 10:02:22.410259 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 10:02:22.413206 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 10:02:22.419850 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 10:02:22.423317 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 10:02:22.426206 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 10:02:22.432713 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8066 10:02:22.436350 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8067 10:02:22.439367 Total UI for P1: 0, mck2ui 16
8068 10:02:22.443447 best dqsien dly found for B0: ( 1, 9, 8)
8069 10:02:22.445821 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8070 10:02:22.452801 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8071 10:02:22.455817 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 10:02:22.459271 Total UI for P1: 0, mck2ui 16
8073 10:02:22.462681 best dqsien dly found for B1: ( 1, 9, 18)
8074 10:02:22.466279 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8075 10:02:22.469199 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8076 10:02:22.469283
8077 10:02:22.472263 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8078 10:02:22.475597 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8079 10:02:22.479189 [Gating] SW calibration Done
8080 10:02:22.479275 ==
8081 10:02:22.482213 Dram Type= 6, Freq= 0, CH_0, rank 1
8082 10:02:22.488722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8083 10:02:22.488800 ==
8084 10:02:22.488862 RX Vref Scan: 0
8085 10:02:22.488922
8086 10:02:22.492518 RX Vref 0 -> 0, step: 1
8087 10:02:22.492599
8088 10:02:22.495603 RX Delay 0 -> 252, step: 8
8089 10:02:22.499028 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8090 10:02:22.502651 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8091 10:02:22.505551 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8092 10:02:22.509177 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8093 10:02:22.514915 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8094 10:02:22.518568 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8095 10:02:22.522047 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8096 10:02:22.524978 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8097 10:02:22.528694 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8098 10:02:22.535164 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8099 10:02:22.538197 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8100 10:02:22.542668 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8101 10:02:22.544905 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8102 10:02:22.551581 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8103 10:02:22.554462 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8104 10:02:22.557804 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8105 10:02:22.557886 ==
8106 10:02:22.561360 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 10:02:22.564399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 10:02:22.567653 ==
8109 10:02:22.567734 DQS Delay:
8110 10:02:22.567798 DQS0 = 0, DQS1 = 0
8111 10:02:22.570920 DQM Delay:
8112 10:02:22.571028 DQM0 = 132, DQM1 = 127
8113 10:02:22.574010 DQ Delay:
8114 10:02:22.577350 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8115 10:02:22.580722 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8116 10:02:22.584319 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
8117 10:02:22.587325 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8118 10:02:22.587398
8119 10:02:22.587457
8120 10:02:22.587514 ==
8121 10:02:22.590494 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 10:02:22.594061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 10:02:22.597348 ==
8124 10:02:22.597515
8125 10:02:22.597617
8126 10:02:22.597708 TX Vref Scan disable
8127 10:02:22.601177 == TX Byte 0 ==
8128 10:02:22.604546 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8129 10:02:22.607566 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8130 10:02:22.610912 == TX Byte 1 ==
8131 10:02:22.614369 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8132 10:02:22.617242 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8133 10:02:22.620753 ==
8134 10:02:22.623221 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 10:02:22.626941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 10:02:22.627023 ==
8137 10:02:22.639604
8138 10:02:22.642924 TX Vref early break, caculate TX vref
8139 10:02:22.646434 TX Vref=16, minBit 1, minWin=22, winSum=377
8140 10:02:22.650137 TX Vref=18, minBit 0, minWin=23, winSum=384
8141 10:02:22.652939 TX Vref=20, minBit 3, minWin=23, winSum=395
8142 10:02:22.656780 TX Vref=22, minBit 3, minWin=24, winSum=402
8143 10:02:22.659195 TX Vref=24, minBit 0, minWin=24, winSum=405
8144 10:02:22.666222 TX Vref=26, minBit 0, minWin=25, winSum=417
8145 10:02:22.669590 TX Vref=28, minBit 0, minWin=25, winSum=418
8146 10:02:22.672678 TX Vref=30, minBit 0, minWin=24, winSum=408
8147 10:02:22.675963 TX Vref=32, minBit 0, minWin=24, winSum=403
8148 10:02:22.679681 TX Vref=34, minBit 0, minWin=24, winSum=393
8149 10:02:22.686397 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8150 10:02:22.686649
8151 10:02:22.689221 Final TX Range 0 Vref 28
8152 10:02:22.689517
8153 10:02:22.689747 ==
8154 10:02:22.692781 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 10:02:22.696316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 10:02:22.696696 ==
8157 10:02:22.696993
8158 10:02:22.697266
8159 10:02:22.699535 TX Vref Scan disable
8160 10:02:22.705940 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8161 10:02:22.706028 == TX Byte 0 ==
8162 10:02:22.708781 u2DelayCellOfst[0]=14 cells (4 PI)
8163 10:02:22.712258 u2DelayCellOfst[1]=17 cells (5 PI)
8164 10:02:22.715628 u2DelayCellOfst[2]=14 cells (4 PI)
8165 10:02:22.718713 u2DelayCellOfst[3]=10 cells (3 PI)
8166 10:02:22.723301 u2DelayCellOfst[4]=10 cells (3 PI)
8167 10:02:22.725894 u2DelayCellOfst[5]=0 cells (0 PI)
8168 10:02:22.728943 u2DelayCellOfst[6]=17 cells (5 PI)
8169 10:02:22.732184 u2DelayCellOfst[7]=17 cells (5 PI)
8170 10:02:22.735299 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8171 10:02:22.738556 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8172 10:02:22.742124 == TX Byte 1 ==
8173 10:02:22.745495 u2DelayCellOfst[8]=3 cells (1 PI)
8174 10:02:22.748674 u2DelayCellOfst[9]=0 cells (0 PI)
8175 10:02:22.751774 u2DelayCellOfst[10]=3 cells (1 PI)
8176 10:02:22.754837 u2DelayCellOfst[11]=3 cells (1 PI)
8177 10:02:22.754924 u2DelayCellOfst[12]=10 cells (3 PI)
8178 10:02:22.758380 u2DelayCellOfst[13]=10 cells (3 PI)
8179 10:02:22.761779 u2DelayCellOfst[14]=14 cells (4 PI)
8180 10:02:22.765071 u2DelayCellOfst[15]=10 cells (3 PI)
8181 10:02:22.771167 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8182 10:02:22.774553 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8183 10:02:22.774675 DramC Write-DBI on
8184 10:02:22.778257 ==
8185 10:02:22.781424 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 10:02:22.785012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 10:02:22.785164 ==
8188 10:02:22.785283
8189 10:02:22.785392
8190 10:02:22.788002 TX Vref Scan disable
8191 10:02:22.788166 == TX Byte 0 ==
8192 10:02:22.794650 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8193 10:02:22.794851 == TX Byte 1 ==
8194 10:02:22.797783 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8195 10:02:22.801100 DramC Write-DBI off
8196 10:02:22.801336
8197 10:02:22.801522 [DATLAT]
8198 10:02:22.804729 Freq=1600, CH0 RK1
8199 10:02:22.805055
8200 10:02:22.805309 DATLAT Default: 0xf
8201 10:02:22.807504 0, 0xFFFF, sum = 0
8202 10:02:22.807880 1, 0xFFFF, sum = 0
8203 10:02:22.811192 2, 0xFFFF, sum = 0
8204 10:02:22.811636 3, 0xFFFF, sum = 0
8205 10:02:22.814382 4, 0xFFFF, sum = 0
8206 10:02:22.818066 5, 0xFFFF, sum = 0
8207 10:02:22.818439 6, 0xFFFF, sum = 0
8208 10:02:22.821224 7, 0xFFFF, sum = 0
8209 10:02:22.821592 8, 0xFFFF, sum = 0
8210 10:02:22.824263 9, 0xFFFF, sum = 0
8211 10:02:22.824784 10, 0xFFFF, sum = 0
8212 10:02:22.827607 11, 0xFFFF, sum = 0
8213 10:02:22.828015 12, 0xFFFF, sum = 0
8214 10:02:22.830953 13, 0xFFFF, sum = 0
8215 10:02:22.831364 14, 0x0, sum = 1
8216 10:02:22.834499 15, 0x0, sum = 2
8217 10:02:22.835035 16, 0x0, sum = 3
8218 10:02:22.837715 17, 0x0, sum = 4
8219 10:02:22.838142 best_step = 15
8220 10:02:22.838475
8221 10:02:22.838780 ==
8222 10:02:22.840733 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 10:02:22.847211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 10:02:22.847663 ==
8225 10:02:22.848179 RX Vref Scan: 0
8226 10:02:22.848537
8227 10:02:22.850863 RX Vref 0 -> 0, step: 1
8228 10:02:22.851379
8229 10:02:22.853884 RX Delay 11 -> 252, step: 4
8230 10:02:22.857136 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8231 10:02:22.860650 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8232 10:02:22.863839 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8233 10:02:22.870259 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8234 10:02:22.873876 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8235 10:02:22.877208 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8236 10:02:22.880152 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8237 10:02:22.883830 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8238 10:02:22.890212 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8239 10:02:22.893425 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8240 10:02:22.896727 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8241 10:02:22.900086 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8242 10:02:22.906550 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8243 10:02:22.909888 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8244 10:02:22.913170 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8245 10:02:22.916359 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8246 10:02:22.916800 ==
8247 10:02:22.919713 Dram Type= 6, Freq= 0, CH_0, rank 1
8248 10:02:22.926780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8249 10:02:22.927324 ==
8250 10:02:22.927802 DQS Delay:
8251 10:02:22.929563 DQS0 = 0, DQS1 = 0
8252 10:02:22.930016 DQM Delay:
8253 10:02:22.930365 DQM0 = 128, DQM1 = 123
8254 10:02:22.933018 DQ Delay:
8255 10:02:22.936130 DQ0 =126, DQ1 =132, DQ2 =124, DQ3 =126
8256 10:02:22.939718 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =134
8257 10:02:22.943286 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8258 10:02:22.946393 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130
8259 10:02:22.946839
8260 10:02:22.947359
8261 10:02:22.947810
8262 10:02:22.949425 [DramC_TX_OE_Calibration] TA2
8263 10:02:22.952616 Original DQ_B0 (3 6) =30, OEN = 27
8264 10:02:22.955959 Original DQ_B1 (3 6) =30, OEN = 27
8265 10:02:22.959194 24, 0x0, End_B0=24 End_B1=24
8266 10:02:22.962645 25, 0x0, End_B0=25 End_B1=25
8267 10:02:22.963230 26, 0x0, End_B0=26 End_B1=26
8268 10:02:22.965685 27, 0x0, End_B0=27 End_B1=27
8269 10:02:22.969359 28, 0x0, End_B0=28 End_B1=28
8270 10:02:22.973106 29, 0x0, End_B0=29 End_B1=29
8271 10:02:22.973534 30, 0x0, End_B0=30 End_B1=30
8272 10:02:22.975809 31, 0x4545, End_B0=30 End_B1=30
8273 10:02:22.979078 Byte0 end_step=30 best_step=27
8274 10:02:22.982136 Byte1 end_step=30 best_step=27
8275 10:02:22.986050 Byte0 TX OE(2T, 0.5T) = (3, 3)
8276 10:02:22.988700 Byte1 TX OE(2T, 0.5T) = (3, 3)
8277 10:02:22.989129
8278 10:02:22.989471
8279 10:02:22.995553 [DQSOSCAuto] RK1, (LSB)MR18= 0x1614, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8280 10:02:22.999112 CH0 RK1: MR19=303, MR18=1614
8281 10:02:23.005794 CH0_RK1: MR19=0x303, MR18=0x1614, DQSOSC=398, MR23=63, INC=23, DEC=15
8282 10:02:23.008947 [RxdqsGatingPostProcess] freq 1600
8283 10:02:23.015283 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8284 10:02:23.015855 best DQS0 dly(2T, 0.5T) = (1, 1)
8285 10:02:23.018447 best DQS1 dly(2T, 0.5T) = (1, 1)
8286 10:02:23.021905 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8287 10:02:23.025410 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8288 10:02:23.027999 best DQS0 dly(2T, 0.5T) = (1, 1)
8289 10:02:23.031366 best DQS1 dly(2T, 0.5T) = (1, 1)
8290 10:02:23.034564 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8291 10:02:23.038646 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8292 10:02:23.041392 Pre-setting of DQS Precalculation
8293 10:02:23.045027 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8294 10:02:23.047912 ==
8295 10:02:23.051042 Dram Type= 6, Freq= 0, CH_1, rank 0
8296 10:02:23.054625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 10:02:23.054721 ==
8298 10:02:23.057919 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8299 10:02:23.064301 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8300 10:02:23.067853 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8301 10:02:23.074051 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8302 10:02:23.082247 [CA 0] Center 41 (11~72) winsize 62
8303 10:02:23.085384 [CA 1] Center 42 (12~72) winsize 61
8304 10:02:23.088849 [CA 2] Center 38 (9~67) winsize 59
8305 10:02:23.092321 [CA 3] Center 37 (8~66) winsize 59
8306 10:02:23.095749 [CA 4] Center 37 (8~67) winsize 60
8307 10:02:23.098816 [CA 5] Center 36 (6~66) winsize 61
8308 10:02:23.098897
8309 10:02:23.101997 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8310 10:02:23.102079
8311 10:02:23.109005 [CATrainingPosCal] consider 1 rank data
8312 10:02:23.109087 u2DelayCellTimex100 = 275/100 ps
8313 10:02:23.115681 CA0 delay=41 (11~72),Diff = 5 PI (17 cell)
8314 10:02:23.118677 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8315 10:02:23.122602 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8316 10:02:23.125807 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8317 10:02:23.128996 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8318 10:02:23.132382 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8319 10:02:23.132528
8320 10:02:23.135109 CA PerBit enable=1, Macro0, CA PI delay=36
8321 10:02:23.135270
8322 10:02:23.138434 [CBTSetCACLKResult] CA Dly = 36
8323 10:02:23.141479 CS Dly: 8 (0~39)
8324 10:02:23.145075 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8325 10:02:23.148462 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8326 10:02:23.148535 ==
8327 10:02:23.151430 Dram Type= 6, Freq= 0, CH_1, rank 1
8328 10:02:23.157942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 10:02:23.158025 ==
8330 10:02:23.161299 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8331 10:02:23.168885 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8332 10:02:23.171003 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8333 10:02:23.177764 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8334 10:02:23.185568 [CA 0] Center 42 (12~72) winsize 61
8335 10:02:23.189635 [CA 1] Center 42 (13~72) winsize 60
8336 10:02:23.192068 [CA 2] Center 38 (9~68) winsize 60
8337 10:02:23.195579 [CA 3] Center 37 (7~67) winsize 61
8338 10:02:23.199042 [CA 4] Center 37 (8~67) winsize 60
8339 10:02:23.201765 [CA 5] Center 37 (7~67) winsize 61
8340 10:02:23.201867
8341 10:02:23.205654 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8342 10:02:23.205750
8343 10:02:23.209005 [CATrainingPosCal] consider 2 rank data
8344 10:02:23.212471 u2DelayCellTimex100 = 275/100 ps
8345 10:02:23.218488 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8346 10:02:23.221632 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8347 10:02:23.225320 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8348 10:02:23.228217 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8349 10:02:23.231761 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8350 10:02:23.235242 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8351 10:02:23.235356
8352 10:02:23.238518 CA PerBit enable=1, Macro0, CA PI delay=36
8353 10:02:23.238608
8354 10:02:23.241475 [CBTSetCACLKResult] CA Dly = 36
8355 10:02:23.244820 CS Dly: 9 (0~42)
8356 10:02:23.248279 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8357 10:02:23.251536 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8358 10:02:23.251634
8359 10:02:23.254612 ----->DramcWriteLeveling(PI) begin...
8360 10:02:23.254707 ==
8361 10:02:23.257905 Dram Type= 6, Freq= 0, CH_1, rank 0
8362 10:02:23.264601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8363 10:02:23.264679 ==
8364 10:02:23.267903 Write leveling (Byte 0): 26 => 26
8365 10:02:23.271650 Write leveling (Byte 1): 26 => 26
8366 10:02:23.271757 DramcWriteLeveling(PI) end<-----
8367 10:02:23.271848
8368 10:02:23.274533 ==
8369 10:02:23.277569 Dram Type= 6, Freq= 0, CH_1, rank 0
8370 10:02:23.281173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8371 10:02:23.281254 ==
8372 10:02:23.284636 [Gating] SW mode calibration
8373 10:02:23.291561 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8374 10:02:23.294183 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8375 10:02:23.301311 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 10:02:23.304176 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 10:02:23.307944 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
8378 10:02:23.314522 1 4 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8379 10:02:23.317873 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 10:02:23.320971 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 10:02:23.327510 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 10:02:23.330917 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 10:02:23.337358 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 10:02:23.340963 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 10:02:23.343809 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8386 10:02:23.350337 1 5 12 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)
8387 10:02:23.354167 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8388 10:02:23.356935 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 10:02:23.363641 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 10:02:23.366763 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 10:02:23.370412 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 10:02:23.376692 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 10:02:23.380473 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8394 10:02:23.383447 1 6 12 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
8395 10:02:23.389807 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 10:02:23.393389 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 10:02:23.396836 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 10:02:23.403458 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 10:02:23.406328 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 10:02:23.409729 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 10:02:23.416506 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 10:02:23.419481 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8403 10:02:23.423330 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8404 10:02:23.429317 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 10:02:23.432946 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 10:02:23.436148 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 10:02:23.442841 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 10:02:23.445810 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 10:02:23.449291 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 10:02:23.455610 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 10:02:23.459328 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 10:02:23.462178 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 10:02:23.469181 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 10:02:23.472475 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 10:02:23.475543 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 10:02:23.482071 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 10:02:23.485491 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8418 10:02:23.488635 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8419 10:02:23.492123 Total UI for P1: 0, mck2ui 16
8420 10:02:23.495493 best dqsien dly found for B0: ( 1, 9, 8)
8421 10:02:23.502654 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8422 10:02:23.505542 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 10:02:23.508518 Total UI for P1: 0, mck2ui 16
8424 10:02:23.512018 best dqsien dly found for B1: ( 1, 9, 14)
8425 10:02:23.515273 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8426 10:02:23.518498 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8427 10:02:23.519043
8428 10:02:23.521688 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8429 10:02:23.525226 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8430 10:02:23.528561 [Gating] SW calibration Done
8431 10:02:23.528984 ==
8432 10:02:23.531713 Dram Type= 6, Freq= 0, CH_1, rank 0
8433 10:02:23.534840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8434 10:02:23.537893 ==
8435 10:02:23.538314 RX Vref Scan: 0
8436 10:02:23.538645
8437 10:02:23.541122 RX Vref 0 -> 0, step: 1
8438 10:02:23.541542
8439 10:02:23.545025 RX Delay 0 -> 252, step: 8
8440 10:02:23.547540 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8441 10:02:23.550828 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8442 10:02:23.554251 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8443 10:02:23.557314 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8444 10:02:23.563861 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8445 10:02:23.567245 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8446 10:02:23.570522 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8447 10:02:23.574286 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8448 10:02:23.577150 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8449 10:02:23.583846 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8450 10:02:23.587286 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8451 10:02:23.590443 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8452 10:02:23.594150 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8453 10:02:23.597796 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8454 10:02:23.603756 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8455 10:02:23.607239 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8456 10:02:23.607415 ==
8457 10:02:23.609941 Dram Type= 6, Freq= 0, CH_1, rank 0
8458 10:02:23.613166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8459 10:02:23.613315 ==
8460 10:02:23.616681 DQS Delay:
8461 10:02:23.616789 DQS0 = 0, DQS1 = 0
8462 10:02:23.620669 DQM Delay:
8463 10:02:23.620788 DQM0 = 135, DQM1 = 131
8464 10:02:23.620887 DQ Delay:
8465 10:02:23.626917 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8466 10:02:23.630390 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8467 10:02:23.633139 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8468 10:02:23.636651 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8469 10:02:23.636827
8470 10:02:23.636985
8471 10:02:23.637127 ==
8472 10:02:23.639741 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 10:02:23.643599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 10:02:23.643816 ==
8475 10:02:23.644005
8476 10:02:23.644204
8477 10:02:23.646323 TX Vref Scan disable
8478 10:02:23.649650 == TX Byte 0 ==
8479 10:02:23.653083 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8480 10:02:23.657180 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8481 10:02:23.660011 == TX Byte 1 ==
8482 10:02:23.663584 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8483 10:02:23.666056 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8484 10:02:23.666587 ==
8485 10:02:23.669650 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 10:02:23.675903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 10:02:23.676409 ==
8488 10:02:23.688942
8489 10:02:23.691912 TX Vref early break, caculate TX vref
8490 10:02:23.694941 TX Vref=16, minBit 8, minWin=21, winSum=368
8491 10:02:23.698286 TX Vref=18, minBit 8, minWin=22, winSum=377
8492 10:02:23.701586 TX Vref=20, minBit 3, minWin=23, winSum=387
8493 10:02:23.705111 TX Vref=22, minBit 9, minWin=23, winSum=399
8494 10:02:23.708443 TX Vref=24, minBit 9, minWin=24, winSum=405
8495 10:02:23.714817 TX Vref=26, minBit 9, minWin=24, winSum=414
8496 10:02:23.718369 TX Vref=28, minBit 0, minWin=25, winSum=415
8497 10:02:23.722077 TX Vref=30, minBit 0, minWin=25, winSum=414
8498 10:02:23.724859 TX Vref=32, minBit 10, minWin=24, winSum=403
8499 10:02:23.727910 TX Vref=34, minBit 0, minWin=24, winSum=399
8500 10:02:23.734949 TX Vref=36, minBit 9, minWin=22, winSum=385
8501 10:02:23.738023 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
8502 10:02:23.738453
8503 10:02:23.741298 Final TX Range 0 Vref 28
8504 10:02:23.741726
8505 10:02:23.742155 ==
8506 10:02:23.744493 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 10:02:23.747469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 10:02:23.750919 ==
8509 10:02:23.751347
8510 10:02:23.751770
8511 10:02:23.752262 TX Vref Scan disable
8512 10:02:23.757897 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8513 10:02:23.758325 == TX Byte 0 ==
8514 10:02:23.761390 u2DelayCellOfst[0]=17 cells (5 PI)
8515 10:02:23.764622 u2DelayCellOfst[1]=10 cells (3 PI)
8516 10:02:23.768189 u2DelayCellOfst[2]=0 cells (0 PI)
8517 10:02:23.771319 u2DelayCellOfst[3]=7 cells (2 PI)
8518 10:02:23.774218 u2DelayCellOfst[4]=7 cells (2 PI)
8519 10:02:23.777955 u2DelayCellOfst[5]=17 cells (5 PI)
8520 10:02:23.781306 u2DelayCellOfst[6]=17 cells (5 PI)
8521 10:02:23.784681 u2DelayCellOfst[7]=7 cells (2 PI)
8522 10:02:23.787801 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8523 10:02:23.790836 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8524 10:02:23.794389 == TX Byte 1 ==
8525 10:02:23.797707 u2DelayCellOfst[8]=0 cells (0 PI)
8526 10:02:23.800575 u2DelayCellOfst[9]=7 cells (2 PI)
8527 10:02:23.804465 u2DelayCellOfst[10]=10 cells (3 PI)
8528 10:02:23.807359 u2DelayCellOfst[11]=3 cells (1 PI)
8529 10:02:23.810507 u2DelayCellOfst[12]=14 cells (4 PI)
8530 10:02:23.810928 u2DelayCellOfst[13]=14 cells (4 PI)
8531 10:02:23.814303 u2DelayCellOfst[14]=17 cells (5 PI)
8532 10:02:23.818578 u2DelayCellOfst[15]=17 cells (5 PI)
8533 10:02:23.823955 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8534 10:02:23.827631 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8535 10:02:23.830545 DramC Write-DBI on
8536 10:02:23.830965 ==
8537 10:02:23.833755 Dram Type= 6, Freq= 0, CH_1, rank 0
8538 10:02:23.837129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8539 10:02:23.837553 ==
8540 10:02:23.837882
8541 10:02:23.838185
8542 10:02:23.840664 TX Vref Scan disable
8543 10:02:23.841208 == TX Byte 0 ==
8544 10:02:23.847196 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8545 10:02:23.847696 == TX Byte 1 ==
8546 10:02:23.850242 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8547 10:02:23.853943 DramC Write-DBI off
8548 10:02:23.854364
8549 10:02:23.854694 [DATLAT]
8550 10:02:23.856785 Freq=1600, CH1 RK0
8551 10:02:23.857210
8552 10:02:23.857543 DATLAT Default: 0xf
8553 10:02:23.860008 0, 0xFFFF, sum = 0
8554 10:02:23.860462 1, 0xFFFF, sum = 0
8555 10:02:23.863253 2, 0xFFFF, sum = 0
8556 10:02:23.866724 3, 0xFFFF, sum = 0
8557 10:02:23.867149 4, 0xFFFF, sum = 0
8558 10:02:23.869823 5, 0xFFFF, sum = 0
8559 10:02:23.870252 6, 0xFFFF, sum = 0
8560 10:02:23.873359 7, 0xFFFF, sum = 0
8561 10:02:23.873786 8, 0xFFFF, sum = 0
8562 10:02:23.876587 9, 0xFFFF, sum = 0
8563 10:02:23.877015 10, 0xFFFF, sum = 0
8564 10:02:23.880749 11, 0xFFFF, sum = 0
8565 10:02:23.881469 12, 0xFFFF, sum = 0
8566 10:02:23.883565 13, 0xFFFF, sum = 0
8567 10:02:23.883993 14, 0x0, sum = 1
8568 10:02:23.886697 15, 0x0, sum = 2
8569 10:02:23.886780 16, 0x0, sum = 3
8570 10:02:23.889425 17, 0x0, sum = 4
8571 10:02:23.889508 best_step = 15
8572 10:02:23.889573
8573 10:02:23.889632 ==
8574 10:02:23.892736 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 10:02:23.899260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 10:02:23.899351 ==
8577 10:02:23.899422 RX Vref Scan: 1
8578 10:02:23.899483
8579 10:02:23.902294 Set Vref Range= 24 -> 127
8580 10:02:23.902376
8581 10:02:23.905495 RX Vref 24 -> 127, step: 1
8582 10:02:23.905577
8583 10:02:23.905641 RX Delay 19 -> 252, step: 4
8584 10:02:23.909023
8585 10:02:23.909104 Set Vref, RX VrefLevel [Byte0]: 24
8586 10:02:23.912779 [Byte1]: 24
8587 10:02:23.916731
8588 10:02:23.916812 Set Vref, RX VrefLevel [Byte0]: 25
8589 10:02:23.919698 [Byte1]: 25
8590 10:02:23.924943
8591 10:02:23.925024 Set Vref, RX VrefLevel [Byte0]: 26
8592 10:02:23.927247 [Byte1]: 26
8593 10:02:23.931839
8594 10:02:23.931920 Set Vref, RX VrefLevel [Byte0]: 27
8595 10:02:23.935306 [Byte1]: 27
8596 10:02:23.939127
8597 10:02:23.939218 Set Vref, RX VrefLevel [Byte0]: 28
8598 10:02:23.942993 [Byte1]: 28
8599 10:02:23.946878
8600 10:02:23.946978 Set Vref, RX VrefLevel [Byte0]: 29
8601 10:02:23.950278 [Byte1]: 29
8602 10:02:23.954095
8603 10:02:23.954176 Set Vref, RX VrefLevel [Byte0]: 30
8604 10:02:23.957640 [Byte1]: 30
8605 10:02:23.962027
8606 10:02:23.965139 Set Vref, RX VrefLevel [Byte0]: 31
8607 10:02:23.968264 [Byte1]: 31
8608 10:02:23.968352
8609 10:02:23.971915 Set Vref, RX VrefLevel [Byte0]: 32
8610 10:02:23.974933 [Byte1]: 32
8611 10:02:23.975027
8612 10:02:23.979105 Set Vref, RX VrefLevel [Byte0]: 33
8613 10:02:23.982208 [Byte1]: 33
8614 10:02:23.982395
8615 10:02:23.984843 Set Vref, RX VrefLevel [Byte0]: 34
8616 10:02:23.988554 [Byte1]: 34
8617 10:02:23.992129
8618 10:02:23.992267 Set Vref, RX VrefLevel [Byte0]: 35
8619 10:02:23.995860 [Byte1]: 35
8620 10:02:23.999701
8621 10:02:23.999914 Set Vref, RX VrefLevel [Byte0]: 36
8622 10:02:24.003331 [Byte1]: 36
8623 10:02:24.007444
8624 10:02:24.007663 Set Vref, RX VrefLevel [Byte0]: 37
8625 10:02:24.010584 [Byte1]: 37
8626 10:02:24.015291
8627 10:02:24.015611 Set Vref, RX VrefLevel [Byte0]: 38
8628 10:02:24.018619 [Byte1]: 38
8629 10:02:24.022704
8630 10:02:24.023112 Set Vref, RX VrefLevel [Byte0]: 39
8631 10:02:24.026585 [Byte1]: 39
8632 10:02:24.030572
8633 10:02:24.030992 Set Vref, RX VrefLevel [Byte0]: 40
8634 10:02:24.033962 [Byte1]: 40
8635 10:02:24.037984
8636 10:02:24.038401 Set Vref, RX VrefLevel [Byte0]: 41
8637 10:02:24.041223 [Byte1]: 41
8638 10:02:24.045565
8639 10:02:24.046144 Set Vref, RX VrefLevel [Byte0]: 42
8640 10:02:24.049191 [Byte1]: 42
8641 10:02:24.053027
8642 10:02:24.053443 Set Vref, RX VrefLevel [Byte0]: 43
8643 10:02:24.056545 [Byte1]: 43
8644 10:02:24.060534
8645 10:02:24.060952 Set Vref, RX VrefLevel [Byte0]: 44
8646 10:02:24.064138 [Byte1]: 44
8647 10:02:24.068731
8648 10:02:24.069150 Set Vref, RX VrefLevel [Byte0]: 45
8649 10:02:24.072074 [Byte1]: 45
8650 10:02:24.076149
8651 10:02:24.076568 Set Vref, RX VrefLevel [Byte0]: 46
8652 10:02:24.078969 [Byte1]: 46
8653 10:02:24.083736
8654 10:02:24.084280 Set Vref, RX VrefLevel [Byte0]: 47
8655 10:02:24.086867 [Byte1]: 47
8656 10:02:24.091487
8657 10:02:24.091900 Set Vref, RX VrefLevel [Byte0]: 48
8658 10:02:24.094662 [Byte1]: 48
8659 10:02:24.099328
8660 10:02:24.099847 Set Vref, RX VrefLevel [Byte0]: 49
8661 10:02:24.102209 [Byte1]: 49
8662 10:02:24.106063
8663 10:02:24.106612 Set Vref, RX VrefLevel [Byte0]: 50
8664 10:02:24.109795 [Byte1]: 50
8665 10:02:24.113722
8666 10:02:24.114138 Set Vref, RX VrefLevel [Byte0]: 51
8667 10:02:24.116952 [Byte1]: 51
8668 10:02:24.121351
8669 10:02:24.121871 Set Vref, RX VrefLevel [Byte0]: 52
8670 10:02:24.124850 [Byte1]: 52
8671 10:02:24.128897
8672 10:02:24.129313 Set Vref, RX VrefLevel [Byte0]: 53
8673 10:02:24.131949 [Byte1]: 53
8674 10:02:24.136880
8675 10:02:24.137293 Set Vref, RX VrefLevel [Byte0]: 54
8676 10:02:24.139826 [Byte1]: 54
8677 10:02:24.144356
8678 10:02:24.144771 Set Vref, RX VrefLevel [Byte0]: 55
8679 10:02:24.147664 [Byte1]: 55
8680 10:02:24.151342
8681 10:02:24.151754 Set Vref, RX VrefLevel [Byte0]: 56
8682 10:02:24.155165 [Byte1]: 56
8683 10:02:24.158978
8684 10:02:24.159563 Set Vref, RX VrefLevel [Byte0]: 57
8685 10:02:24.162235 [Byte1]: 57
8686 10:02:24.166665
8687 10:02:24.167107 Set Vref, RX VrefLevel [Byte0]: 58
8688 10:02:24.170220 [Byte1]: 58
8689 10:02:24.174831
8690 10:02:24.175325 Set Vref, RX VrefLevel [Byte0]: 59
8691 10:02:24.178071 [Byte1]: 59
8692 10:02:24.181917
8693 10:02:24.182471 Set Vref, RX VrefLevel [Byte0]: 60
8694 10:02:24.185333 [Byte1]: 60
8695 10:02:24.189562
8696 10:02:24.190129 Set Vref, RX VrefLevel [Byte0]: 61
8697 10:02:24.192571 [Byte1]: 61
8698 10:02:24.196908
8699 10:02:24.197357 Set Vref, RX VrefLevel [Byte0]: 62
8700 10:02:24.200295 [Byte1]: 62
8701 10:02:24.204511
8702 10:02:24.204931 Set Vref, RX VrefLevel [Byte0]: 63
8703 10:02:24.207731 [Byte1]: 63
8704 10:02:24.212513
8705 10:02:24.213102 Set Vref, RX VrefLevel [Byte0]: 64
8706 10:02:24.215530 [Byte1]: 64
8707 10:02:24.219828
8708 10:02:24.220345 Set Vref, RX VrefLevel [Byte0]: 65
8709 10:02:24.223217 [Byte1]: 65
8710 10:02:24.227637
8711 10:02:24.228197 Set Vref, RX VrefLevel [Byte0]: 66
8712 10:02:24.230654 [Byte1]: 66
8713 10:02:24.234757
8714 10:02:24.235176 Set Vref, RX VrefLevel [Byte0]: 67
8715 10:02:24.238467 [Byte1]: 67
8716 10:02:24.242924
8717 10:02:24.243473 Set Vref, RX VrefLevel [Byte0]: 68
8718 10:02:24.245902 [Byte1]: 68
8719 10:02:24.250219
8720 10:02:24.250639 Set Vref, RX VrefLevel [Byte0]: 69
8721 10:02:24.253267 [Byte1]: 69
8722 10:02:24.257374
8723 10:02:24.260886 Final RX Vref Byte 0 = 57 to rank0
8724 10:02:24.261399 Final RX Vref Byte 1 = 61 to rank0
8725 10:02:24.264603 Final RX Vref Byte 0 = 57 to rank1
8726 10:02:24.267527 Final RX Vref Byte 1 = 61 to rank1==
8727 10:02:24.270704 Dram Type= 6, Freq= 0, CH_1, rank 0
8728 10:02:24.277694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8729 10:02:24.278120 ==
8730 10:02:24.278450 DQS Delay:
8731 10:02:24.281076 DQS0 = 0, DQS1 = 0
8732 10:02:24.281499 DQM Delay:
8733 10:02:24.281830 DQM0 = 132, DQM1 = 130
8734 10:02:24.284389 DQ Delay:
8735 10:02:24.287180 DQ0 =140, DQ1 =130, DQ2 =118, DQ3 =130
8736 10:02:24.290890 DQ4 =128, DQ5 =144, DQ6 =146, DQ7 =126
8737 10:02:24.293924 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =122
8738 10:02:24.297650 DQ12 =140, DQ13 =140, DQ14 =136, DQ15 =140
8739 10:02:24.298069
8740 10:02:24.298396
8741 10:02:24.298699
8742 10:02:24.300169 [DramC_TX_OE_Calibration] TA2
8743 10:02:24.303920 Original DQ_B0 (3 6) =30, OEN = 27
8744 10:02:24.307009 Original DQ_B1 (3 6) =30, OEN = 27
8745 10:02:24.310059 24, 0x0, End_B0=24 End_B1=24
8746 10:02:24.313688 25, 0x0, End_B0=25 End_B1=25
8747 10:02:24.314120 26, 0x0, End_B0=26 End_B1=26
8748 10:02:24.316895 27, 0x0, End_B0=27 End_B1=27
8749 10:02:24.319945 28, 0x0, End_B0=28 End_B1=28
8750 10:02:24.323411 29, 0x0, End_B0=29 End_B1=29
8751 10:02:24.323837 30, 0x0, End_B0=30 End_B1=30
8752 10:02:24.326798 31, 0x4141, End_B0=30 End_B1=30
8753 10:02:24.329998 Byte0 end_step=30 best_step=27
8754 10:02:24.333343 Byte1 end_step=30 best_step=27
8755 10:02:24.336586 Byte0 TX OE(2T, 0.5T) = (3, 3)
8756 10:02:24.339496 Byte1 TX OE(2T, 0.5T) = (3, 3)
8757 10:02:24.339919
8758 10:02:24.340285
8759 10:02:24.345721 [DQSOSCAuto] RK0, (LSB)MR18= 0xb15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
8760 10:02:24.349509 CH1 RK0: MR19=303, MR18=B15
8761 10:02:24.355678 CH1_RK0: MR19=0x303, MR18=0xB15, DQSOSC=399, MR23=63, INC=23, DEC=15
8762 10:02:24.355760
8763 10:02:24.358888 ----->DramcWriteLeveling(PI) begin...
8764 10:02:24.358972 ==
8765 10:02:24.362337 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 10:02:24.365474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 10:02:24.365556 ==
8768 10:02:24.368895 Write leveling (Byte 0): 25 => 25
8769 10:02:24.372760 Write leveling (Byte 1): 26 => 26
8770 10:02:24.375652 DramcWriteLeveling(PI) end<-----
8771 10:02:24.375754
8772 10:02:24.375861 ==
8773 10:02:24.378640 Dram Type= 6, Freq= 0, CH_1, rank 1
8774 10:02:24.385144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 10:02:24.385227 ==
8776 10:02:24.385290 [Gating] SW mode calibration
8777 10:02:24.395342 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8778 10:02:24.398428 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8779 10:02:24.404769 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 10:02:24.408290 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 10:02:24.411780 1 4 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
8782 10:02:24.418339 1 4 12 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
8783 10:02:24.421154 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 10:02:24.424708 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 10:02:24.430939 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 10:02:24.434627 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 10:02:24.438036 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 10:02:24.444663 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8789 10:02:24.448200 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8790 10:02:24.451211 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8791 10:02:24.457780 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8792 10:02:24.460987 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 10:02:24.464353 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 10:02:24.470740 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 10:02:24.474093 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 10:02:24.477765 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8797 10:02:24.484554 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8798 10:02:24.487189 1 6 12 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
8799 10:02:24.490858 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 10:02:24.497556 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 10:02:24.500438 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 10:02:24.503803 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 10:02:24.510620 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 10:02:24.513783 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8805 10:02:24.517038 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8806 10:02:24.523457 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8807 10:02:24.526980 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8808 10:02:24.530436 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 10:02:24.536645 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 10:02:24.539943 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 10:02:24.543010 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 10:02:24.549821 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 10:02:24.553286 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 10:02:24.556474 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 10:02:24.563411 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 10:02:24.566438 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 10:02:24.569679 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 10:02:24.576360 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 10:02:24.579199 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 10:02:24.583511 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 10:02:24.589238 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8822 10:02:24.592753 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8823 10:02:24.595871 Total UI for P1: 0, mck2ui 16
8824 10:02:24.599322 best dqsien dly found for B0: ( 1, 9, 8)
8825 10:02:24.602202 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8826 10:02:24.608806 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 10:02:24.612116 Total UI for P1: 0, mck2ui 16
8828 10:02:24.615647 best dqsien dly found for B1: ( 1, 9, 14)
8829 10:02:24.618872 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8830 10:02:24.622211 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8831 10:02:24.622632
8832 10:02:24.625421 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8833 10:02:24.629182 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8834 10:02:24.632383 [Gating] SW calibration Done
8835 10:02:24.632893 ==
8836 10:02:24.635985 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 10:02:24.638655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 10:02:24.639165 ==
8839 10:02:24.642506 RX Vref Scan: 0
8840 10:02:24.642990
8841 10:02:24.645202 RX Vref 0 -> 0, step: 1
8842 10:02:24.645655
8843 10:02:24.645990 RX Delay 0 -> 252, step: 8
8844 10:02:24.652540 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8845 10:02:24.655511 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8846 10:02:24.658345 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8847 10:02:24.661433 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8848 10:02:24.664823 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8849 10:02:24.671482 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8850 10:02:24.674743 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8851 10:02:24.678990 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8852 10:02:24.681223 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8853 10:02:24.684670 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8854 10:02:24.691680 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8855 10:02:24.694763 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8856 10:02:24.698567 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8857 10:02:24.701388 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8858 10:02:24.707875 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8859 10:02:24.710816 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8860 10:02:24.711236 ==
8861 10:02:24.714020 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 10:02:24.717780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 10:02:24.718199 ==
8864 10:02:24.720816 DQS Delay:
8865 10:02:24.721232 DQS0 = 0, DQS1 = 0
8866 10:02:24.721564 DQM Delay:
8867 10:02:24.724245 DQM0 = 136, DQM1 = 130
8868 10:02:24.724775 DQ Delay:
8869 10:02:24.727168 DQ0 =139, DQ1 =135, DQ2 =127, DQ3 =135
8870 10:02:24.730714 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =135
8871 10:02:24.737272 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8872 10:02:24.740395 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8873 10:02:24.740916
8874 10:02:24.741252
8875 10:02:24.741563 ==
8876 10:02:24.744109 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 10:02:24.747499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 10:02:24.748100 ==
8879 10:02:24.748484
8880 10:02:24.748824
8881 10:02:24.750656 TX Vref Scan disable
8882 10:02:24.754106 == TX Byte 0 ==
8883 10:02:24.757406 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8884 10:02:24.760266 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8885 10:02:24.763782 == TX Byte 1 ==
8886 10:02:24.768231 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8887 10:02:24.770182 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8888 10:02:24.770670 ==
8889 10:02:24.773313 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 10:02:24.776695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 10:02:24.779859 ==
8892 10:02:24.792228
8893 10:02:24.795466 TX Vref early break, caculate TX vref
8894 10:02:24.798740 TX Vref=16, minBit 9, minWin=22, winSum=378
8895 10:02:24.802422 TX Vref=18, minBit 9, minWin=22, winSum=383
8896 10:02:24.805609 TX Vref=20, minBit 9, minWin=22, winSum=392
8897 10:02:24.808990 TX Vref=22, minBit 9, minWin=22, winSum=399
8898 10:02:24.812113 TX Vref=24, minBit 5, minWin=24, winSum=404
8899 10:02:24.819076 TX Vref=26, minBit 9, minWin=24, winSum=414
8900 10:02:24.821893 TX Vref=28, minBit 9, minWin=25, winSum=422
8901 10:02:24.824943 TX Vref=30, minBit 9, minWin=25, winSum=417
8902 10:02:24.828184 TX Vref=32, minBit 0, minWin=24, winSum=409
8903 10:02:24.831712 TX Vref=34, minBit 9, minWin=23, winSum=402
8904 10:02:24.838341 TX Vref=36, minBit 8, minWin=23, winSum=398
8905 10:02:24.842202 [TxChooseVref] Worse bit 9, Min win 25, Win sum 422, Final Vref 28
8906 10:02:24.842761
8907 10:02:24.845089 Final TX Range 0 Vref 28
8908 10:02:24.845549
8909 10:02:24.845911 ==
8910 10:02:24.847870 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 10:02:24.850849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 10:02:24.853828 ==
8913 10:02:24.853910
8914 10:02:24.853973
8915 10:02:24.854032 TX Vref Scan disable
8916 10:02:24.860759 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8917 10:02:24.860841 == TX Byte 0 ==
8918 10:02:24.864444 u2DelayCellOfst[0]=14 cells (4 PI)
8919 10:02:24.867655 u2DelayCellOfst[1]=10 cells (3 PI)
8920 10:02:24.870957 u2DelayCellOfst[2]=0 cells (0 PI)
8921 10:02:24.874091 u2DelayCellOfst[3]=3 cells (1 PI)
8922 10:02:24.877104 u2DelayCellOfst[4]=7 cells (2 PI)
8923 10:02:24.880559 u2DelayCellOfst[5]=14 cells (4 PI)
8924 10:02:24.883964 u2DelayCellOfst[6]=14 cells (4 PI)
8925 10:02:24.887616 u2DelayCellOfst[7]=7 cells (2 PI)
8926 10:02:24.891544 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8927 10:02:24.894052 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8928 10:02:24.897000 == TX Byte 1 ==
8929 10:02:24.900721 u2DelayCellOfst[8]=0 cells (0 PI)
8930 10:02:24.903960 u2DelayCellOfst[9]=3 cells (1 PI)
8931 10:02:24.907065 u2DelayCellOfst[10]=10 cells (3 PI)
8932 10:02:24.910513 u2DelayCellOfst[11]=7 cells (2 PI)
8933 10:02:24.914102 u2DelayCellOfst[12]=14 cells (4 PI)
8934 10:02:24.917204 u2DelayCellOfst[13]=14 cells (4 PI)
8935 10:02:24.920063 u2DelayCellOfst[14]=17 cells (5 PI)
8936 10:02:24.920265 u2DelayCellOfst[15]=17 cells (5 PI)
8937 10:02:24.926815 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8938 10:02:24.930723 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8939 10:02:24.933462 DramC Write-DBI on
8940 10:02:24.933761 ==
8941 10:02:24.936961 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 10:02:24.940701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 10:02:24.941193 ==
8944 10:02:24.941497
8945 10:02:24.941776
8946 10:02:24.943972 TX Vref Scan disable
8947 10:02:24.944486 == TX Byte 0 ==
8948 10:02:24.950574 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8949 10:02:24.951179 == TX Byte 1 ==
8950 10:02:24.954103 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8951 10:02:24.956842 DramC Write-DBI off
8952 10:02:24.957380
8953 10:02:24.957828 [DATLAT]
8954 10:02:24.959818 Freq=1600, CH1 RK1
8955 10:02:24.960329
8956 10:02:24.960764 DATLAT Default: 0xf
8957 10:02:24.963795 0, 0xFFFF, sum = 0
8958 10:02:24.964381 1, 0xFFFF, sum = 0
8959 10:02:24.966529 2, 0xFFFF, sum = 0
8960 10:02:24.970136 3, 0xFFFF, sum = 0
8961 10:02:24.970602 4, 0xFFFF, sum = 0
8962 10:02:24.973256 5, 0xFFFF, sum = 0
8963 10:02:24.973705 6, 0xFFFF, sum = 0
8964 10:02:24.976279 7, 0xFFFF, sum = 0
8965 10:02:24.976732 8, 0xFFFF, sum = 0
8966 10:02:24.979757 9, 0xFFFF, sum = 0
8967 10:02:24.980230 10, 0xFFFF, sum = 0
8968 10:02:24.983212 11, 0xFFFF, sum = 0
8969 10:02:24.983629 12, 0xFFFF, sum = 0
8970 10:02:24.986807 13, 0xFFFF, sum = 0
8971 10:02:24.987335 14, 0x0, sum = 1
8972 10:02:24.989541 15, 0x0, sum = 2
8973 10:02:24.989960 16, 0x0, sum = 3
8974 10:02:24.992847 17, 0x0, sum = 4
8975 10:02:24.993272 best_step = 15
8976 10:02:24.993597
8977 10:02:24.993896 ==
8978 10:02:24.996322 Dram Type= 6, Freq= 0, CH_1, rank 1
8979 10:02:25.003032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8980 10:02:25.003549 ==
8981 10:02:25.003880 RX Vref Scan: 0
8982 10:02:25.004233
8983 10:02:25.005874 RX Vref 0 -> 0, step: 1
8984 10:02:25.006283
8985 10:02:25.009394 RX Delay 11 -> 252, step: 4
8986 10:02:25.012825 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8987 10:02:25.015910 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8988 10:02:25.022891 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8989 10:02:25.026011 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8990 10:02:25.029650 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8991 10:02:25.032535 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8992 10:02:25.035560 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8993 10:02:25.042566 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8994 10:02:25.046299 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8995 10:02:25.048789 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8996 10:02:25.052348 iDelay=195, Bit 10, Center 130 (75 ~ 186) 112
8997 10:02:25.055219 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8998 10:02:25.062314 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8999 10:02:25.065237 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9000 10:02:25.068420 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9001 10:02:25.071735 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9002 10:02:25.072182 ==
9003 10:02:25.075594 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 10:02:25.081693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 10:02:25.082114 ==
9006 10:02:25.082456 DQS Delay:
9007 10:02:25.085986 DQS0 = 0, DQS1 = 0
9008 10:02:25.086399 DQM Delay:
9009 10:02:25.088874 DQM0 = 133, DQM1 = 128
9010 10:02:25.089287 DQ Delay:
9011 10:02:25.091668 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
9012 10:02:25.095401 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =130
9013 10:02:25.098659 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
9014 10:02:25.101501 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =136
9015 10:02:25.101918
9016 10:02:25.102240
9017 10:02:25.102541
9018 10:02:25.105521 [DramC_TX_OE_Calibration] TA2
9019 10:02:25.108360 Original DQ_B0 (3 6) =30, OEN = 27
9020 10:02:25.111142 Original DQ_B1 (3 6) =30, OEN = 27
9021 10:02:25.114826 24, 0x0, End_B0=24 End_B1=24
9022 10:02:25.118008 25, 0x0, End_B0=25 End_B1=25
9023 10:02:25.118467 26, 0x0, End_B0=26 End_B1=26
9024 10:02:25.121207 27, 0x0, End_B0=27 End_B1=27
9025 10:02:25.125023 28, 0x0, End_B0=28 End_B1=28
9026 10:02:25.127897 29, 0x0, End_B0=29 End_B1=29
9027 10:02:25.131481 30, 0x0, End_B0=30 End_B1=30
9028 10:02:25.131931 31, 0x4141, End_B0=30 End_B1=30
9029 10:02:25.134747 Byte0 end_step=30 best_step=27
9030 10:02:25.137529 Byte1 end_step=30 best_step=27
9031 10:02:25.141004 Byte0 TX OE(2T, 0.5T) = (3, 3)
9032 10:02:25.144497 Byte1 TX OE(2T, 0.5T) = (3, 3)
9033 10:02:25.144990
9034 10:02:25.145337
9035 10:02:25.151231 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
9036 10:02:25.153975 CH1 RK1: MR19=303, MR18=F1D
9037 10:02:25.160748 CH1_RK1: MR19=0x303, MR18=0xF1D, DQSOSC=395, MR23=63, INC=23, DEC=15
9038 10:02:25.164100 [RxdqsGatingPostProcess] freq 1600
9039 10:02:25.170136 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9040 10:02:25.170216 best DQS0 dly(2T, 0.5T) = (1, 1)
9041 10:02:25.174207 best DQS1 dly(2T, 0.5T) = (1, 1)
9042 10:02:25.177066 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9043 10:02:25.180315 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9044 10:02:25.183309 best DQS0 dly(2T, 0.5T) = (1, 1)
9045 10:02:25.187414 best DQS1 dly(2T, 0.5T) = (1, 1)
9046 10:02:25.190343 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9047 10:02:25.193318 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9048 10:02:25.196676 Pre-setting of DQS Precalculation
9049 10:02:25.199834 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9050 10:02:25.210027 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9051 10:02:25.216760 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9052 10:02:25.216962
9053 10:02:25.217118
9054 10:02:25.219765 [Calibration Summary] 3200 Mbps
9055 10:02:25.219959 CH 0, Rank 0
9056 10:02:25.223445 SW Impedance : PASS
9057 10:02:25.223781 DUTY Scan : NO K
9058 10:02:25.226633 ZQ Calibration : PASS
9059 10:02:25.229676 Jitter Meter : NO K
9060 10:02:25.230066 CBT Training : PASS
9061 10:02:25.233420 Write leveling : PASS
9062 10:02:25.236460 RX DQS gating : PASS
9063 10:02:25.236915 RX DQ/DQS(RDDQC) : PASS
9064 10:02:25.239737 TX DQ/DQS : PASS
9065 10:02:25.242993 RX DATLAT : PASS
9066 10:02:25.243429 RX DQ/DQS(Engine): PASS
9067 10:02:25.246554 TX OE : PASS
9068 10:02:25.246975 All Pass.
9069 10:02:25.247319
9070 10:02:25.249535 CH 0, Rank 1
9071 10:02:25.249955 SW Impedance : PASS
9072 10:02:25.252883 DUTY Scan : NO K
9073 10:02:25.256210 ZQ Calibration : PASS
9074 10:02:25.256632 Jitter Meter : NO K
9075 10:02:25.259987 CBT Training : PASS
9076 10:02:25.263132 Write leveling : PASS
9077 10:02:25.263552 RX DQS gating : PASS
9078 10:02:25.266129 RX DQ/DQS(RDDQC) : PASS
9079 10:02:25.269634 TX DQ/DQS : PASS
9080 10:02:25.270054 RX DATLAT : PASS
9081 10:02:25.272660 RX DQ/DQS(Engine): PASS
9082 10:02:25.275722 TX OE : PASS
9083 10:02:25.276216 All Pass.
9084 10:02:25.276590
9085 10:02:25.276917 CH 1, Rank 0
9086 10:02:25.279680 SW Impedance : PASS
9087 10:02:25.282702 DUTY Scan : NO K
9088 10:02:25.283330 ZQ Calibration : PASS
9089 10:02:25.285911 Jitter Meter : NO K
9090 10:02:25.289076 CBT Training : PASS
9091 10:02:25.289535 Write leveling : PASS
9092 10:02:25.292108 RX DQS gating : PASS
9093 10:02:25.295844 RX DQ/DQS(RDDQC) : PASS
9094 10:02:25.296352 TX DQ/DQS : PASS
9095 10:02:25.299533 RX DATLAT : PASS
9096 10:02:25.300020 RX DQ/DQS(Engine): PASS
9097 10:02:25.302019 TX OE : PASS
9098 10:02:25.302499 All Pass.
9099 10:02:25.302831
9100 10:02:25.305473 CH 1, Rank 1
9101 10:02:25.309171 SW Impedance : PASS
9102 10:02:25.309637 DUTY Scan : NO K
9103 10:02:25.312429 ZQ Calibration : PASS
9104 10:02:25.312847 Jitter Meter : NO K
9105 10:02:25.316137 CBT Training : PASS
9106 10:02:25.318708 Write leveling : PASS
9107 10:02:25.319178 RX DQS gating : PASS
9108 10:02:25.322034 RX DQ/DQS(RDDQC) : PASS
9109 10:02:25.325672 TX DQ/DQS : PASS
9110 10:02:25.326089 RX DATLAT : PASS
9111 10:02:25.328557 RX DQ/DQS(Engine): PASS
9112 10:02:25.332106 TX OE : PASS
9113 10:02:25.332530 All Pass.
9114 10:02:25.332885
9115 10:02:25.334853 DramC Write-DBI on
9116 10:02:25.335267 PER_BANK_REFRESH: Hybrid Mode
9117 10:02:25.338585 TX_TRACKING: ON
9118 10:02:25.348634 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9119 10:02:25.355338 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9120 10:02:25.361996 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9121 10:02:25.364968 [FAST_K] Save calibration result to emmc
9122 10:02:25.367780 sync common calibartion params.
9123 10:02:25.371535 sync cbt_mode0:1, 1:1
9124 10:02:25.371949 dram_init: ddr_geometry: 2
9125 10:02:25.374874 dram_init: ddr_geometry: 2
9126 10:02:25.377954 dram_init: ddr_geometry: 2
9127 10:02:25.381308 0:dram_rank_size:100000000
9128 10:02:25.381733 1:dram_rank_size:100000000
9129 10:02:25.387954 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9130 10:02:25.390968 DFS_SHUFFLE_HW_MODE: ON
9131 10:02:25.394501 dramc_set_vcore_voltage set vcore to 725000
9132 10:02:25.397597 Read voltage for 1600, 0
9133 10:02:25.398013 Vio18 = 0
9134 10:02:25.398369 Vcore = 725000
9135 10:02:25.400613 Vdram = 0
9136 10:02:25.401022 Vddq = 0
9137 10:02:25.401350 Vmddr = 0
9138 10:02:25.404405 switch to 3200 Mbps bootup
9139 10:02:25.404822 [DramcRunTimeConfig]
9140 10:02:25.407682 PHYPLL
9141 10:02:25.408128 DPM_CONTROL_AFTERK: ON
9142 10:02:25.411117 PER_BANK_REFRESH: ON
9143 10:02:25.414322 REFRESH_OVERHEAD_REDUCTION: ON
9144 10:02:25.414737 CMD_PICG_NEW_MODE: OFF
9145 10:02:25.417151 XRTWTW_NEW_MODE: ON
9146 10:02:25.417567 XRTRTR_NEW_MODE: ON
9147 10:02:25.420618 TX_TRACKING: ON
9148 10:02:25.421034 RDSEL_TRACKING: OFF
9149 10:02:25.424191 DQS Precalculation for DVFS: ON
9150 10:02:25.427215 RX_TRACKING: OFF
9151 10:02:25.427625 HW_GATING DBG: ON
9152 10:02:25.430403 ZQCS_ENABLE_LP4: ON
9153 10:02:25.430817 RX_PICG_NEW_MODE: ON
9154 10:02:25.433804 TX_PICG_NEW_MODE: ON
9155 10:02:25.436857 ENABLE_RX_DCM_DPHY: ON
9156 10:02:25.440367 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9157 10:02:25.440793 DUMMY_READ_FOR_TRACKING: OFF
9158 10:02:25.443714 !!! SPM_CONTROL_AFTERK: OFF
9159 10:02:25.447107 !!! SPM could not control APHY
9160 10:02:25.450495 IMPEDANCE_TRACKING: ON
9161 10:02:25.450904 TEMP_SENSOR: ON
9162 10:02:25.453598 HW_SAVE_FOR_SR: OFF
9163 10:02:25.454010 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9164 10:02:25.460045 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9165 10:02:25.460459 Read ODT Tracking: ON
9166 10:02:25.463499 Refresh Rate DeBounce: ON
9167 10:02:25.467041 DFS_NO_QUEUE_FLUSH: ON
9168 10:02:25.469653 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9169 10:02:25.470066 ENABLE_DFS_RUNTIME_MRW: OFF
9170 10:02:25.473027 DDR_RESERVE_NEW_MODE: ON
9171 10:02:25.476625 MR_CBT_SWITCH_FREQ: ON
9172 10:02:25.477037 =========================
9173 10:02:25.496365 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9174 10:02:25.499448 dram_init: ddr_geometry: 2
9175 10:02:25.517558 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9176 10:02:25.520983 dram_init: dram init end (result: 0)
9177 10:02:25.527593 DRAM-K: Full calibration passed in 24404 msecs
9178 10:02:25.530947 MRC: failed to locate region type 0.
9179 10:02:25.531371 DRAM rank0 size:0x100000000,
9180 10:02:25.534329 DRAM rank1 size=0x100000000
9181 10:02:25.544120 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9182 10:02:25.551169 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9183 10:02:25.557540 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9184 10:02:25.567485 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9185 10:02:25.568007 DRAM rank0 size:0x100000000,
9186 10:02:25.570622 DRAM rank1 size=0x100000000
9187 10:02:25.571014 CBMEM:
9188 10:02:25.573799 IMD: root @ 0xfffff000 254 entries.
9189 10:02:25.577092 IMD: root @ 0xffffec00 62 entries.
9190 10:02:25.580719 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9191 10:02:25.587743 WARNING: RO_VPD is uninitialized or empty.
9192 10:02:25.590443 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9193 10:02:25.598076 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9194 10:02:25.611223 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9195 10:02:25.622231 BS: romstage times (exec / console): total (unknown) / 23940 ms
9196 10:02:25.622788
9197 10:02:25.623152
9198 10:02:25.631819 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9199 10:02:25.635260 ARM64: Exception handlers installed.
9200 10:02:25.638567 ARM64: Testing exception
9201 10:02:25.641737 ARM64: Done test exception
9202 10:02:25.642185 Enumerating buses...
9203 10:02:25.644796 Show all devs... Before device enumeration.
9204 10:02:25.648418 Root Device: enabled 1
9205 10:02:25.651678 CPU_CLUSTER: 0: enabled 1
9206 10:02:25.652313 CPU: 00: enabled 1
9207 10:02:25.654998 Compare with tree...
9208 10:02:25.655414 Root Device: enabled 1
9209 10:02:25.658197 CPU_CLUSTER: 0: enabled 1
9210 10:02:25.661314 CPU: 00: enabled 1
9211 10:02:25.661730 Root Device scanning...
9212 10:02:25.664489 scan_static_bus for Root Device
9213 10:02:25.668545 CPU_CLUSTER: 0 enabled
9214 10:02:25.671539 scan_static_bus for Root Device done
9215 10:02:25.674610 scan_bus: bus Root Device finished in 8 msecs
9216 10:02:25.675137 done
9217 10:02:25.681654 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9218 10:02:25.684296 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9219 10:02:25.690908 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9220 10:02:25.697879 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9221 10:02:25.698422 Allocating resources...
9222 10:02:25.701460 Reading resources...
9223 10:02:25.704606 Root Device read_resources bus 0 link: 0
9224 10:02:25.707577 DRAM rank0 size:0x100000000,
9225 10:02:25.708176 DRAM rank1 size=0x100000000
9226 10:02:25.714300 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9227 10:02:25.714849 CPU: 00 missing read_resources
9228 10:02:25.720904 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9229 10:02:25.724086 Root Device read_resources bus 0 link: 0 done
9230 10:02:25.727393 Done reading resources.
9231 10:02:25.731030 Show resources in subtree (Root Device)...After reading.
9232 10:02:25.734395 Root Device child on link 0 CPU_CLUSTER: 0
9233 10:02:25.737427 CPU_CLUSTER: 0 child on link 0 CPU: 00
9234 10:02:25.747320 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9235 10:02:25.747798 CPU: 00
9236 10:02:25.753287 Root Device assign_resources, bus 0 link: 0
9237 10:02:25.756646 CPU_CLUSTER: 0 missing set_resources
9238 10:02:25.760107 Root Device assign_resources, bus 0 link: 0 done
9239 10:02:25.763500 Done setting resources.
9240 10:02:25.766644 Show resources in subtree (Root Device)...After assigning values.
9241 10:02:25.769863 Root Device child on link 0 CPU_CLUSTER: 0
9242 10:02:25.776688 CPU_CLUSTER: 0 child on link 0 CPU: 00
9243 10:02:25.783031 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9244 10:02:25.786406 CPU: 00
9245 10:02:25.786835 Done allocating resources.
9246 10:02:25.792912 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9247 10:02:25.793418 Enabling resources...
9248 10:02:25.796677 done.
9249 10:02:25.800189 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9250 10:02:25.803700 Initializing devices...
9251 10:02:25.804274 Root Device init
9252 10:02:25.806737 init hardware done!
9253 10:02:25.807276 0x00000018: ctrlr->caps
9254 10:02:25.809374 52.000 MHz: ctrlr->f_max
9255 10:02:25.813364 0.400 MHz: ctrlr->f_min
9256 10:02:25.816584 0x40ff8080: ctrlr->voltages
9257 10:02:25.817130 sclk: 390625
9258 10:02:25.817576 Bus Width = 1
9259 10:02:25.819890 sclk: 390625
9260 10:02:25.820457 Bus Width = 1
9261 10:02:25.822953 Early init status = 3
9262 10:02:25.826226 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9263 10:02:25.830420 in-header: 03 fc 00 00 01 00 00 00
9264 10:02:25.832892 in-data: 00
9265 10:02:25.836301 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9266 10:02:25.841228 in-header: 03 fd 00 00 00 00 00 00
9267 10:02:25.844939 in-data:
9268 10:02:25.848017 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9269 10:02:25.851867 in-header: 03 fc 00 00 01 00 00 00
9270 10:02:25.855205 in-data: 00
9271 10:02:25.859412 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9272 10:02:25.864169 in-header: 03 fd 00 00 00 00 00 00
9273 10:02:25.867466 in-data:
9274 10:02:25.870505 [SSUSB] Setting up USB HOST controller...
9275 10:02:25.873843 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9276 10:02:25.877369 [SSUSB] phy power-on done.
9277 10:02:25.880134 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9278 10:02:25.887078 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9279 10:02:25.890559 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9280 10:02:25.897140 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9281 10:02:25.903553 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9282 10:02:25.910253 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9283 10:02:25.917033 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9284 10:02:25.923010 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9285 10:02:25.926827 SPM: binary array size = 0x9dc
9286 10:02:25.929852 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9287 10:02:25.936651 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9288 10:02:25.942702 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9289 10:02:25.949765 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9290 10:02:25.952883 configure_display: Starting display init
9291 10:02:25.986826 anx7625_power_on_init: Init interface.
9292 10:02:25.990473 anx7625_disable_pd_protocol: Disabled PD feature.
9293 10:02:25.993364 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9294 10:02:26.021925 anx7625_start_dp_work: Secure OCM version=00
9295 10:02:26.025254 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9296 10:02:26.039689 sp_tx_get_edid_block: EDID Block = 1
9297 10:02:26.142554 Extracted contents:
9298 10:02:26.145655 header: 00 ff ff ff ff ff ff 00
9299 10:02:26.148695 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9300 10:02:26.151929 version: 01 04
9301 10:02:26.155463 basic params: 95 1f 11 78 0a
9302 10:02:26.158864 chroma info: 76 90 94 55 54 90 27 21 50 54
9303 10:02:26.162162 established: 00 00 00
9304 10:02:26.168461 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9305 10:02:26.175440 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9306 10:02:26.178514 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9307 10:02:26.185364 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9308 10:02:26.192157 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9309 10:02:26.194853 extensions: 00
9310 10:02:26.195340 checksum: fb
9311 10:02:26.195671
9312 10:02:26.197953 Manufacturer: IVO Model 57d Serial Number 0
9313 10:02:26.201402 Made week 0 of 2020
9314 10:02:26.204802 EDID version: 1.4
9315 10:02:26.205289 Digital display
9316 10:02:26.208264 6 bits per primary color channel
9317 10:02:26.208694 DisplayPort interface
9318 10:02:26.211117 Maximum image size: 31 cm x 17 cm
9319 10:02:26.214746 Gamma: 220%
9320 10:02:26.215167 Check DPMS levels
9321 10:02:26.221441 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9322 10:02:26.224990 First detailed timing is preferred timing
9323 10:02:26.225506 Established timings supported:
9324 10:02:26.228221 Standard timings supported:
9325 10:02:26.231317 Detailed timings
9326 10:02:26.234411 Hex of detail: 383680a07038204018303c0035ae10000019
9327 10:02:26.240864 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9328 10:02:26.244022 0780 0798 07c8 0820 hborder 0
9329 10:02:26.247121 0438 043b 0447 0458 vborder 0
9330 10:02:26.250917 -hsync -vsync
9331 10:02:26.251489 Did detailed timing
9332 10:02:26.257652 Hex of detail: 000000000000000000000000000000000000
9333 10:02:26.260672 Manufacturer-specified data, tag 0
9334 10:02:26.264498 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9335 10:02:26.267281 ASCII string: InfoVision
9336 10:02:26.270637 Hex of detail: 000000fe00523134304e574635205248200a
9337 10:02:26.273959 ASCII string: R140NWF5 RH
9338 10:02:26.274380 Checksum
9339 10:02:26.277414 Checksum: 0xfb (valid)
9340 10:02:26.280391 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9341 10:02:26.283444 DSI data_rate: 832800000 bps
9342 10:02:26.290397 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9343 10:02:26.293440 anx7625_parse_edid: pixelclock(138800).
9344 10:02:26.296328 hactive(1920), hsync(48), hfp(24), hbp(88)
9345 10:02:26.300099 vactive(1080), vsync(12), vfp(3), vbp(17)
9346 10:02:26.302957 anx7625_dsi_config: config dsi.
9347 10:02:26.310177 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9348 10:02:26.323992 anx7625_dsi_config: success to config DSI
9349 10:02:26.326976 anx7625_dp_start: MIPI phy setup OK.
9350 10:02:26.330368 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9351 10:02:26.333693 mtk_ddp_mode_set invalid vrefresh 60
9352 10:02:26.336973 main_disp_path_setup
9353 10:02:26.337053 ovl_layer_smi_id_en
9354 10:02:26.340288 ovl_layer_smi_id_en
9355 10:02:26.340374 ccorr_config
9356 10:02:26.340440 aal_config
9357 10:02:26.343505 gamma_config
9358 10:02:26.343585 postmask_config
9359 10:02:26.346474 dither_config
9360 10:02:26.350084 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9361 10:02:26.356571 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9362 10:02:26.360246 Root Device init finished in 553 msecs
9363 10:02:26.363192 CPU_CLUSTER: 0 init
9364 10:02:26.369771 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9365 10:02:26.376909 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9366 10:02:26.376988 APU_MBOX 0x190000b0 = 0x10001
9367 10:02:26.379573 APU_MBOX 0x190001b0 = 0x10001
9368 10:02:26.383024 APU_MBOX 0x190005b0 = 0x10001
9369 10:02:26.386383 APU_MBOX 0x190006b0 = 0x10001
9370 10:02:26.392700 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9371 10:02:26.402922 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9372 10:02:26.415182 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9373 10:02:26.421885 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9374 10:02:26.433425 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9375 10:02:26.442991 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9376 10:02:26.446370 CPU_CLUSTER: 0 init finished in 81 msecs
9377 10:02:26.449340 Devices initialized
9378 10:02:26.452259 Show all devs... After init.
9379 10:02:26.452331 Root Device: enabled 1
9380 10:02:26.455405 CPU_CLUSTER: 0: enabled 1
9381 10:02:26.458946 CPU: 00: enabled 1
9382 10:02:26.462281 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9383 10:02:26.465499 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9384 10:02:26.468971 ELOG: NV offset 0x57f000 size 0x1000
9385 10:02:26.475558 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9386 10:02:26.482348 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9387 10:02:26.485415 ELOG: Event(17) added with size 13 at 2023-06-10 10:02:28 UTC
9388 10:02:26.492206 out: cmd=0x121: 03 db 21 01 00 00 00 00
9389 10:02:26.495312 in-header: 03 40 00 00 2c 00 00 00
9390 10:02:26.505314 in-data: 1f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9391 10:02:26.511669 ELOG: Event(A1) added with size 10 at 2023-06-10 10:02:28 UTC
9392 10:02:26.518446 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9393 10:02:26.524819 ELOG: Event(A0) added with size 9 at 2023-06-10 10:02:28 UTC
9394 10:02:26.528172 elog_add_boot_reason: Logged dev mode boot
9395 10:02:26.535304 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9396 10:02:26.535386 Finalize devices...
9397 10:02:26.538226 Devices finalized
9398 10:02:26.541562 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9399 10:02:26.544979 Writing coreboot table at 0xffe64000
9400 10:02:26.548377 0. 000000000010a000-0000000000113fff: RAMSTAGE
9401 10:02:26.555199 1. 0000000040000000-00000000400fffff: RAM
9402 10:02:26.557783 2. 0000000040100000-000000004032afff: RAMSTAGE
9403 10:02:26.561712 3. 000000004032b000-00000000545fffff: RAM
9404 10:02:26.564488 4. 0000000054600000-000000005465ffff: BL31
9405 10:02:26.567678 5. 0000000054660000-00000000ffe63fff: RAM
9406 10:02:26.574535 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9407 10:02:26.577857 7. 0000000100000000-000000023fffffff: RAM
9408 10:02:26.581046 Passing 5 GPIOs to payload:
9409 10:02:26.584165 NAME | PORT | POLARITY | VALUE
9410 10:02:26.590876 EC in RW | 0x000000aa | low | undefined
9411 10:02:26.594233 EC interrupt | 0x00000005 | low | undefined
9412 10:02:26.600912 TPM interrupt | 0x000000ab | high | undefined
9413 10:02:26.604194 SD card detect | 0x00000011 | high | undefined
9414 10:02:26.607204 speaker enable | 0x00000093 | high | undefined
9415 10:02:26.610631 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9416 10:02:26.614333 in-header: 03 f9 00 00 02 00 00 00
9417 10:02:26.617062 in-data: 02 00
9418 10:02:26.620644 ADC[4]: Raw value=902955 ID=7
9419 10:02:26.623666 ADC[3]: Raw value=213916 ID=1
9420 10:02:26.623738 RAM Code: 0x71
9421 10:02:26.627408 ADC[6]: Raw value=74630 ID=0
9422 10:02:26.630373 ADC[5]: Raw value=213546 ID=1
9423 10:02:26.630442 SKU Code: 0x1
9424 10:02:26.636986 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a51a
9425 10:02:26.637074 coreboot table: 964 bytes.
9426 10:02:26.640208 IMD ROOT 0. 0xfffff000 0x00001000
9427 10:02:26.643639 IMD SMALL 1. 0xffffe000 0x00001000
9428 10:02:26.647033 RO MCACHE 2. 0xffffc000 0x00001104
9429 10:02:26.650699 CONSOLE 3. 0xfff7c000 0x00080000
9430 10:02:26.653386 FMAP 4. 0xfff7b000 0x00000452
9431 10:02:26.656973 TIME STAMP 5. 0xfff7a000 0x00000910
9432 10:02:26.660207 VBOOT WORK 6. 0xfff66000 0x00014000
9433 10:02:26.664090 RAMOOPS 7. 0xffe66000 0x00100000
9434 10:02:26.666845 COREBOOT 8. 0xffe64000 0x00002000
9435 10:02:26.670520 IMD small region:
9436 10:02:26.673423 IMD ROOT 0. 0xffffec00 0x00000400
9437 10:02:26.677414 VPD 1. 0xffffeba0 0x0000004c
9438 10:02:26.680447 MMC STATUS 2. 0xffffeb80 0x00000004
9439 10:02:26.686688 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9440 10:02:26.687247 Probing TPM: done!
9441 10:02:26.693279 Connected to device vid:did:rid of 1ae0:0028:00
9442 10:02:26.699812 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9443 10:02:26.703628 Initialized TPM device CR50 revision 0
9444 10:02:26.706886 Checking cr50 for pending updates
9445 10:02:26.712495 Reading cr50 TPM mode
9446 10:02:26.722209 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9447 10:02:26.728000 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9448 10:02:26.768069 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9449 10:02:26.771544 Checking segment from ROM address 0x40100000
9450 10:02:26.774874 Checking segment from ROM address 0x4010001c
9451 10:02:26.781672 Loading segment from ROM address 0x40100000
9452 10:02:26.782258 code (compression=0)
9453 10:02:26.791634 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9454 10:02:26.798260 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9455 10:02:26.798810 it's not compressed!
9456 10:02:26.804521 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9457 10:02:26.811222 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9458 10:02:26.828248 Loading segment from ROM address 0x4010001c
9459 10:02:26.828802 Entry Point 0x80000000
9460 10:02:26.832128 Loaded segments
9461 10:02:26.834885 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9462 10:02:26.841479 Jumping to boot code at 0x80000000(0xffe64000)
9463 10:02:26.848417 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9464 10:02:26.854341 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9465 10:02:26.862949 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9466 10:02:26.866611 Checking segment from ROM address 0x40100000
9467 10:02:26.869482 Checking segment from ROM address 0x4010001c
9468 10:02:26.876097 Loading segment from ROM address 0x40100000
9469 10:02:26.876515 code (compression=1)
9470 10:02:26.882504 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9471 10:02:26.892664 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9472 10:02:26.893095 using LZMA
9473 10:02:26.901201 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9474 10:02:26.908072 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9475 10:02:26.911128 Loading segment from ROM address 0x4010001c
9476 10:02:26.911693 Entry Point 0x54601000
9477 10:02:26.914582 Loaded segments
9478 10:02:26.917664 NOTICE: MT8192 bl31_setup
9479 10:02:26.925091 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9480 10:02:26.928306 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9481 10:02:26.931930 WARNING: region 0:
9482 10:02:26.934774 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 10:02:26.935245 WARNING: region 1:
9484 10:02:26.942017 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9485 10:02:26.944881 WARNING: region 2:
9486 10:02:26.947905 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9487 10:02:26.951268 WARNING: region 3:
9488 10:02:26.954509 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9489 10:02:26.958218 WARNING: region 4:
9490 10:02:26.964668 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9491 10:02:26.965180 WARNING: region 5:
9492 10:02:26.968135 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 10:02:26.971506 WARNING: region 6:
9494 10:02:26.974700 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 10:02:26.978330 WARNING: region 7:
9496 10:02:26.981219 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 10:02:26.988293 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9498 10:02:26.991441 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9499 10:02:26.994601 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9500 10:02:27.001058 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9501 10:02:27.004850 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9502 10:02:27.008150 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9503 10:02:27.014695 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9504 10:02:27.018135 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9505 10:02:27.024533 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9506 10:02:27.028181 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9507 10:02:27.031615 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9508 10:02:27.038067 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9509 10:02:27.040945 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9510 10:02:27.044462 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9511 10:02:27.050982 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9512 10:02:27.054060 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9513 10:02:27.060678 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9514 10:02:27.064310 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9515 10:02:27.067719 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9516 10:02:27.074136 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9517 10:02:27.077353 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9518 10:02:27.084622 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9519 10:02:27.087290 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9520 10:02:27.090687 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9521 10:02:27.097150 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9522 10:02:27.100998 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9523 10:02:27.107304 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9524 10:02:27.110671 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9525 10:02:27.114126 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9526 10:02:27.120710 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9527 10:02:27.124181 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9528 10:02:27.131043 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9529 10:02:27.133802 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9530 10:02:27.137188 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9531 10:02:27.140278 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9532 10:02:27.146923 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9533 10:02:27.150314 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9534 10:02:27.153781 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9535 10:02:27.157070 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9536 10:02:27.163550 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9537 10:02:27.167247 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9538 10:02:27.170623 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9539 10:02:27.173644 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9540 10:02:27.180479 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9541 10:02:27.183533 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9542 10:02:27.187049 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9543 10:02:27.189931 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9544 10:02:27.196626 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9545 10:02:27.200612 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9546 10:02:27.206500 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9547 10:02:27.210290 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9548 10:02:27.213701 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9549 10:02:27.220131 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9550 10:02:27.223159 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9551 10:02:27.229721 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9552 10:02:27.233341 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9553 10:02:27.239948 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9554 10:02:27.242913 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9555 10:02:27.246551 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9556 10:02:27.252884 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9557 10:02:27.256013 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9558 10:02:27.263801 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9559 10:02:27.266184 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9560 10:02:27.273226 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9561 10:02:27.275857 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9562 10:02:27.283200 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9563 10:02:27.286064 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9564 10:02:27.289326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9565 10:02:27.295776 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9566 10:02:27.299873 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9567 10:02:27.305981 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9568 10:02:27.309655 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9569 10:02:27.315844 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9570 10:02:27.319084 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9571 10:02:27.326416 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9572 10:02:27.329712 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9573 10:02:27.332450 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9574 10:02:27.339050 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9575 10:02:27.342670 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9576 10:02:27.349328 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9577 10:02:27.352450 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9578 10:02:27.359493 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9579 10:02:27.362798 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9580 10:02:27.366656 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9581 10:02:27.372317 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9582 10:02:27.375853 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9583 10:02:27.382363 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9584 10:02:27.385929 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9585 10:02:27.392754 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9586 10:02:27.396202 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9587 10:02:27.399380 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9588 10:02:27.406113 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9589 10:02:27.409619 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9590 10:02:27.415979 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9591 10:02:27.419741 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9592 10:02:27.425833 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9593 10:02:27.429504 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9594 10:02:27.433075 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9595 10:02:27.435671 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9596 10:02:27.443088 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9597 10:02:27.446789 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9598 10:02:27.449366 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9599 10:02:27.455723 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9600 10:02:27.459535 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9601 10:02:27.465941 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9602 10:02:27.469444 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9603 10:02:27.472922 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9604 10:02:27.479223 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9605 10:02:27.482694 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9606 10:02:27.488942 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9607 10:02:27.492157 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9608 10:02:27.496105 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9609 10:02:27.502755 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9610 10:02:27.505977 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9611 10:02:27.512483 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9612 10:02:27.516121 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9613 10:02:27.519100 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9614 10:02:27.522226 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9615 10:02:27.528754 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9616 10:02:27.532353 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9617 10:02:27.535587 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9618 10:02:27.542021 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9619 10:02:27.545598 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9620 10:02:27.549069 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9621 10:02:27.552227 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9622 10:02:27.558607 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9623 10:02:27.562693 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9624 10:02:27.569358 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9625 10:02:27.571895 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9626 10:02:27.575551 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9627 10:02:27.581770 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9628 10:02:27.585432 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9629 10:02:27.591842 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9630 10:02:27.595860 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9631 10:02:27.598496 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9632 10:02:27.604873 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9633 10:02:27.608477 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9634 10:02:27.615013 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9635 10:02:27.618705 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9636 10:02:27.621738 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9637 10:02:27.628634 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9638 10:02:27.632470 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9639 10:02:27.638411 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9640 10:02:27.641988 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9641 10:02:27.645035 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9642 10:02:27.652315 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9643 10:02:27.656160 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9644 10:02:27.658726 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9645 10:02:27.665123 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9646 10:02:27.668379 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9647 10:02:27.675772 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9648 10:02:27.679060 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9649 10:02:27.681769 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9650 10:02:27.688438 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9651 10:02:27.691518 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9652 10:02:27.698431 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9653 10:02:27.701667 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9654 10:02:27.704993 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9655 10:02:27.711259 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9656 10:02:27.714713 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9657 10:02:27.721163 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9658 10:02:27.724794 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9659 10:02:27.728384 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9660 10:02:27.734805 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9661 10:02:27.738153 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9662 10:02:27.744592 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9663 10:02:27.747902 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9664 10:02:27.750740 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9665 10:02:27.758561 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9666 10:02:27.760674 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9667 10:02:27.768013 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9668 10:02:27.771233 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9669 10:02:27.774265 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9670 10:02:27.780964 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9671 10:02:27.783943 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9672 10:02:27.790171 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9673 10:02:27.793737 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9674 10:02:27.796853 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9675 10:02:27.804080 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9676 10:02:27.807321 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9677 10:02:27.813920 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9678 10:02:27.817517 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9679 10:02:27.820350 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9680 10:02:27.826828 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9681 10:02:27.830283 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9682 10:02:27.836674 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9683 10:02:27.840173 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9684 10:02:27.843823 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9685 10:02:27.850542 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9686 10:02:27.853732 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9687 10:02:27.860193 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9688 10:02:27.863497 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9689 10:02:27.870112 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9690 10:02:27.873437 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9691 10:02:27.876881 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9692 10:02:27.883112 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9693 10:02:27.886746 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9694 10:02:27.893214 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9695 10:02:27.896396 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9696 10:02:27.899800 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9697 10:02:27.906215 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9698 10:02:27.910075 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9699 10:02:27.916197 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9700 10:02:27.919394 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9701 10:02:27.926067 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9702 10:02:27.929428 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9703 10:02:27.932406 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9704 10:02:27.939198 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9705 10:02:27.942620 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9706 10:02:27.948945 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9707 10:02:27.952144 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9708 10:02:27.959197 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9709 10:02:27.962454 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9710 10:02:27.965751 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9711 10:02:27.971886 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9712 10:02:27.975164 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9713 10:02:27.982594 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9714 10:02:27.985316 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9715 10:02:27.992191 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9716 10:02:27.994937 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9717 10:02:27.998567 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9718 10:02:28.004578 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9719 10:02:28.008724 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9720 10:02:28.015434 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9721 10:02:28.017895 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9722 10:02:28.024962 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9723 10:02:28.028062 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9724 10:02:28.031424 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9725 10:02:28.037960 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9726 10:02:28.041224 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9727 10:02:28.044113 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9728 10:02:28.051056 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9729 10:02:28.054013 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9730 10:02:28.057531 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9731 10:02:28.060674 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9732 10:02:28.067674 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9733 10:02:28.070924 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9734 10:02:28.077932 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9735 10:02:28.080428 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9736 10:02:28.084203 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9737 10:02:28.090358 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9738 10:02:28.094378 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9739 10:02:28.097076 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9740 10:02:28.104102 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9741 10:02:28.107180 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9742 10:02:28.113672 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9743 10:02:28.117040 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9744 10:02:28.120214 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9745 10:02:28.126873 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9746 10:02:28.130552 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9747 10:02:28.133387 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9748 10:02:28.140171 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9749 10:02:28.143771 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9750 10:02:28.146344 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9751 10:02:28.153688 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9752 10:02:28.156207 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9753 10:02:28.163056 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9754 10:02:28.166439 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9755 10:02:28.169559 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9756 10:02:28.175674 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9757 10:02:28.179440 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9758 10:02:28.186052 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9759 10:02:28.189436 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9760 10:02:28.192905 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9761 10:02:28.198851 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9762 10:02:28.202596 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9763 10:02:28.209344 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9764 10:02:28.212206 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9765 10:02:28.215542 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9766 10:02:28.218731 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9767 10:02:28.225187 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9768 10:02:28.228966 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9769 10:02:28.232454 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9770 10:02:28.235144 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9771 10:02:28.242028 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9772 10:02:28.245354 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9773 10:02:28.248515 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9774 10:02:28.251414 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9775 10:02:28.258342 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9776 10:02:28.261248 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9777 10:02:28.264690 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9778 10:02:28.271719 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9779 10:02:28.274761 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9780 10:02:28.278259 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9781 10:02:28.284774 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9782 10:02:28.288978 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9783 10:02:28.294496 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9784 10:02:28.297897 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9785 10:02:28.304145 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9786 10:02:28.307796 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9787 10:02:28.310933 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9788 10:02:28.317669 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9789 10:02:28.320824 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9790 10:02:28.327697 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9791 10:02:28.331010 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9792 10:02:28.337260 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9793 10:02:28.340536 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9794 10:02:28.344186 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9795 10:02:28.350539 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9796 10:02:28.354865 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9797 10:02:28.360216 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9798 10:02:28.363473 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9799 10:02:28.367282 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9800 10:02:28.373498 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9801 10:02:28.376633 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9802 10:02:28.383468 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9803 10:02:28.386790 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9804 10:02:28.392908 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9805 10:02:28.396486 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9806 10:02:28.399854 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9807 10:02:28.406238 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9808 10:02:28.410264 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9809 10:02:28.416325 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9810 10:02:28.419804 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9811 10:02:28.422742 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9812 10:02:28.429969 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9813 10:02:28.432953 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9814 10:02:28.439532 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9815 10:02:28.442408 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9816 10:02:28.449605 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9817 10:02:28.452977 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9818 10:02:28.455976 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9819 10:02:28.462478 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9820 10:02:28.466523 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9821 10:02:28.472563 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9822 10:02:28.475445 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9823 10:02:28.482072 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9824 10:02:28.485326 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9825 10:02:28.488641 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9826 10:02:28.495174 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9827 10:02:28.498299 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9828 10:02:28.505656 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9829 10:02:28.508451 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9830 10:02:28.512121 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9831 10:02:28.518300 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9832 10:02:28.521351 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9833 10:02:28.527924 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9834 10:02:28.531479 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9835 10:02:28.537982 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9836 10:02:28.541244 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9837 10:02:28.544467 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9838 10:02:28.550926 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9839 10:02:28.554630 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9840 10:02:28.561252 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9841 10:02:28.564252 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9842 10:02:28.567108 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9843 10:02:28.574291 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9844 10:02:28.577380 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9845 10:02:28.584420 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9846 10:02:28.587409 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9847 10:02:28.593878 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9848 10:02:28.597209 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9849 10:02:28.603848 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9850 10:02:28.606881 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9851 10:02:28.610496 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9852 10:02:28.617230 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9853 10:02:28.620320 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9854 10:02:28.627003 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9855 10:02:28.630068 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9856 10:02:28.636707 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9857 10:02:28.639725 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9858 10:02:28.643537 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9859 10:02:28.649830 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9860 10:02:28.653067 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9861 10:02:28.659441 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9862 10:02:28.662747 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9863 10:02:28.669483 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9864 10:02:28.673172 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9865 10:02:28.679487 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9866 10:02:28.682592 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9867 10:02:28.685734 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9868 10:02:28.692822 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9869 10:02:28.695928 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9870 10:02:28.702342 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9871 10:02:28.705853 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9872 10:02:28.712447 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9873 10:02:28.715891 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9874 10:02:28.722299 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9875 10:02:28.725330 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9876 10:02:28.729016 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9877 10:02:28.736015 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9878 10:02:28.738542 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9879 10:02:28.745345 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9880 10:02:28.749106 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9881 10:02:28.755431 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9882 10:02:28.758507 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9883 10:02:28.764920 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9884 10:02:28.768457 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9885 10:02:28.771614 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9886 10:02:28.778189 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9887 10:02:28.781529 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9888 10:02:28.788309 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9889 10:02:28.791661 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9890 10:02:28.797934 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9891 10:02:28.801159 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9892 10:02:28.807823 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9893 10:02:28.811071 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9894 10:02:28.814584 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9895 10:02:28.820940 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9896 10:02:28.823953 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9897 10:02:28.830750 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9898 10:02:28.833940 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9899 10:02:28.840215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9900 10:02:28.843844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9901 10:02:28.850995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9902 10:02:28.853788 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9903 10:02:28.860461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9904 10:02:28.863588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9905 10:02:28.870127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9906 10:02:28.873999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9907 10:02:28.880197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9908 10:02:28.883767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9909 10:02:28.886554 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9910 10:02:28.893278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9911 10:02:28.896514 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9912 10:02:28.903238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9913 10:02:28.906685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9914 10:02:28.912969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9915 10:02:28.916519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9916 10:02:28.923007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9917 10:02:28.926229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9918 10:02:28.933118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9919 10:02:28.935967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9920 10:02:28.943678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9921 10:02:28.946854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9922 10:02:28.953116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9923 10:02:28.955867 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9924 10:02:28.962818 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9925 10:02:28.966371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9926 10:02:28.972662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9927 10:02:28.979355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9928 10:02:28.982207 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9929 10:02:28.988851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9930 10:02:28.992067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9931 10:02:28.996246 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9932 10:02:28.999116 INFO: [APUAPC] vio 0
9933 10:02:29.002508 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9934 10:02:29.009057 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9935 10:02:29.012064 INFO: [APUAPC] D0_APC_0: 0x400510
9936 10:02:29.015656 INFO: [APUAPC] D0_APC_1: 0x0
9937 10:02:29.018622 INFO: [APUAPC] D0_APC_2: 0x1540
9938 10:02:29.019034 INFO: [APUAPC] D0_APC_3: 0x0
9939 10:02:29.025125 INFO: [APUAPC] D1_APC_0: 0xffffffff
9940 10:02:29.029116 INFO: [APUAPC] D1_APC_1: 0xffffffff
9941 10:02:29.031993 INFO: [APUAPC] D1_APC_2: 0x3fffff
9942 10:02:29.032485 INFO: [APUAPC] D1_APC_3: 0x0
9943 10:02:29.035293 INFO: [APUAPC] D2_APC_0: 0xffffffff
9944 10:02:29.042105 INFO: [APUAPC] D2_APC_1: 0xffffffff
9945 10:02:29.044934 INFO: [APUAPC] D2_APC_2: 0x3fffff
9946 10:02:29.045419 INFO: [APUAPC] D2_APC_3: 0x0
9947 10:02:29.048162 INFO: [APUAPC] D3_APC_0: 0xffffffff
9948 10:02:29.051789 INFO: [APUAPC] D3_APC_1: 0xffffffff
9949 10:02:29.054811 INFO: [APUAPC] D3_APC_2: 0x3fffff
9950 10:02:29.058849 INFO: [APUAPC] D3_APC_3: 0x0
9951 10:02:29.061655 INFO: [APUAPC] D4_APC_0: 0xffffffff
9952 10:02:29.064662 INFO: [APUAPC] D4_APC_1: 0xffffffff
9953 10:02:29.068022 INFO: [APUAPC] D4_APC_2: 0x3fffff
9954 10:02:29.071692 INFO: [APUAPC] D4_APC_3: 0x0
9955 10:02:29.074774 INFO: [APUAPC] D5_APC_0: 0xffffffff
9956 10:02:29.077958 INFO: [APUAPC] D5_APC_1: 0xffffffff
9957 10:02:29.081464 INFO: [APUAPC] D5_APC_2: 0x3fffff
9958 10:02:29.084640 INFO: [APUAPC] D5_APC_3: 0x0
9959 10:02:29.087931 INFO: [APUAPC] D6_APC_0: 0xffffffff
9960 10:02:29.091696 INFO: [APUAPC] D6_APC_1: 0xffffffff
9961 10:02:29.094780 INFO: [APUAPC] D6_APC_2: 0x3fffff
9962 10:02:29.097976 INFO: [APUAPC] D6_APC_3: 0x0
9963 10:02:29.101336 INFO: [APUAPC] D7_APC_0: 0xffffffff
9964 10:02:29.104160 INFO: [APUAPC] D7_APC_1: 0xffffffff
9965 10:02:29.107743 INFO: [APUAPC] D7_APC_2: 0x3fffff
9966 10:02:29.111410 INFO: [APUAPC] D7_APC_3: 0x0
9967 10:02:29.114477 INFO: [APUAPC] D8_APC_0: 0xffffffff
9968 10:02:29.117670 INFO: [APUAPC] D8_APC_1: 0xffffffff
9969 10:02:29.121168 INFO: [APUAPC] D8_APC_2: 0x3fffff
9970 10:02:29.124390 INFO: [APUAPC] D8_APC_3: 0x0
9971 10:02:29.128128 INFO: [APUAPC] D9_APC_0: 0xffffffff
9972 10:02:29.130974 INFO: [APUAPC] D9_APC_1: 0xffffffff
9973 10:02:29.134475 INFO: [APUAPC] D9_APC_2: 0x3fffff
9974 10:02:29.137347 INFO: [APUAPC] D9_APC_3: 0x0
9975 10:02:29.141074 INFO: [APUAPC] D10_APC_0: 0xffffffff
9976 10:02:29.144159 INFO: [APUAPC] D10_APC_1: 0xffffffff
9977 10:02:29.147441 INFO: [APUAPC] D10_APC_2: 0x3fffff
9978 10:02:29.150794 INFO: [APUAPC] D10_APC_3: 0x0
9979 10:02:29.154143 INFO: [APUAPC] D11_APC_0: 0xffffffff
9980 10:02:29.157620 INFO: [APUAPC] D11_APC_1: 0xffffffff
9981 10:02:29.160475 INFO: [APUAPC] D11_APC_2: 0x3fffff
9982 10:02:29.163901 INFO: [APUAPC] D11_APC_3: 0x0
9983 10:02:29.167129 INFO: [APUAPC] D12_APC_0: 0xffffffff
9984 10:02:29.170224 INFO: [APUAPC] D12_APC_1: 0xffffffff
9985 10:02:29.173954 INFO: [APUAPC] D12_APC_2: 0x3fffff
9986 10:02:29.176940 INFO: [APUAPC] D12_APC_3: 0x0
9987 10:02:29.180532 INFO: [APUAPC] D13_APC_0: 0xffffffff
9988 10:02:29.184153 INFO: [APUAPC] D13_APC_1: 0xffffffff
9989 10:02:29.187028 INFO: [APUAPC] D13_APC_2: 0x3fffff
9990 10:02:29.190086 INFO: [APUAPC] D13_APC_3: 0x0
9991 10:02:29.193998 INFO: [APUAPC] D14_APC_0: 0xffffffff
9992 10:02:29.196737 INFO: [APUAPC] D14_APC_1: 0xffffffff
9993 10:02:29.200374 INFO: [APUAPC] D14_APC_2: 0x3fffff
9994 10:02:29.203720 INFO: [APUAPC] D14_APC_3: 0x0
9995 10:02:29.207109 INFO: [APUAPC] D15_APC_0: 0xffffffff
9996 10:02:29.209857 INFO: [APUAPC] D15_APC_1: 0xffffffff
9997 10:02:29.213193 INFO: [APUAPC] D15_APC_2: 0x3fffff
9998 10:02:29.216607 INFO: [APUAPC] D15_APC_3: 0x0
9999 10:02:29.220345 INFO: [APUAPC] APC_CON: 0x4
10000 10:02:29.222918 INFO: [NOCDAPC] D0_APC_0: 0x0
10001 10:02:29.226373 INFO: [NOCDAPC] D0_APC_1: 0x0
10002 10:02:29.229439 INFO: [NOCDAPC] D1_APC_0: 0x0
10003 10:02:29.233132 INFO: [NOCDAPC] D1_APC_1: 0xfff
10004 10:02:29.236489 INFO: [NOCDAPC] D2_APC_0: 0x0
10005 10:02:29.239930 INFO: [NOCDAPC] D2_APC_1: 0xfff
10006 10:02:29.240400 INFO: [NOCDAPC] D3_APC_0: 0x0
10007 10:02:29.243411 INFO: [NOCDAPC] D3_APC_1: 0xfff
10008 10:02:29.246374 INFO: [NOCDAPC] D4_APC_0: 0x0
10009 10:02:29.249660 INFO: [NOCDAPC] D4_APC_1: 0xfff
10010 10:02:29.252580 INFO: [NOCDAPC] D5_APC_0: 0x0
10011 10:02:29.255878 INFO: [NOCDAPC] D5_APC_1: 0xfff
10012 10:02:29.259821 INFO: [NOCDAPC] D6_APC_0: 0x0
10013 10:02:29.263359 INFO: [NOCDAPC] D6_APC_1: 0xfff
10014 10:02:29.266107 INFO: [NOCDAPC] D7_APC_0: 0x0
10015 10:02:29.269736 INFO: [NOCDAPC] D7_APC_1: 0xfff
10016 10:02:29.272144 INFO: [NOCDAPC] D8_APC_0: 0x0
10017 10:02:29.275775 INFO: [NOCDAPC] D8_APC_1: 0xfff
10018 10:02:29.275856 INFO: [NOCDAPC] D9_APC_0: 0x0
10019 10:02:29.278931 INFO: [NOCDAPC] D9_APC_1: 0xfff
10020 10:02:29.282295 INFO: [NOCDAPC] D10_APC_0: 0x0
10021 10:02:29.285537 INFO: [NOCDAPC] D10_APC_1: 0xfff
10022 10:02:29.288989 INFO: [NOCDAPC] D11_APC_0: 0x0
10023 10:02:29.292189 INFO: [NOCDAPC] D11_APC_1: 0xfff
10024 10:02:29.296190 INFO: [NOCDAPC] D12_APC_0: 0x0
10025 10:02:29.298604 INFO: [NOCDAPC] D12_APC_1: 0xfff
10026 10:02:29.301706 INFO: [NOCDAPC] D13_APC_0: 0x0
10027 10:02:29.305060 INFO: [NOCDAPC] D13_APC_1: 0xfff
10028 10:02:29.308327 INFO: [NOCDAPC] D14_APC_0: 0x0
10029 10:02:29.312055 INFO: [NOCDAPC] D14_APC_1: 0xfff
10030 10:02:29.314842 INFO: [NOCDAPC] D15_APC_0: 0x0
10031 10:02:29.318368 INFO: [NOCDAPC] D15_APC_1: 0xfff
10032 10:02:29.321571 INFO: [NOCDAPC] APC_CON: 0x4
10033 10:02:29.324740 INFO: [APUAPC] set_apusys_apc done
10034 10:02:29.328141 INFO: [DEVAPC] devapc_init done
10035 10:02:29.331790 INFO: GICv3 without legacy support detected.
10036 10:02:29.335077 INFO: ARM GICv3 driver initialized in EL3
10037 10:02:29.338761 INFO: Maximum SPI INTID supported: 639
10038 10:02:29.341363 INFO: BL31: Initializing runtime services
10039 10:02:29.348015 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10040 10:02:29.351385 INFO: SPM: enable CPC mode
10041 10:02:29.357702 INFO: mcdi ready for mcusys-off-idle and system suspend
10042 10:02:29.361413 INFO: BL31: Preparing for EL3 exit to normal world
10043 10:02:29.364915 INFO: Entry point address = 0x80000000
10044 10:02:29.368149 INFO: SPSR = 0x8
10045 10:02:29.372386
10046 10:02:29.372800
10047 10:02:29.373130
10048 10:02:29.375916 Starting depthcharge on Spherion...
10049 10:02:29.376389
10050 10:02:29.376748 Wipe memory regions:
10051 10:02:29.377108
10052 10:02:29.379486 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10053 10:02:29.380050 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10054 10:02:29.380526 Setting prompt string to ['asurada:']
10055 10:02:29.380945 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10056 10:02:29.381681 [0x00000040000000, 0x00000054600000)
10057 10:02:29.501643
10058 10:02:29.502196 [0x00000054660000, 0x00000080000000)
10059 10:02:29.762241
10060 10:02:29.762730 [0x000000821a7280, 0x000000ffe64000)
10061 10:02:30.506411
10062 10:02:30.506564 [0x00000100000000, 0x00000240000000)
10063 10:02:32.396736
10064 10:02:32.399968 Initializing XHCI USB controller at 0x11200000.
10065 10:02:33.439862
10066 10:02:33.442632 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10067 10:02:33.442714
10068 10:02:33.442777
10069 10:02:33.442836
10070 10:02:33.443115 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10072 10:02:33.543609 asurada: tftpboot 192.168.201.1 10670666/tftp-deploy-xbw76tuq/kernel/image.itb 10670666/tftp-deploy-xbw76tuq/kernel/cmdline
10073 10:02:33.543835 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10074 10:02:33.543972 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10075 10:02:33.548372 tftpboot 192.168.201.1 10670666/tftp-deploy-xbw76tuq/kernel/image.ittp-deploy-xbw76tuq/kernel/cmdline
10076 10:02:33.548478
10077 10:02:33.548544 Waiting for link
10078 10:02:33.707214
10079 10:02:33.707764 R8152: Initializing
10080 10:02:33.708221
10081 10:02:33.710211 Version 6 (ocp_data = 5c30)
10082 10:02:33.710632
10083 10:02:33.713402 R8152: Done initializing
10084 10:02:33.713818
10085 10:02:33.714144 Adding net device
10086 10:02:35.806650
10087 10:02:35.807015 done.
10088 10:02:35.807384
10089 10:02:35.807644 MAC: 00:24:32:30:7c:7b
10090 10:02:35.807863
10091 10:02:35.809809 Sending DHCP discover... done.
10092 10:02:35.810103
10093 10:02:39.264211 Waiting for reply... done.
10094 10:02:39.264695
10095 10:02:39.265027 Sending DHCP request... done.
10096 10:02:39.267389
10097 10:02:39.267798 Waiting for reply... done.
10098 10:02:39.268162
10099 10:02:39.270386 My ip is 192.168.201.14
10100 10:02:39.270792
10101 10:02:39.273579 The DHCP server ip is 192.168.201.1
10102 10:02:39.274074
10103 10:02:39.277197 TFTP server IP predefined by user: 192.168.201.1
10104 10:02:39.277607
10105 10:02:39.283776 Bootfile predefined by user: 10670666/tftp-deploy-xbw76tuq/kernel/image.itb
10106 10:02:39.284214
10107 10:02:39.286963 Sending tftp read request... done.
10108 10:02:39.287369
10109 10:02:39.295553 Waiting for the transfer...
10110 10:02:39.295966
10111 10:02:39.951754 00000000 ################################################################
10112 10:02:39.952271
10113 10:02:40.591315 00080000 ################################################################
10114 10:02:40.591452
10115 10:02:41.149506 00100000 ################################################################
10116 10:02:41.149661
10117 10:02:41.710295 00180000 ################################################################
10118 10:02:41.710448
10119 10:02:42.315756 00200000 ################################################################
10120 10:02:42.315897
10121 10:02:42.863231 00280000 ################################################################
10122 10:02:42.863364
10123 10:02:43.419637 00300000 ################################################################
10124 10:02:43.419772
10125 10:02:43.972720 00380000 ################################################################
10126 10:02:43.972870
10127 10:02:44.523443 00400000 ################################################################
10128 10:02:44.523596
10129 10:02:45.095675 00480000 ################################################################
10130 10:02:45.095814
10131 10:02:45.710169 00500000 ################################################################
10132 10:02:45.710666
10133 10:02:46.314959 00580000 ################################################################
10134 10:02:46.315416
10135 10:02:46.997322 00600000 ################################################################
10136 10:02:46.997864
10137 10:02:47.652617 00680000 ################################################################
10138 10:02:47.653169
10139 10:02:48.316857 00700000 ################################################################
10140 10:02:48.316989
10141 10:02:48.971645 00780000 ################################################################
10142 10:02:48.972226
10143 10:02:49.682724 00800000 ################################################################
10144 10:02:49.683275
10145 10:02:50.300308 00880000 ################################################################
10146 10:02:50.300441
10147 10:02:50.862304 00900000 ################################################################
10148 10:02:50.862452
10149 10:02:51.400320 00980000 ################################################################
10150 10:02:51.400470
10151 10:02:51.989455 00a00000 ################################################################
10152 10:02:51.989615
10153 10:02:52.563427 00a80000 ################################################################
10154 10:02:52.563598
10155 10:02:53.178521 00b00000 ################################################################
10156 10:02:53.178669
10157 10:02:53.738715 00b80000 ################################################################
10158 10:02:53.738865
10159 10:02:54.292794 00c00000 ################################################################
10160 10:02:54.292943
10161 10:02:54.857740 00c80000 ################################################################
10162 10:02:54.857891
10163 10:02:55.448253 00d00000 ################################################################
10164 10:02:55.448404
10165 10:02:56.026734 00d80000 ################################################################
10166 10:02:56.026879
10167 10:02:56.619125 00e00000 ################################################################
10168 10:02:56.619668
10169 10:02:57.220925 00e80000 ################################################################
10170 10:02:57.221059
10171 10:02:57.817421 00f00000 ################################################################
10172 10:02:57.817555
10173 10:02:58.475744 00f80000 ################################################################
10174 10:02:58.476291
10175 10:02:59.157079 01000000 ################################################################
10176 10:02:59.157615
10177 10:02:59.876986 01080000 ################################################################
10178 10:02:59.877568
10179 10:03:00.564714 01100000 ################################################################
10180 10:03:00.565240
10181 10:03:01.246775 01180000 ################################################################
10182 10:03:01.247285
10183 10:03:01.953573 01200000 ################################################################
10184 10:03:01.954098
10185 10:03:02.656792 01280000 ################################################################
10186 10:03:02.657333
10187 10:03:03.379862 01300000 ################################################################
10188 10:03:03.380422
10189 10:03:04.103824 01380000 ################################################################
10190 10:03:04.104373
10191 10:03:04.835035 01400000 ################################################################
10192 10:03:04.835578
10193 10:03:05.565358 01480000 ################################################################
10194 10:03:05.565892
10195 10:03:06.300026 01500000 ################################################################
10196 10:03:06.300598
10197 10:03:06.982792 01580000 ################################################################
10198 10:03:06.982949
10199 10:03:07.597021 01600000 ################################################################
10200 10:03:07.597563
10201 10:03:08.180703 01680000 ################################################################
10202 10:03:08.180836
10203 10:03:08.778844 01700000 ################################################################
10204 10:03:08.778983
10205 10:03:09.338013 01780000 ################################################################
10206 10:03:09.338143
10207 10:03:09.925344 01800000 ################################################################
10208 10:03:09.925480
10209 10:03:10.545023 01880000 ################################################################
10210 10:03:10.545529
10211 10:03:11.227678 01900000 ################################################################
10212 10:03:11.228263
10213 10:03:11.856293 01980000 ################################################################
10214 10:03:11.856445
10215 10:03:12.432347 01a00000 ############################################################### done.
10216 10:03:12.432492
10217 10:03:12.436481 The bootfile was 27773886 bytes long.
10218 10:03:12.436575
10219 10:03:12.436660 Sending tftp read request... done.
10220 10:03:12.438713
10221 10:03:12.438796 Waiting for the transfer...
10222 10:03:12.438879
10223 10:03:12.442170 00000000 # done.
10224 10:03:12.442255
10225 10:03:12.448703 Command line loaded dynamically from TFTP file: 10670666/tftp-deploy-xbw76tuq/kernel/cmdline
10226 10:03:12.448791
10227 10:03:12.468442 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10670666/extract-nfsrootfs-8_8v8c5l,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10228 10:03:12.468541
10229 10:03:12.472134 Loading FIT.
10230 10:03:12.472218
10231 10:03:12.474885 Image ramdisk-1 has 17637611 bytes.
10232 10:03:12.474967
10233 10:03:12.475049 Image fdt-1 has 46924 bytes.
10234 10:03:12.475127
10235 10:03:12.478578 Image kernel-1 has 10087317 bytes.
10236 10:03:12.478676
10237 10:03:12.487978 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10238 10:03:12.488071
10239 10:03:12.505015 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10240 10:03:12.505115
10241 10:03:12.511231 Choosing best match conf-1 for compat google,spherion-rev2.
10242 10:03:12.515538
10243 10:03:12.519746 Connected to device vid:did:rid of 1ae0:0028:00
10244 10:03:12.527986
10245 10:03:12.530994 tpm_get_response: command 0x17b, return code 0x0
10246 10:03:12.531078
10247 10:03:12.534347 ec_init: CrosEC protocol v3 supported (256, 248)
10248 10:03:12.540058
10249 10:03:12.541764 tpm_cleanup: add release locality here.
10250 10:03:12.541858
10251 10:03:12.541940 Shutting down all USB controllers.
10252 10:03:12.544945
10253 10:03:12.545028 Removing current net device
10254 10:03:12.545112
10255 10:03:12.551557 Exiting depthcharge with code 4 at timestamp: 72404525
10256 10:03:12.551641
10257 10:03:12.555197 LZMA decompressing kernel-1 to 0x821a6718
10258 10:03:12.555281
10259 10:03:12.558265 LZMA decompressing kernel-1 to 0x40000000
10260 10:03:13.825669
10261 10:03:13.825809 jumping to kernel
10262 10:03:13.826230 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10263 10:03:13.826337 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10264 10:03:13.826420 Setting prompt string to ['Linux version [0-9]']
10265 10:03:13.826503 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10266 10:03:13.826581 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10267 10:03:13.907839
10268 10:03:13.910876 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10269 10:03:13.914211 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10270 10:03:13.914308 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10271 10:03:13.914406 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10272 10:03:13.914493 Using line separator: #'\n'#
10273 10:03:13.914563 No login prompt set.
10274 10:03:13.914642 Parsing kernel messages
10275 10:03:13.914711 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10276 10:03:13.914843 [login-action] Waiting for messages, (timeout 00:03:41)
10277 10:03:13.934839 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j19381-arm64-gcc-10-defconfig-arm64-chromebook-d6qsg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023
10278 10:03:13.937457 [ 0.000000] random: crng init done
10279 10:03:13.941031 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10280 10:03:13.943550 [ 0.000000] efi: UEFI not found.
10281 10:03:13.953833 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10282 10:03:13.960361 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10283 10:03:13.970283 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10284 10:03:13.980397 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10285 10:03:13.986754 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10286 10:03:13.993365 [ 0.000000] printk: bootconsole [mtk8250] enabled
10287 10:03:14.000354 [ 0.000000] NUMA: No NUMA configuration found
10288 10:03:14.006909 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10289 10:03:14.009718 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10290 10:03:14.013518 [ 0.000000] Zone ranges:
10291 10:03:14.019838 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10292 10:03:14.022931 [ 0.000000] DMA32 empty
10293 10:03:14.029655 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10294 10:03:14.032933 [ 0.000000] Movable zone start for each node
10295 10:03:14.036411 [ 0.000000] Early memory node ranges
10296 10:03:14.043339 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10297 10:03:14.049492 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10298 10:03:14.056093 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10299 10:03:14.062367 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10300 10:03:14.065655 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10301 10:03:14.075460 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10302 10:03:14.131743 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10303 10:03:14.137374 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10304 10:03:14.144364 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10305 10:03:14.147599 [ 0.000000] psci: probing for conduit method from DT.
10306 10:03:14.154158 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10307 10:03:14.157147 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10308 10:03:14.164542 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10309 10:03:14.167411 [ 0.000000] psci: SMC Calling Convention v1.2
10310 10:03:14.173713 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10311 10:03:14.177033 [ 0.000000] Detected VIPT I-cache on CPU0
10312 10:03:14.183543 [ 0.000000] CPU features: detected: GIC system register CPU interface
10313 10:03:14.190436 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10314 10:03:14.196965 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10315 10:03:14.203324 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10316 10:03:14.213589 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10317 10:03:14.219738 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10318 10:03:14.222861 [ 0.000000] alternatives: applying boot alternatives
10319 10:03:14.229823 [ 0.000000] Fallback order for Node 0: 0
10320 10:03:14.236378 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10321 10:03:14.239818 [ 0.000000] Policy zone: Normal
10322 10:03:14.259641 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10670666/extract-nfsrootfs-8_8v8c5l,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10323 10:03:14.269604 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10324 10:03:14.281587 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10325 10:03:14.291277 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10326 10:03:14.298413 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10327 10:03:14.301706 <6>[ 0.000000] software IO TLB: area num 8.
10328 10:03:14.359323 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10329 10:03:14.507554 <6>[ 0.000000] Memory: 7955720K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397048K reserved, 32768K cma-reserved)
10330 10:03:14.514201 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10331 10:03:14.521382 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10332 10:03:14.524173 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10333 10:03:14.530843 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10334 10:03:14.537685 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10335 10:03:14.540582 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10336 10:03:14.551160 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10337 10:03:14.557433 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10338 10:03:14.563887 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10339 10:03:14.570390 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10340 10:03:14.573932 <6>[ 0.000000] GICv3: 608 SPIs implemented
10341 10:03:14.577132 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10342 10:03:14.583625 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10343 10:03:14.586657 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10344 10:03:14.593587 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10345 10:03:14.607013 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10346 10:03:14.620390 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10347 10:03:14.626128 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10348 10:03:14.634231 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10349 10:03:14.647484 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10350 10:03:14.654083 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10351 10:03:14.661245 <6>[ 0.009181] Console: colour dummy device 80x25
10352 10:03:14.670570 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10353 10:03:14.677458 <6>[ 0.024416] pid_max: default: 32768 minimum: 301
10354 10:03:14.680996 <6>[ 0.029290] LSM: Security Framework initializing
10355 10:03:14.687442 <6>[ 0.034228] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10356 10:03:14.697002 <6>[ 0.042042] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10357 10:03:14.707464 <6>[ 0.051470] cblist_init_generic: Setting adjustable number of callback queues.
10358 10:03:14.711148 <6>[ 0.058922] cblist_init_generic: Setting shift to 3 and lim to 1.
10359 10:03:14.717129 <6>[ 0.065300] cblist_init_generic: Setting shift to 3 and lim to 1.
10360 10:03:14.723753 <6>[ 0.071747] rcu: Hierarchical SRCU implementation.
10361 10:03:14.730386 <6>[ 0.076761] rcu: Max phase no-delay instances is 1000.
10362 10:03:14.737155 <6>[ 0.083778] EFI services will not be available.
10363 10:03:14.740928 <6>[ 0.088748] smp: Bringing up secondary CPUs ...
10364 10:03:14.747887 <6>[ 0.093802] Detected VIPT I-cache on CPU1
10365 10:03:14.754577 <6>[ 0.093876] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10366 10:03:14.760951 <6>[ 0.093908] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10367 10:03:14.764147 <6>[ 0.094245] Detected VIPT I-cache on CPU2
10368 10:03:14.774055 <6>[ 0.094295] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10369 10:03:14.780871 <6>[ 0.094310] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10370 10:03:14.783830 <6>[ 0.094567] Detected VIPT I-cache on CPU3
10371 10:03:14.791739 <6>[ 0.094616] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10372 10:03:14.797054 <6>[ 0.094630] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10373 10:03:14.804183 <6>[ 0.094932] CPU features: detected: Spectre-v4
10374 10:03:14.807720 <6>[ 0.094939] CPU features: detected: Spectre-BHB
10375 10:03:14.810853 <6>[ 0.094945] Detected PIPT I-cache on CPU4
10376 10:03:14.817038 <6>[ 0.095004] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10377 10:03:14.826619 <6>[ 0.095020] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10378 10:03:14.830705 <6>[ 0.095315] Detected PIPT I-cache on CPU5
10379 10:03:14.837001 <6>[ 0.095381] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10380 10:03:14.843445 <6>[ 0.095397] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10381 10:03:14.846664 <6>[ 0.095680] Detected PIPT I-cache on CPU6
10382 10:03:14.856239 <6>[ 0.095747] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10383 10:03:14.863239 <6>[ 0.095763] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10384 10:03:14.866103 <6>[ 0.096062] Detected PIPT I-cache on CPU7
10385 10:03:14.873407 <6>[ 0.096127] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10386 10:03:14.879493 <6>[ 0.096143] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10387 10:03:14.882606 <6>[ 0.096191] smp: Brought up 1 node, 8 CPUs
10388 10:03:14.889856 <6>[ 0.237553] SMP: Total of 8 processors activated.
10389 10:03:14.896258 <6>[ 0.242485] CPU features: detected: 32-bit EL0 Support
10390 10:03:14.902038 <6>[ 0.247848] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10391 10:03:14.909254 <6>[ 0.256648] CPU features: detected: Common not Private translations
10392 10:03:14.915492 <6>[ 0.263123] CPU features: detected: CRC32 instructions
10393 10:03:14.922566 <6>[ 0.268475] CPU features: detected: RCpc load-acquire (LDAPR)
10394 10:03:14.925473 <6>[ 0.274434] CPU features: detected: LSE atomic instructions
10395 10:03:14.931931 <6>[ 0.280216] CPU features: detected: Privileged Access Never
10396 10:03:14.938584 <6>[ 0.285996] CPU features: detected: RAS Extension Support
10397 10:03:14.945383 <6>[ 0.291639] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10398 10:03:14.948583 <6>[ 0.298859] CPU: All CPU(s) started at EL2
10399 10:03:14.955196 <6>[ 0.303175] alternatives: applying system-wide alternatives
10400 10:03:14.965144 <6>[ 0.313884] devtmpfs: initialized
10401 10:03:14.977615 <6>[ 0.322691] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10402 10:03:14.987437 <6>[ 0.332655] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10403 10:03:14.994654 <6>[ 0.340671] pinctrl core: initialized pinctrl subsystem
10404 10:03:14.997537 <6>[ 0.347344] DMI not present or invalid.
10405 10:03:15.004121 <6>[ 0.351752] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10406 10:03:15.014022 <6>[ 0.358611] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10407 10:03:15.020431 <6>[ 0.366196] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10408 10:03:15.030302 <6>[ 0.374412] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10409 10:03:15.034360 <6>[ 0.382650] audit: initializing netlink subsys (disabled)
10410 10:03:15.043576 <5>[ 0.388343] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10411 10:03:15.050188 <6>[ 0.389051] thermal_sys: Registered thermal governor 'step_wise'
10412 10:03:15.056907 <6>[ 0.396310] thermal_sys: Registered thermal governor 'power_allocator'
10413 10:03:15.059928 <6>[ 0.402561] cpuidle: using governor menu
10414 10:03:15.066813 <6>[ 0.413520] NET: Registered PF_QIPCRTR protocol family
10415 10:03:15.073399 <6>[ 0.419011] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10416 10:03:15.079960 <6>[ 0.426110] ASID allocator initialised with 32768 entries
10417 10:03:15.083551 <6>[ 0.432668] Serial: AMBA PL011 UART driver
10418 10:03:15.092739 <4>[ 0.441329] Trying to register duplicate clock ID: 134
10419 10:03:15.146941 <6>[ 0.498300] KASLR enabled
10420 10:03:15.161022 <6>[ 0.506050] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10421 10:03:15.167477 <6>[ 0.513067] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10422 10:03:15.174028 <6>[ 0.519557] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10423 10:03:15.180856 <6>[ 0.526562] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10424 10:03:15.187958 <6>[ 0.533051] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10425 10:03:15.193922 <6>[ 0.540054] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10426 10:03:15.200614 <6>[ 0.546540] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10427 10:03:15.207206 <6>[ 0.553542] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10428 10:03:15.210586 <6>[ 0.561049] ACPI: Interpreter disabled.
10429 10:03:15.219709 <6>[ 0.567437] iommu: Default domain type: Translated
10430 10:03:15.225438 <6>[ 0.572549] iommu: DMA domain TLB invalidation policy: strict mode
10431 10:03:15.228871 <5>[ 0.579202] SCSI subsystem initialized
10432 10:03:15.235480 <6>[ 0.583366] usbcore: registered new interface driver usbfs
10433 10:03:15.241833 <6>[ 0.589097] usbcore: registered new interface driver hub
10434 10:03:15.245631 <6>[ 0.594647] usbcore: registered new device driver usb
10435 10:03:15.252204 <6>[ 0.600720] pps_core: LinuxPPS API ver. 1 registered
10436 10:03:15.262219 <6>[ 0.605915] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10437 10:03:15.265799 <6>[ 0.615264] PTP clock support registered
10438 10:03:15.268777 <6>[ 0.619506] EDAC MC: Ver: 3.0.0
10439 10:03:15.276259 <6>[ 0.624647] FPGA manager framework
10440 10:03:15.282914 <6>[ 0.628325] Advanced Linux Sound Architecture Driver Initialized.
10441 10:03:15.286058 <6>[ 0.635034] vgaarb: loaded
10442 10:03:15.292708 <6>[ 0.638213] clocksource: Switched to clocksource arch_sys_counter
10443 10:03:15.296719 <5>[ 0.644650] VFS: Disk quotas dquot_6.6.0
10444 10:03:15.302665 <6>[ 0.648832] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10445 10:03:15.306270 <6>[ 0.656015] pnp: PnP ACPI: disabled
10446 10:03:15.314350 <6>[ 0.662675] NET: Registered PF_INET protocol family
10447 10:03:15.320845 <6>[ 0.668050] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10448 10:03:15.335328 <6>[ 0.680332] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10449 10:03:15.345016 <6>[ 0.689146] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10450 10:03:15.351718 <6>[ 0.697114] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10451 10:03:15.361752 <6>[ 0.705812] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10452 10:03:15.367970 <6>[ 0.715561] TCP: Hash tables configured (established 65536 bind 65536)
10453 10:03:15.375012 <6>[ 0.722416] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10454 10:03:15.384400 <6>[ 0.729614] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10455 10:03:15.390878 <6>[ 0.737315] NET: Registered PF_UNIX/PF_LOCAL protocol family
10456 10:03:15.397446 <6>[ 0.743487] RPC: Registered named UNIX socket transport module.
10457 10:03:15.400738 <6>[ 0.749642] RPC: Registered udp transport module.
10458 10:03:15.407483 <6>[ 0.754576] RPC: Registered tcp transport module.
10459 10:03:15.413978 <6>[ 0.759506] RPC: Registered tcp NFSv4.1 backchannel transport module.
10460 10:03:15.417257 <6>[ 0.766177] PCI: CLS 0 bytes, default 64
10461 10:03:15.420697 <6>[ 0.770566] Unpacking initramfs...
10462 10:03:15.431267 <6>[ 0.774663] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10463 10:03:15.437500 <6>[ 0.783298] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10464 10:03:15.444457 <6>[ 0.792131] kvm [1]: IPA Size Limit: 40 bits
10465 10:03:15.447118 <6>[ 0.796660] kvm [1]: GICv3: no GICV resource entry
10466 10:03:15.453778 <6>[ 0.801679] kvm [1]: disabling GICv2 emulation
10467 10:03:15.460482 <6>[ 0.806362] kvm [1]: GIC system register CPU interface enabled
10468 10:03:15.463829 <6>[ 0.812521] kvm [1]: vgic interrupt IRQ18
10469 10:03:15.470239 <6>[ 0.816882] kvm [1]: VHE mode initialized successfully
10470 10:03:15.473614 <5>[ 0.823269] Initialise system trusted keyrings
10471 10:03:15.480001 <6>[ 0.828030] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10472 10:03:15.489806 <6>[ 0.837997] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10473 10:03:15.496016 <5>[ 0.844358] NFS: Registering the id_resolver key type
10474 10:03:15.499317 <5>[ 0.849664] Key type id_resolver registered
10475 10:03:15.506312 <5>[ 0.854081] Key type id_legacy registered
10476 10:03:15.512466 <6>[ 0.858359] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10477 10:03:15.519735 <6>[ 0.865282] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10478 10:03:15.526173 <6>[ 0.872984] 9p: Installing v9fs 9p2000 file system support
10479 10:03:15.561877 <5>[ 0.910294] Key type asymmetric registered
10480 10:03:15.565145 <5>[ 0.914623] Asymmetric key parser 'x509' registered
10481 10:03:15.575184 <6>[ 0.919751] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10482 10:03:15.578789 <6>[ 0.927364] io scheduler mq-deadline registered
10483 10:03:15.581578 <6>[ 0.932122] io scheduler kyber registered
10484 10:03:15.600490 <6>[ 0.948674] EINJ: ACPI disabled.
10485 10:03:15.631871 <4>[ 0.973706] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10486 10:03:15.642032 <4>[ 0.984320] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10487 10:03:15.656426 <6>[ 1.004504] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10488 10:03:15.663742 <6>[ 1.012387] printk: console [ttyS0] disabled
10489 10:03:15.691892 <6>[ 1.037032] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10490 10:03:15.698489 <6>[ 1.046503] printk: console [ttyS0] enabled
10491 10:03:15.701803 <6>[ 1.046503] printk: console [ttyS0] enabled
10492 10:03:15.708608 <6>[ 1.055397] printk: bootconsole [mtk8250] disabled
10493 10:03:15.711465 <6>[ 1.055397] printk: bootconsole [mtk8250] disabled
10494 10:03:15.718302 <6>[ 1.066411] SuperH (H)SCI(F) driver initialized
10495 10:03:15.721753 <6>[ 1.071671] msm_serial: driver initialized
10496 10:03:15.736182 <6>[ 1.080490] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10497 10:03:15.745600 <6>[ 1.089042] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10498 10:03:15.752554 <6>[ 1.097584] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10499 10:03:15.761894 <6>[ 1.106215] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10500 10:03:15.771955 <6>[ 1.114920] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10501 10:03:15.778215 <6>[ 1.123640] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10502 10:03:15.788290 <6>[ 1.132185] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10503 10:03:15.795041 <6>[ 1.140983] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10504 10:03:15.804770 <6>[ 1.149526] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10505 10:03:15.816856 <6>[ 1.164856] loop: module loaded
10506 10:03:15.823143 <6>[ 1.170821] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10507 10:03:15.845741 <4>[ 1.193988] mtk-pmic-keys: Failed to locate of_node [id: -1]
10508 10:03:15.852012 <6>[ 1.200675] megasas: 07.719.03.00-rc1
10509 10:03:15.862133 <6>[ 1.210112] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10510 10:03:15.869368 <6>[ 1.217617] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10511 10:03:15.885352 <6>[ 1.233456] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10512 10:03:15.938774 <6>[ 1.280527] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10513 10:03:16.195998 <6>[ 1.544441] Freeing initrd memory: 17220K
10514 10:03:16.205793 <6>[ 1.554569] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10515 10:03:16.217067 <6>[ 1.565292] tun: Universal TUN/TAP device driver, 1.6
10516 10:03:16.220404 <6>[ 1.571333] thunder_xcv, ver 1.0
10517 10:03:16.223394 <6>[ 1.574839] thunder_bgx, ver 1.0
10518 10:03:16.226733 <6>[ 1.578335] nicpf, ver 1.0
10519 10:03:16.237472 <6>[ 1.582349] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10520 10:03:16.240331 <6>[ 1.589823] hns3: Copyright (c) 2017 Huawei Corporation.
10521 10:03:16.247081 <6>[ 1.595408] hclge is initializing
10522 10:03:16.250653 <6>[ 1.598982] e1000: Intel(R) PRO/1000 Network Driver
10523 10:03:16.257067 <6>[ 1.604110] e1000: Copyright (c) 1999-2006 Intel Corporation.
10524 10:03:16.260820 <6>[ 1.610125] e1000e: Intel(R) PRO/1000 Network Driver
10525 10:03:16.267322 <6>[ 1.615341] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10526 10:03:16.273982 <6>[ 1.621527] igb: Intel(R) Gigabit Ethernet Network Driver
10527 10:03:16.280563 <6>[ 1.627177] igb: Copyright (c) 2007-2014 Intel Corporation.
10528 10:03:16.287558 <6>[ 1.633012] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10529 10:03:16.293427 <6>[ 1.639530] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10530 10:03:16.297169 <6>[ 1.645986] sky2: driver version 1.30
10531 10:03:16.303130 <6>[ 1.650960] VFIO - User Level meta-driver version: 0.3
10532 10:03:16.311124 <6>[ 1.659157] usbcore: registered new interface driver usb-storage
10533 10:03:16.317478 <6>[ 1.665595] usbcore: registered new device driver onboard-usb-hub
10534 10:03:16.327070 <6>[ 1.674653] mt6397-rtc mt6359-rtc: registered as rtc0
10535 10:03:16.336220 <6>[ 1.680129] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-10T10:03:18 UTC (1686391398)
10536 10:03:16.339337 <6>[ 1.689715] i2c_dev: i2c /dev entries driver
10537 10:03:16.355854 <6>[ 1.701254] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10538 10:03:16.362811 <6>[ 1.711429] sdhci: Secure Digital Host Controller Interface driver
10539 10:03:16.369710 <6>[ 1.717865] sdhci: Copyright(c) Pierre Ossman
10540 10:03:16.376188 <6>[ 1.723257] Synopsys Designware Multimedia Card Interface Driver
10541 10:03:16.379573 <6>[ 1.729853] mmc0: CQHCI version 5.10
10542 10:03:16.386018 <6>[ 1.730400] sdhci-pltfm: SDHCI platform and OF driver helper
10543 10:03:16.393485 <6>[ 1.742055] ledtrig-cpu: registered to indicate activity on CPUs
10544 10:03:16.404245 <6>[ 1.749448] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10545 10:03:16.407418 <6>[ 1.756854] usbcore: registered new interface driver usbhid
10546 10:03:16.414551 <6>[ 1.762687] usbhid: USB HID core driver
10547 10:03:16.420928 <6>[ 1.766926] spi_master spi0: will run message pump with realtime priority
10548 10:03:16.468995 <6>[ 1.810648] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10549 10:03:16.484947 <6>[ 1.826813] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10550 10:03:16.493311 <6>[ 1.840383] mmc0: Command Queue Engine enabled
10551 10:03:16.499428 <6>[ 1.843034] cros-ec-spi spi0.0: Chrome EC device registered
10552 10:03:16.502648 <6>[ 1.845132] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10553 10:03:16.510031 <6>[ 1.858065] mmcblk0: mmc0:0001 DA4128 116 GiB
10554 10:03:16.520153 <6>[ 1.868141] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10555 10:03:16.529570 <6>[ 1.868792] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10556 10:03:16.536017 <6>[ 1.875577] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10557 10:03:16.540065 <6>[ 1.885499] NET: Registered PF_PACKET protocol family
10558 10:03:16.546985 <6>[ 1.889227] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10559 10:03:16.549150 <6>[ 1.894041] 9pnet: Installing 9P2000 support
10560 10:03:16.555939 <6>[ 1.899773] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10561 10:03:16.562563 <5>[ 1.903707] Key type dns_resolver registered
10562 10:03:16.565971 <6>[ 1.915334] registered taskstats version 1
10563 10:03:16.572390 <5>[ 1.919728] Loading compiled-in X.509 certificates
10564 10:03:16.606693 <4>[ 1.947072] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10565 10:03:16.615072 <4>[ 1.957760] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10566 10:03:16.625441 <3>[ 1.970645] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10567 10:03:16.637439 <6>[ 1.986073] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10568 10:03:16.644442 <6>[ 1.992877] xhci-mtk 11200000.usb: xHCI Host Controller
10569 10:03:16.651079 <6>[ 1.998421] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10570 10:03:16.661694 <6>[ 2.006283] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10571 10:03:16.667859 <6>[ 2.015730] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10572 10:03:16.674536 <6>[ 2.021825] xhci-mtk 11200000.usb: xHCI Host Controller
10573 10:03:16.680975 <6>[ 2.027441] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10574 10:03:16.687423 <6>[ 2.035113] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10575 10:03:16.694381 <6>[ 2.042973] hub 1-0:1.0: USB hub found
10576 10:03:16.697668 <6>[ 2.047009] hub 1-0:1.0: 1 port detected
10577 10:03:16.707591 <6>[ 2.051357] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10578 10:03:16.711609 <6>[ 2.060153] hub 2-0:1.0: USB hub found
10579 10:03:16.714658 <6>[ 2.064192] hub 2-0:1.0: 1 port detected
10580 10:03:16.722580 <6>[ 2.071438] mtk-msdc 11f70000.mmc: Got CD GPIO
10581 10:03:16.739802 <6>[ 2.085117] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10582 10:03:16.746803 <6>[ 2.093166] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10583 10:03:16.756497 <4>[ 2.101154] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10584 10:03:16.766698 <6>[ 2.110815] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10585 10:03:16.772979 <6>[ 2.118903] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10586 10:03:16.780331 <6>[ 2.126925] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10587 10:03:16.790003 <6>[ 2.134841] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10588 10:03:16.796272 <6>[ 2.142666] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10589 10:03:16.806488 <6>[ 2.150488] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10590 10:03:16.816418 <6>[ 2.161070] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10591 10:03:16.822670 <6>[ 2.169436] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10592 10:03:16.832815 <6>[ 2.177794] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10593 10:03:16.839287 <6>[ 2.186141] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10594 10:03:16.849039 <6>[ 2.194485] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10595 10:03:16.859724 <6>[ 2.202829] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10596 10:03:16.866311 <6>[ 2.211172] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10597 10:03:16.875825 <6>[ 2.219516] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10598 10:03:16.882694 <6>[ 2.227859] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10599 10:03:16.892432 <6>[ 2.236203] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10600 10:03:16.898963 <6>[ 2.244547] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10601 10:03:16.909029 <6>[ 2.252899] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10602 10:03:16.915551 <6>[ 2.261245] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10603 10:03:16.926344 <6>[ 2.269590] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10604 10:03:16.932592 <6>[ 2.277934] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10605 10:03:16.938645 <6>[ 2.286820] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10606 10:03:16.945631 <6>[ 2.294140] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10607 10:03:16.952875 <6>[ 2.301153] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10608 10:03:16.962793 <6>[ 2.308233] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10609 10:03:16.969754 <6>[ 2.315495] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10610 10:03:16.979968 <6>[ 2.322422] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10611 10:03:16.986426 <6>[ 2.331562] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10612 10:03:16.995864 <6>[ 2.340691] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10613 10:03:17.006281 <6>[ 2.349993] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10614 10:03:17.015966 <6>[ 2.359469] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10615 10:03:17.025499 <6>[ 2.368944] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10616 10:03:17.035342 <6>[ 2.378071] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10617 10:03:17.042208 <6>[ 2.387546] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10618 10:03:17.052284 <6>[ 2.396685] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10619 10:03:17.062220 <6>[ 2.405988] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10620 10:03:17.071959 <6>[ 2.416154] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10621 10:03:17.082532 <6>[ 2.427923] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10622 10:03:17.089338 <6>[ 2.438039] Trying to probe devices needed for running init ...
10623 10:03:17.129574 <6>[ 2.474492] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10624 10:03:17.283339 <6>[ 2.631811] hub 1-1:1.0: USB hub found
10625 10:03:17.286415 <6>[ 2.636265] hub 1-1:1.0: 4 ports detected
10626 10:03:17.409101 <6>[ 2.754674] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10627 10:03:17.434315 <6>[ 2.782792] hub 2-1:1.0: USB hub found
10628 10:03:17.437375 <6>[ 2.787187] hub 2-1:1.0: 3 ports detected
10629 10:03:17.609679 <6>[ 2.954489] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10630 10:03:17.742158 <6>[ 3.090604] hub 1-1.4:1.0: USB hub found
10631 10:03:17.744971 <6>[ 3.095280] hub 1-1.4:1.0: 2 ports detected
10632 10:03:17.821370 <6>[ 3.166723] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10633 10:03:18.040990 <6>[ 3.386488] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10634 10:03:18.233397 <6>[ 3.578486] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10635 10:03:29.378031 <6>[ 14.731094] ALSA device list:
10636 10:03:29.384393 <6>[ 14.734351] No soundcards found.
10637 10:03:29.396666 <6>[ 14.746778] Freeing unused kernel memory: 8384K
10638 10:03:29.399996 <6>[ 14.751713] Run /init as init process
10639 10:03:29.410285 Loading, please wait...
10640 10:03:29.429621 Starting version 247.3-7+deb11u2
10641 10:03:29.750139 <6>[ 15.096802] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10642 10:03:29.762025 <6>[ 15.111546] remoteproc remoteproc0: scp is available
10643 10:03:29.771322 <4>[ 15.117330] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10644 10:03:29.778340 <6>[ 15.127218] remoteproc remoteproc0: powering up scp
10645 10:03:29.788299 <4>[ 15.133709] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10646 10:03:29.794964 <3>[ 15.144490] remoteproc remoteproc0: request_firmware failed: -2
10647 10:03:29.804919 <6>[ 15.146907] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10648 10:03:29.811160 <3>[ 15.150925] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10649 10:03:29.821067 <6>[ 15.158371] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10650 10:03:29.824310 <6>[ 15.158949] mc: Linux media interface: v0.10
10651 10:03:29.830849 <6>[ 15.162793] usbcore: registered new interface driver r8152
10652 10:03:29.837514 <3>[ 15.166451] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10653 10:03:29.847554 <6>[ 15.175106] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10654 10:03:29.854935 <3>[ 15.179672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10655 10:03:29.863996 <4>[ 15.183071] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10656 10:03:29.871324 <4>[ 15.198508] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10657 10:03:29.873819 <6>[ 15.207547] videodev: Linux video capture interface: v2.00
10658 10:03:29.883902 <3>[ 15.215731] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10659 10:03:29.890511 <3>[ 15.238706] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10660 10:03:29.900500 <6>[ 15.243750] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10661 10:03:29.908152 <3>[ 15.246800] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10662 10:03:29.917263 <3>[ 15.246810] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 10:03:29.924615 <3>[ 15.246816] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10664 10:03:29.929917 <6>[ 15.266512] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10665 10:03:29.940839 <3>[ 15.270762] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10666 10:03:29.946828 <3>[ 15.294088] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10667 10:03:29.956344 <3>[ 15.302207] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10668 10:03:29.966402 <6>[ 15.303226] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10669 10:03:29.973128 <6>[ 15.307682] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10670 10:03:29.979279 <6>[ 15.307690] pci_bus 0000:00: root bus resource [bus 00-ff]
10671 10:03:29.985925 <6>[ 15.307698] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10672 10:03:29.995947 <6>[ 15.307703] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10673 10:03:30.002606 <6>[ 15.307736] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10674 10:03:30.008676 <6>[ 15.307753] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10675 10:03:30.012044 <6>[ 15.307839] pci 0000:00:00.0: supports D1 D2
10676 10:03:30.018644 <6>[ 15.307844] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10677 10:03:30.028403 <6>[ 15.309659] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10678 10:03:30.035559 <6>[ 15.309757] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10679 10:03:30.042747 <6>[ 15.309786] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10680 10:03:30.048303 <6>[ 15.309806] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10681 10:03:30.058501 <6>[ 15.309823] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10682 10:03:30.061943 <6>[ 15.309933] pci 0000:01:00.0: supports D1 D2
10683 10:03:30.068453 <6>[ 15.309936] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10684 10:03:30.078427 <3>[ 15.310325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10685 10:03:30.085068 <3>[ 15.310582] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10686 10:03:30.094744 <6>[ 15.320982] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10687 10:03:30.101353 <6>[ 15.322580] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10688 10:03:30.108117 <6>[ 15.322606] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10689 10:03:30.118264 <6>[ 15.322614] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10690 10:03:30.125518 <6>[ 15.322627] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10691 10:03:30.131890 <6>[ 15.322643] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10692 10:03:30.141747 <6>[ 15.322658] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10693 10:03:30.145304 <6>[ 15.322674] pci 0000:00:00.0: PCI bridge to [bus 01]
10694 10:03:30.154794 <6>[ 15.322681] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10695 10:03:30.162039 <6>[ 15.322806] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10696 10:03:30.165482 <6>[ 15.323661] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10697 10:03:30.172368 <6>[ 15.324131] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10698 10:03:30.182027 <3>[ 15.327306] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 10:03:30.188835 <3>[ 15.327313] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 10:03:30.198441 <3>[ 15.327320] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 10:03:30.205560 <3>[ 15.327327] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10702 10:03:30.211775 <3>[ 15.327361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 10:03:30.221974 <4>[ 15.335722] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10704 10:03:30.231641 <6>[ 15.336795] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10705 10:03:30.238106 <6>[ 15.340591] usbcore: registered new interface driver cdc_ether
10706 10:03:30.244563 <4>[ 15.350198] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10707 10:03:30.254872 <5>[ 15.358725] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10708 10:03:30.261402 <6>[ 15.368786] usbcore: registered new interface driver r8153_ecm
10709 10:03:30.264900 <6>[ 15.384714] Bluetooth: Core ver 2.22
10710 10:03:30.271502 <5>[ 15.387672] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10711 10:03:30.278542 <4>[ 15.387754] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10712 10:03:30.284599 <6>[ 15.387762] cfg80211: failed to load regulatory.db
10713 10:03:30.291430 <6>[ 15.393356] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10714 10:03:30.297450 <6>[ 15.397737] NET: Registered PF_BLUETOOTH protocol family
10715 10:03:30.307617 <6>[ 15.406479] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10716 10:03:30.314657 <6>[ 15.412568] Bluetooth: HCI device and connection manager initialized
10717 10:03:30.320969 <6>[ 15.412596] Bluetooth: HCI socket layer initialized
10718 10:03:30.327362 <6>[ 15.415101] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10719 10:03:30.334184 <6>[ 15.417312] usbcore: registered new interface driver uvcvideo
10720 10:03:30.337525 <6>[ 15.424003] Bluetooth: L2CAP socket layer initialized
10721 10:03:30.344145 <6>[ 15.426326] r8152 2-1.3:1.0 eth0: v1.12.13
10722 10:03:30.350408 <4>[ 15.432082] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10723 10:03:30.357211 <4>[ 15.432082] Fallback method does not support PEC.
10724 10:03:30.363753 <6>[ 15.435099] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10725 10:03:30.367075 <6>[ 15.440260] Bluetooth: SCO socket layer initialized
10726 10:03:30.376759 <3>[ 15.464739] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10727 10:03:30.383325 <6>[ 15.492038] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10728 10:03:30.390285 <6>[ 15.516529] usbcore: registered new interface driver btusb
10729 10:03:30.399845 <4>[ 15.517232] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10730 10:03:30.406646 <3>[ 15.517240] Bluetooth: hci0: Failed to load firmware file (-2)
10731 10:03:30.413320 <3>[ 15.517243] Bluetooth: hci0: Failed to set up firmware (-2)
10732 10:03:30.423324 <4>[ 15.517246] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10733 10:03:30.433742 <3>[ 15.519161] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10734 10:03:30.436251 <6>[ 15.521970] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10735 10:03:30.462774 <6>[ 15.813144] mt7921e 0000:01:00.0: ASIC revision: 79610010
10736 10:03:30.570516 <4>[ 15.913917] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10737 10:03:30.584329 Begin: Loading essential drivers ... done.
10738 10:03:30.587640 Begin: Running /scripts/init-premount ... done.
10739 10:03:30.597254 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10740 10:03:30.603840 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10741 10:03:30.606916 Device /sys/class/net/enx002432307c7b found
10742 10:03:30.610275 done.
10743 10:03:30.689327 <4>[ 16.032755] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10744 10:03:30.696190 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10745 10:03:30.808672 <4>[ 16.152019] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10746 10:03:30.924214 <4>[ 16.267918] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10747 10:03:31.040023 <4>[ 16.383888] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10748 10:03:31.156646 <4>[ 16.499771] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10749 10:03:31.272454 <4>[ 16.615760] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10750 10:03:31.388247 <4>[ 16.731666] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10751 10:03:31.503874 <4>[ 16.847602] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10752 10:03:31.620069 <4>[ 16.963651] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10753 10:03:31.728011 <3>[ 17.077560] mt7921e 0000:01:00.0: hardware init failed
10754 10:03:31.799941 <6>[ 17.149559] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10755 10:03:31.829863 IP-Config: no response after 2 secs - giving up
10756 10:03:31.860277 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10757 10:03:32.964670 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10758 10:03:32.971196 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10759 10:03:32.978577 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10760 10:03:32.984565 host : mt8192-asurada-spherion-r0-cbg-2
10761 10:03:32.990645 domain : lava-rack
10762 10:03:32.997254 rootserver: 192.168.201.1 rootpath:
10763 10:03:32.997348 filename :
10764 10:03:33.019911 done.
10765 10:03:33.028468 Begin: Running /scripts/nfs-bottom ... done.
10766 10:03:33.047586 Begin: Running /scripts/init-bottom ... done.
10767 10:03:34.211091 <6>[ 19.560953] NET: Registered PF_INET6 protocol family
10768 10:03:34.217165 <6>[ 19.567577] Segment Routing with IPv6
10769 10:03:34.220699 <6>[ 19.571540] In-situ OAM (IOAM) with IPv6
10770 10:03:34.348647 <30>[ 19.678588] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10771 10:03:34.352009 <30>[ 19.702418] systemd[1]: Detected architecture arm64.
10772 10:03:34.373102
10773 10:03:34.376575 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10774 10:03:34.376999
10775 10:03:34.399762 <30>[ 19.749214] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10776 10:03:35.166555 <30>[ 20.513824] systemd[1]: Queued start job for default target Graphical Interface.
10777 10:03:35.201243 <30>[ 20.551474] systemd[1]: Created slice system-getty.slice.
10778 10:03:35.207733 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10779 10:03:35.224745 <30>[ 20.574963] systemd[1]: Created slice system-modprobe.slice.
10780 10:03:35.231135 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10781 10:03:35.249641 <30>[ 20.599679] systemd[1]: Created slice system-serial\x2dgetty.slice.
10782 10:03:35.260125 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10783 10:03:35.272677 <30>[ 20.622797] systemd[1]: Created slice User and Session Slice.
10784 10:03:35.279452 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10785 10:03:35.300232 <30>[ 20.647026] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10786 10:03:35.310265 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10787 10:03:35.328390 <30>[ 20.674960] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10788 10:03:35.334790 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10789 10:03:35.355240 <30>[ 20.698453] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10790 10:03:35.361728 <30>[ 20.710560] systemd[1]: Reached target Local Encrypted Volumes.
10791 10:03:35.367809 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10792 10:03:35.384385 <30>[ 20.734665] systemd[1]: Reached target Paths.
10793 10:03:35.388258 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10794 10:03:35.404280 <30>[ 20.754358] systemd[1]: Reached target Remote File Systems.
10795 10:03:35.410854 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10796 10:03:35.424562 <30>[ 20.774352] systemd[1]: Reached target Slices.
10797 10:03:35.427985 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10798 10:03:35.444402 <30>[ 20.794365] systemd[1]: Reached target Swap.
10799 10:03:35.447375 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10800 10:03:35.467812 <30>[ 20.814661] systemd[1]: Listening on initctl Compatibility Named Pipe.
10801 10:03:35.474565 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10802 10:03:35.490845 <30>[ 20.840579] systemd[1]: Listening on Journal Audit Socket.
10803 10:03:35.497463 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10804 10:03:35.513503 <30>[ 20.863740] systemd[1]: Listening on Journal Socket (/dev/log).
10805 10:03:35.520170 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10806 10:03:35.537410 <30>[ 20.887289] systemd[1]: Listening on Journal Socket.
10807 10:03:35.543657 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10808 10:03:35.561321 <30>[ 20.907821] systemd[1]: Listening on Network Service Netlink Socket.
10809 10:03:35.568170 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10810 10:03:35.582971 <30>[ 20.933313] systemd[1]: Listening on udev Control Socket.
10811 10:03:35.589805 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10812 10:03:35.604411 <30>[ 20.954538] systemd[1]: Listening on udev Kernel Socket.
10813 10:03:35.610993 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10814 10:03:35.648423 <30>[ 20.998544] systemd[1]: Mounting Huge Pages File System...
10815 10:03:35.655021 Mounting [0;1;39mHuge Pages File System[0m...
10816 10:03:35.670458 <30>[ 21.020531] systemd[1]: Mounting POSIX Message Queue File System...
10817 10:03:35.677219 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10818 10:03:35.694844 <30>[ 21.044905] systemd[1]: Mounting Kernel Debug File System...
10819 10:03:35.701052 Mounting [0;1;39mKernel Debug File System[0m...
10820 10:03:35.719586 <30>[ 21.066670] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10821 10:03:35.733514 <30>[ 21.079849] systemd[1]: Starting Create list of static device nodes for the current kernel...
10822 10:03:35.739339 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10823 10:03:35.758756 <30>[ 21.109567] systemd[1]: Starting Load Kernel Module configfs...
10824 10:03:35.765244 Starting [0;1;39mLoad Kernel Module configfs[0m...
10825 10:03:35.783254 <30>[ 21.133492] systemd[1]: Starting Load Kernel Module drm...
10826 10:03:35.789438 Starting [0;1;39mLoad Kernel Module drm[0m...
10827 10:03:35.806760 <30>[ 21.156969] systemd[1]: Starting Load Kernel Module fuse...
10828 10:03:35.813304 Starting [0;1;39mLoad Kernel Module fuse[0m...
10829 10:03:35.849044 <6>[ 21.199345] fuse: init (API version 7.37)
10830 10:03:35.859263 <30>[ 21.199542] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10831 10:03:35.888812 <30>[ 21.239017] systemd[1]: Starting Journal Service...
10832 10:03:35.891968 Starting [0;1;39mJournal Service[0m...
10833 10:03:35.917448 <30>[ 21.268064] systemd[1]: Starting Load Kernel Modules...
10834 10:03:35.924136 Starting [0;1;39mLoad Kernel Modules[0m...
10835 10:03:35.967392 <30>[ 21.315097] systemd[1]: Starting Remount Root and Kernel File Systems...
10836 10:03:35.974320 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10837 10:03:35.994745 <30>[ 21.345050] systemd[1]: Starting Coldplug All udev Devices...
10838 10:03:36.001281 Starting [0;1;39mColdplug All udev Devices[0m...
10839 10:03:36.019466 <30>[ 21.369251] systemd[1]: Mounted Huge Pages File System.
10840 10:03:36.025423 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10841 10:03:36.041230 <30>[ 21.391202] systemd[1]: Mounted POSIX Message Queue File System.
10842 10:03:36.047686 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10843 10:03:36.062156 <3>[ 21.409196] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10844 10:03:36.069165 <30>[ 21.418998] systemd[1]: Mounted Kernel Debug File System.
10845 10:03:36.075787 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10846 10:03:36.093083 <3>[ 21.440075] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10847 10:03:36.103075 <30>[ 21.449984] systemd[1]: Finished Create list of static device nodes for the current kernel.
10848 10:03:36.112898 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10849 10:03:36.125477 <30>[ 21.475451] systemd[1]: modprobe@configfs.service: Succeeded.
10850 10:03:36.135358 <3>[ 21.475795] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10851 10:03:36.142421 <30>[ 21.482136] systemd[1]: Finished Load Kernel Module configfs.
10852 10:03:36.148868 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10853 10:03:36.161497 <30>[ 21.511510] systemd[1]: modprobe@drm.service: Succeeded.
10854 10:03:36.171640 <3>[ 21.513239] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10855 10:03:36.174752 <30>[ 21.517748] systemd[1]: Finished Load Kernel Module drm.
10856 10:03:36.181490 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10857 10:03:36.197616 <30>[ 21.547802] systemd[1]: modprobe@fuse.service: Succeeded.
10858 10:03:36.207957 <3>[ 21.549072] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10859 10:03:36.214119 <30>[ 21.554122] systemd[1]: Finished Load Kernel Module fuse.
10860 10:03:36.217817 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10861 10:03:36.233302 <30>[ 21.583679] systemd[1]: Finished Load Kernel Modules.
10862 10:03:36.244387 <3>[ 21.584362] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10863 10:03:36.249999 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10864 10:03:36.265536 <30>[ 21.615611] systemd[1]: Finished Remount Root and Kernel File Systems.
10865 10:03:36.275724 <3>[ 21.619966] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10866 10:03:36.282153 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10867 10:03:36.306502 <3>[ 21.653474] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10868 10:03:36.336318 <3>[ 21.683355] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10869 10:03:36.342640 <30>[ 21.686247] systemd[1]: Mounting FUSE Control File System...
10870 10:03:36.349671 Mounting [0;1;39mFUSE Control File System[0m...
10871 10:03:36.367437 <3>[ 21.714377] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 10:03:36.374350 <30>[ 21.717000] systemd[1]: Mounting Kernel Configuration File System...
10873 10:03:36.380451 Mounting [0;1;39mKernel Configuration File System[0m...
10874 10:03:36.406833 <30>[ 21.753529] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10875 10:03:36.416944 <30>[ 21.762570] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10876 10:03:36.424418 <30>[ 21.774864] systemd[1]: Starting Load/Save Random Seed...
10877 10:03:36.430901 Starting [0;1;39mLoad/Save Random Seed[0m...
10878 10:03:36.446225 <30>[ 21.796900] systemd[1]: Starting Apply Kernel Variables...
10879 10:03:36.453920 Starting [0;1;39mApply Kernel Variables[0m...
10880 10:03:36.472787 <30>[ 21.822995] systemd[1]: Starting Create System Users...
10881 10:03:36.479115 Starting [0;1;39mCreate System Users[0m...
10882 10:03:36.494092 <30>[ 21.843972] systemd[1]: Started Journal Service.
10883 10:03:36.500109 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10884 10:03:36.514535 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10885 10:03:36.549904 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File S<4>[ 21.888564] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10886 10:03:36.550353 ystem[0m.
10887 10:03:36.556134 <3>[ 21.904470] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10888 10:03:36.565917 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10889 10:03:36.582807 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10890 10:03:36.604985 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10891 10:03:36.616548 See 'systemctl status systemd-udev-trigger.service' for details.
10892 10:03:36.633011 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10893 10:03:36.676884 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10894 10:03:36.694826 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10895 10:03:36.740649 <46>[ 22.087825] systemd-journald[295]: Received client request to flush runtime journal.
10896 10:03:37.504872 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10897 10:03:37.515807 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10898 10:03:37.531871 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10899 10:03:37.583748 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10900 10:03:38.133132 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10901 10:03:38.168325 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10902 10:03:38.239978 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10903 10:03:38.292905 Starting [0;1;39mNetwork Service[0m...
10904 10:03:38.586560 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10905 10:03:38.635947 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10906 10:03:38.654697 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10907 10:03:38.871124 <6>[ 24.221683] remoteproc remoteproc0: powering up scp
10908 10:03:38.904144 <4>[ 24.252128] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10909 10:03:38.911233 <3>[ 24.262039] remoteproc remoteproc0: request_firmware failed: -2
10910 10:03:38.920899 <3>[ 24.268227] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10911 10:03:39.032148 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10912 10:03:39.052060 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10913 10:03:39.067860 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10914 10:03:39.118701 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10915 10:03:39.135833 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10916 10:03:39.172145 Starting [0;1;39mNetwork Name Resolution[0m...
10917 10:03:39.202464 Starting [0;1;39mNetwork Time Synchronization[0m...
10918 10:03:39.223060 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10919 10:03:39.248580 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10920 10:03:39.289576 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10921 10:03:39.328338 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10922 10:03:39.511130 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10923 10:03:39.528080 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10924 10:03:39.551318 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10925 10:03:39.567873 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10926 10:03:39.589324 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10927 10:03:39.672436 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10928 10:03:39.701128 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10929 10:03:39.721411 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10930 10:03:39.749385 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10931 10:03:39.764138 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10932 10:03:39.814415 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10933 10:03:39.827837 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10934 10:03:39.843724 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10935 10:03:39.888137 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10936 10:03:40.591438 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10937 10:03:40.933054 Starting [0;1;39mUser Login Management[0m...
10938 10:03:40.948235 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10939 10:03:40.965044 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10940 10:03:40.982812 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10941 10:03:41.023639 Starting [0;1;39mPermit User Sessions[0m...
10942 10:03:41.135155 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10943 10:03:41.183831 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10944 10:03:41.202933 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10945 10:03:41.219608 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10946 10:03:41.244647 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10947 10:03:41.261133 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10948 10:03:41.280633 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10949 10:03:41.295691 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10950 10:03:41.351605 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10951 10:03:41.396167 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10952 10:03:41.463861
10953 10:03:41.464018
10954 10:03:41.467354 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10955 10:03:41.467430
10956 10:03:41.470221 debian-bullseye-arm64 login: root (automatic login)
10957 10:03:41.470298
10958 10:03:41.470362
10959 10:03:41.867477 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023 aarch64
10960 10:03:41.868020
10961 10:03:41.874449 The programs included with the Debian GNU/Linux system are free software;
10962 10:03:41.880620 the exact distribution terms for each program are described in the
10963 10:03:41.883830 individual files in /usr/share/doc/*/copyright.
10964 10:03:41.884437
10965 10:03:41.890699 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10966 10:03:41.893569 permitted by applicable law.
10967 10:03:42.851501 Matched prompt #10: / #
10969 10:03:42.852708 Setting prompt string to ['/ #']
10970 10:03:42.853181 end: 2.2.5.1 login-action (duration 00:00:29) [common]
10972 10:03:42.854148 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
10973 10:03:42.854577 start: 2.2.6 expect-shell-connection (timeout 00:03:12) [common]
10974 10:03:42.855073 Setting prompt string to ['/ #']
10975 10:03:42.855472 Forcing a shell prompt, looking for ['/ #']
10977 10:03:42.906334 / #
10978 10:03:42.907023 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10979 10:03:42.907516 Waiting using forced prompt support (timeout 00:02:30)
10980 10:03:42.912393
10981 10:03:42.913214 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10982 10:03:42.913731 start: 2.2.7 export-device-env (timeout 00:03:12) [common]
10984 10:03:43.015098 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10670666/extract-nfsrootfs-8_8v8c5l'
10985 10:03:43.021967 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10670666/extract-nfsrootfs-8_8v8c5l'
10987 10:03:43.123466 / # export NFS_SERVER_IP='192.168.201.1'
10988 10:03:43.129138 export NFS_SERVER_IP='192.168.201.1'
10989 10:03:43.129723 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10990 10:03:43.130059 end: 2.2 depthcharge-retry (duration 00:01:48) [common]
10991 10:03:43.130311 end: 2 depthcharge-action (duration 00:01:48) [common]
10992 10:03:43.130552 start: 3 lava-test-retry (timeout 00:07:24) [common]
10993 10:03:43.130783 start: 3.1 lava-test-shell (timeout 00:07:24) [common]
10994 10:03:43.130987 Using namespace: common
10996 10:03:43.231677 / # #
10997 10:03:43.232336 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10998 10:03:43.238017 #
10999 10:03:43.238712 Using /lava-10670666
11001 10:03:43.339685 / # export SHELL=/bin/bash
11002 10:03:43.346101 export SHELL=/bin/bash
11004 10:03:43.447396 / # . /lava-10670666/environment
11005 10:03:43.454287 . /lava-10670666/environment
11007 10:03:43.559541 / # /lava-10670666/bin/lava-test-runner /lava-10670666/0
11008 10:03:43.560093 Test shell timeout: 10s (minimum of the action and connection timeout)
11009 10:03:43.565729 /lava-10670666/bin/lava-test-runner /lava-10670666/0
11010 10:03:43.840560 + export TESTRUN_ID=0_timesync-off
11011 10:03:43.843678 + TESTRUN_ID=0_timesync-off
11012 10:03:43.846880 + cd /lava-10670666/0/tests/0_timesync-off
11013 10:03:43.850455 ++ cat uuid
11014 10:03:43.855436 + UUID=10670666_1.6.2.3.1
11015 10:03:43.855519 + set +x
11016 10:03:43.862588 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10670666_1.6.2.3.1>
11017 10:03:43.862850 Received signal: <STARTRUN> 0_timesync-off 10670666_1.6.2.3.1
11018 10:03:43.862927 Starting test lava.0_timesync-off (10670666_1.6.2.3.1)
11019 10:03:43.863012 Skipping test definition patterns.
11020 10:03:43.865156 + systemctl stop systemd-timesyncd
11021 10:03:43.902511 + set +x
11022 10:03:43.904908 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10670666_1.6.2.3.1>
11023 10:03:43.905159 Received signal: <ENDRUN> 0_timesync-off 10670666_1.6.2.3.1
11024 10:03:43.905244 Ending use of test pattern.
11025 10:03:43.905306 Ending test lava.0_timesync-off (10670666_1.6.2.3.1), duration 0.04
11027 10:03:43.979244 + export TESTRUN_ID=1_kselftest-arm64
11028 10:03:43.979356 + TESTRUN_ID=1_kselftest-arm64
11029 10:03:43.985680 + cd /lava-10670666/0/tests/1_kselftest-arm64
11030 10:03:43.985763 ++ cat uuid
11031 10:03:43.990643 + UUID=10670666_1.6.2.3.5
11032 10:03:43.990725 + set +x
11033 10:03:43.997221 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 10670666_1.6.2.3.5>
11034 10:03:43.997477 Received signal: <STARTRUN> 1_kselftest-arm64 10670666_1.6.2.3.5
11035 10:03:43.997551 Starting test lava.1_kselftest-arm64 (10670666_1.6.2.3.5)
11036 10:03:43.997632 Skipping test definition patterns.
11037 10:03:44.000834 + cd ./automated/linux/kselftest/
11038 10:03:44.027204 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11039 10:03:44.062925 INFO: install_deps skipped
11040 10:03:44.173905 --2023-06-10 10:03:44-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11041 10:03:44.185178 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11042 10:03:44.318495 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11043 10:03:44.451039 HTTP request sent, awaiting response... 200 OK
11044 10:03:44.454847 Length: 2883260 (2.7M) [application/octet-stream]
11045 10:03:44.457757 Saving to: 'kselftest.tar.xz'
11046 10:03:44.457839
11047 10:03:44.457902
11048 10:03:44.717623 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11049 10:03:44.984544 kselftest.tar.xz 1%[ ] 47.81K 180KB/s
11050 10:03:45.302109 kselftest.tar.xz 7%[> ] 217.50K 409KB/s
11051 10:03:45.581740 kselftest.tar.xz 29%[====> ] 841.10K 990KB/s
11052 10:03:45.689349 kselftest.tar.xz 71%[=============> ] 1.96M 1.73MB/s
11053 10:03:45.695851 kselftest.tar.xz 100%[===================>] 2.75M 2.22MB/s in 1.2s
11054 10:03:45.695966
11055 10:03:45.945863 2023-06-10 10:03:45 (2.22 MB/s) - 'kselftest.tar.xz' saved [2883260/2883260]
11056 10:03:45.946006
11057 10:03:51.666764 skiplist:
11058 10:03:51.670134 ========================================
11059 10:03:51.673025 ========================================
11060 10:03:51.717817 arm64:tags_test
11061 10:03:51.720739 arm64:run_tags_test.sh
11062 10:03:51.720822 arm64:fake_sigreturn_bad_magic
11063 10:03:51.724154 arm64:fake_sigreturn_bad_size
11064 10:03:51.727210 arm64:fake_sigreturn_bad_size_for_magic0
11065 10:03:51.730853 arm64:fake_sigreturn_duplicated_fpsimd
11066 10:03:51.733557 arm64:fake_sigreturn_misaligned_sp
11067 10:03:51.737385 arm64:fake_sigreturn_missing_fpsimd
11068 10:03:51.740168 arm64:fake_sigreturn_sme_change_vl
11069 10:03:51.744320 arm64:fake_sigreturn_sve_change_vl
11070 10:03:51.747384 arm64:mangle_pstate_invalid_compat_toggle
11071 10:03:51.750625 arm64:mangle_pstate_invalid_daif_bits
11072 10:03:51.753454 arm64:mangle_pstate_invalid_mode_el1h
11073 10:03:51.756716 arm64:mangle_pstate_invalid_mode_el1t
11074 10:03:51.760072 arm64:mangle_pstate_invalid_mode_el2h
11075 10:03:51.763434 arm64:mangle_pstate_invalid_mode_el2t
11076 10:03:51.766586 arm64:mangle_pstate_invalid_mode_el3h
11077 10:03:51.773386 arm64:mangle_pstate_invalid_mode_el3t
11078 10:03:51.773467 arm64:sme_trap_no_sm
11079 10:03:51.776555 arm64:sme_trap_non_streaming
11080 10:03:51.776636 arm64:sme_trap_za
11081 10:03:51.779799 arm64:sme_vl
11082 10:03:51.779879 arm64:ssve_regs
11083 10:03:51.783172 arm64:sve_regs
11084 10:03:51.783253 arm64:sve_vl
11085 10:03:51.783316 arm64:za_no_regs
11086 10:03:51.786638 arm64:za_regs
11087 10:03:51.786718 arm64:pac
11088 10:03:51.789983 arm64:fp-stress
11089 10:03:51.790064 arm64:sve-ptrace
11090 10:03:51.793330 arm64:sve-probe-vls
11091 10:03:51.793410 arm64:vec-syscfg
11092 10:03:51.793474 arm64:za-fork
11093 10:03:51.796404 arm64:za-ptrace
11094 10:03:51.799879 arm64:check_buffer_fill
11095 10:03:51.799960 arm64:check_child_memory
11096 10:03:51.803344 arm64:check_gcr_el1_cswitch
11097 10:03:51.806438 arm64:check_ksm_options
11098 10:03:51.806519 arm64:check_mmap_options
11099 10:03:51.810207 arm64:check_prctl
11100 10:03:51.813097 arm64:check_tags_inclusion
11101 10:03:51.813178 arm64:check_user_mem
11102 10:03:51.816699 arm64:btitest
11103 10:03:51.816779 arm64:nobtitest
11104 10:03:51.816843 arm64:hwcap
11105 10:03:51.819602 arm64:ptrace
11106 10:03:51.819682 arm64:syscall-abi
11107 10:03:51.822935 arm64:tpidr2
11108 10:03:51.826530 ============== Tests to run ===============
11109 10:03:51.826611 arm64:tags_test
11110 10:03:51.829748 arm64:run_tags_test.sh
11111 10:03:51.833046 arm64:fake_sigreturn_bad_magic
11112 10:03:51.836374 arm64:fake_sigreturn_bad_size
11113 10:03:51.839355 arm64:fake_sigreturn_bad_size_for_magic0
11114 10:03:51.843193 arm64:fake_sigreturn_duplicated_fpsimd
11115 10:03:51.846492 arm64:fake_sigreturn_misaligned_sp
11116 10:03:51.849059 arm64:fake_sigreturn_missing_fpsimd
11117 10:03:51.852361 arm64:fake_sigreturn_sme_change_vl
11118 10:03:51.855944 arm64:fake_sigreturn_sve_change_vl
11119 10:03:51.858975 arm64:mangle_pstate_invalid_compat_toggle
11120 10:03:51.862458 arm64:mangle_pstate_invalid_daif_bits
11121 10:03:51.865941 arm64:mangle_pstate_invalid_mode_el1h
11122 10:03:51.869151 arm64:mangle_pstate_invalid_mode_el1t
11123 10:03:51.872234 arm64:mangle_pstate_invalid_mode_el2h
11124 10:03:51.875590 arm64:mangle_pstate_invalid_mode_el2t
11125 10:03:51.878965 arm64:mangle_pstate_invalid_mode_el3h
11126 10:03:51.882494 arm64:mangle_pstate_invalid_mode_el3t
11127 10:03:51.882575 arm64:sme_trap_no_sm
11128 10:03:51.885415 arm64:sme_trap_non_streaming
11129 10:03:51.888934 arm64:sme_trap_za
11130 10:03:51.889014 arm64:sme_vl
11131 10:03:51.891956 arm64:ssve_regs
11132 10:03:51.892078 arm64:sve_regs
11133 10:03:51.892144 arm64:sve_vl
11134 10:03:51.895283 arm64:za_no_regs
11135 10:03:51.895363 arm64:za_regs
11136 10:03:51.895427 arm64:pac
11137 10:03:51.898646 arm64:fp-stress
11138 10:03:51.898728 arm64:sve-ptrace
11139 10:03:51.902057 arm64:sve-probe-vls
11140 10:03:51.902142 arm64:vec-syscfg
11141 10:03:51.905329 arm64:za-fork
11142 10:03:51.905414 arm64:za-ptrace
11143 10:03:51.908710 arm64:check_buffer_fill
11144 10:03:51.912752 arm64:check_child_memory
11145 10:03:51.912830 arm64:check_gcr_el1_cswitch
11146 10:03:51.916012 arm64:check_ksm_options
11147 10:03:51.918556 arm64:check_mmap_options
11148 10:03:51.918628 arm64:check_prctl
11149 10:03:51.922007 arm64:check_tags_inclusion
11150 10:03:51.925150 arm64:check_user_mem
11151 10:03:51.925237 arm64:btitest
11152 10:03:51.925302 arm64:nobtitest
11153 10:03:51.928695 arm64:hwcap
11154 10:03:51.928766 arm64:ptrace
11155 10:03:51.931636 arm64:syscall-abi
11156 10:03:51.931705 arm64:tpidr2
11157 10:03:51.934647 ===========End Tests to run ===============
11158 10:03:52.157469 <12>[ 37.509993] kselftest: Running tests in arm64
11159 10:03:52.166978 TAP version 13
11160 10:03:52.181748 1..48
11161 10:03:52.197714 # selftests: arm64: tags_test
11162 10:03:52.583268 ok 1 selftests: arm64: tags_test
11163 10:03:52.598524 # selftests: arm64: run_tags_test.sh
11164 10:03:52.652491 # --------------------
11165 10:03:52.655012 # running tags test
11166 10:03:52.655133 # --------------------
11167 10:03:52.658509 # [PASS]
11168 10:03:52.661600 ok 2 selftests: arm64: run_tags_test.sh
11169 10:03:52.675375 # selftests: arm64: fake_sigreturn_bad_magic
11170 10:03:52.726492 # Registered handlers for all signals.
11171 10:03:52.726714 # Detected MINSTKSIGSZ:4720
11172 10:03:52.730033 # Testcase initialized.
11173 10:03:52.733215 # uc context validated.
11174 10:03:52.736608 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11175 10:03:52.740010 # Handled SIG_COPYCTX
11176 10:03:52.740115 # Available space:3568
11177 10:03:52.746166 # Using badly built context - ERR: BAD MAGIC !
11178 10:03:52.752915 # SIG_OK -- SP:0xFFFFC5CB7900 si_addr@:0xffffc5cb7900 si_code:2 token@:0xffffc5cb66a0 offset:-4704
11179 10:03:52.756023 # ==>> completed. PASS(1)
11180 10:03:52.762845 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11181 10:03:52.769652 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC5CB66A0
11182 10:03:52.776058 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11183 10:03:52.779389 # selftests: arm64: fake_sigreturn_bad_size
11184 10:03:52.797509 # Registered handlers for all signals.
11185 10:03:52.797626 # Detected MINSTKSIGSZ:4720
11186 10:03:52.800343 # Testcase initialized.
11187 10:03:52.803960 # uc context validated.
11188 10:03:52.807292 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11189 10:03:52.810639 # Handled SIG_COPYCTX
11190 10:03:52.810738 # Available space:3568
11191 10:03:52.813716 # uc context validated.
11192 10:03:52.820663 # Using badly built context - ERR: Bad size for esr_context
11193 10:03:52.826934 # SIG_OK -- SP:0xFFFFCE4CE010 si_addr@:0xffffce4ce010 si_code:2 token@:0xffffce4ccdb0 offset:-4704
11194 10:03:52.830263 # ==>> completed. PASS(1)
11195 10:03:52.836775 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11196 10:03:52.844500 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCE4CCDB0
11197 10:03:52.846526 ok 4 selftests: arm64: fake_sigreturn_bad_size
11198 10:03:52.853171 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11199 10:03:52.868689 # Registered handlers for all signals.
11200 10:03:52.868778 # Detected MINSTKSIGSZ:4720
11201 10:03:52.871485 # Testcase initialized.
11202 10:03:52.875233 # uc context validated.
11203 10:03:52.878342 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11204 10:03:52.880936 # Handled SIG_COPYCTX
11205 10:03:52.881039 # Available space:3568
11206 10:03:52.887967 # Using badly built context - ERR: Bad size for terminator
11207 10:03:52.897793 # SIG_OK -- SP:0xFFFFD3F2B0C0 si_addr@:0xffffd3f2b0c0 si_code:2 token@:0xffffd3f29e60 offset:-4704
11208 10:03:52.897906 # ==>> completed. PASS(1)
11209 10:03:52.907895 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11210 10:03:52.914212 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD3F29E60
11211 10:03:52.917328 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11212 10:03:52.924429 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11213 10:03:52.941856 # Registered handlers for all signals.
11214 10:03:52.941950 # Detected MINSTKSIGSZ:4720
11215 10:03:52.945314 # Testcase initialized.
11216 10:03:52.948552 # uc context validated.
11217 10:03:52.951834 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11218 10:03:52.955072 # Handled SIG_COPYCTX
11219 10:03:52.955179 # Available space:3568
11220 10:03:52.961563 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11221 10:03:52.971122 # SIG_OK -- SP:0xFFFFEA421320 si_addr@:0xffffea421320 si_code:2 token@:0xffffea4200c0 offset:-4704
11222 10:03:52.971205 # ==>> completed. PASS(1)
11223 10:03:52.981707 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11224 10:03:52.987841 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEA4200C0
11225 10:03:52.991254 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11226 10:03:52.994829 # selftests: arm64: fake_sigreturn_misaligned_sp
11227 10:03:53.014372 # Registered handlers for all signals.
11228 10:03:53.014465 # Detected MINSTKSIGSZ:4720
11229 10:03:53.017708 # Testcase initialized.
11230 10:03:53.020989 # uc context validated.
11231 10:03:53.024074 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11232 10:03:53.027517 # Handled SIG_COPYCTX
11233 10:03:53.034033 # SIG_OK -- SP:0xFFFFF2EE14E3 si_addr@:0xfffff2ee14e3 si_code:2 token@:0xfffff2ee14e3 offset:0
11234 10:03:53.037245 # ==>> completed. PASS(1)
11235 10:03:53.043684 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11236 10:03:53.050404 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF2EE14E3
11237 10:03:53.057302 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11238 10:03:53.060280 # selftests: arm64: fake_sigreturn_missing_fpsimd
11239 10:03:53.085234 # Registered handlers for all signals.
11240 10:03:53.085330 # Detected MINSTKSIGSZ:4720
11241 10:03:53.088520 # Testcase initialized.
11242 10:03:53.091712 # uc context validated.
11243 10:03:53.095368 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11244 10:03:53.098706 # Handled SIG_COPYCTX
11245 10:03:53.101787 # Mangling template header. Spare space:4096
11246 10:03:53.104697 # Using badly built context - ERR: Missing FPSIMD
11247 10:03:53.115186 # SIG_OK -- SP:0xFFFFD768A440 si_addr@:0xffffd768a440 si_code:2 token@:0xffffd76891e0 offset:-4704
11248 10:03:53.118149 # ==>> completed. PASS(1)
11249 10:03:53.124738 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11250 10:03:53.131253 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD76891E0
11251 10:03:53.135007 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11252 10:03:53.140957 # selftests: arm64: fake_sigreturn_sme_change_vl
11253 10:03:53.154929 # Registered handlers for all signals.
11254 10:03:53.155015 # Detected MINSTKSIGSZ:4720
11255 10:03:53.157699 # ==>> completed. SKIP.
11256 10:03:53.164754 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11257 10:03:53.167922 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11258 10:03:53.174567 # selftests: arm64: fake_sigreturn_sve_change_vl
11259 10:03:53.224819 # Registered handlers for all signals.
11260 10:03:53.224960 # Detected MINSTKSIGSZ:4720
11261 10:03:53.228316 # ==>> completed. SKIP.
11262 10:03:53.234974 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11263 10:03:53.238153 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11264 10:03:53.245341 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11265 10:03:53.296839 # Registered handlers for all signals.
11266 10:03:53.296973 # Detected MINSTKSIGSZ:4720
11267 10:03:53.300690 # Testcase initialized.
11268 10:03:53.304473 # uc context validated.
11269 10:03:53.304559 # Handled SIG_TRIG
11270 10:03:53.313551 # SIG_OK -- SP:0xFFFFD8D23E00 si_addr@:0xffffd8d23e00 si_code:2 token@:(nil) offset:-281474319400448
11271 10:03:53.316685 # ==>> completed. PASS(1)
11272 10:03:53.323422 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11273 10:03:53.330883 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11274 10:03:53.333938 # selftests: arm64: mangle_pstate_invalid_daif_bits
11275 10:03:53.367225 # Registered handlers for all signals.
11276 10:03:53.367369 # Detected MINSTKSIGSZ:4720
11277 10:03:53.370967 # Testcase initialized.
11278 10:03:53.373788 # uc context validated.
11279 10:03:53.373886 # Handled SIG_TRIG
11280 10:03:53.384109 # SIG_OK -- SP:0xFFFFC13C3DF0 si_addr@:0xffffc13c3df0 si_code:2 token@:(nil) offset:-281473923694064
11281 10:03:53.387859 # ==>> completed. PASS(1)
11282 10:03:53.394307 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11283 10:03:53.396899 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11284 10:03:53.403273 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11285 10:03:53.438263 # Registered handlers for all signals.
11286 10:03:53.438402 # Detected MINSTKSIGSZ:4720
11287 10:03:53.442027 # Testcase initialized.
11288 10:03:53.444923 # uc context validated.
11289 10:03:53.445034 # Handled SIG_TRIG
11290 10:03:53.454650 # SIG_OK -- SP:0xFFFFC7F15C90 si_addr@:0xffffc7f15c90 si_code:2 token@:(nil) offset:-281474036227216
11291 10:03:53.458028 # ==>> completed. PASS(1)
11292 10:03:53.464494 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11293 10:03:53.467978 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11294 10:03:53.474734 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11295 10:03:53.506003 # Registered handlers for all signals.
11296 10:03:53.506129 # Detected MINSTKSIGSZ:4720
11297 10:03:53.509444 # Testcase initialized.
11298 10:03:53.512172 # uc context validated.
11299 10:03:53.512255 # Handled SIG_TRIG
11300 10:03:53.521973 # SIG_OK -- SP:0xFFFFC66EC500 si_addr@:0xffffc66ec500 si_code:2 token@:(nil) offset:-281474010891520
11301 10:03:53.525579 # ==>> completed. PASS(1)
11302 10:03:53.533197 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11303 10:03:53.535393 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11304 10:03:53.541820 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11305 10:03:53.576195 # Registered handlers for all signals.
11306 10:03:53.576345 # Detected MINSTKSIGSZ:4720
11307 10:03:53.579362 # Testcase initialized.
11308 10:03:53.583129 # uc context validated.
11309 10:03:53.583253 # Handled SIG_TRIG
11310 10:03:53.593403 # SIG_OK -- SP:0xFFFFC6F55E20 si_addr@:0xffffc6f55e20 si_code:2 token@:(nil) offset:-281474019712544
11311 10:03:53.596199 # ==>> completed. PASS(1)
11312 10:03:53.603245 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11313 10:03:53.606105 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11314 10:03:53.612406 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11315 10:03:53.647868 # Registered handlers for all signals.
11316 10:03:53.648071 # Detected MINSTKSIGSZ:4720
11317 10:03:53.650976 # Testcase initialized.
11318 10:03:53.654734 # uc context validated.
11319 10:03:53.654817 # Handled SIG_TRIG
11320 10:03:53.664376 # SIG_OK -- SP:0xFFFFFB15CA90 si_addr@:0xfffffb15ca90 si_code:2 token@:(nil) offset:-281474894252688
11321 10:03:53.667320 # ==>> completed. PASS(1)
11322 10:03:53.673671 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11323 10:03:53.677321 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11324 10:03:53.684011 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11325 10:03:53.718978 # Registered handlers for all signals.
11326 10:03:53.719139 # Detected MINSTKSIGSZ:4720
11327 10:03:53.722223 # Testcase initialized.
11328 10:03:53.725686 # uc context validated.
11329 10:03:53.725801 # Handled SIG_TRIG
11330 10:03:53.735537 # SIG_OK -- SP:0xFFFFC8410B40 si_addr@:0xffffc8410b40 si_code:2 token@:(nil) offset:-281474041449280
11331 10:03:53.738924 # ==>> completed. PASS(1)
11332 10:03:53.746245 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11333 10:03:53.748639 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11334 10:03:53.755242 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11335 10:03:53.787724 # Registered handlers for all signals.
11336 10:03:53.787888 # Detected MINSTKSIGSZ:4720
11337 10:03:53.791007 # Testcase initialized.
11338 10:03:53.794959 # uc context validated.
11339 10:03:53.795062 # Handled SIG_TRIG
11340 10:03:53.804622 # SIG_OK -- SP:0xFFFFEA6FF040 si_addr@:0xffffea6ff040 si_code:2 token@:(nil) offset:-281474614947904
11341 10:03:53.807903 # ==>> completed. PASS(1)
11342 10:03:53.814384 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11343 10:03:53.817594 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11344 10:03:53.820861 # selftests: arm64: sme_trap_no_sm
11345 10:03:53.855466 # Registered handlers for all signals.
11346 10:03:53.855650 # Detected MINSTKSIGSZ:4720
11347 10:03:53.858793 # ==>> completed. SKIP.
11348 10:03:53.868891 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11349 10:03:53.871732 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11350 10:03:53.874839 # selftests: arm64: sme_trap_non_streaming
11351 10:03:53.923558 # Registered handlers for all signals.
11352 10:03:53.923710 # Detected MINSTKSIGSZ:4720
11353 10:03:53.926957 # ==>> completed. SKIP.
11354 10:03:53.936936 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11355 10:03:53.943391 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11356 10:03:53.947015 # selftests: arm64: sme_trap_za
11357 10:03:53.992908 # Registered handlers for all signals.
11358 10:03:53.993057 # Detected MINSTKSIGSZ:4720
11359 10:03:53.995667 # Testcase initialized.
11360 10:03:54.005510 # SIG_OK -- SP:0xFFFFC61CFA60 si_addr@:0xaaaacffc2510 si_code:1 token@:(nil) offset:-187650610570512
11361 10:03:54.005643 # ==>> completed. PASS(1)
11362 10:03:54.015692 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11363 10:03:54.018703 ok 21 selftests: arm64: sme_trap_za
11364 10:03:54.018789 # selftests: arm64: sme_vl
11365 10:03:54.063284 # Registered handlers for all signals.
11366 10:03:54.063432 # Detected MINSTKSIGSZ:4720
11367 10:03:54.065658 # ==>> completed. SKIP.
11368 10:03:54.072451 # # SME VL :: Check that we get the right SME VL reported
11369 10:03:54.075977 ok 22 selftests: arm64: sme_vl # SKIP
11370 10:03:54.078820 # selftests: arm64: ssve_regs
11371 10:03:54.131796 # Registered handlers for all signals.
11372 10:03:54.131962 # Detected MINSTKSIGSZ:4720
11373 10:03:54.134879 # ==>> completed. SKIP.
11374 10:03:54.141134 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11375 10:03:54.148027 ok 23 selftests: arm64: ssve_regs # SKIP
11376 10:03:54.148138 # selftests: arm64: sve_regs
11377 10:03:54.202275 # Registered handlers for all signals.
11378 10:03:54.202408 # Detected MINSTKSIGSZ:4720
11379 10:03:54.205809 # ==>> completed. SKIP.
11380 10:03:54.212189 # # SVE registers :: Check that we get the right SVE registers reported
11381 10:03:54.216362 ok 24 selftests: arm64: sve_regs # SKIP
11382 10:03:54.218611 # selftests: arm64: sve_vl
11383 10:03:54.273377 # Registered handlers for all signals.
11384 10:03:54.273521 # Detected MINSTKSIGSZ:4720
11385 10:03:54.277340 # ==>> completed. SKIP.
11386 10:03:54.282639 # # SVE VL :: Check that we get the right SVE VL reported
11387 10:03:54.286218 ok 25 selftests: arm64: sve_vl # SKIP
11388 10:03:54.289394 # selftests: arm64: za_no_regs
11389 10:03:54.342593 # Registered handlers for all signals.
11390 10:03:54.342733 # Detected MINSTKSIGSZ:4720
11391 10:03:54.345963 # ==>> completed. SKIP.
11392 10:03:54.352304 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11393 10:03:54.355578 ok 26 selftests: arm64: za_no_regs # SKIP
11394 10:03:54.358958 # selftests: arm64: za_regs
11395 10:03:54.414221 # Registered handlers for all signals.
11396 10:03:54.414367 # Detected MINSTKSIGSZ:4720
11397 10:03:54.417650 # ==>> completed. SKIP.
11398 10:03:54.423974 # # ZA register :: Check that we get the right ZA registers reported
11399 10:03:54.427346 ok 27 selftests: arm64: za_regs # SKIP
11400 10:03:54.430343 # selftests: arm64: pac
11401 10:03:54.483551 # TAP version 13
11402 10:03:54.483699 # 1..7
11403 10:03:54.486921 # # Starting 7 tests from 1 test cases.
11404 10:03:54.490221 # # RUN global.corrupt_pac ...
11405 10:03:54.493265 # # SKIP PAUTH not enabled
11406 10:03:54.496816 # # OK global.corrupt_pac
11407 10:03:54.500167 # ok 1 # SKIP PAUTH not enabled
11408 10:03:54.506432 # # RUN global.pac_instructions_not_nop ...
11409 10:03:54.509967 # # SKIP PAUTH not enabled
11410 10:03:54.513349 # # OK global.pac_instructions_not_nop
11411 10:03:54.516362 # ok 2 # SKIP PAUTH not enabled
11412 10:03:54.522928 # # RUN global.pac_instructions_not_nop_generic ...
11413 10:03:54.526636 # # SKIP Generic PAUTH not enabled
11414 10:03:54.529722 # # OK global.pac_instructions_not_nop_generic
11415 10:03:54.536008 # ok 3 # SKIP Generic PAUTH not enabled
11416 10:03:54.539244 # # RUN global.single_thread_different_keys ...
11417 10:03:54.542606 # # SKIP PAUTH not enabled
11418 10:03:54.549478 # # OK global.single_thread_different_keys
11419 10:03:54.549563 # ok 4 # SKIP PAUTH not enabled
11420 10:03:54.555809 # # RUN global.exec_changed_keys ...
11421 10:03:54.559030 # # SKIP PAUTH not enabled
11422 10:03:54.562550 # # OK global.exec_changed_keys
11423 10:03:54.565847 # ok 5 # SKIP PAUTH not enabled
11424 10:03:54.569078 # # RUN global.context_switch_keep_keys ...
11425 10:03:54.572501 # # SKIP PAUTH not enabled
11426 10:03:54.579233 # # OK global.context_switch_keep_keys
11427 10:03:54.579320 # ok 6 # SKIP PAUTH not enabled
11428 10:03:54.585979 # # RUN global.context_switch_keep_keys_generic ...
11429 10:03:54.588833 # # SKIP Generic PAUTH not enabled
11430 10:03:54.595475 # # OK global.context_switch_keep_keys_generic
11431 10:03:54.599819 # ok 7 # SKIP Generic PAUTH not enabled
11432 10:03:54.602360 # # PASSED: 7 / 7 tests passed.
11433 10:03:54.605367 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11434 10:03:54.608613 ok 28 selftests: arm64: pac
11435 10:03:54.611991 # selftests: arm64: fp-stress
11436 10:04:00.797330 <6>[ 46.154297] vpu: disabling
11437 10:04:00.800819 <6>[ 46.157360] vproc2: disabling
11438 10:04:00.804003 <6>[ 46.160641] vproc1: disabling
11439 10:04:00.807198 <6>[ 46.163926] vaud18: disabling
11440 10:04:00.813932 <6>[ 46.167410] vsram_others: disabling
11441 10:04:00.817735 <6>[ 46.171343] va09: disabling
11442 10:04:00.820359 <6>[ 46.174478] vsram_md: disabling
11443 10:04:00.823792 <6>[ 46.178000] Vgpu: disabling
11444 10:04:04.564415 # TAP version 13
11445 10:04:04.564589 # 1..16
11446 10:04:04.567377 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11447 10:04:04.570437 # # Will run for 10s
11448 10:04:04.570523 # # Started FPSIMD-0-0
11449 10:04:04.573724 # # Started FPSIMD-0-1
11450 10:04:04.577550 # # Started FPSIMD-1-0
11451 10:04:04.577639 # # Started FPSIMD-1-1
11452 10:04:04.580710 # # Started FPSIMD-2-0
11453 10:04:04.583995 # # Started FPSIMD-2-1
11454 10:04:04.584147 # # Started FPSIMD-3-0
11455 10:04:04.587488 # # Started FPSIMD-3-1
11456 10:04:04.587621 # # Started FPSIMD-4-0
11457 10:04:04.590241 # # Started FPSIMD-4-1
11458 10:04:04.593839 # # Started FPSIMD-5-0
11459 10:04:04.593925 # # Started FPSIMD-5-1
11460 10:04:04.597074 # # Started FPSIMD-6-0
11461 10:04:04.600650 # # Started FPSIMD-6-1
11462 10:04:04.600768 # # Started FPSIMD-7-0
11463 10:04:04.603782 # # Started FPSIMD-7-1
11464 10:04:04.606901 # # FPSIMD-1-0: Vector length: 128 bits
11465 10:04:04.610100 # # FPSIMD-1-0: PID: 1126
11466 10:04:04.613338 # # FPSIMD-0-1: Vector length: 128 bits
11467 10:04:04.613415 # # FPSIMD-0-1: PID: 1125
11468 10:04:04.620138 # # FPSIMD-1-1: Vector length: 128 bits
11469 10:04:04.620239 # # FPSIMD-1-1: PID: 1127
11470 10:04:04.623660 # # FPSIMD-0-0: Vector length: 128 bits
11471 10:04:04.626819 # # FPSIMD-0-0: PID: 1124
11472 10:04:04.629793 # # FPSIMD-3-0: Vector length: 128 bits
11473 10:04:04.633705 # # FPSIMD-3-0: PID: 1130
11474 10:04:04.636688 # # FPSIMD-2-0: Vector length: 128 bits
11475 10:04:04.639610 # # FPSIMD-2-0: PID: 1128
11476 10:04:04.643214 # # FPSIMD-5-0: Vector length: 128 bits
11477 10:04:04.643301 # # FPSIMD-5-0: PID: 1134
11478 10:04:04.649881 # # FPSIMD-4-0: Vector length: 128 bits
11479 10:04:04.649997 # # FPSIMD-4-0: PID: 1132
11480 10:04:04.653006 # # FPSIMD-4-1: Vector length: 128 bits
11481 10:04:04.656299 # # FPSIMD-4-1: PID: 1133
11482 10:04:04.659832 # # FPSIMD-3-1: Vector length: 128 bits
11483 10:04:04.662988 # # FPSIMD-3-1: PID: 1131
11484 10:04:04.666368 # # FPSIMD-2-1: Vector length: 128 bits
11485 10:04:04.669450 # # FPSIMD-2-1: PID: 1129
11486 10:04:04.672638 # # FPSIMD-6-1: Vector length: 128 bits
11487 10:04:04.672723 # # FPSIMD-6-1: PID: 1137
11488 10:04:04.675940 # # FPSIMD-7-0: Vector length: 128 bits
11489 10:04:04.679968 # # FPSIMD-7-0: PID: 1138
11490 10:04:04.682443 # # FPSIMD-5-1: Vector length: 128 bits
11491 10:04:04.686388 # # FPSIMD-5-1: PID: 1135
11492 10:04:04.689585 # # FPSIMD-7-1: Vector length: 128 bits
11493 10:04:04.692876 # # FPSIMD-7-1: PID: 1139
11494 10:04:04.695705 # # FPSIMD-6-0: Vector length: 128 bits
11495 10:04:04.699439 # # FPSIMD-6-0: PID: 1136
11496 10:04:04.699519 # # Finishing up...
11497 10:04:04.705959 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=791128, signals=10
11498 10:04:04.712568 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=361417, signals=10
11499 10:04:04.722641 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1032463, signals=10
11500 10:04:04.729033 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=838055, signals=10
11501 10:04:04.735481 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=573872, signals=10
11502 10:04:04.742476 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=362231, signals=10
11503 10:04:04.748773 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=817941, signals=10
11504 10:04:04.752650 # ok 1 FPSIMD-0-0
11505 10:04:04.752778 # ok 2 FPSIMD-0-1
11506 10:04:04.755558 # ok 3 FPSIMD-1-0
11507 10:04:04.755662 # ok 4 FPSIMD-1-1
11508 10:04:04.758730 # ok 5 FPSIMD-2-0
11509 10:04:04.758841 # ok 6 FPSIMD-2-1
11510 10:04:04.761924 # ok 7 FPSIMD-3-0
11511 10:04:04.762010 # ok 8 FPSIMD-3-1
11512 10:04:04.765487 # ok 9 FPSIMD-4-0
11513 10:04:04.765574 # ok 10 FPSIMD-4-1
11514 10:04:04.768783 # ok 11 FPSIMD-5-0
11515 10:04:04.768868 # ok 12 FPSIMD-5-1
11516 10:04:04.771816 # ok 13 FPSIMD-6-0
11517 10:04:04.771901 # ok 14 FPSIMD-6-1
11518 10:04:04.775322 # ok 15 FPSIMD-7-0
11519 10:04:04.775407 # ok 16 FPSIMD-7-1
11520 10:04:04.784859 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1138084, signals=9
11521 10:04:04.791357 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1136830, signals=10
11522 10:04:04.798109 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=341197, signals=10
11523 10:04:04.804826 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=783800, signals=10
11524 10:04:04.811923 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=769766, signals=10
11525 10:04:04.817979 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=717389, signals=9
11526 10:04:04.827948 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=583719, signals=10
11527 10:04:04.834376 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1340877, signals=10
11528 10:04:04.841175 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1177838, signals=9
11529 10:04:04.844696 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11530 10:04:04.847764 ok 29 selftests: arm64: fp-stress
11531 10:04:04.851343 # selftests: arm64: sve-ptrace
11532 10:04:04.854448 # TAP version 13
11533 10:04:04.854537 # 1..4104
11534 10:04:04.858828 # ok 2 # SKIP SVE not available
11535 10:04:04.860914 # # Planned tests != run tests (4104 != 1)
11536 10:04:04.864453 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11537 10:04:04.870933 ok 30 selftests: arm64: sve-ptrace # SKIP
11538 10:04:04.871041 # selftests: arm64: sve-probe-vls
11539 10:04:04.874278 # TAP version 13
11540 10:04:04.874367 # 1..2
11541 10:04:04.877595 # ok 2 # SKIP SVE not available
11542 10:04:04.881192 # # Planned tests != run tests (2 != 1)
11543 10:04:04.887459 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11544 10:04:04.891506 ok 31 selftests: arm64: sve-probe-vls # SKIP
11545 10:04:04.894112 # selftests: arm64: vec-syscfg
11546 10:04:04.894226 # TAP version 13
11547 10:04:04.894319 # 1..20
11548 10:04:04.897170 # ok 1 # SKIP SVE not supported
11549 10:04:04.901851 # ok 2 # SKIP SVE not supported
11550 10:04:04.903931 # ok 3 # SKIP SVE not supported
11551 10:04:04.906924 # ok 4 # SKIP SVE not supported
11552 10:04:04.910298 # ok 5 # SKIP SVE not supported
11553 10:04:04.914520 # ok 6 # SKIP SVE not supported
11554 10:04:04.914639 # ok 7 # SKIP SVE not supported
11555 10:04:04.917014 # ok 8 # SKIP SVE not supported
11556 10:04:04.920179 # ok 9 # SKIP SVE not supported
11557 10:04:04.923721 # ok 10 # SKIP SVE not supported
11558 10:04:04.927465 # ok 11 # SKIP SME not supported
11559 10:04:04.931326 # ok 12 # SKIP SME not supported
11560 10:04:04.933985 # ok 13 # SKIP SME not supported
11561 10:04:04.937113 # ok 14 # SKIP SME not supported
11562 10:04:04.940640 # ok 15 # SKIP SME not supported
11563 10:04:04.940727 # ok 16 # SKIP SME not supported
11564 10:04:04.943874 # ok 17 # SKIP SME not supported
11565 10:04:04.947093 # ok 18 # SKIP SME not supported
11566 10:04:04.950640 # ok 19 # SKIP SME not supported
11567 10:04:04.953741 # ok 20 # SKIP SME not supported
11568 10:04:04.960297 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11569 10:04:04.960403 ok 32 selftests: arm64: vec-syscfg
11570 10:04:04.963315 # selftests: arm64: za-fork
11571 10:04:04.966590 # TAP version 13
11572 10:04:04.966682 # 1..1
11573 10:04:04.966747 # # PID: 1209
11574 10:04:04.970192 # # SME support not present
11575 10:04:04.973379 # ok 0 skipped
11576 10:04:04.977024 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11577 10:04:04.979761 ok 33 selftests: arm64: za-fork
11578 10:04:04.983126 # selftests: arm64: za-ptrace
11579 10:04:04.983237 # TAP version 13
11580 10:04:04.983328 # 1..1
11581 10:04:04.986491 # ok 2 # SKIP SME not available
11582 10:04:04.993312 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11583 10:04:04.996689 ok 34 selftests: arm64: za-ptrace # SKIP
11584 10:04:04.999486 # selftests: arm64: check_buffer_fill
11585 10:04:05.022570 # # SKIP: MTE features unavailable
11586 10:04:05.029526 ok 35 selftests: arm64: check_buffer_fill # SKIP
11587 10:04:05.046466 # selftests: arm64: check_child_memory
11588 10:04:05.094758 # # SKIP: MTE features unavailable
11589 10:04:05.100990 ok 36 selftests: arm64: check_child_memory # SKIP
11590 10:04:05.116123 # selftests: arm64: check_gcr_el1_cswitch
11591 10:04:05.166268 # # SKIP: MTE features unavailable
11592 10:04:05.172898 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11593 10:04:05.186006 # selftests: arm64: check_ksm_options
11594 10:04:05.240085 # # SKIP: MTE features unavailable
11595 10:04:05.247186 ok 38 selftests: arm64: check_ksm_options # SKIP
11596 10:04:05.263906 # selftests: arm64: check_mmap_options
11597 10:04:05.315667 # # SKIP: MTE features unavailable
11598 10:04:05.321308 ok 39 selftests: arm64: check_mmap_options # SKIP
11599 10:04:05.335282 # selftests: arm64: check_prctl
11600 10:04:05.391490 # TAP version 13
11601 10:04:05.391646 # 1..5
11602 10:04:05.394473 # ok 1 check_basic_read
11603 10:04:05.394560 # ok 2 NONE
11604 10:04:05.398040 # ok 3 # SKIP SYNC
11605 10:04:05.398128 # ok 4 # SKIP ASYNC
11606 10:04:05.401113 # ok 5 # SKIP SYNC+ASYNC
11607 10:04:05.404488 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11608 10:04:05.408014 ok 40 selftests: arm64: check_prctl
11609 10:04:05.414215 # selftests: arm64: check_tags_inclusion
11610 10:04:05.460960 # # SKIP: MTE features unavailable
11611 10:04:05.467545 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11612 10:04:05.480320 # selftests: arm64: check_user_mem
11613 10:04:05.532096 # # SKIP: MTE features unavailable
11614 10:04:05.538800 ok 42 selftests: arm64: check_user_mem # SKIP
11615 10:04:05.552073 # selftests: arm64: btitest
11616 10:04:05.604672 # TAP version 13
11617 10:04:05.604827 # 1..18
11618 10:04:05.608026 # # HWCAP_PACA not present
11619 10:04:05.611825 # # HWCAP2_BTI not present
11620 10:04:05.611919 # # Test binary built for BTI
11621 10:04:05.618301 # ok 1 nohint_func/call_using_br_x0 # SKIP
11622 10:04:05.621515 # ok 1 nohint_func/call_using_br_x16 # SKIP
11623 10:04:05.624637 # ok 1 nohint_func/call_using_blr # SKIP
11624 10:04:05.628185 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11625 10:04:05.631047 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11626 10:04:05.637529 # ok 1 bti_none_func/call_using_blr # SKIP
11627 10:04:05.641146 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11628 10:04:05.644204 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11629 10:04:05.647795 # ok 1 bti_c_func/call_using_blr # SKIP
11630 10:04:05.650942 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11631 10:04:05.654040 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11632 10:04:05.657524 # ok 1 bti_j_func/call_using_blr # SKIP
11633 10:04:05.661479 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11634 10:04:05.667782 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11635 10:04:05.671250 # ok 1 bti_jc_func/call_using_blr # SKIP
11636 10:04:05.674189 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11637 10:04:05.677660 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11638 10:04:05.680871 # ok 1 paciasp_func/call_using_blr # SKIP
11639 10:04:05.687555 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11640 10:04:05.690817 # # WARNING - EXPECTED TEST COUNT WRONG
11641 10:04:05.693948 ok 43 selftests: arm64: btitest
11642 10:04:05.697510 # selftests: arm64: nobtitest
11643 10:04:05.697600 # TAP version 13
11644 10:04:05.697665 # 1..18
11645 10:04:05.700631 # # HWCAP_PACA not present
11646 10:04:05.704269 # # HWCAP2_BTI not present
11647 10:04:05.707054 # # Test binary not built for BTI
11648 10:04:05.710712 # ok 1 nohint_func/call_using_br_x0 # SKIP
11649 10:04:05.713748 # ok 1 nohint_func/call_using_br_x16 # SKIP
11650 10:04:05.717517 # ok 1 nohint_func/call_using_blr # SKIP
11651 10:04:05.720529 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11652 10:04:05.727462 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11653 10:04:05.730860 # ok 1 bti_none_func/call_using_blr # SKIP
11654 10:04:05.734519 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11655 10:04:05.736929 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11656 10:04:05.740210 # ok 1 bti_c_func/call_using_blr # SKIP
11657 10:04:05.743876 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11658 10:04:05.746518 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11659 10:04:05.750046 # ok 1 bti_j_func/call_using_blr # SKIP
11660 10:04:05.756650 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11661 10:04:05.760392 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11662 10:04:05.763225 # ok 1 bti_jc_func/call_using_blr # SKIP
11663 10:04:05.766685 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11664 10:04:05.770179 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11665 10:04:05.773166 # ok 1 paciasp_func/call_using_blr # SKIP
11666 10:04:05.779543 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11667 10:04:05.783172 # # WARNING - EXPECTED TEST COUNT WRONG
11668 10:04:05.786289 ok 44 selftests: arm64: nobtitest
11669 10:04:05.789442 # selftests: arm64: hwcap
11670 10:04:05.789530 # TAP version 13
11671 10:04:05.789594 # 1..28
11672 10:04:05.793360 # ok 1 cpuinfo_match_RNG
11673 10:04:05.796804 # # SIGILL reported for RNG
11674 10:04:05.796890 # ok 2 # SKIP sigill_RNG
11675 10:04:05.799764 # ok 3 cpuinfo_match_SME
11676 10:04:05.803056 # ok 4 sigill_SME
11677 10:04:05.803138 # ok 5 cpuinfo_match_SVE
11678 10:04:05.806524 # ok 6 sigill_SVE
11679 10:04:05.809789 # ok 7 cpuinfo_match_SVE 2
11680 10:04:05.809874 # # SIGILL reported for SVE 2
11681 10:04:05.812453 # ok 8 # SKIP sigill_SVE 2
11682 10:04:05.815797 # ok 9 cpuinfo_match_SVE AES
11683 10:04:05.819026 # # SIGILL reported for SVE AES
11684 10:04:05.822819 # ok 10 # SKIP sigill_SVE AES
11685 10:04:05.825590 # ok 11 cpuinfo_match_SVE2 PMULL
11686 10:04:05.825676 # # SIGILL reported for SVE2 PMULL
11687 10:04:05.828818 # ok 12 # SKIP sigill_SVE2 PMULL
11688 10:04:05.832204 # ok 13 cpuinfo_match_SVE2 BITPERM
11689 10:04:05.835449 # # SIGILL reported for SVE2 BITPERM
11690 10:04:05.838924 # ok 14 # SKIP sigill_SVE2 BITPERM
11691 10:04:05.842082 # ok 15 cpuinfo_match_SVE2 SHA3
11692 10:04:05.845220 # # SIGILL reported for SVE2 SHA3
11693 10:04:05.848427 # ok 16 # SKIP sigill_SVE2 SHA3
11694 10:04:05.852147 # ok 17 cpuinfo_match_SVE2 SM4
11695 10:04:05.855358 # # SIGILL reported for SVE2 SM4
11696 10:04:05.858673 # ok 18 # SKIP sigill_SVE2 SM4
11697 10:04:05.858762 # ok 19 cpuinfo_match_SVE2 I8MM
11698 10:04:05.861824 # # SIGILL reported for SVE2 I8MM
11699 10:04:05.864816 # ok 20 # SKIP sigill_SVE2 I8MM
11700 10:04:05.868456 # ok 21 cpuinfo_match_SVE2 F32MM
11701 10:04:05.871771 # # SIGILL reported for SVE2 F32MM
11702 10:04:05.875024 # ok 22 # SKIP sigill_SVE2 F32MM
11703 10:04:05.878498 # ok 23 cpuinfo_match_SVE2 F64MM
11704 10:04:05.881645 # # SIGILL reported for SVE2 F64MM
11705 10:04:05.885226 # ok 24 # SKIP sigill_SVE2 F64MM
11706 10:04:05.888542 # ok 25 cpuinfo_match_SVE2 BF16
11707 10:04:05.891749 # # SIGILL reported for SVE2 BF16
11708 10:04:05.891838 # ok 26 # SKIP sigill_SVE2 BF16
11709 10:04:05.895155 # ok 27 cpuinfo_match_SVE2 EBF16
11710 10:04:05.898651 # ok 28 # SKIP sigill_SVE2 EBF16
11711 10:04:05.904824 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11712 10:04:05.908587 ok 45 selftests: arm64: hwcap
11713 10:04:05.908678 # selftests: arm64: ptrace
11714 10:04:05.910970 # TAP version 13
11715 10:04:05.911051 # 1..7
11716 10:04:05.914595 # # Parent is 1438, child is 1439
11717 10:04:05.918105 # ok 1 read_tpidr_one
11718 10:04:05.918192 # ok 2 write_tpidr_one
11719 10:04:05.920931 # ok 3 verify_tpidr_one
11720 10:04:05.921025 # ok 4 count_tpidrs
11721 10:04:05.924595 # ok 5 tpidr2_write
11722 10:04:05.924678 # ok 6 tpidr2_read
11723 10:04:05.927702 # ok 7 write_tpidr_only
11724 10:04:05.934371 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11725 10:04:05.934473 ok 46 selftests: arm64: ptrace
11726 10:04:05.937899 # selftests: arm64: syscall-abi
11727 10:04:05.942198 # TAP version 13
11728 10:04:05.942288 # 1..2
11729 10:04:05.944430 # ok 1 getpid() FPSIMD
11730 10:04:05.944513 # ok 2 sched_yield() FPSIMD
11731 10:04:05.950822 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11732 10:04:05.954031 ok 47 selftests: arm64: syscall-abi
11733 10:04:05.957557 # selftests: arm64: tpidr2
11734 10:04:05.969699 # TAP version 13
11735 10:04:05.969844 # 1..5
11736 10:04:05.973731 # # PID: 1473
11737 10:04:05.973821 # # SME support not present
11738 10:04:05.975620 # ok 0 skipped, TPIDR2 not supported
11739 10:04:05.979250 # ok 1 skipped, TPIDR2 not supported
11740 10:04:05.982260 # ok 2 skipped, TPIDR2 not supported
11741 10:04:05.985610 # ok 3 skipped, TPIDR2 not supported
11742 10:04:05.988875 # ok 4 skipped, TPIDR2 not supported
11743 10:04:05.995734 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11744 10:04:05.999537 ok 48 selftests: arm64: tpidr2
11745 10:04:06.618078 arm64_tags_test pass
11746 10:04:06.621317 arm64_run_tags_test_sh pass
11747 10:04:06.624824 arm64_fake_sigreturn_bad_magic pass
11748 10:04:06.627952 arm64_fake_sigreturn_bad_size pass
11749 10:04:06.631670 arm64_fake_sigreturn_bad_size_for_magic0 pass
11750 10:04:06.635108 arm64_fake_sigreturn_duplicated_fpsimd pass
11751 10:04:06.638851 arm64_fake_sigreturn_misaligned_sp pass
11752 10:04:06.641467 arm64_fake_sigreturn_missing_fpsimd pass
11753 10:04:06.644463 arm64_fake_sigreturn_sme_change_vl skip
11754 10:04:06.650905 arm64_fake_sigreturn_sve_change_vl skip
11755 10:04:06.654943 arm64_mangle_pstate_invalid_compat_toggle pass
11756 10:04:06.657727 arm64_mangle_pstate_invalid_daif_bits pass
11757 10:04:06.660848 arm64_mangle_pstate_invalid_mode_el1h pass
11758 10:04:06.664598 arm64_mangle_pstate_invalid_mode_el1t pass
11759 10:04:06.667271 arm64_mangle_pstate_invalid_mode_el2h pass
11760 10:04:06.673846 arm64_mangle_pstate_invalid_mode_el2t pass
11761 10:04:06.677552 arm64_mangle_pstate_invalid_mode_el3h pass
11762 10:04:06.680801 arm64_mangle_pstate_invalid_mode_el3t pass
11763 10:04:06.684229 arm64_sme_trap_no_sm skip
11764 10:04:06.687298 arm64_sme_trap_non_streaming skip
11765 10:04:06.687378 arm64_sme_trap_za pass
11766 10:04:06.690707 arm64_sme_vl skip
11767 10:04:06.690788 arm64_ssve_regs skip
11768 10:04:06.693922 arm64_sve_regs skip
11769 10:04:06.694002 arm64_sve_vl skip
11770 10:04:06.697178 arm64_za_no_regs skip
11771 10:04:06.697257 arm64_za_regs skip
11772 10:04:06.700313 arm64_pac_PAUTH_not_enabled skip
11773 10:04:06.703868 arm64_pac_PAUTH_not_enabled skip
11774 10:04:06.707087 arm64_pac_Generic_PAUTH_not_enabled skip
11775 10:04:06.710713 arm64_pac_PAUTH_not_enabled skip
11776 10:04:06.713785 arm64_pac_PAUTH_not_enabled skip
11777 10:04:06.717265 arm64_pac_PAUTH_not_enabled skip
11778 10:04:06.720341 arm64_pac_Generic_PAUTH_not_enabled skip
11779 10:04:06.723417 arm64_pac pass
11780 10:04:06.723497 arm64_fp-stress_FPSIMD-0-0 pass
11781 10:04:06.727582 arm64_fp-stress_FPSIMD-0-1 pass
11782 10:04:06.729995 arm64_fp-stress_FPSIMD-1-0 pass
11783 10:04:06.733860 arm64_fp-stress_FPSIMD-1-1 pass
11784 10:04:06.736929 arm64_fp-stress_FPSIMD-2-0 pass
11785 10:04:06.740185 arm64_fp-stress_FPSIMD-2-1 pass
11786 10:04:06.743514 arm64_fp-stress_FPSIMD-3-0 pass
11787 10:04:06.743593 arm64_fp-stress_FPSIMD-3-1 pass
11788 10:04:06.746584 arm64_fp-stress_FPSIMD-4-0 pass
11789 10:04:06.750143 arm64_fp-stress_FPSIMD-4-1 pass
11790 10:04:06.753128 arm64_fp-stress_FPSIMD-5-0 pass
11791 10:04:06.756353 arm64_fp-stress_FPSIMD-5-1 pass
11792 10:04:06.760222 arm64_fp-stress_FPSIMD-6-0 pass
11793 10:04:06.762976 arm64_fp-stress_FPSIMD-6-1 pass
11794 10:04:06.766630 arm64_fp-stress_FPSIMD-7-0 pass
11795 10:04:06.766710 arm64_fp-stress_FPSIMD-7-1 pass
11796 10:04:06.770214 arm64_fp-stress pass
11797 10:04:06.772969 arm64_sve-ptrace_SVE_not_available skip
11798 10:04:06.776241 arm64_sve-ptrace skip
11799 10:04:06.779361 arm64_sve-probe-vls_SVE_not_available skip
11800 10:04:06.783011 arm64_sve-probe-vls skip
11801 10:04:06.786364 arm64_vec-syscfg_SVE_not_supported skip
11802 10:04:06.789414 arm64_vec-syscfg_SVE_not_supported skip
11803 10:04:06.792444 arm64_vec-syscfg_SVE_not_supported skip
11804 10:04:06.796301 arm64_vec-syscfg_SVE_not_supported skip
11805 10:04:06.799858 arm64_vec-syscfg_SVE_not_supported skip
11806 10:04:06.802578 arm64_vec-syscfg_SVE_not_supported skip
11807 10:04:06.805665 arm64_vec-syscfg_SVE_not_supported skip
11808 10:04:06.809461 arm64_vec-syscfg_SVE_not_supported skip
11809 10:04:06.812281 arm64_vec-syscfg_SVE_not_supported skip
11810 10:04:06.815477 arm64_vec-syscfg_SVE_not_supported skip
11811 10:04:06.819201 arm64_vec-syscfg_SME_not_supported skip
11812 10:04:06.826328 arm64_vec-syscfg_SME_not_supported skip
11813 10:04:06.828820 arm64_vec-syscfg_SME_not_supported skip
11814 10:04:06.832760 arm64_vec-syscfg_SME_not_supported skip
11815 10:04:06.835407 arm64_vec-syscfg_SME_not_supported skip
11816 10:04:06.839881 arm64_vec-syscfg_SME_not_supported skip
11817 10:04:06.842383 arm64_vec-syscfg_SME_not_supported skip
11818 10:04:06.845999 arm64_vec-syscfg_SME_not_supported skip
11819 10:04:06.849014 arm64_vec-syscfg_SME_not_supported skip
11820 10:04:06.852148 arm64_vec-syscfg_SME_not_supported skip
11821 10:04:06.855243 arm64_vec-syscfg pass
11822 10:04:06.855323 arm64_za-fork_skipped pass
11823 10:04:06.858918 arm64_za-fork pass
11824 10:04:06.861855 arm64_za-ptrace_SME_not_available skip
11825 10:04:06.865030 arm64_za-ptrace skip
11826 10:04:06.865109 arm64_check_buffer_fill skip
11827 10:04:06.868535 arm64_check_child_memory skip
11828 10:04:06.872160 arm64_check_gcr_el1_cswitch skip
11829 10:04:06.875469 arm64_check_ksm_options skip
11830 10:04:06.878948 arm64_check_mmap_options skip
11831 10:04:06.882016 arm64_check_prctl_check_basic_read pass
11832 10:04:06.885059 arm64_check_prctl_NONE pass
11833 10:04:06.885138 arm64_check_prctl_SYNC skip
11834 10:04:06.888577 arm64_check_prctl_ASYNC skip
11835 10:04:06.892112 arm64_check_prctl_SYNC_ASYNC skip
11836 10:04:06.894986 arm64_check_prctl pass
11837 10:04:06.898396 arm64_check_tags_inclusion skip
11838 10:04:06.898474 arm64_check_user_mem skip
11839 10:04:06.904767 arm64_btitest_nohint_func_call_using_br_x0 skip
11840 10:04:06.908906 arm64_btitest_nohint_func_call_using_br_x16 skip
11841 10:04:06.911880 arm64_btitest_nohint_func_call_using_blr skip
11842 10:04:06.914956 arm64_btitest_bti_none_func_call_using_br_x0 skip
11843 10:04:06.921594 arm64_btitest_bti_none_func_call_using_br_x16 skip
11844 10:04:06.925089 arm64_btitest_bti_none_func_call_using_blr skip
11845 10:04:06.927713 arm64_btitest_bti_c_func_call_using_br_x0 skip
11846 10:04:06.934812 arm64_btitest_bti_c_func_call_using_br_x16 skip
11847 10:04:06.938388 arm64_btitest_bti_c_func_call_using_blr skip
11848 10:04:06.941151 arm64_btitest_bti_j_func_call_using_br_x0 skip
11849 10:04:06.944878 arm64_btitest_bti_j_func_call_using_br_x16 skip
11850 10:04:06.951757 arm64_btitest_bti_j_func_call_using_blr skip
11851 10:04:06.954470 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11852 10:04:06.957522 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11853 10:04:06.961261 arm64_btitest_bti_jc_func_call_using_blr skip
11854 10:04:06.967375 arm64_btitest_paciasp_func_call_using_br_x0 skip
11855 10:04:06.970876 arm64_btitest_paciasp_func_call_using_br_x16 skip
11856 10:04:06.974739 arm64_btitest_paciasp_func_call_using_blr skip
11857 10:04:06.977758 arm64_btitest pass
11858 10:04:06.980689 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11859 10:04:06.987192 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11860 10:04:06.990556 arm64_nobtitest_nohint_func_call_using_blr skip
11861 10:04:06.993976 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11862 10:04:07.000713 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11863 10:04:07.003941 arm64_nobtitest_bti_none_func_call_using_blr skip
11864 10:04:07.006918 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11865 10:04:07.013857 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11866 10:04:07.017129 arm64_nobtitest_bti_c_func_call_using_blr skip
11867 10:04:07.020531 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11868 10:04:07.027191 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11869 10:04:07.030507 arm64_nobtitest_bti_j_func_call_using_blr skip
11870 10:04:07.036850 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11871 10:04:07.040529 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11872 10:04:07.043440 arm64_nobtitest_bti_jc_func_call_using_blr skip
11873 10:04:07.050510 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11874 10:04:07.054201 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11875 10:04:07.057072 arm64_nobtitest_paciasp_func_call_using_blr skip
11876 10:04:07.059848 arm64_nobtitest pass
11877 10:04:07.063093 arm64_hwcap_cpuinfo_match_RNG pass
11878 10:04:07.066770 arm64_hwcap_sigill_RNG skip
11879 10:04:07.066851 arm64_hwcap_cpuinfo_match_SME pass
11880 10:04:07.069928 arm64_hwcap_sigill_SME pass
11881 10:04:07.073362 arm64_hwcap_cpuinfo_match_SVE pass
11882 10:04:07.076392 arm64_hwcap_sigill_SVE pass
11883 10:04:07.079895 arm64_hwcap_cpuinfo_match_SVE_2 pass
11884 10:04:07.083495 arm64_hwcap_sigill_SVE_2 skip
11885 10:04:07.086365 arm64_hwcap_cpuinfo_match_SVE_AES pass
11886 10:04:07.089494 arm64_hwcap_sigill_SVE_AES skip
11887 10:04:07.092890 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11888 10:04:07.096204 arm64_hwcap_sigill_SVE2_PMULL skip
11889 10:04:07.099313 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11890 10:04:07.103022 arm64_hwcap_sigill_SVE2_BITPERM skip
11891 10:04:07.106004 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11892 10:04:07.109799 arm64_hwcap_sigill_SVE2_SHA3 skip
11893 10:04:07.112820 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11894 10:04:07.116066 arm64_hwcap_sigill_SVE2_SM4 skip
11895 10:04:07.119469 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11896 10:04:07.123432 arm64_hwcap_sigill_SVE2_I8MM skip
11897 10:04:07.125706 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11898 10:04:07.129759 arm64_hwcap_sigill_SVE2_F32MM skip
11899 10:04:07.132563 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11900 10:04:07.136046 arm64_hwcap_sigill_SVE2_F64MM skip
11901 10:04:07.138878 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11902 10:04:07.142483 arm64_hwcap_sigill_SVE2_BF16 skip
11903 10:04:07.145478 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11904 10:04:07.149073 arm64_hwcap_sigill_SVE2_EBF16 skip
11905 10:04:07.152851 arm64_hwcap pass
11906 10:04:07.155569 arm64_ptrace_read_tpidr_one pass
11907 10:04:07.158603 arm64_ptrace_write_tpidr_one pass
11908 10:04:07.158685 arm64_ptrace_verify_tpidr_one pass
11909 10:04:07.162312 arm64_ptrace_count_tpidrs pass
11910 10:04:07.165680 arm64_ptrace_tpidr2_write pass
11911 10:04:07.168855 arm64_ptrace_tpidr2_read pass
11912 10:04:07.172164 arm64_ptrace_write_tpidr_only pass
11913 10:04:07.172245 arm64_ptrace pass
11914 10:04:07.175257 arm64_syscall-abi_getpid_FPSIMD pass
11915 10:04:07.182005 arm64_syscall-abi_sched_yield_FPSIMD pass
11916 10:04:07.182096 arm64_syscall-abi pass
11917 10:04:07.185495 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11918 10:04:07.191976 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11919 10:04:07.195930 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11920 10:04:07.198646 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11921 10:04:07.202202 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11922 10:04:07.205118 arm64_tpidr2 pass
11923 10:04:07.208482 + ../../utils/send-to-lava.sh ./output/result.txt
11924 10:04:07.214991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11925 10:04:07.215271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11927 10:04:07.221759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11928 10:04:07.222020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11930 10:04:07.228761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11931 10:04:07.229016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11933 10:04:07.234819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11934 10:04:07.235070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11936 10:04:07.284692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11937 10:04:07.285016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11939 10:04:07.344333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11940 10:04:07.344656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11942 10:04:07.397900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11943 10:04:07.398223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11945 10:04:07.451024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11946 10:04:07.451350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11948 10:04:07.505570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11949 10:04:07.505894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11951 10:04:07.556306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11952 10:04:07.556667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
11954 10:04:07.607240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
11955 10:04:07.607563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
11957 10:04:07.657360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
11958 10:04:07.657678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
11960 10:04:07.710572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
11961 10:04:07.710892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
11963 10:04:07.762856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
11964 10:04:07.763177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
11966 10:04:07.818542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
11967 10:04:07.818861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
11969 10:04:07.875677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
11970 10:04:07.875996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
11972 10:04:07.930810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
11973 10:04:07.931138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
11975 10:04:07.979996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
11976 10:04:07.980361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
11978 10:04:08.029626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
11979 10:04:08.029948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
11981 10:04:08.083167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
11983 10:04:08.086512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
11984 10:04:08.130640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
11985 10:04:08.130964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
11987 10:04:08.179784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
11988 10:04:08.180110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
11990 10:04:08.234692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
11991 10:04:08.235015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
11993 10:04:08.290592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
11994 10:04:08.290913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
11996 10:04:08.341167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
11997 10:04:08.341488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
11999 10:04:08.393378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12000 10:04:08.393698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12002 10:04:08.454450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12003 10:04:08.454766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12005 10:04:08.514197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12007 10:04:08.517033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12008 10:04:08.573454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12010 10:04:08.576715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12011 10:04:08.634866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12012 10:04:08.635174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12014 10:04:08.693329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12016 10:04:08.696262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12017 10:04:08.755512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12019 10:04:08.758235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12020 10:04:08.812566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12022 10:04:08.816358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12023 10:04:08.874485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12024 10:04:08.874805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12026 10:04:08.929843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12027 10:04:08.930154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12029 10:04:08.991238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12030 10:04:08.991555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12032 10:04:09.047422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12033 10:04:09.047739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12035 10:04:09.111182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12036 10:04:09.111533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12038 10:04:09.171988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12039 10:04:09.172352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12041 10:04:09.229431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12043 10:04:09.232458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12044 10:04:09.289482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12045 10:04:09.289806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12047 10:04:09.347659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12048 10:04:09.347980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12050 10:04:09.413752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12051 10:04:09.414099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12053 10:04:09.477306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12054 10:04:09.477629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12056 10:04:09.532571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12057 10:04:09.532896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12059 10:04:09.583428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12060 10:04:09.583748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12062 10:04:09.644203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12063 10:04:09.644524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12065 10:04:09.711570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12066 10:04:09.711894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12068 10:04:09.772605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12069 10:04:09.772928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12071 10:04:09.835142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12072 10:04:09.835465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12074 10:04:09.899853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12075 10:04:09.900175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12077 10:04:09.959998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12078 10:04:09.960355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12080 10:04:10.014653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12081 10:04:10.014971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12083 10:04:10.069632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12084 10:04:10.069956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12086 10:04:10.134627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12087 10:04:10.134952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12089 10:04:10.197239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12090 10:04:10.197561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12092 10:04:10.248431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12093 10:04:10.248742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12095 10:04:10.302933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12096 10:04:10.303261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12098 10:04:10.350864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12099 10:04:10.351174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12101 10:04:10.409150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12102 10:04:10.409478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12104 10:04:10.458620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12105 10:04:10.458967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12107 10:04:10.513460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12108 10:04:10.513783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12110 10:04:10.562997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12111 10:04:10.563321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12113 10:04:10.615641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12114 10:04:10.615962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12116 10:04:10.663654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12117 10:04:10.663976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12119 10:04:10.718301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12120 10:04:10.718591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12122 10:04:10.768692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12123 10:04:10.768976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12125 10:04:10.824674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12126 10:04:10.824997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12128 10:04:10.871456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12129 10:04:10.871752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12131 10:04:10.920226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12132 10:04:10.920518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12134 10:04:10.967942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12135 10:04:10.968284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12137 10:04:11.020572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12138 10:04:11.020867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12140 10:04:11.074829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12141 10:04:11.075138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12143 10:04:11.136798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12144 10:04:11.137202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12146 10:04:11.195729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12147 10:04:11.196091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12149 10:04:11.246471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12150 10:04:11.246864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12152 10:04:11.294129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12153 10:04:11.294451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12155 10:04:11.348356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12156 10:04:11.348699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12158 10:04:11.398726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12159 10:04:11.399044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12161 10:04:11.457264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12162 10:04:11.457580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12164 10:04:11.515272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12165 10:04:11.515588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12167 10:04:11.566269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12168 10:04:11.566570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12170 10:04:11.628018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12171 10:04:11.628361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12173 10:04:11.678502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12175 10:04:11.681442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12176 10:04:11.732232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12177 10:04:11.732522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12179 10:04:11.783703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12180 10:04:11.783977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12182 10:04:11.845354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12183 10:04:11.845667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12185 10:04:11.900621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12186 10:04:11.901083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12188 10:04:11.970864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12189 10:04:11.971575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12191 10:04:12.036522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12192 10:04:12.037115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12194 10:04:12.108779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12196 10:04:12.111343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12197 10:04:12.179982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12198 10:04:12.180714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12200 10:04:12.250763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12201 10:04:12.251360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12203 10:04:12.323491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12204 10:04:12.324220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12206 10:04:12.394823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12207 10:04:12.395469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12209 10:04:12.463068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12210 10:04:12.463846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12212 10:04:12.532478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12213 10:04:12.533068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12215 10:04:12.601201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12216 10:04:12.601816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12218 10:04:12.675162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12219 10:04:12.675810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12221 10:04:12.746402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12222 10:04:12.746995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12224 10:04:12.825685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12225 10:04:12.826406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12227 10:04:12.896694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12228 10:04:12.897474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12230 10:04:12.974759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12231 10:04:12.975405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12233 10:04:13.042258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12234 10:04:13.042977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12236 10:04:13.114562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12237 10:04:13.115200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12239 10:04:13.184818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12240 10:04:13.185588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12242 10:04:13.254607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12243 10:04:13.255314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12245 10:04:13.324369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12246 10:04:13.325127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12248 10:04:13.394590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12249 10:04:13.395360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12251 10:04:13.471760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12252 10:04:13.472612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12254 10:04:13.541855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12255 10:04:13.542641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12257 10:04:13.609812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12258 10:04:13.610612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12260 10:04:13.682002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12261 10:04:13.682764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12263 10:04:13.756665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12264 10:04:13.757434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12266 10:04:13.832300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12267 10:04:13.833134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12269 10:04:13.901604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12270 10:04:13.902432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12272 10:04:13.986232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12273 10:04:13.987069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12275 10:04:14.062950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12276 10:04:14.063853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12278 10:04:14.137810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12279 10:04:14.138580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12281 10:04:14.214014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12282 10:04:14.214789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12284 10:04:14.277946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12285 10:04:14.278751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12287 10:04:14.348845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12288 10:04:14.349554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12290 10:04:14.420381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12291 10:04:14.421118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12293 10:04:14.489325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12294 10:04:14.490214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12296 10:04:14.560712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12297 10:04:14.561505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12299 10:04:14.627602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12300 10:04:14.628497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12302 10:04:14.701563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12303 10:04:14.702352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12305 10:04:14.775261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12306 10:04:14.776115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12308 10:04:14.847739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12309 10:04:14.848629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12311 10:04:14.919298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12312 10:04:14.920105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12314 10:04:14.994991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12315 10:04:14.995763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12317 10:04:15.065126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12318 10:04:15.065935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12320 10:04:15.136107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12321 10:04:15.136876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12323 10:04:15.201521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12324 10:04:15.202316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12326 10:04:15.271606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12327 10:04:15.272438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12329 10:04:15.340301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12330 10:04:15.341088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12332 10:04:15.410279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12333 10:04:15.411112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12335 10:04:15.482833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12336 10:04:15.483747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12338 10:04:15.557357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12339 10:04:15.558184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12341 10:04:15.618820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12342 10:04:15.619638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12344 10:04:15.695000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12345 10:04:15.695795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12347 10:04:15.767422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12348 10:04:15.768217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12350 10:04:15.837323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12351 10:04:15.838157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12353 10:04:15.902728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12354 10:04:15.903530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12356 10:04:15.969998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12357 10:04:15.970807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12359 10:04:16.051295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12360 10:04:16.052098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12362 10:04:16.126919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12363 10:04:16.127939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12365 10:04:16.188763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12367 10:04:16.191819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12368 10:04:16.268314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12369 10:04:16.269098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12371 10:04:16.333653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12372 10:04:16.334366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12374 10:04:16.408395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12375 10:04:16.409151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12377 10:04:16.481116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12379 10:04:16.483306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12380 10:04:16.549805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12381 10:04:16.550508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12383 10:04:16.623127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12384 10:04:16.623859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12386 10:04:16.685887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12387 10:04:16.686618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12389 10:04:16.755705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12390 10:04:16.756496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12392 10:04:16.824446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12393 10:04:16.825318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12395 10:04:16.887131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12397 10:04:16.889992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12398 10:04:16.956574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12399 10:04:16.957342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12401 10:04:17.024348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12402 10:04:17.025084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12404 10:04:17.097534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12405 10:04:17.098237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12407 10:04:17.162141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12409 10:04:17.164687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12410 10:04:17.226957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12412 10:04:17.230010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12413 10:04:17.302062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12415 10:04:17.304465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12416 10:04:17.371918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12417 10:04:17.372785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12419 10:04:17.438189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12420 10:04:17.438983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12422 10:04:17.508982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12423 10:04:17.509766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12425 10:04:17.582298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12426 10:04:17.582992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12428 10:04:17.645624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12429 10:04:17.646490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12431 10:04:17.717038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12432 10:04:17.717726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12434 10:04:17.781851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12435 10:04:17.782116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12437 10:04:17.840665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12438 10:04:17.841023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12440 10:04:17.906569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12441 10:04:17.906875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12443 10:04:17.976860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12444 10:04:17.977585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12446 10:04:18.044967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12447 10:04:18.045258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12449 10:04:18.105062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12450 10:04:18.105352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12452 10:04:18.167928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12453 10:04:18.168220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12455 10:04:18.220203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12456 10:04:18.220306 + set +x
12457 10:04:18.220554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12459 10:04:18.226947 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 10670666_1.6.2.3.5>
12460 10:04:18.227191 Received signal: <ENDRUN> 1_kselftest-arm64 10670666_1.6.2.3.5
12461 10:04:18.227264 Ending use of test pattern.
12462 10:04:18.227325 Ending test lava.1_kselftest-arm64 (10670666_1.6.2.3.5), duration 34.23
12464 10:04:18.230164 <LAVA_TEST_RUNNER EXIT>
12465 10:04:18.230405 ok: lava_test_shell seems to have completed
12466 10:04:18.231352 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
12467 10:04:18.231497 end: 3.1 lava-test-shell (duration 00:00:35) [common]
12468 10:04:18.231582 end: 3 lava-test-retry (duration 00:00:35) [common]
12469 10:04:18.231668 start: 4 finalize (timeout 00:06:49) [common]
12470 10:04:18.231764 start: 4.1 power-off (timeout 00:00:30) [common]
12471 10:04:18.231917 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
12472 10:04:18.307025 >> Command sent successfully.
12473 10:04:18.311726 Returned 0 in 0 seconds
12474 10:04:18.412302 end: 4.1 power-off (duration 00:00:00) [common]
12476 10:04:18.412702 start: 4.2 read-feedback (timeout 00:06:48) [common]
12477 10:04:18.413031 Listened to connection for namespace 'common' for up to 1s
12478 10:04:19.413972 Finalising connection for namespace 'common'
12479 10:04:19.414174 Disconnecting from shell: Finalise
12480 10:04:19.414260 / #
12481 10:04:19.514842 end: 4.2 read-feedback (duration 00:00:01) [common]
12482 10:04:19.515648 end: 4 finalize (duration 00:00:01) [common]
12483 10:04:19.516243 Cleaning after the job
12484 10:04:19.516706 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/ramdisk
12485 10:04:19.525588 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/kernel
12486 10:04:19.554775 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/dtb
12487 10:04:19.555152 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/nfsrootfs
12488 10:04:19.622929 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670666/tftp-deploy-xbw76tuq/modules
12489 10:04:19.628335 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10670666
12490 10:04:20.153419 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10670666
12491 10:04:20.153587 Job finished correctly