Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 43
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 33
- Errors: 0
1 10:04:08.337460 lava-dispatcher, installed at version: 2023.05.1
2 10:04:08.337663 start: 0 validate
3 10:04:08.337793 Start time: 2023-06-10 10:04:08.337785+00:00 (UTC)
4 10:04:08.337910 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:04:08.338036 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 10:04:08.619541 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:04:08.620295 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:04:08.882930 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:04:08.883659 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:04:09.146503 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:04:09.147209 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:04:09.410320 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:04:09.410967 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:04:09.671490 validate duration: 1.33
16 10:04:09.672731 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:04:09.673238 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:04:09.673701 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:04:09.674272 Not decompressing ramdisk as can be used compressed.
20 10:04:09.674724 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 10:04:09.675069 saving as /var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/ramdisk/initrd.cpio.gz
22 10:04:09.675397 total size: 4665601 (4MB)
23 10:04:09.680730 progress 0% (0MB)
24 10:04:09.688077 progress 5% (0MB)
25 10:04:09.694390 progress 10% (0MB)
26 10:04:09.700032 progress 15% (0MB)
27 10:04:09.704017 progress 20% (0MB)
28 10:04:09.707267 progress 25% (1MB)
29 10:04:09.710047 progress 30% (1MB)
30 10:04:09.712687 progress 35% (1MB)
31 10:04:09.714934 progress 40% (1MB)
32 10:04:09.717441 progress 45% (2MB)
33 10:04:09.719494 progress 50% (2MB)
34 10:04:09.721408 progress 55% (2MB)
35 10:04:09.723264 progress 60% (2MB)
36 10:04:09.724937 progress 65% (2MB)
37 10:04:09.726615 progress 70% (3MB)
38 10:04:09.728283 progress 75% (3MB)
39 10:04:09.729776 progress 80% (3MB)
40 10:04:09.731461 progress 85% (3MB)
41 10:04:09.732964 progress 90% (4MB)
42 10:04:09.734301 progress 95% (4MB)
43 10:04:09.735681 progress 100% (4MB)
44 10:04:09.735853 4MB downloaded in 0.06s (73.59MB/s)
45 10:04:09.736016 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:04:09.736283 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:04:09.736379 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:04:09.736472 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:04:09.736621 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:04:09.736704 saving as /var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/kernel/Image
52 10:04:09.736772 total size: 45746688 (43MB)
53 10:04:09.736861 No compression specified
54 10:04:09.738197 progress 0% (0MB)
55 10:04:09.749817 progress 5% (2MB)
56 10:04:09.761030 progress 10% (4MB)
57 10:04:09.772290 progress 15% (6MB)
58 10:04:09.783537 progress 20% (8MB)
59 10:04:09.794894 progress 25% (10MB)
60 10:04:09.806231 progress 30% (13MB)
61 10:04:09.817626 progress 35% (15MB)
62 10:04:09.829305 progress 40% (17MB)
63 10:04:09.840770 progress 45% (19MB)
64 10:04:09.852099 progress 50% (21MB)
65 10:04:09.863245 progress 55% (24MB)
66 10:04:09.874470 progress 60% (26MB)
67 10:04:09.885807 progress 65% (28MB)
68 10:04:09.897202 progress 70% (30MB)
69 10:04:09.908671 progress 75% (32MB)
70 10:04:09.919850 progress 80% (34MB)
71 10:04:09.931982 progress 85% (37MB)
72 10:04:09.944276 progress 90% (39MB)
73 10:04:09.956343 progress 95% (41MB)
74 10:04:09.967433 progress 100% (43MB)
75 10:04:09.967549 43MB downloaded in 0.23s (189.05MB/s)
76 10:04:09.967693 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:04:09.967919 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:04:09.968008 start: 1.3 download-retry (timeout 00:10:00) [common]
80 10:04:09.968094 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 10:04:09.968224 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 10:04:09.968338 saving as /var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/dtb/mt8192-asurada-spherion-r0.dtb
83 10:04:09.968427 total size: 46924 (0MB)
84 10:04:09.968499 No compression specified
85 10:04:09.969577 progress 69% (0MB)
86 10:04:09.969849 progress 100% (0MB)
87 10:04:09.970000 0MB downloaded in 0.00s (28.50MB/s)
88 10:04:09.970120 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:04:09.970345 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:04:09.970429 start: 1.4 download-retry (timeout 00:10:00) [common]
92 10:04:09.970511 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 10:04:09.970618 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 10:04:09.970686 saving as /var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/nfsrootfs/full.rootfs.tar
95 10:04:09.970746 total size: 200770336 (191MB)
96 10:04:09.970806 Using unxz to decompress xz
97 10:04:09.974401 progress 0% (0MB)
98 10:04:10.499339 progress 5% (9MB)
99 10:04:10.999004 progress 10% (19MB)
100 10:04:11.570923 progress 15% (28MB)
101 10:04:11.933290 progress 20% (38MB)
102 10:04:12.250584 progress 25% (47MB)
103 10:04:12.833465 progress 30% (57MB)
104 10:04:13.375500 progress 35% (67MB)
105 10:04:13.952830 progress 40% (76MB)
106 10:04:14.503530 progress 45% (86MB)
107 10:04:15.073832 progress 50% (95MB)
108 10:04:15.692811 progress 55% (105MB)
109 10:04:16.347341 progress 60% (114MB)
110 10:04:16.463766 progress 65% (124MB)
111 10:04:16.602977 progress 70% (134MB)
112 10:04:16.697026 progress 75% (143MB)
113 10:04:16.770041 progress 80% (153MB)
114 10:04:16.837310 progress 85% (162MB)
115 10:04:16.933754 progress 90% (172MB)
116 10:04:17.203055 progress 95% (181MB)
117 10:04:17.757544 progress 100% (191MB)
118 10:04:17.761971 191MB downloaded in 7.79s (24.58MB/s)
119 10:04:17.762258 end: 1.4.1 http-download (duration 00:00:08) [common]
121 10:04:17.762515 end: 1.4 download-retry (duration 00:00:08) [common]
122 10:04:17.762605 start: 1.5 download-retry (timeout 00:09:52) [common]
123 10:04:17.762692 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 10:04:17.762843 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:04:17.762915 saving as /var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/modules/modules.tar
126 10:04:17.762978 total size: 8540248 (8MB)
127 10:04:17.763041 Using unxz to decompress xz
128 10:04:17.766677 progress 0% (0MB)
129 10:04:17.788314 progress 5% (0MB)
130 10:04:17.812447 progress 10% (0MB)
131 10:04:17.835860 progress 15% (1MB)
132 10:04:17.860356 progress 20% (1MB)
133 10:04:17.883891 progress 25% (2MB)
134 10:04:17.906133 progress 30% (2MB)
135 10:04:17.931229 progress 35% (2MB)
136 10:04:17.955064 progress 40% (3MB)
137 10:04:17.977784 progress 45% (3MB)
138 10:04:18.004206 progress 50% (4MB)
139 10:04:18.028456 progress 55% (4MB)
140 10:04:18.054264 progress 60% (4MB)
141 10:04:18.079047 progress 65% (5MB)
142 10:04:18.103478 progress 70% (5MB)
143 10:04:18.127259 progress 75% (6MB)
144 10:04:18.153983 progress 80% (6MB)
145 10:04:18.177228 progress 85% (6MB)
146 10:04:18.205344 progress 90% (7MB)
147 10:04:18.230282 progress 95% (7MB)
148 10:04:18.254854 progress 100% (8MB)
149 10:04:18.259945 8MB downloaded in 0.50s (16.39MB/s)
150 10:04:18.260205 end: 1.5.1 http-download (duration 00:00:00) [common]
152 10:04:18.260463 end: 1.5 download-retry (duration 00:00:00) [common]
153 10:04:18.260597 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 10:04:18.260693 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 10:04:21.454706 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10670685/extract-nfsrootfs-fbgtgk4p
156 10:04:21.454917 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 10:04:21.455022 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 10:04:21.455185 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph
159 10:04:21.455317 makedir: /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin
160 10:04:21.455479 makedir: /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/tests
161 10:04:21.455603 makedir: /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/results
162 10:04:21.455702 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-add-keys
163 10:04:21.455841 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-add-sources
164 10:04:21.455964 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-background-process-start
165 10:04:21.456086 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-background-process-stop
166 10:04:21.456207 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-common-functions
167 10:04:21.456327 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-echo-ipv4
168 10:04:21.456447 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-install-packages
169 10:04:21.456826 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-installed-packages
170 10:04:21.456951 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-os-build
171 10:04:21.457079 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-probe-channel
172 10:04:21.457199 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-probe-ip
173 10:04:21.457321 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-target-ip
174 10:04:21.457439 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-target-mac
175 10:04:21.457557 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-target-storage
176 10:04:21.457677 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-test-case
177 10:04:21.457797 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-test-event
178 10:04:21.457916 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-test-feedback
179 10:04:21.458034 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-test-raise
180 10:04:21.458153 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-test-reference
181 10:04:21.458271 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-test-runner
182 10:04:21.458389 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-test-set
183 10:04:21.458507 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-test-shell
184 10:04:21.458627 Updating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-add-keys (debian)
185 10:04:21.458773 Updating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-add-sources (debian)
186 10:04:21.458907 Updating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-install-packages (debian)
187 10:04:21.459038 Updating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-installed-packages (debian)
188 10:04:21.459168 Updating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/bin/lava-os-build (debian)
189 10:04:21.459283 Creating /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/environment
190 10:04:21.459375 LAVA metadata
191 10:04:21.459463 - LAVA_JOB_ID=10670685
192 10:04:21.459539 - LAVA_DISPATCHER_IP=192.168.201.1
193 10:04:21.459635 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 10:04:21.459701 skipped lava-vland-overlay
195 10:04:21.459773 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 10:04:21.459851 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 10:04:21.459910 skipped lava-multinode-overlay
198 10:04:21.459980 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 10:04:21.460069 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 10:04:21.460140 Loading test definitions
201 10:04:21.460229 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 10:04:21.460300 Using /lava-10670685 at stage 0
203 10:04:21.460563 uuid=10670685_1.6.2.3.1 testdef=None
204 10:04:21.460650 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 10:04:21.460733 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 10:04:21.461166 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 10:04:21.461384 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 10:04:21.461914 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 10:04:21.462147 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 10:04:21.462663 runner path: /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/0/tests/0_timesync-off test_uuid 10670685_1.6.2.3.1
213 10:04:21.462811 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 10:04:21.463032 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 10:04:21.463103 Using /lava-10670685 at stage 0
217 10:04:21.463197 Fetching tests from https://github.com/kernelci/test-definitions.git
218 10:04:21.463272 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/0/tests/1_kselftest-rtc'
219 10:04:25.755863 Running '/usr/bin/git checkout kernelci.org
220 10:04:25.896141 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 10:04:25.896890 uuid=10670685_1.6.2.3.5 testdef=None
222 10:04:25.897042 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 10:04:25.897285 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 10:04:25.898009 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 10:04:25.898239 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 10:04:25.899194 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 10:04:25.899427 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 10:04:25.900319 runner path: /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/0/tests/1_kselftest-rtc test_uuid 10670685_1.6.2.3.5
232 10:04:25.900410 BOARD='mt8192-asurada-spherion-r0'
233 10:04:25.900475 BRANCH='cip'
234 10:04:25.900569 SKIPFILE='/dev/null'
235 10:04:25.900657 SKIP_INSTALL='True'
236 10:04:25.900712 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 10:04:25.900769 TST_CASENAME=''
238 10:04:25.900825 TST_CMDFILES='rtc'
239 10:04:25.900969 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 10:04:25.901209 Creating lava-test-runner.conf files
242 10:04:25.901297 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10670685/lava-overlay-s13u0uph/lava-10670685/0 for stage 0
243 10:04:25.901417 - 0_timesync-off
244 10:04:25.901495 - 1_kselftest-rtc
245 10:04:25.901616 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 10:04:25.901720 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 10:04:33.667170 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 10:04:33.667360 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 10:04:33.667497 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 10:04:33.667649 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 10:04:33.667783 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 10:04:33.782985 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 10:04:33.783393 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 10:04:33.783557 extracting modules file /var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670685/extract-nfsrootfs-fbgtgk4p
255 10:04:34.036820 extracting modules file /var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670685/extract-overlay-ramdisk-y56z75wf/ramdisk
256 10:04:34.274566 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 10:04:34.274745 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 10:04:34.274842 [common] Applying overlay to NFS
259 10:04:34.274914 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670685/compress-overlay-jwym638f/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10670685/extract-nfsrootfs-fbgtgk4p
260 10:04:35.190547 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 10:04:35.190727 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 10:04:35.190823 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 10:04:35.190917 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 10:04:35.191007 Building ramdisk /var/lib/lava/dispatcher/tmp/10670685/extract-overlay-ramdisk-y56z75wf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10670685/extract-overlay-ramdisk-y56z75wf/ramdisk
265 10:04:35.498415 >> 117806 blocks
266 10:04:37.393823 rename /var/lib/lava/dispatcher/tmp/10670685/extract-overlay-ramdisk-y56z75wf/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/ramdisk/ramdisk.cpio.gz
267 10:04:37.394274 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 10:04:37.394394 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 10:04:37.394500 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 10:04:37.394608 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/kernel/Image'
271 10:04:48.692327 Returned 0 in 11 seconds
272 10:04:48.793024 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/kernel/image.itb
273 10:04:49.107740 output: FIT description: Kernel Image image with one or more FDT blobs
274 10:04:49.108124 output: Created: Sat Jun 10 11:04:49 2023
275 10:04:49.108214 output: Image 0 (kernel-1)
276 10:04:49.108281 output: Description:
277 10:04:49.108347 output: Created: Sat Jun 10 11:04:49 2023
278 10:04:49.108413 output: Type: Kernel Image
279 10:04:49.108476 output: Compression: lzma compressed
280 10:04:49.108547 output: Data Size: 10087317 Bytes = 9850.90 KiB = 9.62 MiB
281 10:04:49.108611 output: Architecture: AArch64
282 10:04:49.108671 output: OS: Linux
283 10:04:49.108730 output: Load Address: 0x00000000
284 10:04:49.108789 output: Entry Point: 0x00000000
285 10:04:49.108850 output: Hash algo: crc32
286 10:04:49.108906 output: Hash value: c9e456fd
287 10:04:49.108961 output: Image 1 (fdt-1)
288 10:04:49.109016 output: Description: mt8192-asurada-spherion-r0
289 10:04:49.109072 output: Created: Sat Jun 10 11:04:49 2023
290 10:04:49.109128 output: Type: Flat Device Tree
291 10:04:49.109183 output: Compression: uncompressed
292 10:04:49.109239 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 10:04:49.109295 output: Architecture: AArch64
294 10:04:49.109351 output: Hash algo: crc32
295 10:04:49.109406 output: Hash value: 1df858fa
296 10:04:49.109461 output: Image 2 (ramdisk-1)
297 10:04:49.109516 output: Description: unavailable
298 10:04:49.109571 output: Created: Sat Jun 10 11:04:49 2023
299 10:04:49.109626 output: Type: RAMDisk Image
300 10:04:49.109681 output: Compression: Unknown Compression
301 10:04:49.109736 output: Data Size: 17646324 Bytes = 17232.74 KiB = 16.83 MiB
302 10:04:49.109791 output: Architecture: AArch64
303 10:04:49.109847 output: OS: Linux
304 10:04:49.109902 output: Load Address: unavailable
305 10:04:49.109956 output: Entry Point: unavailable
306 10:04:49.110011 output: Hash algo: crc32
307 10:04:49.110066 output: Hash value: 959372da
308 10:04:49.110120 output: Default Configuration: 'conf-1'
309 10:04:49.110175 output: Configuration 0 (conf-1)
310 10:04:49.110229 output: Description: mt8192-asurada-spherion-r0
311 10:04:49.110284 output: Kernel: kernel-1
312 10:04:49.110339 output: Init Ramdisk: ramdisk-1
313 10:04:49.110394 output: FDT: fdt-1
314 10:04:49.110448 output: Loadables: kernel-1
315 10:04:49.110503 output:
316 10:04:49.110704 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 10:04:49.110808 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 10:04:49.110914 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 10:04:49.111017 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 10:04:49.111098 No LXC device requested
321 10:04:49.111182 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 10:04:49.111270 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 10:04:49.111348 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 10:04:49.111421 Checking files for TFTP limit of 4294967296 bytes.
325 10:04:49.111936 end: 1 tftp-deploy (duration 00:00:39) [common]
326 10:04:49.112049 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 10:04:49.112144 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 10:04:49.112274 substitutions:
329 10:04:49.112345 - {DTB}: 10670685/tftp-deploy-bg4sbiaz/dtb/mt8192-asurada-spherion-r0.dtb
330 10:04:49.112413 - {INITRD}: 10670685/tftp-deploy-bg4sbiaz/ramdisk/ramdisk.cpio.gz
331 10:04:49.112476 - {KERNEL}: 10670685/tftp-deploy-bg4sbiaz/kernel/Image
332 10:04:49.112542 - {LAVA_MAC}: None
333 10:04:49.112608 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10670685/extract-nfsrootfs-fbgtgk4p
334 10:04:49.112668 - {NFS_SERVER_IP}: 192.168.201.1
335 10:04:49.112726 - {PRESEED_CONFIG}: None
336 10:04:49.112784 - {PRESEED_LOCAL}: None
337 10:04:49.112841 - {RAMDISK}: 10670685/tftp-deploy-bg4sbiaz/ramdisk/ramdisk.cpio.gz
338 10:04:49.112898 - {ROOT_PART}: None
339 10:04:49.112954 - {ROOT}: None
340 10:04:49.113011 - {SERVER_IP}: 192.168.201.1
341 10:04:49.113068 - {TEE}: None
342 10:04:49.113125 Parsed boot commands:
343 10:04:49.113183 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 10:04:49.113371 Parsed boot commands: tftpboot 192.168.201.1 10670685/tftp-deploy-bg4sbiaz/kernel/image.itb 10670685/tftp-deploy-bg4sbiaz/kernel/cmdline
345 10:04:49.113468 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 10:04:49.113559 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 10:04:49.113653 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 10:04:49.113747 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 10:04:49.113821 Not connected, no need to disconnect.
350 10:04:49.113899 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 10:04:49.113986 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 10:04:49.114055 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
353 10:04:49.117693 Setting prompt string to ['lava-test: # ']
354 10:04:49.118082 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 10:04:49.118208 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 10:04:49.118314 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 10:04:49.118409 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 10:04:49.118601 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 10:04:54.252200 >> Command sent successfully.
360 10:04:54.254690 Returned 0 in 5 seconds
361 10:04:54.355099 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 10:04:54.355475 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 10:04:54.355581 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 10:04:54.355678 Setting prompt string to 'Starting depthcharge on Spherion...'
366 10:04:54.355746 Changing prompt to 'Starting depthcharge on Spherion...'
367 10:04:54.355845 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 10:04:54.356126 [Enter `^Ec?' for help]
369 10:04:54.528576
370 10:04:54.528716
371 10:04:54.528788 F0: 102B 0000
372 10:04:54.528900
373 10:04:54.528994 F3: 1001 0000 [0200]
374 10:04:54.529070
375 10:04:54.531523 F3: 1001 0000
376 10:04:54.531612
377 10:04:54.531674 F7: 102D 0000
378 10:04:54.531732
379 10:04:54.534565 F1: 0000 0000
380 10:04:54.534636
381 10:04:54.534703 V0: 0000 0000 [0001]
382 10:04:54.534762
383 10:04:54.538038 00: 0007 8000
384 10:04:54.538128
385 10:04:54.538197 01: 0000 0000
386 10:04:54.538278
387 10:04:54.541282 BP: 0C00 0209 [0000]
388 10:04:54.541367
389 10:04:54.541435 G0: 1182 0000
390 10:04:54.541499
391 10:04:54.544509 EC: 0000 0021 [4000]
392 10:04:54.544637
393 10:04:54.544706 S7: 0000 0000 [0000]
394 10:04:54.544768
395 10:04:54.548584 CC: 0000 0000 [0001]
396 10:04:54.548687
397 10:04:54.548763 T0: 0000 0040 [010F]
398 10:04:54.548860
399 10:04:54.548921 Jump to BL
400 10:04:54.551995
401 10:04:54.575639
402 10:04:54.575738
403 10:04:54.575808
404 10:04:54.581698 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 10:04:54.585357 ARM64: Exception handlers installed.
406 10:04:54.589615 ARM64: Testing exception
407 10:04:54.592670 ARM64: Done test exception
408 10:04:54.600120 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 10:04:54.610211 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 10:04:54.616299 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 10:04:54.626938 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 10:04:54.633353 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 10:04:54.640080 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 10:04:54.651096 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 10:04:54.657818 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 10:04:54.677887 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 10:04:54.680882 WDT: Last reset was cold boot
418 10:04:54.684701 SPI1(PAD0) initialized at 2873684 Hz
419 10:04:54.687572 SPI5(PAD0) initialized at 992727 Hz
420 10:04:54.691018 VBOOT: Loading verstage.
421 10:04:54.697884 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 10:04:54.700794 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 10:04:54.704270 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 10:04:54.707604 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 10:04:54.715209 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 10:04:54.722059 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 10:04:54.732769 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 10:04:54.732857
429 10:04:54.732926
430 10:04:54.742833 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 10:04:54.746102 ARM64: Exception handlers installed.
432 10:04:54.749628 ARM64: Testing exception
433 10:04:54.752398 ARM64: Done test exception
434 10:04:54.755759 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 10:04:54.759322 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 10:04:54.774108 Probing TPM: . done!
437 10:04:54.774198 TPM ready after 0 ms
438 10:04:54.780731 Connected to device vid:did:rid of 1ae0:0028:00
439 10:04:54.790124 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 10:04:54.828623 Initialized TPM device CR50 revision 0
441 10:04:54.841203 tlcl_send_startup: Startup return code is 0
442 10:04:54.841310 TPM: setup succeeded
443 10:04:54.853574 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 10:04:54.861766 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 10:04:54.869040 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 10:04:54.882205 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 10:04:54.885474 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 10:04:54.888545 in-header: 03 07 00 00 08 00 00 00
449 10:04:54.891941 in-data: aa e4 47 04 13 02 00 00
450 10:04:54.895035 Chrome EC: UHEPI supported
451 10:04:54.901581 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 10:04:54.905343 in-header: 03 ad 00 00 08 00 00 00
453 10:04:54.908345 in-data: 00 20 20 08 00 00 00 00
454 10:04:54.908448 Phase 1
455 10:04:54.911729 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 10:04:54.918309 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 10:04:54.925051 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 10:04:54.928200 Recovery requested (1009000e)
459 10:04:54.932510 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 10:04:54.940915 tlcl_extend: response is 0
461 10:04:54.949308 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 10:04:54.954328 tlcl_extend: response is 0
463 10:04:54.960527 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 10:04:54.981517 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 10:04:54.988371 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 10:04:54.988469
467 10:04:54.988577
468 10:04:54.998294 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 10:04:55.002189 ARM64: Exception handlers installed.
470 10:04:55.002305 ARM64: Testing exception
471 10:04:55.005273 ARM64: Done test exception
472 10:04:55.026910 pmic_efuse_setting: Set efuses in 11 msecs
473 10:04:55.030559 pmwrap_interface_init: Select PMIF_VLD_RDY
474 10:04:55.037474 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 10:04:55.040814 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 10:04:55.046998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 10:04:55.050635 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 10:04:55.054229 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 10:04:55.060695 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 10:04:55.064205 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 10:04:55.070811 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 10:04:55.073715 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 10:04:55.080774 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 10:04:55.084146 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 10:04:55.087111 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 10:04:55.094126 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 10:04:55.100741 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 10:04:55.103787 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 10:04:55.110519 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 10:04:55.117278 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 10:04:55.120394 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 10:04:55.126609 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 10:04:55.133714 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 10:04:55.137122 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 10:04:55.143967 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 10:04:55.151365 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 10:04:55.154802 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 10:04:55.161477 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 10:04:55.164920 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 10:04:55.172474 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 10:04:55.175173 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 10:04:55.182237 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 10:04:55.185664 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 10:04:55.193151 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 10:04:55.196596 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 10:04:55.200114 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 10:04:55.206233 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 10:04:55.210032 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 10:04:55.216648 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 10:04:55.220585 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 10:04:55.227533 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 10:04:55.231213 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 10:04:55.234201 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 10:04:55.237597 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 10:04:55.244545 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 10:04:55.247419 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 10:04:55.250674 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 10:04:55.257908 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 10:04:55.261027 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 10:04:55.264472 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 10:04:55.271245 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 10:04:55.274148 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 10:04:55.277649 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 10:04:55.281053 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 10:04:55.290631 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 10:04:55.297834 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 10:04:55.304058 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 10:04:55.310745 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 10:04:55.320854 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 10:04:55.324525 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 10:04:55.327698 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 10:04:55.334204 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 10:04:55.340330 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x13
534 10:04:55.344055 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 10:04:55.350933 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 10:04:55.354719 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 10:04:55.364022 [RTC]rtc_get_frequency_meter,154: input=15, output=834
538 10:04:55.373784 [RTC]rtc_get_frequency_meter,154: input=7, output=708
539 10:04:55.382951 [RTC]rtc_get_frequency_meter,154: input=11, output=771
540 10:04:55.392509 [RTC]rtc_get_frequency_meter,154: input=13, output=803
541 10:04:55.402057 [RTC]rtc_get_frequency_meter,154: input=12, output=787
542 10:04:55.411338 [RTC]rtc_get_frequency_meter,154: input=12, output=787
543 10:04:55.421256 [RTC]rtc_get_frequency_meter,154: input=13, output=803
544 10:04:55.424416 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 10:04:55.431868 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 10:04:55.435011 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 10:04:55.438433 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 10:04:55.444844 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 10:04:55.448030 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 10:04:55.451375 ADC[4]: Raw value=903031 ID=7
551 10:04:55.451486 ADC[3]: Raw value=214021 ID=1
552 10:04:55.454741 RAM Code: 0x71
553 10:04:55.458192 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 10:04:55.464968 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 10:04:55.471368 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 10:04:55.478102 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 10:04:55.481213 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 10:04:55.484319 in-header: 03 07 00 00 08 00 00 00
559 10:04:55.487890 in-data: aa e4 47 04 13 02 00 00
560 10:04:55.491277 Chrome EC: UHEPI supported
561 10:04:55.497921 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 10:04:55.501629 in-header: 03 dd 00 00 08 00 00 00
563 10:04:55.504446 in-data: 90 20 60 08 00 00 00 00
564 10:04:55.508329 MRC: failed to locate region type 0.
565 10:04:55.514561 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 10:04:55.518072 DRAM-K: Running full calibration
567 10:04:55.524167 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 10:04:55.524260 header.status = 0x0
569 10:04:55.527683 header.version = 0x6 (expected: 0x6)
570 10:04:55.531174 header.size = 0xd00 (expected: 0xd00)
571 10:04:55.534247 header.flags = 0x0
572 10:04:55.541071 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 10:04:55.557811 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 10:04:55.564246 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 10:04:55.567727 dram_init: ddr_geometry: 2
576 10:04:55.570955 [EMI] MDL number = 2
577 10:04:55.571036 [EMI] Get MDL freq = 0
578 10:04:55.574395 dram_init: ddr_type: 0
579 10:04:55.574487 is_discrete_lpddr4: 1
580 10:04:55.577693 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 10:04:55.577777
582 10:04:55.580923
583 10:04:55.581010 [Bian_co] ETT version 0.0.0.1
584 10:04:55.587931 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 10:04:55.588078
586 10:04:55.591157 dramc_set_vcore_voltage set vcore to 650000
587 10:04:55.594071 Read voltage for 800, 4
588 10:04:55.594151 Vio18 = 0
589 10:04:55.594218 Vcore = 650000
590 10:04:55.597599 Vdram = 0
591 10:04:55.597709 Vddq = 0
592 10:04:55.597782 Vmddr = 0
593 10:04:55.601195 dram_init: config_dvfs: 1
594 10:04:55.604134 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 10:04:55.610844 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 10:04:55.614080 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 10:04:55.617664 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 10:04:55.621105 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 10:04:55.627371 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 10:04:55.627456 MEM_TYPE=3, freq_sel=18
601 10:04:55.631002 sv_algorithm_assistance_LP4_1600
602 10:04:55.633874 ============ PULL DRAM RESETB DOWN ============
603 10:04:55.640903 ========== PULL DRAM RESETB DOWN end =========
604 10:04:55.644313 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 10:04:55.647414 ===================================
606 10:04:55.650484 LPDDR4 DRAM CONFIGURATION
607 10:04:55.654347 ===================================
608 10:04:55.654433 EX_ROW_EN[0] = 0x0
609 10:04:55.657206 EX_ROW_EN[1] = 0x0
610 10:04:55.657320 LP4Y_EN = 0x0
611 10:04:55.660466 WORK_FSP = 0x0
612 10:04:55.660586 WL = 0x2
613 10:04:55.663521 RL = 0x2
614 10:04:55.666840 BL = 0x2
615 10:04:55.666946 RPST = 0x0
616 10:04:55.670234 RD_PRE = 0x0
617 10:04:55.670366 WR_PRE = 0x1
618 10:04:55.673861 WR_PST = 0x0
619 10:04:55.673950 DBI_WR = 0x0
620 10:04:55.677086 DBI_RD = 0x0
621 10:04:55.677180 OTF = 0x1
622 10:04:55.681034 ===================================
623 10:04:55.683718 ===================================
624 10:04:55.687012 ANA top config
625 10:04:55.687128 ===================================
626 10:04:55.690596 DLL_ASYNC_EN = 0
627 10:04:55.693633 ALL_SLAVE_EN = 1
628 10:04:55.696911 NEW_RANK_MODE = 1
629 10:04:55.700262 DLL_IDLE_MODE = 1
630 10:04:55.700370 LP45_APHY_COMB_EN = 1
631 10:04:55.703503 TX_ODT_DIS = 1
632 10:04:55.706956 NEW_8X_MODE = 1
633 10:04:55.710098 ===================================
634 10:04:55.713763 ===================================
635 10:04:55.716866 data_rate = 1600
636 10:04:55.720164 CKR = 1
637 10:04:55.723110 DQ_P2S_RATIO = 8
638 10:04:55.726878 ===================================
639 10:04:55.726964 CA_P2S_RATIO = 8
640 10:04:55.730009 DQ_CA_OPEN = 0
641 10:04:55.733854 DQ_SEMI_OPEN = 0
642 10:04:55.736411 CA_SEMI_OPEN = 0
643 10:04:55.739889 CA_FULL_RATE = 0
644 10:04:55.743360 DQ_CKDIV4_EN = 1
645 10:04:55.743446 CA_CKDIV4_EN = 1
646 10:04:55.746387 CA_PREDIV_EN = 0
647 10:04:55.749701 PH8_DLY = 0
648 10:04:55.753278 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 10:04:55.756417 DQ_AAMCK_DIV = 4
650 10:04:55.760122 CA_AAMCK_DIV = 4
651 10:04:55.760260 CA_ADMCK_DIV = 4
652 10:04:55.763799 DQ_TRACK_CA_EN = 0
653 10:04:55.766162 CA_PICK = 800
654 10:04:55.769636 CA_MCKIO = 800
655 10:04:55.773069 MCKIO_SEMI = 0
656 10:04:55.776244 PLL_FREQ = 3068
657 10:04:55.779941 DQ_UI_PI_RATIO = 32
658 10:04:55.780047 CA_UI_PI_RATIO = 0
659 10:04:55.782979 ===================================
660 10:04:55.786584 ===================================
661 10:04:55.789563 memory_type:LPDDR4
662 10:04:55.792842 GP_NUM : 10
663 10:04:55.792926 SRAM_EN : 1
664 10:04:55.796183 MD32_EN : 0
665 10:04:55.799805 ===================================
666 10:04:55.802853 [ANA_INIT] >>>>>>>>>>>>>>
667 10:04:55.805841 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 10:04:55.809221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 10:04:55.812377 ===================================
670 10:04:55.812485 data_rate = 1600,PCW = 0X7600
671 10:04:55.815794 ===================================
672 10:04:55.819136 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 10:04:55.826383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 10:04:55.832606 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 10:04:55.835564 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 10:04:55.839365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 10:04:55.842131 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 10:04:55.845717 [ANA_INIT] flow start
679 10:04:55.849059 [ANA_INIT] PLL >>>>>>>>
680 10:04:55.849173 [ANA_INIT] PLL <<<<<<<<
681 10:04:55.852435 [ANA_INIT] MIDPI >>>>>>>>
682 10:04:55.855672 [ANA_INIT] MIDPI <<<<<<<<
683 10:04:55.855756 [ANA_INIT] DLL >>>>>>>>
684 10:04:55.858668 [ANA_INIT] flow end
685 10:04:55.861905 ============ LP4 DIFF to SE enter ============
686 10:04:55.865976 ============ LP4 DIFF to SE exit ============
687 10:04:55.868650 [ANA_INIT] <<<<<<<<<<<<<
688 10:04:55.871937 [Flow] Enable top DCM control >>>>>
689 10:04:55.875655 [Flow] Enable top DCM control <<<<<
690 10:04:55.878756 Enable DLL master slave shuffle
691 10:04:55.885310 ==============================================================
692 10:04:55.885397 Gating Mode config
693 10:04:55.892355 ==============================================================
694 10:04:55.892489 Config description:
695 10:04:55.902104 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 10:04:55.908729 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 10:04:55.915418 SELPH_MODE 0: By rank 1: By Phase
698 10:04:55.918817 ==============================================================
699 10:04:55.922105 GAT_TRACK_EN = 1
700 10:04:55.925726 RX_GATING_MODE = 2
701 10:04:55.929277 RX_GATING_TRACK_MODE = 2
702 10:04:55.932726 SELPH_MODE = 1
703 10:04:55.935757 PICG_EARLY_EN = 1
704 10:04:55.938571 VALID_LAT_VALUE = 1
705 10:04:55.945324 ==============================================================
706 10:04:55.948792 Enter into Gating configuration >>>>
707 10:04:55.952047 Exit from Gating configuration <<<<
708 10:04:55.952140 Enter into DVFS_PRE_config >>>>>
709 10:04:55.965505 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 10:04:55.968502 Exit from DVFS_PRE_config <<<<<
711 10:04:55.972136 Enter into PICG configuration >>>>
712 10:04:55.975534 Exit from PICG configuration <<<<
713 10:04:55.975629 [RX_INPUT] configuration >>>>>
714 10:04:55.978871 [RX_INPUT] configuration <<<<<
715 10:04:55.986028 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 10:04:55.989232 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 10:04:55.996401 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 10:04:56.003589 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 10:04:56.010379 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 10:04:56.014639 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 10:04:56.017727 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 10:04:56.024882 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 10:04:56.028086 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 10:04:56.032086 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 10:04:56.035261 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 10:04:56.039270 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 10:04:56.042566 ===================================
728 10:04:56.046794 LPDDR4 DRAM CONFIGURATION
729 10:04:56.049714 ===================================
730 10:04:56.049830 EX_ROW_EN[0] = 0x0
731 10:04:56.054213 EX_ROW_EN[1] = 0x0
732 10:04:56.054322 LP4Y_EN = 0x0
733 10:04:56.057204 WORK_FSP = 0x0
734 10:04:56.057287 WL = 0x2
735 10:04:56.060975 RL = 0x2
736 10:04:56.061059 BL = 0x2
737 10:04:56.064451 RPST = 0x0
738 10:04:56.064589 RD_PRE = 0x0
739 10:04:56.068463 WR_PRE = 0x1
740 10:04:56.068599 WR_PST = 0x0
741 10:04:56.068703 DBI_WR = 0x0
742 10:04:56.072447 DBI_RD = 0x0
743 10:04:56.072584 OTF = 0x1
744 10:04:56.076168 ===================================
745 10:04:56.079626 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 10:04:56.083400 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 10:04:56.090906 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 10:04:56.094237 ===================================
749 10:04:56.094324 LPDDR4 DRAM CONFIGURATION
750 10:04:56.098216 ===================================
751 10:04:56.102131 EX_ROW_EN[0] = 0x10
752 10:04:56.102217 EX_ROW_EN[1] = 0x0
753 10:04:56.105542 LP4Y_EN = 0x0
754 10:04:56.105695 WORK_FSP = 0x0
755 10:04:56.109081 WL = 0x2
756 10:04:56.109166 RL = 0x2
757 10:04:56.113072 BL = 0x2
758 10:04:56.113183 RPST = 0x0
759 10:04:56.113280 RD_PRE = 0x0
760 10:04:56.116978 WR_PRE = 0x1
761 10:04:56.117095 WR_PST = 0x0
762 10:04:56.120347 DBI_WR = 0x0
763 10:04:56.120458 DBI_RD = 0x0
764 10:04:56.123848 OTF = 0x1
765 10:04:56.127911 ===================================
766 10:04:56.131575 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 10:04:56.136331 nWR fixed to 40
768 10:04:56.140304 [ModeRegInit_LP4] CH0 RK0
769 10:04:56.140409 [ModeRegInit_LP4] CH0 RK1
770 10:04:56.143757 [ModeRegInit_LP4] CH1 RK0
771 10:04:56.146722 [ModeRegInit_LP4] CH1 RK1
772 10:04:56.146808 match AC timing 13
773 10:04:56.150325 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 10:04:56.156666 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 10:04:56.160263 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 10:04:56.163941 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 10:04:56.170209 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 10:04:56.170295 [EMI DOE] emi_dcm 0
779 10:04:56.174128 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 10:04:56.176959 ==
781 10:04:56.180583 Dram Type= 6, Freq= 0, CH_0, rank 0
782 10:04:56.185343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 10:04:56.185429 ==
784 10:04:56.188250 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 10:04:56.194758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 10:04:56.203567 [CA 0] Center 37 (6~68) winsize 63
787 10:04:56.207533 [CA 1] Center 36 (6~67) winsize 62
788 10:04:56.210682 [CA 2] Center 34 (4~65) winsize 62
789 10:04:56.213824 [CA 3] Center 34 (4~65) winsize 62
790 10:04:56.217531 [CA 4] Center 34 (4~64) winsize 61
791 10:04:56.220849 [CA 5] Center 33 (3~64) winsize 62
792 10:04:56.220934
793 10:04:56.224797 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 10:04:56.224883
795 10:04:56.228016 [CATrainingPosCal] consider 1 rank data
796 10:04:56.231331 u2DelayCellTimex100 = 270/100 ps
797 10:04:56.234623 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
798 10:04:56.237603 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
799 10:04:56.241356 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 10:04:56.244073 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 10:04:56.250901 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
802 10:04:56.254081 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 10:04:56.254182
804 10:04:56.257447 CA PerBit enable=1, Macro0, CA PI delay=33
805 10:04:56.257540
806 10:04:56.260880 [CBTSetCACLKResult] CA Dly = 33
807 10:04:56.260958 CS Dly: 6 (0~37)
808 10:04:56.261024 ==
809 10:04:56.264166 Dram Type= 6, Freq= 0, CH_0, rank 1
810 10:04:56.270577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 10:04:56.270663 ==
812 10:04:56.274221 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 10:04:56.280680 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 10:04:56.290051 [CA 0] Center 37 (6~68) winsize 63
815 10:04:56.293059 [CA 1] Center 37 (7~68) winsize 62
816 10:04:56.296737 [CA 2] Center 34 (4~65) winsize 62
817 10:04:56.299679 [CA 3] Center 34 (4~65) winsize 62
818 10:04:56.302858 [CA 4] Center 33 (3~64) winsize 62
819 10:04:56.306385 [CA 5] Center 33 (3~64) winsize 62
820 10:04:56.306471
821 10:04:56.309779 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 10:04:56.309865
823 10:04:56.313155 [CATrainingPosCal] consider 2 rank data
824 10:04:56.316771 u2DelayCellTimex100 = 270/100 ps
825 10:04:56.319554 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
826 10:04:56.323203 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
827 10:04:56.330756 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 10:04:56.330840 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 10:04:56.334556 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
830 10:04:56.337653 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 10:04:56.341486
832 10:04:56.344833 CA PerBit enable=1, Macro0, CA PI delay=33
833 10:04:56.344925
834 10:04:56.344991 [CBTSetCACLKResult] CA Dly = 33
835 10:04:56.348454 CS Dly: 6 (0~38)
836 10:04:56.348539
837 10:04:56.352145 ----->DramcWriteLeveling(PI) begin...
838 10:04:56.352222 ==
839 10:04:56.355710 Dram Type= 6, Freq= 0, CH_0, rank 0
840 10:04:56.358831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 10:04:56.358909 ==
842 10:04:56.362599 Write leveling (Byte 0): 30 => 30
843 10:04:56.366216 Write leveling (Byte 1): 29 => 29
844 10:04:56.369228 DramcWriteLeveling(PI) end<-----
845 10:04:56.369305
846 10:04:56.369381 ==
847 10:04:56.372354 Dram Type= 6, Freq= 0, CH_0, rank 0
848 10:04:56.375950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 10:04:56.376027 ==
850 10:04:56.378750 [Gating] SW mode calibration
851 10:04:56.385855 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 10:04:56.392543 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 10:04:56.395465 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 10:04:56.399038 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 10:04:56.405615 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 10:04:56.408498 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
857 10:04:56.412315 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 10:04:56.418837 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 10:04:56.421679 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 10:04:56.425038 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 10:04:56.431640 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 10:04:56.435258 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 10:04:56.438430 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 10:04:56.445069 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 10:04:56.448469 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 10:04:56.452211 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 10:04:56.458320 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 10:04:56.461686 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 10:04:56.465136 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 10:04:56.471797 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
871 10:04:56.475418 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
872 10:04:56.478492 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 10:04:56.485107 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 10:04:56.488400 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 10:04:56.491442 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 10:04:56.498175 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 10:04:56.501384 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 10:04:56.504899 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 10:04:56.511491 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
880 10:04:56.514756 0 9 12 | B1->B0 | 3130 3434 | 1 1 | (0 0) (1 1)
881 10:04:56.518045 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 10:04:56.524534 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 10:04:56.528364 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 10:04:56.532274 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 10:04:56.535867 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 10:04:56.539724 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 10:04:56.546756 0 10 8 | B1->B0 | 3232 2c2c | 0 0 | (1 0) (0 0)
888 10:04:56.550166 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
889 10:04:56.553884 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 10:04:56.557353 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 10:04:56.564883 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 10:04:56.567836 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 10:04:56.571703 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 10:04:56.575413 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 10:04:56.579422 0 11 8 | B1->B0 | 2828 3636 | 0 0 | (1 1) (0 0)
896 10:04:56.586177 0 11 12 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
897 10:04:56.589619 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 10:04:56.593476 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 10:04:56.597140 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 10:04:56.603514 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 10:04:56.606575 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 10:04:56.610056 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 10:04:56.616551 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 10:04:56.620172 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 10:04:56.623284 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 10:04:56.630069 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 10:04:56.633476 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 10:04:56.636681 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 10:04:56.640162 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 10:04:56.647050 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 10:04:56.650930 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 10:04:56.654594 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 10:04:56.658547 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 10:04:56.666120 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 10:04:56.668798 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 10:04:56.672434 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 10:04:56.675801 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 10:04:56.682481 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 10:04:56.685951 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 10:04:56.689142 Total UI for P1: 0, mck2ui 16
921 10:04:56.692367 best dqsien dly found for B0: ( 0, 14, 4)
922 10:04:56.695737 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 10:04:56.698926 Total UI for P1: 0, mck2ui 16
924 10:04:56.701978 best dqsien dly found for B1: ( 0, 14, 8)
925 10:04:56.705875 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 10:04:56.709012 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 10:04:56.709127
928 10:04:56.716012 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 10:04:56.718827 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 10:04:56.718908 [Gating] SW calibration Done
931 10:04:56.718976 ==
932 10:04:56.722530 Dram Type= 6, Freq= 0, CH_0, rank 0
933 10:04:56.729633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 10:04:56.729736 ==
935 10:04:56.729805 RX Vref Scan: 0
936 10:04:56.729884
937 10:04:56.733042 RX Vref 0 -> 0, step: 1
938 10:04:56.733117
939 10:04:56.736406 RX Delay -130 -> 252, step: 16
940 10:04:56.739316 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 10:04:56.742697 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 10:04:56.746173 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 10:04:56.749607 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 10:04:56.755647 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 10:04:56.759482 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 10:04:56.762986 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 10:04:56.765815 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 10:04:56.772216 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 10:04:56.775984 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 10:04:56.779545 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 10:04:56.783027 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 10:04:56.785878 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
953 10:04:56.792618 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
954 10:04:56.795911 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 10:04:56.799040 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
956 10:04:56.799124 ==
957 10:04:56.802499 Dram Type= 6, Freq= 0, CH_0, rank 0
958 10:04:56.805956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 10:04:56.806041 ==
960 10:04:56.808932 DQS Delay:
961 10:04:56.809017 DQS0 = 0, DQS1 = 0
962 10:04:56.812423 DQM Delay:
963 10:04:56.812507 DQM0 = 87, DQM1 = 72
964 10:04:56.812618 DQ Delay:
965 10:04:56.815961 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 10:04:56.819527 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
967 10:04:56.822285 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
968 10:04:56.825989 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
969 10:04:56.826073
970 10:04:56.826168
971 10:04:56.828868 ==
972 10:04:56.832443 Dram Type= 6, Freq= 0, CH_0, rank 0
973 10:04:56.835521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 10:04:56.835606 ==
975 10:04:56.835673
976 10:04:56.835735
977 10:04:56.838887 TX Vref Scan disable
978 10:04:56.838970 == TX Byte 0 ==
979 10:04:56.842308 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 10:04:56.849002 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 10:04:56.849087 == TX Byte 1 ==
982 10:04:56.852417 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 10:04:56.859040 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 10:04:56.859152 ==
985 10:04:56.862252 Dram Type= 6, Freq= 0, CH_0, rank 0
986 10:04:56.865486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 10:04:56.865600 ==
988 10:04:56.878746 TX Vref=22, minBit 5, minWin=27, winSum=441
989 10:04:56.882282 TX Vref=24, minBit 8, minWin=27, winSum=445
990 10:04:56.885510 TX Vref=26, minBit 5, minWin=27, winSum=443
991 10:04:56.888583 TX Vref=28, minBit 10, minWin=27, winSum=447
992 10:04:56.893269 TX Vref=30, minBit 8, minWin=27, winSum=446
993 10:04:56.895501 TX Vref=32, minBit 4, minWin=27, winSum=447
994 10:04:56.902011 [TxChooseVref] Worse bit 10, Min win 27, Win sum 447, Final Vref 28
995 10:04:56.902123
996 10:04:56.905344 Final TX Range 1 Vref 28
997 10:04:56.905421
998 10:04:56.905486 ==
999 10:04:56.908644 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 10:04:56.911915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 10:04:56.912016 ==
1002 10:04:56.915285
1003 10:04:56.915385
1004 10:04:56.915517 TX Vref Scan disable
1005 10:04:56.919111 == TX Byte 0 ==
1006 10:04:56.922441 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1007 10:04:56.925418 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1008 10:04:56.928561 == TX Byte 1 ==
1009 10:04:56.932400 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 10:04:56.935284 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 10:04:56.938927
1012 10:04:56.939010 [DATLAT]
1013 10:04:56.939114 Freq=800, CH0 RK0
1014 10:04:56.939206
1015 10:04:56.942056 DATLAT Default: 0xa
1016 10:04:56.942153 0, 0xFFFF, sum = 0
1017 10:04:56.945739 1, 0xFFFF, sum = 0
1018 10:04:56.945825 2, 0xFFFF, sum = 0
1019 10:04:56.948644 3, 0xFFFF, sum = 0
1020 10:04:56.948744 4, 0xFFFF, sum = 0
1021 10:04:56.952040 5, 0xFFFF, sum = 0
1022 10:04:56.955196 6, 0xFFFF, sum = 0
1023 10:04:56.955274 7, 0xFFFF, sum = 0
1024 10:04:56.958467 8, 0xFFFF, sum = 0
1025 10:04:56.958562 9, 0x0, sum = 1
1026 10:04:56.958627 10, 0x0, sum = 2
1027 10:04:56.962313 11, 0x0, sum = 3
1028 10:04:56.962399 12, 0x0, sum = 4
1029 10:04:56.965721 best_step = 10
1030 10:04:56.965790
1031 10:04:56.965854 ==
1032 10:04:56.969521 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 10:04:56.973181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 10:04:56.973254 ==
1035 10:04:56.973315 RX Vref Scan: 1
1036 10:04:56.973382
1037 10:04:56.976759 Set Vref Range= 32 -> 127
1038 10:04:56.976854
1039 10:04:56.980711 RX Vref 32 -> 127, step: 1
1040 10:04:56.980839
1041 10:04:56.983708 RX Delay -111 -> 252, step: 8
1042 10:04:56.983791
1043 10:04:56.987413 Set Vref, RX VrefLevel [Byte0]: 32
1044 10:04:56.987499 [Byte1]: 32
1045 10:04:56.992059
1046 10:04:56.992143 Set Vref, RX VrefLevel [Byte0]: 33
1047 10:04:56.995656 [Byte1]: 33
1048 10:04:56.999055
1049 10:04:56.999153 Set Vref, RX VrefLevel [Byte0]: 34
1050 10:04:57.002791 [Byte1]: 34
1051 10:04:57.007280
1052 10:04:57.007366 Set Vref, RX VrefLevel [Byte0]: 35
1053 10:04:57.011020 [Byte1]: 35
1054 10:04:57.014640
1055 10:04:57.014740 Set Vref, RX VrefLevel [Byte0]: 36
1056 10:04:57.018429 [Byte1]: 36
1057 10:04:57.022802
1058 10:04:57.022888 Set Vref, RX VrefLevel [Byte0]: 37
1059 10:04:57.025843 [Byte1]: 37
1060 10:04:57.030052
1061 10:04:57.030135 Set Vref, RX VrefLevel [Byte0]: 38
1062 10:04:57.033459 [Byte1]: 38
1063 10:04:57.037878
1064 10:04:57.037978 Set Vref, RX VrefLevel [Byte0]: 39
1065 10:04:57.041036 [Byte1]: 39
1066 10:04:57.045905
1067 10:04:57.045985 Set Vref, RX VrefLevel [Byte0]: 40
1068 10:04:57.048865 [Byte1]: 40
1069 10:04:57.053722
1070 10:04:57.053802 Set Vref, RX VrefLevel [Byte0]: 41
1071 10:04:57.056211 [Byte1]: 41
1072 10:04:57.060634
1073 10:04:57.060719 Set Vref, RX VrefLevel [Byte0]: 42
1074 10:04:57.063890 [Byte1]: 42
1075 10:04:57.068760
1076 10:04:57.068841 Set Vref, RX VrefLevel [Byte0]: 43
1077 10:04:57.071825 [Byte1]: 43
1078 10:04:57.076397
1079 10:04:57.076473 Set Vref, RX VrefLevel [Byte0]: 44
1080 10:04:57.079102 [Byte1]: 44
1081 10:04:57.084328
1082 10:04:57.084401 Set Vref, RX VrefLevel [Byte0]: 45
1083 10:04:57.087227 [Byte1]: 45
1084 10:04:57.091190
1085 10:04:57.091290 Set Vref, RX VrefLevel [Byte0]: 46
1086 10:04:57.094620 [Byte1]: 46
1087 10:04:57.099324
1088 10:04:57.099436 Set Vref, RX VrefLevel [Byte0]: 47
1089 10:04:57.102246 [Byte1]: 47
1090 10:04:57.106415
1091 10:04:57.106519 Set Vref, RX VrefLevel [Byte0]: 48
1092 10:04:57.109782 [Byte1]: 48
1093 10:04:57.114101
1094 10:04:57.114205 Set Vref, RX VrefLevel [Byte0]: 49
1095 10:04:57.117406 [Byte1]: 49
1096 10:04:57.122209
1097 10:04:57.122318 Set Vref, RX VrefLevel [Byte0]: 50
1098 10:04:57.125759 [Byte1]: 50
1099 10:04:57.129740
1100 10:04:57.129824 Set Vref, RX VrefLevel [Byte0]: 51
1101 10:04:57.133428 [Byte1]: 51
1102 10:04:57.136853
1103 10:04:57.136937 Set Vref, RX VrefLevel [Byte0]: 52
1104 10:04:57.140483 [Byte1]: 52
1105 10:04:57.145139
1106 10:04:57.145254 Set Vref, RX VrefLevel [Byte0]: 53
1107 10:04:57.149127 [Byte1]: 53
1108 10:04:57.152339
1109 10:04:57.152436 Set Vref, RX VrefLevel [Byte0]: 54
1110 10:04:57.155924 [Byte1]: 54
1111 10:04:57.160048
1112 10:04:57.160132 Set Vref, RX VrefLevel [Byte0]: 55
1113 10:04:57.163873 [Byte1]: 55
1114 10:04:57.167594
1115 10:04:57.167677 Set Vref, RX VrefLevel [Byte0]: 56
1116 10:04:57.170872 [Byte1]: 56
1117 10:04:57.175452
1118 10:04:57.175535 Set Vref, RX VrefLevel [Byte0]: 57
1119 10:04:57.178612 [Byte1]: 57
1120 10:04:57.183543
1121 10:04:57.183654 Set Vref, RX VrefLevel [Byte0]: 58
1122 10:04:57.186623 [Byte1]: 58
1123 10:04:57.190820
1124 10:04:57.190959 Set Vref, RX VrefLevel [Byte0]: 59
1125 10:04:57.194530 [Byte1]: 59
1126 10:04:57.198469
1127 10:04:57.198553 Set Vref, RX VrefLevel [Byte0]: 60
1128 10:04:57.202249 [Byte1]: 60
1129 10:04:57.206148
1130 10:04:57.206260 Set Vref, RX VrefLevel [Byte0]: 61
1131 10:04:57.209365 [Byte1]: 61
1132 10:04:57.213702
1133 10:04:57.213799 Set Vref, RX VrefLevel [Byte0]: 62
1134 10:04:57.216697 [Byte1]: 62
1135 10:04:57.220976
1136 10:04:57.221088 Set Vref, RX VrefLevel [Byte0]: 63
1137 10:04:57.224792 [Byte1]: 63
1138 10:04:57.228818
1139 10:04:57.228895 Set Vref, RX VrefLevel [Byte0]: 64
1140 10:04:57.232295 [Byte1]: 64
1141 10:04:57.236732
1142 10:04:57.236838 Set Vref, RX VrefLevel [Byte0]: 65
1143 10:04:57.239887 [Byte1]: 65
1144 10:04:57.244275
1145 10:04:57.244353 Set Vref, RX VrefLevel [Byte0]: 66
1146 10:04:57.247473 [Byte1]: 66
1147 10:04:57.251497
1148 10:04:57.251600 Set Vref, RX VrefLevel [Byte0]: 67
1149 10:04:57.255261 [Byte1]: 67
1150 10:04:57.259661
1151 10:04:57.259737 Set Vref, RX VrefLevel [Byte0]: 68
1152 10:04:57.263008 [Byte1]: 68
1153 10:04:57.267054
1154 10:04:57.267158 Set Vref, RX VrefLevel [Byte0]: 69
1155 10:04:57.270784 [Byte1]: 69
1156 10:04:57.274949
1157 10:04:57.275031 Set Vref, RX VrefLevel [Byte0]: 70
1158 10:04:57.278192 [Byte1]: 70
1159 10:04:57.282910
1160 10:04:57.282983 Set Vref, RX VrefLevel [Byte0]: 71
1161 10:04:57.286117 [Byte1]: 71
1162 10:04:57.289864
1163 10:04:57.289962 Set Vref, RX VrefLevel [Byte0]: 72
1164 10:04:57.293380 [Byte1]: 72
1165 10:04:57.297419
1166 10:04:57.297524 Set Vref, RX VrefLevel [Byte0]: 73
1167 10:04:57.300941 [Byte1]: 73
1168 10:04:57.305184
1169 10:04:57.305260 Set Vref, RX VrefLevel [Byte0]: 74
1170 10:04:57.308109 [Byte1]: 74
1171 10:04:57.312872
1172 10:04:57.312974 Set Vref, RX VrefLevel [Byte0]: 75
1173 10:04:57.316752 [Byte1]: 75
1174 10:04:57.320042
1175 10:04:57.323508 Set Vref, RX VrefLevel [Byte0]: 76
1176 10:04:57.323584 [Byte1]: 76
1177 10:04:57.328064
1178 10:04:57.328142 Set Vref, RX VrefLevel [Byte0]: 77
1179 10:04:57.331419 [Byte1]: 77
1180 10:04:57.336186
1181 10:04:57.336263 Set Vref, RX VrefLevel [Byte0]: 78
1182 10:04:57.339573 [Byte1]: 78
1183 10:04:57.343621
1184 10:04:57.343727 Set Vref, RX VrefLevel [Byte0]: 79
1185 10:04:57.347384 [Byte1]: 79
1186 10:04:57.350853
1187 10:04:57.350955 Set Vref, RX VrefLevel [Byte0]: 80
1188 10:04:57.354523 [Byte1]: 80
1189 10:04:57.359268
1190 10:04:57.359344 Set Vref, RX VrefLevel [Byte0]: 81
1191 10:04:57.362416 [Byte1]: 81
1192 10:04:57.365956
1193 10:04:57.366030 Set Vref, RX VrefLevel [Byte0]: 82
1194 10:04:57.369496 [Byte1]: 82
1195 10:04:57.373716
1196 10:04:57.373815 Set Vref, RX VrefLevel [Byte0]: 83
1197 10:04:57.377532 [Byte1]: 83
1198 10:04:57.382267
1199 10:04:57.382364 Final RX Vref Byte 0 = 68 to rank0
1200 10:04:57.385900 Final RX Vref Byte 1 = 55 to rank0
1201 10:04:57.389362 Final RX Vref Byte 0 = 68 to rank1
1202 10:04:57.392616 Final RX Vref Byte 1 = 55 to rank1==
1203 10:04:57.396261 Dram Type= 6, Freq= 0, CH_0, rank 0
1204 10:04:57.400380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1205 10:04:57.400491 ==
1206 10:04:57.400613 DQS Delay:
1207 10:04:57.404490 DQS0 = 0, DQS1 = 0
1208 10:04:57.404617 DQM Delay:
1209 10:04:57.407345 DQM0 = 88, DQM1 = 75
1210 10:04:57.407444 DQ Delay:
1211 10:04:57.411025 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1212 10:04:57.414179 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1213 10:04:57.417645 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1214 10:04:57.421236 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1215 10:04:57.421323
1216 10:04:57.421399
1217 10:04:57.428627 [DQSOSCAuto] RK0, (LSB)MR18= 0x4122, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1218 10:04:57.432105 CH0 RK0: MR19=606, MR18=4122
1219 10:04:57.435574 CH0_RK0: MR19=0x606, MR18=0x4122, DQSOSC=393, MR23=63, INC=95, DEC=63
1220 10:04:57.435653
1221 10:04:57.439425 ----->DramcWriteLeveling(PI) begin...
1222 10:04:57.439547 ==
1223 10:04:57.442938 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 10:04:57.446914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1225 10:04:57.450309 ==
1226 10:04:57.450382 Write leveling (Byte 0): 32 => 32
1227 10:04:57.494239 Write leveling (Byte 1): 32 => 32
1228 10:04:57.495023 DramcWriteLeveling(PI) end<-----
1229 10:04:57.495121
1230 10:04:57.495186 ==
1231 10:04:57.495259 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 10:04:57.495508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 10:04:57.495575 ==
1234 10:04:57.495634 [Gating] SW mode calibration
1235 10:04:57.496047 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1236 10:04:57.496296 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1237 10:04:57.496380 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1238 10:04:57.496741 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1239 10:04:57.497593 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1240 10:04:57.508490 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 10:04:57.508839 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 10:04:57.508941 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 10:04:57.512505 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 10:04:57.515730 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 10:04:57.518713 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 10:04:57.525762 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 10:04:57.528942 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 10:04:57.531834 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 10:04:57.538899 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 10:04:57.542106 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 10:04:57.545559 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 10:04:57.552130 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 10:04:57.555434 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 10:04:57.558806 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1255 10:04:57.565412 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1256 10:04:57.568479 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 10:04:57.571939 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 10:04:57.578710 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 10:04:57.581509 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 10:04:57.585447 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 10:04:57.591824 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 10:04:57.595276 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 10:04:57.598508 0 9 8 | B1->B0 | 2323 2d2d | 1 1 | (1 1) (1 1)
1264 10:04:57.605467 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1265 10:04:57.608540 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1266 10:04:57.611816 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1267 10:04:57.614948 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1268 10:04:57.621649 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1269 10:04:57.624999 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1270 10:04:57.628296 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
1271 10:04:57.634912 0 10 8 | B1->B0 | 3030 2828 | 0 0 | (1 1) (1 0)
1272 10:04:57.638245 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 0)
1273 10:04:57.641777 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1274 10:04:57.648951 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1275 10:04:57.651673 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1276 10:04:57.655271 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1277 10:04:57.661645 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1278 10:04:57.665306 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1279 10:04:57.668257 0 11 8 | B1->B0 | 2727 3b3b | 0 0 | (1 1) (0 0)
1280 10:04:57.674683 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1281 10:04:57.678248 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 10:04:57.681271 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 10:04:57.687743 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 10:04:57.691344 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1285 10:04:57.694482 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 10:04:57.701329 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 10:04:57.704502 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1288 10:04:57.707665 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 10:04:57.714776 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 10:04:57.717505 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 10:04:57.721337 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 10:04:57.727580 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 10:04:57.730794 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 10:04:57.734245 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 10:04:57.740470 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 10:04:57.744298 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 10:04:57.747500 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 10:04:57.753814 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 10:04:57.757181 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1300 10:04:57.760832 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1301 10:04:57.767293 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1302 10:04:57.771002 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1303 10:04:57.773928 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1304 10:04:57.780802 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1305 10:04:57.780903 Total UI for P1: 0, mck2ui 16
1306 10:04:57.787118 best dqsien dly found for B0: ( 0, 14, 8)
1307 10:04:57.790500 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1308 10:04:57.794155 Total UI for P1: 0, mck2ui 16
1309 10:04:57.797101 best dqsien dly found for B1: ( 0, 14, 12)
1310 10:04:57.800224 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1311 10:04:57.803870 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1312 10:04:57.803954
1313 10:04:57.807442 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1314 10:04:57.810505 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1315 10:04:57.813693 [Gating] SW calibration Done
1316 10:04:57.813806 ==
1317 10:04:57.816824 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 10:04:57.821887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 10:04:57.823547 ==
1320 10:04:57.823629 RX Vref Scan: 0
1321 10:04:57.823695
1322 10:04:57.826642 RX Vref 0 -> 0, step: 1
1323 10:04:57.826725
1324 10:04:57.830248 RX Delay -130 -> 252, step: 16
1325 10:04:57.833403 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1326 10:04:57.836749 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1327 10:04:57.840093 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1328 10:04:57.843406 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1329 10:04:57.850299 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1330 10:04:57.853711 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1331 10:04:57.857003 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1332 10:04:57.860578 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1333 10:04:57.863327 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1334 10:04:57.870176 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1335 10:04:57.873201 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1336 10:04:57.877230 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1337 10:04:57.880155 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1338 10:04:57.886378 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1339 10:04:57.889698 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1340 10:04:57.892649 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1341 10:04:57.892754 ==
1342 10:04:57.896243 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 10:04:57.899774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 10:04:57.899857 ==
1345 10:04:57.902891 DQS Delay:
1346 10:04:57.902998 DQS0 = 0, DQS1 = 0
1347 10:04:57.906361 DQM Delay:
1348 10:04:57.906532 DQM0 = 86, DQM1 = 78
1349 10:04:57.906625 DQ Delay:
1350 10:04:57.909427 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1351 10:04:57.913076 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1352 10:04:57.916414 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1353 10:04:57.919468 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1354 10:04:57.919567
1355 10:04:57.919667
1356 10:04:57.922517 ==
1357 10:04:57.926463 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 10:04:57.929267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 10:04:57.929348 ==
1360 10:04:57.929456
1361 10:04:57.929549
1362 10:04:57.932833 TX Vref Scan disable
1363 10:04:57.932937 == TX Byte 0 ==
1364 10:04:57.938971 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1365 10:04:57.942478 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1366 10:04:57.942559 == TX Byte 1 ==
1367 10:04:57.949275 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1368 10:04:57.952368 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1369 10:04:57.952467 ==
1370 10:04:57.955673 Dram Type= 6, Freq= 0, CH_0, rank 1
1371 10:04:57.959308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 10:04:57.959390 ==
1373 10:04:57.972452 TX Vref=22, minBit 1, minWin=27, winSum=444
1374 10:04:57.975498 TX Vref=24, minBit 11, minWin=27, winSum=446
1375 10:04:57.978902 TX Vref=26, minBit 11, minWin=27, winSum=447
1376 10:04:57.982470 TX Vref=28, minBit 9, minWin=27, winSum=447
1377 10:04:57.985712 TX Vref=30, minBit 9, minWin=27, winSum=445
1378 10:04:57.992263 TX Vref=32, minBit 8, minWin=27, winSum=442
1379 10:04:57.995411 [TxChooseVref] Worse bit 11, Min win 27, Win sum 447, Final Vref 26
1380 10:04:57.995493
1381 10:04:57.998728 Final TX Range 1 Vref 26
1382 10:04:57.998809
1383 10:04:57.998873 ==
1384 10:04:58.001962 Dram Type= 6, Freq= 0, CH_0, rank 1
1385 10:04:58.005670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 10:04:58.008643 ==
1387 10:04:58.008723
1388 10:04:58.008804
1389 10:04:58.008865 TX Vref Scan disable
1390 10:04:58.013099 == TX Byte 0 ==
1391 10:04:58.015650 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1392 10:04:58.022492 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1393 10:04:58.022573 == TX Byte 1 ==
1394 10:04:58.025621 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1395 10:04:58.032732 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1396 10:04:58.032813
1397 10:04:58.032877 [DATLAT]
1398 10:04:58.032938 Freq=800, CH0 RK1
1399 10:04:58.032997
1400 10:04:58.035663 DATLAT Default: 0xa
1401 10:04:58.035743 0, 0xFFFF, sum = 0
1402 10:04:58.039470 1, 0xFFFF, sum = 0
1403 10:04:58.039553 2, 0xFFFF, sum = 0
1404 10:04:58.042339 3, 0xFFFF, sum = 0
1405 10:04:58.045900 4, 0xFFFF, sum = 0
1406 10:04:58.045982 5, 0xFFFF, sum = 0
1407 10:04:58.049134 6, 0xFFFF, sum = 0
1408 10:04:58.049217 7, 0xFFFF, sum = 0
1409 10:04:58.052437 8, 0xFFFF, sum = 0
1410 10:04:58.052542 9, 0x0, sum = 1
1411 10:04:58.055716 10, 0x0, sum = 2
1412 10:04:58.055798 11, 0x0, sum = 3
1413 10:04:58.055864 12, 0x0, sum = 4
1414 10:04:58.058798 best_step = 10
1415 10:04:58.058879
1416 10:04:58.058953 ==
1417 10:04:58.062425 Dram Type= 6, Freq= 0, CH_0, rank 1
1418 10:04:58.065713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 10:04:58.065823 ==
1420 10:04:58.068931 RX Vref Scan: 0
1421 10:04:58.069040
1422 10:04:58.069138 RX Vref 0 -> 0, step: 1
1423 10:04:58.072186
1424 10:04:58.072266 RX Delay -95 -> 252, step: 8
1425 10:04:58.079145 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1426 10:04:58.082782 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1427 10:04:58.085782 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1428 10:04:58.089327 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1429 10:04:58.092892 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1430 10:04:58.099009 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1431 10:04:58.102591 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1432 10:04:58.105769 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1433 10:04:58.109569 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1434 10:04:58.112339 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1435 10:04:58.119367 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1436 10:04:58.122694 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1437 10:04:58.125593 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1438 10:04:58.128969 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1439 10:04:58.135807 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1440 10:04:58.138700 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1441 10:04:58.138783 ==
1442 10:04:58.142424 Dram Type= 6, Freq= 0, CH_0, rank 1
1443 10:04:58.145487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 10:04:58.145571 ==
1445 10:04:58.145637 DQS Delay:
1446 10:04:58.149212 DQS0 = 0, DQS1 = 0
1447 10:04:58.149295 DQM Delay:
1448 10:04:58.152422 DQM0 = 86, DQM1 = 77
1449 10:04:58.152551 DQ Delay:
1450 10:04:58.155417 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1451 10:04:58.159265 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =96
1452 10:04:58.162237 DQ8 =68, DQ9 =60, DQ10 =80, DQ11 =68
1453 10:04:58.165824 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1454 10:04:58.165907
1455 10:04:58.165972
1456 10:04:58.175684 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d03, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1457 10:04:58.175770 CH0 RK1: MR19=606, MR18=3D03
1458 10:04:58.182326 CH0_RK1: MR19=0x606, MR18=0x3D03, DQSOSC=394, MR23=63, INC=95, DEC=63
1459 10:04:58.185671 [RxdqsGatingPostProcess] freq 800
1460 10:04:58.191903 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1461 10:04:58.195252 Pre-setting of DQS Precalculation
1462 10:04:58.198584 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1463 10:04:58.198668 ==
1464 10:04:58.202182 Dram Type= 6, Freq= 0, CH_1, rank 0
1465 10:04:58.205438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 10:04:58.209048 ==
1467 10:04:58.212173 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1468 10:04:58.218843 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1469 10:04:58.228433 [CA 0] Center 36 (6~67) winsize 62
1470 10:04:58.231217 [CA 1] Center 36 (6~67) winsize 62
1471 10:04:58.234388 [CA 2] Center 34 (4~65) winsize 62
1472 10:04:58.237005 [CA 3] Center 34 (3~65) winsize 63
1473 10:04:58.240534 [CA 4] Center 34 (4~65) winsize 62
1474 10:04:58.243775 [CA 5] Center 34 (3~65) winsize 63
1475 10:04:58.243883
1476 10:04:58.247306 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1477 10:04:58.247381
1478 10:04:58.250271 [CATrainingPosCal] consider 1 rank data
1479 10:04:58.253797 u2DelayCellTimex100 = 270/100 ps
1480 10:04:58.257416 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1481 10:04:58.263849 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1482 10:04:58.266856 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1483 10:04:58.270209 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1484 10:04:58.273476 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1485 10:04:58.276736 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1486 10:04:58.276819
1487 10:04:58.280080 CA PerBit enable=1, Macro0, CA PI delay=34
1488 10:04:58.280163
1489 10:04:58.283877 [CBTSetCACLKResult] CA Dly = 34
1490 10:04:58.287016 CS Dly: 5 (0~36)
1491 10:04:58.287098 ==
1492 10:04:58.290328 Dram Type= 6, Freq= 0, CH_1, rank 1
1493 10:04:58.293492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1494 10:04:58.293587 ==
1495 10:04:58.299630 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1496 10:04:58.303317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1497 10:04:58.313419 [CA 0] Center 36 (6~67) winsize 62
1498 10:04:58.316962 [CA 1] Center 36 (6~67) winsize 62
1499 10:04:58.320734 [CA 2] Center 34 (3~65) winsize 63
1500 10:04:58.323814 [CA 3] Center 34 (3~65) winsize 63
1501 10:04:58.327327 [CA 4] Center 34 (4~65) winsize 62
1502 10:04:58.330193 [CA 5] Center 34 (3~65) winsize 63
1503 10:04:58.330276
1504 10:04:58.333348 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1505 10:04:58.333431
1506 10:04:58.337107 [CATrainingPosCal] consider 2 rank data
1507 10:04:58.339829 u2DelayCellTimex100 = 270/100 ps
1508 10:04:58.343435 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1509 10:04:58.350396 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1510 10:04:58.353413 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1511 10:04:58.356384 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1512 10:04:58.359902 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1513 10:04:58.362869 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1514 10:04:58.362945
1515 10:04:58.366346 CA PerBit enable=1, Macro0, CA PI delay=34
1516 10:04:58.366421
1517 10:04:58.369570 [CBTSetCACLKResult] CA Dly = 34
1518 10:04:58.373028 CS Dly: 6 (0~38)
1519 10:04:58.373103
1520 10:04:58.376336 ----->DramcWriteLeveling(PI) begin...
1521 10:04:58.376420 ==
1522 10:04:58.379599 Dram Type= 6, Freq= 0, CH_1, rank 0
1523 10:04:58.383195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1524 10:04:58.383270 ==
1525 10:04:58.386544 Write leveling (Byte 0): 26 => 26
1526 10:04:58.389824 Write leveling (Byte 1): 31 => 31
1527 10:04:58.392933 DramcWriteLeveling(PI) end<-----
1528 10:04:58.393037
1529 10:04:58.393163 ==
1530 10:04:58.396773 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 10:04:58.400017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 10:04:58.400101 ==
1533 10:04:58.402669 [Gating] SW mode calibration
1534 10:04:58.409516 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1535 10:04:58.416020 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1536 10:04:58.419539 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1537 10:04:58.423278 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1538 10:04:58.429589 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1539 10:04:58.432929 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 10:04:58.436073 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 10:04:58.443027 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 10:04:58.446569 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 10:04:58.449526 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 10:04:58.455913 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 10:04:58.459470 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 10:04:58.462932 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 10:04:58.469381 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 10:04:58.472722 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 10:04:58.476374 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 10:04:58.482742 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 10:04:58.485757 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 10:04:58.489361 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1553 10:04:58.492748 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1554 10:04:58.498958 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 10:04:58.502448 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 10:04:58.505823 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 10:04:58.512380 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 10:04:58.515924 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 10:04:58.518989 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 10:04:58.525863 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 10:04:58.528888 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 10:04:58.532571 0 9 8 | B1->B0 | 2f2f 3232 | 1 0 | (0 0) (0 0)
1563 10:04:58.538967 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1564 10:04:58.542338 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1565 10:04:58.545834 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1566 10:04:58.552308 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1567 10:04:58.555767 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1568 10:04:58.559100 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1569 10:04:58.565581 0 10 4 | B1->B0 | 3333 3333 | 1 1 | (1 1) (0 0)
1570 10:04:58.569171 0 10 8 | B1->B0 | 2b2b 2525 | 0 0 | (1 0) (0 0)
1571 10:04:58.572289 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1572 10:04:58.578583 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1573 10:04:58.582216 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1574 10:04:58.585306 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1575 10:04:58.592425 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1576 10:04:58.595205 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1577 10:04:58.598417 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1578 10:04:58.605066 0 11 8 | B1->B0 | 3939 3d3d | 0 0 | (0 0) (0 0)
1579 10:04:58.608874 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 10:04:58.612314 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 10:04:58.618592 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 10:04:58.622308 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1583 10:04:58.625386 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 10:04:58.632006 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1585 10:04:58.635060 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1586 10:04:58.638606 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1587 10:04:58.644953 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 10:04:58.648084 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 10:04:58.652176 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 10:04:58.658533 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 10:04:58.661562 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 10:04:58.664959 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 10:04:58.668188 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 10:04:58.674599 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 10:04:58.678265 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 10:04:58.681600 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1597 10:04:58.688381 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1598 10:04:58.691466 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1599 10:04:58.694936 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1600 10:04:58.701120 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1601 10:04:58.705046 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1602 10:04:58.707940 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1603 10:04:58.711232 Total UI for P1: 0, mck2ui 16
1604 10:04:58.715004 best dqsien dly found for B0: ( 0, 14, 4)
1605 10:04:58.721501 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1606 10:04:58.724558 Total UI for P1: 0, mck2ui 16
1607 10:04:58.728301 best dqsien dly found for B1: ( 0, 14, 8)
1608 10:04:58.731040 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1609 10:04:58.734404 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1610 10:04:58.734487
1611 10:04:58.737603 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1612 10:04:58.741353 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1613 10:04:58.744718 [Gating] SW calibration Done
1614 10:04:58.744805 ==
1615 10:04:58.747915 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 10:04:58.751305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 10:04:58.751399 ==
1618 10:04:58.754611 RX Vref Scan: 0
1619 10:04:58.754695
1620 10:04:58.754799 RX Vref 0 -> 0, step: 1
1621 10:04:58.754912
1622 10:04:58.757798 RX Delay -130 -> 252, step: 16
1623 10:04:58.764184 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1624 10:04:58.767481 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1625 10:04:58.771304 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1626 10:04:58.774559 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1627 10:04:58.777553 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1628 10:04:58.784220 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1629 10:04:58.787461 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1630 10:04:58.790746 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1631 10:04:58.794363 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1632 10:04:58.797505 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1633 10:04:58.803912 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1634 10:04:58.807293 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1635 10:04:58.811070 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1636 10:04:58.814054 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1637 10:04:58.817814 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1638 10:04:58.823837 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1639 10:04:58.823949 ==
1640 10:04:58.827400 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 10:04:58.830641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 10:04:58.830757 ==
1643 10:04:58.830825 DQS Delay:
1644 10:04:58.834065 DQS0 = 0, DQS1 = 0
1645 10:04:58.834150 DQM Delay:
1646 10:04:58.837280 DQM0 = 89, DQM1 = 79
1647 10:04:58.837365 DQ Delay:
1648 10:04:58.840773 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1649 10:04:58.843878 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1650 10:04:58.848189 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1651 10:04:58.850665 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1652 10:04:58.850769
1653 10:04:58.850868
1654 10:04:58.850958 ==
1655 10:04:58.853743 Dram Type= 6, Freq= 0, CH_1, rank 0
1656 10:04:58.857079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1657 10:04:58.861196 ==
1658 10:04:58.861277
1659 10:04:58.861341
1660 10:04:58.861399 TX Vref Scan disable
1661 10:04:58.863670 == TX Byte 0 ==
1662 10:04:58.866691 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1663 10:04:58.870480 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1664 10:04:58.873455 == TX Byte 1 ==
1665 10:04:58.876819 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1666 10:04:58.883638 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1667 10:04:58.883757 ==
1668 10:04:58.886800 Dram Type= 6, Freq= 0, CH_1, rank 0
1669 10:04:58.890342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1670 10:04:58.890466 ==
1671 10:04:58.902998 TX Vref=22, minBit 10, minWin=26, winSum=441
1672 10:04:58.906521 TX Vref=24, minBit 8, minWin=27, winSum=448
1673 10:04:58.909504 TX Vref=26, minBit 9, minWin=27, winSum=448
1674 10:04:58.913078 TX Vref=28, minBit 10, minWin=27, winSum=450
1675 10:04:58.916338 TX Vref=30, minBit 10, minWin=27, winSum=449
1676 10:04:58.922724 TX Vref=32, minBit 8, minWin=27, winSum=445
1677 10:04:58.926506 [TxChooseVref] Worse bit 10, Min win 27, Win sum 450, Final Vref 28
1678 10:04:58.926653
1679 10:04:58.929357 Final TX Range 1 Vref 28
1680 10:04:58.929439
1681 10:04:58.929503 ==
1682 10:04:58.932897 Dram Type= 6, Freq= 0, CH_1, rank 0
1683 10:04:58.939220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1684 10:04:58.939338 ==
1685 10:04:58.939418
1686 10:04:58.939480
1687 10:04:58.939540 TX Vref Scan disable
1688 10:04:58.943360 == TX Byte 0 ==
1689 10:04:58.946591 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1690 10:04:58.953452 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1691 10:04:58.953580 == TX Byte 1 ==
1692 10:04:58.956713 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1693 10:04:58.963099 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1694 10:04:58.963230
1695 10:04:58.963298 [DATLAT]
1696 10:04:58.963403 Freq=800, CH1 RK0
1697 10:04:58.963463
1698 10:04:58.966482 DATLAT Default: 0xa
1699 10:04:58.966563 0, 0xFFFF, sum = 0
1700 10:04:58.969864 1, 0xFFFF, sum = 0
1701 10:04:58.969951 2, 0xFFFF, sum = 0
1702 10:04:58.973113 3, 0xFFFF, sum = 0
1703 10:04:58.976436 4, 0xFFFF, sum = 0
1704 10:04:58.976590 5, 0xFFFF, sum = 0
1705 10:04:58.979705 6, 0xFFFF, sum = 0
1706 10:04:58.979815 7, 0xFFFF, sum = 0
1707 10:04:58.982856 8, 0xFFFF, sum = 0
1708 10:04:58.982963 9, 0x0, sum = 1
1709 10:04:58.986169 10, 0x0, sum = 2
1710 10:04:58.986253 11, 0x0, sum = 3
1711 10:04:58.986317 12, 0x0, sum = 4
1712 10:04:58.989343 best_step = 10
1713 10:04:58.989463
1714 10:04:58.989587 ==
1715 10:04:58.993096 Dram Type= 6, Freq= 0, CH_1, rank 0
1716 10:04:58.996211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1717 10:04:58.996343 ==
1718 10:04:58.999824 RX Vref Scan: 1
1719 10:04:58.999928
1720 10:04:59.002724 Set Vref Range= 32 -> 127
1721 10:04:59.002828
1722 10:04:59.002926 RX Vref 32 -> 127, step: 1
1723 10:04:59.003056
1724 10:04:59.006022 RX Delay -95 -> 252, step: 8
1725 10:04:59.006111
1726 10:04:59.009682 Set Vref, RX VrefLevel [Byte0]: 32
1727 10:04:59.013022 [Byte1]: 32
1728 10:04:59.013119
1729 10:04:59.016324 Set Vref, RX VrefLevel [Byte0]: 33
1730 10:04:59.019986 [Byte1]: 33
1731 10:04:59.023448
1732 10:04:59.023554 Set Vref, RX VrefLevel [Byte0]: 34
1733 10:04:59.027319 [Byte1]: 34
1734 10:04:59.031544
1735 10:04:59.031654 Set Vref, RX VrefLevel [Byte0]: 35
1736 10:04:59.034351 [Byte1]: 35
1737 10:04:59.038728
1738 10:04:59.038833 Set Vref, RX VrefLevel [Byte0]: 36
1739 10:04:59.042203 [Byte1]: 36
1740 10:04:59.046519
1741 10:04:59.046625 Set Vref, RX VrefLevel [Byte0]: 37
1742 10:04:59.049620 [Byte1]: 37
1743 10:04:59.054377
1744 10:04:59.054483 Set Vref, RX VrefLevel [Byte0]: 38
1745 10:04:59.057326 [Byte1]: 38
1746 10:04:59.061980
1747 10:04:59.062120 Set Vref, RX VrefLevel [Byte0]: 39
1748 10:04:59.065146 [Byte1]: 39
1749 10:04:59.069092
1750 10:04:59.069199 Set Vref, RX VrefLevel [Byte0]: 40
1751 10:04:59.072429 [Byte1]: 40
1752 10:04:59.077021
1753 10:04:59.077129 Set Vref, RX VrefLevel [Byte0]: 41
1754 10:04:59.080205 [Byte1]: 41
1755 10:04:59.084530
1756 10:04:59.084638 Set Vref, RX VrefLevel [Byte0]: 42
1757 10:04:59.087401 [Byte1]: 42
1758 10:04:59.092161
1759 10:04:59.092262 Set Vref, RX VrefLevel [Byte0]: 43
1760 10:04:59.095157 [Byte1]: 43
1761 10:04:59.099424
1762 10:04:59.099585 Set Vref, RX VrefLevel [Byte0]: 44
1763 10:04:59.102933 [Byte1]: 44
1764 10:04:59.107449
1765 10:04:59.107578 Set Vref, RX VrefLevel [Byte0]: 45
1766 10:04:59.110470 [Byte1]: 45
1767 10:04:59.114601
1768 10:04:59.114703 Set Vref, RX VrefLevel [Byte0]: 46
1769 10:04:59.118093 [Byte1]: 46
1770 10:04:59.122255
1771 10:04:59.122363 Set Vref, RX VrefLevel [Byte0]: 47
1772 10:04:59.125575 [Byte1]: 47
1773 10:04:59.130296
1774 10:04:59.130411 Set Vref, RX VrefLevel [Byte0]: 48
1775 10:04:59.133458 [Byte1]: 48
1776 10:04:59.137341
1777 10:04:59.137469 Set Vref, RX VrefLevel [Byte0]: 49
1778 10:04:59.140851 [Byte1]: 49
1779 10:04:59.145413
1780 10:04:59.145520 Set Vref, RX VrefLevel [Byte0]: 50
1781 10:04:59.148692 [Byte1]: 50
1782 10:04:59.152631
1783 10:04:59.152734 Set Vref, RX VrefLevel [Byte0]: 51
1784 10:04:59.156151 [Byte1]: 51
1785 10:04:59.160179
1786 10:04:59.160277 Set Vref, RX VrefLevel [Byte0]: 52
1787 10:04:59.164030 [Byte1]: 52
1788 10:04:59.168007
1789 10:04:59.168107 Set Vref, RX VrefLevel [Byte0]: 53
1790 10:04:59.171719 [Byte1]: 53
1791 10:04:59.175920
1792 10:04:59.176024 Set Vref, RX VrefLevel [Byte0]: 54
1793 10:04:59.178883 [Byte1]: 54
1794 10:04:59.183652
1795 10:04:59.183786 Set Vref, RX VrefLevel [Byte0]: 55
1796 10:04:59.186356 [Byte1]: 55
1797 10:04:59.190949
1798 10:04:59.191083 Set Vref, RX VrefLevel [Byte0]: 56
1799 10:04:59.194145 [Byte1]: 56
1800 10:04:59.198240
1801 10:04:59.198351 Set Vref, RX VrefLevel [Byte0]: 57
1802 10:04:59.202026 [Byte1]: 57
1803 10:04:59.206186
1804 10:04:59.206295 Set Vref, RX VrefLevel [Byte0]: 58
1805 10:04:59.209200 [Byte1]: 58
1806 10:04:59.213595
1807 10:04:59.213703 Set Vref, RX VrefLevel [Byte0]: 59
1808 10:04:59.216832 [Byte1]: 59
1809 10:04:59.221465
1810 10:04:59.221592 Set Vref, RX VrefLevel [Byte0]: 60
1811 10:04:59.224694 [Byte1]: 60
1812 10:04:59.228890
1813 10:04:59.229010 Set Vref, RX VrefLevel [Byte0]: 61
1814 10:04:59.232168 [Byte1]: 61
1815 10:04:59.236427
1816 10:04:59.236606 Set Vref, RX VrefLevel [Byte0]: 62
1817 10:04:59.239611 [Byte1]: 62
1818 10:04:59.243702
1819 10:04:59.243802 Set Vref, RX VrefLevel [Byte0]: 63
1820 10:04:59.247240 [Byte1]: 63
1821 10:04:59.251465
1822 10:04:59.251580 Set Vref, RX VrefLevel [Byte0]: 64
1823 10:04:59.255281 [Byte1]: 64
1824 10:04:59.259169
1825 10:04:59.259284 Set Vref, RX VrefLevel [Byte0]: 65
1826 10:04:59.262414 [Byte1]: 65
1827 10:04:59.266911
1828 10:04:59.267012 Set Vref, RX VrefLevel [Byte0]: 66
1829 10:04:59.270080 [Byte1]: 66
1830 10:04:59.274453
1831 10:04:59.274548 Set Vref, RX VrefLevel [Byte0]: 67
1832 10:04:59.278154 [Byte1]: 67
1833 10:04:59.281923
1834 10:04:59.282030 Set Vref, RX VrefLevel [Byte0]: 68
1835 10:04:59.285236 [Byte1]: 68
1836 10:04:59.289659
1837 10:04:59.289788 Set Vref, RX VrefLevel [Byte0]: 69
1838 10:04:59.293029 [Byte1]: 69
1839 10:04:59.297415
1840 10:04:59.297538 Set Vref, RX VrefLevel [Byte0]: 70
1841 10:04:59.301142 [Byte1]: 70
1842 10:04:59.304982
1843 10:04:59.305171 Set Vref, RX VrefLevel [Byte0]: 71
1844 10:04:59.308011 [Byte1]: 71
1845 10:04:59.312140
1846 10:04:59.312285 Set Vref, RX VrefLevel [Byte0]: 72
1847 10:04:59.315724 [Byte1]: 72
1848 10:04:59.319822
1849 10:04:59.319958 Set Vref, RX VrefLevel [Byte0]: 73
1850 10:04:59.322993 [Byte1]: 73
1851 10:04:59.328014
1852 10:04:59.331044 Set Vref, RX VrefLevel [Byte0]: 74
1853 10:04:59.334160 [Byte1]: 74
1854 10:04:59.334289
1855 10:04:59.337167 Set Vref, RX VrefLevel [Byte0]: 75
1856 10:04:59.340451 [Byte1]: 75
1857 10:04:59.340609
1858 10:04:59.344133 Set Vref, RX VrefLevel [Byte0]: 76
1859 10:04:59.347285 [Byte1]: 76
1860 10:04:59.347384
1861 10:04:59.350377 Set Vref, RX VrefLevel [Byte0]: 77
1862 10:04:59.353969 [Byte1]: 77
1863 10:04:59.357959
1864 10:04:59.358071 Set Vref, RX VrefLevel [Byte0]: 78
1865 10:04:59.361527 [Byte1]: 78
1866 10:04:59.365529
1867 10:04:59.365659 Final RX Vref Byte 0 = 56 to rank0
1868 10:04:59.369030 Final RX Vref Byte 1 = 67 to rank0
1869 10:04:59.372705 Final RX Vref Byte 0 = 56 to rank1
1870 10:04:59.375674 Final RX Vref Byte 1 = 67 to rank1==
1871 10:04:59.378863 Dram Type= 6, Freq= 0, CH_1, rank 0
1872 10:04:59.385244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1873 10:04:59.385397 ==
1874 10:04:59.385477 DQS Delay:
1875 10:04:59.385540 DQS0 = 0, DQS1 = 0
1876 10:04:59.388733 DQM Delay:
1877 10:04:59.388824 DQM0 = 87, DQM1 = 78
1878 10:04:59.392647 DQ Delay:
1879 10:04:59.395538 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1880 10:04:59.398735 DQ4 =84, DQ5 =100, DQ6 =100, DQ7 =80
1881 10:04:59.401696 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1882 10:04:59.405059 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1883 10:04:59.405185
1884 10:04:59.405316
1885 10:04:59.411767 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1886 10:04:59.415277 CH1 RK0: MR19=606, MR18=2E19
1887 10:04:59.421781 CH1_RK0: MR19=0x606, MR18=0x2E19, DQSOSC=398, MR23=63, INC=93, DEC=62
1888 10:04:59.421906
1889 10:04:59.425035 ----->DramcWriteLeveling(PI) begin...
1890 10:04:59.425120 ==
1891 10:04:59.428209 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 10:04:59.431548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 10:04:59.431651 ==
1894 10:04:59.435109 Write leveling (Byte 0): 26 => 26
1895 10:04:59.438357 Write leveling (Byte 1): 30 => 30
1896 10:04:59.441582 DramcWriteLeveling(PI) end<-----
1897 10:04:59.441675
1898 10:04:59.441767 ==
1899 10:04:59.445319 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 10:04:59.448249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 10:04:59.448346 ==
1902 10:04:59.452018 [Gating] SW mode calibration
1903 10:04:59.458528 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1904 10:04:59.465029 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1905 10:04:59.468260 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1906 10:04:59.475529 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1907 10:04:59.478296 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 10:04:59.481473 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 10:04:59.488615 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 10:04:59.491521 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 10:04:59.494681 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 10:04:59.498350 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 10:04:59.504885 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 10:04:59.508210 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 10:04:59.511260 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 10:04:59.517851 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 10:04:59.521770 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 10:04:59.524438 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 10:04:59.531474 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 10:04:59.534817 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 10:04:59.538104 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 10:04:59.544889 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1923 10:04:59.548115 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 10:04:59.551132 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 10:04:59.557723 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 10:04:59.561378 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 10:04:59.564159 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 10:04:59.571190 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 10:04:59.574905 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 10:04:59.578030 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1931 10:04:59.584533 0 9 8 | B1->B0 | 3333 2b2b | 0 1 | (0 0) (1 1)
1932 10:04:59.588202 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1933 10:04:59.590886 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1934 10:04:59.597367 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1935 10:04:59.600738 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1936 10:04:59.604084 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1937 10:04:59.610860 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1938 10:04:59.613975 0 10 4 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
1939 10:04:59.617245 0 10 8 | B1->B0 | 2727 2e2e | 0 0 | (0 0) (0 0)
1940 10:04:59.623865 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1941 10:04:59.627246 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1942 10:04:59.630655 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1943 10:04:59.637256 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1944 10:04:59.640561 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1945 10:04:59.643719 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1946 10:04:59.650504 0 11 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1947 10:04:59.653987 0 11 8 | B1->B0 | 4141 3535 | 0 1 | (1 1) (0 0)
1948 10:04:59.657455 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1949 10:04:59.663666 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1950 10:04:59.667228 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1951 10:04:59.670739 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1952 10:04:59.676816 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1953 10:04:59.680313 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1954 10:04:59.683521 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1955 10:04:59.690223 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 10:04:59.693462 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 10:04:59.696708 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1958 10:04:59.703415 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1959 10:04:59.707124 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1960 10:04:59.710015 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1961 10:04:59.713868 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1962 10:04:59.720286 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1963 10:04:59.723391 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1964 10:04:59.727106 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1965 10:04:59.733502 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1966 10:04:59.737199 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1967 10:04:59.740081 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1968 10:04:59.747068 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1969 10:04:59.750387 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1970 10:04:59.753377 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1971 10:04:59.760397 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1972 10:04:59.763741 Total UI for P1: 0, mck2ui 16
1973 10:04:59.766843 best dqsien dly found for B1: ( 0, 14, 4)
1974 10:04:59.770257 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1975 10:04:59.773283 Total UI for P1: 0, mck2ui 16
1976 10:04:59.776632 best dqsien dly found for B0: ( 0, 14, 8)
1977 10:04:59.779678 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1978 10:04:59.783482 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1979 10:04:59.783589
1980 10:04:59.786548 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1981 10:04:59.790387 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1982 10:04:59.793190 [Gating] SW calibration Done
1983 10:04:59.793291 ==
1984 10:04:59.796655 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 10:04:59.800306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 10:04:59.803353 ==
1987 10:04:59.803459 RX Vref Scan: 0
1988 10:04:59.803529
1989 10:04:59.806610 RX Vref 0 -> 0, step: 1
1990 10:04:59.806704
1991 10:04:59.810281 RX Delay -130 -> 252, step: 16
1992 10:04:59.812963 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1993 10:04:59.816838 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1994 10:04:59.819996 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1995 10:04:59.822836 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1996 10:04:59.829417 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1997 10:04:59.833242 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1998 10:04:59.836200 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1999 10:04:59.839807 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
2000 10:04:59.843011 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
2001 10:04:59.849371 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
2002 10:04:59.852892 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
2003 10:04:59.856448 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
2004 10:04:59.859743 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
2005 10:04:59.862908 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
2006 10:04:59.869477 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
2007 10:04:59.872803 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
2008 10:04:59.872905 ==
2009 10:04:59.876301 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 10:04:59.879240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 10:04:59.879321 ==
2012 10:04:59.882614 DQS Delay:
2013 10:04:59.882698 DQS0 = 0, DQS1 = 0
2014 10:04:59.882765 DQM Delay:
2015 10:04:59.885924 DQM0 = 86, DQM1 = 78
2016 10:04:59.886038 DQ Delay:
2017 10:04:59.889442 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
2018 10:04:59.892693 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2019 10:04:59.895821 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2020 10:04:59.899203 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2021 10:04:59.899295
2022 10:04:59.899396
2023 10:04:59.902595 ==
2024 10:04:59.902690 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 10:04:59.909187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 10:04:59.909289 ==
2027 10:04:59.909377
2028 10:04:59.909458
2029 10:04:59.912410 TX Vref Scan disable
2030 10:04:59.912499 == TX Byte 0 ==
2031 10:04:59.915966 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2032 10:04:59.922485 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2033 10:04:59.922575 == TX Byte 1 ==
2034 10:04:59.925614 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2035 10:04:59.932784 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2036 10:04:59.932875 ==
2037 10:04:59.935774 Dram Type= 6, Freq= 0, CH_1, rank 1
2038 10:04:59.938959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2039 10:04:59.939046 ==
2040 10:04:59.952378 TX Vref=22, minBit 9, minWin=26, winSum=441
2041 10:04:59.955695 TX Vref=24, minBit 1, minWin=27, winSum=446
2042 10:04:59.958964 TX Vref=26, minBit 1, minWin=27, winSum=446
2043 10:04:59.962479 TX Vref=28, minBit 1, minWin=27, winSum=447
2044 10:04:59.965403 TX Vref=30, minBit 0, minWin=28, winSum=449
2045 10:04:59.972401 TX Vref=32, minBit 8, minWin=27, winSum=451
2046 10:04:59.975401 [TxChooseVref] Worse bit 0, Min win 28, Win sum 449, Final Vref 30
2047 10:04:59.975501
2048 10:04:59.978508 Final TX Range 1 Vref 30
2049 10:04:59.978593
2050 10:04:59.978661 ==
2051 10:04:59.982316 Dram Type= 6, Freq= 0, CH_1, rank 1
2052 10:04:59.985445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2053 10:04:59.988626 ==
2054 10:04:59.988717
2055 10:04:59.988784
2056 10:04:59.988846 TX Vref Scan disable
2057 10:04:59.992208 == TX Byte 0 ==
2058 10:04:59.995541 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2059 10:05:00.002323 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2060 10:05:00.002432 == TX Byte 1 ==
2061 10:05:00.005604 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2062 10:05:00.012512 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2063 10:05:00.012663
2064 10:05:00.012757 [DATLAT]
2065 10:05:00.012839 Freq=800, CH1 RK1
2066 10:05:00.012918
2067 10:05:00.015353 DATLAT Default: 0xa
2068 10:05:00.015453 0, 0xFFFF, sum = 0
2069 10:05:00.019089 1, 0xFFFF, sum = 0
2070 10:05:00.022039 2, 0xFFFF, sum = 0
2071 10:05:00.022134 3, 0xFFFF, sum = 0
2072 10:05:00.026006 4, 0xFFFF, sum = 0
2073 10:05:00.026200 5, 0xFFFF, sum = 0
2074 10:05:00.028763 6, 0xFFFF, sum = 0
2075 10:05:00.028872 7, 0xFFFF, sum = 0
2076 10:05:00.032153 8, 0xFFFF, sum = 0
2077 10:05:00.032297 9, 0x0, sum = 1
2078 10:05:00.035330 10, 0x0, sum = 2
2079 10:05:00.035433 11, 0x0, sum = 3
2080 10:05:00.035531 12, 0x0, sum = 4
2081 10:05:00.038555 best_step = 10
2082 10:05:00.038646
2083 10:05:00.038710 ==
2084 10:05:00.042223 Dram Type= 6, Freq= 0, CH_1, rank 1
2085 10:05:00.045606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2086 10:05:00.045688 ==
2087 10:05:00.048552 RX Vref Scan: 0
2088 10:05:00.048648
2089 10:05:00.051593 RX Vref 0 -> 0, step: 1
2090 10:05:00.051669
2091 10:05:00.051756 RX Delay -95 -> 252, step: 8
2092 10:05:00.058954 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2093 10:05:00.062398 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2094 10:05:00.065594 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2095 10:05:00.069278 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2096 10:05:00.072262 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2097 10:05:00.078717 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2098 10:05:00.082010 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2099 10:05:00.085549 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2100 10:05:00.088499 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2101 10:05:00.095435 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2102 10:05:00.098504 iDelay=217, Bit 10, Center 80 (-31 ~ 192) 224
2103 10:05:00.102395 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2104 10:05:00.105193 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2105 10:05:00.108654 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2106 10:05:00.115154 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2107 10:05:00.118421 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2108 10:05:00.118532 ==
2109 10:05:00.121857 Dram Type= 6, Freq= 0, CH_1, rank 1
2110 10:05:00.125209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2111 10:05:00.125327 ==
2112 10:05:00.128805 DQS Delay:
2113 10:05:00.128923 DQS0 = 0, DQS1 = 0
2114 10:05:00.129020 DQM Delay:
2115 10:05:00.131531 DQM0 = 87, DQM1 = 79
2116 10:05:00.131630 DQ Delay:
2117 10:05:00.135025 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2118 10:05:00.138898 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2119 10:05:00.142267 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
2120 10:05:00.144955 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2121 10:05:00.145065
2122 10:05:00.145162
2123 10:05:00.155186 [DQSOSCAuto] RK1, (LSB)MR18= 0x180f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 403 ps
2124 10:05:00.158464 CH1 RK1: MR19=606, MR18=180F
2125 10:05:00.161577 CH1_RK1: MR19=0x606, MR18=0x180F, DQSOSC=403, MR23=63, INC=90, DEC=60
2126 10:05:00.164942 [RxdqsGatingPostProcess] freq 800
2127 10:05:00.171491 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2128 10:05:00.174736 Pre-setting of DQS Precalculation
2129 10:05:00.178303 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2130 10:05:00.188425 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2131 10:05:00.194917 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2132 10:05:00.195064
2133 10:05:00.195174
2134 10:05:00.198100 [Calibration Summary] 1600 Mbps
2135 10:05:00.198256 CH 0, Rank 0
2136 10:05:00.201699 SW Impedance : PASS
2137 10:05:00.201810 DUTY Scan : NO K
2138 10:05:00.205145 ZQ Calibration : PASS
2139 10:05:00.207843 Jitter Meter : NO K
2140 10:05:00.207947 CBT Training : PASS
2141 10:05:00.211496 Write leveling : PASS
2142 10:05:00.214407 RX DQS gating : PASS
2143 10:05:00.214501 RX DQ/DQS(RDDQC) : PASS
2144 10:05:00.217766 TX DQ/DQS : PASS
2145 10:05:00.221182 RX DATLAT : PASS
2146 10:05:00.221307 RX DQ/DQS(Engine): PASS
2147 10:05:00.224873 TX OE : NO K
2148 10:05:00.224968 All Pass.
2149 10:05:00.225036
2150 10:05:00.228121 CH 0, Rank 1
2151 10:05:00.228223 SW Impedance : PASS
2152 10:05:00.231196 DUTY Scan : NO K
2153 10:05:00.231349 ZQ Calibration : PASS
2154 10:05:00.234891 Jitter Meter : NO K
2155 10:05:00.237799 CBT Training : PASS
2156 10:05:00.237891 Write leveling : PASS
2157 10:05:00.241836 RX DQS gating : PASS
2158 10:05:00.244831 RX DQ/DQS(RDDQC) : PASS
2159 10:05:00.244917 TX DQ/DQS : PASS
2160 10:05:00.247983 RX DATLAT : PASS
2161 10:05:00.250999 RX DQ/DQS(Engine): PASS
2162 10:05:00.251087 TX OE : NO K
2163 10:05:00.254282 All Pass.
2164 10:05:00.254385
2165 10:05:00.254454 CH 1, Rank 0
2166 10:05:00.257980 SW Impedance : PASS
2167 10:05:00.258065 DUTY Scan : NO K
2168 10:05:00.261007 ZQ Calibration : PASS
2169 10:05:00.264163 Jitter Meter : NO K
2170 10:05:00.264247 CBT Training : PASS
2171 10:05:00.267732 Write leveling : PASS
2172 10:05:00.270789 RX DQS gating : PASS
2173 10:05:00.270873 RX DQ/DQS(RDDQC) : PASS
2174 10:05:00.274365 TX DQ/DQS : PASS
2175 10:05:00.277555 RX DATLAT : PASS
2176 10:05:00.277638 RX DQ/DQS(Engine): PASS
2177 10:05:00.281044 TX OE : NO K
2178 10:05:00.281128 All Pass.
2179 10:05:00.281194
2180 10:05:00.284002 CH 1, Rank 1
2181 10:05:00.284084 SW Impedance : PASS
2182 10:05:00.287812 DUTY Scan : NO K
2183 10:05:00.287896 ZQ Calibration : PASS
2184 10:05:00.291034 Jitter Meter : NO K
2185 10:05:00.294425 CBT Training : PASS
2186 10:05:00.294512 Write leveling : PASS
2187 10:05:00.297309 RX DQS gating : PASS
2188 10:05:00.300912 RX DQ/DQS(RDDQC) : PASS
2189 10:05:00.301000 TX DQ/DQS : PASS
2190 10:05:00.304318 RX DATLAT : PASS
2191 10:05:00.307347 RX DQ/DQS(Engine): PASS
2192 10:05:00.307458 TX OE : NO K
2193 10:05:00.310810 All Pass.
2194 10:05:00.310894
2195 10:05:00.310960 DramC Write-DBI off
2196 10:05:00.314512 PER_BANK_REFRESH: Hybrid Mode
2197 10:05:00.314597 TX_TRACKING: ON
2198 10:05:00.317798 [GetDramInforAfterCalByMRR] Vendor 6.
2199 10:05:00.324266 [GetDramInforAfterCalByMRR] Revision 606.
2200 10:05:00.327097 [GetDramInforAfterCalByMRR] Revision 2 0.
2201 10:05:00.327181 MR0 0x3b3b
2202 10:05:00.327248 MR8 0x5151
2203 10:05:00.330474 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2204 10:05:00.333901
2205 10:05:00.333985 MR0 0x3b3b
2206 10:05:00.334052 MR8 0x5151
2207 10:05:00.337649 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2208 10:05:00.337736
2209 10:05:00.347009 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2210 10:05:00.350999 [FAST_K] Save calibration result to emmc
2211 10:05:00.353703 [FAST_K] Save calibration result to emmc
2212 10:05:00.357523 dram_init: config_dvfs: 1
2213 10:05:00.360485 dramc_set_vcore_voltage set vcore to 662500
2214 10:05:00.363858 Read voltage for 1200, 2
2215 10:05:00.363963 Vio18 = 0
2216 10:05:00.364033 Vcore = 662500
2217 10:05:00.367077 Vdram = 0
2218 10:05:00.367160 Vddq = 0
2219 10:05:00.367228 Vmddr = 0
2220 10:05:00.373942 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2221 10:05:00.377008 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2222 10:05:00.380460 MEM_TYPE=3, freq_sel=15
2223 10:05:00.383490 sv_algorithm_assistance_LP4_1600
2224 10:05:00.387501 ============ PULL DRAM RESETB DOWN ============
2225 10:05:00.390184 ========== PULL DRAM RESETB DOWN end =========
2226 10:05:00.397084 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2227 10:05:00.400381 ===================================
2228 10:05:00.403615 LPDDR4 DRAM CONFIGURATION
2229 10:05:00.406890 ===================================
2230 10:05:00.406987 EX_ROW_EN[0] = 0x0
2231 10:05:00.410678 EX_ROW_EN[1] = 0x0
2232 10:05:00.410771 LP4Y_EN = 0x0
2233 10:05:00.414095 WORK_FSP = 0x0
2234 10:05:00.414206 WL = 0x4
2235 10:05:00.416990 RL = 0x4
2236 10:05:00.417074 BL = 0x2
2237 10:05:00.419907 RPST = 0x0
2238 10:05:00.419991 RD_PRE = 0x0
2239 10:05:00.423411 WR_PRE = 0x1
2240 10:05:00.423498 WR_PST = 0x0
2241 10:05:00.426771 DBI_WR = 0x0
2242 10:05:00.426883 DBI_RD = 0x0
2243 10:05:00.429864 OTF = 0x1
2244 10:05:00.433505 ===================================
2245 10:05:00.436812 ===================================
2246 10:05:00.436916 ANA top config
2247 10:05:00.439944 ===================================
2248 10:05:00.443345 DLL_ASYNC_EN = 0
2249 10:05:00.446853 ALL_SLAVE_EN = 0
2250 10:05:00.449755 NEW_RANK_MODE = 1
2251 10:05:00.453473 DLL_IDLE_MODE = 1
2252 10:05:00.453559 LP45_APHY_COMB_EN = 1
2253 10:05:00.456415 TX_ODT_DIS = 1
2254 10:05:00.459589 NEW_8X_MODE = 1
2255 10:05:00.463128 ===================================
2256 10:05:00.466173 ===================================
2257 10:05:00.470358 data_rate = 2400
2258 10:05:00.473369 CKR = 1
2259 10:05:00.473460 DQ_P2S_RATIO = 8
2260 10:05:00.476269 ===================================
2261 10:05:00.479857 CA_P2S_RATIO = 8
2262 10:05:00.482913 DQ_CA_OPEN = 0
2263 10:05:00.486102 DQ_SEMI_OPEN = 0
2264 10:05:00.489615 CA_SEMI_OPEN = 0
2265 10:05:00.492765 CA_FULL_RATE = 0
2266 10:05:00.492869 DQ_CKDIV4_EN = 0
2267 10:05:00.496614 CA_CKDIV4_EN = 0
2268 10:05:00.499475 CA_PREDIV_EN = 0
2269 10:05:00.503287 PH8_DLY = 17
2270 10:05:00.506224 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2271 10:05:00.509532 DQ_AAMCK_DIV = 4
2272 10:05:00.509616 CA_AAMCK_DIV = 4
2273 10:05:00.512960 CA_ADMCK_DIV = 4
2274 10:05:00.516853 DQ_TRACK_CA_EN = 0
2275 10:05:00.519563 CA_PICK = 1200
2276 10:05:00.523090 CA_MCKIO = 1200
2277 10:05:00.526578 MCKIO_SEMI = 0
2278 10:05:00.529670 PLL_FREQ = 2366
2279 10:05:00.529762 DQ_UI_PI_RATIO = 32
2280 10:05:00.532756 CA_UI_PI_RATIO = 0
2281 10:05:00.536255 ===================================
2282 10:05:00.539720 ===================================
2283 10:05:00.543112 memory_type:LPDDR4
2284 10:05:00.546318 GP_NUM : 10
2285 10:05:00.546429 SRAM_EN : 1
2286 10:05:00.549526 MD32_EN : 0
2287 10:05:00.552646 ===================================
2288 10:05:00.552757 [ANA_INIT] >>>>>>>>>>>>>>
2289 10:05:00.556214 <<<<<< [CONFIGURE PHASE]: ANA_TX
2290 10:05:00.559719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2291 10:05:00.562831 ===================================
2292 10:05:00.566058 data_rate = 2400,PCW = 0X5b00
2293 10:05:00.569463 ===================================
2294 10:05:00.572891 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2295 10:05:00.579794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2296 10:05:00.586475 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2297 10:05:00.589178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2298 10:05:00.592699 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2299 10:05:00.595844 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2300 10:05:00.599904 [ANA_INIT] flow start
2301 10:05:00.600022 [ANA_INIT] PLL >>>>>>>>
2302 10:05:00.602698 [ANA_INIT] PLL <<<<<<<<
2303 10:05:00.605605 [ANA_INIT] MIDPI >>>>>>>>
2304 10:05:00.605688 [ANA_INIT] MIDPI <<<<<<<<
2305 10:05:00.609297 [ANA_INIT] DLL >>>>>>>>
2306 10:05:00.612462 [ANA_INIT] DLL <<<<<<<<
2307 10:05:00.612572 [ANA_INIT] flow end
2308 10:05:00.618906 ============ LP4 DIFF to SE enter ============
2309 10:05:00.622780 ============ LP4 DIFF to SE exit ============
2310 10:05:00.625627 [ANA_INIT] <<<<<<<<<<<<<
2311 10:05:00.629303 [Flow] Enable top DCM control >>>>>
2312 10:05:00.632401 [Flow] Enable top DCM control <<<<<
2313 10:05:00.632497 Enable DLL master slave shuffle
2314 10:05:00.639136 ==============================================================
2315 10:05:00.642240 Gating Mode config
2316 10:05:00.645641 ==============================================================
2317 10:05:00.649114 Config description:
2318 10:05:00.658848 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2319 10:05:00.665612 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2320 10:05:00.668648 SELPH_MODE 0: By rank 1: By Phase
2321 10:05:00.675153 ==============================================================
2322 10:05:00.678510 GAT_TRACK_EN = 1
2323 10:05:00.681837 RX_GATING_MODE = 2
2324 10:05:00.685539 RX_GATING_TRACK_MODE = 2
2325 10:05:00.688732 SELPH_MODE = 1
2326 10:05:00.692031 PICG_EARLY_EN = 1
2327 10:05:00.692114 VALID_LAT_VALUE = 1
2328 10:05:00.698516 ==============================================================
2329 10:05:00.701537 Enter into Gating configuration >>>>
2330 10:05:00.705316 Exit from Gating configuration <<<<
2331 10:05:00.708825 Enter into DVFS_PRE_config >>>>>
2332 10:05:00.718668 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2333 10:05:00.721976 Exit from DVFS_PRE_config <<<<<
2334 10:05:00.725006 Enter into PICG configuration >>>>
2335 10:05:00.728281 Exit from PICG configuration <<<<
2336 10:05:00.731911 [RX_INPUT] configuration >>>>>
2337 10:05:00.734724 [RX_INPUT] configuration <<<<<
2338 10:05:00.741258 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2339 10:05:00.744863 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2340 10:05:00.751377 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2341 10:05:00.757933 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2342 10:05:00.764847 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2343 10:05:00.771350 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2344 10:05:00.774809 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2345 10:05:00.777804 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2346 10:05:00.781332 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2347 10:05:00.787695 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2348 10:05:00.791165 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2349 10:05:00.794736 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2350 10:05:00.798160 ===================================
2351 10:05:00.801296 LPDDR4 DRAM CONFIGURATION
2352 10:05:00.804920 ===================================
2353 10:05:00.805000 EX_ROW_EN[0] = 0x0
2354 10:05:00.808425 EX_ROW_EN[1] = 0x0
2355 10:05:00.808547 LP4Y_EN = 0x0
2356 10:05:00.811338 WORK_FSP = 0x0
2357 10:05:00.811435 WL = 0x4
2358 10:05:00.814877 RL = 0x4
2359 10:05:00.817523 BL = 0x2
2360 10:05:00.817607 RPST = 0x0
2361 10:05:00.821358 RD_PRE = 0x0
2362 10:05:00.821442 WR_PRE = 0x1
2363 10:05:00.824334 WR_PST = 0x0
2364 10:05:00.824417 DBI_WR = 0x0
2365 10:05:00.827654 DBI_RD = 0x0
2366 10:05:00.827735 OTF = 0x1
2367 10:05:00.831747 ===================================
2368 10:05:00.834542 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2369 10:05:00.841125 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2370 10:05:00.844773 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2371 10:05:00.847368 ===================================
2372 10:05:00.851521 LPDDR4 DRAM CONFIGURATION
2373 10:05:00.854257 ===================================
2374 10:05:00.854339 EX_ROW_EN[0] = 0x10
2375 10:05:00.857691 EX_ROW_EN[1] = 0x0
2376 10:05:00.857772 LP4Y_EN = 0x0
2377 10:05:00.860785 WORK_FSP = 0x0
2378 10:05:00.860866 WL = 0x4
2379 10:05:00.864343 RL = 0x4
2380 10:05:00.867555 BL = 0x2
2381 10:05:00.867637 RPST = 0x0
2382 10:05:00.870825 RD_PRE = 0x0
2383 10:05:00.870907 WR_PRE = 0x1
2384 10:05:00.874794 WR_PST = 0x0
2385 10:05:00.874876 DBI_WR = 0x0
2386 10:05:00.877247 DBI_RD = 0x0
2387 10:05:00.877329 OTF = 0x1
2388 10:05:00.880979 ===================================
2389 10:05:00.887380 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2390 10:05:00.887492 ==
2391 10:05:00.890397 Dram Type= 6, Freq= 0, CH_0, rank 0
2392 10:05:00.894372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2393 10:05:00.894462 ==
2394 10:05:00.896997 [Duty_Offset_Calibration]
2395 10:05:00.900311 B0:1 B1:-1 CA:0
2396 10:05:00.900396
2397 10:05:00.903520 [DutyScan_Calibration_Flow] k_type=0
2398 10:05:00.912306
2399 10:05:00.912397 ==CLK 0==
2400 10:05:00.915280 Final CLK duty delay cell = 0
2401 10:05:00.918741 [0] MAX Duty = 5125%(X100), DQS PI = 24
2402 10:05:00.922285 [0] MIN Duty = 4875%(X100), DQS PI = 8
2403 10:05:00.922369 [0] AVG Duty = 5000%(X100)
2404 10:05:00.925374
2405 10:05:00.928398 CH0 CLK Duty spec in!! Max-Min= 250%
2406 10:05:00.931963 [DutyScan_Calibration_Flow] ====Done====
2407 10:05:00.932044
2408 10:05:00.934976 [DutyScan_Calibration_Flow] k_type=1
2409 10:05:00.949546
2410 10:05:00.949629 ==DQS 0 ==
2411 10:05:00.953073 Final DQS duty delay cell = -4
2412 10:05:00.956302 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2413 10:05:00.959250 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2414 10:05:00.963061 [-4] AVG Duty = 4968%(X100)
2415 10:05:00.963141
2416 10:05:00.963206 ==DQS 1 ==
2417 10:05:00.966593 Final DQS duty delay cell = -4
2418 10:05:00.969313 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2419 10:05:00.972842 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2420 10:05:00.976013 [-4] AVG Duty = 4938%(X100)
2421 10:05:00.976096
2422 10:05:00.979734 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2423 10:05:00.979826
2424 10:05:00.982567 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2425 10:05:00.985853 [DutyScan_Calibration_Flow] ====Done====
2426 10:05:00.985937
2427 10:05:00.989312 [DutyScan_Calibration_Flow] k_type=3
2428 10:05:01.008272
2429 10:05:01.008412 ==DQM 0 ==
2430 10:05:01.011049 Final DQM duty delay cell = 0
2431 10:05:01.014540 [0] MAX Duty = 5031%(X100), DQS PI = 16
2432 10:05:01.017655 [0] MIN Duty = 4875%(X100), DQS PI = 6
2433 10:05:01.020671 [0] AVG Duty = 4953%(X100)
2434 10:05:01.020759
2435 10:05:01.020827 ==DQM 1 ==
2436 10:05:01.024296 Final DQM duty delay cell = 4
2437 10:05:01.027705 [4] MAX Duty = 5156%(X100), DQS PI = 8
2438 10:05:01.031021 [4] MIN Duty = 4969%(X100), DQS PI = 24
2439 10:05:01.034125 [4] AVG Duty = 5062%(X100)
2440 10:05:01.034209
2441 10:05:01.037726 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2442 10:05:01.037807
2443 10:05:01.040868 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2444 10:05:01.044618 [DutyScan_Calibration_Flow] ====Done====
2445 10:05:01.044702
2446 10:05:01.047451 [DutyScan_Calibration_Flow] k_type=2
2447 10:05:01.063239
2448 10:05:01.063328 ==DQ 0 ==
2449 10:05:01.066566 Final DQ duty delay cell = -4
2450 10:05:01.069846 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2451 10:05:01.073620 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2452 10:05:01.076533 [-4] AVG Duty = 4969%(X100)
2453 10:05:01.076623
2454 10:05:01.076686 ==DQ 1 ==
2455 10:05:01.080023 Final DQ duty delay cell = 0
2456 10:05:01.083678 [0] MAX Duty = 5094%(X100), DQS PI = 50
2457 10:05:01.086704 [0] MIN Duty = 4969%(X100), DQS PI = 40
2458 10:05:01.089971 [0] AVG Duty = 5031%(X100)
2459 10:05:01.090054
2460 10:05:01.092976 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2461 10:05:01.093061
2462 10:05:01.096455 CH0 DQ 1 Duty spec in!! Max-Min= 125%
2463 10:05:01.099739 [DutyScan_Calibration_Flow] ====Done====
2464 10:05:01.099826 ==
2465 10:05:01.102714 Dram Type= 6, Freq= 0, CH_1, rank 0
2466 10:05:01.106733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 10:05:01.106817 ==
2468 10:05:01.109748 [Duty_Offset_Calibration]
2469 10:05:01.109837 B0:-1 B1:1 CA:1
2470 10:05:01.109911
2471 10:05:01.113158 [DutyScan_Calibration_Flow] k_type=0
2472 10:05:01.123392
2473 10:05:01.123478 ==CLK 0==
2474 10:05:01.126788 Final CLK duty delay cell = 0
2475 10:05:01.130420 [0] MAX Duty = 5156%(X100), DQS PI = 22
2476 10:05:01.133381 [0] MIN Duty = 4969%(X100), DQS PI = 60
2477 10:05:01.136963 [0] AVG Duty = 5062%(X100)
2478 10:05:01.137046
2479 10:05:01.140396 CH1 CLK Duty spec in!! Max-Min= 187%
2480 10:05:01.143219 [DutyScan_Calibration_Flow] ====Done====
2481 10:05:01.143302
2482 10:05:01.146705 [DutyScan_Calibration_Flow] k_type=1
2483 10:05:01.162834
2484 10:05:01.162922 ==DQS 0 ==
2485 10:05:01.166489 Final DQS duty delay cell = 0
2486 10:05:01.169607 [0] MAX Duty = 5125%(X100), DQS PI = 16
2487 10:05:01.172961 [0] MIN Duty = 4938%(X100), DQS PI = 4
2488 10:05:01.173044 [0] AVG Duty = 5031%(X100)
2489 10:05:01.176465
2490 10:05:01.176612 ==DQS 1 ==
2491 10:05:01.179490 Final DQS duty delay cell = 0
2492 10:05:01.182854 [0] MAX Duty = 5094%(X100), DQS PI = 12
2493 10:05:01.186111 [0] MIN Duty = 4969%(X100), DQS PI = 58
2494 10:05:01.186197 [0] AVG Duty = 5031%(X100)
2495 10:05:01.189441
2496 10:05:01.192780 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2497 10:05:01.192864
2498 10:05:01.195935 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2499 10:05:01.199079 [DutyScan_Calibration_Flow] ====Done====
2500 10:05:01.199167
2501 10:05:01.202523 [DutyScan_Calibration_Flow] k_type=3
2502 10:05:01.218102
2503 10:05:01.218200 ==DQM 0 ==
2504 10:05:01.221684 Final DQM duty delay cell = -4
2505 10:05:01.224949 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2506 10:05:01.228674 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2507 10:05:01.231831 [-4] AVG Duty = 4969%(X100)
2508 10:05:01.231908
2509 10:05:01.231973 ==DQM 1 ==
2510 10:05:01.234807 Final DQM duty delay cell = 0
2511 10:05:01.238627 [0] MAX Duty = 5156%(X100), DQS PI = 2
2512 10:05:01.241918 [0] MIN Duty = 4969%(X100), DQS PI = 28
2513 10:05:01.245207 [0] AVG Duty = 5062%(X100)
2514 10:05:01.245292
2515 10:05:01.248278 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2516 10:05:01.248361
2517 10:05:01.251714 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2518 10:05:01.254902 [DutyScan_Calibration_Flow] ====Done====
2519 10:05:01.254986
2520 10:05:01.258131 [DutyScan_Calibration_Flow] k_type=2
2521 10:05:01.275156
2522 10:05:01.275246 ==DQ 0 ==
2523 10:05:01.278580 Final DQ duty delay cell = 0
2524 10:05:01.282048 [0] MAX Duty = 5187%(X100), DQS PI = 30
2525 10:05:01.285168 [0] MIN Duty = 4907%(X100), DQS PI = 6
2526 10:05:01.285259 [0] AVG Duty = 5047%(X100)
2527 10:05:01.285358
2528 10:05:01.288561 ==DQ 1 ==
2529 10:05:01.291788 Final DQ duty delay cell = 0
2530 10:05:01.294998 [0] MAX Duty = 5124%(X100), DQS PI = 10
2531 10:05:01.298682 [0] MIN Duty = 4969%(X100), DQS PI = 0
2532 10:05:01.298794 [0] AVG Duty = 5046%(X100)
2533 10:05:01.298890
2534 10:05:01.301644 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2535 10:05:01.301757
2536 10:05:01.304946 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2537 10:05:01.311661 [DutyScan_Calibration_Flow] ====Done====
2538 10:05:01.315059 nWR fixed to 30
2539 10:05:01.315183 [ModeRegInit_LP4] CH0 RK0
2540 10:05:01.318052 [ModeRegInit_LP4] CH0 RK1
2541 10:05:01.321848 [ModeRegInit_LP4] CH1 RK0
2542 10:05:01.321978 [ModeRegInit_LP4] CH1 RK1
2543 10:05:01.324908 match AC timing 7
2544 10:05:01.328465 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2545 10:05:01.331822 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2546 10:05:01.338473 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2547 10:05:01.341406 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2548 10:05:01.348408 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2549 10:05:01.348524 ==
2550 10:05:01.351598 Dram Type= 6, Freq= 0, CH_0, rank 0
2551 10:05:01.354691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2552 10:05:01.354801 ==
2553 10:05:01.361443 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2554 10:05:01.368284 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2555 10:05:01.374871 [CA 0] Center 39 (9~70) winsize 62
2556 10:05:01.378253 [CA 1] Center 39 (9~69) winsize 61
2557 10:05:01.381852 [CA 2] Center 35 (5~66) winsize 62
2558 10:05:01.385030 [CA 3] Center 35 (4~66) winsize 63
2559 10:05:01.388579 [CA 4] Center 33 (4~63) winsize 60
2560 10:05:01.391577 [CA 5] Center 33 (3~63) winsize 61
2561 10:05:01.391701
2562 10:05:01.394992 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2563 10:05:01.395080
2564 10:05:01.398340 [CATrainingPosCal] consider 1 rank data
2565 10:05:01.401663 u2DelayCellTimex100 = 270/100 ps
2566 10:05:01.405441 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2567 10:05:01.408494 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2568 10:05:01.415243 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2569 10:05:01.418385 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2570 10:05:01.421870 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2571 10:05:01.424936 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2572 10:05:01.425024
2573 10:05:01.428336 CA PerBit enable=1, Macro0, CA PI delay=33
2574 10:05:01.428420
2575 10:05:01.431884 [CBTSetCACLKResult] CA Dly = 33
2576 10:05:01.431967 CS Dly: 8 (0~39)
2577 10:05:01.434612 ==
2578 10:05:01.434695 Dram Type= 6, Freq= 0, CH_0, rank 1
2579 10:05:01.441261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 10:05:01.441346 ==
2581 10:05:01.445049 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2582 10:05:01.451551 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2583 10:05:01.460933 [CA 0] Center 39 (9~70) winsize 62
2584 10:05:01.464179 [CA 1] Center 39 (9~70) winsize 62
2585 10:05:01.467429 [CA 2] Center 35 (5~66) winsize 62
2586 10:05:01.470642 [CA 3] Center 34 (4~65) winsize 62
2587 10:05:01.474237 [CA 4] Center 33 (3~64) winsize 62
2588 10:05:01.477220 [CA 5] Center 33 (3~63) winsize 61
2589 10:05:01.477304
2590 10:05:01.480509 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2591 10:05:01.480629
2592 10:05:01.484129 [CATrainingPosCal] consider 2 rank data
2593 10:05:01.487234 u2DelayCellTimex100 = 270/100 ps
2594 10:05:01.490812 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2595 10:05:01.497024 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2596 10:05:01.500907 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2597 10:05:01.504067 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2598 10:05:01.506893 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2599 10:05:01.510283 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2600 10:05:01.510368
2601 10:05:01.513599 CA PerBit enable=1, Macro0, CA PI delay=33
2602 10:05:01.513709
2603 10:05:01.516954 [CBTSetCACLKResult] CA Dly = 33
2604 10:05:01.517066 CS Dly: 9 (0~41)
2605 10:05:01.517167
2606 10:05:01.520381 ----->DramcWriteLeveling(PI) begin...
2607 10:05:01.523750 ==
2608 10:05:01.527492 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 10:05:01.530301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 10:05:01.530409 ==
2611 10:05:01.534058 Write leveling (Byte 0): 33 => 33
2612 10:05:01.537113 Write leveling (Byte 1): 30 => 30
2613 10:05:01.540480 DramcWriteLeveling(PI) end<-----
2614 10:05:01.540610
2615 10:05:01.540677 ==
2616 10:05:01.543786 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 10:05:01.547374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 10:05:01.547459 ==
2619 10:05:01.550336 [Gating] SW mode calibration
2620 10:05:01.557183 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2621 10:05:01.563580 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2622 10:05:01.567195 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2623 10:05:01.570690 0 15 4 | B1->B0 | 2828 3434 | 0 1 | (1 1) (1 1)
2624 10:05:01.574101 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2625 10:05:01.580264 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2626 10:05:01.583395 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2627 10:05:01.587341 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2628 10:05:01.593661 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2629 10:05:01.597285 0 15 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
2630 10:05:01.600554 1 0 0 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
2631 10:05:01.606689 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2632 10:05:01.610449 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2633 10:05:01.613532 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2634 10:05:01.620254 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2635 10:05:01.623349 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2636 10:05:01.627127 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2637 10:05:01.633708 1 0 28 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
2638 10:05:01.636961 1 1 0 | B1->B0 | 2928 4545 | 1 0 | (0 0) (0 0)
2639 10:05:01.639949 1 1 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2640 10:05:01.646823 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2641 10:05:01.650191 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2642 10:05:01.653395 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2643 10:05:01.660939 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2644 10:05:01.663441 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2645 10:05:01.667030 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2646 10:05:01.673678 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2647 10:05:01.676769 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2648 10:05:01.679857 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2649 10:05:01.686191 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2650 10:05:01.689891 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2651 10:05:01.693643 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2652 10:05:01.699581 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2653 10:05:01.702867 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2654 10:05:01.706271 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2655 10:05:01.712853 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2656 10:05:01.716488 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2657 10:05:01.719754 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2658 10:05:01.726130 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2659 10:05:01.729541 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2660 10:05:01.732898 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2661 10:05:01.739687 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2662 10:05:01.742568 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2663 10:05:01.746068 Total UI for P1: 0, mck2ui 16
2664 10:05:01.749516 best dqsien dly found for B0: ( 1, 3, 26)
2665 10:05:01.752969 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2666 10:05:01.755894 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2667 10:05:01.759920 Total UI for P1: 0, mck2ui 16
2668 10:05:01.762914 best dqsien dly found for B1: ( 1, 4, 2)
2669 10:05:01.766278 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2670 10:05:01.770045 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2671 10:05:01.772479
2672 10:05:01.775878 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2673 10:05:01.779342 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2674 10:05:01.782351 [Gating] SW calibration Done
2675 10:05:01.782434 ==
2676 10:05:01.785953 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 10:05:01.789251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 10:05:01.789334 ==
2679 10:05:01.789399 RX Vref Scan: 0
2680 10:05:01.792347
2681 10:05:01.792471 RX Vref 0 -> 0, step: 1
2682 10:05:01.792589
2683 10:05:01.795565 RX Delay -40 -> 252, step: 8
2684 10:05:01.798848 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2685 10:05:01.802583 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2686 10:05:01.809396 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2687 10:05:01.812447 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2688 10:05:01.815528 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2689 10:05:01.819381 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2690 10:05:01.822383 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2691 10:05:01.829125 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2692 10:05:01.832665 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2693 10:05:01.835883 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2694 10:05:01.838656 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2695 10:05:01.842031 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2696 10:05:01.848731 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2697 10:05:01.851819 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2698 10:05:01.855649 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2699 10:05:01.858702 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2700 10:05:01.858787 ==
2701 10:05:01.862037 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 10:05:01.868667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 10:05:01.868778 ==
2704 10:05:01.868881 DQS Delay:
2705 10:05:01.871993 DQS0 = 0, DQS1 = 0
2706 10:05:01.872103 DQM Delay:
2707 10:05:01.875014 DQM0 = 119, DQM1 = 107
2708 10:05:01.875090 DQ Delay:
2709 10:05:01.878641 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2710 10:05:01.881598 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2711 10:05:01.884977 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2712 10:05:01.888548 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2713 10:05:01.888638
2714 10:05:01.888711
2715 10:05:01.888785 ==
2716 10:05:01.891583 Dram Type= 6, Freq= 0, CH_0, rank 0
2717 10:05:01.898388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2718 10:05:01.898475 ==
2719 10:05:01.898542
2720 10:05:01.898612
2721 10:05:01.898681 TX Vref Scan disable
2722 10:05:01.901692 == TX Byte 0 ==
2723 10:05:01.904994 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2724 10:05:01.908364 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2725 10:05:01.911827 == TX Byte 1 ==
2726 10:05:01.915078 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2727 10:05:01.918335 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2728 10:05:01.921787 ==
2729 10:05:01.925185 Dram Type= 6, Freq= 0, CH_0, rank 0
2730 10:05:01.928280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2731 10:05:01.928405 ==
2732 10:05:01.939593 TX Vref=22, minBit 7, minWin=25, winSum=416
2733 10:05:01.942601 TX Vref=24, minBit 7, minWin=25, winSum=426
2734 10:05:01.946444 TX Vref=26, minBit 10, minWin=26, winSum=432
2735 10:05:01.949262 TX Vref=28, minBit 5, minWin=26, winSum=433
2736 10:05:01.952473 TX Vref=30, minBit 4, minWin=26, winSum=432
2737 10:05:01.959475 TX Vref=32, minBit 10, minWin=25, winSum=429
2738 10:05:01.962547 [TxChooseVref] Worse bit 5, Min win 26, Win sum 433, Final Vref 28
2739 10:05:01.962634
2740 10:05:01.966244 Final TX Range 1 Vref 28
2741 10:05:01.966329
2742 10:05:01.966395 ==
2743 10:05:01.969586 Dram Type= 6, Freq= 0, CH_0, rank 0
2744 10:05:01.972476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2745 10:05:01.975888 ==
2746 10:05:01.975966
2747 10:05:01.976038
2748 10:05:01.976113 TX Vref Scan disable
2749 10:05:01.979369 == TX Byte 0 ==
2750 10:05:01.982585 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2751 10:05:01.985880 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2752 10:05:01.989514 == TX Byte 1 ==
2753 10:05:01.992543 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2754 10:05:01.996153 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2755 10:05:01.999602
2756 10:05:01.999713 [DATLAT]
2757 10:05:01.999814 Freq=1200, CH0 RK0
2758 10:05:01.999877
2759 10:05:02.002691 DATLAT Default: 0xd
2760 10:05:02.002794 0, 0xFFFF, sum = 0
2761 10:05:02.006162 1, 0xFFFF, sum = 0
2762 10:05:02.006265 2, 0xFFFF, sum = 0
2763 10:05:02.009663 3, 0xFFFF, sum = 0
2764 10:05:02.012472 4, 0xFFFF, sum = 0
2765 10:05:02.012619 5, 0xFFFF, sum = 0
2766 10:05:02.016471 6, 0xFFFF, sum = 0
2767 10:05:02.016616 7, 0xFFFF, sum = 0
2768 10:05:02.019269 8, 0xFFFF, sum = 0
2769 10:05:02.019374 9, 0xFFFF, sum = 0
2770 10:05:02.022207 10, 0xFFFF, sum = 0
2771 10:05:02.022315 11, 0xFFFF, sum = 0
2772 10:05:02.025785 12, 0x0, sum = 1
2773 10:05:02.025894 13, 0x0, sum = 2
2774 10:05:02.029271 14, 0x0, sum = 3
2775 10:05:02.029380 15, 0x0, sum = 4
2776 10:05:02.032219 best_step = 13
2777 10:05:02.032318
2778 10:05:02.032408 ==
2779 10:05:02.035772 Dram Type= 6, Freq= 0, CH_0, rank 0
2780 10:05:02.038758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2781 10:05:02.038860 ==
2782 10:05:02.038954 RX Vref Scan: 1
2783 10:05:02.039045
2784 10:05:02.042331 Set Vref Range= 32 -> 127
2785 10:05:02.042425
2786 10:05:02.045761 RX Vref 32 -> 127, step: 1
2787 10:05:02.045837
2788 10:05:02.048717 RX Delay -21 -> 252, step: 4
2789 10:05:02.048830
2790 10:05:02.052602 Set Vref, RX VrefLevel [Byte0]: 32
2791 10:05:02.055994 [Byte1]: 32
2792 10:05:02.056069
2793 10:05:02.059308 Set Vref, RX VrefLevel [Byte0]: 33
2794 10:05:02.062103 [Byte1]: 33
2795 10:05:02.066311
2796 10:05:02.066385 Set Vref, RX VrefLevel [Byte0]: 34
2797 10:05:02.068982 [Byte1]: 34
2798 10:05:02.074001
2799 10:05:02.074109 Set Vref, RX VrefLevel [Byte0]: 35
2800 10:05:02.076873 [Byte1]: 35
2801 10:05:02.081709
2802 10:05:02.081789 Set Vref, RX VrefLevel [Byte0]: 36
2803 10:05:02.085099 [Byte1]: 36
2804 10:05:02.089381
2805 10:05:02.089485 Set Vref, RX VrefLevel [Byte0]: 37
2806 10:05:02.093137 [Byte1]: 37
2807 10:05:02.097464
2808 10:05:02.097572 Set Vref, RX VrefLevel [Byte0]: 38
2809 10:05:02.100916 [Byte1]: 38
2810 10:05:02.105760
2811 10:05:02.105850 Set Vref, RX VrefLevel [Byte0]: 39
2812 10:05:02.109147 [Byte1]: 39
2813 10:05:02.113434
2814 10:05:02.113547 Set Vref, RX VrefLevel [Byte0]: 40
2815 10:05:02.116857 [Byte1]: 40
2816 10:05:02.121115
2817 10:05:02.121198 Set Vref, RX VrefLevel [Byte0]: 41
2818 10:05:02.124395 [Byte1]: 41
2819 10:05:02.129383
2820 10:05:02.129466 Set Vref, RX VrefLevel [Byte0]: 42
2821 10:05:02.132603 [Byte1]: 42
2822 10:05:02.137448
2823 10:05:02.137532 Set Vref, RX VrefLevel [Byte0]: 43
2824 10:05:02.140309 [Byte1]: 43
2825 10:05:02.145199
2826 10:05:02.145283 Set Vref, RX VrefLevel [Byte0]: 44
2827 10:05:02.149061 [Byte1]: 44
2828 10:05:02.153097
2829 10:05:02.153182 Set Vref, RX VrefLevel [Byte0]: 45
2830 10:05:02.156219 [Byte1]: 45
2831 10:05:02.161273
2832 10:05:02.161422 Set Vref, RX VrefLevel [Byte0]: 46
2833 10:05:02.164241 [Byte1]: 46
2834 10:05:02.168696
2835 10:05:02.168831 Set Vref, RX VrefLevel [Byte0]: 47
2836 10:05:02.172434 [Byte1]: 47
2837 10:05:02.176932
2838 10:05:02.177015 Set Vref, RX VrefLevel [Byte0]: 48
2839 10:05:02.180156 [Byte1]: 48
2840 10:05:02.185073
2841 10:05:02.185158 Set Vref, RX VrefLevel [Byte0]: 49
2842 10:05:02.188117 [Byte1]: 49
2843 10:05:02.192680
2844 10:05:02.192795 Set Vref, RX VrefLevel [Byte0]: 50
2845 10:05:02.195730 [Byte1]: 50
2846 10:05:02.200484
2847 10:05:02.200605 Set Vref, RX VrefLevel [Byte0]: 51
2848 10:05:02.204205 [Byte1]: 51
2849 10:05:02.208665
2850 10:05:02.208747 Set Vref, RX VrefLevel [Byte0]: 52
2851 10:05:02.211844 [Byte1]: 52
2852 10:05:02.216698
2853 10:05:02.216780 Set Vref, RX VrefLevel [Byte0]: 53
2854 10:05:02.220094 [Byte1]: 53
2855 10:05:02.224452
2856 10:05:02.224605 Set Vref, RX VrefLevel [Byte0]: 54
2857 10:05:02.227668 [Byte1]: 54
2858 10:05:02.232560
2859 10:05:02.232652 Set Vref, RX VrefLevel [Byte0]: 55
2860 10:05:02.235495 [Byte1]: 55
2861 10:05:02.240478
2862 10:05:02.240599 Set Vref, RX VrefLevel [Byte0]: 56
2863 10:05:02.243483 [Byte1]: 56
2864 10:05:02.247945
2865 10:05:02.248027 Set Vref, RX VrefLevel [Byte0]: 57
2866 10:05:02.251502 [Byte1]: 57
2867 10:05:02.255994
2868 10:05:02.256078 Set Vref, RX VrefLevel [Byte0]: 58
2869 10:05:02.259258 [Byte1]: 58
2870 10:05:02.263855
2871 10:05:02.263937 Set Vref, RX VrefLevel [Byte0]: 59
2872 10:05:02.267693 [Byte1]: 59
2873 10:05:02.271842
2874 10:05:02.271924 Set Vref, RX VrefLevel [Byte0]: 60
2875 10:05:02.275095 [Byte1]: 60
2876 10:05:02.279921
2877 10:05:02.280003 Set Vref, RX VrefLevel [Byte0]: 61
2878 10:05:02.283000 [Byte1]: 61
2879 10:05:02.287665
2880 10:05:02.287748 Set Vref, RX VrefLevel [Byte0]: 62
2881 10:05:02.291102 [Byte1]: 62
2882 10:05:02.295854
2883 10:05:02.295940 Set Vref, RX VrefLevel [Byte0]: 63
2884 10:05:02.298931 [Byte1]: 63
2885 10:05:02.303938
2886 10:05:02.304023 Set Vref, RX VrefLevel [Byte0]: 64
2887 10:05:02.306813 [Byte1]: 64
2888 10:05:02.311390
2889 10:05:02.311492 Set Vref, RX VrefLevel [Byte0]: 65
2890 10:05:02.314679 [Byte1]: 65
2891 10:05:02.319377
2892 10:05:02.319459 Set Vref, RX VrefLevel [Byte0]: 66
2893 10:05:02.322504 [Byte1]: 66
2894 10:05:02.327270
2895 10:05:02.327356 Set Vref, RX VrefLevel [Byte0]: 67
2896 10:05:02.330784 [Byte1]: 67
2897 10:05:02.335413
2898 10:05:02.335519 Set Vref, RX VrefLevel [Byte0]: 68
2899 10:05:02.339034 [Byte1]: 68
2900 10:05:02.343098
2901 10:05:02.343231 Set Vref, RX VrefLevel [Byte0]: 69
2902 10:05:02.346854 [Byte1]: 69
2903 10:05:02.351282
2904 10:05:02.351385 Set Vref, RX VrefLevel [Byte0]: 70
2905 10:05:02.354526 [Byte1]: 70
2906 10:05:02.359173
2907 10:05:02.359276 Set Vref, RX VrefLevel [Byte0]: 71
2908 10:05:02.362424 [Byte1]: 71
2909 10:05:02.367206
2910 10:05:02.367309 Set Vref, RX VrefLevel [Byte0]: 72
2911 10:05:02.370275 [Byte1]: 72
2912 10:05:02.374733
2913 10:05:02.374842 Set Vref, RX VrefLevel [Byte0]: 73
2914 10:05:02.378312 [Byte1]: 73
2915 10:05:02.382999
2916 10:05:02.383078 Set Vref, RX VrefLevel [Byte0]: 74
2917 10:05:02.385955 [Byte1]: 74
2918 10:05:02.390870
2919 10:05:02.390948 Set Vref, RX VrefLevel [Byte0]: 75
2920 10:05:02.394140 [Byte1]: 75
2921 10:05:02.398923
2922 10:05:02.399016 Set Vref, RX VrefLevel [Byte0]: 76
2923 10:05:02.402031 [Byte1]: 76
2924 10:05:02.406683
2925 10:05:02.406784 Set Vref, RX VrefLevel [Byte0]: 77
2926 10:05:02.409979 [Byte1]: 77
2927 10:05:02.414339
2928 10:05:02.414434 Set Vref, RX VrefLevel [Byte0]: 78
2929 10:05:02.417747 [Byte1]: 78
2930 10:05:02.422351
2931 10:05:02.422426 Final RX Vref Byte 0 = 61 to rank0
2932 10:05:02.425728 Final RX Vref Byte 1 = 58 to rank0
2933 10:05:02.429131 Final RX Vref Byte 0 = 61 to rank1
2934 10:05:02.432733 Final RX Vref Byte 1 = 58 to rank1==
2935 10:05:02.436070 Dram Type= 6, Freq= 0, CH_0, rank 0
2936 10:05:02.442514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 10:05:02.442655 ==
2938 10:05:02.442783 DQS Delay:
2939 10:05:02.445681 DQS0 = 0, DQS1 = 0
2940 10:05:02.445816 DQM Delay:
2941 10:05:02.445943 DQM0 = 119, DQM1 = 107
2942 10:05:02.448756 DQ Delay:
2943 10:05:02.452262 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2944 10:05:02.455306 DQ4 =118, DQ5 =114, DQ6 =128, DQ7 =126
2945 10:05:02.458778 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =102
2946 10:05:02.462170 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =114
2947 10:05:02.462300
2948 10:05:02.462418
2949 10:05:02.471960 [DQSOSCAuto] RK0, (LSB)MR18= 0xdf9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 405 ps
2950 10:05:02.472101 CH0 RK0: MR19=403, MR18=DF9
2951 10:05:02.478605 CH0_RK0: MR19=0x403, MR18=0xDF9, DQSOSC=405, MR23=63, INC=39, DEC=26
2952 10:05:02.478744
2953 10:05:02.481725 ----->DramcWriteLeveling(PI) begin...
2954 10:05:02.481861 ==
2955 10:05:02.485157 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 10:05:02.492231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 10:05:02.492334 ==
2958 10:05:02.495681 Write leveling (Byte 0): 33 => 33
2959 10:05:02.495795 Write leveling (Byte 1): 29 => 29
2960 10:05:02.498424 DramcWriteLeveling(PI) end<-----
2961 10:05:02.498533
2962 10:05:02.498635 ==
2963 10:05:02.501931 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 10:05:02.508756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 10:05:02.508868 ==
2966 10:05:02.511717 [Gating] SW mode calibration
2967 10:05:02.518425 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2968 10:05:02.521901 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2969 10:05:02.528450 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2970 10:05:02.532090 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
2971 10:05:02.536343 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2972 10:05:02.541574 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2973 10:05:02.545109 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2974 10:05:02.548595 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2975 10:05:02.552056 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2976 10:05:02.558782 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 0)
2977 10:05:02.561669 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2978 10:05:02.565429 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2979 10:05:02.572154 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2980 10:05:02.575144 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2981 10:05:02.578559 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2982 10:05:02.585307 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2983 10:05:02.588416 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2984 10:05:02.591894 1 0 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2985 10:05:02.598071 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2986 10:05:02.601880 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2987 10:05:02.605508 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2988 10:05:02.611998 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2989 10:05:02.615009 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2990 10:05:02.618631 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2991 10:05:02.625282 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2992 10:05:02.628478 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2993 10:05:02.631919 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2994 10:05:02.638086 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 10:05:02.641437 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 10:05:02.645044 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 10:05:02.651743 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 10:05:02.654600 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 10:05:02.658103 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 10:05:02.664679 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 10:05:02.667762 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3002 10:05:02.671142 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3003 10:05:02.677845 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3004 10:05:02.681431 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3005 10:05:02.684764 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3006 10:05:02.690908 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3007 10:05:02.694387 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3008 10:05:02.697655 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3009 10:05:02.704890 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3010 10:05:02.705039 Total UI for P1: 0, mck2ui 16
3011 10:05:02.707920 best dqsien dly found for B0: ( 1, 3, 26)
3012 10:05:02.714463 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3013 10:05:02.717429 Total UI for P1: 0, mck2ui 16
3014 10:05:02.720993 best dqsien dly found for B1: ( 1, 4, 0)
3015 10:05:02.724413 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3016 10:05:02.727307 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3017 10:05:02.727420
3018 10:05:02.730627 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3019 10:05:02.734277 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3020 10:05:02.737650 [Gating] SW calibration Done
3021 10:05:02.737749 ==
3022 10:05:02.740931 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 10:05:02.744050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 10:05:02.744147 ==
3025 10:05:02.747508 RX Vref Scan: 0
3026 10:05:02.747601
3027 10:05:02.751023 RX Vref 0 -> 0, step: 1
3028 10:05:02.751148
3029 10:05:02.751217 RX Delay -40 -> 252, step: 8
3030 10:05:02.757300 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3031 10:05:02.760906 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
3032 10:05:02.763790 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3033 10:05:02.767137 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3034 10:05:02.770941 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3035 10:05:02.777000 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3036 10:05:02.780974 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3037 10:05:02.783769 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3038 10:05:02.787129 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3039 10:05:02.790656 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3040 10:05:02.796949 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3041 10:05:02.800740 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3042 10:05:02.803530 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3043 10:05:02.807316 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3044 10:05:02.811178 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3045 10:05:02.817420 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3046 10:05:02.817550 ==
3047 10:05:02.820737 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 10:05:02.823766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 10:05:02.823899 ==
3050 10:05:02.823971 DQS Delay:
3051 10:05:02.826848 DQS0 = 0, DQS1 = 0
3052 10:05:02.826940 DQM Delay:
3053 10:05:02.830329 DQM0 = 117, DQM1 = 109
3054 10:05:02.830437 DQ Delay:
3055 10:05:02.834035 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
3056 10:05:02.836688 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3057 10:05:02.840241 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3058 10:05:02.843585 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =119
3059 10:05:02.843687
3060 10:05:02.843758
3061 10:05:02.846898 ==
3062 10:05:02.850251 Dram Type= 6, Freq= 0, CH_0, rank 1
3063 10:05:02.853379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 10:05:02.853501 ==
3065 10:05:02.853571
3066 10:05:02.853636
3067 10:05:02.856553 TX Vref Scan disable
3068 10:05:02.856661 == TX Byte 0 ==
3069 10:05:02.863361 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3070 10:05:02.866934 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3071 10:05:02.867137 == TX Byte 1 ==
3072 10:05:02.873074 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3073 10:05:02.876491 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3074 10:05:02.876643 ==
3075 10:05:02.879755 Dram Type= 6, Freq= 0, CH_0, rank 1
3076 10:05:02.883403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 10:05:02.883546 ==
3078 10:05:02.895936 TX Vref=22, minBit 10, minWin=25, winSum=417
3079 10:05:02.899085 TX Vref=24, minBit 5, minWin=25, winSum=420
3080 10:05:02.902280 TX Vref=26, minBit 1, minWin=26, winSum=423
3081 10:05:02.905674 TX Vref=28, minBit 12, minWin=25, winSum=426
3082 10:05:02.909033 TX Vref=30, minBit 12, minWin=25, winSum=428
3083 10:05:02.915500 TX Vref=32, minBit 10, minWin=25, winSum=425
3084 10:05:02.919120 [TxChooseVref] Worse bit 1, Min win 26, Win sum 423, Final Vref 26
3085 10:05:02.919241
3086 10:05:02.922346 Final TX Range 1 Vref 26
3087 10:05:02.922426
3088 10:05:02.922491 ==
3089 10:05:02.925554 Dram Type= 6, Freq= 0, CH_0, rank 1
3090 10:05:02.929091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3091 10:05:02.932367 ==
3092 10:05:02.932445
3093 10:05:02.932511
3094 10:05:02.932581 TX Vref Scan disable
3095 10:05:02.936085 == TX Byte 0 ==
3096 10:05:02.938929 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3097 10:05:02.945993 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3098 10:05:02.946125 == TX Byte 1 ==
3099 10:05:02.949197 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3100 10:05:02.955556 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3101 10:05:02.955684
3102 10:05:02.955758 [DATLAT]
3103 10:05:02.955822 Freq=1200, CH0 RK1
3104 10:05:02.955883
3105 10:05:02.958983 DATLAT Default: 0xd
3106 10:05:02.959067 0, 0xFFFF, sum = 0
3107 10:05:02.962194 1, 0xFFFF, sum = 0
3108 10:05:02.965442 2, 0xFFFF, sum = 0
3109 10:05:02.965550 3, 0xFFFF, sum = 0
3110 10:05:02.969372 4, 0xFFFF, sum = 0
3111 10:05:02.969495 5, 0xFFFF, sum = 0
3112 10:05:02.972147 6, 0xFFFF, sum = 0
3113 10:05:02.972274 7, 0xFFFF, sum = 0
3114 10:05:02.975642 8, 0xFFFF, sum = 0
3115 10:05:02.975757 9, 0xFFFF, sum = 0
3116 10:05:02.978718 10, 0xFFFF, sum = 0
3117 10:05:02.978844 11, 0xFFFF, sum = 0
3118 10:05:02.982292 12, 0x0, sum = 1
3119 10:05:02.982383 13, 0x0, sum = 2
3120 10:05:02.985560 14, 0x0, sum = 3
3121 10:05:02.985663 15, 0x0, sum = 4
3122 10:05:02.989201 best_step = 13
3123 10:05:02.989313
3124 10:05:02.989407 ==
3125 10:05:02.992311 Dram Type= 6, Freq= 0, CH_0, rank 1
3126 10:05:02.995562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 10:05:02.995675 ==
3128 10:05:02.995768 RX Vref Scan: 0
3129 10:05:02.999023
3130 10:05:02.999121 RX Vref 0 -> 0, step: 1
3131 10:05:02.999211
3132 10:05:03.002803 RX Delay -21 -> 252, step: 4
3133 10:05:03.008737 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3134 10:05:03.012052 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3135 10:05:03.015890 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3136 10:05:03.018969 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3137 10:05:03.022307 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3138 10:05:03.025817 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3139 10:05:03.032381 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3140 10:05:03.035374 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3141 10:05:03.038653 iDelay=195, Bit 8, Center 98 (31 ~ 166) 136
3142 10:05:03.041690 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3143 10:05:03.045478 iDelay=195, Bit 10, Center 112 (43 ~ 182) 140
3144 10:05:03.051971 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3145 10:05:03.055142 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3146 10:05:03.058479 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3147 10:05:03.062113 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3148 10:05:03.068601 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3149 10:05:03.068694 ==
3150 10:05:03.072050 Dram Type= 6, Freq= 0, CH_0, rank 1
3151 10:05:03.075307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3152 10:05:03.075395 ==
3153 10:05:03.075470 DQS Delay:
3154 10:05:03.078583 DQS0 = 0, DQS1 = 0
3155 10:05:03.078668 DQM Delay:
3156 10:05:03.081743 DQM0 = 116, DQM1 = 109
3157 10:05:03.081849 DQ Delay:
3158 10:05:03.085018 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3159 10:05:03.088312 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3160 10:05:03.091888 DQ8 =98, DQ9 =96, DQ10 =112, DQ11 =104
3161 10:05:03.094902 DQ12 =116, DQ13 =114, DQ14 =122, DQ15 =116
3162 10:05:03.094999
3163 10:05:03.095095
3164 10:05:03.104647 [DQSOSCAuto] RK1, (LSB)MR18= 0xde8, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3165 10:05:03.107828 CH0 RK1: MR19=403, MR18=DE8
3166 10:05:03.111500 CH0_RK1: MR19=0x403, MR18=0xDE8, DQSOSC=405, MR23=63, INC=39, DEC=26
3167 10:05:03.114653 [RxdqsGatingPostProcess] freq 1200
3168 10:05:03.121101 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3169 10:05:03.124511 best DQS0 dly(2T, 0.5T) = (0, 11)
3170 10:05:03.127982 best DQS1 dly(2T, 0.5T) = (0, 12)
3171 10:05:03.131146 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3172 10:05:03.134326 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3173 10:05:03.137927 best DQS0 dly(2T, 0.5T) = (0, 11)
3174 10:05:03.140762 best DQS1 dly(2T, 0.5T) = (0, 12)
3175 10:05:03.144034 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3176 10:05:03.147438 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3177 10:05:03.150719 Pre-setting of DQS Precalculation
3178 10:05:03.154048 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3179 10:05:03.154130 ==
3180 10:05:03.157625 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 10:05:03.161149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 10:05:03.161238 ==
3183 10:05:03.167200 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3184 10:05:03.174212 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3185 10:05:03.182485 [CA 0] Center 37 (7~68) winsize 62
3186 10:05:03.185556 [CA 1] Center 38 (8~68) winsize 61
3187 10:05:03.188557 [CA 2] Center 34 (4~64) winsize 61
3188 10:05:03.192010 [CA 3] Center 33 (3~64) winsize 62
3189 10:05:03.195432 [CA 4] Center 34 (5~64) winsize 60
3190 10:05:03.198658 [CA 5] Center 33 (3~64) winsize 62
3191 10:05:03.198759
3192 10:05:03.202206 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3193 10:05:03.202323
3194 10:05:03.205007 [CATrainingPosCal] consider 1 rank data
3195 10:05:03.208339 u2DelayCellTimex100 = 270/100 ps
3196 10:05:03.211512 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3197 10:05:03.218596 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3198 10:05:03.221725 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3199 10:05:03.225371 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3200 10:05:03.228441 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3201 10:05:03.232360 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3202 10:05:03.232448
3203 10:05:03.235099 CA PerBit enable=1, Macro0, CA PI delay=33
3204 10:05:03.235185
3205 10:05:03.238468 [CBTSetCACLKResult] CA Dly = 33
3206 10:05:03.238552 CS Dly: 5 (0~36)
3207 10:05:03.242084 ==
3208 10:05:03.245076 Dram Type= 6, Freq= 0, CH_1, rank 1
3209 10:05:03.248098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 10:05:03.248242 ==
3211 10:05:03.251348 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3212 10:05:03.258623 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3213 10:05:03.267545 [CA 0] Center 37 (7~67) winsize 61
3214 10:05:03.271068 [CA 1] Center 37 (7~68) winsize 62
3215 10:05:03.274475 [CA 2] Center 34 (4~65) winsize 62
3216 10:05:03.277335 [CA 3] Center 33 (3~64) winsize 62
3217 10:05:03.280822 [CA 4] Center 34 (4~64) winsize 61
3218 10:05:03.284441 [CA 5] Center 33 (3~64) winsize 62
3219 10:05:03.284569
3220 10:05:03.287680 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3221 10:05:03.287825
3222 10:05:03.290722 [CATrainingPosCal] consider 2 rank data
3223 10:05:03.294696 u2DelayCellTimex100 = 270/100 ps
3224 10:05:03.297521 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3225 10:05:03.304076 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3226 10:05:03.307268 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3227 10:05:03.310558 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3228 10:05:03.313903 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3229 10:05:03.317523 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3230 10:05:03.317614
3231 10:05:03.320749 CA PerBit enable=1, Macro0, CA PI delay=33
3232 10:05:03.320836
3233 10:05:03.324054 [CBTSetCACLKResult] CA Dly = 33
3234 10:05:03.324141 CS Dly: 7 (0~40)
3235 10:05:03.327288
3236 10:05:03.330430 ----->DramcWriteLeveling(PI) begin...
3237 10:05:03.330521 ==
3238 10:05:03.333763 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 10:05:03.337039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 10:05:03.337149 ==
3241 10:05:03.340583 Write leveling (Byte 0): 25 => 25
3242 10:05:03.343619 Write leveling (Byte 1): 26 => 26
3243 10:05:03.347201 DramcWriteLeveling(PI) end<-----
3244 10:05:03.347341
3245 10:05:03.347438 ==
3246 10:05:03.350658 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 10:05:03.353558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 10:05:03.353652 ==
3249 10:05:03.357414 [Gating] SW mode calibration
3250 10:05:03.364085 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3251 10:05:03.370487 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3252 10:05:03.373394 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3253 10:05:03.376774 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3254 10:05:03.383725 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3255 10:05:03.387361 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3256 10:05:03.390158 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3257 10:05:03.397110 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3258 10:05:03.400422 0 15 24 | B1->B0 | 3434 2c2c | 0 0 | (0 1) (0 1)
3259 10:05:03.403554 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
3260 10:05:03.410207 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3261 10:05:03.413454 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3262 10:05:03.416606 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3263 10:05:03.420476 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3264 10:05:03.426988 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3265 10:05:03.430284 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3266 10:05:03.433677 1 0 24 | B1->B0 | 2828 4141 | 0 0 | (0 0) (0 0)
3267 10:05:03.440336 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3268 10:05:03.443508 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3269 10:05:03.447174 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3270 10:05:03.453138 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3271 10:05:03.456783 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3272 10:05:03.459720 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3273 10:05:03.466331 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3274 10:05:03.470061 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3275 10:05:03.473958 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3276 10:05:03.479846 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3277 10:05:03.483338 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3278 10:05:03.486423 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3279 10:05:03.493086 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3280 10:05:03.496970 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 10:05:03.500070 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 10:05:03.506326 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 10:05:03.510073 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3284 10:05:03.513323 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 10:05:03.519672 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 10:05:03.523564 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 10:05:03.526703 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 10:05:03.533232 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 10:05:03.536544 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 10:05:03.539616 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3291 10:05:03.546176 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3292 10:05:03.549492 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3293 10:05:03.552859 Total UI for P1: 0, mck2ui 16
3294 10:05:03.556079 best dqsien dly found for B0: ( 1, 3, 26)
3295 10:05:03.559952 Total UI for P1: 0, mck2ui 16
3296 10:05:03.562721 best dqsien dly found for B1: ( 1, 3, 28)
3297 10:05:03.566468 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3298 10:05:03.569523 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3299 10:05:03.569617
3300 10:05:03.572701 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3301 10:05:03.575952 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3302 10:05:03.579279 [Gating] SW calibration Done
3303 10:05:03.579401 ==
3304 10:05:03.582974 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 10:05:03.586068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 10:05:03.586190 ==
3307 10:05:03.589704 RX Vref Scan: 0
3308 10:05:03.589799
3309 10:05:03.592870 RX Vref 0 -> 0, step: 1
3310 10:05:03.592974
3311 10:05:03.593064 RX Delay -40 -> 252, step: 8
3312 10:05:03.599222 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3313 10:05:03.602719 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3314 10:05:03.606137 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3315 10:05:03.609253 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3316 10:05:03.612511 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3317 10:05:03.619004 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3318 10:05:03.622647 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3319 10:05:03.625921 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3320 10:05:03.629189 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3321 10:05:03.632341 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3322 10:05:03.639027 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3323 10:05:03.642419 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3324 10:05:03.645666 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3325 10:05:03.648982 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3326 10:05:03.652204 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3327 10:05:03.659018 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3328 10:05:03.659149 ==
3329 10:05:03.662415 Dram Type= 6, Freq= 0, CH_1, rank 0
3330 10:05:03.665455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3331 10:05:03.665579 ==
3332 10:05:03.665655 DQS Delay:
3333 10:05:03.668945 DQS0 = 0, DQS1 = 0
3334 10:05:03.669043 DQM Delay:
3335 10:05:03.671972 DQM0 = 117, DQM1 = 109
3336 10:05:03.672062 DQ Delay:
3337 10:05:03.676265 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3338 10:05:03.678744 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3339 10:05:03.682187 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3340 10:05:03.685784 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3341 10:05:03.685903
3342 10:05:03.688985
3343 10:05:03.689096 ==
3344 10:05:03.692035 Dram Type= 6, Freq= 0, CH_1, rank 0
3345 10:05:03.695762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3346 10:05:03.695868 ==
3347 10:05:03.695938
3348 10:05:03.696001
3349 10:05:03.698669 TX Vref Scan disable
3350 10:05:03.698748 == TX Byte 0 ==
3351 10:05:03.701917 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3352 10:05:03.708683 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3353 10:05:03.708831 == TX Byte 1 ==
3354 10:05:03.715424 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3355 10:05:03.718883 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3356 10:05:03.719007 ==
3357 10:05:03.722469 Dram Type= 6, Freq= 0, CH_1, rank 0
3358 10:05:03.725325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3359 10:05:03.725451 ==
3360 10:05:03.737584 TX Vref=22, minBit 3, minWin=25, winSum=416
3361 10:05:03.740566 TX Vref=24, minBit 9, minWin=25, winSum=421
3362 10:05:03.744024 TX Vref=26, minBit 9, minWin=25, winSum=426
3363 10:05:03.747253 TX Vref=28, minBit 9, minWin=25, winSum=428
3364 10:05:03.750401 TX Vref=30, minBit 9, minWin=25, winSum=429
3365 10:05:03.757396 TX Vref=32, minBit 9, minWin=25, winSum=422
3366 10:05:03.760355 [TxChooseVref] Worse bit 9, Min win 25, Win sum 429, Final Vref 30
3367 10:05:03.760477
3368 10:05:03.763692 Final TX Range 1 Vref 30
3369 10:05:03.763796
3370 10:05:03.763865 ==
3371 10:05:03.767051 Dram Type= 6, Freq= 0, CH_1, rank 0
3372 10:05:03.770307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3373 10:05:03.773824 ==
3374 10:05:03.773927
3375 10:05:03.773994
3376 10:05:03.774056 TX Vref Scan disable
3377 10:05:03.777218 == TX Byte 0 ==
3378 10:05:03.780221 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3379 10:05:03.786927 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3380 10:05:03.787058 == TX Byte 1 ==
3381 10:05:03.790219 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3382 10:05:03.796594 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3383 10:05:03.796734
3384 10:05:03.796807 [DATLAT]
3385 10:05:03.796869 Freq=1200, CH1 RK0
3386 10:05:03.796929
3387 10:05:03.799905 DATLAT Default: 0xd
3388 10:05:03.799991 0, 0xFFFF, sum = 0
3389 10:05:03.803538 1, 0xFFFF, sum = 0
3390 10:05:03.806912 2, 0xFFFF, sum = 0
3391 10:05:03.807017 3, 0xFFFF, sum = 0
3392 10:05:03.810080 4, 0xFFFF, sum = 0
3393 10:05:03.810197 5, 0xFFFF, sum = 0
3394 10:05:03.813798 6, 0xFFFF, sum = 0
3395 10:05:03.813897 7, 0xFFFF, sum = 0
3396 10:05:03.817060 8, 0xFFFF, sum = 0
3397 10:05:03.817180 9, 0xFFFF, sum = 0
3398 10:05:03.819968 10, 0xFFFF, sum = 0
3399 10:05:03.820088 11, 0xFFFF, sum = 0
3400 10:05:03.823348 12, 0x0, sum = 1
3401 10:05:03.823455 13, 0x0, sum = 2
3402 10:05:03.826734 14, 0x0, sum = 3
3403 10:05:03.826831 15, 0x0, sum = 4
3404 10:05:03.829726 best_step = 13
3405 10:05:03.829815
3406 10:05:03.829882 ==
3407 10:05:03.833079 Dram Type= 6, Freq= 0, CH_1, rank 0
3408 10:05:03.837070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3409 10:05:03.837169 ==
3410 10:05:03.837238 RX Vref Scan: 1
3411 10:05:03.837301
3412 10:05:03.839750 Set Vref Range= 32 -> 127
3413 10:05:03.839837
3414 10:05:03.843800 RX Vref 32 -> 127, step: 1
3415 10:05:03.843898
3416 10:05:03.846782 RX Delay -21 -> 252, step: 4
3417 10:05:03.846873
3418 10:05:03.850110 Set Vref, RX VrefLevel [Byte0]: 32
3419 10:05:03.853319 [Byte1]: 32
3420 10:05:03.853417
3421 10:05:03.856663 Set Vref, RX VrefLevel [Byte0]: 33
3422 10:05:03.860034 [Byte1]: 33
3423 10:05:03.863476
3424 10:05:03.863579 Set Vref, RX VrefLevel [Byte0]: 34
3425 10:05:03.866792 [Byte1]: 34
3426 10:05:03.871364
3427 10:05:03.871474 Set Vref, RX VrefLevel [Byte0]: 35
3428 10:05:03.874722 [Byte1]: 35
3429 10:05:03.879520
3430 10:05:03.879670 Set Vref, RX VrefLevel [Byte0]: 36
3431 10:05:03.883022 [Byte1]: 36
3432 10:05:03.887501
3433 10:05:03.887625 Set Vref, RX VrefLevel [Byte0]: 37
3434 10:05:03.890540 [Byte1]: 37
3435 10:05:03.895181
3436 10:05:03.895300 Set Vref, RX VrefLevel [Byte0]: 38
3437 10:05:03.898639 [Byte1]: 38
3438 10:05:03.902888
3439 10:05:03.903024 Set Vref, RX VrefLevel [Byte0]: 39
3440 10:05:03.906659 [Byte1]: 39
3441 10:05:03.911077
3442 10:05:03.911169 Set Vref, RX VrefLevel [Byte0]: 40
3443 10:05:03.914219 [Byte1]: 40
3444 10:05:03.919097
3445 10:05:03.919217 Set Vref, RX VrefLevel [Byte0]: 41
3446 10:05:03.922612 [Byte1]: 41
3447 10:05:03.926650
3448 10:05:03.926747 Set Vref, RX VrefLevel [Byte0]: 42
3449 10:05:03.930169 [Byte1]: 42
3450 10:05:03.934981
3451 10:05:03.935087 Set Vref, RX VrefLevel [Byte0]: 43
3452 10:05:03.938233 [Byte1]: 43
3453 10:05:03.942670
3454 10:05:03.942768 Set Vref, RX VrefLevel [Byte0]: 44
3455 10:05:03.946097 [Byte1]: 44
3456 10:05:03.950296
3457 10:05:03.950406 Set Vref, RX VrefLevel [Byte0]: 45
3458 10:05:03.953683 [Byte1]: 45
3459 10:05:03.958249
3460 10:05:03.958338 Set Vref, RX VrefLevel [Byte0]: 46
3461 10:05:03.961982 [Byte1]: 46
3462 10:05:03.966303
3463 10:05:03.966399 Set Vref, RX VrefLevel [Byte0]: 47
3464 10:05:03.969462 [Byte1]: 47
3465 10:05:03.974885
3466 10:05:03.975037 Set Vref, RX VrefLevel [Byte0]: 48
3467 10:05:03.977888 [Byte1]: 48
3468 10:05:03.982364
3469 10:05:03.982451 Set Vref, RX VrefLevel [Byte0]: 49
3470 10:05:03.985520 [Byte1]: 49
3471 10:05:03.990295
3472 10:05:03.990382 Set Vref, RX VrefLevel [Byte0]: 50
3473 10:05:03.993448 [Byte1]: 50
3474 10:05:03.997836
3475 10:05:03.997981 Set Vref, RX VrefLevel [Byte0]: 51
3476 10:05:04.001546 [Byte1]: 51
3477 10:05:04.005817
3478 10:05:04.005897 Set Vref, RX VrefLevel [Byte0]: 52
3479 10:05:04.009027 [Byte1]: 52
3480 10:05:04.013815
3481 10:05:04.013978 Set Vref, RX VrefLevel [Byte0]: 53
3482 10:05:04.017022 [Byte1]: 53
3483 10:05:04.022151
3484 10:05:04.022230 Set Vref, RX VrefLevel [Byte0]: 54
3485 10:05:04.025167 [Byte1]: 54
3486 10:05:04.029429
3487 10:05:04.029510 Set Vref, RX VrefLevel [Byte0]: 55
3488 10:05:04.032853 [Byte1]: 55
3489 10:05:04.037798
3490 10:05:04.037905 Set Vref, RX VrefLevel [Byte0]: 56
3491 10:05:04.040923 [Byte1]: 56
3492 10:05:04.045565
3493 10:05:04.045675 Set Vref, RX VrefLevel [Byte0]: 57
3494 10:05:04.048744 [Byte1]: 57
3495 10:05:04.053172
3496 10:05:04.053248 Set Vref, RX VrefLevel [Byte0]: 58
3497 10:05:04.056613 [Byte1]: 58
3498 10:05:04.061187
3499 10:05:04.061272 Set Vref, RX VrefLevel [Byte0]: 59
3500 10:05:04.064430 [Byte1]: 59
3501 10:05:04.069059
3502 10:05:04.069136 Set Vref, RX VrefLevel [Byte0]: 60
3503 10:05:04.072430 [Byte1]: 60
3504 10:05:04.077180
3505 10:05:04.077281 Set Vref, RX VrefLevel [Byte0]: 61
3506 10:05:04.080449 [Byte1]: 61
3507 10:05:04.085218
3508 10:05:04.085295 Set Vref, RX VrefLevel [Byte0]: 62
3509 10:05:04.088386 [Byte1]: 62
3510 10:05:04.092971
3511 10:05:04.093049 Set Vref, RX VrefLevel [Byte0]: 63
3512 10:05:04.096435 [Byte1]: 63
3513 10:05:04.101006
3514 10:05:04.101111 Set Vref, RX VrefLevel [Byte0]: 64
3515 10:05:04.104084 [Byte1]: 64
3516 10:05:04.108973
3517 10:05:04.109078 Set Vref, RX VrefLevel [Byte0]: 65
3518 10:05:04.112111 [Byte1]: 65
3519 10:05:04.116787
3520 10:05:04.116890 Set Vref, RX VrefLevel [Byte0]: 66
3521 10:05:04.122904 [Byte1]: 66
3522 10:05:04.123007
3523 10:05:04.126268 Set Vref, RX VrefLevel [Byte0]: 67
3524 10:05:04.129693 [Byte1]: 67
3525 10:05:04.129772
3526 10:05:04.133412 Set Vref, RX VrefLevel [Byte0]: 68
3527 10:05:04.136381 [Byte1]: 68
3528 10:05:04.140305
3529 10:05:04.140405 Set Vref, RX VrefLevel [Byte0]: 69
3530 10:05:04.144005 [Byte1]: 69
3531 10:05:04.148307
3532 10:05:04.148388 Final RX Vref Byte 0 = 47 to rank0
3533 10:05:04.151959 Final RX Vref Byte 1 = 52 to rank0
3534 10:05:04.154938 Final RX Vref Byte 0 = 47 to rank1
3535 10:05:04.158763 Final RX Vref Byte 1 = 52 to rank1==
3536 10:05:04.161875 Dram Type= 6, Freq= 0, CH_1, rank 0
3537 10:05:04.168422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 10:05:04.168570 ==
3539 10:05:04.168647 DQS Delay:
3540 10:05:04.168737 DQS0 = 0, DQS1 = 0
3541 10:05:04.171402 DQM Delay:
3542 10:05:04.171499 DQM0 = 116, DQM1 = 110
3543 10:05:04.174664 DQ Delay:
3544 10:05:04.178315 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =112
3545 10:05:04.181586 DQ4 =114, DQ5 =128, DQ6 =126, DQ7 =114
3546 10:05:04.184991 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =98
3547 10:05:04.187820 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =118
3548 10:05:04.187906
3549 10:05:04.187981
3550 10:05:04.198021 [DQSOSCAuto] RK0, (LSB)MR18= 0xf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3551 10:05:04.198182 CH1 RK0: MR19=403, MR18=F4
3552 10:05:04.204304 CH1_RK0: MR19=0x403, MR18=0xF4, DQSOSC=410, MR23=63, INC=39, DEC=26
3553 10:05:04.204438
3554 10:05:04.207862 ----->DramcWriteLeveling(PI) begin...
3555 10:05:04.207971 ==
3556 10:05:04.210984 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 10:05:04.214134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 10:05:04.217941 ==
3559 10:05:04.218050 Write leveling (Byte 0): 26 => 26
3560 10:05:04.221296 Write leveling (Byte 1): 29 => 29
3561 10:05:04.224037 DramcWriteLeveling(PI) end<-----
3562 10:05:04.224140
3563 10:05:04.224231 ==
3564 10:05:04.227240 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 10:05:04.233767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 10:05:04.233882 ==
3567 10:05:04.237495 [Gating] SW mode calibration
3568 10:05:04.243841 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3569 10:05:04.247128 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3570 10:05:04.253791 0 15 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3571 10:05:04.256853 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3572 10:05:04.260445 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3573 10:05:04.266962 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3574 10:05:04.270345 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3575 10:05:04.273490 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3576 10:05:04.280346 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3577 10:05:04.283429 0 15 28 | B1->B0 | 2323 2d2d | 0 0 | (1 0) (1 0)
3578 10:05:04.286840 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3579 10:05:04.293185 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3580 10:05:04.296504 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3581 10:05:04.299691 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3582 10:05:04.306350 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3583 10:05:04.309576 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3584 10:05:04.312788 1 0 24 | B1->B0 | 3232 2323 | 0 0 | (1 1) (0 0)
3585 10:05:04.319875 1 0 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
3586 10:05:04.323221 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3587 10:05:04.326069 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3588 10:05:04.332734 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3589 10:05:04.336225 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3590 10:05:04.339449 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3591 10:05:04.346068 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3592 10:05:04.349427 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3593 10:05:04.352507 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3594 10:05:04.359393 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3595 10:05:04.362665 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3596 10:05:04.365915 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3597 10:05:04.372865 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3598 10:05:04.375953 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3599 10:05:04.379120 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3600 10:05:04.385993 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3601 10:05:04.389365 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3602 10:05:04.392608 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3603 10:05:04.399050 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3604 10:05:04.402262 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3605 10:05:04.405707 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3606 10:05:04.412311 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3607 10:05:04.415157 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3608 10:05:04.418982 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3609 10:05:04.425558 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3610 10:05:04.428994 Total UI for P1: 0, mck2ui 16
3611 10:05:04.432240 best dqsien dly found for B1: ( 1, 3, 24)
3612 10:05:04.435371 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3613 10:05:04.438589 Total UI for P1: 0, mck2ui 16
3614 10:05:04.441902 best dqsien dly found for B0: ( 1, 3, 28)
3615 10:05:04.445429 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3616 10:05:04.448283 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3617 10:05:04.448723
3618 10:05:04.451861 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3619 10:05:04.455338 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3620 10:05:04.458286 [Gating] SW calibration Done
3621 10:05:04.458804 ==
3622 10:05:04.461735 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 10:05:04.468277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 10:05:04.468799 ==
3625 10:05:04.469161 RX Vref Scan: 0
3626 10:05:04.469616
3627 10:05:04.471934 RX Vref 0 -> 0, step: 1
3628 10:05:04.472299
3629 10:05:04.475192 RX Delay -40 -> 252, step: 8
3630 10:05:04.478017 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3631 10:05:04.481937 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3632 10:05:04.484572 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3633 10:05:04.488011 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3634 10:05:04.495204 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3635 10:05:04.498280 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3636 10:05:04.501691 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3637 10:05:04.505007 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3638 10:05:04.508331 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3639 10:05:04.514565 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3640 10:05:04.517760 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3641 10:05:04.521327 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3642 10:05:04.524617 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3643 10:05:04.527913 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3644 10:05:04.533976 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3645 10:05:04.537837 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3646 10:05:04.537928 ==
3647 10:05:04.540587 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 10:05:04.544543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 10:05:04.544663 ==
3650 10:05:04.547693 DQS Delay:
3651 10:05:04.547802 DQS0 = 0, DQS1 = 0
3652 10:05:04.547902 DQM Delay:
3653 10:05:04.551285 DQM0 = 116, DQM1 = 109
3654 10:05:04.551367 DQ Delay:
3655 10:05:04.554131 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =111
3656 10:05:04.557366 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3657 10:05:04.560869 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3658 10:05:04.567495 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3659 10:05:04.567591
3660 10:05:04.567665
3661 10:05:04.567733 ==
3662 10:05:04.570538 Dram Type= 6, Freq= 0, CH_1, rank 1
3663 10:05:04.573968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3664 10:05:04.574050 ==
3665 10:05:04.574116
3666 10:05:04.574175
3667 10:05:04.577310 TX Vref Scan disable
3668 10:05:04.577402 == TX Byte 0 ==
3669 10:05:04.583608 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3670 10:05:04.587000 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3671 10:05:04.590106 == TX Byte 1 ==
3672 10:05:04.593886 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3673 10:05:04.596682 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3674 10:05:04.596770 ==
3675 10:05:04.600193 Dram Type= 6, Freq= 0, CH_1, rank 1
3676 10:05:04.603674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3677 10:05:04.603770 ==
3678 10:05:04.616554 TX Vref=22, minBit 8, minWin=25, winSum=421
3679 10:05:04.619855 TX Vref=24, minBit 8, minWin=25, winSum=423
3680 10:05:04.623306 TX Vref=26, minBit 8, minWin=25, winSum=425
3681 10:05:04.626989 TX Vref=28, minBit 8, minWin=25, winSum=426
3682 10:05:04.629699 TX Vref=30, minBit 8, minWin=26, winSum=431
3683 10:05:04.636507 TX Vref=32, minBit 8, minWin=26, winSum=430
3684 10:05:04.639879 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 30
3685 10:05:04.639965
3686 10:05:04.643231 Final TX Range 1 Vref 30
3687 10:05:04.643315
3688 10:05:04.643382 ==
3689 10:05:04.646307 Dram Type= 6, Freq= 0, CH_1, rank 1
3690 10:05:04.649835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3691 10:05:04.653030 ==
3692 10:05:04.653112
3693 10:05:04.653178
3694 10:05:04.653238 TX Vref Scan disable
3695 10:05:04.656428 == TX Byte 0 ==
3696 10:05:04.659678 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3697 10:05:04.666314 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3698 10:05:04.666404 == TX Byte 1 ==
3699 10:05:04.670021 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3700 10:05:04.676421 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3701 10:05:04.676504
3702 10:05:04.676611 [DATLAT]
3703 10:05:04.676674 Freq=1200, CH1 RK1
3704 10:05:04.676734
3705 10:05:04.679343 DATLAT Default: 0xd
3706 10:05:04.683047 0, 0xFFFF, sum = 0
3707 10:05:04.683132 1, 0xFFFF, sum = 0
3708 10:05:04.686296 2, 0xFFFF, sum = 0
3709 10:05:04.686380 3, 0xFFFF, sum = 0
3710 10:05:04.689451 4, 0xFFFF, sum = 0
3711 10:05:04.689550 5, 0xFFFF, sum = 0
3712 10:05:04.692710 6, 0xFFFF, sum = 0
3713 10:05:04.692795 7, 0xFFFF, sum = 0
3714 10:05:04.696195 8, 0xFFFF, sum = 0
3715 10:05:04.696279 9, 0xFFFF, sum = 0
3716 10:05:04.699672 10, 0xFFFF, sum = 0
3717 10:05:04.699757 11, 0xFFFF, sum = 0
3718 10:05:04.702820 12, 0x0, sum = 1
3719 10:05:04.702904 13, 0x0, sum = 2
3720 10:05:04.706331 14, 0x0, sum = 3
3721 10:05:04.706417 15, 0x0, sum = 4
3722 10:05:04.709571 best_step = 13
3723 10:05:04.709653
3724 10:05:04.709719 ==
3725 10:05:04.712393 Dram Type= 6, Freq= 0, CH_1, rank 1
3726 10:05:04.715859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3727 10:05:04.715943 ==
3728 10:05:04.716011 RX Vref Scan: 0
3729 10:05:04.719737
3730 10:05:04.719820 RX Vref 0 -> 0, step: 1
3731 10:05:04.719886
3732 10:05:04.722553 RX Delay -21 -> 252, step: 4
3733 10:05:04.729356 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3734 10:05:04.732282 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3735 10:05:04.735691 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3736 10:05:04.738907 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3737 10:05:04.742222 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3738 10:05:04.748739 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3739 10:05:04.752027 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3740 10:05:04.755411 iDelay=199, Bit 7, Center 114 (51 ~ 178) 128
3741 10:05:04.758648 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3742 10:05:04.761928 iDelay=199, Bit 9, Center 98 (31 ~ 166) 136
3743 10:05:04.768877 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3744 10:05:04.773002 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3745 10:05:04.776125 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3746 10:05:04.778479 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3747 10:05:04.781771 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3748 10:05:04.788410 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3749 10:05:04.788493 ==
3750 10:05:04.791722 Dram Type= 6, Freq= 0, CH_1, rank 1
3751 10:05:04.794972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3752 10:05:04.795066 ==
3753 10:05:04.795136 DQS Delay:
3754 10:05:04.798352 DQS0 = 0, DQS1 = 0
3755 10:05:04.798435 DQM Delay:
3756 10:05:04.801839 DQM0 = 116, DQM1 = 109
3757 10:05:04.801920 DQ Delay:
3758 10:05:04.804946 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3759 10:05:04.808046 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =114
3760 10:05:04.812058 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =98
3761 10:05:04.814714 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =118
3762 10:05:04.814791
3763 10:05:04.818048
3764 10:05:04.824958 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2ed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3765 10:05:04.828079 CH1 RK1: MR19=303, MR18=F2ED
3766 10:05:04.834336 CH1_RK1: MR19=0x303, MR18=0xF2ED, DQSOSC=415, MR23=63, INC=38, DEC=25
3767 10:05:04.838471 [RxdqsGatingPostProcess] freq 1200
3768 10:05:04.841298 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3769 10:05:04.844534 best DQS0 dly(2T, 0.5T) = (0, 11)
3770 10:05:04.848013 best DQS1 dly(2T, 0.5T) = (0, 11)
3771 10:05:04.851259 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3772 10:05:04.854138 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3773 10:05:04.857802 best DQS0 dly(2T, 0.5T) = (0, 11)
3774 10:05:04.861054 best DQS1 dly(2T, 0.5T) = (0, 11)
3775 10:05:04.864005 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3776 10:05:04.867307 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3777 10:05:04.871075 Pre-setting of DQS Precalculation
3778 10:05:04.873895 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3779 10:05:04.883793 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3780 10:05:04.890166 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3781 10:05:04.890249
3782 10:05:04.890314
3783 10:05:04.894045 [Calibration Summary] 2400 Mbps
3784 10:05:04.894127 CH 0, Rank 0
3785 10:05:04.897355 SW Impedance : PASS
3786 10:05:04.897436 DUTY Scan : NO K
3787 10:05:04.900054 ZQ Calibration : PASS
3788 10:05:04.903418 Jitter Meter : NO K
3789 10:05:04.903499 CBT Training : PASS
3790 10:05:04.906785 Write leveling : PASS
3791 10:05:04.909838 RX DQS gating : PASS
3792 10:05:04.909946 RX DQ/DQS(RDDQC) : PASS
3793 10:05:04.913171 TX DQ/DQS : PASS
3794 10:05:04.916702 RX DATLAT : PASS
3795 10:05:04.916784 RX DQ/DQS(Engine): PASS
3796 10:05:04.920013 TX OE : NO K
3797 10:05:04.920096 All Pass.
3798 10:05:04.920162
3799 10:05:04.923366 CH 0, Rank 1
3800 10:05:04.923448 SW Impedance : PASS
3801 10:05:04.926429 DUTY Scan : NO K
3802 10:05:04.929886 ZQ Calibration : PASS
3803 10:05:04.929968 Jitter Meter : NO K
3804 10:05:04.933121 CBT Training : PASS
3805 10:05:04.936401 Write leveling : PASS
3806 10:05:04.936509 RX DQS gating : PASS
3807 10:05:04.939936 RX DQ/DQS(RDDQC) : PASS
3808 10:05:04.942997 TX DQ/DQS : PASS
3809 10:05:04.943079 RX DATLAT : PASS
3810 10:05:04.946274 RX DQ/DQS(Engine): PASS
3811 10:05:04.950018 TX OE : NO K
3812 10:05:04.950100 All Pass.
3813 10:05:04.950195
3814 10:05:04.950254 CH 1, Rank 0
3815 10:05:04.953354 SW Impedance : PASS
3816 10:05:04.956598 DUTY Scan : NO K
3817 10:05:04.956680 ZQ Calibration : PASS
3818 10:05:04.959837 Jitter Meter : NO K
3819 10:05:04.959919 CBT Training : PASS
3820 10:05:04.963597 Write leveling : PASS
3821 10:05:04.966225 RX DQS gating : PASS
3822 10:05:04.966307 RX DQ/DQS(RDDQC) : PASS
3823 10:05:04.969808 TX DQ/DQS : PASS
3824 10:05:04.972975 RX DATLAT : PASS
3825 10:05:04.973057 RX DQ/DQS(Engine): PASS
3826 10:05:04.976014 TX OE : NO K
3827 10:05:04.976104 All Pass.
3828 10:05:04.976185
3829 10:05:04.979319 CH 1, Rank 1
3830 10:05:04.979401 SW Impedance : PASS
3831 10:05:04.982905 DUTY Scan : NO K
3832 10:05:04.985991 ZQ Calibration : PASS
3833 10:05:04.986074 Jitter Meter : NO K
3834 10:05:04.989332 CBT Training : PASS
3835 10:05:04.992992 Write leveling : PASS
3836 10:05:04.993074 RX DQS gating : PASS
3837 10:05:04.995750 RX DQ/DQS(RDDQC) : PASS
3838 10:05:04.998996 TX DQ/DQS : PASS
3839 10:05:04.999155 RX DATLAT : PASS
3840 10:05:05.002321 RX DQ/DQS(Engine): PASS
3841 10:05:05.005791 TX OE : NO K
3842 10:05:05.005876 All Pass.
3843 10:05:05.005943
3844 10:05:05.009032 DramC Write-DBI off
3845 10:05:05.009132 PER_BANK_REFRESH: Hybrid Mode
3846 10:05:05.012863 TX_TRACKING: ON
3847 10:05:05.019425 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3848 10:05:05.025914 [FAST_K] Save calibration result to emmc
3849 10:05:05.029205 dramc_set_vcore_voltage set vcore to 650000
3850 10:05:05.029288 Read voltage for 600, 5
3851 10:05:05.032108 Vio18 = 0
3852 10:05:05.032190 Vcore = 650000
3853 10:05:05.032256 Vdram = 0
3854 10:05:05.035633 Vddq = 0
3855 10:05:05.035714 Vmddr = 0
3856 10:05:05.039244 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3857 10:05:05.045606 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3858 10:05:05.049182 MEM_TYPE=3, freq_sel=19
3859 10:05:05.052157 sv_algorithm_assistance_LP4_1600
3860 10:05:05.055334 ============ PULL DRAM RESETB DOWN ============
3861 10:05:05.058737 ========== PULL DRAM RESETB DOWN end =========
3862 10:05:05.065020 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3863 10:05:05.068344 ===================================
3864 10:05:05.068464 LPDDR4 DRAM CONFIGURATION
3865 10:05:05.071658 ===================================
3866 10:05:05.075031 EX_ROW_EN[0] = 0x0
3867 10:05:05.075147 EX_ROW_EN[1] = 0x0
3868 10:05:05.078312 LP4Y_EN = 0x0
3869 10:05:05.081913 WORK_FSP = 0x0
3870 10:05:05.081996 WL = 0x2
3871 10:05:05.085225 RL = 0x2
3872 10:05:05.085307 BL = 0x2
3873 10:05:05.088340 RPST = 0x0
3874 10:05:05.088425 RD_PRE = 0x0
3875 10:05:05.091733 WR_PRE = 0x1
3876 10:05:05.091818 WR_PST = 0x0
3877 10:05:05.094612 DBI_WR = 0x0
3878 10:05:05.094697 DBI_RD = 0x0
3879 10:05:05.098015 OTF = 0x1
3880 10:05:05.101810 ===================================
3881 10:05:05.104767 ===================================
3882 10:05:05.104889 ANA top config
3883 10:05:05.108076 ===================================
3884 10:05:05.111431 DLL_ASYNC_EN = 0
3885 10:05:05.114773 ALL_SLAVE_EN = 1
3886 10:05:05.117675 NEW_RANK_MODE = 1
3887 10:05:05.117768 DLL_IDLE_MODE = 1
3888 10:05:05.121602 LP45_APHY_COMB_EN = 1
3889 10:05:05.124410 TX_ODT_DIS = 1
3890 10:05:05.127624 NEW_8X_MODE = 1
3891 10:05:05.130942 ===================================
3892 10:05:05.134249 ===================================
3893 10:05:05.137810 data_rate = 1200
3894 10:05:05.137907 CKR = 1
3895 10:05:05.140913 DQ_P2S_RATIO = 8
3896 10:05:05.144137 ===================================
3897 10:05:05.147433 CA_P2S_RATIO = 8
3898 10:05:05.150621 DQ_CA_OPEN = 0
3899 10:05:05.154154 DQ_SEMI_OPEN = 0
3900 10:05:05.157616 CA_SEMI_OPEN = 0
3901 10:05:05.157701 CA_FULL_RATE = 0
3902 10:05:05.160784 DQ_CKDIV4_EN = 1
3903 10:05:05.163946 CA_CKDIV4_EN = 1
3904 10:05:05.167178 CA_PREDIV_EN = 0
3905 10:05:05.170577 PH8_DLY = 0
3906 10:05:05.174273 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3907 10:05:05.174360 DQ_AAMCK_DIV = 4
3908 10:05:05.177074 CA_AAMCK_DIV = 4
3909 10:05:05.180838 CA_ADMCK_DIV = 4
3910 10:05:05.183715 DQ_TRACK_CA_EN = 0
3911 10:05:05.186912 CA_PICK = 600
3912 10:05:05.190645 CA_MCKIO = 600
3913 10:05:05.193761 MCKIO_SEMI = 0
3914 10:05:05.193847 PLL_FREQ = 2288
3915 10:05:05.196851 DQ_UI_PI_RATIO = 32
3916 10:05:05.200289 CA_UI_PI_RATIO = 0
3917 10:05:05.203541 ===================================
3918 10:05:05.206845 ===================================
3919 10:05:05.210214 memory_type:LPDDR4
3920 10:05:05.210305 GP_NUM : 10
3921 10:05:05.213399 SRAM_EN : 1
3922 10:05:05.216885 MD32_EN : 0
3923 10:05:05.220477 ===================================
3924 10:05:05.220581 [ANA_INIT] >>>>>>>>>>>>>>
3925 10:05:05.223698 <<<<<< [CONFIGURE PHASE]: ANA_TX
3926 10:05:05.227052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3927 10:05:05.230374 ===================================
3928 10:05:05.233529 data_rate = 1200,PCW = 0X5800
3929 10:05:05.237108 ===================================
3930 10:05:05.240377 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3931 10:05:05.247032 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3932 10:05:05.250553 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3933 10:05:05.257010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3934 10:05:05.260348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3935 10:05:05.263656 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3936 10:05:05.266927 [ANA_INIT] flow start
3937 10:05:05.267000 [ANA_INIT] PLL >>>>>>>>
3938 10:05:05.269811 [ANA_INIT] PLL <<<<<<<<
3939 10:05:05.273333 [ANA_INIT] MIDPI >>>>>>>>
3940 10:05:05.273405 [ANA_INIT] MIDPI <<<<<<<<
3941 10:05:05.276715 [ANA_INIT] DLL >>>>>>>>
3942 10:05:05.279645 [ANA_INIT] flow end
3943 10:05:05.283669 ============ LP4 DIFF to SE enter ============
3944 10:05:05.286675 ============ LP4 DIFF to SE exit ============
3945 10:05:05.289739 [ANA_INIT] <<<<<<<<<<<<<
3946 10:05:05.292867 [Flow] Enable top DCM control >>>>>
3947 10:05:05.296685 [Flow] Enable top DCM control <<<<<
3948 10:05:05.299558 Enable DLL master slave shuffle
3949 10:05:05.302985 ==============================================================
3950 10:05:05.305910 Gating Mode config
3951 10:05:05.312731 ==============================================================
3952 10:05:05.312809 Config description:
3953 10:05:05.322611 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3954 10:05:05.329476 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3955 10:05:05.335820 SELPH_MODE 0: By rank 1: By Phase
3956 10:05:05.338835 ==============================================================
3957 10:05:05.342412 GAT_TRACK_EN = 1
3958 10:05:05.345774 RX_GATING_MODE = 2
3959 10:05:05.348813 RX_GATING_TRACK_MODE = 2
3960 10:05:05.352420 SELPH_MODE = 1
3961 10:05:05.355318 PICG_EARLY_EN = 1
3962 10:05:05.358831 VALID_LAT_VALUE = 1
3963 10:05:05.362473 ==============================================================
3964 10:05:05.368917 Enter into Gating configuration >>>>
3965 10:05:05.371863 Exit from Gating configuration <<<<
3966 10:05:05.371970 Enter into DVFS_PRE_config >>>>>
3967 10:05:05.385419 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3968 10:05:05.388564 Exit from DVFS_PRE_config <<<<<
3969 10:05:05.391705 Enter into PICG configuration >>>>
3970 10:05:05.394927 Exit from PICG configuration <<<<
3971 10:05:05.398439 [RX_INPUT] configuration >>>>>
3972 10:05:05.398554 [RX_INPUT] configuration <<<<<
3973 10:05:05.404885 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3974 10:05:05.411326 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3975 10:05:05.414660 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3976 10:05:05.421528 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3977 10:05:05.428011 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3978 10:05:05.434658 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3979 10:05:05.437982 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3980 10:05:05.441483 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3981 10:05:05.447885 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3982 10:05:05.451289 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3983 10:05:05.454014 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3984 10:05:05.460931 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3985 10:05:05.464140 ===================================
3986 10:05:05.464215 LPDDR4 DRAM CONFIGURATION
3987 10:05:05.467901 ===================================
3988 10:05:05.470901 EX_ROW_EN[0] = 0x0
3989 10:05:05.473778 EX_ROW_EN[1] = 0x0
3990 10:05:05.473864 LP4Y_EN = 0x0
3991 10:05:05.477470 WORK_FSP = 0x0
3992 10:05:05.477572 WL = 0x2
3993 10:05:05.480878 RL = 0x2
3994 10:05:05.480955 BL = 0x2
3995 10:05:05.483744 RPST = 0x0
3996 10:05:05.483842 RD_PRE = 0x0
3997 10:05:05.487407 WR_PRE = 0x1
3998 10:05:05.487483 WR_PST = 0x0
3999 10:05:05.490482 DBI_WR = 0x0
4000 10:05:05.490554 DBI_RD = 0x0
4001 10:05:05.493782 OTF = 0x1
4002 10:05:05.497325 ===================================
4003 10:05:05.500424 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4004 10:05:05.503905 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4005 10:05:05.510876 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
4006 10:05:05.514026 ===================================
4007 10:05:05.514117 LPDDR4 DRAM CONFIGURATION
4008 10:05:05.517516 ===================================
4009 10:05:05.520197 EX_ROW_EN[0] = 0x10
4010 10:05:05.523758 EX_ROW_EN[1] = 0x0
4011 10:05:05.523854 LP4Y_EN = 0x0
4012 10:05:05.527064 WORK_FSP = 0x0
4013 10:05:05.527167 WL = 0x2
4014 10:05:05.530602 RL = 0x2
4015 10:05:05.530715 BL = 0x2
4016 10:05:05.533902 RPST = 0x0
4017 10:05:05.534041 RD_PRE = 0x0
4018 10:05:05.536800 WR_PRE = 0x1
4019 10:05:05.536924 WR_PST = 0x0
4020 10:05:05.540286 DBI_WR = 0x0
4021 10:05:05.540370 DBI_RD = 0x0
4022 10:05:05.543634 OTF = 0x1
4023 10:05:05.546407 ===================================
4024 10:05:05.553118 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4025 10:05:05.556667 nWR fixed to 30
4026 10:05:05.556752 [ModeRegInit_LP4] CH0 RK0
4027 10:05:05.560284 [ModeRegInit_LP4] CH0 RK1
4028 10:05:05.563065 [ModeRegInit_LP4] CH1 RK0
4029 10:05:05.566855 [ModeRegInit_LP4] CH1 RK1
4030 10:05:05.566938 match AC timing 17
4031 10:05:05.572850 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4032 10:05:05.576486 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4033 10:05:05.579972 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4034 10:05:05.586074 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4035 10:05:05.589346 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4036 10:05:05.589429 ==
4037 10:05:05.592726 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 10:05:05.595769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 10:05:05.595851 ==
4040 10:05:05.602469 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4041 10:05:05.609825 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4042 10:05:05.612447 [CA 0] Center 36 (6~66) winsize 61
4043 10:05:05.615721 [CA 1] Center 36 (6~66) winsize 61
4044 10:05:05.619327 [CA 2] Center 34 (4~65) winsize 62
4045 10:05:05.622168 [CA 3] Center 34 (4~65) winsize 62
4046 10:05:05.625759 [CA 4] Center 33 (3~64) winsize 62
4047 10:05:05.629005 [CA 5] Center 33 (3~64) winsize 62
4048 10:05:05.629088
4049 10:05:05.632135 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4050 10:05:05.632218
4051 10:05:05.635520 [CATrainingPosCal] consider 1 rank data
4052 10:05:05.638821 u2DelayCellTimex100 = 270/100 ps
4053 10:05:05.642106 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4054 10:05:05.645324 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4055 10:05:05.648778 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4056 10:05:05.651859 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4057 10:05:05.658640 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4058 10:05:05.662511 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4059 10:05:05.662594
4060 10:05:05.665304 CA PerBit enable=1, Macro0, CA PI delay=33
4061 10:05:05.665386
4062 10:05:05.668860 [CBTSetCACLKResult] CA Dly = 33
4063 10:05:05.668942 CS Dly: 6 (0~37)
4064 10:05:05.669009 ==
4065 10:05:05.672052 Dram Type= 6, Freq= 0, CH_0, rank 1
4066 10:05:05.678325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 10:05:05.678408 ==
4068 10:05:05.681558 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4069 10:05:05.688345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4070 10:05:05.691761 [CA 0] Center 36 (6~66) winsize 61
4071 10:05:05.694803 [CA 1] Center 36 (6~66) winsize 61
4072 10:05:05.698238 [CA 2] Center 34 (3~65) winsize 63
4073 10:05:05.701399 [CA 3] Center 33 (3~64) winsize 62
4074 10:05:05.704737 [CA 4] Center 33 (3~64) winsize 62
4075 10:05:05.708087 [CA 5] Center 33 (2~64) winsize 63
4076 10:05:05.708202
4077 10:05:05.711689 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4078 10:05:05.711797
4079 10:05:05.714903 [CATrainingPosCal] consider 2 rank data
4080 10:05:05.718449 u2DelayCellTimex100 = 270/100 ps
4081 10:05:05.721160 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4082 10:05:05.727990 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4083 10:05:05.731234 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4084 10:05:05.734488 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4085 10:05:05.737880 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4086 10:05:05.740839 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4087 10:05:05.740962
4088 10:05:05.744062 CA PerBit enable=1, Macro0, CA PI delay=33
4089 10:05:05.744177
4090 10:05:05.747373 [CBTSetCACLKResult] CA Dly = 33
4091 10:05:05.750676 CS Dly: 6 (0~37)
4092 10:05:05.750764
4093 10:05:05.753913 ----->DramcWriteLeveling(PI) begin...
4094 10:05:05.754061 ==
4095 10:05:05.757131 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 10:05:05.760634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 10:05:05.760717 ==
4098 10:05:05.764161 Write leveling (Byte 0): 33 => 33
4099 10:05:05.767520 Write leveling (Byte 1): 32 => 32
4100 10:05:05.770630 DramcWriteLeveling(PI) end<-----
4101 10:05:05.770712
4102 10:05:05.770778 ==
4103 10:05:05.773574 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 10:05:05.777120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 10:05:05.777202 ==
4106 10:05:05.780136 [Gating] SW mode calibration
4107 10:05:05.786895 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4108 10:05:05.793262 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4109 10:05:05.797104 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4110 10:05:05.800050 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4111 10:05:05.806596 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4112 10:05:05.809859 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
4113 10:05:05.813194 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4114 10:05:05.819763 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4115 10:05:05.823280 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4116 10:05:05.826089 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4117 10:05:05.832715 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4118 10:05:05.836174 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4119 10:05:05.842653 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4120 10:05:05.845947 0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4121 10:05:05.849421 0 10 16 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
4122 10:05:05.856103 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4123 10:05:05.858959 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4124 10:05:05.862936 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4125 10:05:05.865710 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4126 10:05:05.872782 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4127 10:05:05.875977 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4128 10:05:05.878812 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4129 10:05:05.885793 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4130 10:05:05.888985 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4131 10:05:05.895945 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4132 10:05:05.898634 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4133 10:05:05.902404 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4134 10:05:05.908959 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4135 10:05:05.911613 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4136 10:05:05.915118 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4137 10:05:05.921504 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4138 10:05:05.924943 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4139 10:05:05.928421 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4140 10:05:05.934839 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4141 10:05:05.938207 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4142 10:05:05.941402 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4143 10:05:05.948007 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4144 10:05:05.951527 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4145 10:05:05.954759 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4146 10:05:05.961423 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4147 10:05:05.961510 Total UI for P1: 0, mck2ui 16
4148 10:05:05.968658 best dqsien dly found for B0: ( 0, 13, 16)
4149 10:05:05.968765 Total UI for P1: 0, mck2ui 16
4150 10:05:05.971164 best dqsien dly found for B1: ( 0, 13, 16)
4151 10:05:05.978614 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4152 10:05:05.981511 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4153 10:05:05.981598
4154 10:05:05.984230 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4155 10:05:05.987481 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4156 10:05:05.991501 [Gating] SW calibration Done
4157 10:05:05.991588 ==
4158 10:05:05.994302 Dram Type= 6, Freq= 0, CH_0, rank 0
4159 10:05:05.997890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 10:05:05.997981 ==
4161 10:05:06.000875 RX Vref Scan: 0
4162 10:05:06.000962
4163 10:05:06.001048 RX Vref 0 -> 0, step: 1
4164 10:05:06.001128
4165 10:05:06.004137 RX Delay -230 -> 252, step: 16
4166 10:05:06.007625 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4167 10:05:06.014031 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4168 10:05:06.017365 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4169 10:05:06.020674 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4170 10:05:06.023996 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4171 10:05:06.031019 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4172 10:05:06.034362 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4173 10:05:06.037220 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4174 10:05:06.040571 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4175 10:05:06.047294 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4176 10:05:06.050720 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4177 10:05:06.053606 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4178 10:05:06.056989 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4179 10:05:06.063982 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4180 10:05:06.067351 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4181 10:05:06.070147 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4182 10:05:06.070222 ==
4183 10:05:06.073560 Dram Type= 6, Freq= 0, CH_0, rank 0
4184 10:05:06.076860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 10:05:06.076964 ==
4186 10:05:06.080262 DQS Delay:
4187 10:05:06.080340 DQS0 = 0, DQS1 = 0
4188 10:05:06.083662 DQM Delay:
4189 10:05:06.083756 DQM0 = 42, DQM1 = 30
4190 10:05:06.083835 DQ Delay:
4191 10:05:06.086721 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4192 10:05:06.090056 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4193 10:05:06.093364 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4194 10:05:06.096899 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4195 10:05:06.096982
4196 10:05:06.097047
4197 10:05:06.099994 ==
4198 10:05:06.103277 Dram Type= 6, Freq= 0, CH_0, rank 0
4199 10:05:06.106469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 10:05:06.106553 ==
4201 10:05:06.106620
4202 10:05:06.106680
4203 10:05:06.110158 TX Vref Scan disable
4204 10:05:06.110241 == TX Byte 0 ==
4205 10:05:06.116333 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4206 10:05:06.120356 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4207 10:05:06.120466 == TX Byte 1 ==
4208 10:05:06.126358 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4209 10:05:06.129715 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4210 10:05:06.129799 ==
4211 10:05:06.133163 Dram Type= 6, Freq= 0, CH_0, rank 0
4212 10:05:06.136489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 10:05:06.136622 ==
4214 10:05:06.136689
4215 10:05:06.136751
4216 10:05:06.139645 TX Vref Scan disable
4217 10:05:06.142986 == TX Byte 0 ==
4218 10:05:06.146365 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4219 10:05:06.149646 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4220 10:05:06.153282 == TX Byte 1 ==
4221 10:05:06.156401 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4222 10:05:06.163072 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4223 10:05:06.163164
4224 10:05:06.163230 [DATLAT]
4225 10:05:06.163292 Freq=600, CH0 RK0
4226 10:05:06.163352
4227 10:05:06.166076 DATLAT Default: 0x9
4228 10:05:06.166158 0, 0xFFFF, sum = 0
4229 10:05:06.168955 1, 0xFFFF, sum = 0
4230 10:05:06.172655 2, 0xFFFF, sum = 0
4231 10:05:06.172763 3, 0xFFFF, sum = 0
4232 10:05:06.175760 4, 0xFFFF, sum = 0
4233 10:05:06.175851 5, 0xFFFF, sum = 0
4234 10:05:06.179116 6, 0xFFFF, sum = 0
4235 10:05:06.179213 7, 0xFFFF, sum = 0
4236 10:05:06.182618 8, 0x0, sum = 1
4237 10:05:06.182703 9, 0x0, sum = 2
4238 10:05:06.182770 10, 0x0, sum = 3
4239 10:05:06.185524 11, 0x0, sum = 4
4240 10:05:06.185608 best_step = 9
4241 10:05:06.185675
4242 10:05:06.185735 ==
4243 10:05:06.188938 Dram Type= 6, Freq= 0, CH_0, rank 0
4244 10:05:06.195562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 10:05:06.195670 ==
4246 10:05:06.195765 RX Vref Scan: 1
4247 10:05:06.195855
4248 10:05:06.198790 RX Vref 0 -> 0, step: 1
4249 10:05:06.198901
4250 10:05:06.202380 RX Delay -195 -> 252, step: 8
4251 10:05:06.202493
4252 10:05:06.205646 Set Vref, RX VrefLevel [Byte0]: 61
4253 10:05:06.208673 [Byte1]: 58
4254 10:05:06.208760
4255 10:05:06.212108 Final RX Vref Byte 0 = 61 to rank0
4256 10:05:06.215502 Final RX Vref Byte 1 = 58 to rank0
4257 10:05:06.218506 Final RX Vref Byte 0 = 61 to rank1
4258 10:05:06.221716 Final RX Vref Byte 1 = 58 to rank1==
4259 10:05:06.225346 Dram Type= 6, Freq= 0, CH_0, rank 0
4260 10:05:06.228699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4261 10:05:06.231584 ==
4262 10:05:06.231665 DQS Delay:
4263 10:05:06.231731 DQS0 = 0, DQS1 = 0
4264 10:05:06.234740 DQM Delay:
4265 10:05:06.234866 DQM0 = 44, DQM1 = 33
4266 10:05:06.238359 DQ Delay:
4267 10:05:06.241947 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4268 10:05:06.242054 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4269 10:05:06.244789 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4270 10:05:06.248412 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4271 10:05:06.251560
4272 10:05:06.251663
4273 10:05:06.258122 [DQSOSCAuto] RK0, (LSB)MR18= 0x623a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4274 10:05:06.261721 CH0 RK0: MR19=808, MR18=623A
4275 10:05:06.268478 CH0_RK0: MR19=0x808, MR18=0x623A, DQSOSC=391, MR23=63, INC=171, DEC=114
4276 10:05:06.268609
4277 10:05:06.271555 ----->DramcWriteLeveling(PI) begin...
4278 10:05:06.271674 ==
4279 10:05:06.274290 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 10:05:06.277981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 10:05:06.278069 ==
4282 10:05:06.280941 Write leveling (Byte 0): 33 => 33
4283 10:05:06.284873 Write leveling (Byte 1): 29 => 29
4284 10:05:06.287661 DramcWriteLeveling(PI) end<-----
4285 10:05:06.287742
4286 10:05:06.287807 ==
4287 10:05:06.291091 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 10:05:06.294419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 10:05:06.294515 ==
4290 10:05:06.297644 [Gating] SW mode calibration
4291 10:05:06.304581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4292 10:05:06.311112 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4293 10:05:06.314509 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4294 10:05:06.321140 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4295 10:05:06.324283 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4296 10:05:06.328106 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4297 10:05:06.333682 0 9 16 | B1->B0 | 3030 2626 | 0 0 | (1 1) (1 1)
4298 10:05:06.337102 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4299 10:05:06.340328 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4300 10:05:06.347370 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4301 10:05:06.350260 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4302 10:05:06.354047 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4303 10:05:06.360465 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4304 10:05:06.363514 0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4305 10:05:06.366843 0 10 16 | B1->B0 | 3a3a 4040 | 0 0 | (0 0) (0 0)
4306 10:05:06.373540 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4307 10:05:06.376924 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4308 10:05:06.380197 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4309 10:05:06.387162 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4310 10:05:06.390082 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4311 10:05:06.393685 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4312 10:05:06.400287 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4313 10:05:06.403196 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 10:05:06.406464 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 10:05:06.410280 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 10:05:06.416891 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 10:05:06.419957 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 10:05:06.426409 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 10:05:06.429682 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 10:05:06.432971 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4321 10:05:06.439655 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4322 10:05:06.443004 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4323 10:05:06.445986 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4324 10:05:06.452653 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4325 10:05:06.456188 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4326 10:05:06.459327 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4327 10:05:06.465675 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4328 10:05:06.469269 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4329 10:05:06.472404 Total UI for P1: 0, mck2ui 16
4330 10:05:06.476007 best dqsien dly found for B0: ( 0, 13, 10)
4331 10:05:06.478770 Total UI for P1: 0, mck2ui 16
4332 10:05:06.482547 best dqsien dly found for B1: ( 0, 13, 10)
4333 10:05:06.485986 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4334 10:05:06.488759 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4335 10:05:06.488834
4336 10:05:06.492095 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4337 10:05:06.495520 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4338 10:05:06.498484 [Gating] SW calibration Done
4339 10:05:06.498553 ==
4340 10:05:06.501887 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 10:05:06.508613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 10:05:06.508726 ==
4343 10:05:06.508797 RX Vref Scan: 0
4344 10:05:06.508874
4345 10:05:06.511942 RX Vref 0 -> 0, step: 1
4346 10:05:06.512057
4347 10:05:06.515354 RX Delay -230 -> 252, step: 16
4348 10:05:06.518510 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4349 10:05:06.521707 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4350 10:05:06.525022 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4351 10:05:06.531496 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4352 10:05:06.534910 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4353 10:05:06.538355 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4354 10:05:06.541119 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4355 10:05:06.548048 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4356 10:05:06.550999 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4357 10:05:06.554394 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4358 10:05:06.558207 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4359 10:05:06.564442 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4360 10:05:06.567657 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4361 10:05:06.570960 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4362 10:05:06.573821 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4363 10:05:06.580790 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4364 10:05:06.580868 ==
4365 10:05:06.584433 Dram Type= 6, Freq= 0, CH_0, rank 1
4366 10:05:06.587232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 10:05:06.587316 ==
4368 10:05:06.587386 DQS Delay:
4369 10:05:06.590785 DQS0 = 0, DQS1 = 0
4370 10:05:06.590861 DQM Delay:
4371 10:05:06.593975 DQM0 = 42, DQM1 = 34
4372 10:05:06.594083 DQ Delay:
4373 10:05:06.597143 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4374 10:05:06.600854 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4375 10:05:06.604238 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4376 10:05:06.607602 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4377 10:05:06.607718
4378 10:05:06.607817
4379 10:05:06.607917 ==
4380 10:05:06.610325 Dram Type= 6, Freq= 0, CH_0, rank 1
4381 10:05:06.613663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4382 10:05:06.613767 ==
4383 10:05:06.618001
4384 10:05:06.618102
4385 10:05:06.618193 TX Vref Scan disable
4386 10:05:06.620838 == TX Byte 0 ==
4387 10:05:06.624000 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4388 10:05:06.627144 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4389 10:05:06.630383 == TX Byte 1 ==
4390 10:05:06.633470 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4391 10:05:06.636678 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4392 10:05:06.640200 ==
4393 10:05:06.643579 Dram Type= 6, Freq= 0, CH_0, rank 1
4394 10:05:06.646676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 10:05:06.646789 ==
4396 10:05:06.646891
4397 10:05:06.646958
4398 10:05:06.649799 TX Vref Scan disable
4399 10:05:06.653146 == TX Byte 0 ==
4400 10:05:06.656337 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4401 10:05:06.660090 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4402 10:05:06.663467 == TX Byte 1 ==
4403 10:05:06.666723 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4404 10:05:06.670049 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4405 10:05:06.670156
4406 10:05:06.670256 [DATLAT]
4407 10:05:06.672945 Freq=600, CH0 RK1
4408 10:05:06.673027
4409 10:05:06.676220 DATLAT Default: 0x9
4410 10:05:06.676301 0, 0xFFFF, sum = 0
4411 10:05:06.679603 1, 0xFFFF, sum = 0
4412 10:05:06.679685 2, 0xFFFF, sum = 0
4413 10:05:06.682706 3, 0xFFFF, sum = 0
4414 10:05:06.682789 4, 0xFFFF, sum = 0
4415 10:05:06.686179 5, 0xFFFF, sum = 0
4416 10:05:06.686262 6, 0xFFFF, sum = 0
4417 10:05:06.689491 7, 0xFFFF, sum = 0
4418 10:05:06.689596 8, 0x0, sum = 1
4419 10:05:06.692859 9, 0x0, sum = 2
4420 10:05:06.692968 10, 0x0, sum = 3
4421 10:05:06.696104 11, 0x0, sum = 4
4422 10:05:06.696186 best_step = 9
4423 10:05:06.696284
4424 10:05:06.696375 ==
4425 10:05:06.699620 Dram Type= 6, Freq= 0, CH_0, rank 1
4426 10:05:06.702494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4427 10:05:06.702609 ==
4428 10:05:06.706414 RX Vref Scan: 0
4429 10:05:06.706527
4430 10:05:06.709120 RX Vref 0 -> 0, step: 1
4431 10:05:06.709208
4432 10:05:06.709275 RX Delay -195 -> 252, step: 8
4433 10:05:06.717393 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4434 10:05:06.720484 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4435 10:05:06.723863 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4436 10:05:06.727057 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4437 10:05:06.733706 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4438 10:05:06.736920 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4439 10:05:06.740780 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4440 10:05:06.743716 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4441 10:05:06.750403 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4442 10:05:06.753644 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4443 10:05:06.756638 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4444 10:05:06.759992 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4445 10:05:06.766413 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4446 10:05:06.769818 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4447 10:05:06.773135 iDelay=205, Bit 14, Center 48 (-107 ~ 204) 312
4448 10:05:06.776870 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4449 10:05:06.776945 ==
4450 10:05:06.779712 Dram Type= 6, Freq= 0, CH_0, rank 1
4451 10:05:06.786218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 10:05:06.786302 ==
4453 10:05:06.786368 DQS Delay:
4454 10:05:06.790521 DQS0 = 0, DQS1 = 0
4455 10:05:06.790597 DQM Delay:
4456 10:05:06.790661 DQM0 = 41, DQM1 = 36
4457 10:05:06.792744 DQ Delay:
4458 10:05:06.796485 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4459 10:05:06.799362 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4460 10:05:06.802765 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4461 10:05:06.806078 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4462 10:05:06.806153
4463 10:05:06.806253
4464 10:05:06.813100 [DQSOSCAuto] RK1, (LSB)MR18= 0x6316, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4465 10:05:06.816420 CH0 RK1: MR19=808, MR18=6316
4466 10:05:06.822867 CH0_RK1: MR19=0x808, MR18=0x6316, DQSOSC=391, MR23=63, INC=171, DEC=114
4467 10:05:06.826195 [RxdqsGatingPostProcess] freq 600
4468 10:05:06.832736 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4469 10:05:06.832821 Pre-setting of DQS Precalculation
4470 10:05:06.839531 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4471 10:05:06.839664 ==
4472 10:05:06.842701 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 10:05:06.845835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 10:05:06.845935 ==
4475 10:05:06.852728 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4476 10:05:06.859279 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4477 10:05:06.863019 [CA 0] Center 35 (5~66) winsize 62
4478 10:05:06.865724 [CA 1] Center 36 (6~66) winsize 61
4479 10:05:06.868991 [CA 2] Center 34 (4~65) winsize 62
4480 10:05:06.872265 [CA 3] Center 33 (3~64) winsize 62
4481 10:05:06.875738 [CA 4] Center 34 (4~64) winsize 61
4482 10:05:06.879033 [CA 5] Center 33 (3~64) winsize 62
4483 10:05:06.879116
4484 10:05:06.882369 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4485 10:05:06.882474
4486 10:05:06.885432 [CATrainingPosCal] consider 1 rank data
4487 10:05:06.888769 u2DelayCellTimex100 = 270/100 ps
4488 10:05:06.892018 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4489 10:05:06.895552 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4490 10:05:06.898946 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4491 10:05:06.902194 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4492 10:05:06.905668 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4493 10:05:06.908629 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4494 10:05:06.912094
4495 10:05:06.915507 CA PerBit enable=1, Macro0, CA PI delay=33
4496 10:05:06.915613
4497 10:05:06.918419 [CBTSetCACLKResult] CA Dly = 33
4498 10:05:06.918525 CS Dly: 3 (0~34)
4499 10:05:06.918616 ==
4500 10:05:06.922067 Dram Type= 6, Freq= 0, CH_1, rank 1
4501 10:05:06.924818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 10:05:06.928858 ==
4503 10:05:06.931592 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4504 10:05:06.938475 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4505 10:05:06.941670 [CA 0] Center 35 (5~66) winsize 62
4506 10:05:06.945020 [CA 1] Center 36 (6~66) winsize 61
4507 10:05:06.948069 [CA 2] Center 34 (4~65) winsize 62
4508 10:05:06.951323 [CA 3] Center 34 (3~65) winsize 63
4509 10:05:06.954967 [CA 4] Center 34 (4~65) winsize 62
4510 10:05:06.958376 [CA 5] Center 34 (4~65) winsize 62
4511 10:05:06.958483
4512 10:05:06.961313 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4513 10:05:06.961417
4514 10:05:06.964403 [CATrainingPosCal] consider 2 rank data
4515 10:05:06.968275 u2DelayCellTimex100 = 270/100 ps
4516 10:05:06.971289 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4517 10:05:06.974306 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4518 10:05:06.980987 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4519 10:05:06.984205 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4520 10:05:06.987479 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4521 10:05:06.991004 CA5 delay=34 (4~64),Diff = 1 PI (9 cell)
4522 10:05:06.991120
4523 10:05:06.994329 CA PerBit enable=1, Macro0, CA PI delay=33
4524 10:05:06.994405
4525 10:05:06.997599 [CBTSetCACLKResult] CA Dly = 33
4526 10:05:06.997683 CS Dly: 4 (0~37)
4527 10:05:06.997750
4528 10:05:07.000855 ----->DramcWriteLeveling(PI) begin...
4529 10:05:07.004538 ==
4530 10:05:07.007370 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 10:05:07.010762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 10:05:07.010863 ==
4533 10:05:07.014046 Write leveling (Byte 0): 27 => 27
4534 10:05:07.017162 Write leveling (Byte 1): 28 => 28
4535 10:05:07.020461 DramcWriteLeveling(PI) end<-----
4536 10:05:07.020608
4537 10:05:07.020680 ==
4538 10:05:07.024193 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 10:05:07.027686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 10:05:07.027793 ==
4541 10:05:07.030604 [Gating] SW mode calibration
4542 10:05:07.037176 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4543 10:05:07.044041 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4544 10:05:07.047371 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4545 10:05:07.050488 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4546 10:05:07.057084 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4547 10:05:07.060383 0 9 12 | B1->B0 | 3030 2e2e | 0 1 | (0 1) (1 0)
4548 10:05:07.063761 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4549 10:05:07.070260 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4550 10:05:07.073888 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4551 10:05:07.076668 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4552 10:05:07.083571 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4553 10:05:07.086871 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4554 10:05:07.090035 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4555 10:05:07.096326 0 10 12 | B1->B0 | 2e2e 3938 | 0 1 | (0 0) (0 0)
4556 10:05:07.099885 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4557 10:05:07.103647 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4558 10:05:07.110141 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4559 10:05:07.113074 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4560 10:05:07.116459 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4561 10:05:07.123158 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4562 10:05:07.126084 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4563 10:05:07.129582 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4564 10:05:07.136321 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4565 10:05:07.139607 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4566 10:05:07.142684 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4567 10:05:07.149437 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4568 10:05:07.152499 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4569 10:05:07.155919 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4570 10:05:07.162541 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4571 10:05:07.165721 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4572 10:05:07.169391 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4573 10:05:07.175634 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4574 10:05:07.179353 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4575 10:05:07.182272 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4576 10:05:07.185706 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4577 10:05:07.192595 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4578 10:05:07.195830 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4579 10:05:07.201931 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4580 10:05:07.202035 Total UI for P1: 0, mck2ui 16
4581 10:05:07.205497 best dqsien dly found for B0: ( 0, 13, 8)
4582 10:05:07.208479 Total UI for P1: 0, mck2ui 16
4583 10:05:07.211994 best dqsien dly found for B1: ( 0, 13, 10)
4584 10:05:07.218477 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4585 10:05:07.221980 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4586 10:05:07.222090
4587 10:05:07.224893 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4588 10:05:07.228663 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4589 10:05:07.231785 [Gating] SW calibration Done
4590 10:05:07.231879 ==
4591 10:05:07.234865 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 10:05:07.238516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 10:05:07.238621 ==
4594 10:05:07.241938 RX Vref Scan: 0
4595 10:05:07.242049
4596 10:05:07.242145 RX Vref 0 -> 0, step: 1
4597 10:05:07.242254
4598 10:05:07.244969 RX Delay -230 -> 252, step: 16
4599 10:05:07.248395 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4600 10:05:07.255205 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4601 10:05:07.258553 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4602 10:05:07.261976 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4603 10:05:07.264933 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4604 10:05:07.271945 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4605 10:05:07.274892 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4606 10:05:07.278087 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4607 10:05:07.281342 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4608 10:05:07.284608 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4609 10:05:07.291489 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4610 10:05:07.294869 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4611 10:05:07.298097 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4612 10:05:07.301489 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4613 10:05:07.308258 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4614 10:05:07.311163 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4615 10:05:07.311268 ==
4616 10:05:07.314450 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 10:05:07.317545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 10:05:07.317653 ==
4619 10:05:07.320800 DQS Delay:
4620 10:05:07.320877 DQS0 = 0, DQS1 = 0
4621 10:05:07.324399 DQM Delay:
4622 10:05:07.324499 DQM0 = 45, DQM1 = 36
4623 10:05:07.324596 DQ Delay:
4624 10:05:07.327565 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4625 10:05:07.330905 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4626 10:05:07.333790 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4627 10:05:07.337456 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4628 10:05:07.337532
4629 10:05:07.341157
4630 10:05:07.341270 ==
4631 10:05:07.343845 Dram Type= 6, Freq= 0, CH_1, rank 0
4632 10:05:07.347385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 10:05:07.347465 ==
4634 10:05:07.347529
4635 10:05:07.347589
4636 10:05:07.350773 TX Vref Scan disable
4637 10:05:07.350844 == TX Byte 0 ==
4638 10:05:07.357083 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4639 10:05:07.360510 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4640 10:05:07.360624 == TX Byte 1 ==
4641 10:05:07.367161 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4642 10:05:07.370295 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4643 10:05:07.370395 ==
4644 10:05:07.374125 Dram Type= 6, Freq= 0, CH_1, rank 0
4645 10:05:07.376857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 10:05:07.376957 ==
4647 10:05:07.377053
4648 10:05:07.377140
4649 10:05:07.380400 TX Vref Scan disable
4650 10:05:07.383463 == TX Byte 0 ==
4651 10:05:07.387567 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4652 10:05:07.390361 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4653 10:05:07.393528 == TX Byte 1 ==
4654 10:05:07.396563 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4655 10:05:07.400234 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4656 10:05:07.403359
4657 10:05:07.403478 [DATLAT]
4658 10:05:07.403590 Freq=600, CH1 RK0
4659 10:05:07.403680
4660 10:05:07.406824 DATLAT Default: 0x9
4661 10:05:07.406924 0, 0xFFFF, sum = 0
4662 10:05:07.409676 1, 0xFFFF, sum = 0
4663 10:05:07.409785 2, 0xFFFF, sum = 0
4664 10:05:07.413291 3, 0xFFFF, sum = 0
4665 10:05:07.413383 4, 0xFFFF, sum = 0
4666 10:05:07.416535 5, 0xFFFF, sum = 0
4667 10:05:07.419945 6, 0xFFFF, sum = 0
4668 10:05:07.420050 7, 0xFFFF, sum = 0
4669 10:05:07.420145 8, 0x0, sum = 1
4670 10:05:07.423060 9, 0x0, sum = 2
4671 10:05:07.423169 10, 0x0, sum = 3
4672 10:05:07.426557 11, 0x0, sum = 4
4673 10:05:07.426662 best_step = 9
4674 10:05:07.426754
4675 10:05:07.426847 ==
4676 10:05:07.429737 Dram Type= 6, Freq= 0, CH_1, rank 0
4677 10:05:07.436489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4678 10:05:07.436622 ==
4679 10:05:07.436720 RX Vref Scan: 1
4680 10:05:07.436789
4681 10:05:07.439911 RX Vref 0 -> 0, step: 1
4682 10:05:07.440008
4683 10:05:07.443236 RX Delay -195 -> 252, step: 8
4684 10:05:07.443339
4685 10:05:07.446431 Set Vref, RX VrefLevel [Byte0]: 47
4686 10:05:07.449902 [Byte1]: 52
4687 10:05:07.450001
4688 10:05:07.452769 Final RX Vref Byte 0 = 47 to rank0
4689 10:05:07.456171 Final RX Vref Byte 1 = 52 to rank0
4690 10:05:07.459545 Final RX Vref Byte 0 = 47 to rank1
4691 10:05:07.462700 Final RX Vref Byte 1 = 52 to rank1==
4692 10:05:07.466328 Dram Type= 6, Freq= 0, CH_1, rank 0
4693 10:05:07.469190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 10:05:07.469291 ==
4695 10:05:07.472627 DQS Delay:
4696 10:05:07.472733 DQS0 = 0, DQS1 = 0
4697 10:05:07.475908 DQM Delay:
4698 10:05:07.476010 DQM0 = 46, DQM1 = 37
4699 10:05:07.476110 DQ Delay:
4700 10:05:07.479298 DQ0 =48, DQ1 =40, DQ2 =40, DQ3 =44
4701 10:05:07.482837 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =40
4702 10:05:07.485896 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4703 10:05:07.488966 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4704 10:05:07.489044
4705 10:05:07.492223
4706 10:05:07.499206 [DQSOSCAuto] RK0, (LSB)MR18= 0x492e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4707 10:05:07.502363 CH1 RK0: MR19=808, MR18=492E
4708 10:05:07.508904 CH1_RK0: MR19=0x808, MR18=0x492E, DQSOSC=396, MR23=63, INC=167, DEC=111
4709 10:05:07.509084
4710 10:05:07.512221 ----->DramcWriteLeveling(PI) begin...
4711 10:05:07.512327 ==
4712 10:05:07.515375 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 10:05:07.518650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 10:05:07.518789 ==
4715 10:05:07.522000 Write leveling (Byte 0): 30 => 30
4716 10:05:07.525504 Write leveling (Byte 1): 31 => 31
4717 10:05:07.528856 DramcWriteLeveling(PI) end<-----
4718 10:05:07.528939
4719 10:05:07.529006 ==
4720 10:05:07.531650 Dram Type= 6, Freq= 0, CH_1, rank 1
4721 10:05:07.534958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4722 10:05:07.535075 ==
4723 10:05:07.538476 [Gating] SW mode calibration
4724 10:05:07.544690 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4725 10:05:07.551737 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4726 10:05:07.555290 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4727 10:05:07.561640 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4728 10:05:07.564945 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4729 10:05:07.568287 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
4730 10:05:07.574667 0 9 16 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
4731 10:05:07.578114 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4732 10:05:07.581347 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4733 10:05:07.587908 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4734 10:05:07.590951 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4735 10:05:07.594635 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4736 10:05:07.600956 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4737 10:05:07.604422 0 10 12 | B1->B0 | 2d2d 2d2d | 0 0 | (0 0) (0 0)
4738 10:05:07.607531 0 10 16 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
4739 10:05:07.614476 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4740 10:05:07.617310 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4741 10:05:07.620681 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4742 10:05:07.627747 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4743 10:05:07.630840 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4744 10:05:07.634069 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4745 10:05:07.640818 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4746 10:05:07.644019 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4747 10:05:07.646837 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4748 10:05:07.653621 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4749 10:05:07.657120 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4750 10:05:07.660436 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4751 10:05:07.666594 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4752 10:05:07.670039 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4753 10:05:07.673591 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4754 10:05:07.680057 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4755 10:05:07.683435 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4756 10:05:07.686934 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4757 10:05:07.693765 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4758 10:05:07.696378 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4759 10:05:07.700258 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4760 10:05:07.706700 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4761 10:05:07.709865 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4762 10:05:07.713169 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4763 10:05:07.716290 Total UI for P1: 0, mck2ui 16
4764 10:05:07.719773 best dqsien dly found for B0: ( 0, 13, 12)
4765 10:05:07.723063 Total UI for P1: 0, mck2ui 16
4766 10:05:07.726449 best dqsien dly found for B1: ( 0, 13, 12)
4767 10:05:07.729892 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4768 10:05:07.733306 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4769 10:05:07.733386
4770 10:05:07.736409 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4771 10:05:07.742851 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4772 10:05:07.742941 [Gating] SW calibration Done
4773 10:05:07.746159 ==
4774 10:05:07.746255 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 10:05:07.752996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 10:05:07.753097 ==
4777 10:05:07.753186 RX Vref Scan: 0
4778 10:05:07.753249
4779 10:05:07.755958 RX Vref 0 -> 0, step: 1
4780 10:05:07.756053
4781 10:05:07.759380 RX Delay -230 -> 252, step: 16
4782 10:05:07.762682 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4783 10:05:07.766339 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4784 10:05:07.772404 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4785 10:05:07.775856 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4786 10:05:07.779310 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4787 10:05:07.782803 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4788 10:05:07.785922 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4789 10:05:07.792650 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4790 10:05:07.796065 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4791 10:05:07.799200 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4792 10:05:07.802576 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4793 10:05:07.809165 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4794 10:05:07.812354 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4795 10:05:07.815741 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4796 10:05:07.819041 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4797 10:05:07.825872 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4798 10:05:07.825954 ==
4799 10:05:07.829252 Dram Type= 6, Freq= 0, CH_1, rank 1
4800 10:05:07.832384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4801 10:05:07.832485 ==
4802 10:05:07.832596 DQS Delay:
4803 10:05:07.835762 DQS0 = 0, DQS1 = 0
4804 10:05:07.835863 DQM Delay:
4805 10:05:07.839159 DQM0 = 44, DQM1 = 38
4806 10:05:07.839261 DQ Delay:
4807 10:05:07.842137 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4808 10:05:07.845434 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4809 10:05:07.848699 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4810 10:05:07.852294 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4811 10:05:07.852376
4812 10:05:07.852441
4813 10:05:07.852502 ==
4814 10:05:07.855326 Dram Type= 6, Freq= 0, CH_1, rank 1
4815 10:05:07.859014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4816 10:05:07.862260 ==
4817 10:05:07.862342
4818 10:05:07.862407
4819 10:05:07.862466 TX Vref Scan disable
4820 10:05:07.865406 == TX Byte 0 ==
4821 10:05:07.868603 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4822 10:05:07.872203 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4823 10:05:07.875213 == TX Byte 1 ==
4824 10:05:07.878364 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4825 10:05:07.885248 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4826 10:05:07.885351 ==
4827 10:05:07.888540 Dram Type= 6, Freq= 0, CH_1, rank 1
4828 10:05:07.891613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4829 10:05:07.891725 ==
4830 10:05:07.891815
4831 10:05:07.891898
4832 10:05:07.894807 TX Vref Scan disable
4833 10:05:07.898413 == TX Byte 0 ==
4834 10:05:07.901384 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4835 10:05:07.904651 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4836 10:05:07.907951 == TX Byte 1 ==
4837 10:05:07.911216 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4838 10:05:07.914499 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4839 10:05:07.914691
4840 10:05:07.914853 [DATLAT]
4841 10:05:07.918018 Freq=600, CH1 RK1
4842 10:05:07.918208
4843 10:05:07.921305 DATLAT Default: 0x9
4844 10:05:07.921551 0, 0xFFFF, sum = 0
4845 10:05:07.924711 1, 0xFFFF, sum = 0
4846 10:05:07.925009 2, 0xFFFF, sum = 0
4847 10:05:07.928436 3, 0xFFFF, sum = 0
4848 10:05:07.928836 4, 0xFFFF, sum = 0
4849 10:05:07.931344 5, 0xFFFF, sum = 0
4850 10:05:07.931851 6, 0xFFFF, sum = 0
4851 10:05:07.934733 7, 0xFFFF, sum = 0
4852 10:05:07.935251 8, 0x0, sum = 1
4853 10:05:07.938323 9, 0x0, sum = 2
4854 10:05:07.938843 10, 0x0, sum = 3
4855 10:05:07.941533 11, 0x0, sum = 4
4856 10:05:07.941970 best_step = 9
4857 10:05:07.942496
4858 10:05:07.942951 ==
4859 10:05:07.944918 Dram Type= 6, Freq= 0, CH_1, rank 1
4860 10:05:07.947915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4861 10:05:07.948407 ==
4862 10:05:07.951233 RX Vref Scan: 0
4863 10:05:07.951716
4864 10:05:07.954437 RX Vref 0 -> 0, step: 1
4865 10:05:07.955018
4866 10:05:07.955514 RX Delay -179 -> 252, step: 8
4867 10:05:07.961767 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4868 10:05:07.965219 iDelay=205, Bit 1, Center 40 (-107 ~ 188) 296
4869 10:05:07.968703 iDelay=205, Bit 2, Center 32 (-115 ~ 180) 296
4870 10:05:07.972045 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4871 10:05:07.978666 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4872 10:05:07.982110 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4873 10:05:07.985393 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4874 10:05:07.988473 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4875 10:05:07.991849 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4876 10:05:07.998410 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4877 10:05:08.001674 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4878 10:05:08.004880 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4879 10:05:08.008203 iDelay=205, Bit 12, Center 48 (-107 ~ 204) 312
4880 10:05:08.014985 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4881 10:05:08.017980 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4882 10:05:08.021254 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4883 10:05:08.021333 ==
4884 10:05:08.024889 Dram Type= 6, Freq= 0, CH_1, rank 1
4885 10:05:08.031589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4886 10:05:08.031675 ==
4887 10:05:08.031784 DQS Delay:
4888 10:05:08.034448 DQS0 = 0, DQS1 = 0
4889 10:05:08.034556 DQM Delay:
4890 10:05:08.034663 DQM0 = 45, DQM1 = 37
4891 10:05:08.037785 DQ Delay:
4892 10:05:08.041204 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4893 10:05:08.044570 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4894 10:05:08.047648 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4895 10:05:08.050825 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4896 10:05:08.050917
4897 10:05:08.051024
4898 10:05:08.057588 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4899 10:05:08.061001 CH1 RK1: MR19=808, MR18=2B20
4900 10:05:08.067544 CH1_RK1: MR19=0x808, MR18=0x2B20, DQSOSC=401, MR23=63, INC=163, DEC=108
4901 10:05:08.070953 [RxdqsGatingPostProcess] freq 600
4902 10:05:08.074011 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4903 10:05:08.077415 Pre-setting of DQS Precalculation
4904 10:05:08.083983 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4905 10:05:08.090500 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4906 10:05:08.097139 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4907 10:05:08.097215
4908 10:05:08.097284
4909 10:05:08.100631 [Calibration Summary] 1200 Mbps
4910 10:05:08.103406 CH 0, Rank 0
4911 10:05:08.103511 SW Impedance : PASS
4912 10:05:08.107380 DUTY Scan : NO K
4913 10:05:08.107481 ZQ Calibration : PASS
4914 10:05:08.110421 Jitter Meter : NO K
4915 10:05:08.113783 CBT Training : PASS
4916 10:05:08.113887 Write leveling : PASS
4917 10:05:08.117007 RX DQS gating : PASS
4918 10:05:08.120400 RX DQ/DQS(RDDQC) : PASS
4919 10:05:08.120505 TX DQ/DQS : PASS
4920 10:05:08.123540 RX DATLAT : PASS
4921 10:05:08.126939 RX DQ/DQS(Engine): PASS
4922 10:05:08.127042 TX OE : NO K
4923 10:05:08.130256 All Pass.
4924 10:05:08.130358
4925 10:05:08.130451 CH 0, Rank 1
4926 10:05:08.133294 SW Impedance : PASS
4927 10:05:08.133400 DUTY Scan : NO K
4928 10:05:08.136663 ZQ Calibration : PASS
4929 10:05:08.139690 Jitter Meter : NO K
4930 10:05:08.139773 CBT Training : PASS
4931 10:05:08.143227 Write leveling : PASS
4932 10:05:08.146281 RX DQS gating : PASS
4933 10:05:08.146380 RX DQ/DQS(RDDQC) : PASS
4934 10:05:08.150165 TX DQ/DQS : PASS
4935 10:05:08.152856 RX DATLAT : PASS
4936 10:05:08.152961 RX DQ/DQS(Engine): PASS
4937 10:05:08.156632 TX OE : NO K
4938 10:05:08.156707 All Pass.
4939 10:05:08.156777
4940 10:05:08.159851 CH 1, Rank 0
4941 10:05:08.159957 SW Impedance : PASS
4942 10:05:08.162873 DUTY Scan : NO K
4943 10:05:08.166351 ZQ Calibration : PASS
4944 10:05:08.166462 Jitter Meter : NO K
4945 10:05:08.169948 CBT Training : PASS
4946 10:05:08.173257 Write leveling : PASS
4947 10:05:08.173358 RX DQS gating : PASS
4948 10:05:08.176112 RX DQ/DQS(RDDQC) : PASS
4949 10:05:08.176210 TX DQ/DQS : PASS
4950 10:05:08.179555 RX DATLAT : PASS
4951 10:05:08.182732 RX DQ/DQS(Engine): PASS
4952 10:05:08.182833 TX OE : NO K
4953 10:05:08.185795 All Pass.
4954 10:05:08.185892
4955 10:05:08.185973 CH 1, Rank 1
4956 10:05:08.189088 SW Impedance : PASS
4957 10:05:08.189185 DUTY Scan : NO K
4958 10:05:08.192477 ZQ Calibration : PASS
4959 10:05:08.196035 Jitter Meter : NO K
4960 10:05:08.196132 CBT Training : PASS
4961 10:05:08.199190 Write leveling : PASS
4962 10:05:08.202717 RX DQS gating : PASS
4963 10:05:08.202818 RX DQ/DQS(RDDQC) : PASS
4964 10:05:08.205549 TX DQ/DQS : PASS
4965 10:05:08.208796 RX DATLAT : PASS
4966 10:05:08.208899 RX DQ/DQS(Engine): PASS
4967 10:05:08.212299 TX OE : NO K
4968 10:05:08.212403 All Pass.
4969 10:05:08.212495
4970 10:05:08.215655 DramC Write-DBI off
4971 10:05:08.218814 PER_BANK_REFRESH: Hybrid Mode
4972 10:05:08.218898 TX_TRACKING: ON
4973 10:05:08.228936 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4974 10:05:08.231827 [FAST_K] Save calibration result to emmc
4975 10:05:08.235122 dramc_set_vcore_voltage set vcore to 662500
4976 10:05:08.238413 Read voltage for 933, 3
4977 10:05:08.238525 Vio18 = 0
4978 10:05:08.238625 Vcore = 662500
4979 10:05:08.242421 Vdram = 0
4980 10:05:08.242533 Vddq = 0
4981 10:05:08.242629 Vmddr = 0
4982 10:05:08.248411 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4983 10:05:08.251816 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4984 10:05:08.255313 MEM_TYPE=3, freq_sel=17
4985 10:05:08.258474 sv_algorithm_assistance_LP4_1600
4986 10:05:08.261468 ============ PULL DRAM RESETB DOWN ============
4987 10:05:08.268240 ========== PULL DRAM RESETB DOWN end =========
4988 10:05:08.271466 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4989 10:05:08.274704 ===================================
4990 10:05:08.278155 LPDDR4 DRAM CONFIGURATION
4991 10:05:08.281682 ===================================
4992 10:05:08.281821 EX_ROW_EN[0] = 0x0
4993 10:05:08.284654 EX_ROW_EN[1] = 0x0
4994 10:05:08.284727 LP4Y_EN = 0x0
4995 10:05:08.288046 WORK_FSP = 0x0
4996 10:05:08.288142 WL = 0x3
4997 10:05:08.291199 RL = 0x3
4998 10:05:08.294577 BL = 0x2
4999 10:05:08.294674 RPST = 0x0
5000 10:05:08.297951 RD_PRE = 0x0
5001 10:05:08.298049 WR_PRE = 0x1
5002 10:05:08.301781 WR_PST = 0x0
5003 10:05:08.301878 DBI_WR = 0x0
5004 10:05:08.304306 DBI_RD = 0x0
5005 10:05:08.304432 OTF = 0x1
5006 10:05:08.307831 ===================================
5007 10:05:08.310980 ===================================
5008 10:05:08.314569 ANA top config
5009 10:05:08.317415 ===================================
5010 10:05:08.317531 DLL_ASYNC_EN = 0
5011 10:05:08.320771 ALL_SLAVE_EN = 1
5012 10:05:08.324035 NEW_RANK_MODE = 1
5013 10:05:08.327687 DLL_IDLE_MODE = 1
5014 10:05:08.327869 LP45_APHY_COMB_EN = 1
5015 10:05:08.330935 TX_ODT_DIS = 1
5016 10:05:08.334415 NEW_8X_MODE = 1
5017 10:05:08.337341 ===================================
5018 10:05:08.341297 ===================================
5019 10:05:08.344082 data_rate = 1866
5020 10:05:08.347563 CKR = 1
5021 10:05:08.350691 DQ_P2S_RATIO = 8
5022 10:05:08.353888 ===================================
5023 10:05:08.353970 CA_P2S_RATIO = 8
5024 10:05:08.357204 DQ_CA_OPEN = 0
5025 10:05:08.360675 DQ_SEMI_OPEN = 0
5026 10:05:08.364520 CA_SEMI_OPEN = 0
5027 10:05:08.367081 CA_FULL_RATE = 0
5028 10:05:08.370669 DQ_CKDIV4_EN = 1
5029 10:05:08.370779 CA_CKDIV4_EN = 1
5030 10:05:08.373515 CA_PREDIV_EN = 0
5031 10:05:08.377314 PH8_DLY = 0
5032 10:05:08.380613 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5033 10:05:08.383421 DQ_AAMCK_DIV = 4
5034 10:05:08.386729 CA_AAMCK_DIV = 4
5035 10:05:08.389940 CA_ADMCK_DIV = 4
5036 10:05:08.390019 DQ_TRACK_CA_EN = 0
5037 10:05:08.393574 CA_PICK = 933
5038 10:05:08.396450 CA_MCKIO = 933
5039 10:05:08.399971 MCKIO_SEMI = 0
5040 10:05:08.403352 PLL_FREQ = 3732
5041 10:05:08.406896 DQ_UI_PI_RATIO = 32
5042 10:05:08.409725 CA_UI_PI_RATIO = 0
5043 10:05:08.413521 ===================================
5044 10:05:08.416447 ===================================
5045 10:05:08.416562 memory_type:LPDDR4
5046 10:05:08.419874 GP_NUM : 10
5047 10:05:08.423107 SRAM_EN : 1
5048 10:05:08.423193 MD32_EN : 0
5049 10:05:08.426600 ===================================
5050 10:05:08.429902 [ANA_INIT] >>>>>>>>>>>>>>
5051 10:05:08.433287 <<<<<< [CONFIGURE PHASE]: ANA_TX
5052 10:05:08.436429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5053 10:05:08.439942 ===================================
5054 10:05:08.442637 data_rate = 1866,PCW = 0X8f00
5055 10:05:08.446392 ===================================
5056 10:05:08.449834 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5057 10:05:08.452769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5058 10:05:08.459372 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5059 10:05:08.462586 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5060 10:05:08.465931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5061 10:05:08.469405 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5062 10:05:08.473054 [ANA_INIT] flow start
5063 10:05:08.476356 [ANA_INIT] PLL >>>>>>>>
5064 10:05:08.476463 [ANA_INIT] PLL <<<<<<<<
5065 10:05:08.479146 [ANA_INIT] MIDPI >>>>>>>>
5066 10:05:08.482523 [ANA_INIT] MIDPI <<<<<<<<
5067 10:05:08.486209 [ANA_INIT] DLL >>>>>>>>
5068 10:05:08.486293 [ANA_INIT] flow end
5069 10:05:08.489359 ============ LP4 DIFF to SE enter ============
5070 10:05:08.495829 ============ LP4 DIFF to SE exit ============
5071 10:05:08.495941 [ANA_INIT] <<<<<<<<<<<<<
5072 10:05:08.499652 [Flow] Enable top DCM control >>>>>
5073 10:05:08.502401 [Flow] Enable top DCM control <<<<<
5074 10:05:08.505811 Enable DLL master slave shuffle
5075 10:05:08.512231 ==============================================================
5076 10:05:08.512316 Gating Mode config
5077 10:05:08.518831 ==============================================================
5078 10:05:08.522173 Config description:
5079 10:05:08.532324 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5080 10:05:08.538733 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5081 10:05:08.542367 SELPH_MODE 0: By rank 1: By Phase
5082 10:05:08.548480 ==============================================================
5083 10:05:08.551782 GAT_TRACK_EN = 1
5084 10:05:08.555035 RX_GATING_MODE = 2
5085 10:05:08.558318 RX_GATING_TRACK_MODE = 2
5086 10:05:08.558403 SELPH_MODE = 1
5087 10:05:08.561756 PICG_EARLY_EN = 1
5088 10:05:08.564809 VALID_LAT_VALUE = 1
5089 10:05:08.571961 ==============================================================
5090 10:05:08.575337 Enter into Gating configuration >>>>
5091 10:05:08.578281 Exit from Gating configuration <<<<
5092 10:05:08.581702 Enter into DVFS_PRE_config >>>>>
5093 10:05:08.591419 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5094 10:05:08.594993 Exit from DVFS_PRE_config <<<<<
5095 10:05:08.598293 Enter into PICG configuration >>>>
5096 10:05:08.601921 Exit from PICG configuration <<<<
5097 10:05:08.604933 [RX_INPUT] configuration >>>>>
5098 10:05:08.608329 [RX_INPUT] configuration <<<<<
5099 10:05:08.611244 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5100 10:05:08.617979 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5101 10:05:08.624398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5102 10:05:08.631119 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5103 10:05:08.637894 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5104 10:05:08.641124 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5105 10:05:08.647811 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5106 10:05:08.651287 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5107 10:05:08.654401 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5108 10:05:08.657746 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5109 10:05:08.664807 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5110 10:05:08.668061 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5111 10:05:08.670694 ===================================
5112 10:05:08.674461 LPDDR4 DRAM CONFIGURATION
5113 10:05:08.677331 ===================================
5114 10:05:08.677416 EX_ROW_EN[0] = 0x0
5115 10:05:08.680637 EX_ROW_EN[1] = 0x0
5116 10:05:08.680748 LP4Y_EN = 0x0
5117 10:05:08.683966 WORK_FSP = 0x0
5118 10:05:08.684080 WL = 0x3
5119 10:05:08.687430 RL = 0x3
5120 10:05:08.687513 BL = 0x2
5121 10:05:08.690486 RPST = 0x0
5122 10:05:08.693908 RD_PRE = 0x0
5123 10:05:08.694007 WR_PRE = 0x1
5124 10:05:08.697350 WR_PST = 0x0
5125 10:05:08.697433 DBI_WR = 0x0
5126 10:05:08.700660 DBI_RD = 0x0
5127 10:05:08.700744 OTF = 0x1
5128 10:05:08.704009 ===================================
5129 10:05:08.706965 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5130 10:05:08.713743 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5131 10:05:08.716697 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5132 10:05:08.720012 ===================================
5133 10:05:08.723582 LPDDR4 DRAM CONFIGURATION
5134 10:05:08.726884 ===================================
5135 10:05:08.727014 EX_ROW_EN[0] = 0x10
5136 10:05:08.730370 EX_ROW_EN[1] = 0x0
5137 10:05:08.730453 LP4Y_EN = 0x0
5138 10:05:08.733173 WORK_FSP = 0x0
5139 10:05:08.736500 WL = 0x3
5140 10:05:08.736619 RL = 0x3
5141 10:05:08.740062 BL = 0x2
5142 10:05:08.740144 RPST = 0x0
5143 10:05:08.743056 RD_PRE = 0x0
5144 10:05:08.743140 WR_PRE = 0x1
5145 10:05:08.746203 WR_PST = 0x0
5146 10:05:08.746301 DBI_WR = 0x0
5147 10:05:08.749600 DBI_RD = 0x0
5148 10:05:08.749727 OTF = 0x1
5149 10:05:08.753255 ===================================
5150 10:05:08.759536 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5151 10:05:08.763948 nWR fixed to 30
5152 10:05:08.767365 [ModeRegInit_LP4] CH0 RK0
5153 10:05:08.767439 [ModeRegInit_LP4] CH0 RK1
5154 10:05:08.770532 [ModeRegInit_LP4] CH1 RK0
5155 10:05:08.773788 [ModeRegInit_LP4] CH1 RK1
5156 10:05:08.773861 match AC timing 9
5157 10:05:08.780672 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5158 10:05:08.783431 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5159 10:05:08.786871 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5160 10:05:08.793697 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5161 10:05:08.797087 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5162 10:05:08.797168 ==
5163 10:05:08.800016 Dram Type= 6, Freq= 0, CH_0, rank 0
5164 10:05:08.803360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 10:05:08.803461 ==
5166 10:05:08.810193 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5167 10:05:08.816701 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5168 10:05:08.819771 [CA 0] Center 37 (7~68) winsize 62
5169 10:05:08.823284 [CA 1] Center 37 (7~68) winsize 62
5170 10:05:08.826828 [CA 2] Center 34 (4~65) winsize 62
5171 10:05:08.829601 [CA 3] Center 35 (5~65) winsize 61
5172 10:05:08.832932 [CA 4] Center 33 (3~64) winsize 62
5173 10:05:08.836653 [CA 5] Center 33 (3~63) winsize 61
5174 10:05:08.836739
5175 10:05:08.839279 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5176 10:05:08.839360
5177 10:05:08.842695 [CATrainingPosCal] consider 1 rank data
5178 10:05:08.845921 u2DelayCellTimex100 = 270/100 ps
5179 10:05:08.849094 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5180 10:05:08.853049 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5181 10:05:08.856018 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5182 10:05:08.862416 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5183 10:05:08.866171 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5184 10:05:08.869311 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5185 10:05:08.869426
5186 10:05:08.872470 CA PerBit enable=1, Macro0, CA PI delay=33
5187 10:05:08.872601
5188 10:05:08.875619 [CBTSetCACLKResult] CA Dly = 33
5189 10:05:08.875727 CS Dly: 7 (0~38)
5190 10:05:08.875821 ==
5191 10:05:08.878912 Dram Type= 6, Freq= 0, CH_0, rank 1
5192 10:05:08.885866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 10:05:08.885953 ==
5194 10:05:08.889336 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5195 10:05:08.895607 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5196 10:05:08.898878 [CA 0] Center 37 (7~68) winsize 62
5197 10:05:08.902243 [CA 1] Center 37 (7~68) winsize 62
5198 10:05:08.905338 [CA 2] Center 34 (4~65) winsize 62
5199 10:05:08.908508 [CA 3] Center 34 (4~65) winsize 62
5200 10:05:08.912129 [CA 4] Center 33 (3~64) winsize 62
5201 10:05:08.915813 [CA 5] Center 33 (3~63) winsize 61
5202 10:05:08.915927
5203 10:05:08.918637 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5204 10:05:08.918750
5205 10:05:08.922158 [CATrainingPosCal] consider 2 rank data
5206 10:05:08.925321 u2DelayCellTimex100 = 270/100 ps
5207 10:05:08.928432 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5208 10:05:08.935061 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5209 10:05:08.938270 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5210 10:05:08.941753 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5211 10:05:08.945105 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5212 10:05:08.948448 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5213 10:05:08.948792
5214 10:05:08.951453 CA PerBit enable=1, Macro0, CA PI delay=33
5215 10:05:08.951544
5216 10:05:08.954976 [CBTSetCACLKResult] CA Dly = 33
5217 10:05:08.958275 CS Dly: 7 (0~39)
5218 10:05:08.958358
5219 10:05:08.961223 ----->DramcWriteLeveling(PI) begin...
5220 10:05:08.961308 ==
5221 10:05:08.964743 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 10:05:08.968308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 10:05:08.968402 ==
5224 10:05:08.971557 Write leveling (Byte 0): 34 => 34
5225 10:05:08.974569 Write leveling (Byte 1): 28 => 28
5226 10:05:08.978098 DramcWriteLeveling(PI) end<-----
5227 10:05:08.978181
5228 10:05:08.978247 ==
5229 10:05:08.981541 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 10:05:08.984424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 10:05:08.984535 ==
5232 10:05:08.988179 [Gating] SW mode calibration
5233 10:05:08.994740 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5234 10:05:09.001570 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5235 10:05:09.005217 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5236 10:05:09.007704 0 14 4 | B1->B0 | 3030 3434 | 0 1 | (1 1) (1 1)
5237 10:05:09.014270 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5238 10:05:09.017926 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5239 10:05:09.020866 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5240 10:05:09.028042 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5241 10:05:09.030909 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5242 10:05:09.034433 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5243 10:05:09.040985 0 15 0 | B1->B0 | 3232 2525 | 1 0 | (1 1) (0 0)
5244 10:05:09.044176 0 15 4 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
5245 10:05:09.047213 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5246 10:05:09.053900 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5247 10:05:09.057114 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5248 10:05:09.060325 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5249 10:05:09.067390 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5250 10:05:09.070698 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5251 10:05:09.073944 1 0 0 | B1->B0 | 2d2d 4141 | 0 1 | (0 0) (0 0)
5252 10:05:09.080451 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5253 10:05:09.083827 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5254 10:05:09.087278 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5255 10:05:09.094146 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5256 10:05:09.096958 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5257 10:05:09.100632 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5258 10:05:09.107150 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5259 10:05:09.110375 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5260 10:05:09.113727 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5261 10:05:09.120013 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5262 10:05:09.123605 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5263 10:05:09.126501 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5264 10:05:09.133368 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5265 10:05:09.136771 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5266 10:05:09.139820 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5267 10:05:09.146360 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5268 10:05:09.149531 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5269 10:05:09.153497 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5270 10:05:09.159565 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5271 10:05:09.163115 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5272 10:05:09.166113 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5273 10:05:09.173224 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5274 10:05:09.176240 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5275 10:05:09.179513 Total UI for P1: 0, mck2ui 16
5276 10:05:09.182679 best dqsien dly found for B0: ( 1, 2, 26)
5277 10:05:09.185952 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5278 10:05:09.192912 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5279 10:05:09.192996 Total UI for P1: 0, mck2ui 16
5280 10:05:09.199687 best dqsien dly found for B1: ( 1, 3, 2)
5281 10:05:09.202599 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5282 10:05:09.205951 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5283 10:05:09.206035
5284 10:05:09.209629 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5285 10:05:09.212711 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5286 10:05:09.215967 [Gating] SW calibration Done
5287 10:05:09.216052 ==
5288 10:05:09.219508 Dram Type= 6, Freq= 0, CH_0, rank 0
5289 10:05:09.222624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 10:05:09.222701 ==
5291 10:05:09.225648 RX Vref Scan: 0
5292 10:05:09.225724
5293 10:05:09.225787 RX Vref 0 -> 0, step: 1
5294 10:05:09.225884
5295 10:05:09.229008 RX Delay -80 -> 252, step: 8
5296 10:05:09.232604 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5297 10:05:09.239273 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5298 10:05:09.242272 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5299 10:05:09.245575 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5300 10:05:09.249370 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5301 10:05:09.252030 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5302 10:05:09.255857 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5303 10:05:09.262370 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5304 10:05:09.265651 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5305 10:05:09.268569 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5306 10:05:09.272438 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5307 10:05:09.275605 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5308 10:05:09.282271 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5309 10:05:09.285035 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5310 10:05:09.288250 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5311 10:05:09.292034 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5312 10:05:09.292145 ==
5313 10:05:09.294850 Dram Type= 6, Freq= 0, CH_0, rank 0
5314 10:05:09.301962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 10:05:09.302073 ==
5316 10:05:09.302169 DQS Delay:
5317 10:05:09.304872 DQS0 = 0, DQS1 = 0
5318 10:05:09.304980 DQM Delay:
5319 10:05:09.305075 DQM0 = 97, DQM1 = 86
5320 10:05:09.308393 DQ Delay:
5321 10:05:09.311267 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5322 10:05:09.314810 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5323 10:05:09.318327 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5324 10:05:09.321710 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5325 10:05:09.321797
5326 10:05:09.321863
5327 10:05:09.321924 ==
5328 10:05:09.324682 Dram Type= 6, Freq= 0, CH_0, rank 0
5329 10:05:09.328061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 10:05:09.328150 ==
5331 10:05:09.328216
5332 10:05:09.328277
5333 10:05:09.331723 TX Vref Scan disable
5334 10:05:09.334863 == TX Byte 0 ==
5335 10:05:09.338251 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5336 10:05:09.341707 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5337 10:05:09.344383 == TX Byte 1 ==
5338 10:05:09.347772 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5339 10:05:09.351262 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5340 10:05:09.351370 ==
5341 10:05:09.354365 Dram Type= 6, Freq= 0, CH_0, rank 0
5342 10:05:09.357711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 10:05:09.361010 ==
5344 10:05:09.361091
5345 10:05:09.361156
5346 10:05:09.361216 TX Vref Scan disable
5347 10:05:09.365082 == TX Byte 0 ==
5348 10:05:09.367773 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5349 10:05:09.374376 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5350 10:05:09.374459 == TX Byte 1 ==
5351 10:05:09.377875 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5352 10:05:09.384675 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5353 10:05:09.384759
5354 10:05:09.384824 [DATLAT]
5355 10:05:09.384886 Freq=933, CH0 RK0
5356 10:05:09.384944
5357 10:05:09.388026 DATLAT Default: 0xd
5358 10:05:09.391093 0, 0xFFFF, sum = 0
5359 10:05:09.391176 1, 0xFFFF, sum = 0
5360 10:05:09.394636 2, 0xFFFF, sum = 0
5361 10:05:09.394760 3, 0xFFFF, sum = 0
5362 10:05:09.397988 4, 0xFFFF, sum = 0
5363 10:05:09.398111 5, 0xFFFF, sum = 0
5364 10:05:09.401197 6, 0xFFFF, sum = 0
5365 10:05:09.401276 7, 0xFFFF, sum = 0
5366 10:05:09.404364 8, 0xFFFF, sum = 0
5367 10:05:09.404443 9, 0xFFFF, sum = 0
5368 10:05:09.407264 10, 0x0, sum = 1
5369 10:05:09.407346 11, 0x0, sum = 2
5370 10:05:09.410867 12, 0x0, sum = 3
5371 10:05:09.410945 13, 0x0, sum = 4
5372 10:05:09.414202 best_step = 11
5373 10:05:09.414284
5374 10:05:09.414349 ==
5375 10:05:09.417694 Dram Type= 6, Freq= 0, CH_0, rank 0
5376 10:05:09.420852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 10:05:09.420933 ==
5378 10:05:09.420997 RX Vref Scan: 1
5379 10:05:09.421056
5380 10:05:09.423734 RX Vref 0 -> 0, step: 1
5381 10:05:09.423840
5382 10:05:09.427424 RX Delay -61 -> 252, step: 4
5383 10:05:09.427538
5384 10:05:09.430856 Set Vref, RX VrefLevel [Byte0]: 61
5385 10:05:09.433723 [Byte1]: 58
5386 10:05:09.437476
5387 10:05:09.437576 Final RX Vref Byte 0 = 61 to rank0
5388 10:05:09.440901 Final RX Vref Byte 1 = 58 to rank0
5389 10:05:09.444288 Final RX Vref Byte 0 = 61 to rank1
5390 10:05:09.447299 Final RX Vref Byte 1 = 58 to rank1==
5391 10:05:09.450698 Dram Type= 6, Freq= 0, CH_0, rank 0
5392 10:05:09.456952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 10:05:09.457061 ==
5394 10:05:09.457157 DQS Delay:
5395 10:05:09.460650 DQS0 = 0, DQS1 = 0
5396 10:05:09.460748 DQM Delay:
5397 10:05:09.460842 DQM0 = 97, DQM1 = 88
5398 10:05:09.463731 DQ Delay:
5399 10:05:09.467204 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =96
5400 10:05:09.470026 DQ4 =96, DQ5 =88, DQ6 =106, DQ7 =104
5401 10:05:09.473473 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =84
5402 10:05:09.476782 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =96
5403 10:05:09.476880
5404 10:05:09.476990
5405 10:05:09.483705 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5406 10:05:09.487015 CH0 RK0: MR19=505, MR18=2A11
5407 10:05:09.492961 CH0_RK0: MR19=0x505, MR18=0x2A11, DQSOSC=408, MR23=63, INC=65, DEC=43
5408 10:05:09.493041
5409 10:05:09.496288 ----->DramcWriteLeveling(PI) begin...
5410 10:05:09.496370 ==
5411 10:05:09.499776 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 10:05:09.503350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 10:05:09.503431 ==
5414 10:05:09.506423 Write leveling (Byte 0): 35 => 35
5415 10:05:09.510070 Write leveling (Byte 1): 31 => 31
5416 10:05:09.513390 DramcWriteLeveling(PI) end<-----
5417 10:05:09.513472
5418 10:05:09.513535 ==
5419 10:05:09.516090 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 10:05:09.519404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 10:05:09.523173 ==
5422 10:05:09.523254 [Gating] SW mode calibration
5423 10:05:09.532983 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5424 10:05:09.536158 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5425 10:05:09.539700 0 14 0 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
5426 10:05:09.546051 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5427 10:05:09.549558 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5428 10:05:09.552397 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5429 10:05:09.559223 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5430 10:05:09.562329 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5431 10:05:09.565514 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5432 10:05:09.572253 0 14 28 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
5433 10:05:09.575657 0 15 0 | B1->B0 | 2f2f 2424 | 0 0 | (1 1) (0 0)
5434 10:05:09.579159 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5435 10:05:09.585345 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5436 10:05:09.588640 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5437 10:05:09.591837 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5438 10:05:09.599057 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5439 10:05:09.602233 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5440 10:05:09.605682 0 15 28 | B1->B0 | 2a2a 3737 | 0 1 | (0 0) (0 0)
5441 10:05:09.611668 1 0 0 | B1->B0 | 4141 4444 | 0 0 | (0 0) (0 0)
5442 10:05:09.615003 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5443 10:05:09.618542 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5444 10:05:09.625271 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5445 10:05:09.628585 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5446 10:05:09.631413 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5447 10:05:09.638325 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5448 10:05:09.641296 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5449 10:05:09.644833 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5450 10:05:09.651297 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5451 10:05:09.654461 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 10:05:09.658245 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 10:05:09.664745 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 10:05:09.668037 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 10:05:09.671426 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 10:05:09.677829 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 10:05:09.680975 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 10:05:09.684344 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5459 10:05:09.691051 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5460 10:05:09.694514 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5461 10:05:09.697773 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5462 10:05:09.704353 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5463 10:05:09.707539 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5464 10:05:09.710812 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5465 10:05:09.717307 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5466 10:05:09.720763 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5467 10:05:09.723906 Total UI for P1: 0, mck2ui 16
5468 10:05:09.727237 best dqsien dly found for B0: ( 1, 2, 30)
5469 10:05:09.730546 Total UI for P1: 0, mck2ui 16
5470 10:05:09.734293 best dqsien dly found for B1: ( 1, 2, 30)
5471 10:05:09.737192 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5472 10:05:09.740642 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5473 10:05:09.740760
5474 10:05:09.744145 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5475 10:05:09.750391 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5476 10:05:09.750476 [Gating] SW calibration Done
5477 10:05:09.750563 ==
5478 10:05:09.753798 Dram Type= 6, Freq= 0, CH_0, rank 1
5479 10:05:09.760488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5480 10:05:09.760596 ==
5481 10:05:09.760676 RX Vref Scan: 0
5482 10:05:09.760751
5483 10:05:09.763728 RX Vref 0 -> 0, step: 1
5484 10:05:09.763813
5485 10:05:09.767144 RX Delay -80 -> 252, step: 8
5486 10:05:09.770323 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5487 10:05:09.773755 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5488 10:05:09.777075 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5489 10:05:09.780016 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5490 10:05:09.786755 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5491 10:05:09.790520 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5492 10:05:09.793743 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5493 10:05:09.796631 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5494 10:05:09.799825 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5495 10:05:09.803307 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5496 10:05:09.810265 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5497 10:05:09.813201 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5498 10:05:09.816311 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5499 10:05:09.819738 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5500 10:05:09.823167 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5501 10:05:09.829860 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5502 10:05:09.829971 ==
5503 10:05:09.833073 Dram Type= 6, Freq= 0, CH_0, rank 1
5504 10:05:09.836014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 10:05:09.836119 ==
5506 10:05:09.836216 DQS Delay:
5507 10:05:09.839583 DQS0 = 0, DQS1 = 0
5508 10:05:09.839655 DQM Delay:
5509 10:05:09.843064 DQM0 = 96, DQM1 = 88
5510 10:05:09.843134 DQ Delay:
5511 10:05:09.845771 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5512 10:05:09.849145 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5513 10:05:09.853376 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5514 10:05:09.856061 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =91
5515 10:05:09.856145
5516 10:05:09.856213
5517 10:05:09.856275 ==
5518 10:05:09.859045 Dram Type= 6, Freq= 0, CH_0, rank 1
5519 10:05:09.865881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 10:05:09.865996 ==
5521 10:05:09.866093
5522 10:05:09.866184
5523 10:05:09.866274 TX Vref Scan disable
5524 10:05:09.869296 == TX Byte 0 ==
5525 10:05:09.872707 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5526 10:05:09.879331 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5527 10:05:09.879417 == TX Byte 1 ==
5528 10:05:09.882428 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5529 10:05:09.888766 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5530 10:05:09.888853 ==
5531 10:05:09.893112 Dram Type= 6, Freq= 0, CH_0, rank 1
5532 10:05:09.895637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 10:05:09.895749 ==
5534 10:05:09.895833
5535 10:05:09.895898
5536 10:05:09.898711 TX Vref Scan disable
5537 10:05:09.898795 == TX Byte 0 ==
5538 10:05:09.905586 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5539 10:05:09.908818 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5540 10:05:09.911951 == TX Byte 1 ==
5541 10:05:09.915250 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5542 10:05:09.918444 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5543 10:05:09.918552
5544 10:05:09.918647 [DATLAT]
5545 10:05:09.921889 Freq=933, CH0 RK1
5546 10:05:09.922002
5547 10:05:09.925327 DATLAT Default: 0xb
5548 10:05:09.925411 0, 0xFFFF, sum = 0
5549 10:05:09.928472 1, 0xFFFF, sum = 0
5550 10:05:09.928590 2, 0xFFFF, sum = 0
5551 10:05:09.932205 3, 0xFFFF, sum = 0
5552 10:05:09.932309 4, 0xFFFF, sum = 0
5553 10:05:09.934937 5, 0xFFFF, sum = 0
5554 10:05:09.935048 6, 0xFFFF, sum = 0
5555 10:05:09.938309 7, 0xFFFF, sum = 0
5556 10:05:09.938397 8, 0xFFFF, sum = 0
5557 10:05:09.941945 9, 0xFFFF, sum = 0
5558 10:05:09.942029 10, 0x0, sum = 1
5559 10:05:09.944973 11, 0x0, sum = 2
5560 10:05:09.945060 12, 0x0, sum = 3
5561 10:05:09.948267 13, 0x0, sum = 4
5562 10:05:09.948378 best_step = 11
5563 10:05:09.948472
5564 10:05:09.948576 ==
5565 10:05:09.951674 Dram Type= 6, Freq= 0, CH_0, rank 1
5566 10:05:09.955278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 10:05:09.958299 ==
5568 10:05:09.958385 RX Vref Scan: 0
5569 10:05:09.958453
5570 10:05:09.961676 RX Vref 0 -> 0, step: 1
5571 10:05:09.961760
5572 10:05:09.964668 RX Delay -61 -> 252, step: 4
5573 10:05:09.968038 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5574 10:05:09.971291 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5575 10:05:09.977846 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5576 10:05:09.981374 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5577 10:05:09.984339 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5578 10:05:09.987882 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5579 10:05:09.990974 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5580 10:05:09.994364 iDelay=203, Bit 7, Center 102 (7 ~ 198) 192
5581 10:05:10.000912 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5582 10:05:10.004118 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5583 10:05:10.007648 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5584 10:05:10.011020 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5585 10:05:10.013783 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5586 10:05:10.020425 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5587 10:05:10.024206 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5588 10:05:10.027642 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5589 10:05:10.027726 ==
5590 10:05:10.030867 Dram Type= 6, Freq= 0, CH_0, rank 1
5591 10:05:10.034153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 10:05:10.037105 ==
5593 10:05:10.037189 DQS Delay:
5594 10:05:10.037255 DQS0 = 0, DQS1 = 0
5595 10:05:10.040392 DQM Delay:
5596 10:05:10.040476 DQM0 = 94, DQM1 = 88
5597 10:05:10.043723 DQ Delay:
5598 10:05:10.043839 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
5599 10:05:10.047319 DQ4 =94, DQ5 =86, DQ6 =106, DQ7 =102
5600 10:05:10.050472 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =80
5601 10:05:10.057354 DQ12 =92, DQ13 =92, DQ14 =100, DQ15 =92
5602 10:05:10.057440
5603 10:05:10.057556
5604 10:05:10.063420 [DQSOSCAuto] RK1, (LSB)MR18= 0x28fa, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 409 ps
5605 10:05:10.067108 CH0 RK1: MR19=504, MR18=28FA
5606 10:05:10.073807 CH0_RK1: MR19=0x504, MR18=0x28FA, DQSOSC=409, MR23=63, INC=64, DEC=43
5607 10:05:10.077103 [RxdqsGatingPostProcess] freq 933
5608 10:05:10.080393 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5609 10:05:10.083255 best DQS0 dly(2T, 0.5T) = (0, 10)
5610 10:05:10.086499 best DQS1 dly(2T, 0.5T) = (0, 11)
5611 10:05:10.089634 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5612 10:05:10.092951 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5613 10:05:10.096492 best DQS0 dly(2T, 0.5T) = (0, 10)
5614 10:05:10.099960 best DQS1 dly(2T, 0.5T) = (0, 10)
5615 10:05:10.103118 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5616 10:05:10.106528 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5617 10:05:10.109408 Pre-setting of DQS Precalculation
5618 10:05:10.113303 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5619 10:05:10.115976 ==
5620 10:05:10.119350 Dram Type= 6, Freq= 0, CH_1, rank 0
5621 10:05:10.122705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5622 10:05:10.122951 ==
5623 10:05:10.129800 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5624 10:05:10.132559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5625 10:05:10.136593 [CA 0] Center 36 (6~67) winsize 62
5626 10:05:10.140475 [CA 1] Center 37 (6~68) winsize 63
5627 10:05:10.143494 [CA 2] Center 34 (4~65) winsize 62
5628 10:05:10.146747 [CA 3] Center 33 (3~64) winsize 62
5629 10:05:10.149783 [CA 4] Center 34 (4~64) winsize 61
5630 10:05:10.153314 [CA 5] Center 33 (3~64) winsize 62
5631 10:05:10.153783
5632 10:05:10.156198 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5633 10:05:10.156724
5634 10:05:10.159655 [CATrainingPosCal] consider 1 rank data
5635 10:05:10.163182 u2DelayCellTimex100 = 270/100 ps
5636 10:05:10.166074 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5637 10:05:10.173329 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5638 10:05:10.176578 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5639 10:05:10.179610 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5640 10:05:10.182953 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5641 10:05:10.186328 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5642 10:05:10.186758
5643 10:05:10.189521 CA PerBit enable=1, Macro0, CA PI delay=33
5644 10:05:10.190049
5645 10:05:10.192747 [CBTSetCACLKResult] CA Dly = 33
5646 10:05:10.195672 CS Dly: 5 (0~36)
5647 10:05:10.196188 ==
5648 10:05:10.199069 Dram Type= 6, Freq= 0, CH_1, rank 1
5649 10:05:10.202391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 10:05:10.202962 ==
5651 10:05:10.209057 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5652 10:05:10.212864 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5653 10:05:10.216770 [CA 0] Center 36 (6~67) winsize 62
5654 10:05:10.220029 [CA 1] Center 36 (6~67) winsize 62
5655 10:05:10.223104 [CA 2] Center 34 (3~65) winsize 63
5656 10:05:10.226507 [CA 3] Center 33 (3~64) winsize 62
5657 10:05:10.229892 [CA 4] Center 34 (3~65) winsize 63
5658 10:05:10.232928 [CA 5] Center 33 (3~64) winsize 62
5659 10:05:10.233348
5660 10:05:10.236665 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5661 10:05:10.237193
5662 10:05:10.239415 [CATrainingPosCal] consider 2 rank data
5663 10:05:10.242873 u2DelayCellTimex100 = 270/100 ps
5664 10:05:10.246750 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5665 10:05:10.253025 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5666 10:05:10.256496 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5667 10:05:10.259801 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5668 10:05:10.262583 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5669 10:05:10.266334 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5670 10:05:10.266757
5671 10:05:10.269576 CA PerBit enable=1, Macro0, CA PI delay=33
5672 10:05:10.269964
5673 10:05:10.272763 [CBTSetCACLKResult] CA Dly = 33
5674 10:05:10.276591 CS Dly: 6 (0~39)
5675 10:05:10.277011
5676 10:05:10.279709 ----->DramcWriteLeveling(PI) begin...
5677 10:05:10.280140 ==
5678 10:05:10.282818 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 10:05:10.286011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 10:05:10.286460 ==
5681 10:05:10.289221 Write leveling (Byte 0): 28 => 28
5682 10:05:10.292496 Write leveling (Byte 1): 28 => 28
5683 10:05:10.296065 DramcWriteLeveling(PI) end<-----
5684 10:05:10.296508
5685 10:05:10.296891 ==
5686 10:05:10.299166 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 10:05:10.302371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 10:05:10.302796 ==
5689 10:05:10.305767 [Gating] SW mode calibration
5690 10:05:10.312497 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5691 10:05:10.319237 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5692 10:05:10.322516 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (1 1) (1 1)
5693 10:05:10.325702 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5694 10:05:10.332272 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5695 10:05:10.335149 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5696 10:05:10.338661 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5697 10:05:10.345448 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5698 10:05:10.348252 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
5699 10:05:10.351553 0 14 28 | B1->B0 | 2e2e 2b2b | 1 1 | (1 0) (1 0)
5700 10:05:10.359097 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5701 10:05:10.361960 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5702 10:05:10.364908 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5703 10:05:10.371682 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5704 10:05:10.374662 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5705 10:05:10.378105 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5706 10:05:10.384597 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
5707 10:05:10.387778 0 15 28 | B1->B0 | 3535 3b3b | 0 0 | (0 0) (1 1)
5708 10:05:10.394284 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5709 10:05:10.397426 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5710 10:05:10.400854 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5711 10:05:10.404039 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5712 10:05:10.410941 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5713 10:05:10.414458 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5714 10:05:10.420728 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5715 10:05:10.423986 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5716 10:05:10.427368 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5717 10:05:10.430878 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5718 10:05:10.436956 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5719 10:05:10.440975 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5720 10:05:10.443962 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5721 10:05:10.450553 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5722 10:05:10.454040 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5723 10:05:10.460370 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5724 10:05:10.463817 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5725 10:05:10.467465 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5726 10:05:10.473345 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5727 10:05:10.476812 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5728 10:05:10.480031 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5729 10:05:10.483482 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5730 10:05:10.489894 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5731 10:05:10.493386 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5732 10:05:10.496746 Total UI for P1: 0, mck2ui 16
5733 10:05:10.499875 best dqsien dly found for B0: ( 1, 2, 24)
5734 10:05:10.503164 Total UI for P1: 0, mck2ui 16
5735 10:05:10.506633 best dqsien dly found for B1: ( 1, 2, 26)
5736 10:05:10.509910 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5737 10:05:10.513649 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5738 10:05:10.514076
5739 10:05:10.516726 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5740 10:05:10.523225 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5741 10:05:10.523794 [Gating] SW calibration Done
5742 10:05:10.524321 ==
5743 10:05:10.526379 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 10:05:10.532962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 10:05:10.533397 ==
5746 10:05:10.533741 RX Vref Scan: 0
5747 10:05:10.534060
5748 10:05:10.536481 RX Vref 0 -> 0, step: 1
5749 10:05:10.536893
5750 10:05:10.539711 RX Delay -80 -> 252, step: 8
5751 10:05:10.543032 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5752 10:05:10.546317 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5753 10:05:10.549771 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5754 10:05:10.553085 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5755 10:05:10.559324 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5756 10:05:10.562831 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5757 10:05:10.566162 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5758 10:05:10.569577 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5759 10:05:10.572094 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5760 10:05:10.579165 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5761 10:05:10.582104 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5762 10:05:10.585785 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5763 10:05:10.588615 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5764 10:05:10.592527 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5765 10:05:10.595630 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5766 10:05:10.601881 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5767 10:05:10.601967 ==
5768 10:05:10.605177 Dram Type= 6, Freq= 0, CH_1, rank 0
5769 10:05:10.608509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 10:05:10.608633 ==
5771 10:05:10.608723 DQS Delay:
5772 10:05:10.611714 DQS0 = 0, DQS1 = 0
5773 10:05:10.611827 DQM Delay:
5774 10:05:10.615335 DQM0 = 100, DQM1 = 91
5775 10:05:10.615450 DQ Delay:
5776 10:05:10.618284 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5777 10:05:10.622010 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5778 10:05:10.625226 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5779 10:05:10.628443 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5780 10:05:10.628560
5781 10:05:10.628662
5782 10:05:10.628733 ==
5783 10:05:10.631725 Dram Type= 6, Freq= 0, CH_1, rank 0
5784 10:05:10.638741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 10:05:10.638852 ==
5786 10:05:10.638954
5787 10:05:10.639053
5788 10:05:10.639150 TX Vref Scan disable
5789 10:05:10.641870 == TX Byte 0 ==
5790 10:05:10.644826 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5791 10:05:10.651982 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5792 10:05:10.652067 == TX Byte 1 ==
5793 10:05:10.654879 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5794 10:05:10.661677 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5795 10:05:10.661789 ==
5796 10:05:10.664864 Dram Type= 6, Freq= 0, CH_1, rank 0
5797 10:05:10.668261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 10:05:10.668366 ==
5799 10:05:10.668465
5800 10:05:10.668562
5801 10:05:10.671115 TX Vref Scan disable
5802 10:05:10.674523 == TX Byte 0 ==
5803 10:05:10.678675 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5804 10:05:10.681509 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5805 10:05:10.685214 == TX Byte 1 ==
5806 10:05:10.687848 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5807 10:05:10.691067 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5808 10:05:10.691159
5809 10:05:10.691234 [DATLAT]
5810 10:05:10.694448 Freq=933, CH1 RK0
5811 10:05:10.694548
5812 10:05:10.697947 DATLAT Default: 0xd
5813 10:05:10.698059 0, 0xFFFF, sum = 0
5814 10:05:10.700736 1, 0xFFFF, sum = 0
5815 10:05:10.700868 2, 0xFFFF, sum = 0
5816 10:05:10.704334 3, 0xFFFF, sum = 0
5817 10:05:10.704486 4, 0xFFFF, sum = 0
5818 10:05:10.708265 5, 0xFFFF, sum = 0
5819 10:05:10.708404 6, 0xFFFF, sum = 0
5820 10:05:10.711248 7, 0xFFFF, sum = 0
5821 10:05:10.711361 8, 0xFFFF, sum = 0
5822 10:05:10.714293 9, 0xFFFF, sum = 0
5823 10:05:10.714457 10, 0x0, sum = 1
5824 10:05:10.717293 11, 0x0, sum = 2
5825 10:05:10.717448 12, 0x0, sum = 3
5826 10:05:10.720952 13, 0x0, sum = 4
5827 10:05:10.721105 best_step = 11
5828 10:05:10.721214
5829 10:05:10.721315 ==
5830 10:05:10.724395 Dram Type= 6, Freq= 0, CH_1, rank 0
5831 10:05:10.727669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 10:05:10.730469 ==
5833 10:05:10.730679 RX Vref Scan: 1
5834 10:05:10.730868
5835 10:05:10.733721 RX Vref 0 -> 0, step: 1
5836 10:05:10.733953
5837 10:05:10.737292 RX Delay -69 -> 252, step: 4
5838 10:05:10.737495
5839 10:05:10.740794 Set Vref, RX VrefLevel [Byte0]: 47
5840 10:05:10.743815 [Byte1]: 52
5841 10:05:10.744165
5842 10:05:10.747206 Final RX Vref Byte 0 = 47 to rank0
5843 10:05:10.750826 Final RX Vref Byte 1 = 52 to rank0
5844 10:05:10.754036 Final RX Vref Byte 0 = 47 to rank1
5845 10:05:10.757073 Final RX Vref Byte 1 = 52 to rank1==
5846 10:05:10.760455 Dram Type= 6, Freq= 0, CH_1, rank 0
5847 10:05:10.763926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 10:05:10.764244 ==
5849 10:05:10.767247 DQS Delay:
5850 10:05:10.767651 DQS0 = 0, DQS1 = 0
5851 10:05:10.767902 DQM Delay:
5852 10:05:10.770166 DQM0 = 101, DQM1 = 94
5853 10:05:10.770556 DQ Delay:
5854 10:05:10.773629 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5855 10:05:10.776994 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =98
5856 10:05:10.779822 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =84
5857 10:05:10.783808 DQ12 =104, DQ13 =98, DQ14 =104, DQ15 =104
5858 10:05:10.784177
5859 10:05:10.787264
5860 10:05:10.793120 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5861 10:05:10.797207 CH1 RK0: MR19=505, MR18=1D0D
5862 10:05:10.803493 CH1_RK0: MR19=0x505, MR18=0x1D0D, DQSOSC=412, MR23=63, INC=63, DEC=42
5863 10:05:10.803800
5864 10:05:10.806790 ----->DramcWriteLeveling(PI) begin...
5865 10:05:10.807190 ==
5866 10:05:10.809626 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 10:05:10.813267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 10:05:10.813640 ==
5869 10:05:10.816382 Write leveling (Byte 0): 30 => 30
5870 10:05:10.819669 Write leveling (Byte 1): 31 => 31
5871 10:05:10.822904 DramcWriteLeveling(PI) end<-----
5872 10:05:10.823286
5873 10:05:10.823620 ==
5874 10:05:10.826533 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 10:05:10.829866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 10:05:10.830235 ==
5877 10:05:10.832562 [Gating] SW mode calibration
5878 10:05:10.839342 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5879 10:05:10.845989 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5880 10:05:10.849623 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5881 10:05:10.856001 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5882 10:05:10.859374 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5883 10:05:10.862624 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5884 10:05:10.869102 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5885 10:05:10.872562 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5886 10:05:10.876010 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
5887 10:05:10.882109 0 14 28 | B1->B0 | 2828 2d2d | 0 1 | (0 0) (1 0)
5888 10:05:10.885697 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5889 10:05:10.888913 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5890 10:05:10.895760 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5891 10:05:10.898948 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5892 10:05:10.902496 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5893 10:05:10.908727 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5894 10:05:10.912369 0 15 24 | B1->B0 | 2a2a 2525 | 1 0 | (0 0) (0 0)
5895 10:05:10.915400 0 15 28 | B1->B0 | 3a3a 3a3a | 0 1 | (0 0) (0 0)
5896 10:05:10.918754 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5897 10:05:10.925566 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5898 10:05:10.928481 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5899 10:05:10.931644 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5900 10:05:10.938608 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5901 10:05:10.941674 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5902 10:05:10.948392 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5903 10:05:10.951427 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5904 10:05:10.955306 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5905 10:05:10.958463 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5906 10:05:10.965164 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5907 10:05:10.968146 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5908 10:05:10.971351 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5909 10:05:10.978053 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5910 10:05:10.981681 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5911 10:05:10.984678 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5912 10:05:10.991039 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5913 10:05:10.994978 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5914 10:05:10.998046 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5915 10:05:11.005048 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5916 10:05:11.008074 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5917 10:05:11.010876 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5918 10:05:11.018196 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5919 10:05:11.021230 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5920 10:05:11.024372 Total UI for P1: 0, mck2ui 16
5921 10:05:11.027654 best dqsien dly found for B0: ( 1, 2, 24)
5922 10:05:11.030861 Total UI for P1: 0, mck2ui 16
5923 10:05:11.034148 best dqsien dly found for B1: ( 1, 2, 24)
5924 10:05:11.037657 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5925 10:05:11.041440 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5926 10:05:11.041912
5927 10:05:11.044542 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5928 10:05:11.051135 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5929 10:05:11.051679 [Gating] SW calibration Done
5930 10:05:11.052059 ==
5931 10:05:11.054152 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 10:05:11.060981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 10:05:11.061584 ==
5934 10:05:11.061935 RX Vref Scan: 0
5935 10:05:11.062291
5936 10:05:11.064006 RX Vref 0 -> 0, step: 1
5937 10:05:11.064583
5938 10:05:11.067431 RX Delay -80 -> 252, step: 8
5939 10:05:11.070180 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5940 10:05:11.073932 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5941 10:05:11.077852 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5942 10:05:11.080631 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5943 10:05:11.086929 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5944 10:05:11.090688 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5945 10:05:11.093923 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5946 10:05:11.096762 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5947 10:05:11.100228 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5948 10:05:11.106738 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5949 10:05:11.109844 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5950 10:05:11.113074 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5951 10:05:11.116657 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5952 10:05:11.120249 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5953 10:05:11.126387 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5954 10:05:11.129707 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5955 10:05:11.130241 ==
5956 10:05:11.132928 Dram Type= 6, Freq= 0, CH_1, rank 1
5957 10:05:11.136243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5958 10:05:11.136859 ==
5959 10:05:11.139533 DQS Delay:
5960 10:05:11.140054 DQS0 = 0, DQS1 = 0
5961 10:05:11.140573 DQM Delay:
5962 10:05:11.143122 DQM0 = 100, DQM1 = 91
5963 10:05:11.143749 DQ Delay:
5964 10:05:11.146386 DQ0 =103, DQ1 =99, DQ2 =87, DQ3 =99
5965 10:05:11.149926 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5966 10:05:11.153120 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5967 10:05:11.156368 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =99
5968 10:05:11.156913
5969 10:05:11.157295
5970 10:05:11.157639 ==
5971 10:05:11.159269 Dram Type= 6, Freq= 0, CH_1, rank 1
5972 10:05:11.166154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5973 10:05:11.166584 ==
5974 10:05:11.166931
5975 10:05:11.167250
5976 10:05:11.169703 TX Vref Scan disable
5977 10:05:11.170263 == TX Byte 0 ==
5978 10:05:11.172923 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5979 10:05:11.179382 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5980 10:05:11.179965 == TX Byte 1 ==
5981 10:05:11.182773 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5982 10:05:11.189361 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5983 10:05:11.189798 ==
5984 10:05:11.192912 Dram Type= 6, Freq= 0, CH_1, rank 1
5985 10:05:11.195695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5986 10:05:11.196309 ==
5987 10:05:11.196863
5988 10:05:11.197276
5989 10:05:11.199182 TX Vref Scan disable
5990 10:05:11.202490 == TX Byte 0 ==
5991 10:05:11.205905 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5992 10:05:11.208843 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5993 10:05:11.212852 == TX Byte 1 ==
5994 10:05:11.215703 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5995 10:05:11.218899 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5996 10:05:11.219437
5997 10:05:11.222273 [DATLAT]
5998 10:05:11.222784 Freq=933, CH1 RK1
5999 10:05:11.223344
6000 10:05:11.225553 DATLAT Default: 0xb
6001 10:05:11.226060 0, 0xFFFF, sum = 0
6002 10:05:11.229484 1, 0xFFFF, sum = 0
6003 10:05:11.230061 2, 0xFFFF, sum = 0
6004 10:05:11.232769 3, 0xFFFF, sum = 0
6005 10:05:11.233285 4, 0xFFFF, sum = 0
6006 10:05:11.235511 5, 0xFFFF, sum = 0
6007 10:05:11.236030 6, 0xFFFF, sum = 0
6008 10:05:11.238857 7, 0xFFFF, sum = 0
6009 10:05:11.239456 8, 0xFFFF, sum = 0
6010 10:05:11.242177 9, 0xFFFF, sum = 0
6011 10:05:11.242768 10, 0x0, sum = 1
6012 10:05:11.245698 11, 0x0, sum = 2
6013 10:05:11.246251 12, 0x0, sum = 3
6014 10:05:11.248607 13, 0x0, sum = 4
6015 10:05:11.249041 best_step = 11
6016 10:05:11.249385
6017 10:05:11.249709 ==
6018 10:05:11.252312 Dram Type= 6, Freq= 0, CH_1, rank 1
6019 10:05:11.259059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6020 10:05:11.259625 ==
6021 10:05:11.260114 RX Vref Scan: 0
6022 10:05:11.260493
6023 10:05:11.262661 RX Vref 0 -> 0, step: 1
6024 10:05:11.263090
6025 10:05:11.265241 RX Delay -69 -> 252, step: 4
6026 10:05:11.268830 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
6027 10:05:11.272005 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6028 10:05:11.278797 iDelay=207, Bit 2, Center 92 (7 ~ 178) 172
6029 10:05:11.282240 iDelay=207, Bit 3, Center 96 (11 ~ 182) 172
6030 10:05:11.285138 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6031 10:05:11.288630 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6032 10:05:11.291939 iDelay=207, Bit 6, Center 112 (19 ~ 206) 188
6033 10:05:11.295441 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6034 10:05:11.302465 iDelay=207, Bit 8, Center 80 (-9 ~ 170) 180
6035 10:05:11.305195 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
6036 10:05:11.308843 iDelay=207, Bit 10, Center 94 (7 ~ 182) 176
6037 10:05:11.311814 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6038 10:05:11.315432 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6039 10:05:11.318435 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
6040 10:05:11.325244 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
6041 10:05:11.328625 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6042 10:05:11.329095 ==
6043 10:05:11.332149 Dram Type= 6, Freq= 0, CH_1, rank 1
6044 10:05:11.335514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6045 10:05:11.336031 ==
6046 10:05:11.338292 DQS Delay:
6047 10:05:11.338776 DQS0 = 0, DQS1 = 0
6048 10:05:11.339308 DQM Delay:
6049 10:05:11.341565 DQM0 = 100, DQM1 = 92
6050 10:05:11.342013 DQ Delay:
6051 10:05:11.345456 DQ0 =104, DQ1 =94, DQ2 =92, DQ3 =96
6052 10:05:11.348070 DQ4 =98, DQ5 =110, DQ6 =112, DQ7 =98
6053 10:05:11.351457 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =84
6054 10:05:11.354701 DQ12 =102, DQ13 =100, DQ14 =98, DQ15 =102
6055 10:05:11.355226
6056 10:05:11.358020
6057 10:05:11.364629 [DQSOSCAuto] RK1, (LSB)MR18= 0xb04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 418 ps
6058 10:05:11.367734 CH1 RK1: MR19=505, MR18=B04
6059 10:05:11.374837 CH1_RK1: MR19=0x505, MR18=0xB04, DQSOSC=418, MR23=63, INC=62, DEC=41
6060 10:05:11.375251 [RxdqsGatingPostProcess] freq 933
6061 10:05:11.381126 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6062 10:05:11.384205 best DQS0 dly(2T, 0.5T) = (0, 10)
6063 10:05:11.387779 best DQS1 dly(2T, 0.5T) = (0, 10)
6064 10:05:11.391122 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6065 10:05:11.394565 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6066 10:05:11.397856 best DQS0 dly(2T, 0.5T) = (0, 10)
6067 10:05:11.400749 best DQS1 dly(2T, 0.5T) = (0, 10)
6068 10:05:11.403995 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6069 10:05:11.407482 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6070 10:05:11.410743 Pre-setting of DQS Precalculation
6071 10:05:11.413756 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6072 10:05:11.420573 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6073 10:05:11.430242 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6074 10:05:11.430683
6075 10:05:11.431120
6076 10:05:11.433951 [Calibration Summary] 1866 Mbps
6077 10:05:11.434375 CH 0, Rank 0
6078 10:05:11.436833 SW Impedance : PASS
6079 10:05:11.437406 DUTY Scan : NO K
6080 10:05:11.440578 ZQ Calibration : PASS
6081 10:05:11.444223 Jitter Meter : NO K
6082 10:05:11.444817 CBT Training : PASS
6083 10:05:11.446839 Write leveling : PASS
6084 10:05:11.450258 RX DQS gating : PASS
6085 10:05:11.450786 RX DQ/DQS(RDDQC) : PASS
6086 10:05:11.453545 TX DQ/DQS : PASS
6087 10:05:11.456786 RX DATLAT : PASS
6088 10:05:11.457208 RX DQ/DQS(Engine): PASS
6089 10:05:11.460136 TX OE : NO K
6090 10:05:11.460587 All Pass.
6091 10:05:11.460931
6092 10:05:11.463182 CH 0, Rank 1
6093 10:05:11.463604 SW Impedance : PASS
6094 10:05:11.467013 DUTY Scan : NO K
6095 10:05:11.467558 ZQ Calibration : PASS
6096 10:05:11.469795 Jitter Meter : NO K
6097 10:05:11.473583 CBT Training : PASS
6098 10:05:11.474091 Write leveling : PASS
6099 10:05:11.476584 RX DQS gating : PASS
6100 10:05:11.479732 RX DQ/DQS(RDDQC) : PASS
6101 10:05:11.480307 TX DQ/DQS : PASS
6102 10:05:11.483255 RX DATLAT : PASS
6103 10:05:11.486106 RX DQ/DQS(Engine): PASS
6104 10:05:11.486712 TX OE : NO K
6105 10:05:11.489750 All Pass.
6106 10:05:11.490374
6107 10:05:11.490954 CH 1, Rank 0
6108 10:05:11.492811 SW Impedance : PASS
6109 10:05:11.493376 DUTY Scan : NO K
6110 10:05:11.496336 ZQ Calibration : PASS
6111 10:05:11.499546 Jitter Meter : NO K
6112 10:05:11.500077 CBT Training : PASS
6113 10:05:11.502954 Write leveling : PASS
6114 10:05:11.506613 RX DQS gating : PASS
6115 10:05:11.507043 RX DQ/DQS(RDDQC) : PASS
6116 10:05:11.509730 TX DQ/DQS : PASS
6117 10:05:11.513225 RX DATLAT : PASS
6118 10:05:11.513653 RX DQ/DQS(Engine): PASS
6119 10:05:11.516006 TX OE : NO K
6120 10:05:11.516436 All Pass.
6121 10:05:11.516937
6122 10:05:11.519547 CH 1, Rank 1
6123 10:05:11.519996 SW Impedance : PASS
6124 10:05:11.522808 DUTY Scan : NO K
6125 10:05:11.526219 ZQ Calibration : PASS
6126 10:05:11.526643 Jitter Meter : NO K
6127 10:05:11.529569 CBT Training : PASS
6128 10:05:11.532941 Write leveling : PASS
6129 10:05:11.533362 RX DQS gating : PASS
6130 10:05:11.536036 RX DQ/DQS(RDDQC) : PASS
6131 10:05:11.536492 TX DQ/DQS : PASS
6132 10:05:11.539308 RX DATLAT : PASS
6133 10:05:11.542502 RX DQ/DQS(Engine): PASS
6134 10:05:11.542959 TX OE : NO K
6135 10:05:11.545935 All Pass.
6136 10:05:11.546389
6137 10:05:11.546765 DramC Write-DBI off
6138 10:05:11.549235 PER_BANK_REFRESH: Hybrid Mode
6139 10:05:11.552617 TX_TRACKING: ON
6140 10:05:11.559114 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6141 10:05:11.562191 [FAST_K] Save calibration result to emmc
6142 10:05:11.568594 dramc_set_vcore_voltage set vcore to 650000
6143 10:05:11.569001 Read voltage for 400, 6
6144 10:05:11.572190 Vio18 = 0
6145 10:05:11.572670 Vcore = 650000
6146 10:05:11.572996 Vdram = 0
6147 10:05:11.573333 Vddq = 0
6148 10:05:11.574963 Vmddr = 0
6149 10:05:11.578271 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6150 10:05:11.585588 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6151 10:05:11.588305 MEM_TYPE=3, freq_sel=20
6152 10:05:11.588489 sv_algorithm_assistance_LP4_800
6153 10:05:11.594954 ============ PULL DRAM RESETB DOWN ============
6154 10:05:11.598515 ========== PULL DRAM RESETB DOWN end =========
6155 10:05:11.601598 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6156 10:05:11.604861 ===================================
6157 10:05:11.608309 LPDDR4 DRAM CONFIGURATION
6158 10:05:11.611770 ===================================
6159 10:05:11.614566 EX_ROW_EN[0] = 0x0
6160 10:05:11.614825 EX_ROW_EN[1] = 0x0
6161 10:05:11.618218 LP4Y_EN = 0x0
6162 10:05:11.618401 WORK_FSP = 0x0
6163 10:05:11.621118 WL = 0x2
6164 10:05:11.621347 RL = 0x2
6165 10:05:11.624539 BL = 0x2
6166 10:05:11.624794 RPST = 0x0
6167 10:05:11.627916 RD_PRE = 0x0
6168 10:05:11.631278 WR_PRE = 0x1
6169 10:05:11.631474 WR_PST = 0x0
6170 10:05:11.634759 DBI_WR = 0x0
6171 10:05:11.635013 DBI_RD = 0x0
6172 10:05:11.637472 OTF = 0x1
6173 10:05:11.640999 ===================================
6174 10:05:11.644134 ===================================
6175 10:05:11.644327 ANA top config
6176 10:05:11.647868 ===================================
6177 10:05:11.650951 DLL_ASYNC_EN = 0
6178 10:05:11.654191 ALL_SLAVE_EN = 1
6179 10:05:11.654420 NEW_RANK_MODE = 1
6180 10:05:11.657736 DLL_IDLE_MODE = 1
6181 10:05:11.660966 LP45_APHY_COMB_EN = 1
6182 10:05:11.664659 TX_ODT_DIS = 1
6183 10:05:11.664875 NEW_8X_MODE = 1
6184 10:05:11.667500 ===================================
6185 10:05:11.670792 ===================================
6186 10:05:11.674010 data_rate = 800
6187 10:05:11.677576 CKR = 1
6188 10:05:11.680876 DQ_P2S_RATIO = 4
6189 10:05:11.683977 ===================================
6190 10:05:11.687213 CA_P2S_RATIO = 4
6191 10:05:11.690730 DQ_CA_OPEN = 0
6192 10:05:11.693914 DQ_SEMI_OPEN = 1
6193 10:05:11.694340 CA_SEMI_OPEN = 1
6194 10:05:11.697229 CA_FULL_RATE = 0
6195 10:05:11.700467 DQ_CKDIV4_EN = 0
6196 10:05:11.703538 CA_CKDIV4_EN = 1
6197 10:05:11.707072 CA_PREDIV_EN = 0
6198 10:05:11.710286 PH8_DLY = 0
6199 10:05:11.710742 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6200 10:05:11.713947 DQ_AAMCK_DIV = 0
6201 10:05:11.717144 CA_AAMCK_DIV = 0
6202 10:05:11.720333 CA_ADMCK_DIV = 4
6203 10:05:11.723840 DQ_TRACK_CA_EN = 0
6204 10:05:11.726868 CA_PICK = 800
6205 10:05:11.729984 CA_MCKIO = 400
6206 10:05:11.730409 MCKIO_SEMI = 400
6207 10:05:11.733183 PLL_FREQ = 3016
6208 10:05:11.736619 DQ_UI_PI_RATIO = 32
6209 10:05:11.739961 CA_UI_PI_RATIO = 32
6210 10:05:11.743483 ===================================
6211 10:05:11.746901 ===================================
6212 10:05:11.750245 memory_type:LPDDR4
6213 10:05:11.750670 GP_NUM : 10
6214 10:05:11.753851 SRAM_EN : 1
6215 10:05:11.756496 MD32_EN : 0
6216 10:05:11.759991 ===================================
6217 10:05:11.760462 [ANA_INIT] >>>>>>>>>>>>>>
6218 10:05:11.763256 <<<<<< [CONFIGURE PHASE]: ANA_TX
6219 10:05:11.766492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6220 10:05:11.770019 ===================================
6221 10:05:11.773548 data_rate = 800,PCW = 0X7400
6222 10:05:11.776102 ===================================
6223 10:05:11.779646 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6224 10:05:11.786140 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6225 10:05:11.796414 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6226 10:05:11.802846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6227 10:05:11.806072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6228 10:05:11.809504 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6229 10:05:11.809693 [ANA_INIT] flow start
6230 10:05:11.812624 [ANA_INIT] PLL >>>>>>>>
6231 10:05:11.815672 [ANA_INIT] PLL <<<<<<<<
6232 10:05:11.815829 [ANA_INIT] MIDPI >>>>>>>>
6233 10:05:11.819432 [ANA_INIT] MIDPI <<<<<<<<
6234 10:05:11.822097 [ANA_INIT] DLL >>>>>>>>
6235 10:05:11.822235 [ANA_INIT] flow end
6236 10:05:11.829386 ============ LP4 DIFF to SE enter ============
6237 10:05:11.832366 ============ LP4 DIFF to SE exit ============
6238 10:05:11.835568 [ANA_INIT] <<<<<<<<<<<<<
6239 10:05:11.839088 [Flow] Enable top DCM control >>>>>
6240 10:05:11.842500 [Flow] Enable top DCM control <<<<<
6241 10:05:11.842592 Enable DLL master slave shuffle
6242 10:05:11.848816 ==============================================================
6243 10:05:11.852435 Gating Mode config
6244 10:05:11.855210 ==============================================================
6245 10:05:11.858958 Config description:
6246 10:05:11.868483 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6247 10:05:11.875343 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6248 10:05:11.878286 SELPH_MODE 0: By rank 1: By Phase
6249 10:05:11.884910 ==============================================================
6250 10:05:11.888495 GAT_TRACK_EN = 0
6251 10:05:11.892019 RX_GATING_MODE = 2
6252 10:05:11.895195 RX_GATING_TRACK_MODE = 2
6253 10:05:11.898139 SELPH_MODE = 1
6254 10:05:11.902125 PICG_EARLY_EN = 1
6255 10:05:11.902303 VALID_LAT_VALUE = 1
6256 10:05:11.908634 ==============================================================
6257 10:05:11.911824 Enter into Gating configuration >>>>
6258 10:05:11.915500 Exit from Gating configuration <<<<
6259 10:05:11.918610 Enter into DVFS_PRE_config >>>>>
6260 10:05:11.928179 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6261 10:05:11.932173 Exit from DVFS_PRE_config <<<<<
6262 10:05:11.935048 Enter into PICG configuration >>>>
6263 10:05:11.938494 Exit from PICG configuration <<<<
6264 10:05:11.941739 [RX_INPUT] configuration >>>>>
6265 10:05:11.945002 [RX_INPUT] configuration <<<<<
6266 10:05:11.951211 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6267 10:05:11.954792 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6268 10:05:11.961142 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6269 10:05:11.968202 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6270 10:05:11.974676 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6271 10:05:11.981551 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6272 10:05:11.984305 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6273 10:05:11.987372 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6274 10:05:11.990614 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6275 10:05:11.997204 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6276 10:05:12.000494 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6277 10:05:12.004088 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6278 10:05:12.007139 ===================================
6279 10:05:12.010831 LPDDR4 DRAM CONFIGURATION
6280 10:05:12.013620 ===================================
6281 10:05:12.017436 EX_ROW_EN[0] = 0x0
6282 10:05:12.017547 EX_ROW_EN[1] = 0x0
6283 10:05:12.020186 LP4Y_EN = 0x0
6284 10:05:12.020305 WORK_FSP = 0x0
6285 10:05:12.023570 WL = 0x2
6286 10:05:12.023655 RL = 0x2
6287 10:05:12.026817 BL = 0x2
6288 10:05:12.026925 RPST = 0x0
6289 10:05:12.030312 RD_PRE = 0x0
6290 10:05:12.030441 WR_PRE = 0x1
6291 10:05:12.033791 WR_PST = 0x0
6292 10:05:12.033899 DBI_WR = 0x0
6293 10:05:12.036725 DBI_RD = 0x0
6294 10:05:12.036870 OTF = 0x1
6295 10:05:12.040333 ===================================
6296 10:05:12.046908 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6297 10:05:12.049813 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6298 10:05:12.053346 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6299 10:05:12.056784 ===================================
6300 10:05:12.059927 LPDDR4 DRAM CONFIGURATION
6301 10:05:12.063489 ===================================
6302 10:05:12.066785 EX_ROW_EN[0] = 0x10
6303 10:05:12.066898 EX_ROW_EN[1] = 0x0
6304 10:05:12.069994 LP4Y_EN = 0x0
6305 10:05:12.070090 WORK_FSP = 0x0
6306 10:05:12.073157 WL = 0x2
6307 10:05:12.073226 RL = 0x2
6308 10:05:12.076500 BL = 0x2
6309 10:05:12.076603 RPST = 0x0
6310 10:05:12.079800 RD_PRE = 0x0
6311 10:05:12.079882 WR_PRE = 0x1
6312 10:05:12.083380 WR_PST = 0x0
6313 10:05:12.083462 DBI_WR = 0x0
6314 10:05:12.086197 DBI_RD = 0x0
6315 10:05:12.086305 OTF = 0x1
6316 10:05:12.089751 ===================================
6317 10:05:12.096305 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6318 10:05:12.101204 nWR fixed to 30
6319 10:05:12.104708 [ModeRegInit_LP4] CH0 RK0
6320 10:05:12.104807 [ModeRegInit_LP4] CH0 RK1
6321 10:05:12.108003 [ModeRegInit_LP4] CH1 RK0
6322 10:05:12.111401 [ModeRegInit_LP4] CH1 RK1
6323 10:05:12.111485 match AC timing 19
6324 10:05:12.117695 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6325 10:05:12.121053 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6326 10:05:12.124454 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6327 10:05:12.131180 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6328 10:05:12.134353 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6329 10:05:12.134437 ==
6330 10:05:12.137662 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 10:05:12.140441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 10:05:12.140584 ==
6333 10:05:12.147351 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6334 10:05:12.153802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6335 10:05:12.157559 [CA 0] Center 36 (8~64) winsize 57
6336 10:05:12.160794 [CA 1] Center 36 (8~64) winsize 57
6337 10:05:12.163703 [CA 2] Center 36 (8~64) winsize 57
6338 10:05:12.167065 [CA 3] Center 36 (8~64) winsize 57
6339 10:05:12.170547 [CA 4] Center 36 (8~64) winsize 57
6340 10:05:12.173475 [CA 5] Center 36 (8~64) winsize 57
6341 10:05:12.173584
6342 10:05:12.176895 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6343 10:05:12.177006
6344 10:05:12.179728 [CATrainingPosCal] consider 1 rank data
6345 10:05:12.183091 u2DelayCellTimex100 = 270/100 ps
6346 10:05:12.186452 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 10:05:12.189836 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 10:05:12.193484 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 10:05:12.196547 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 10:05:12.200043 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6351 10:05:12.203012 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6352 10:05:12.203096
6353 10:05:12.209820 CA PerBit enable=1, Macro0, CA PI delay=36
6354 10:05:12.209903
6355 10:05:12.209970 [CBTSetCACLKResult] CA Dly = 36
6356 10:05:12.213554 CS Dly: 1 (0~32)
6357 10:05:12.213671 ==
6358 10:05:12.216034 Dram Type= 6, Freq= 0, CH_0, rank 1
6359 10:05:12.219416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 10:05:12.219518 ==
6361 10:05:12.226005 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6362 10:05:12.232738 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6363 10:05:12.236078 [CA 0] Center 36 (8~64) winsize 57
6364 10:05:12.239475 [CA 1] Center 36 (8~64) winsize 57
6365 10:05:12.242800 [CA 2] Center 36 (8~64) winsize 57
6366 10:05:12.246167 [CA 3] Center 36 (8~64) winsize 57
6367 10:05:12.249563 [CA 4] Center 36 (8~64) winsize 57
6368 10:05:12.249644 [CA 5] Center 36 (8~64) winsize 57
6369 10:05:12.252268
6370 10:05:12.255653 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6371 10:05:12.255759
6372 10:05:12.259195 [CATrainingPosCal] consider 2 rank data
6373 10:05:12.262668 u2DelayCellTimex100 = 270/100 ps
6374 10:05:12.265448 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6375 10:05:12.269453 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6376 10:05:12.272696 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6377 10:05:12.275299 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6378 10:05:12.278541 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6379 10:05:12.282211 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6380 10:05:12.282293
6381 10:05:12.288507 CA PerBit enable=1, Macro0, CA PI delay=36
6382 10:05:12.288605
6383 10:05:12.288675 [CBTSetCACLKResult] CA Dly = 36
6384 10:05:12.291972 CS Dly: 1 (0~32)
6385 10:05:12.292066
6386 10:05:12.295210 ----->DramcWriteLeveling(PI) begin...
6387 10:05:12.295312 ==
6388 10:05:12.298556 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 10:05:12.301836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 10:05:12.301948 ==
6391 10:05:12.305153 Write leveling (Byte 0): 40 => 8
6392 10:05:12.308424 Write leveling (Byte 1): 32 => 0
6393 10:05:12.311993 DramcWriteLeveling(PI) end<-----
6394 10:05:12.312171
6395 10:05:12.312324 ==
6396 10:05:12.315186 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 10:05:12.318286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 10:05:12.321434 ==
6399 10:05:12.321662 [Gating] SW mode calibration
6400 10:05:12.331825 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6401 10:05:12.335203 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6402 10:05:12.338438 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6403 10:05:12.345232 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6404 10:05:12.347938 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6405 10:05:12.351714 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6406 10:05:12.358228 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6407 10:05:12.361142 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6408 10:05:12.364487 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6409 10:05:12.371001 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6410 10:05:12.374641 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6411 10:05:12.377751 Total UI for P1: 0, mck2ui 16
6412 10:05:12.381290 best dqsien dly found for B0: ( 0, 14, 24)
6413 10:05:12.384711 Total UI for P1: 0, mck2ui 16
6414 10:05:12.387598 best dqsien dly found for B1: ( 0, 14, 24)
6415 10:05:12.390942 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6416 10:05:12.394078 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6417 10:05:12.394472
6418 10:05:12.397851 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6419 10:05:12.404444 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6420 10:05:12.404918 [Gating] SW calibration Done
6421 10:05:12.405429 ==
6422 10:05:12.407695 Dram Type= 6, Freq= 0, CH_0, rank 0
6423 10:05:12.414356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 10:05:12.414807 ==
6425 10:05:12.415198 RX Vref Scan: 0
6426 10:05:12.415534
6427 10:05:12.417689 RX Vref 0 -> 0, step: 1
6428 10:05:12.418198
6429 10:05:12.421009 RX Delay -410 -> 252, step: 16
6430 10:05:12.424362 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6431 10:05:12.427641 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6432 10:05:12.434342 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6433 10:05:12.437373 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6434 10:05:12.440657 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6435 10:05:12.443831 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6436 10:05:12.450420 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6437 10:05:12.454037 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6438 10:05:12.457594 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6439 10:05:12.460242 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6440 10:05:12.466772 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6441 10:05:12.470533 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6442 10:05:12.473627 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6443 10:05:12.476936 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6444 10:05:12.483437 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6445 10:05:12.486568 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6446 10:05:12.486859 ==
6447 10:05:12.489939 Dram Type= 6, Freq= 0, CH_0, rank 0
6448 10:05:12.493203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 10:05:12.493503 ==
6450 10:05:12.496594 DQS Delay:
6451 10:05:12.496875 DQS0 = 43, DQS1 = 59
6452 10:05:12.500042 DQM Delay:
6453 10:05:12.500316 DQM0 = 9, DQM1 = 12
6454 10:05:12.500586 DQ Delay:
6455 10:05:12.503350 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6456 10:05:12.507046 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6457 10:05:12.510083 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6458 10:05:12.513331 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6459 10:05:12.513561
6460 10:05:12.513766
6461 10:05:12.514031 ==
6462 10:05:12.516437 Dram Type= 6, Freq= 0, CH_0, rank 0
6463 10:05:12.523363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 10:05:12.523670 ==
6465 10:05:12.523930
6466 10:05:12.524176
6467 10:05:12.524418 TX Vref Scan disable
6468 10:05:13.865768 == TX Byte 0 ==
6469 10:05:13.866190 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6470 10:05:13.866300 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6471 10:05:13.866403 == TX Byte 1 ==
6472 10:05:13.866505 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6473 10:05:13.866636 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6474 10:05:13.866736 ==
6475 10:05:13.866835 Dram Type= 6, Freq= 0, CH_0, rank 0
6476 10:05:13.866933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 10:05:13.867028 ==
6478 10:05:13.867139
6479 10:05:13.867274
6480 10:05:13.867367 TX Vref Scan disable
6481 10:05:13.867476 == TX Byte 0 ==
6482 10:05:13.867582 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6483 10:05:13.867675 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6484 10:05:13.867768 == TX Byte 1 ==
6485 10:05:13.867861 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6486 10:05:13.867954 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6487 10:05:13.868047
6488 10:05:13.868139 [DATLAT]
6489 10:05:13.868230 Freq=400, CH0 RK0
6490 10:05:13.868323
6491 10:05:13.868432 DATLAT Default: 0xf
6492 10:05:13.868538 0, 0xFFFF, sum = 0
6493 10:05:13.868646 1, 0xFFFF, sum = 0
6494 10:05:13.868740 2, 0xFFFF, sum = 0
6495 10:05:13.868834 3, 0xFFFF, sum = 0
6496 10:05:13.868928 4, 0xFFFF, sum = 0
6497 10:05:13.869023 5, 0xFFFF, sum = 0
6498 10:05:13.869116 6, 0xFFFF, sum = 0
6499 10:05:13.869209 7, 0xFFFF, sum = 0
6500 10:05:13.869302 8, 0xFFFF, sum = 0
6501 10:05:13.869395 9, 0xFFFF, sum = 0
6502 10:05:13.869489 10, 0xFFFF, sum = 0
6503 10:05:13.869599 11, 0xFFFF, sum = 0
6504 10:05:13.869708 12, 0xFFFF, sum = 0
6505 10:05:13.869832 13, 0x0, sum = 1
6506 10:05:13.869925 14, 0x0, sum = 2
6507 10:05:13.870048 15, 0x0, sum = 3
6508 10:05:13.870143 16, 0x0, sum = 4
6509 10:05:13.870236 best_step = 14
6510 10:05:13.870328
6511 10:05:13.870421 ==
6512 10:05:13.870528 Dram Type= 6, Freq= 0, CH_0, rank 0
6513 10:05:13.870636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6514 10:05:13.870776 ==
6515 10:05:13.870883 RX Vref Scan: 1
6516 10:05:13.870976
6517 10:05:13.871068 RX Vref 0 -> 0, step: 1
6518 10:05:13.871160
6519 10:05:13.871252 RX Delay -359 -> 252, step: 8
6520 10:05:13.871345
6521 10:05:13.871437 Set Vref, RX VrefLevel [Byte0]: 61
6522 10:05:13.871547 [Byte1]: 58
6523 10:05:13.871642
6524 10:05:13.871737 Final RX Vref Byte 0 = 61 to rank0
6525 10:05:13.871833 Final RX Vref Byte 1 = 58 to rank0
6526 10:05:13.871940 Final RX Vref Byte 0 = 61 to rank1
6527 10:05:13.872050 Final RX Vref Byte 1 = 58 to rank1==
6528 10:05:13.872157 Dram Type= 6, Freq= 0, CH_0, rank 0
6529 10:05:13.872308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 10:05:13.872402 ==
6531 10:05:13.872512 DQS Delay:
6532 10:05:13.872624 DQS0 = 48, DQS1 = 60
6533 10:05:13.872801 DQM Delay:
6534 10:05:13.872908 DQM0 = 11, DQM1 = 11
6535 10:05:13.873061 DQ Delay:
6536 10:05:13.873184 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6537 10:05:13.873278 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6538 10:05:13.873369 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6539 10:05:13.873463 DQ12 =20, DQ13 =12, DQ14 =20, DQ15 =20
6540 10:05:13.873558
6541 10:05:13.873651
6542 10:05:13.873747 [DQSOSCAuto] RK0, (LSB)MR18= 0xb679, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 387 ps
6543 10:05:13.873846 CH0 RK0: MR19=C0C, MR18=B679
6544 10:05:13.873940 CH0_RK0: MR19=0xC0C, MR18=0xB679, DQSOSC=387, MR23=63, INC=394, DEC=262
6545 10:05:13.874042 ==
6546 10:05:13.874133 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 10:05:13.874229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 10:05:13.874357 ==
6549 10:05:13.874452 [Gating] SW mode calibration
6550 10:05:13.874546 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6551 10:05:13.874642 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6552 10:05:13.874764 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6553 10:05:13.874858 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6554 10:05:13.874953 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6555 10:05:13.875080 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6556 10:05:13.875175 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6557 10:05:13.875293 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6558 10:05:13.875400 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6559 10:05:13.875522 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6560 10:05:13.875615 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6561 10:05:13.875708 Total UI for P1: 0, mck2ui 16
6562 10:05:13.875802 best dqsien dly found for B0: ( 0, 14, 24)
6563 10:05:13.875896 Total UI for P1: 0, mck2ui 16
6564 10:05:13.875989 best dqsien dly found for B1: ( 0, 14, 24)
6565 10:05:13.876083 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6566 10:05:13.876191 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6567 10:05:13.876297
6568 10:05:13.876418 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6569 10:05:13.876511 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6570 10:05:13.876671 [Gating] SW calibration Done
6571 10:05:13.876792 ==
6572 10:05:13.876929 Dram Type= 6, Freq= 0, CH_0, rank 1
6573 10:05:13.877035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 10:05:13.877129 ==
6575 10:05:13.877266 RX Vref Scan: 0
6576 10:05:13.877373
6577 10:05:13.877466 RX Vref 0 -> 0, step: 1
6578 10:05:13.877559
6579 10:05:13.877693 RX Delay -410 -> 252, step: 16
6580 10:05:13.877828 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6581 10:05:13.877937 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6582 10:05:13.878033 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6583 10:05:13.878158 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6584 10:05:13.878253 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6585 10:05:13.878349 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6586 10:05:13.878446 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6587 10:05:13.878542 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6588 10:05:13.878637 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6589 10:05:13.878761 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6590 10:05:13.878868 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6591 10:05:13.878962 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6592 10:05:13.879055 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6593 10:05:13.879149 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6594 10:05:13.879243 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6595 10:05:13.879352 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6596 10:05:13.879459 ==
6597 10:05:13.879570 Dram Type= 6, Freq= 0, CH_0, rank 1
6598 10:05:13.879666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6599 10:05:13.879789 ==
6600 10:05:13.879883 DQS Delay:
6601 10:05:13.879978 DQS0 = 43, DQS1 = 59
6602 10:05:13.880085 DQM Delay:
6603 10:05:13.880178 DQM0 = 10, DQM1 = 14
6604 10:05:13.880271 DQ Delay:
6605 10:05:13.880364 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6606 10:05:13.880676 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6607 10:05:13.880779 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6608 10:05:13.880878 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6609 10:05:13.880976
6610 10:05:13.881073
6611 10:05:13.881170 ==
6612 10:05:13.881264 Dram Type= 6, Freq= 0, CH_0, rank 1
6613 10:05:13.881357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 10:05:13.881466 ==
6615 10:05:13.881561
6616 10:05:13.881654
6617 10:05:13.881766 TX Vref Scan disable
6618 10:05:13.881862 == TX Byte 0 ==
6619 10:05:13.881958 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6620 10:05:13.882056 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6621 10:05:13.882153 == TX Byte 1 ==
6622 10:05:13.882247 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6623 10:05:13.882340 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6624 10:05:13.882462 ==
6625 10:05:13.882556 Dram Type= 6, Freq= 0, CH_0, rank 1
6626 10:05:13.882672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6627 10:05:13.882794 ==
6628 10:05:13.882889
6629 10:05:13.882984
6630 10:05:13.883078 TX Vref Scan disable
6631 10:05:13.883174 == TX Byte 0 ==
6632 10:05:13.883281 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6633 10:05:13.883375 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6634 10:05:13.883468 == TX Byte 1 ==
6635 10:05:13.883561 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6636 10:05:13.883654 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6637 10:05:13.883747
6638 10:05:13.883839 [DATLAT]
6639 10:05:13.883932 Freq=400, CH0 RK1
6640 10:05:13.884025
6641 10:05:13.884117 DATLAT Default: 0xe
6642 10:05:13.884209 0, 0xFFFF, sum = 0
6643 10:05:13.884303 1, 0xFFFF, sum = 0
6644 10:05:13.884399 2, 0xFFFF, sum = 0
6645 10:05:13.884492 3, 0xFFFF, sum = 0
6646 10:05:13.884638 4, 0xFFFF, sum = 0
6647 10:05:13.884735 5, 0xFFFF, sum = 0
6648 10:05:13.884832 6, 0xFFFF, sum = 0
6649 10:05:13.884927 7, 0xFFFF, sum = 0
6650 10:05:13.885036 8, 0xFFFF, sum = 0
6651 10:05:13.885131 9, 0xFFFF, sum = 0
6652 10:05:13.885225 10, 0xFFFF, sum = 0
6653 10:05:13.885351 11, 0xFFFF, sum = 0
6654 10:05:13.885445 12, 0xFFFF, sum = 0
6655 10:05:13.885538 13, 0x0, sum = 1
6656 10:05:13.885631 14, 0x0, sum = 2
6657 10:05:13.885726 15, 0x0, sum = 3
6658 10:05:13.885820 16, 0x0, sum = 4
6659 10:05:13.885913 best_step = 14
6660 10:05:13.886006
6661 10:05:13.886114 ==
6662 10:05:13.886209 Dram Type= 6, Freq= 0, CH_0, rank 1
6663 10:05:13.886304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6664 10:05:13.886399 ==
6665 10:05:13.886507 RX Vref Scan: 0
6666 10:05:13.886599
6667 10:05:13.886692 RX Vref 0 -> 0, step: 1
6668 10:05:13.886784
6669 10:05:13.886876 RX Delay -359 -> 252, step: 8
6670 10:05:13.886969 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6671 10:05:13.887063 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6672 10:05:13.887157 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6673 10:05:13.887250 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6674 10:05:13.887343 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6675 10:05:13.887436 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6676 10:05:13.887528 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6677 10:05:13.887621 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6678 10:05:13.887713 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6679 10:05:13.887806 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6680 10:05:13.887898 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6681 10:05:13.887991 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6682 10:05:13.888084 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6683 10:05:13.888177 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6684 10:05:13.888270 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6685 10:05:13.888362 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6686 10:05:13.888455 ==
6687 10:05:13.888573 Dram Type= 6, Freq= 0, CH_0, rank 1
6688 10:05:13.888667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 10:05:13.888758 ==
6690 10:05:13.888896 DQS Delay:
6691 10:05:13.888987 DQS0 = 44, DQS1 = 60
6692 10:05:13.889082 DQM Delay:
6693 10:05:13.889179 DQM0 = 7, DQM1 = 14
6694 10:05:13.889271 DQ Delay:
6695 10:05:13.889370 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6696 10:05:13.889495 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6697 10:05:13.889590 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =4
6698 10:05:13.889736 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6699 10:05:13.889890
6700 10:05:13.890031
6701 10:05:13.890156 [DQSOSCAuto] RK1, (LSB)MR18= 0xb540, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6702 10:05:13.890251 CH0 RK1: MR19=C0C, MR18=B540
6703 10:05:13.890346 CH0_RK1: MR19=0xC0C, MR18=0xB540, DQSOSC=387, MR23=63, INC=394, DEC=262
6704 10:05:13.890440 [RxdqsGatingPostProcess] freq 400
6705 10:05:13.890550 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6706 10:05:13.890658 best DQS0 dly(2T, 0.5T) = (0, 10)
6707 10:05:13.890751 best DQS1 dly(2T, 0.5T) = (0, 10)
6708 10:05:13.890845 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6709 10:05:13.890938 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6710 10:05:13.891032 best DQS0 dly(2T, 0.5T) = (0, 10)
6711 10:05:13.891126 best DQS1 dly(2T, 0.5T) = (0, 10)
6712 10:05:13.891249 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6713 10:05:13.891342 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6714 10:05:13.891464 Pre-setting of DQS Precalculation
6715 10:05:13.891574 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6716 10:05:13.891670 ==
6717 10:05:13.891765 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 10:05:13.891860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 10:05:13.891968 ==
6720 10:05:13.892061 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6721 10:05:13.892156 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6722 10:05:13.892280 [CA 0] Center 36 (8~64) winsize 57
6723 10:05:13.892373 [CA 1] Center 36 (8~64) winsize 57
6724 10:05:13.892467 [CA 2] Center 36 (8~64) winsize 57
6725 10:05:13.892596 [CA 3] Center 36 (8~64) winsize 57
6726 10:05:13.892689 [CA 4] Center 36 (8~64) winsize 57
6727 10:05:13.892783 [CA 5] Center 36 (8~64) winsize 57
6728 10:05:13.892876
6729 10:05:13.892969 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6730 10:05:13.893092
6731 10:05:13.893186 [CATrainingPosCal] consider 1 rank data
6732 10:05:13.893280 u2DelayCellTimex100 = 270/100 ps
6733 10:05:13.893373 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 10:05:13.893467 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 10:05:13.893587 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 10:05:13.893681 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 10:05:13.893773 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6738 10:05:13.893866 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6739 10:05:13.893963
6740 10:05:13.894051 CA PerBit enable=1, Macro0, CA PI delay=36
6741 10:05:13.894147
6742 10:05:13.894245 [CBTSetCACLKResult] CA Dly = 36
6743 10:05:13.894335 CS Dly: 1 (0~32)
6744 10:05:13.894451 ==
6745 10:05:13.894761 Dram Type= 6, Freq= 0, CH_1, rank 1
6746 10:05:13.894843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 10:05:13.894904 ==
6748 10:05:13.894962 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6749 10:05:13.895020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6750 10:05:13.895112 [CA 0] Center 36 (8~64) winsize 57
6751 10:05:13.895200 [CA 1] Center 36 (8~64) winsize 57
6752 10:05:13.895271 [CA 2] Center 36 (8~64) winsize 57
6753 10:05:13.895390 [CA 3] Center 36 (8~64) winsize 57
6754 10:05:13.895498 [CA 4] Center 36 (8~64) winsize 57
6755 10:05:13.895577 [CA 5] Center 36 (8~64) winsize 57
6756 10:05:13.895710
6757 10:05:13.895780 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6758 10:05:13.895836
6759 10:05:13.895891 [CATrainingPosCal] consider 2 rank data
6760 10:05:13.895945 u2DelayCellTimex100 = 270/100 ps
6761 10:05:13.895999 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6762 10:05:13.896059 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6763 10:05:13.896147 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6764 10:05:13.896236 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6765 10:05:13.896326 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6766 10:05:13.896412 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6767 10:05:13.896525
6768 10:05:13.896628 CA PerBit enable=1, Macro0, CA PI delay=36
6769 10:05:13.896687
6770 10:05:13.896741 [CBTSetCACLKResult] CA Dly = 36
6771 10:05:13.896796 CS Dly: 1 (0~32)
6772 10:05:13.896849
6773 10:05:13.896903 ----->DramcWriteLeveling(PI) begin...
6774 10:05:13.896959 ==
6775 10:05:13.897013 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 10:05:13.897068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 10:05:13.897122 ==
6778 10:05:13.897176 Write leveling (Byte 0): 40 => 8
6779 10:05:13.897229 Write leveling (Byte 1): 40 => 8
6780 10:05:13.897307 DramcWriteLeveling(PI) end<-----
6781 10:05:13.897390
6782 10:05:13.897474 ==
6783 10:05:13.897531 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 10:05:13.897586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 10:05:13.897640 ==
6786 10:05:13.897694 [Gating] SW mode calibration
6787 10:05:13.897748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6788 10:05:13.897802 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6789 10:05:13.897856 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6790 10:05:13.897934 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6791 10:05:13.898027 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6792 10:05:13.898114 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6793 10:05:13.898206 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6794 10:05:13.898293 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6795 10:05:13.898382 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6796 10:05:13.898441 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6797 10:05:13.898497 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6798 10:05:13.898551 Total UI for P1: 0, mck2ui 16
6799 10:05:13.898606 best dqsien dly found for B0: ( 0, 14, 24)
6800 10:05:13.898660 Total UI for P1: 0, mck2ui 16
6801 10:05:13.898714 best dqsien dly found for B1: ( 0, 14, 24)
6802 10:05:13.898768 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6803 10:05:13.898822 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6804 10:05:13.898876
6805 10:05:13.898929 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6806 10:05:13.898998 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6807 10:05:13.899083 [Gating] SW calibration Done
6808 10:05:13.899172 ==
6809 10:05:13.899230 Dram Type= 6, Freq= 0, CH_1, rank 0
6810 10:05:13.899284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 10:05:13.899339 ==
6812 10:05:13.899393 RX Vref Scan: 0
6813 10:05:13.899446
6814 10:05:13.899500 RX Vref 0 -> 0, step: 1
6815 10:05:13.899553
6816 10:05:13.899638 RX Delay -410 -> 252, step: 16
6817 10:05:13.899722 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6818 10:05:13.899809 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6819 10:05:13.899895 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6820 10:05:13.899985 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6821 10:05:13.900059 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6822 10:05:13.900145 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6823 10:05:13.900236 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6824 10:05:13.900321 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6825 10:05:13.900408 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6826 10:05:13.900492 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6827 10:05:13.900606 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6828 10:05:13.900661 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6829 10:05:13.900741 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6830 10:05:13.900826 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6831 10:05:13.900917 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6832 10:05:13.901011 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6833 10:05:13.901098 ==
6834 10:05:13.901189 Dram Type= 6, Freq= 0, CH_1, rank 0
6835 10:05:13.901276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 10:05:13.901368 ==
6837 10:05:13.901453 DQS Delay:
6838 10:05:13.901544 DQS0 = 43, DQS1 = 51
6839 10:05:13.901630 DQM Delay:
6840 10:05:13.901721 DQM0 = 12, DQM1 = 14
6841 10:05:13.901835 DQ Delay:
6842 10:05:13.901926 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6843 10:05:13.902011 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6844 10:05:13.902099 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6845 10:05:13.902157 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6846 10:05:13.902212
6847 10:05:13.902266
6848 10:05:13.902320 ==
6849 10:05:13.902373 Dram Type= 6, Freq= 0, CH_1, rank 0
6850 10:05:13.902427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 10:05:13.902481 ==
6852 10:05:13.902539
6853 10:05:13.902626
6854 10:05:13.902747 TX Vref Scan disable
6855 10:05:13.902834 == TX Byte 0 ==
6856 10:05:13.902923 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6857 10:05:13.903012 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6858 10:05:13.903101 == TX Byte 1 ==
6859 10:05:13.903164 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6860 10:05:13.903220 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6861 10:05:13.903273 ==
6862 10:05:13.903328 Dram Type= 6, Freq= 0, CH_1, rank 0
6863 10:05:13.903389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 10:05:13.903476 ==
6865 10:05:13.903564
6866 10:05:13.903627
6867 10:05:13.903682 TX Vref Scan disable
6868 10:05:13.903735 == TX Byte 0 ==
6869 10:05:13.903789 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6870 10:05:13.903849 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6871 10:05:13.903937 == TX Byte 1 ==
6872 10:05:13.904207 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6873 10:05:13.904271 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6874 10:05:13.904327
6875 10:05:13.904382 [DATLAT]
6876 10:05:13.904435 Freq=400, CH1 RK0
6877 10:05:13.904490
6878 10:05:13.904614 DATLAT Default: 0xf
6879 10:05:13.904709 0, 0xFFFF, sum = 0
6880 10:05:13.904797 1, 0xFFFF, sum = 0
6881 10:05:13.904914 2, 0xFFFF, sum = 0
6882 10:05:13.905021 3, 0xFFFF, sum = 0
6883 10:05:13.905083 4, 0xFFFF, sum = 0
6884 10:05:13.905139 5, 0xFFFF, sum = 0
6885 10:05:13.905195 6, 0xFFFF, sum = 0
6886 10:05:13.905249 7, 0xFFFF, sum = 0
6887 10:05:13.905304 8, 0xFFFF, sum = 0
6888 10:05:13.905358 9, 0xFFFF, sum = 0
6889 10:05:13.905413 10, 0xFFFF, sum = 0
6890 10:05:13.905479 11, 0xFFFF, sum = 0
6891 10:05:13.905565 12, 0xFFFF, sum = 0
6892 10:05:13.905658 13, 0x0, sum = 1
6893 10:05:13.905718 14, 0x0, sum = 2
6894 10:05:13.905774 15, 0x0, sum = 3
6895 10:05:13.905829 16, 0x0, sum = 4
6896 10:05:13.905883 best_step = 14
6897 10:05:13.905960
6898 10:05:13.906043 ==
6899 10:05:13.906126 Dram Type= 6, Freq= 0, CH_1, rank 0
6900 10:05:13.906184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6901 10:05:13.906239 ==
6902 10:05:13.906292 RX Vref Scan: 1
6903 10:05:13.906345
6904 10:05:13.906399 RX Vref 0 -> 0, step: 1
6905 10:05:13.906453
6906 10:05:13.906507 RX Delay -343 -> 252, step: 8
6907 10:05:13.906573
6908 10:05:13.906659 Set Vref, RX VrefLevel [Byte0]: 47
6909 10:05:13.906747 [Byte1]: 52
6910 10:05:13.906838
6911 10:05:13.906923 Final RX Vref Byte 0 = 47 to rank0
6912 10:05:13.907014 Final RX Vref Byte 1 = 52 to rank0
6913 10:05:13.907099 Final RX Vref Byte 0 = 47 to rank1
6914 10:05:13.907190 Final RX Vref Byte 1 = 52 to rank1==
6915 10:05:13.907274 Dram Type= 6, Freq= 0, CH_1, rank 0
6916 10:05:13.907357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 10:05:13.907440 ==
6918 10:05:13.907522 DQS Delay:
6919 10:05:13.907609 DQS0 = 44, DQS1 = 52
6920 10:05:13.907693 DQM Delay:
6921 10:05:13.907776 DQM0 = 7, DQM1 = 9
6922 10:05:13.907833 DQ Delay:
6923 10:05:13.907887 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6924 10:05:13.907941 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6925 10:05:13.907995 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6926 10:05:13.908049 DQ12 =20, DQ13 =12, DQ14 =12, DQ15 =16
6927 10:05:13.908125
6928 10:05:13.908209
6929 10:05:13.908328 [DQSOSCAuto] RK0, (LSB)MR18= 0x966c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6930 10:05:13.908414 CH1 RK0: MR19=C0C, MR18=966C
6931 10:05:13.908504 CH1_RK0: MR19=0xC0C, MR18=0x966C, DQSOSC=391, MR23=63, INC=386, DEC=257
6932 10:05:13.908604 ==
6933 10:05:13.908659 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 10:05:13.908739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 10:05:13.908853 ==
6936 10:05:13.908928 [Gating] SW mode calibration
6937 10:05:13.909022 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6938 10:05:13.909119 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6939 10:05:13.909205 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6940 10:05:13.909278 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6941 10:05:13.909335 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6942 10:05:13.909406 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6943 10:05:13.909490 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6944 10:05:13.909576 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6945 10:05:13.909664 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6946 10:05:13.909723 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6947 10:05:13.909777 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6948 10:05:13.909831 Total UI for P1: 0, mck2ui 16
6949 10:05:13.909886 best dqsien dly found for B0: ( 0, 14, 24)
6950 10:05:13.909940 Total UI for P1: 0, mck2ui 16
6951 10:05:13.909994 best dqsien dly found for B1: ( 0, 14, 24)
6952 10:05:13.910047 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6953 10:05:13.910137 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6954 10:05:13.910257
6955 10:05:13.910344 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6956 10:05:13.910432 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6957 10:05:13.910521 [Gating] SW calibration Done
6958 10:05:13.910609 ==
6959 10:05:13.910699 Dram Type= 6, Freq= 0, CH_1, rank 1
6960 10:05:13.910784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6961 10:05:13.910906 ==
6962 10:05:13.910990 RX Vref Scan: 0
6963 10:05:13.911072
6964 10:05:13.911155 RX Vref 0 -> 0, step: 1
6965 10:05:13.911237
6966 10:05:13.911326 RX Delay -410 -> 252, step: 16
6967 10:05:13.911412 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6968 10:05:13.911483 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6969 10:05:13.911539 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6970 10:05:13.911604 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6971 10:05:13.911689 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6972 10:05:13.911778 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6973 10:05:13.911866 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6974 10:05:13.911954 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6975 10:05:13.912019 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6976 10:05:13.912074 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6977 10:05:13.912128 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6978 10:05:13.912182 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6979 10:05:13.912238 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6980 10:05:13.912326 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6981 10:05:13.912412 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6982 10:05:13.912503 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6983 10:05:13.912602 ==
6984 10:05:13.912657 Dram Type= 6, Freq= 0, CH_1, rank 1
6985 10:05:13.912711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6986 10:05:13.912767 ==
6987 10:05:13.912821 DQS Delay:
6988 10:05:13.912874 DQS0 = 51, DQS1 = 51
6989 10:05:13.912960 DQM Delay:
6990 10:05:13.913043 DQM0 = 20, DQM1 = 14
6991 10:05:13.913135 DQ Delay:
6992 10:05:13.913233 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6993 10:05:13.913313 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6994 10:05:13.913369 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6995 10:05:13.914968 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6996 10:05:13.915082
6997 10:05:13.915183
6998 10:05:13.915249 ==
6999 10:05:13.918517 Dram Type= 6, Freq= 0, CH_1, rank 1
7000 10:05:13.921944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7001 10:05:13.922028 ==
7002 10:05:13.922094
7003 10:05:13.922155
7004 10:05:13.925207 TX Vref Scan disable
7005 10:05:13.928891 == TX Byte 0 ==
7006 10:05:13.931881 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
7007 10:05:13.935169 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
7008 10:05:13.938293 == TX Byte 1 ==
7009 10:05:13.941538 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
7010 10:05:13.944888 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
7011 10:05:13.944972 ==
7012 10:05:13.947972 Dram Type= 6, Freq= 0, CH_1, rank 1
7013 10:05:13.951614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7014 10:05:13.954782 ==
7015 10:05:13.954865
7016 10:05:13.954930
7017 10:05:13.954991 TX Vref Scan disable
7018 10:05:13.958249 == TX Byte 0 ==
7019 10:05:13.961543 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
7020 10:05:13.964818 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
7021 10:05:13.967855 == TX Byte 1 ==
7022 10:05:13.971349 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
7023 10:05:13.974334 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
7024 10:05:13.974419
7025 10:05:13.977924 [DATLAT]
7026 10:05:13.978008 Freq=400, CH1 RK1
7027 10:05:13.978076
7028 10:05:13.980909 DATLAT Default: 0xe
7029 10:05:13.980993 0, 0xFFFF, sum = 0
7030 10:05:13.984556 1, 0xFFFF, sum = 0
7031 10:05:13.984643 2, 0xFFFF, sum = 0
7032 10:05:13.988008 3, 0xFFFF, sum = 0
7033 10:05:13.988094 4, 0xFFFF, sum = 0
7034 10:05:13.991108 5, 0xFFFF, sum = 0
7035 10:05:13.991194 6, 0xFFFF, sum = 0
7036 10:05:13.994576 7, 0xFFFF, sum = 0
7037 10:05:13.994662 8, 0xFFFF, sum = 0
7038 10:05:13.997405 9, 0xFFFF, sum = 0
7039 10:05:14.000812 10, 0xFFFF, sum = 0
7040 10:05:14.000898 11, 0xFFFF, sum = 0
7041 10:05:14.004254 12, 0xFFFF, sum = 0
7042 10:05:14.004340 13, 0x0, sum = 1
7043 10:05:14.007530 14, 0x0, sum = 2
7044 10:05:14.007616 15, 0x0, sum = 3
7045 10:05:14.010773 16, 0x0, sum = 4
7046 10:05:14.010859 best_step = 14
7047 10:05:14.010926
7048 10:05:14.010988 ==
7049 10:05:14.013932 Dram Type= 6, Freq= 0, CH_1, rank 1
7050 10:05:14.017150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7051 10:05:14.017235 ==
7052 10:05:14.020837 RX Vref Scan: 0
7053 10:05:14.020921
7054 10:05:14.023847 RX Vref 0 -> 0, step: 1
7055 10:05:14.023931
7056 10:05:14.023997 RX Delay -343 -> 252, step: 8
7057 10:05:14.033464 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7058 10:05:14.036408 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7059 10:05:14.039241 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7060 10:05:14.042599 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7061 10:05:14.049583 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7062 10:05:14.052748 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7063 10:05:14.056211 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7064 10:05:14.059357 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7065 10:05:14.066317 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7066 10:05:14.069077 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7067 10:05:14.072657 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7068 10:05:14.079031 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7069 10:05:14.082557 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7070 10:05:14.086016 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7071 10:05:14.089248 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7072 10:05:14.095926 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7073 10:05:14.096011 ==
7074 10:05:14.099473 Dram Type= 6, Freq= 0, CH_1, rank 1
7075 10:05:14.102305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7076 10:05:14.102405 ==
7077 10:05:14.102516 DQS Delay:
7078 10:05:14.105510 DQS0 = 48, DQS1 = 56
7079 10:05:14.105598 DQM Delay:
7080 10:05:14.108804 DQM0 = 13, DQM1 = 11
7081 10:05:14.108881 DQ Delay:
7082 10:05:14.112451 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
7083 10:05:14.115861 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7084 10:05:14.118926 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7085 10:05:14.122307 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7086 10:05:14.122390
7087 10:05:14.122455
7088 10:05:14.128509 [DQSOSCAuto] RK1, (LSB)MR18= 0x6957, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7089 10:05:14.132415 CH1 RK1: MR19=C0C, MR18=6957
7090 10:05:14.138912 CH1_RK1: MR19=0xC0C, MR18=0x6957, DQSOSC=396, MR23=63, INC=376, DEC=251
7091 10:05:14.141938 [RxdqsGatingPostProcess] freq 400
7092 10:05:14.148756 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7093 10:05:14.151873 best DQS0 dly(2T, 0.5T) = (0, 10)
7094 10:05:14.151970 best DQS1 dly(2T, 0.5T) = (0, 10)
7095 10:05:14.155054 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7096 10:05:14.158666 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7097 10:05:14.161903 best DQS0 dly(2T, 0.5T) = (0, 10)
7098 10:05:14.165211 best DQS1 dly(2T, 0.5T) = (0, 10)
7099 10:05:14.168578 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7100 10:05:14.171826 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7101 10:05:14.175249 Pre-setting of DQS Precalculation
7102 10:05:14.181376 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7103 10:05:14.188119 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7104 10:05:14.194716 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7105 10:05:14.194799
7106 10:05:14.194863
7107 10:05:14.197979 [Calibration Summary] 800 Mbps
7108 10:05:14.198063 CH 0, Rank 0
7109 10:05:14.201327 SW Impedance : PASS
7110 10:05:14.204804 DUTY Scan : NO K
7111 10:05:14.204887 ZQ Calibration : PASS
7112 10:05:14.208127 Jitter Meter : NO K
7113 10:05:14.211347 CBT Training : PASS
7114 10:05:14.211466 Write leveling : PASS
7115 10:05:14.214661 RX DQS gating : PASS
7116 10:05:14.218274 RX DQ/DQS(RDDQC) : PASS
7117 10:05:14.218357 TX DQ/DQS : PASS
7118 10:05:14.221286 RX DATLAT : PASS
7119 10:05:14.224762 RX DQ/DQS(Engine): PASS
7120 10:05:14.224846 TX OE : NO K
7121 10:05:14.228059 All Pass.
7122 10:05:14.228196
7123 10:05:14.228299 CH 0, Rank 1
7124 10:05:14.230987 SW Impedance : PASS
7125 10:05:14.231071 DUTY Scan : NO K
7126 10:05:14.234500 ZQ Calibration : PASS
7127 10:05:14.238003 Jitter Meter : NO K
7128 10:05:14.238088 CBT Training : PASS
7129 10:05:14.241054 Write leveling : NO K
7130 10:05:14.244672 RX DQS gating : PASS
7131 10:05:14.244757 RX DQ/DQS(RDDQC) : PASS
7132 10:05:14.247908 TX DQ/DQS : PASS
7133 10:05:14.248018 RX DATLAT : PASS
7134 10:05:14.250949 RX DQ/DQS(Engine): PASS
7135 10:05:14.254220 TX OE : NO K
7136 10:05:14.254336 All Pass.
7137 10:05:14.254403
7138 10:05:14.254463 CH 1, Rank 0
7139 10:05:14.257972 SW Impedance : PASS
7140 10:05:14.260867 DUTY Scan : NO K
7141 10:05:14.260994 ZQ Calibration : PASS
7142 10:05:14.264166 Jitter Meter : NO K
7143 10:05:14.267346 CBT Training : PASS
7144 10:05:14.267469 Write leveling : PASS
7145 10:05:14.270745 RX DQS gating : PASS
7146 10:05:14.274284 RX DQ/DQS(RDDQC) : PASS
7147 10:05:14.274370 TX DQ/DQS : PASS
7148 10:05:14.277270 RX DATLAT : PASS
7149 10:05:14.280627 RX DQ/DQS(Engine): PASS
7150 10:05:14.280712 TX OE : NO K
7151 10:05:14.284058 All Pass.
7152 10:05:14.284157
7153 10:05:14.284224 CH 1, Rank 1
7154 10:05:14.287547 SW Impedance : PASS
7155 10:05:14.287632 DUTY Scan : NO K
7156 10:05:14.290886 ZQ Calibration : PASS
7157 10:05:14.293716 Jitter Meter : NO K
7158 10:05:14.293801 CBT Training : PASS
7159 10:05:14.297421 Write leveling : NO K
7160 10:05:14.300247 RX DQS gating : PASS
7161 10:05:14.300330 RX DQ/DQS(RDDQC) : PASS
7162 10:05:14.303592 TX DQ/DQS : PASS
7163 10:05:14.307154 RX DATLAT : PASS
7164 10:05:14.307228 RX DQ/DQS(Engine): PASS
7165 10:05:14.310529 TX OE : NO K
7166 10:05:14.310641 All Pass.
7167 10:05:14.310722
7168 10:05:14.313476 DramC Write-DBI off
7169 10:05:14.317036 PER_BANK_REFRESH: Hybrid Mode
7170 10:05:14.317109 TX_TRACKING: ON
7171 10:05:14.326630 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7172 10:05:14.330382 [FAST_K] Save calibration result to emmc
7173 10:05:14.333340 dramc_set_vcore_voltage set vcore to 725000
7174 10:05:14.336845 Read voltage for 1600, 0
7175 10:05:14.336928 Vio18 = 0
7176 10:05:14.336994 Vcore = 725000
7177 10:05:14.339810 Vdram = 0
7178 10:05:14.339900 Vddq = 0
7179 10:05:14.339977 Vmddr = 0
7180 10:05:14.346445 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7181 10:05:14.350228 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7182 10:05:14.353320 MEM_TYPE=3, freq_sel=13
7183 10:05:14.356738 sv_algorithm_assistance_LP4_3733
7184 10:05:14.359588 ============ PULL DRAM RESETB DOWN ============
7185 10:05:14.362957 ========== PULL DRAM RESETB DOWN end =========
7186 10:05:14.369823 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7187 10:05:14.373260 ===================================
7188 10:05:14.376678 LPDDR4 DRAM CONFIGURATION
7189 10:05:14.379934 ===================================
7190 10:05:14.380064 EX_ROW_EN[0] = 0x0
7191 10:05:14.383582 EX_ROW_EN[1] = 0x0
7192 10:05:14.383664 LP4Y_EN = 0x0
7193 10:05:14.385845 WORK_FSP = 0x1
7194 10:05:14.385927 WL = 0x5
7195 10:05:14.389317 RL = 0x5
7196 10:05:14.389398 BL = 0x2
7197 10:05:14.392630 RPST = 0x0
7198 10:05:14.392714 RD_PRE = 0x0
7199 10:05:14.396122 WR_PRE = 0x1
7200 10:05:14.396233 WR_PST = 0x1
7201 10:05:14.398910 DBI_WR = 0x0
7202 10:05:14.402268 DBI_RD = 0x0
7203 10:05:14.402350 OTF = 0x1
7204 10:05:14.405527 ===================================
7205 10:05:14.408864 ===================================
7206 10:05:14.408971 ANA top config
7207 10:05:14.412238 ===================================
7208 10:05:14.415607 DLL_ASYNC_EN = 0
7209 10:05:14.419001 ALL_SLAVE_EN = 0
7210 10:05:14.421958 NEW_RANK_MODE = 1
7211 10:05:14.425522 DLL_IDLE_MODE = 1
7212 10:05:14.425613 LP45_APHY_COMB_EN = 1
7213 10:05:14.428831 TX_ODT_DIS = 0
7214 10:05:14.431997 NEW_8X_MODE = 1
7215 10:05:14.435359 ===================================
7216 10:05:14.438764 ===================================
7217 10:05:14.441677 data_rate = 3200
7218 10:05:14.445874 CKR = 1
7219 10:05:14.448766 DQ_P2S_RATIO = 8
7220 10:05:14.451687 ===================================
7221 10:05:14.451798 CA_P2S_RATIO = 8
7222 10:05:14.455349 DQ_CA_OPEN = 0
7223 10:05:14.457951 DQ_SEMI_OPEN = 0
7224 10:05:14.461366 CA_SEMI_OPEN = 0
7225 10:05:14.464919 CA_FULL_RATE = 0
7226 10:05:14.468205 DQ_CKDIV4_EN = 0
7227 10:05:14.468303 CA_CKDIV4_EN = 0
7228 10:05:14.471542 CA_PREDIV_EN = 0
7229 10:05:14.474858 PH8_DLY = 12
7230 10:05:14.478162 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7231 10:05:14.481287 DQ_AAMCK_DIV = 4
7232 10:05:14.485329 CA_AAMCK_DIV = 4
7233 10:05:14.485411 CA_ADMCK_DIV = 4
7234 10:05:14.488023 DQ_TRACK_CA_EN = 0
7235 10:05:14.491474 CA_PICK = 1600
7236 10:05:14.494743 CA_MCKIO = 1600
7237 10:05:14.498096 MCKIO_SEMI = 0
7238 10:05:14.501397 PLL_FREQ = 3068
7239 10:05:14.504392 DQ_UI_PI_RATIO = 32
7240 10:05:14.507787 CA_UI_PI_RATIO = 0
7241 10:05:14.511265 ===================================
7242 10:05:14.514498 ===================================
7243 10:05:14.514582 memory_type:LPDDR4
7244 10:05:14.517366 GP_NUM : 10
7245 10:05:14.520672 SRAM_EN : 1
7246 10:05:14.520749 MD32_EN : 0
7247 10:05:14.524200 ===================================
7248 10:05:14.527347 [ANA_INIT] >>>>>>>>>>>>>>
7249 10:05:14.530869 <<<<<< [CONFIGURE PHASE]: ANA_TX
7250 10:05:14.534435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7251 10:05:14.537417 ===================================
7252 10:05:14.540891 data_rate = 3200,PCW = 0X7600
7253 10:05:14.544037 ===================================
7254 10:05:14.547090 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7255 10:05:14.550787 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7256 10:05:14.557364 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7257 10:05:14.560966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7258 10:05:14.563987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7259 10:05:14.567529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7260 10:05:14.570600 [ANA_INIT] flow start
7261 10:05:14.573483 [ANA_INIT] PLL >>>>>>>>
7262 10:05:14.573587 [ANA_INIT] PLL <<<<<<<<
7263 10:05:14.577404 [ANA_INIT] MIDPI >>>>>>>>
7264 10:05:14.580143 [ANA_INIT] MIDPI <<<<<<<<
7265 10:05:14.583583 [ANA_INIT] DLL >>>>>>>>
7266 10:05:14.583668 [ANA_INIT] DLL <<<<<<<<
7267 10:05:14.586706 [ANA_INIT] flow end
7268 10:05:14.590120 ============ LP4 DIFF to SE enter ============
7269 10:05:14.593060 ============ LP4 DIFF to SE exit ============
7270 10:05:14.596423 [ANA_INIT] <<<<<<<<<<<<<
7271 10:05:14.599950 [Flow] Enable top DCM control >>>>>
7272 10:05:14.603204 [Flow] Enable top DCM control <<<<<
7273 10:05:14.606916 Enable DLL master slave shuffle
7274 10:05:14.613106 ==============================================================
7275 10:05:14.613191 Gating Mode config
7276 10:05:14.619563 ==============================================================
7277 10:05:14.619652 Config description:
7278 10:05:14.629548 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7279 10:05:14.636416 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7280 10:05:14.643004 SELPH_MODE 0: By rank 1: By Phase
7281 10:05:14.649008 ==============================================================
7282 10:05:14.652428 GAT_TRACK_EN = 1
7283 10:05:14.652575 RX_GATING_MODE = 2
7284 10:05:14.655578 RX_GATING_TRACK_MODE = 2
7285 10:05:14.659024 SELPH_MODE = 1
7286 10:05:14.662735 PICG_EARLY_EN = 1
7287 10:05:14.665562 VALID_LAT_VALUE = 1
7288 10:05:14.672235 ==============================================================
7289 10:05:14.675947 Enter into Gating configuration >>>>
7290 10:05:14.679031 Exit from Gating configuration <<<<
7291 10:05:14.681947 Enter into DVFS_PRE_config >>>>>
7292 10:05:14.691863 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7293 10:05:14.695293 Exit from DVFS_PRE_config <<<<<
7294 10:05:14.698753 Enter into PICG configuration >>>>
7295 10:05:14.701774 Exit from PICG configuration <<<<
7296 10:05:14.705578 [RX_INPUT] configuration >>>>>
7297 10:05:14.708395 [RX_INPUT] configuration <<<<<
7298 10:05:14.712065 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7299 10:05:14.718423 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7300 10:05:14.725008 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7301 10:05:14.731784 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7302 10:05:14.734715 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7303 10:05:14.741462 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7304 10:05:14.745006 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7305 10:05:14.751416 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7306 10:05:14.754740 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7307 10:05:14.758150 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7308 10:05:14.761618 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7309 10:05:14.767837 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7310 10:05:14.771210 ===================================
7311 10:05:14.774683 LPDDR4 DRAM CONFIGURATION
7312 10:05:14.778073 ===================================
7313 10:05:14.778148 EX_ROW_EN[0] = 0x0
7314 10:05:14.780977 EX_ROW_EN[1] = 0x0
7315 10:05:14.781061 LP4Y_EN = 0x0
7316 10:05:14.784623 WORK_FSP = 0x1
7317 10:05:14.784706 WL = 0x5
7318 10:05:14.787770 RL = 0x5
7319 10:05:14.787853 BL = 0x2
7320 10:05:14.791236 RPST = 0x0
7321 10:05:14.791320 RD_PRE = 0x0
7322 10:05:14.794142 WR_PRE = 0x1
7323 10:05:14.794226 WR_PST = 0x1
7324 10:05:14.797565 DBI_WR = 0x0
7325 10:05:14.800863 DBI_RD = 0x0
7326 10:05:14.800948 OTF = 0x1
7327 10:05:14.804619 ===================================
7328 10:05:14.807741 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7329 10:05:14.810920 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7330 10:05:14.817317 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7331 10:05:14.820587 ===================================
7332 10:05:14.823768 LPDDR4 DRAM CONFIGURATION
7333 10:05:14.827598 ===================================
7334 10:05:14.827685 EX_ROW_EN[0] = 0x10
7335 10:05:14.830817 EX_ROW_EN[1] = 0x0
7336 10:05:14.830903 LP4Y_EN = 0x0
7337 10:05:14.833768 WORK_FSP = 0x1
7338 10:05:14.833852 WL = 0x5
7339 10:05:14.837089 RL = 0x5
7340 10:05:14.837174 BL = 0x2
7341 10:05:14.840624 RPST = 0x0
7342 10:05:14.840707 RD_PRE = 0x0
7343 10:05:14.843888 WR_PRE = 0x1
7344 10:05:14.847118 WR_PST = 0x1
7345 10:05:14.847204 DBI_WR = 0x0
7346 10:05:14.850468 DBI_RD = 0x0
7347 10:05:14.850566 OTF = 0x1
7348 10:05:14.853930 ===================================
7349 10:05:14.860043 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7350 10:05:14.860142 ==
7351 10:05:14.863241 Dram Type= 6, Freq= 0, CH_0, rank 0
7352 10:05:14.866915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7353 10:05:14.867003 ==
7354 10:05:14.870320 [Duty_Offset_Calibration]
7355 10:05:14.873719 B0:1 B1:-1 CA:0
7356 10:05:14.873802
7357 10:05:14.876511 [DutyScan_Calibration_Flow] k_type=0
7358 10:05:14.885018
7359 10:05:14.885101 ==CLK 0==
7360 10:05:14.888512 Final CLK duty delay cell = 0
7361 10:05:14.891948 [0] MAX Duty = 5124%(X100), DQS PI = 22
7362 10:05:14.894773 [0] MIN Duty = 4907%(X100), DQS PI = 6
7363 10:05:14.894852 [0] AVG Duty = 5015%(X100)
7364 10:05:14.898090
7365 10:05:14.901398 CH0 CLK Duty spec in!! Max-Min= 217%
7366 10:05:14.904827 [DutyScan_Calibration_Flow] ====Done====
7367 10:05:14.904904
7368 10:05:14.907730 [DutyScan_Calibration_Flow] k_type=1
7369 10:05:14.924364
7370 10:05:14.924484 ==DQS 0 ==
7371 10:05:14.927171 Final DQS duty delay cell = -4
7372 10:05:14.930867 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7373 10:05:14.934211 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7374 10:05:14.937180 [-4] AVG Duty = 4906%(X100)
7375 10:05:14.937254
7376 10:05:14.937347 ==DQS 1 ==
7377 10:05:14.940487 Final DQS duty delay cell = 0
7378 10:05:14.943965 [0] MAX Duty = 5156%(X100), DQS PI = 0
7379 10:05:14.947430 [0] MIN Duty = 5031%(X100), DQS PI = 20
7380 10:05:14.950813 [0] AVG Duty = 5093%(X100)
7381 10:05:14.950888
7382 10:05:14.953894 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7383 10:05:14.953963
7384 10:05:14.957198 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7385 10:05:14.960235 [DutyScan_Calibration_Flow] ====Done====
7386 10:05:14.960328
7387 10:05:14.963570 [DutyScan_Calibration_Flow] k_type=3
7388 10:05:14.981506
7389 10:05:14.981590 ==DQM 0 ==
7390 10:05:14.984775 Final DQM duty delay cell = 0
7391 10:05:14.988344 [0] MAX Duty = 5124%(X100), DQS PI = 20
7392 10:05:14.991305 [0] MIN Duty = 4907%(X100), DQS PI = 10
7393 10:05:14.994597 [0] AVG Duty = 5015%(X100)
7394 10:05:14.994706
7395 10:05:14.994798 ==DQM 1 ==
7396 10:05:14.997838 Final DQM duty delay cell = 0
7397 10:05:15.001471 [0] MAX Duty = 5031%(X100), DQS PI = 12
7398 10:05:15.004680 [0] MIN Duty = 4782%(X100), DQS PI = 20
7399 10:05:15.008025 [0] AVG Duty = 4906%(X100)
7400 10:05:15.008147
7401 10:05:15.011466 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7402 10:05:15.011559
7403 10:05:15.014369 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7404 10:05:15.017647 [DutyScan_Calibration_Flow] ====Done====
7405 10:05:15.017755
7406 10:05:15.020999 [DutyScan_Calibration_Flow] k_type=2
7407 10:05:15.038025
7408 10:05:15.038177 ==DQ 0 ==
7409 10:05:15.041406 Final DQ duty delay cell = -4
7410 10:05:15.044659 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7411 10:05:15.048242 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7412 10:05:15.051416 [-4] AVG Duty = 4953%(X100)
7413 10:05:15.051526
7414 10:05:15.051620 ==DQ 1 ==
7415 10:05:15.054749 Final DQ duty delay cell = 0
7416 10:05:15.057595 [0] MAX Duty = 5125%(X100), DQS PI = 2
7417 10:05:15.061414 [0] MIN Duty = 5000%(X100), DQS PI = 34
7418 10:05:15.064320 [0] AVG Duty = 5062%(X100)
7419 10:05:15.064426
7420 10:05:15.067700 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7421 10:05:15.067790
7422 10:05:15.071212 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7423 10:05:15.074617 [DutyScan_Calibration_Flow] ====Done====
7424 10:05:15.074699 ==
7425 10:05:15.077851 Dram Type= 6, Freq= 0, CH_1, rank 0
7426 10:05:15.081066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7427 10:05:15.081152 ==
7428 10:05:15.083880 [Duty_Offset_Calibration]
7429 10:05:15.083989 B0:-1 B1:1 CA:2
7430 10:05:15.084127
7431 10:05:15.087809 [DutyScan_Calibration_Flow] k_type=0
7432 10:05:15.098726
7433 10:05:15.098933 ==CLK 0==
7434 10:05:15.101953 Final CLK duty delay cell = 0
7435 10:05:15.105534 [0] MAX Duty = 5187%(X100), DQS PI = 24
7436 10:05:15.108830 [0] MIN Duty = 4969%(X100), DQS PI = 2
7437 10:05:15.111633 [0] AVG Duty = 5078%(X100)
7438 10:05:15.111770
7439 10:05:15.115084 CH1 CLK Duty spec in!! Max-Min= 218%
7440 10:05:15.118308 [DutyScan_Calibration_Flow] ====Done====
7441 10:05:15.118431
7442 10:05:15.121258 [DutyScan_Calibration_Flow] k_type=1
7443 10:05:15.138097
7444 10:05:15.138339 ==DQS 0 ==
7445 10:05:15.141860 Final DQS duty delay cell = 0
7446 10:05:15.145149 [0] MAX Duty = 5124%(X100), DQS PI = 16
7447 10:05:15.148405 [0] MIN Duty = 4907%(X100), DQS PI = 10
7448 10:05:15.151898 [0] AVG Duty = 5015%(X100)
7449 10:05:15.152318
7450 10:05:15.152763 ==DQS 1 ==
7451 10:05:15.155496 Final DQS duty delay cell = 0
7452 10:05:15.158669 [0] MAX Duty = 5093%(X100), DQS PI = 26
7453 10:05:15.161908 [0] MIN Duty = 4969%(X100), DQS PI = 54
7454 10:05:15.165067 [0] AVG Duty = 5031%(X100)
7455 10:05:15.165639
7456 10:05:15.168275 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7457 10:05:15.168854
7458 10:05:15.171631 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7459 10:05:15.175084 [DutyScan_Calibration_Flow] ====Done====
7460 10:05:15.175623
7461 10:05:15.177848 [DutyScan_Calibration_Flow] k_type=3
7462 10:05:15.194663
7463 10:05:15.195200 ==DQM 0 ==
7464 10:05:15.197968 Final DQM duty delay cell = -4
7465 10:05:15.201270 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7466 10:05:15.204782 [-4] MIN Duty = 4782%(X100), DQS PI = 10
7467 10:05:15.207997 [-4] AVG Duty = 4922%(X100)
7468 10:05:15.208393
7469 10:05:15.208987 ==DQM 1 ==
7470 10:05:15.210997 Final DQM duty delay cell = 0
7471 10:05:15.214311 [0] MAX Duty = 5156%(X100), DQS PI = 0
7472 10:05:15.217576 [0] MIN Duty = 4969%(X100), DQS PI = 28
7473 10:05:15.221132 [0] AVG Duty = 5062%(X100)
7474 10:05:15.221576
7475 10:05:15.224406 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7476 10:05:15.224934
7477 10:05:15.227572 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7478 10:05:15.231034 [DutyScan_Calibration_Flow] ====Done====
7479 10:05:15.231445
7480 10:05:15.234122 [DutyScan_Calibration_Flow] k_type=2
7481 10:05:15.251790
7482 10:05:15.252343 ==DQ 0 ==
7483 10:05:15.255279 Final DQ duty delay cell = 0
7484 10:05:15.258614 [0] MAX Duty = 5156%(X100), DQS PI = 30
7485 10:05:15.262146 [0] MIN Duty = 4906%(X100), DQS PI = 10
7486 10:05:15.265001 [0] AVG Duty = 5031%(X100)
7487 10:05:15.265442
7488 10:05:15.265783 ==DQ 1 ==
7489 10:05:15.268507 Final DQ duty delay cell = 0
7490 10:05:15.271625 [0] MAX Duty = 5156%(X100), DQS PI = 8
7491 10:05:15.275063 [0] MIN Duty = 4969%(X100), DQS PI = 56
7492 10:05:15.275149 [0] AVG Duty = 5062%(X100)
7493 10:05:15.279087
7494 10:05:15.281141 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7495 10:05:15.281232
7496 10:05:15.284525 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7497 10:05:15.287860 [DutyScan_Calibration_Flow] ====Done====
7498 10:05:15.291240 nWR fixed to 30
7499 10:05:15.291375 [ModeRegInit_LP4] CH0 RK0
7500 10:05:15.294601 [ModeRegInit_LP4] CH0 RK1
7501 10:05:15.298241 [ModeRegInit_LP4] CH1 RK0
7502 10:05:15.300996 [ModeRegInit_LP4] CH1 RK1
7503 10:05:15.301098 match AC timing 5
7504 10:05:15.307402 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7505 10:05:15.311107 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7506 10:05:15.314523 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7507 10:05:15.321334 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7508 10:05:15.324372 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7509 10:05:15.324456 [MiockJmeterHQA]
7510 10:05:15.324546
7511 10:05:15.327287 [DramcMiockJmeter] u1RxGatingPI = 0
7512 10:05:15.331001 0 : 4368, 4140
7513 10:05:15.331116 4 : 4252, 4027
7514 10:05:15.334290 8 : 4252, 4027
7515 10:05:15.334405 12 : 4253, 4026
7516 10:05:15.337572 16 : 4255, 4029
7517 10:05:15.337683 20 : 4252, 4027
7518 10:05:15.337782 24 : 4252, 4027
7519 10:05:15.340262 28 : 4365, 4140
7520 10:05:15.340377 32 : 4252, 4027
7521 10:05:15.343780 36 : 4255, 4029
7522 10:05:15.343878 40 : 4253, 4027
7523 10:05:15.347322 44 : 4363, 4137
7524 10:05:15.347429 48 : 4253, 4027
7525 10:05:15.350741 52 : 4363, 4138
7526 10:05:15.350919 56 : 4250, 4027
7527 10:05:15.350989 60 : 4250, 4027
7528 10:05:15.354095 64 : 4250, 4027
7529 10:05:15.354206 68 : 4252, 4030
7530 10:05:15.356858 72 : 4250, 4027
7531 10:05:15.356942 76 : 4250, 4027
7532 10:05:15.360080 80 : 4363, 4140
7533 10:05:15.360164 84 : 4250, 4026
7534 10:05:15.363563 88 : 4252, 4028
7535 10:05:15.363647 92 : 4250, 723
7536 10:05:15.363714 96 : 4249, 0
7537 10:05:15.366921 100 : 4255, 0
7538 10:05:15.367005 104 : 4250, 0
7539 10:05:15.369942 108 : 4252, 0
7540 10:05:15.370029 112 : 4250, 0
7541 10:05:15.370098 116 : 4361, 0
7542 10:05:15.373663 120 : 4360, 0
7543 10:05:15.373749 124 : 4247, 0
7544 10:05:15.373818 128 : 4363, 0
7545 10:05:15.377091 132 : 4360, 0
7546 10:05:15.377186 136 : 4361, 0
7547 10:05:15.380402 140 : 4250, 0
7548 10:05:15.380483 144 : 4253, 0
7549 10:05:15.380576 148 : 4252, 0
7550 10:05:15.383333 152 : 4363, 0
7551 10:05:15.383414 156 : 4253, 0
7552 10:05:15.386932 160 : 4250, 0
7553 10:05:15.387011 164 : 4252, 0
7554 10:05:15.387094 168 : 4253, 0
7555 10:05:15.390383 172 : 4250, 0
7556 10:05:15.390461 176 : 4252, 0
7557 10:05:15.393299 180 : 4365, 0
7558 10:05:15.393386 184 : 4360, 0
7559 10:05:15.393459 188 : 4363, 0
7560 10:05:15.396370 192 : 4252, 0
7561 10:05:15.396456 196 : 4250, 0
7562 10:05:15.400379 200 : 4252, 0
7563 10:05:15.400466 204 : 4252, 0
7564 10:05:15.400543 208 : 4250, 0
7565 10:05:15.403373 212 : 4250, 0
7566 10:05:15.403468 216 : 4252, 0
7567 10:05:15.403553 220 : 4253, 0
7568 10:05:15.406640 224 : 4250, 247
7569 10:05:15.406726 228 : 4250, 3602
7570 10:05:15.409807 232 : 4360, 4138
7571 10:05:15.409894 236 : 4250, 4027
7572 10:05:15.413726 240 : 4250, 4027
7573 10:05:15.413817 244 : 4360, 4137
7574 10:05:15.416467 248 : 4361, 4138
7575 10:05:15.416577 252 : 4250, 4027
7576 10:05:15.419900 256 : 4363, 4140
7577 10:05:15.419986 260 : 4250, 4027
7578 10:05:15.423162 264 : 4250, 4026
7579 10:05:15.423252 268 : 4250, 4027
7580 10:05:15.426506 272 : 4252, 4029
7581 10:05:15.426596 276 : 4250, 4027
7582 10:05:15.426667 280 : 4250, 4027
7583 10:05:15.429859 284 : 4250, 4027
7584 10:05:15.429972 288 : 4252, 4029
7585 10:05:15.433417 292 : 4250, 4027
7586 10:05:15.433529 296 : 4361, 4137
7587 10:05:15.436332 300 : 4361, 4137
7588 10:05:15.436438 304 : 4250, 4027
7589 10:05:15.439931 308 : 4363, 4140
7590 10:05:15.440046 312 : 4250, 4027
7591 10:05:15.443352 316 : 4250, 4027
7592 10:05:15.443465 320 : 4250, 4027
7593 10:05:15.446421 324 : 4252, 4029
7594 10:05:15.446508 328 : 4250, 4027
7595 10:05:15.449607 332 : 4250, 4027
7596 10:05:15.449717 336 : 4250, 3811
7597 10:05:15.453000 340 : 4252, 2234
7598 10:05:15.453087 344 : 4250, 167
7599 10:05:15.453155
7600 10:05:15.455956 MIOCK jitter meter ch=0
7601 10:05:15.456041
7602 10:05:15.459701 1T = (344-92) = 252 dly cells
7603 10:05:15.462813 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7604 10:05:15.462898 ==
7605 10:05:15.466364 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 10:05:15.472664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 10:05:15.472748 ==
7608 10:05:15.475743 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7609 10:05:15.482542 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7610 10:05:15.485972 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7611 10:05:15.492692 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7612 10:05:15.500224 [CA 0] Center 43 (12~74) winsize 63
7613 10:05:15.503796 [CA 1] Center 42 (12~73) winsize 62
7614 10:05:15.506761 [CA 2] Center 38 (9~68) winsize 60
7615 10:05:15.509983 [CA 3] Center 38 (8~68) winsize 61
7616 10:05:15.513234 [CA 4] Center 36 (7~66) winsize 60
7617 10:05:15.516413 [CA 5] Center 35 (6~65) winsize 60
7618 10:05:15.516495
7619 10:05:15.520253 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7620 10:05:15.520374
7621 10:05:15.523172 [CATrainingPosCal] consider 1 rank data
7622 10:05:15.526350 u2DelayCellTimex100 = 258/100 ps
7623 10:05:15.533900 CA0 delay=43 (12~74),Diff = 8 PI (30 cell)
7624 10:05:15.536789 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7625 10:05:15.539935 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7626 10:05:15.543268 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7627 10:05:15.546493 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7628 10:05:15.549648 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7629 10:05:15.549731
7630 10:05:15.553129 CA PerBit enable=1, Macro0, CA PI delay=35
7631 10:05:15.553212
7632 10:05:15.556434 [CBTSetCACLKResult] CA Dly = 35
7633 10:05:15.559727 CS Dly: 12 (0~43)
7634 10:05:15.563108 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7635 10:05:15.565876 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7636 10:05:15.565960 ==
7637 10:05:15.569304 Dram Type= 6, Freq= 0, CH_0, rank 1
7638 10:05:15.575793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 10:05:15.575875 ==
7640 10:05:15.579446 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7641 10:05:15.586022 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7642 10:05:15.589362 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7643 10:05:15.595633 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7644 10:05:15.603859 [CA 0] Center 43 (13~74) winsize 62
7645 10:05:15.606989 [CA 1] Center 44 (14~74) winsize 61
7646 10:05:15.610635 [CA 2] Center 38 (9~68) winsize 60
7647 10:05:15.613429 [CA 3] Center 38 (9~68) winsize 60
7648 10:05:15.616912 [CA 4] Center 36 (7~66) winsize 60
7649 10:05:15.620267 [CA 5] Center 36 (6~66) winsize 61
7650 10:05:15.620377
7651 10:05:15.623301 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7652 10:05:15.623408
7653 10:05:15.630013 [CATrainingPosCal] consider 2 rank data
7654 10:05:15.630132 u2DelayCellTimex100 = 258/100 ps
7655 10:05:15.636442 CA0 delay=43 (13~74),Diff = 8 PI (30 cell)
7656 10:05:15.639822 CA1 delay=43 (14~73),Diff = 8 PI (30 cell)
7657 10:05:15.643279 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7658 10:05:15.646650 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7659 10:05:15.649737 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7660 10:05:15.653298 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7661 10:05:15.653404
7662 10:05:15.656198 CA PerBit enable=1, Macro0, CA PI delay=35
7663 10:05:15.656352
7664 10:05:15.660439 [CBTSetCACLKResult] CA Dly = 35
7665 10:05:15.663722 CS Dly: 12 (0~44)
7666 10:05:15.666771 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7667 10:05:15.670129 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7668 10:05:15.670615
7669 10:05:15.673717 ----->DramcWriteLeveling(PI) begin...
7670 10:05:15.674153 ==
7671 10:05:15.677015 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 10:05:15.683806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 10:05:15.684240 ==
7674 10:05:15.686345 Write leveling (Byte 0): 34 => 34
7675 10:05:15.689787 Write leveling (Byte 1): 26 => 26
7676 10:05:15.690488 DramcWriteLeveling(PI) end<-----
7677 10:05:15.693023
7678 10:05:15.693547 ==
7679 10:05:15.696858 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 10:05:15.700079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 10:05:15.700672 ==
7682 10:05:15.702846 [Gating] SW mode calibration
7683 10:05:15.709538 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7684 10:05:15.716174 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7685 10:05:15.719379 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7686 10:05:15.723180 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7687 10:05:15.728906 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7688 10:05:15.732226 1 4 12 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
7689 10:05:15.735297 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7690 10:05:15.742010 1 4 20 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
7691 10:05:15.745451 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7692 10:05:15.748465 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7693 10:05:15.755024 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7694 10:05:15.758394 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7695 10:05:15.761869 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7696 10:05:15.768448 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7697 10:05:15.771835 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7698 10:05:15.775061 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7699 10:05:15.782006 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
7700 10:05:15.784708 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7701 10:05:15.788276 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7702 10:05:15.794876 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7703 10:05:15.797972 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7704 10:05:15.801487 1 6 12 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (1 1)
7705 10:05:15.807901 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7706 10:05:15.811203 1 6 20 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7707 10:05:15.814364 1 6 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7708 10:05:15.821316 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7709 10:05:15.824485 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7710 10:05:15.827694 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7711 10:05:15.834402 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7712 10:05:15.837569 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7713 10:05:15.840986 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7714 10:05:15.847636 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7715 10:05:15.850902 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7716 10:05:15.854235 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7717 10:05:15.860850 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7718 10:05:15.864054 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7719 10:05:15.866900 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7720 10:05:15.873350 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7721 10:05:15.876870 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7722 10:05:15.880077 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7723 10:05:15.886649 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7724 10:05:15.889871 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7725 10:05:15.893095 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7726 10:05:15.899912 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7727 10:05:15.903359 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7728 10:05:15.906446 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7729 10:05:15.912965 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7730 10:05:15.916358 Total UI for P1: 0, mck2ui 16
7731 10:05:15.919585 best dqsien dly found for B0: ( 1, 9, 12)
7732 10:05:15.922826 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7733 10:05:15.926340 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7734 10:05:15.930102 Total UI for P1: 0, mck2ui 16
7735 10:05:15.933126 best dqsien dly found for B1: ( 1, 9, 18)
7736 10:05:15.936533 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7737 10:05:15.939444 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7738 10:05:15.939539
7739 10:05:15.946043 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7740 10:05:15.949524 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7741 10:05:15.952381 [Gating] SW calibration Done
7742 10:05:15.952505 ==
7743 10:05:15.955730 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 10:05:15.959332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 10:05:15.959426 ==
7746 10:05:15.959496 RX Vref Scan: 0
7747 10:05:15.959559
7748 10:05:15.962538 RX Vref 0 -> 0, step: 1
7749 10:05:15.962612
7750 10:05:15.965721 RX Delay 0 -> 252, step: 8
7751 10:05:15.969403 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7752 10:05:15.972408 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7753 10:05:15.979047 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7754 10:05:15.982549 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7755 10:05:15.985668 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7756 10:05:15.989184 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7757 10:05:15.992508 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7758 10:05:15.998623 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7759 10:05:16.002542 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7760 10:05:16.005323 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7761 10:05:16.009203 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7762 10:05:16.012451 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7763 10:05:16.018760 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7764 10:05:16.022197 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7765 10:05:16.025490 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7766 10:05:16.028792 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7767 10:05:16.028888 ==
7768 10:05:16.032062 Dram Type= 6, Freq= 0, CH_0, rank 0
7769 10:05:16.038374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7770 10:05:16.038533 ==
7771 10:05:16.038640 DQS Delay:
7772 10:05:16.042310 DQS0 = 0, DQS1 = 0
7773 10:05:16.042450 DQM Delay:
7774 10:05:16.042559 DQM0 = 135, DQM1 = 126
7775 10:05:16.045447 DQ Delay:
7776 10:05:16.048305 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7777 10:05:16.052407 DQ4 =135, DQ5 =123, DQ6 =143, DQ7 =147
7778 10:05:16.055065 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7779 10:05:16.058383 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7780 10:05:16.058503
7781 10:05:16.058599
7782 10:05:16.058690 ==
7783 10:05:16.061874 Dram Type= 6, Freq= 0, CH_0, rank 0
7784 10:05:16.068146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7785 10:05:16.068258 ==
7786 10:05:16.068329
7787 10:05:16.068392
7788 10:05:16.068452 TX Vref Scan disable
7789 10:05:16.071476 == TX Byte 0 ==
7790 10:05:16.075013 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7791 10:05:16.081694 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7792 10:05:16.081810 == TX Byte 1 ==
7793 10:05:16.085016 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7794 10:05:16.091741 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7795 10:05:16.091834 ==
7796 10:05:16.095124 Dram Type= 6, Freq= 0, CH_0, rank 0
7797 10:05:16.098053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7798 10:05:16.098148 ==
7799 10:05:16.111216
7800 10:05:16.114617 TX Vref early break, caculate TX vref
7801 10:05:16.117795 TX Vref=16, minBit 0, minWin=23, winSum=373
7802 10:05:16.120674 TX Vref=18, minBit 4, minWin=23, winSum=379
7803 10:05:16.124110 TX Vref=20, minBit 3, minWin=23, winSum=387
7804 10:05:16.127241 TX Vref=22, minBit 1, minWin=24, winSum=400
7805 10:05:16.130595 TX Vref=24, minBit 1, minWin=24, winSum=406
7806 10:05:16.137528 TX Vref=26, minBit 0, minWin=25, winSum=416
7807 10:05:16.140886 TX Vref=28, minBit 4, minWin=25, winSum=419
7808 10:05:16.144086 TX Vref=30, minBit 5, minWin=24, winSum=411
7809 10:05:16.147029 TX Vref=32, minBit 1, minWin=24, winSum=400
7810 10:05:16.150950 TX Vref=34, minBit 4, minWin=23, winSum=389
7811 10:05:16.157053 [TxChooseVref] Worse bit 4, Min win 25, Win sum 419, Final Vref 28
7812 10:05:16.157164
7813 10:05:16.160513 Final TX Range 0 Vref 28
7814 10:05:16.160613
7815 10:05:16.160683 ==
7816 10:05:16.164013 Dram Type= 6, Freq= 0, CH_0, rank 0
7817 10:05:16.166860 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7818 10:05:16.166947 ==
7819 10:05:16.167016
7820 10:05:16.167080
7821 10:05:16.170634 TX Vref Scan disable
7822 10:05:16.177070 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7823 10:05:16.177157 == TX Byte 0 ==
7824 10:05:16.180228 u2DelayCellOfst[0]=15 cells (4 PI)
7825 10:05:16.183385 u2DelayCellOfst[1]=18 cells (5 PI)
7826 10:05:16.187257 u2DelayCellOfst[2]=15 cells (4 PI)
7827 10:05:16.189975 u2DelayCellOfst[3]=15 cells (4 PI)
7828 10:05:16.193470 u2DelayCellOfst[4]=11 cells (3 PI)
7829 10:05:16.196630 u2DelayCellOfst[5]=0 cells (0 PI)
7830 10:05:16.200091 u2DelayCellOfst[6]=18 cells (5 PI)
7831 10:05:16.203452 u2DelayCellOfst[7]=22 cells (6 PI)
7832 10:05:16.206615 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7833 10:05:16.209871 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7834 10:05:16.213340 == TX Byte 1 ==
7835 10:05:16.216289 u2DelayCellOfst[8]=0 cells (0 PI)
7836 10:05:16.219446 u2DelayCellOfst[9]=3 cells (1 PI)
7837 10:05:16.222869 u2DelayCellOfst[10]=7 cells (2 PI)
7838 10:05:16.226579 u2DelayCellOfst[11]=3 cells (1 PI)
7839 10:05:16.229316 u2DelayCellOfst[12]=15 cells (4 PI)
7840 10:05:16.232496 u2DelayCellOfst[13]=15 cells (4 PI)
7841 10:05:16.232592 u2DelayCellOfst[14]=15 cells (4 PI)
7842 10:05:16.236144 u2DelayCellOfst[15]=15 cells (4 PI)
7843 10:05:16.243029 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7844 10:05:16.246135 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7845 10:05:16.249466 DramC Write-DBI on
7846 10:05:16.249551 ==
7847 10:05:16.252278 Dram Type= 6, Freq= 0, CH_0, rank 0
7848 10:05:16.255687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7849 10:05:16.255773 ==
7850 10:05:16.255842
7851 10:05:16.255905
7852 10:05:16.259096 TX Vref Scan disable
7853 10:05:16.259204 == TX Byte 0 ==
7854 10:05:16.265789 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7855 10:05:16.265874 == TX Byte 1 ==
7856 10:05:16.269118 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7857 10:05:16.272394 DramC Write-DBI off
7858 10:05:16.272503
7859 10:05:16.272609 [DATLAT]
7860 10:05:16.275706 Freq=1600, CH0 RK0
7861 10:05:16.275812
7862 10:05:16.275905 DATLAT Default: 0xf
7863 10:05:16.278997 0, 0xFFFF, sum = 0
7864 10:05:16.279082 1, 0xFFFF, sum = 0
7865 10:05:16.282819 2, 0xFFFF, sum = 0
7866 10:05:16.285379 3, 0xFFFF, sum = 0
7867 10:05:16.285465 4, 0xFFFF, sum = 0
7868 10:05:16.288728 5, 0xFFFF, sum = 0
7869 10:05:16.288813 6, 0xFFFF, sum = 0
7870 10:05:16.292154 7, 0xFFFF, sum = 0
7871 10:05:16.292261 8, 0xFFFF, sum = 0
7872 10:05:16.295482 9, 0xFFFF, sum = 0
7873 10:05:16.295595 10, 0xFFFF, sum = 0
7874 10:05:16.298837 11, 0xFFFF, sum = 0
7875 10:05:16.298927 12, 0xFFFF, sum = 0
7876 10:05:16.302078 13, 0xFFFF, sum = 0
7877 10:05:16.302162 14, 0x0, sum = 1
7878 10:05:16.304984 15, 0x0, sum = 2
7879 10:05:16.305068 16, 0x0, sum = 3
7880 10:05:16.308198 17, 0x0, sum = 4
7881 10:05:16.308305 best_step = 15
7882 10:05:16.308399
7883 10:05:16.308488 ==
7884 10:05:16.311985 Dram Type= 6, Freq= 0, CH_0, rank 0
7885 10:05:16.318259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7886 10:05:16.318375 ==
7887 10:05:16.318441 RX Vref Scan: 1
7888 10:05:16.318503
7889 10:05:16.321662 Set Vref Range= 24 -> 127
7890 10:05:16.321760
7891 10:05:16.325754 RX Vref 24 -> 127, step: 1
7892 10:05:16.325826
7893 10:05:16.325885 RX Delay 11 -> 252, step: 4
7894 10:05:16.325952
7895 10:05:16.328372 Set Vref, RX VrefLevel [Byte0]: 24
7896 10:05:16.331801 [Byte1]: 24
7897 10:05:16.335850
7898 10:05:16.335927 Set Vref, RX VrefLevel [Byte0]: 25
7899 10:05:16.339156 [Byte1]: 25
7900 10:05:16.343706
7901 10:05:16.343794 Set Vref, RX VrefLevel [Byte0]: 26
7902 10:05:16.347257 [Byte1]: 26
7903 10:05:16.351070
7904 10:05:16.351142 Set Vref, RX VrefLevel [Byte0]: 27
7905 10:05:16.354635 [Byte1]: 27
7906 10:05:16.358396
7907 10:05:16.358483 Set Vref, RX VrefLevel [Byte0]: 28
7908 10:05:16.362290 [Byte1]: 28
7909 10:05:16.366257
7910 10:05:16.369319 Set Vref, RX VrefLevel [Byte0]: 29
7911 10:05:16.372730 [Byte1]: 29
7912 10:05:16.372814
7913 10:05:16.375844 Set Vref, RX VrefLevel [Byte0]: 30
7914 10:05:16.379366 [Byte1]: 30
7915 10:05:16.379449
7916 10:05:16.382623 Set Vref, RX VrefLevel [Byte0]: 31
7917 10:05:16.385907 [Byte1]: 31
7918 10:05:16.388874
7919 10:05:16.388956 Set Vref, RX VrefLevel [Byte0]: 32
7920 10:05:16.392117 [Byte1]: 32
7921 10:05:16.397011
7922 10:05:16.397095 Set Vref, RX VrefLevel [Byte0]: 33
7923 10:05:16.400026 [Byte1]: 33
7924 10:05:16.404053
7925 10:05:16.404136 Set Vref, RX VrefLevel [Byte0]: 34
7926 10:05:16.407348 [Byte1]: 34
7927 10:05:16.411850
7928 10:05:16.411934 Set Vref, RX VrefLevel [Byte0]: 35
7929 10:05:16.415222 [Byte1]: 35
7930 10:05:16.419600
7931 10:05:16.419684 Set Vref, RX VrefLevel [Byte0]: 36
7932 10:05:16.423198 [Byte1]: 36
7933 10:05:16.427653
7934 10:05:16.427736 Set Vref, RX VrefLevel [Byte0]: 37
7935 10:05:16.430389 [Byte1]: 37
7936 10:05:16.434860
7937 10:05:16.434947 Set Vref, RX VrefLevel [Byte0]: 38
7938 10:05:16.437908 [Byte1]: 38
7939 10:05:16.442323
7940 10:05:16.442458 Set Vref, RX VrefLevel [Byte0]: 39
7941 10:05:16.445858 [Byte1]: 39
7942 10:05:16.449785
7943 10:05:16.449882 Set Vref, RX VrefLevel [Byte0]: 40
7944 10:05:16.453059 [Byte1]: 40
7945 10:05:16.457520
7946 10:05:16.457603 Set Vref, RX VrefLevel [Byte0]: 41
7947 10:05:16.461221 [Byte1]: 41
7948 10:05:16.465191
7949 10:05:16.465306 Set Vref, RX VrefLevel [Byte0]: 42
7950 10:05:16.468754 [Byte1]: 42
7951 10:05:16.472538
7952 10:05:16.472636 Set Vref, RX VrefLevel [Byte0]: 43
7953 10:05:16.475924 [Byte1]: 43
7954 10:05:16.480319
7955 10:05:16.480401 Set Vref, RX VrefLevel [Byte0]: 44
7956 10:05:16.483768 [Byte1]: 44
7957 10:05:16.488267
7958 10:05:16.488379 Set Vref, RX VrefLevel [Byte0]: 45
7959 10:05:16.491593 [Byte1]: 45
7960 10:05:16.495540
7961 10:05:16.495638 Set Vref, RX VrefLevel [Byte0]: 46
7962 10:05:16.499291 [Byte1]: 46
7963 10:05:16.503054
7964 10:05:16.503148 Set Vref, RX VrefLevel [Byte0]: 47
7965 10:05:16.506606 [Byte1]: 47
7966 10:05:16.510754
7967 10:05:16.510837 Set Vref, RX VrefLevel [Byte0]: 48
7968 10:05:16.514059 [Byte1]: 48
7969 10:05:16.518538
7970 10:05:16.518647 Set Vref, RX VrefLevel [Byte0]: 49
7971 10:05:16.521946 [Byte1]: 49
7972 10:05:16.526296
7973 10:05:16.526407 Set Vref, RX VrefLevel [Byte0]: 50
7974 10:05:16.529537 [Byte1]: 50
7975 10:05:16.533806
7976 10:05:16.533919 Set Vref, RX VrefLevel [Byte0]: 51
7977 10:05:16.537167 [Byte1]: 51
7978 10:05:16.541016
7979 10:05:16.541114 Set Vref, RX VrefLevel [Byte0]: 52
7980 10:05:16.544434 [Byte1]: 52
7981 10:05:16.548905
7982 10:05:16.548990 Set Vref, RX VrefLevel [Byte0]: 53
7983 10:05:16.552377 [Byte1]: 53
7984 10:05:16.556578
7985 10:05:16.556687 Set Vref, RX VrefLevel [Byte0]: 54
7986 10:05:16.559876 [Byte1]: 54
7987 10:05:16.564359
7988 10:05:16.564460 Set Vref, RX VrefLevel [Byte0]: 55
7989 10:05:16.567463 [Byte1]: 55
7990 10:05:16.571823
7991 10:05:16.571930 Set Vref, RX VrefLevel [Byte0]: 56
7992 10:05:16.575203 [Byte1]: 56
7993 10:05:16.579774
7994 10:05:16.579850 Set Vref, RX VrefLevel [Byte0]: 57
7995 10:05:16.582733 [Byte1]: 57
7996 10:05:16.586908
7997 10:05:16.586985 Set Vref, RX VrefLevel [Byte0]: 58
7998 10:05:16.590330 [Byte1]: 58
7999 10:05:16.594721
8000 10:05:16.594825 Set Vref, RX VrefLevel [Byte0]: 59
8001 10:05:16.598011 [Byte1]: 59
8002 10:05:16.602002
8003 10:05:16.602087 Set Vref, RX VrefLevel [Byte0]: 60
8004 10:05:16.605433 [Byte1]: 60
8005 10:05:16.609790
8006 10:05:16.609872 Set Vref, RX VrefLevel [Byte0]: 61
8007 10:05:16.612992 [Byte1]: 61
8008 10:05:16.617330
8009 10:05:16.617438 Set Vref, RX VrefLevel [Byte0]: 62
8010 10:05:16.620977 [Byte1]: 62
8011 10:05:16.625428
8012 10:05:16.625524 Set Vref, RX VrefLevel [Byte0]: 63
8013 10:05:16.628710 [Byte1]: 63
8014 10:05:16.632554
8015 10:05:16.632667 Set Vref, RX VrefLevel [Byte0]: 64
8016 10:05:16.636050 [Byte1]: 64
8017 10:05:16.640589
8018 10:05:16.640671 Set Vref, RX VrefLevel [Byte0]: 65
8019 10:05:16.643393 [Byte1]: 65
8020 10:05:16.647830
8021 10:05:16.647914 Set Vref, RX VrefLevel [Byte0]: 66
8022 10:05:16.651279 [Byte1]: 66
8023 10:05:16.655383
8024 10:05:16.655485 Set Vref, RX VrefLevel [Byte0]: 67
8025 10:05:16.658633 [Byte1]: 67
8026 10:05:16.662967
8027 10:05:16.663056 Set Vref, RX VrefLevel [Byte0]: 68
8028 10:05:16.666186 [Byte1]: 68
8029 10:05:16.670748
8030 10:05:16.670849 Set Vref, RX VrefLevel [Byte0]: 69
8031 10:05:16.674013 [Byte1]: 69
8032 10:05:16.678247
8033 10:05:16.678369 Set Vref, RX VrefLevel [Byte0]: 70
8034 10:05:16.681666 [Byte1]: 70
8035 10:05:16.685985
8036 10:05:16.686067 Set Vref, RX VrefLevel [Byte0]: 71
8037 10:05:16.689259 [Byte1]: 71
8038 10:05:16.693849
8039 10:05:16.693931 Set Vref, RX VrefLevel [Byte0]: 72
8040 10:05:16.697130 [Byte1]: 72
8041 10:05:16.701148
8042 10:05:16.701257 Set Vref, RX VrefLevel [Byte0]: 73
8043 10:05:16.704864 [Byte1]: 73
8044 10:05:16.709100
8045 10:05:16.709209 Set Vref, RX VrefLevel [Byte0]: 74
8046 10:05:16.712283 [Byte1]: 74
8047 10:05:16.716621
8048 10:05:16.716719 Set Vref, RX VrefLevel [Byte0]: 75
8049 10:05:16.719813 [Byte1]: 75
8050 10:05:16.723948
8051 10:05:16.724029 Set Vref, RX VrefLevel [Byte0]: 76
8052 10:05:16.727290 [Byte1]: 76
8053 10:05:16.731682
8054 10:05:16.731790 Set Vref, RX VrefLevel [Byte0]: 77
8055 10:05:16.735134 [Byte1]: 77
8056 10:05:16.739278
8057 10:05:16.739360 Set Vref, RX VrefLevel [Byte0]: 78
8058 10:05:16.742311 [Byte1]: 78
8059 10:05:16.746683
8060 10:05:16.746797 Final RX Vref Byte 0 = 64 to rank0
8061 10:05:16.750027 Final RX Vref Byte 1 = 59 to rank0
8062 10:05:16.753306 Final RX Vref Byte 0 = 64 to rank1
8063 10:05:16.756792 Final RX Vref Byte 1 = 59 to rank1==
8064 10:05:16.760094 Dram Type= 6, Freq= 0, CH_0, rank 0
8065 10:05:16.766660 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 10:05:16.766769 ==
8067 10:05:16.766864 DQS Delay:
8068 10:05:16.769911 DQS0 = 0, DQS1 = 0
8069 10:05:16.769993 DQM Delay:
8070 10:05:16.770059 DQM0 = 133, DQM1 = 122
8071 10:05:16.773239 DQ Delay:
8072 10:05:16.776800 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
8073 10:05:16.779598 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8074 10:05:16.783210 DQ8 =112, DQ9 =112, DQ10 =122, DQ11 =118
8075 10:05:16.786342 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
8076 10:05:16.786427
8077 10:05:16.786578
8078 10:05:16.786682
8079 10:05:16.790150 [DramC_TX_OE_Calibration] TA2
8080 10:05:16.792938 Original DQ_B0 (3 6) =30, OEN = 27
8081 10:05:16.796381 Original DQ_B1 (3 6) =30, OEN = 27
8082 10:05:16.799618 24, 0x0, End_B0=24 End_B1=24
8083 10:05:16.802983 25, 0x0, End_B0=25 End_B1=25
8084 10:05:16.803084 26, 0x0, End_B0=26 End_B1=26
8085 10:05:16.806226 27, 0x0, End_B0=27 End_B1=27
8086 10:05:16.809390 28, 0x0, End_B0=28 End_B1=28
8087 10:05:16.813784 29, 0x0, End_B0=29 End_B1=29
8088 10:05:16.813870 30, 0x0, End_B0=30 End_B1=30
8089 10:05:16.815943 31, 0x4141, End_B0=30 End_B1=30
8090 10:05:16.819685 Byte0 end_step=30 best_step=27
8091 10:05:16.822876 Byte1 end_step=30 best_step=27
8092 10:05:16.825820 Byte0 TX OE(2T, 0.5T) = (3, 3)
8093 10:05:16.829049 Byte1 TX OE(2T, 0.5T) = (3, 3)
8094 10:05:16.829160
8095 10:05:16.829254
8096 10:05:16.835798 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 394 ps
8097 10:05:16.839272 CH0 RK0: MR19=303, MR18=1F10
8098 10:05:16.845587 CH0_RK0: MR19=0x303, MR18=0x1F10, DQSOSC=394, MR23=63, INC=23, DEC=15
8099 10:05:16.845675
8100 10:05:16.848729 ----->DramcWriteLeveling(PI) begin...
8101 10:05:16.848813 ==
8102 10:05:16.852364 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 10:05:16.855288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 10:05:16.855372 ==
8105 10:05:16.858705 Write leveling (Byte 0): 36 => 36
8106 10:05:16.862141 Write leveling (Byte 1): 26 => 26
8107 10:05:16.865380 DramcWriteLeveling(PI) end<-----
8108 10:05:16.865464
8109 10:05:16.865529 ==
8110 10:05:16.868771 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 10:05:16.875468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 10:05:16.875552 ==
8113 10:05:16.875620 [Gating] SW mode calibration
8114 10:05:16.885508 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8115 10:05:16.888275 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8116 10:05:16.894704 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8117 10:05:16.898363 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8118 10:05:16.901752 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8119 10:05:16.904981 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8120 10:05:16.911301 1 4 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8121 10:05:16.915211 1 4 20 | B1->B0 | 2b2a 3434 | 1 1 | (0 0) (1 1)
8122 10:05:16.921636 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8123 10:05:16.925190 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8124 10:05:16.927810 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8125 10:05:16.931513 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8126 10:05:16.937880 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8127 10:05:16.941403 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
8128 10:05:16.944842 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
8129 10:05:16.951359 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8130 10:05:16.954314 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8131 10:05:16.957773 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8132 10:05:16.964386 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8133 10:05:16.967999 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8134 10:05:16.971430 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8135 10:05:16.977412 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8136 10:05:16.980713 1 6 16 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
8137 10:05:16.984210 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8138 10:05:16.991000 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8139 10:05:16.993858 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8140 10:05:16.997212 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8141 10:05:17.004137 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8142 10:05:17.007099 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8143 10:05:17.010503 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8144 10:05:17.017426 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8145 10:05:17.020314 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8146 10:05:17.023901 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8147 10:05:17.030647 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 10:05:17.033963 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 10:05:17.037217 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 10:05:17.043307 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 10:05:17.046731 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 10:05:17.049786 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 10:05:17.056622 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 10:05:17.060102 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 10:05:17.063234 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 10:05:17.070104 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 10:05:17.073555 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 10:05:17.077227 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8159 10:05:17.083216 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8160 10:05:17.086447 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8161 10:05:17.089477 Total UI for P1: 0, mck2ui 16
8162 10:05:17.092876 best dqsien dly found for B0: ( 1, 9, 10)
8163 10:05:17.096344 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8164 10:05:17.103106 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8165 10:05:17.106491 Total UI for P1: 0, mck2ui 16
8166 10:05:17.109930 best dqsien dly found for B1: ( 1, 9, 16)
8167 10:05:17.112703 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8168 10:05:17.115864 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8169 10:05:17.115941
8170 10:05:17.119358 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8171 10:05:17.122569 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8172 10:05:17.126225 [Gating] SW calibration Done
8173 10:05:17.126327 ==
8174 10:05:17.129447 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 10:05:17.132690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 10:05:17.132793 ==
8177 10:05:17.136028 RX Vref Scan: 0
8178 10:05:17.136114
8179 10:05:17.139031 RX Vref 0 -> 0, step: 1
8180 10:05:17.139114
8181 10:05:17.139180 RX Delay 0 -> 252, step: 8
8182 10:05:17.145935 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8183 10:05:17.149467 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8184 10:05:17.152423 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8185 10:05:17.155608 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8186 10:05:17.159037 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8187 10:05:17.165790 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8188 10:05:17.168873 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8189 10:05:17.172254 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8190 10:05:17.175623 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8191 10:05:17.178974 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8192 10:05:17.185549 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8193 10:05:17.188835 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8194 10:05:17.192223 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8195 10:05:17.195460 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8196 10:05:17.201898 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8197 10:05:17.205091 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8198 10:05:17.205175 ==
8199 10:05:17.208562 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 10:05:17.211871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 10:05:17.212005 ==
8202 10:05:17.215396 DQS Delay:
8203 10:05:17.215506 DQS0 = 0, DQS1 = 0
8204 10:05:17.215607 DQM Delay:
8205 10:05:17.218549 DQM0 = 132, DQM1 = 128
8206 10:05:17.218627 DQ Delay:
8207 10:05:17.221635 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8208 10:05:17.225012 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8209 10:05:17.228264 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =127
8210 10:05:17.235132 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8211 10:05:17.235244
8212 10:05:17.235339
8213 10:05:17.235429 ==
8214 10:05:17.238297 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 10:05:17.241209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 10:05:17.241318 ==
8217 10:05:17.241414
8218 10:05:17.241507
8219 10:05:17.244758 TX Vref Scan disable
8220 10:05:17.244855 == TX Byte 0 ==
8221 10:05:17.251487 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8222 10:05:17.254776 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8223 10:05:17.257862 == TX Byte 1 ==
8224 10:05:17.261384 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8225 10:05:17.264204 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8226 10:05:17.264306 ==
8227 10:05:17.268132 Dram Type= 6, Freq= 0, CH_0, rank 1
8228 10:05:17.270880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8229 10:05:17.274136 ==
8230 10:05:17.285237
8231 10:05:17.288596 TX Vref early break, caculate TX vref
8232 10:05:17.291597 TX Vref=16, minBit 0, minWin=23, winSum=379
8233 10:05:17.294933 TX Vref=18, minBit 0, minWin=23, winSum=386
8234 10:05:17.298790 TX Vref=20, minBit 1, minWin=23, winSum=392
8235 10:05:17.301972 TX Vref=22, minBit 0, minWin=24, winSum=401
8236 10:05:17.304802 TX Vref=24, minBit 3, minWin=24, winSum=406
8237 10:05:17.311775 TX Vref=26, minBit 0, minWin=25, winSum=414
8238 10:05:17.315003 TX Vref=28, minBit 0, minWin=24, winSum=407
8239 10:05:17.318540 TX Vref=30, minBit 1, minWin=24, winSum=403
8240 10:05:17.321264 TX Vref=32, minBit 7, minWin=23, winSum=392
8241 10:05:17.328039 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 26
8242 10:05:17.328153
8243 10:05:17.331558 Final TX Range 0 Vref 26
8244 10:05:17.331658
8245 10:05:17.331759 ==
8246 10:05:17.334310 Dram Type= 6, Freq= 0, CH_0, rank 1
8247 10:05:17.337760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8248 10:05:17.337886 ==
8249 10:05:17.337982
8250 10:05:17.338074
8251 10:05:17.341111 TX Vref Scan disable
8252 10:05:17.347935 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8253 10:05:17.348015 == TX Byte 0 ==
8254 10:05:17.351245 u2DelayCellOfst[0]=15 cells (4 PI)
8255 10:05:17.354433 u2DelayCellOfst[1]=18 cells (5 PI)
8256 10:05:17.357856 u2DelayCellOfst[2]=15 cells (4 PI)
8257 10:05:17.360716 u2DelayCellOfst[3]=15 cells (4 PI)
8258 10:05:17.364172 u2DelayCellOfst[4]=11 cells (3 PI)
8259 10:05:17.367436 u2DelayCellOfst[5]=0 cells (0 PI)
8260 10:05:17.370977 u2DelayCellOfst[6]=22 cells (6 PI)
8261 10:05:17.374238 u2DelayCellOfst[7]=22 cells (6 PI)
8262 10:05:17.377419 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8263 10:05:17.380691 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8264 10:05:17.383914 == TX Byte 1 ==
8265 10:05:17.387231 u2DelayCellOfst[8]=0 cells (0 PI)
8266 10:05:17.387303 u2DelayCellOfst[9]=0 cells (0 PI)
8267 10:05:17.390873 u2DelayCellOfst[10]=7 cells (2 PI)
8268 10:05:17.393873 u2DelayCellOfst[11]=3 cells (1 PI)
8269 10:05:17.397088 u2DelayCellOfst[12]=11 cells (3 PI)
8270 10:05:17.400796 u2DelayCellOfst[13]=11 cells (3 PI)
8271 10:05:17.403504 u2DelayCellOfst[14]=15 cells (4 PI)
8272 10:05:17.406923 u2DelayCellOfst[15]=11 cells (3 PI)
8273 10:05:17.410453 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8274 10:05:17.417065 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8275 10:05:17.417149 DramC Write-DBI on
8276 10:05:17.417246 ==
8277 10:05:17.420461 Dram Type= 6, Freq= 0, CH_0, rank 1
8278 10:05:17.426581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 10:05:17.426665 ==
8280 10:05:17.426746
8281 10:05:17.426852
8282 10:05:17.426910 TX Vref Scan disable
8283 10:05:17.431001 == TX Byte 0 ==
8284 10:05:17.434536 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8285 10:05:17.437739 == TX Byte 1 ==
8286 10:05:17.440765 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8287 10:05:17.444006 DramC Write-DBI off
8288 10:05:17.444123
8289 10:05:17.444226 [DATLAT]
8290 10:05:17.444326 Freq=1600, CH0 RK1
8291 10:05:17.444424
8292 10:05:17.447512 DATLAT Default: 0xf
8293 10:05:17.450817 0, 0xFFFF, sum = 0
8294 10:05:17.450903 1, 0xFFFF, sum = 0
8295 10:05:17.454389 2, 0xFFFF, sum = 0
8296 10:05:17.454475 3, 0xFFFF, sum = 0
8297 10:05:17.457502 4, 0xFFFF, sum = 0
8298 10:05:17.457588 5, 0xFFFF, sum = 0
8299 10:05:17.461107 6, 0xFFFF, sum = 0
8300 10:05:17.461193 7, 0xFFFF, sum = 0
8301 10:05:17.463870 8, 0xFFFF, sum = 0
8302 10:05:17.463957 9, 0xFFFF, sum = 0
8303 10:05:17.467434 10, 0xFFFF, sum = 0
8304 10:05:17.467520 11, 0xFFFF, sum = 0
8305 10:05:17.470809 12, 0xFFFF, sum = 0
8306 10:05:17.470895 13, 0xFFFF, sum = 0
8307 10:05:17.473917 14, 0x0, sum = 1
8308 10:05:17.474003 15, 0x0, sum = 2
8309 10:05:17.477469 16, 0x0, sum = 3
8310 10:05:17.477556 17, 0x0, sum = 4
8311 10:05:17.480689 best_step = 15
8312 10:05:17.480773
8313 10:05:17.480859 ==
8314 10:05:17.484026 Dram Type= 6, Freq= 0, CH_0, rank 1
8315 10:05:17.487071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 10:05:17.487157 ==
8317 10:05:17.490586 RX Vref Scan: 0
8318 10:05:17.490670
8319 10:05:17.490755 RX Vref 0 -> 0, step: 1
8320 10:05:17.490836
8321 10:05:17.493922 RX Delay 11 -> 252, step: 4
8322 10:05:17.500283 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8323 10:05:17.504018 iDelay=195, Bit 1, Center 136 (83 ~ 190) 108
8324 10:05:17.506727 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8325 10:05:17.510104 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8326 10:05:17.513534 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8327 10:05:17.520286 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8328 10:05:17.523672 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8329 10:05:17.527146 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8330 10:05:17.530193 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8331 10:05:17.533401 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8332 10:05:17.539893 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8333 10:05:17.543351 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8334 10:05:17.546540 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8335 10:05:17.549833 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8336 10:05:17.553149 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8337 10:05:17.559738 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8338 10:05:17.559825 ==
8339 10:05:17.562956 Dram Type= 6, Freq= 0, CH_0, rank 1
8340 10:05:17.566404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 10:05:17.566510 ==
8342 10:05:17.566611 DQS Delay:
8343 10:05:17.569855 DQS0 = 0, DQS1 = 0
8344 10:05:17.569935 DQM Delay:
8345 10:05:17.573468 DQM0 = 130, DQM1 = 125
8346 10:05:17.573546 DQ Delay:
8347 10:05:17.576858 DQ0 =128, DQ1 =136, DQ2 =126, DQ3 =128
8348 10:05:17.579907 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8349 10:05:17.583025 DQ8 =116, DQ9 =112, DQ10 =128, DQ11 =120
8350 10:05:17.586185 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8351 10:05:17.589875
8352 10:05:17.589957
8353 10:05:17.590023
8354 10:05:17.590083 [DramC_TX_OE_Calibration] TA2
8355 10:05:17.593076 Original DQ_B0 (3 6) =30, OEN = 27
8356 10:05:17.596331 Original DQ_B1 (3 6) =30, OEN = 27
8357 10:05:17.599477 24, 0x0, End_B0=24 End_B1=24
8358 10:05:17.602980 25, 0x0, End_B0=25 End_B1=25
8359 10:05:17.606196 26, 0x0, End_B0=26 End_B1=26
8360 10:05:17.606312 27, 0x0, End_B0=27 End_B1=27
8361 10:05:17.609583 28, 0x0, End_B0=28 End_B1=28
8362 10:05:17.612818 29, 0x0, End_B0=29 End_B1=29
8363 10:05:17.616480 30, 0x0, End_B0=30 End_B1=30
8364 10:05:17.619762 31, 0x5151, End_B0=30 End_B1=30
8365 10:05:17.622594 Byte0 end_step=30 best_step=27
8366 10:05:17.622698 Byte1 end_step=30 best_step=27
8367 10:05:17.625702 Byte0 TX OE(2T, 0.5T) = (3, 3)
8368 10:05:17.629223 Byte1 TX OE(2T, 0.5T) = (3, 3)
8369 10:05:17.629346
8370 10:05:17.629469
8371 10:05:17.639038 [DQSOSCAuto] RK1, (LSB)MR18= 0x1dff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 395 ps
8372 10:05:17.639198 CH0 RK1: MR19=302, MR18=1DFF
8373 10:05:17.645880 CH0_RK1: MR19=0x302, MR18=0x1DFF, DQSOSC=395, MR23=63, INC=23, DEC=15
8374 10:05:17.649202 [RxdqsGatingPostProcess] freq 1600
8375 10:05:17.655772 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8376 10:05:17.658709 best DQS0 dly(2T, 0.5T) = (1, 1)
8377 10:05:17.662055 best DQS1 dly(2T, 0.5T) = (1, 1)
8378 10:05:17.665453 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8379 10:05:17.669232 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8380 10:05:17.671936 best DQS0 dly(2T, 0.5T) = (1, 1)
8381 10:05:17.672136 best DQS1 dly(2T, 0.5T) = (1, 1)
8382 10:05:17.675395 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8383 10:05:17.678739 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8384 10:05:17.681880 Pre-setting of DQS Precalculation
8385 10:05:17.688356 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8386 10:05:17.688570 ==
8387 10:05:17.691542 Dram Type= 6, Freq= 0, CH_1, rank 0
8388 10:05:17.694892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8389 10:05:17.695095 ==
8390 10:05:17.701758 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8391 10:05:17.704714 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8392 10:05:17.708294 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8393 10:05:17.714544 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8394 10:05:17.724252 [CA 0] Center 42 (13~72) winsize 60
8395 10:05:17.727826 [CA 1] Center 42 (13~72) winsize 60
8396 10:05:17.730645 [CA 2] Center 37 (8~67) winsize 60
8397 10:05:17.734116 [CA 3] Center 37 (8~66) winsize 59
8398 10:05:17.737610 [CA 4] Center 37 (8~67) winsize 60
8399 10:05:17.740985 [CA 5] Center 37 (7~67) winsize 61
8400 10:05:17.741309
8401 10:05:17.744267 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8402 10:05:17.744729
8403 10:05:17.747578 [CATrainingPosCal] consider 1 rank data
8404 10:05:17.750973 u2DelayCellTimex100 = 258/100 ps
8405 10:05:17.757686 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8406 10:05:17.760794 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8407 10:05:17.764227 CA2 delay=37 (8~67),Diff = 0 PI (0 cell)
8408 10:05:17.767451 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8409 10:05:17.770701 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8410 10:05:17.774003 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8411 10:05:17.774670
8412 10:05:17.777467 CA PerBit enable=1, Macro0, CA PI delay=37
8413 10:05:17.778119
8414 10:05:17.780743 [CBTSetCACLKResult] CA Dly = 37
8415 10:05:17.784061 CS Dly: 9 (0~40)
8416 10:05:17.787586 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8417 10:05:17.790582 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8418 10:05:17.791224 ==
8419 10:05:17.793955 Dram Type= 6, Freq= 0, CH_1, rank 1
8420 10:05:17.799970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 10:05:17.800329 ==
8422 10:05:17.803437 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8423 10:05:17.809710 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8424 10:05:17.813725 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8425 10:05:17.819608 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8426 10:05:17.827340 [CA 0] Center 42 (13~72) winsize 60
8427 10:05:17.830551 [CA 1] Center 42 (13~72) winsize 60
8428 10:05:17.833485 [CA 2] Center 37 (8~67) winsize 60
8429 10:05:17.837171 [CA 3] Center 37 (7~67) winsize 61
8430 10:05:17.840469 [CA 4] Center 37 (8~67) winsize 60
8431 10:05:17.843916 [CA 5] Center 37 (8~67) winsize 60
8432 10:05:17.844074
8433 10:05:17.846928 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8434 10:05:17.847011
8435 10:05:17.853628 [CATrainingPosCal] consider 2 rank data
8436 10:05:17.853712 u2DelayCellTimex100 = 258/100 ps
8437 10:05:17.860368 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8438 10:05:17.863493 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8439 10:05:17.866893 CA2 delay=37 (8~67),Diff = 0 PI (0 cell)
8440 10:05:17.869877 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8441 10:05:17.873634 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8442 10:05:17.876664 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8443 10:05:17.876777
8444 10:05:17.880215 CA PerBit enable=1, Macro0, CA PI delay=37
8445 10:05:17.880344
8446 10:05:17.882989 [CBTSetCACLKResult] CA Dly = 37
8447 10:05:17.886465 CS Dly: 11 (0~44)
8448 10:05:17.890003 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8449 10:05:17.892809 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8450 10:05:17.892935
8451 10:05:17.896198 ----->DramcWriteLeveling(PI) begin...
8452 10:05:17.896328 ==
8453 10:05:17.899441 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 10:05:17.906211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 10:05:17.906338 ==
8456 10:05:17.909669 Write leveling (Byte 0): 24 => 24
8457 10:05:17.912836 Write leveling (Byte 1): 28 => 28
8458 10:05:17.912970 DramcWriteLeveling(PI) end<-----
8459 10:05:17.916066
8460 10:05:17.916212 ==
8461 10:05:17.919495 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 10:05:17.922428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 10:05:17.922605 ==
8464 10:05:17.925794 [Gating] SW mode calibration
8465 10:05:17.932817 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8466 10:05:17.935718 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8467 10:05:17.942572 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8468 10:05:17.946028 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8469 10:05:17.952152 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8470 10:05:17.956091 1 4 12 | B1->B0 | 2323 3131 | 1 1 | (1 1) (1 1)
8471 10:05:17.959093 1 4 16 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8472 10:05:17.962449 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8473 10:05:17.969159 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8474 10:05:17.972257 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8475 10:05:17.975978 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8476 10:05:17.981942 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8477 10:05:17.985828 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8478 10:05:17.988735 1 5 12 | B1->B0 | 3333 2929 | 1 0 | (1 0) (1 0)
8479 10:05:17.995104 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8480 10:05:17.998985 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8481 10:05:18.001661 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8482 10:05:18.008361 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8483 10:05:18.011736 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8484 10:05:18.015019 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8485 10:05:18.021844 1 6 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8486 10:05:18.025001 1 6 12 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
8487 10:05:18.028222 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8488 10:05:18.034762 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8489 10:05:18.037975 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8490 10:05:18.041401 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8491 10:05:18.048423 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8492 10:05:18.051128 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8493 10:05:18.054793 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8494 10:05:18.061446 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8495 10:05:18.064749 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8496 10:05:18.068328 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 10:05:18.074739 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 10:05:18.077687 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 10:05:18.080856 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 10:05:18.087962 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 10:05:18.091286 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 10:05:18.093987 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 10:05:18.100880 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 10:05:18.104294 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 10:05:18.107328 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 10:05:18.113987 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 10:05:18.117404 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 10:05:18.120686 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8509 10:05:18.127317 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8510 10:05:18.130235 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8511 10:05:18.133627 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8512 10:05:18.137292 Total UI for P1: 0, mck2ui 16
8513 10:05:18.140462 best dqsien dly found for B0: ( 1, 9, 8)
8514 10:05:18.147053 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8515 10:05:18.150478 Total UI for P1: 0, mck2ui 16
8516 10:05:18.153635 best dqsien dly found for B1: ( 1, 9, 14)
8517 10:05:18.156809 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8518 10:05:18.160004 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8519 10:05:18.160092
8520 10:05:18.163450 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8521 10:05:18.167058 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8522 10:05:18.170352 [Gating] SW calibration Done
8523 10:05:18.170460 ==
8524 10:05:18.173301 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 10:05:18.176947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 10:05:18.177031 ==
8527 10:05:18.179867 RX Vref Scan: 0
8528 10:05:18.179949
8529 10:05:18.183288 RX Vref 0 -> 0, step: 1
8530 10:05:18.183469
8531 10:05:18.183587 RX Delay 0 -> 252, step: 8
8532 10:05:18.190103 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8533 10:05:18.193371 iDelay=208, Bit 1, Center 135 (88 ~ 183) 96
8534 10:05:18.196874 iDelay=208, Bit 2, Center 131 (80 ~ 183) 104
8535 10:05:18.199735 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8536 10:05:18.202995 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8537 10:05:18.209766 iDelay=208, Bit 5, Center 155 (104 ~ 207) 104
8538 10:05:18.213145 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8539 10:05:18.216215 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8540 10:05:18.219901 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8541 10:05:18.223150 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8542 10:05:18.229613 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8543 10:05:18.232920 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8544 10:05:18.236636 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8545 10:05:18.239437 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8546 10:05:18.242613 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8547 10:05:18.249426 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8548 10:05:18.249528 ==
8549 10:05:18.252818 Dram Type= 6, Freq= 0, CH_1, rank 0
8550 10:05:18.256003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8551 10:05:18.256090 ==
8552 10:05:18.256156 DQS Delay:
8553 10:05:18.259675 DQS0 = 0, DQS1 = 0
8554 10:05:18.259759 DQM Delay:
8555 10:05:18.262714 DQM0 = 139, DQM1 = 129
8556 10:05:18.262846 DQ Delay:
8557 10:05:18.266146 DQ0 =139, DQ1 =135, DQ2 =131, DQ3 =139
8558 10:05:18.269567 DQ4 =135, DQ5 =155, DQ6 =147, DQ7 =135
8559 10:05:18.272318 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8560 10:05:18.276210 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8561 10:05:18.279387
8562 10:05:18.279470
8563 10:05:18.279536 ==
8564 10:05:18.282287 Dram Type= 6, Freq= 0, CH_1, rank 0
8565 10:05:18.286117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8566 10:05:18.286201 ==
8567 10:05:18.286267
8568 10:05:18.286328
8569 10:05:18.289345 TX Vref Scan disable
8570 10:05:18.289444 == TX Byte 0 ==
8571 10:05:18.295943 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8572 10:05:18.298967 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8573 10:05:18.299049 == TX Byte 1 ==
8574 10:05:18.305518 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8575 10:05:18.308845 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8576 10:05:18.308927 ==
8577 10:05:18.312247 Dram Type= 6, Freq= 0, CH_1, rank 0
8578 10:05:18.315595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8579 10:05:18.315678 ==
8580 10:05:18.329537
8581 10:05:18.332406 TX Vref early break, caculate TX vref
8582 10:05:18.335706 TX Vref=16, minBit 0, minWin=22, winSum=377
8583 10:05:18.339152 TX Vref=18, minBit 0, minWin=23, winSum=389
8584 10:05:18.342455 TX Vref=20, minBit 0, minWin=24, winSum=399
8585 10:05:18.345489 TX Vref=22, minBit 5, minWin=23, winSum=409
8586 10:05:18.348770 TX Vref=24, minBit 0, minWin=24, winSum=417
8587 10:05:18.355437 TX Vref=26, minBit 0, minWin=26, winSum=425
8588 10:05:18.358749 TX Vref=28, minBit 1, minWin=25, winSum=427
8589 10:05:18.362034 TX Vref=30, minBit 1, minWin=25, winSum=415
8590 10:05:18.365335 TX Vref=32, minBit 1, minWin=24, winSum=407
8591 10:05:18.369230 TX Vref=34, minBit 1, minWin=23, winSum=398
8592 10:05:18.375459 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 26
8593 10:05:18.375571
8594 10:05:18.378803 Final TX Range 0 Vref 26
8595 10:05:18.378886
8596 10:05:18.378952 ==
8597 10:05:18.382099 Dram Type= 6, Freq= 0, CH_1, rank 0
8598 10:05:18.385458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8599 10:05:18.385543 ==
8600 10:05:18.385610
8601 10:05:18.385671
8602 10:05:18.388352 TX Vref Scan disable
8603 10:05:18.394876 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8604 10:05:18.394988 == TX Byte 0 ==
8605 10:05:18.398332 u2DelayCellOfst[0]=18 cells (5 PI)
8606 10:05:18.401601 u2DelayCellOfst[1]=11 cells (3 PI)
8607 10:05:18.405015 u2DelayCellOfst[2]=0 cells (0 PI)
8608 10:05:18.408234 u2DelayCellOfst[3]=3 cells (1 PI)
8609 10:05:18.411639 u2DelayCellOfst[4]=7 cells (2 PI)
8610 10:05:18.414746 u2DelayCellOfst[5]=22 cells (6 PI)
8611 10:05:18.417914 u2DelayCellOfst[6]=18 cells (5 PI)
8612 10:05:18.421199 u2DelayCellOfst[7]=7 cells (2 PI)
8613 10:05:18.424793 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8614 10:05:18.428055 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8615 10:05:18.431359 == TX Byte 1 ==
8616 10:05:18.434664 u2DelayCellOfst[8]=0 cells (0 PI)
8617 10:05:18.438125 u2DelayCellOfst[9]=3 cells (1 PI)
8618 10:05:18.441534 u2DelayCellOfst[10]=11 cells (3 PI)
8619 10:05:18.441716 u2DelayCellOfst[11]=3 cells (1 PI)
8620 10:05:18.444582 u2DelayCellOfst[12]=15 cells (4 PI)
8621 10:05:18.448021 u2DelayCellOfst[13]=15 cells (4 PI)
8622 10:05:18.451039 u2DelayCellOfst[14]=18 cells (5 PI)
8623 10:05:18.454955 u2DelayCellOfst[15]=18 cells (5 PI)
8624 10:05:18.461715 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8625 10:05:18.464809 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8626 10:05:18.465237 DramC Write-DBI on
8627 10:05:18.465577 ==
8628 10:05:18.468138 Dram Type= 6, Freq= 0, CH_1, rank 0
8629 10:05:18.474587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8630 10:05:18.475074 ==
8631 10:05:18.475438
8632 10:05:18.475912
8633 10:05:18.477692 TX Vref Scan disable
8634 10:05:18.478198 == TX Byte 0 ==
8635 10:05:18.484499 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8636 10:05:18.484951 == TX Byte 1 ==
8637 10:05:18.487819 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8638 10:05:18.490752 DramC Write-DBI off
8639 10:05:18.491220
8640 10:05:18.491575 [DATLAT]
8641 10:05:18.494378 Freq=1600, CH1 RK0
8642 10:05:18.494835
8643 10:05:18.495264 DATLAT Default: 0xf
8644 10:05:18.497601 0, 0xFFFF, sum = 0
8645 10:05:18.498037 1, 0xFFFF, sum = 0
8646 10:05:18.501349 2, 0xFFFF, sum = 0
8647 10:05:18.501855 3, 0xFFFF, sum = 0
8648 10:05:18.504112 4, 0xFFFF, sum = 0
8649 10:05:18.504623 5, 0xFFFF, sum = 0
8650 10:05:18.507511 6, 0xFFFF, sum = 0
8651 10:05:18.508017 7, 0xFFFF, sum = 0
8652 10:05:18.511117 8, 0xFFFF, sum = 0
8653 10:05:18.514087 9, 0xFFFF, sum = 0
8654 10:05:18.514640 10, 0xFFFF, sum = 0
8655 10:05:18.517272 11, 0xFFFF, sum = 0
8656 10:05:18.517802 12, 0xFFFF, sum = 0
8657 10:05:18.520898 13, 0xFFFF, sum = 0
8658 10:05:18.521508 14, 0x0, sum = 1
8659 10:05:18.524092 15, 0x0, sum = 2
8660 10:05:18.524558 16, 0x0, sum = 3
8661 10:05:18.527333 17, 0x0, sum = 4
8662 10:05:18.527764 best_step = 15
8663 10:05:18.528174
8664 10:05:18.528499 ==
8665 10:05:18.530775 Dram Type= 6, Freq= 0, CH_1, rank 0
8666 10:05:18.533990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8667 10:05:18.536979 ==
8668 10:05:18.537403 RX Vref Scan: 1
8669 10:05:18.537743
8670 10:05:18.540442 Set Vref Range= 24 -> 127
8671 10:05:18.540902
8672 10:05:18.543767 RX Vref 24 -> 127, step: 1
8673 10:05:18.544192
8674 10:05:18.544571 RX Delay 11 -> 252, step: 4
8675 10:05:18.544903
8676 10:05:18.547213 Set Vref, RX VrefLevel [Byte0]: 24
8677 10:05:18.549955 [Byte1]: 24
8678 10:05:18.554033
8679 10:05:18.554607 Set Vref, RX VrefLevel [Byte0]: 25
8680 10:05:18.557145 [Byte1]: 25
8681 10:05:18.561708
8682 10:05:18.562272 Set Vref, RX VrefLevel [Byte0]: 26
8683 10:05:18.565341 [Byte1]: 26
8684 10:05:18.569132
8685 10:05:18.569555 Set Vref, RX VrefLevel [Byte0]: 27
8686 10:05:18.572755 [Byte1]: 27
8687 10:05:18.577253
8688 10:05:18.577676 Set Vref, RX VrefLevel [Byte0]: 28
8689 10:05:18.580258 [Byte1]: 28
8690 10:05:18.584418
8691 10:05:18.584900 Set Vref, RX VrefLevel [Byte0]: 29
8692 10:05:18.587717 [Byte1]: 29
8693 10:05:18.592045
8694 10:05:18.592471 Set Vref, RX VrefLevel [Byte0]: 30
8695 10:05:18.595148 [Byte1]: 30
8696 10:05:18.599629
8697 10:05:18.600238 Set Vref, RX VrefLevel [Byte0]: 31
8698 10:05:18.602770 [Byte1]: 31
8699 10:05:18.607243
8700 10:05:18.607668 Set Vref, RX VrefLevel [Byte0]: 32
8701 10:05:18.610715 [Byte1]: 32
8702 10:05:18.615108
8703 10:05:18.615578 Set Vref, RX VrefLevel [Byte0]: 33
8704 10:05:18.618259 [Byte1]: 33
8705 10:05:18.622567
8706 10:05:18.623076 Set Vref, RX VrefLevel [Byte0]: 34
8707 10:05:18.625985 [Byte1]: 34
8708 10:05:18.630320
8709 10:05:18.630815 Set Vref, RX VrefLevel [Byte0]: 35
8710 10:05:18.633464 [Byte1]: 35
8711 10:05:18.638190
8712 10:05:18.638758 Set Vref, RX VrefLevel [Byte0]: 36
8713 10:05:18.640819 [Byte1]: 36
8714 10:05:18.645459
8715 10:05:18.646036 Set Vref, RX VrefLevel [Byte0]: 37
8716 10:05:18.648822 [Byte1]: 37
8717 10:05:18.652866
8718 10:05:18.653440 Set Vref, RX VrefLevel [Byte0]: 38
8719 10:05:18.656439 [Byte1]: 38
8720 10:05:18.660340
8721 10:05:18.660966 Set Vref, RX VrefLevel [Byte0]: 39
8722 10:05:18.663935 [Byte1]: 39
8723 10:05:18.668079
8724 10:05:18.668693 Set Vref, RX VrefLevel [Byte0]: 40
8725 10:05:18.671459 [Byte1]: 40
8726 10:05:18.676062
8727 10:05:18.676696 Set Vref, RX VrefLevel [Byte0]: 41
8728 10:05:18.678925 [Byte1]: 41
8729 10:05:18.683381
8730 10:05:18.683862 Set Vref, RX VrefLevel [Byte0]: 42
8731 10:05:18.686509 [Byte1]: 42
8732 10:05:18.690874
8733 10:05:18.691360 Set Vref, RX VrefLevel [Byte0]: 43
8734 10:05:18.694657 [Byte1]: 43
8735 10:05:18.698829
8736 10:05:18.699300 Set Vref, RX VrefLevel [Byte0]: 44
8737 10:05:18.702114 [Byte1]: 44
8738 10:05:18.706454
8739 10:05:18.706876 Set Vref, RX VrefLevel [Byte0]: 45
8740 10:05:18.712445 [Byte1]: 45
8741 10:05:18.712922
8742 10:05:18.716211 Set Vref, RX VrefLevel [Byte0]: 46
8743 10:05:18.719279 [Byte1]: 46
8744 10:05:18.719703
8745 10:05:18.722595 Set Vref, RX VrefLevel [Byte0]: 47
8746 10:05:18.725838 [Byte1]: 47
8747 10:05:18.729483
8748 10:05:18.729906 Set Vref, RX VrefLevel [Byte0]: 48
8749 10:05:18.732472 [Byte1]: 48
8750 10:05:18.736736
8751 10:05:18.737262 Set Vref, RX VrefLevel [Byte0]: 49
8752 10:05:18.740406 [Byte1]: 49
8753 10:05:18.744299
8754 10:05:18.744767 Set Vref, RX VrefLevel [Byte0]: 50
8755 10:05:18.747720 [Byte1]: 50
8756 10:05:18.751665
8757 10:05:18.752091 Set Vref, RX VrefLevel [Byte0]: 51
8758 10:05:18.755430 [Byte1]: 51
8759 10:05:18.760141
8760 10:05:18.760608 Set Vref, RX VrefLevel [Byte0]: 52
8761 10:05:18.763167 [Byte1]: 52
8762 10:05:18.767340
8763 10:05:18.767766 Set Vref, RX VrefLevel [Byte0]: 53
8764 10:05:18.770937 [Byte1]: 53
8765 10:05:18.774659
8766 10:05:18.775233 Set Vref, RX VrefLevel [Byte0]: 54
8767 10:05:18.778374 [Byte1]: 54
8768 10:05:18.782411
8769 10:05:18.782712 Set Vref, RX VrefLevel [Byte0]: 55
8770 10:05:18.785621 [Byte1]: 55
8771 10:05:18.789785
8772 10:05:18.789983 Set Vref, RX VrefLevel [Byte0]: 56
8773 10:05:18.793063 [Byte1]: 56
8774 10:05:18.797233
8775 10:05:18.797374 Set Vref, RX VrefLevel [Byte0]: 57
8776 10:05:18.800482 [Byte1]: 57
8777 10:05:18.805163
8778 10:05:18.805321 Set Vref, RX VrefLevel [Byte0]: 58
8779 10:05:18.811400 [Byte1]: 58
8780 10:05:18.811539
8781 10:05:19.324618 Set Vref, RX VrefLevel [Byte0]: 59
8782 10:05:19.325689 [Byte1]: 59
8783 10:05:19.326346
8784 10:05:19.326919 Set Vref, RX VrefLevel [Byte0]: 60
8785 10:05:19.327496 [Byte1]: 60
8786 10:05:19.328027
8787 10:05:19.328590 Set Vref, RX VrefLevel [Byte0]: 61
8788 10:05:19.329111 [Byte1]: 61
8789 10:05:19.329645
8790 10:05:19.330201 Set Vref, RX VrefLevel [Byte0]: 62
8791 10:05:19.330833 [Byte1]: 62
8792 10:05:19.331444
8793 10:05:19.332057 Set Vref, RX VrefLevel [Byte0]: 63
8794 10:05:19.332691 [Byte1]: 63
8795 10:05:19.333295
8796 10:05:19.333900 Set Vref, RX VrefLevel [Byte0]: 64
8797 10:05:19.334518 [Byte1]: 64
8798 10:05:19.335114
8799 10:05:19.335712 Set Vref, RX VrefLevel [Byte0]: 65
8800 10:05:19.336340 [Byte1]: 65
8801 10:05:19.336969
8802 10:05:19.337565 Set Vref, RX VrefLevel [Byte0]: 66
8803 10:05:19.338167 [Byte1]: 66
8804 10:05:19.338784
8805 10:05:19.339397 Set Vref, RX VrefLevel [Byte0]: 67
8806 10:05:19.339999 [Byte1]: 67
8807 10:05:19.340614
8808 10:05:19.341218 Set Vref, RX VrefLevel [Byte0]: 68
8809 10:05:19.341808 [Byte1]: 68
8810 10:05:19.342390
8811 10:05:19.342974 Set Vref, RX VrefLevel [Byte0]: 69
8812 10:05:19.343561 [Byte1]: 69
8813 10:05:19.344134
8814 10:05:19.344739 Set Vref, RX VrefLevel [Byte0]: 70
8815 10:05:19.345329 [Byte1]: 70
8816 10:05:19.345913
8817 10:05:19.346495 Set Vref, RX VrefLevel [Byte0]: 71
8818 10:05:19.347079 [Byte1]: 71
8819 10:05:19.347651
8820 10:05:19.348249 Set Vref, RX VrefLevel [Byte0]: 72
8821 10:05:19.348870 [Byte1]: 72
8822 10:05:19.349458
8823 10:05:19.350051 Set Vref, RX VrefLevel [Byte0]: 73
8824 10:05:19.350634 [Byte1]: 73
8825 10:05:19.351207
8826 10:05:19.351787 Set Vref, RX VrefLevel [Byte0]: 74
8827 10:05:19.352369 [Byte1]: 74
8828 10:05:19.352963
8829 10:05:19.353549 Final RX Vref Byte 0 = 57 to rank0
8830 10:05:19.354063 Final RX Vref Byte 1 = 60 to rank0
8831 10:05:19.354475 Final RX Vref Byte 0 = 57 to rank1
8832 10:05:19.354887 Final RX Vref Byte 1 = 60 to rank1==
8833 10:05:19.355297 Dram Type= 6, Freq= 0, CH_1, rank 0
8834 10:05:19.355705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 10:05:19.356118 ==
8836 10:05:19.356535 DQS Delay:
8837 10:05:19.356939 DQS0 = 0, DQS1 = 0
8838 10:05:19.357346 DQM Delay:
8839 10:05:19.357755 DQM0 = 135, DQM1 = 128
8840 10:05:19.358161 DQ Delay:
8841 10:05:19.358568 DQ0 =142, DQ1 =128, DQ2 =126, DQ3 =132
8842 10:05:19.358949 DQ4 =132, DQ5 =148, DQ6 =146, DQ7 =130
8843 10:05:19.359257 DQ8 =116, DQ9 =116, DQ10 =130, DQ11 =118
8844 10:05:19.359566 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =138
8845 10:05:19.359866
8846 10:05:19.360176
8847 10:05:19.360484
8848 10:05:19.360798 [DramC_TX_OE_Calibration] TA2
8849 10:05:19.361109 Original DQ_B0 (3 6) =30, OEN = 27
8850 10:05:19.361421 Original DQ_B1 (3 6) =30, OEN = 27
8851 10:05:19.361729 24, 0x0, End_B0=24 End_B1=24
8852 10:05:19.362045 25, 0x0, End_B0=25 End_B1=25
8853 10:05:19.362358 26, 0x0, End_B0=26 End_B1=26
8854 10:05:19.362675 27, 0x0, End_B0=27 End_B1=27
8855 10:05:19.362991 28, 0x0, End_B0=28 End_B1=28
8856 10:05:19.363306 29, 0x0, End_B0=29 End_B1=29
8857 10:05:19.363617 30, 0x0, End_B0=30 End_B1=30
8858 10:05:19.363924 31, 0x4141, End_B0=30 End_B1=30
8859 10:05:19.364169 Byte0 end_step=30 best_step=27
8860 10:05:19.364414 Byte1 end_step=30 best_step=27
8861 10:05:19.364664 Byte0 TX OE(2T, 0.5T) = (3, 3)
8862 10:05:19.364911 Byte1 TX OE(2T, 0.5T) = (3, 3)
8863 10:05:19.365157
8864 10:05:19.365407
8865 10:05:19.365657 [DQSOSCAuto] RK0, (LSB)MR18= 0x190e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8866 10:05:19.365907 CH1 RK0: MR19=303, MR18=190E
8867 10:05:19.366154 CH1_RK0: MR19=0x303, MR18=0x190E, DQSOSC=397, MR23=63, INC=23, DEC=15
8868 10:05:19.366411
8869 10:05:19.366652 ----->DramcWriteLeveling(PI) begin...
8870 10:05:19.366905 ==
8871 10:05:19.367157 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 10:05:19.367407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 10:05:19.367654 ==
8874 10:05:19.367903 Write leveling (Byte 0): 22 => 22
8875 10:05:19.368150 Write leveling (Byte 1): 27 => 27
8876 10:05:19.368396 DramcWriteLeveling(PI) end<-----
8877 10:05:19.368657
8878 10:05:19.368903 ==
8879 10:05:19.369112 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 10:05:19.369322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 10:05:19.369529 ==
8882 10:05:19.369736 [Gating] SW mode calibration
8883 10:05:19.369944 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8884 10:05:19.370149 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8885 10:05:19.370353 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8886 10:05:19.370562 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8887 10:05:19.370772 1 4 8 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
8888 10:05:19.370980 1 4 12 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (0 0)
8889 10:05:19.371188 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8890 10:05:19.371396 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8891 10:05:19.371603 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8892 10:05:19.371803 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8893 10:05:19.372007 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8894 10:05:19.372213 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8895 10:05:19.372423 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8896 10:05:19.372724 1 5 12 | B1->B0 | 3232 3434 | 1 1 | (0 1) (1 0)
8897 10:05:19.372885 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8898 10:05:19.373012 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8899 10:05:19.373124 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8900 10:05:19.373232 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8901 10:05:19.373337 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8902 10:05:19.373439 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8903 10:05:19.373541 1 6 8 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
8904 10:05:19.373643 1 6 12 | B1->B0 | 3d3d 2626 | 0 0 | (0 0) (0 0)
8905 10:05:19.373744 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8906 10:05:19.373853 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8907 10:05:19.373938 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8908 10:05:19.374024 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8909 10:05:19.374315 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8910 10:05:19.374411 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8911 10:05:19.374499 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8912 10:05:19.374585 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8913 10:05:19.374671 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8914 10:05:19.374756 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8915 10:05:19.374840 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8916 10:05:19.374925 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8917 10:05:19.375009 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8918 10:05:19.375094 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8919 10:05:19.375179 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8920 10:05:19.375265 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8921 10:05:19.375349 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8922 10:05:19.375433 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8923 10:05:19.375517 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8924 10:05:19.375603 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8925 10:05:19.375688 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8926 10:05:19.375772 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8927 10:05:19.375888 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8928 10:05:19.375975 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8929 10:05:19.376059 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8930 10:05:19.376143 Total UI for P1: 0, mck2ui 16
8931 10:05:19.376229 best dqsien dly found for B1: ( 1, 9, 12)
8932 10:05:19.376315 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8933 10:05:19.376399 Total UI for P1: 0, mck2ui 16
8934 10:05:19.376490 best dqsien dly found for B0: ( 1, 9, 14)
8935 10:05:19.376602 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8936 10:05:19.376690 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8937 10:05:19.376775
8938 10:05:19.376859 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8939 10:05:19.376944 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8940 10:05:19.377029 [Gating] SW calibration Done
8941 10:05:19.377114 ==
8942 10:05:19.377199 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 10:05:19.377284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 10:05:19.377370 ==
8945 10:05:19.377454 RX Vref Scan: 0
8946 10:05:19.377539
8947 10:05:19.377623 RX Vref 0 -> 0, step: 1
8948 10:05:19.377707
8949 10:05:19.377790 RX Delay 0 -> 252, step: 8
8950 10:05:19.377875 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8951 10:05:19.377961 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8952 10:05:19.378044 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8953 10:05:19.378129 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8954 10:05:19.378214 iDelay=208, Bit 4, Center 139 (80 ~ 199) 120
8955 10:05:19.378299 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8956 10:05:19.378383 iDelay=208, Bit 6, Center 151 (96 ~ 207) 112
8957 10:05:19.378468 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8958 10:05:19.378551 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8959 10:05:19.378636 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8960 10:05:19.378720 iDelay=208, Bit 10, Center 127 (64 ~ 191) 128
8961 10:05:19.378805 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8962 10:05:19.378919 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8963 10:05:19.379430 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8964 10:05:19.382494 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8965 10:05:19.389374 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8966 10:05:19.389473 ==
8967 10:05:19.392151 Dram Type= 6, Freq= 0, CH_1, rank 1
8968 10:05:19.395696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8969 10:05:19.395780 ==
8970 10:05:19.395847 DQS Delay:
8971 10:05:19.398978 DQS0 = 0, DQS1 = 0
8972 10:05:19.399062 DQM Delay:
8973 10:05:19.402415 DQM0 = 138, DQM1 = 129
8974 10:05:19.402499 DQ Delay:
8975 10:05:19.405280 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8976 10:05:19.408490 DQ4 =139, DQ5 =151, DQ6 =151, DQ7 =135
8977 10:05:19.412431 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8978 10:05:19.415176 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8979 10:05:19.415260
8980 10:05:19.415326
8981 10:05:19.418963 ==
8982 10:05:19.422229 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 10:05:19.425416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 10:05:19.425500 ==
8985 10:05:19.425566
8986 10:05:19.425626
8987 10:05:19.428837 TX Vref Scan disable
8988 10:05:19.428941 == TX Byte 0 ==
8989 10:05:19.435260 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8990 10:05:19.438607 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8991 10:05:19.438696 == TX Byte 1 ==
8992 10:05:19.445504 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8993 10:05:19.448530 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8994 10:05:19.448621 ==
8995 10:05:19.451605 Dram Type= 6, Freq= 0, CH_1, rank 1
8996 10:05:19.454829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8997 10:05:19.454939 ==
8998 10:05:19.469630
8999 10:05:19.472966 TX Vref early break, caculate TX vref
9000 10:05:19.476512 TX Vref=16, minBit 1, minWin=21, winSum=382
9001 10:05:19.479388 TX Vref=18, minBit 1, minWin=23, winSum=391
9002 10:05:19.482667 TX Vref=20, minBit 1, minWin=23, winSum=400
9003 10:05:19.486188 TX Vref=22, minBit 0, minWin=24, winSum=409
9004 10:05:19.489450 TX Vref=24, minBit 0, minWin=24, winSum=416
9005 10:05:19.496353 TX Vref=26, minBit 0, minWin=24, winSum=416
9006 10:05:19.499535 TX Vref=28, minBit 0, minWin=24, winSum=420
9007 10:05:19.502614 TX Vref=30, minBit 0, minWin=23, winSum=415
9008 10:05:19.505789 TX Vref=32, minBit 0, minWin=23, winSum=411
9009 10:05:19.509222 TX Vref=34, minBit 0, minWin=22, winSum=401
9010 10:05:19.515733 TX Vref=36, minBit 5, minWin=22, winSum=391
9011 10:05:19.519041 [TxChooseVref] Worse bit 0, Min win 24, Win sum 420, Final Vref 28
9012 10:05:19.519124
9013 10:05:19.522464 Final TX Range 0 Vref 28
9014 10:05:19.522549
9015 10:05:19.522615 ==
9016 10:05:19.525849 Dram Type= 6, Freq= 0, CH_1, rank 1
9017 10:05:19.529184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9018 10:05:19.529268 ==
9019 10:05:19.532361
9020 10:05:19.532443
9021 10:05:19.532509 TX Vref Scan disable
9022 10:05:19.539041 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
9023 10:05:19.539131 == TX Byte 0 ==
9024 10:05:19.542549 u2DelayCellOfst[0]=18 cells (5 PI)
9025 10:05:19.545713 u2DelayCellOfst[1]=11 cells (3 PI)
9026 10:05:19.549057 u2DelayCellOfst[2]=0 cells (0 PI)
9027 10:05:19.552279 u2DelayCellOfst[3]=3 cells (1 PI)
9028 10:05:19.555426 u2DelayCellOfst[4]=7 cells (2 PI)
9029 10:05:19.559199 u2DelayCellOfst[5]=18 cells (5 PI)
9030 10:05:19.561890 u2DelayCellOfst[6]=18 cells (5 PI)
9031 10:05:19.565363 u2DelayCellOfst[7]=3 cells (1 PI)
9032 10:05:19.568708 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
9033 10:05:19.571843 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
9034 10:05:19.575317 == TX Byte 1 ==
9035 10:05:19.578696 u2DelayCellOfst[8]=0 cells (0 PI)
9036 10:05:19.582005 u2DelayCellOfst[9]=3 cells (1 PI)
9037 10:05:19.585529 u2DelayCellOfst[10]=11 cells (3 PI)
9038 10:05:19.588480 u2DelayCellOfst[11]=3 cells (1 PI)
9039 10:05:19.591538 u2DelayCellOfst[12]=15 cells (4 PI)
9040 10:05:19.591619 u2DelayCellOfst[13]=15 cells (4 PI)
9041 10:05:19.594898 u2DelayCellOfst[14]=18 cells (5 PI)
9042 10:05:19.598195 u2DelayCellOfst[15]=18 cells (5 PI)
9043 10:05:19.605244 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9044 10:05:19.608214 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9045 10:05:19.611952 DramC Write-DBI on
9046 10:05:19.612029 ==
9047 10:05:19.614670 Dram Type= 6, Freq= 0, CH_1, rank 1
9048 10:05:19.618023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9049 10:05:19.618107 ==
9050 10:05:19.618174
9051 10:05:19.618234
9052 10:05:19.621299 TX Vref Scan disable
9053 10:05:19.621383 == TX Byte 0 ==
9054 10:05:19.627956 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
9055 10:05:19.628053 == TX Byte 1 ==
9056 10:05:19.631737 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9057 10:05:19.634982 DramC Write-DBI off
9058 10:05:19.635094
9059 10:05:19.635190 [DATLAT]
9060 10:05:19.638379 Freq=1600, CH1 RK1
9061 10:05:19.638465
9062 10:05:19.638551 DATLAT Default: 0xf
9063 10:05:19.641213 0, 0xFFFF, sum = 0
9064 10:05:19.641304 1, 0xFFFF, sum = 0
9065 10:05:19.644441 2, 0xFFFF, sum = 0
9066 10:05:19.644577 3, 0xFFFF, sum = 0
9067 10:05:19.647760 4, 0xFFFF, sum = 0
9068 10:05:19.647828 5, 0xFFFF, sum = 0
9069 10:05:19.651188 6, 0xFFFF, sum = 0
9070 10:05:19.654566 7, 0xFFFF, sum = 0
9071 10:05:19.654642 8, 0xFFFF, sum = 0
9072 10:05:19.657988 9, 0xFFFF, sum = 0
9073 10:05:19.658065 10, 0xFFFF, sum = 0
9074 10:05:19.661230 11, 0xFFFF, sum = 0
9075 10:05:19.661332 12, 0xFFFF, sum = 0
9076 10:05:19.664780 13, 0xFFFF, sum = 0
9077 10:05:19.664881 14, 0x0, sum = 1
9078 10:05:19.667662 15, 0x0, sum = 2
9079 10:05:19.667732 16, 0x0, sum = 3
9080 10:05:19.671335 17, 0x0, sum = 4
9081 10:05:19.671432 best_step = 15
9082 10:05:19.671519
9083 10:05:19.671605 ==
9084 10:05:19.674582 Dram Type= 6, Freq= 0, CH_1, rank 1
9085 10:05:19.680543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9086 10:05:19.680639 ==
9087 10:05:19.680728 RX Vref Scan: 0
9088 10:05:19.680815
9089 10:05:19.684104 RX Vref 0 -> 0, step: 1
9090 10:05:19.684170
9091 10:05:19.687063 RX Delay 11 -> 252, step: 4
9092 10:05:19.690410 iDelay=199, Bit 0, Center 140 (87 ~ 194) 108
9093 10:05:19.693975 iDelay=199, Bit 1, Center 130 (79 ~ 182) 104
9094 10:05:19.697236 iDelay=199, Bit 2, Center 122 (67 ~ 178) 112
9095 10:05:19.703821 iDelay=199, Bit 3, Center 132 (83 ~ 182) 100
9096 10:05:19.707101 iDelay=199, Bit 4, Center 134 (79 ~ 190) 112
9097 10:05:19.709982 iDelay=199, Bit 5, Center 146 (95 ~ 198) 104
9098 10:05:19.713462 iDelay=199, Bit 6, Center 146 (95 ~ 198) 104
9099 10:05:19.720025 iDelay=199, Bit 7, Center 132 (83 ~ 182) 100
9100 10:05:19.723244 iDelay=199, Bit 8, Center 112 (55 ~ 170) 116
9101 10:05:19.726562 iDelay=199, Bit 9, Center 114 (59 ~ 170) 112
9102 10:05:19.729891 iDelay=199, Bit 10, Center 126 (71 ~ 182) 112
9103 10:05:19.733246 iDelay=199, Bit 11, Center 116 (63 ~ 170) 108
9104 10:05:19.740052 iDelay=199, Bit 12, Center 134 (79 ~ 190) 112
9105 10:05:19.742981 iDelay=199, Bit 13, Center 134 (79 ~ 190) 112
9106 10:05:19.746557 iDelay=199, Bit 14, Center 132 (75 ~ 190) 116
9107 10:05:19.749555 iDelay=199, Bit 15, Center 136 (79 ~ 194) 116
9108 10:05:19.749638 ==
9109 10:05:19.753095 Dram Type= 6, Freq= 0, CH_1, rank 1
9110 10:05:19.759656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9111 10:05:19.759740 ==
9112 10:05:19.759806 DQS Delay:
9113 10:05:19.762744 DQS0 = 0, DQS1 = 0
9114 10:05:19.762827 DQM Delay:
9115 10:05:19.766004 DQM0 = 135, DQM1 = 125
9116 10:05:19.766086 DQ Delay:
9117 10:05:19.769055 DQ0 =140, DQ1 =130, DQ2 =122, DQ3 =132
9118 10:05:19.772435 DQ4 =134, DQ5 =146, DQ6 =146, DQ7 =132
9119 10:05:19.775661 DQ8 =112, DQ9 =114, DQ10 =126, DQ11 =116
9120 10:05:19.778991 DQ12 =134, DQ13 =134, DQ14 =132, DQ15 =136
9121 10:05:19.779075
9122 10:05:19.779140
9123 10:05:19.779200
9124 10:05:19.782394 [DramC_TX_OE_Calibration] TA2
9125 10:05:19.785414 Original DQ_B0 (3 6) =30, OEN = 27
9126 10:05:19.789003 Original DQ_B1 (3 6) =30, OEN = 27
9127 10:05:19.792054 24, 0x0, End_B0=24 End_B1=24
9128 10:05:19.795525 25, 0x0, End_B0=25 End_B1=25
9129 10:05:19.795633 26, 0x0, End_B0=26 End_B1=26
9130 10:05:19.798988 27, 0x0, End_B0=27 End_B1=27
9131 10:05:19.801874 28, 0x0, End_B0=28 End_B1=28
9132 10:05:19.805663 29, 0x0, End_B0=29 End_B1=29
9133 10:05:19.809078 30, 0x0, End_B0=30 End_B1=30
9134 10:05:19.809163 31, 0x4141, End_B0=30 End_B1=30
9135 10:05:19.811924 Byte0 end_step=30 best_step=27
9136 10:05:19.815366 Byte1 end_step=30 best_step=27
9137 10:05:19.818784 Byte0 TX OE(2T, 0.5T) = (3, 3)
9138 10:05:19.822237 Byte1 TX OE(2T, 0.5T) = (3, 3)
9139 10:05:19.822320
9140 10:05:19.822387
9141 10:05:19.828553 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
9142 10:05:19.831698 CH1 RK1: MR19=303, MR18=E0A
9143 10:05:19.838126 CH1_RK1: MR19=0x303, MR18=0xE0A, DQSOSC=402, MR23=63, INC=22, DEC=15
9144 10:05:19.841956 [RxdqsGatingPostProcess] freq 1600
9145 10:05:19.847919 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9146 10:05:19.851324 best DQS0 dly(2T, 0.5T) = (1, 1)
9147 10:05:19.851473 best DQS1 dly(2T, 0.5T) = (1, 1)
9148 10:05:19.855171 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9149 10:05:19.858578 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9150 10:05:19.861325 best DQS0 dly(2T, 0.5T) = (1, 1)
9151 10:05:19.864757 best DQS1 dly(2T, 0.5T) = (1, 1)
9152 10:05:19.868361 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9153 10:05:19.871609 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9154 10:05:19.874688 Pre-setting of DQS Precalculation
9155 10:05:19.877984 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9156 10:05:19.887771 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9157 10:05:19.894666 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9158 10:05:19.894778
9159 10:05:19.894882
9160 10:05:19.897963 [Calibration Summary] 3200 Mbps
9161 10:05:19.898072 CH 0, Rank 0
9162 10:05:19.901309 SW Impedance : PASS
9163 10:05:19.901422 DUTY Scan : NO K
9164 10:05:19.904622 ZQ Calibration : PASS
9165 10:05:19.907890 Jitter Meter : NO K
9166 10:05:19.908009 CBT Training : PASS
9167 10:05:19.910898 Write leveling : PASS
9168 10:05:19.914142 RX DQS gating : PASS
9169 10:05:19.914261 RX DQ/DQS(RDDQC) : PASS
9170 10:05:19.917504 TX DQ/DQS : PASS
9171 10:05:19.920658 RX DATLAT : PASS
9172 10:05:19.920778 RX DQ/DQS(Engine): PASS
9173 10:05:19.924198 TX OE : PASS
9174 10:05:19.924302 All Pass.
9175 10:05:19.924403
9176 10:05:19.927809 CH 0, Rank 1
9177 10:05:19.927912 SW Impedance : PASS
9178 10:05:19.931138 DUTY Scan : NO K
9179 10:05:19.934013 ZQ Calibration : PASS
9180 10:05:19.934123 Jitter Meter : NO K
9181 10:05:19.937291 CBT Training : PASS
9182 10:05:19.940416 Write leveling : PASS
9183 10:05:19.940593 RX DQS gating : PASS
9184 10:05:19.943760 RX DQ/DQS(RDDQC) : PASS
9185 10:05:19.947532 TX DQ/DQS : PASS
9186 10:05:19.947675 RX DATLAT : PASS
9187 10:05:19.950864 RX DQ/DQS(Engine): PASS
9188 10:05:19.953730 TX OE : PASS
9189 10:05:19.953900 All Pass.
9190 10:05:19.954031
9191 10:05:19.954155 CH 1, Rank 0
9192 10:05:19.957028 SW Impedance : PASS
9193 10:05:19.960906 DUTY Scan : NO K
9194 10:05:19.961007 ZQ Calibration : PASS
9195 10:05:19.963971 Jitter Meter : NO K
9196 10:05:19.967185 CBT Training : PASS
9197 10:05:19.967268 Write leveling : PASS
9198 10:05:19.970683 RX DQS gating : PASS
9199 10:05:19.973936 RX DQ/DQS(RDDQC) : PASS
9200 10:05:19.974018 TX DQ/DQS : PASS
9201 10:05:19.977126 RX DATLAT : PASS
9202 10:05:19.977209 RX DQ/DQS(Engine): PASS
9203 10:05:19.980127 TX OE : PASS
9204 10:05:19.980210 All Pass.
9205 10:05:19.980275
9206 10:05:19.983854 CH 1, Rank 1
9207 10:05:19.983937 SW Impedance : PASS
9208 10:05:19.986687 DUTY Scan : NO K
9209 10:05:19.990129 ZQ Calibration : PASS
9210 10:05:19.990211 Jitter Meter : NO K
9211 10:05:19.993088 CBT Training : PASS
9212 10:05:19.996512 Write leveling : PASS
9213 10:05:19.996632 RX DQS gating : PASS
9214 10:05:19.999774 RX DQ/DQS(RDDQC) : PASS
9215 10:05:20.003490 TX DQ/DQS : PASS
9216 10:05:20.003572 RX DATLAT : PASS
9217 10:05:20.006285 RX DQ/DQS(Engine): PASS
9218 10:05:20.009730 TX OE : PASS
9219 10:05:20.009812 All Pass.
9220 10:05:20.009878
9221 10:05:20.013082 DramC Write-DBI on
9222 10:05:20.013164 PER_BANK_REFRESH: Hybrid Mode
9223 10:05:20.016211 TX_TRACKING: ON
9224 10:05:20.026281 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9225 10:05:20.033019 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9226 10:05:20.039762 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9227 10:05:20.042846 [FAST_K] Save calibration result to emmc
9228 10:05:20.046512 sync common calibartion params.
9229 10:05:20.049816 sync cbt_mode0:1, 1:1
9230 10:05:20.049977 dram_init: ddr_geometry: 2
9231 10:05:20.052877 dram_init: ddr_geometry: 2
9232 10:05:20.056299 dram_init: ddr_geometry: 2
9233 10:05:20.059925 0:dram_rank_size:100000000
9234 10:05:20.060357 1:dram_rank_size:100000000
9235 10:05:20.066289 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9236 10:05:20.069814 DFS_SHUFFLE_HW_MODE: ON
9237 10:05:20.072997 dramc_set_vcore_voltage set vcore to 725000
9238 10:05:20.076165 Read voltage for 1600, 0
9239 10:05:20.076612 Vio18 = 0
9240 10:05:20.076955 Vcore = 725000
9241 10:05:20.079263 Vdram = 0
9242 10:05:20.079685 Vddq = 0
9243 10:05:20.080020 Vmddr = 0
9244 10:05:20.082773 switch to 3200 Mbps bootup
9245 10:05:20.083346 [DramcRunTimeConfig]
9246 10:05:20.086325 PHYPLL
9247 10:05:20.087007 DPM_CONTROL_AFTERK: ON
9248 10:05:20.089425 PER_BANK_REFRESH: ON
9249 10:05:20.092860 REFRESH_OVERHEAD_REDUCTION: ON
9250 10:05:20.093282 CMD_PICG_NEW_MODE: OFF
9251 10:05:20.096378 XRTWTW_NEW_MODE: ON
9252 10:05:20.096955 XRTRTR_NEW_MODE: ON
9253 10:05:20.099553 TX_TRACKING: ON
9254 10:05:20.099975 RDSEL_TRACKING: OFF
9255 10:05:20.102636 DQS Precalculation for DVFS: ON
9256 10:05:20.105884 RX_TRACKING: OFF
9257 10:05:20.106310 HW_GATING DBG: ON
9258 10:05:20.109359 ZQCS_ENABLE_LP4: ON
9259 10:05:20.109806 RX_PICG_NEW_MODE: ON
9260 10:05:20.112545 TX_PICG_NEW_MODE: ON
9261 10:05:20.115984 ENABLE_RX_DCM_DPHY: ON
9262 10:05:20.116407 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9263 10:05:20.118788 DUMMY_READ_FOR_TRACKING: OFF
9264 10:05:20.122243 !!! SPM_CONTROL_AFTERK: OFF
9265 10:05:20.125616 !!! SPM could not control APHY
9266 10:05:20.126063 IMPEDANCE_TRACKING: ON
9267 10:05:20.128630 TEMP_SENSOR: ON
9268 10:05:20.129068 HW_SAVE_FOR_SR: OFF
9269 10:05:20.132143 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9270 10:05:20.138553 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9271 10:05:20.139073 Read ODT Tracking: ON
9272 10:05:20.141769 Refresh Rate DeBounce: ON
9273 10:05:20.142346 DFS_NO_QUEUE_FLUSH: ON
9274 10:05:20.144980 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9275 10:05:20.148401 ENABLE_DFS_RUNTIME_MRW: OFF
9276 10:05:20.151817 DDR_RESERVE_NEW_MODE: ON
9277 10:05:20.154806 MR_CBT_SWITCH_FREQ: ON
9278 10:05:20.155226 =========================
9279 10:05:20.174506 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9280 10:05:20.177722 dram_init: ddr_geometry: 2
9281 10:05:20.196512 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9282 10:05:20.199513 dram_init: dram init end (result: 0)
9283 10:05:20.206252 DRAM-K: Full calibration passed in 24676 msecs
9284 10:05:20.209234 MRC: failed to locate region type 0.
9285 10:05:20.209662 DRAM rank0 size:0x100000000,
9286 10:05:20.212392 DRAM rank1 size=0x100000000
9287 10:05:20.222672 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9288 10:05:20.229260 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9289 10:05:20.235459 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9290 10:05:20.245364 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9291 10:05:20.245804 DRAM rank0 size:0x100000000,
9292 10:05:20.248597 DRAM rank1 size=0x100000000
9293 10:05:20.249027 CBMEM:
9294 10:05:20.252268 IMD: root @ 0xfffff000 254 entries.
9295 10:05:20.255597 IMD: root @ 0xffffec00 62 entries.
9296 10:05:20.258713 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9297 10:05:20.265270 WARNING: RO_VPD is uninitialized or empty.
9298 10:05:20.269002 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9299 10:05:20.276134 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9300 10:05:20.288962 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9301 10:05:20.300080 BS: romstage times (exec / console): total (unknown) / 24158 ms
9302 10:05:20.300555
9303 10:05:20.301006
9304 10:05:20.310028 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9305 10:05:20.313398 ARM64: Exception handlers installed.
9306 10:05:20.316732 ARM64: Testing exception
9307 10:05:20.320037 ARM64: Done test exception
9308 10:05:20.320475 Enumerating buses...
9309 10:05:20.323501 Show all devs... Before device enumeration.
9310 10:05:20.326768 Root Device: enabled 1
9311 10:05:20.329990 CPU_CLUSTER: 0: enabled 1
9312 10:05:20.330586 CPU: 00: enabled 1
9313 10:05:20.333122 Compare with tree...
9314 10:05:20.333704 Root Device: enabled 1
9315 10:05:20.336416 CPU_CLUSTER: 0: enabled 1
9316 10:05:20.339596 CPU: 00: enabled 1
9317 10:05:20.340055 Root Device scanning...
9318 10:05:20.343080 scan_static_bus for Root Device
9319 10:05:20.346304 CPU_CLUSTER: 0 enabled
9320 10:05:20.349683 scan_static_bus for Root Device done
9321 10:05:20.353198 scan_bus: bus Root Device finished in 8 msecs
9322 10:05:20.353626 done
9323 10:05:20.359371 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9324 10:05:20.363010 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9325 10:05:20.369559 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9326 10:05:20.372791 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9327 10:05:20.376818 Allocating resources...
9328 10:05:20.379679 Reading resources...
9329 10:05:20.382469 Root Device read_resources bus 0 link: 0
9330 10:05:20.386249 DRAM rank0 size:0x100000000,
9331 10:05:20.386680 DRAM rank1 size=0x100000000
9332 10:05:20.392509 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9333 10:05:20.393010 CPU: 00 missing read_resources
9334 10:05:20.399879 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9335 10:05:20.403141 Root Device read_resources bus 0 link: 0 done
9336 10:05:20.406168 Done reading resources.
9337 10:05:20.408861 Show resources in subtree (Root Device)...After reading.
9338 10:05:20.412597 Root Device child on link 0 CPU_CLUSTER: 0
9339 10:05:20.415353 CPU_CLUSTER: 0 child on link 0 CPU: 00
9340 10:05:20.425586 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9341 10:05:20.426090 CPU: 00
9342 10:05:20.431831 Root Device assign_resources, bus 0 link: 0
9343 10:05:20.435357 CPU_CLUSTER: 0 missing set_resources
9344 10:05:20.438449 Root Device assign_resources, bus 0 link: 0 done
9345 10:05:20.438891 Done setting resources.
9346 10:05:20.445813 Show resources in subtree (Root Device)...After assigning values.
9347 10:05:20.448642 Root Device child on link 0 CPU_CLUSTER: 0
9348 10:05:20.451849 CPU_CLUSTER: 0 child on link 0 CPU: 00
9349 10:05:20.462122 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9350 10:05:20.462566 CPU: 00
9351 10:05:20.465528 Done allocating resources.
9352 10:05:20.471412 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9353 10:05:20.471845 Enabling resources...
9354 10:05:20.475149 done.
9355 10:05:20.478040 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9356 10:05:20.481255 Initializing devices...
9357 10:05:20.481640 Root Device init
9358 10:05:20.484853 init hardware done!
9359 10:05:20.485281 0x00000018: ctrlr->caps
9360 10:05:20.488431 52.000 MHz: ctrlr->f_max
9361 10:05:20.491212 0.400 MHz: ctrlr->f_min
9362 10:05:20.491581 0x40ff8080: ctrlr->voltages
9363 10:05:20.494657 sclk: 390625
9364 10:05:20.495001 Bus Width = 1
9365 10:05:20.497763 sclk: 390625
9366 10:05:20.498075 Bus Width = 1
9367 10:05:20.501653 Early init status = 3
9368 10:05:20.504836 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9369 10:05:20.507963 in-header: 03 fc 00 00 01 00 00 00
9370 10:05:20.511251 in-data: 00
9371 10:05:20.514487 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9372 10:05:20.519347 in-header: 03 fd 00 00 00 00 00 00
9373 10:05:20.523274 in-data:
9374 10:05:20.526076 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9375 10:05:20.530511 in-header: 03 fc 00 00 01 00 00 00
9376 10:05:20.533971 in-data: 00
9377 10:05:20.536754 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9378 10:05:20.542344 in-header: 03 fd 00 00 00 00 00 00
9379 10:05:20.545716 in-data:
9380 10:05:20.548899 [SSUSB] Setting up USB HOST controller...
9381 10:05:20.552455 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9382 10:05:20.555445 [SSUSB] phy power-on done.
9383 10:05:20.558687 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9384 10:05:20.565641 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9385 10:05:20.568779 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9386 10:05:20.575379 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9387 10:05:20.581815 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9388 10:05:20.588557 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9389 10:05:20.594979 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9390 10:05:20.601548 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9391 10:05:20.604957 SPM: binary array size = 0x9dc
9392 10:05:20.608250 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9393 10:05:20.614974 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9394 10:05:20.621736 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9395 10:05:20.627766 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9396 10:05:20.631188 configure_display: Starting display init
9397 10:05:20.666340 anx7625_power_on_init: Init interface.
9398 10:05:20.669719 anx7625_disable_pd_protocol: Disabled PD feature.
9399 10:05:20.672217 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9400 10:05:20.700808 anx7625_start_dp_work: Secure OCM version=00
9401 10:05:20.703668 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9402 10:05:20.718394 sp_tx_get_edid_block: EDID Block = 1
9403 10:05:21.077611 Extracted contents:
9404 10:05:21.078740 header: 00 ff ff ff ff ff ff 00
9405 10:05:21.079164 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9406 10:05:21.079629 version: 01 04
9407 10:05:21.080262 basic params: 95 1f 11 78 0a
9408 10:05:21.080833 chroma info: 76 90 94 55 54 90 27 21 50 54
9409 10:05:21.081380 established: 00 00 00
9410 10:05:21.081835 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9411 10:05:21.082379 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9412 10:05:21.082828 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9413 10:05:21.083433 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9414 10:05:21.083779 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9415 10:05:21.084267 extensions: 00
9416 10:05:21.084767 checksum: fb
9417 10:05:21.085086
9418 10:05:21.085639 Manufacturer: IVO Model 57d Serial Number 0
9419 10:05:21.085965 Made week 0 of 2020
9420 10:05:21.086374 EDID version: 1.4
9421 10:05:21.086785 Digital display
9422 10:05:21.087104 6 bits per primary color channel
9423 10:05:21.087493 DisplayPort interface
9424 10:05:21.087817 Maximum image size: 31 cm x 17 cm
9425 10:05:21.088262 Gamma: 220%
9426 10:05:21.088710 Check DPMS levels
9427 10:05:21.089066 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9428 10:05:21.089465 First detailed timing is preferred timing
9429 10:05:21.089980 Established timings supported:
9430 10:05:21.090525 Standard timings supported:
9431 10:05:21.091068 Detailed timings
9432 10:05:21.091603 Hex of detail: 383680a07038204018303c0035ae10000019
9433 10:05:21.092109 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9434 10:05:21.092627 0780 0798 07c8 0820 hborder 0
9435 10:05:21.093141 0438 043b 0447 0458 vborder 0
9436 10:05:21.093660 -hsync -vsync
9437 10:05:21.094164 Did detailed timing
9438 10:05:21.094758 Hex of detail: 000000000000000000000000000000000000
9439 10:05:21.095307 Manufacturer-specified data, tag 0
9440 10:05:21.095763 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9441 10:05:21.096203 ASCII string: InfoVision
9442 10:05:21.096774 Hex of detail: 000000fe00523134304e574635205248200a
9443 10:05:21.097111 ASCII string: R140NWF5 RH
9444 10:05:21.097561 Checksum
9445 10:05:21.098074 Checksum: 0xfb (valid)
9446 10:05:21.098609 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9447 10:05:21.099116 DSI data_rate: 832800000 bps
9448 10:05:21.099662 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9449 10:05:21.100126 anx7625_parse_edid: pixelclock(138800).
9450 10:05:21.100667 hactive(1920), hsync(48), hfp(24), hbp(88)
9451 10:05:21.101001 vactive(1080), vsync(12), vfp(3), vbp(17)
9452 10:05:21.101346 anx7625_dsi_config: config dsi.
9453 10:05:21.101648 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9454 10:05:21.101994 anx7625_dsi_config: success to config DSI
9455 10:05:21.102440 anx7625_dp_start: MIPI phy setup OK.
9456 10:05:21.102959 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9457 10:05:21.103419 mtk_ddp_mode_set invalid vrefresh 60
9458 10:05:21.103884 main_disp_path_setup
9459 10:05:21.104250 ovl_layer_smi_id_en
9460 10:05:21.104580 ovl_layer_smi_id_en
9461 10:05:21.104941 ccorr_config
9462 10:05:21.105258 aal_config
9463 10:05:21.105650 gamma_config
9464 10:05:21.106022 postmask_config
9465 10:05:21.106526 dither_config
9466 10:05:21.107016 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9467 10:05:21.107510 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9468 10:05:21.108062 Root Device init finished in 554 msecs
9469 10:05:21.108575 CPU_CLUSTER: 0 init
9470 10:05:21.108923 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9471 10:05:21.109219 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9472 10:05:21.109537 APU_MBOX 0x190000b0 = 0x10001
9473 10:05:21.109791 APU_MBOX 0x190001b0 = 0x10001
9474 10:05:21.110158 APU_MBOX 0x190005b0 = 0x10001
9475 10:05:21.110507 APU_MBOX 0x190006b0 = 0x10001
9476 10:05:21.110864 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9477 10:05:21.111295 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9478 10:05:21.111656 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9479 10:05:21.111982 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9480 10:05:21.112686 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9481 10:05:21.122135 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9482 10:05:21.125324 CPU_CLUSTER: 0 init finished in 81 msecs
9483 10:05:21.128289 Devices initialized
9484 10:05:21.131486 Show all devs... After init.
9485 10:05:21.131664 Root Device: enabled 1
9486 10:05:21.135087 CPU_CLUSTER: 0: enabled 1
9487 10:05:21.138254 CPU: 00: enabled 1
9488 10:05:21.141752 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9489 10:05:21.144456 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9490 10:05:21.147657 ELOG: NV offset 0x57f000 size 0x1000
9491 10:05:21.154560 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9492 10:05:21.161367 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9493 10:05:21.164846 ELOG: Event(17) added with size 13 at 2023-06-10 10:05:21 UTC
9494 10:05:21.171329 out: cmd=0x121: 03 db 21 01 00 00 00 00
9495 10:05:21.174247 in-header: 03 87 00 00 2c 00 00 00
9496 10:05:21.184358 in-data: d8 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9497 10:05:21.190790 ELOG: Event(A1) added with size 10 at 2023-06-10 10:05:21 UTC
9498 10:05:21.197138 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9499 10:05:21.204040 ELOG: Event(A0) added with size 9 at 2023-06-10 10:05:21 UTC
9500 10:05:21.207414 elog_add_boot_reason: Logged dev mode boot
9501 10:05:21.214164 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9502 10:05:21.214250 Finalize devices...
9503 10:05:21.217109 Devices finalized
9504 10:05:21.220955 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9505 10:05:21.223764 Writing coreboot table at 0xffe64000
9506 10:05:21.226942 0. 000000000010a000-0000000000113fff: RAMSTAGE
9507 10:05:21.233626 1. 0000000040000000-00000000400fffff: RAM
9508 10:05:21.237395 2. 0000000040100000-000000004032afff: RAMSTAGE
9509 10:05:21.240450 3. 000000004032b000-00000000545fffff: RAM
9510 10:05:21.244071 4. 0000000054600000-000000005465ffff: BL31
9511 10:05:21.247225 5. 0000000054660000-00000000ffe63fff: RAM
9512 10:05:21.253823 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9513 10:05:21.256824 7. 0000000100000000-000000023fffffff: RAM
9514 10:05:21.260253 Passing 5 GPIOs to payload:
9515 10:05:21.263429 NAME | PORT | POLARITY | VALUE
9516 10:05:21.270393 EC in RW | 0x000000aa | low | undefined
9517 10:05:21.273745 EC interrupt | 0x00000005 | low | undefined
9518 10:05:21.277047 TPM interrupt | 0x000000ab | high | undefined
9519 10:05:21.283387 SD card detect | 0x00000011 | high | undefined
9520 10:05:21.286478 speaker enable | 0x00000093 | high | undefined
9521 10:05:21.289754 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9522 10:05:21.293841 in-header: 03 f9 00 00 02 00 00 00
9523 10:05:21.297152 in-data: 02 00
9524 10:05:21.300262 ADC[4]: Raw value=901552 ID=7
9525 10:05:21.303629 ADC[3]: Raw value=213652 ID=1
9526 10:05:21.303726 RAM Code: 0x71
9527 10:05:21.306787 ADC[6]: Raw value=75036 ID=0
9528 10:05:21.310750 ADC[5]: Raw value=213652 ID=1
9529 10:05:21.310832 SKU Code: 0x1
9530 10:05:21.317073 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a169
9531 10:05:21.317169 coreboot table: 964 bytes.
9532 10:05:21.320447 IMD ROOT 0. 0xfffff000 0x00001000
9533 10:05:21.323422 IMD SMALL 1. 0xffffe000 0x00001000
9534 10:05:21.326724 RO MCACHE 2. 0xffffc000 0x00001104
9535 10:05:21.330197 CONSOLE 3. 0xfff7c000 0x00080000
9536 10:05:21.333400 FMAP 4. 0xfff7b000 0x00000452
9537 10:05:21.337046 TIME STAMP 5. 0xfff7a000 0x00000910
9538 10:05:21.340682 VBOOT WORK 6. 0xfff66000 0x00014000
9539 10:05:21.343410 RAMOOPS 7. 0xffe66000 0x00100000
9540 10:05:21.346825 COREBOOT 8. 0xffe64000 0x00002000
9541 10:05:21.349765 IMD small region:
9542 10:05:21.353184 IMD ROOT 0. 0xffffec00 0x00000400
9543 10:05:21.356471 VPD 1. 0xffffeba0 0x0000004c
9544 10:05:21.359676 MMC STATUS 2. 0xffffeb80 0x00000004
9545 10:05:21.366625 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9546 10:05:21.366729 Probing TPM: done!
9547 10:05:21.369620 Connected to device vid:did:rid of 1ae0:0028:00
9548 10:05:21.381582 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9549 10:05:21.384344 Initialized TPM device CR50 revision 0
9550 10:05:21.387876 Checking cr50 for pending updates
9551 10:05:21.391791 Reading cr50 TPM mode
9552 10:05:21.400462 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9553 10:05:21.407051 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9554 10:05:21.447220 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9555 10:05:21.450562 Checking segment from ROM address 0x40100000
9556 10:05:21.453485 Checking segment from ROM address 0x4010001c
9557 10:05:21.460136 Loading segment from ROM address 0x40100000
9558 10:05:21.460261 code (compression=0)
9559 10:05:21.470574 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9560 10:05:21.476905 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9561 10:05:21.476988 it's not compressed!
9562 10:05:21.483545 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9563 10:05:21.487289 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9564 10:05:21.507664 Loading segment from ROM address 0x4010001c
9565 10:05:21.507748 Entry Point 0x80000000
9566 10:05:21.510730 Loaded segments
9567 10:05:21.514311 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9568 10:05:21.521092 Jumping to boot code at 0x80000000(0xffe64000)
9569 10:05:21.527611 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9570 10:05:21.534072 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9571 10:05:21.541901 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9572 10:05:21.545545 Checking segment from ROM address 0x40100000
9573 10:05:21.548256 Checking segment from ROM address 0x4010001c
9574 10:05:21.555206 Loading segment from ROM address 0x40100000
9575 10:05:21.555304 code (compression=1)
9576 10:05:21.561950 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9577 10:05:21.572141 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9578 10:05:21.572600 using LZMA
9579 10:05:21.580787 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9580 10:05:21.587363 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9581 10:05:21.590760 Loading segment from ROM address 0x4010001c
9582 10:05:21.591182 Entry Point 0x54601000
9583 10:05:21.593981 Loaded segments
9584 10:05:21.597098 NOTICE: MT8192 bl31_setup
9585 10:05:21.604622 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9586 10:05:21.607511 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9587 10:05:21.611125 WARNING: region 0:
9588 10:05:21.614168 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9589 10:05:21.614591 WARNING: region 1:
9590 10:05:21.620496 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9591 10:05:21.624050 WARNING: region 2:
9592 10:05:21.627383 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9593 10:05:21.630706 WARNING: region 3:
9594 10:05:21.634284 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9595 10:05:21.637336 WARNING: region 4:
9596 10:05:21.644177 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9597 10:05:21.644668 WARNING: region 5:
9598 10:05:21.647315 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9599 10:05:21.650677 WARNING: region 6:
9600 10:05:21.653901 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9601 10:05:21.657598 WARNING: region 7:
9602 10:05:21.661067 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9603 10:05:21.667408 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9604 10:05:21.670936 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9605 10:05:21.673706 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9606 10:05:21.680603 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9607 10:05:21.683629 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9608 10:05:21.690400 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9609 10:05:21.693768 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9610 10:05:21.696792 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9611 10:05:21.703651 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9612 10:05:21.707131 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9613 10:05:21.710418 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9614 10:05:21.716753 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9615 10:05:21.720088 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9616 10:05:21.726581 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9617 10:05:21.729965 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9618 10:05:21.733182 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9619 10:05:21.739969 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9620 10:05:21.743922 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9621 10:05:21.746517 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9622 10:05:21.753208 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9623 10:05:21.756743 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9624 10:05:21.763232 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9625 10:05:21.766921 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9626 10:05:21.769950 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9627 10:05:21.776452 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9628 10:05:21.779807 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9629 10:05:21.786607 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9630 10:05:21.789899 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9631 10:05:21.793336 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9632 10:05:21.800196 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9633 10:05:21.803583 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9634 10:05:21.809761 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9635 10:05:21.813554 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9636 10:05:21.816511 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9637 10:05:21.819951 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9638 10:05:21.826721 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9639 10:05:21.829939 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9640 10:05:21.832999 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9641 10:05:21.836573 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9642 10:05:21.843376 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9643 10:05:21.846446 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9644 10:05:21.849876 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9645 10:05:21.853452 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9646 10:05:21.859818 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9647 10:05:21.863036 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9648 10:05:21.867415 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9649 10:05:21.869760 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9650 10:05:21.876326 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9651 10:05:21.880033 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9652 10:05:21.886694 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9653 10:05:21.889660 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9654 10:05:21.892919 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9655 10:05:21.899764 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9656 10:05:21.903114 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9657 10:05:21.909405 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9658 10:05:21.912761 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9659 10:05:21.919334 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9660 10:05:21.922588 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9661 10:05:21.926146 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9662 10:05:21.933029 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9663 10:05:21.936582 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9664 10:05:21.943124 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9665 10:05:21.945752 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9666 10:05:21.952223 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9667 10:05:21.955500 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9668 10:05:21.962117 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9669 10:05:21.965683 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9670 10:05:21.972595 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9671 10:05:21.975364 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9672 10:05:21.978660 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9673 10:05:21.985598 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9674 10:05:21.988849 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9675 10:05:21.996012 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9676 10:05:21.999216 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9677 10:05:22.005489 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9678 10:05:22.009161 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9679 10:05:22.012189 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9680 10:05:22.018771 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9681 10:05:22.021934 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9682 10:05:22.028604 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9683 10:05:22.031833 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9684 10:05:22.038611 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9685 10:05:22.041998 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9686 10:05:22.048487 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9687 10:05:22.051691 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9688 10:05:22.054974 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9689 10:05:22.062209 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9690 10:05:22.065492 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9691 10:05:22.071655 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9692 10:05:22.075103 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9693 10:05:22.081691 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9694 10:05:22.085316 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9695 10:05:22.088211 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9696 10:05:22.095046 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9697 10:05:22.098416 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9698 10:05:22.105442 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9699 10:05:22.108544 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9700 10:05:22.112085 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9701 10:05:22.118791 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9702 10:05:22.121606 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9703 10:05:22.125043 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9704 10:05:22.128610 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9705 10:05:22.135395 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9706 10:05:22.138115 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9707 10:05:22.144736 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9708 10:05:22.147950 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9709 10:05:22.151586 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9710 10:05:22.158194 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9711 10:05:22.161337 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9712 10:05:22.168217 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9713 10:05:22.171599 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9714 10:05:22.174838 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9715 10:05:22.181267 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9716 10:05:22.184536 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9717 10:05:22.191371 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9718 10:05:22.194271 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9719 10:05:22.197557 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9720 10:05:22.204274 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9721 10:05:22.207633 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9722 10:05:22.211135 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9723 10:05:22.217407 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9724 10:05:22.221147 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9725 10:05:22.224052 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9726 10:05:22.227740 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9727 10:05:22.233849 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9728 10:05:22.237139 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9729 10:05:22.243687 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9730 10:05:22.247228 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9731 10:05:22.250327 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9732 10:05:22.256954 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9733 10:05:22.260330 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9734 10:05:22.266393 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9735 10:05:22.270083 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9736 10:05:22.273282 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9737 10:05:22.280256 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9738 10:05:22.283430 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9739 10:05:22.290126 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9740 10:05:22.293380 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9741 10:05:22.296330 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9742 10:05:22.303422 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9743 10:05:22.306260 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9744 10:05:22.312762 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9745 10:05:22.316480 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9746 10:05:22.319406 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9747 10:05:22.326389 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9748 10:05:22.329477 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9749 10:05:22.332703 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9750 10:05:22.339450 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9751 10:05:22.342450 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9752 10:05:22.349241 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9753 10:05:22.352537 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9754 10:05:22.355901 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9755 10:05:22.362408 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9756 10:05:22.366242 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9757 10:05:22.372258 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9758 10:05:22.375696 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9759 10:05:22.382326 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9760 10:05:22.385652 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9761 10:05:22.389298 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9762 10:05:22.395498 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9763 10:05:22.398880 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9764 10:05:22.405197 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9765 10:05:22.408507 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9766 10:05:22.411907 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9767 10:05:22.418420 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9768 10:05:22.421775 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9769 10:05:22.428014 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9770 10:05:22.431719 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9771 10:05:22.434519 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9772 10:05:22.441096 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9773 10:05:22.445047 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9774 10:05:22.451321 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9775 10:05:22.454534 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9776 10:05:22.457822 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9777 10:05:22.464421 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9778 10:05:22.467662 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9779 10:05:22.474357 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9780 10:05:22.477226 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9781 10:05:22.480603 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9782 10:05:22.487341 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9783 10:05:22.490540 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9784 10:05:22.497457 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9785 10:05:22.500823 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9786 10:05:22.503502 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9787 10:05:22.510683 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9788 10:05:22.513479 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9789 10:05:22.520306 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9790 10:05:22.523213 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9791 10:05:22.529741 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9792 10:05:22.533209 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9793 10:05:22.537274 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9794 10:05:22.543622 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9795 10:05:22.546629 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9796 10:05:22.552874 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9797 10:05:22.556247 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9798 10:05:22.562932 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9799 10:05:22.566324 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9800 10:05:22.569969 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9801 10:05:22.576102 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9802 10:05:22.579379 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9803 10:05:22.585978 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9804 10:05:22.588944 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9805 10:05:22.595709 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9806 10:05:22.599292 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9807 10:05:22.602675 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9808 10:05:22.608765 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9809 10:05:22.612331 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9810 10:05:22.618635 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9811 10:05:22.622121 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9812 10:05:22.629022 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9813 10:05:22.632282 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9814 10:05:22.635693 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9815 10:05:22.641886 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9816 10:05:22.645389 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9817 10:05:22.651786 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9818 10:05:22.655058 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9819 10:05:22.661574 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9820 10:05:22.665306 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9821 10:05:22.668396 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9822 10:05:22.674499 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9823 10:05:22.677848 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9824 10:05:22.684681 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9825 10:05:22.687857 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9826 10:05:22.694541 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9827 10:05:22.698200 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9828 10:05:22.701342 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9829 10:05:22.707946 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9830 10:05:22.711325 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9831 10:05:22.717788 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9832 10:05:22.720880 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9833 10:05:22.724358 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9834 10:05:22.727589 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9835 10:05:22.734209 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9836 10:05:22.737484 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9837 10:05:22.740590 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9838 10:05:22.748316 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9839 10:05:22.750927 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9840 10:05:22.753731 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9841 10:05:22.760445 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9842 10:05:22.763815 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9843 10:05:22.766975 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9844 10:05:22.773760 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9845 10:05:22.777223 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9846 10:05:22.783946 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9847 10:05:22.786906 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9848 10:05:22.790579 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9849 10:05:22.797192 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9850 10:05:22.800206 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9851 10:05:22.803747 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9852 10:05:22.810164 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9853 10:05:22.813466 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9854 10:05:22.819983 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9855 10:05:22.823208 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9856 10:05:22.826561 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9857 10:05:22.833130 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9858 10:05:22.836439 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9859 10:05:22.839514 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9860 10:05:22.846121 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9861 10:05:22.849320 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9862 10:05:22.856313 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9863 10:05:22.859943 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9864 10:05:22.863156 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9865 10:05:22.869348 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9866 10:05:22.872507 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9867 10:05:22.875788 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9868 10:05:22.882473 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9869 10:05:22.886086 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9870 10:05:22.892795 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9871 10:05:22.896057 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9872 10:05:22.899375 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9873 10:05:22.902533 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9874 10:05:22.909437 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9875 10:05:22.912414 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9876 10:05:22.915835 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9877 10:05:22.919256 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9878 10:05:22.926199 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9879 10:05:22.928617 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9880 10:05:22.931892 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9881 10:05:22.935345 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9882 10:05:22.941883 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9883 10:05:22.945311 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9884 10:05:22.948703 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9885 10:05:22.955116 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9886 10:05:22.958339 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9887 10:05:22.965091 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9888 10:05:22.968382 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9889 10:05:22.971597 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9890 10:05:22.978411 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9891 10:05:22.982196 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9892 10:05:22.988113 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9893 10:05:22.991342 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9894 10:05:22.994910 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9895 10:05:23.001786 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9896 10:05:23.005022 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9897 10:05:23.011441 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9898 10:05:23.015124 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9899 10:05:23.021405 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9900 10:05:23.024896 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9901 10:05:23.028016 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9902 10:05:23.035327 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9903 10:05:23.037964 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9904 10:05:23.044704 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9905 10:05:23.047996 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9906 10:05:23.051209 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9907 10:05:23.058063 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9908 10:05:23.061056 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9909 10:05:23.067586 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9910 10:05:23.071077 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9911 10:05:23.074210 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9912 10:05:23.080942 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9913 10:05:23.084134 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9914 10:05:23.091057 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9915 10:05:23.094140 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9916 10:05:23.097586 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9917 10:05:23.104289 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9918 10:05:23.107740 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9919 10:05:23.114035 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9920 10:05:23.117220 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9921 10:05:23.123522 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9922 10:05:23.127017 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9923 10:05:23.133752 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9924 10:05:23.137139 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9925 10:05:23.140326 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9926 10:05:23.147020 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9927 10:05:23.150310 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9928 10:05:23.156662 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9929 10:05:23.160057 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9930 10:05:23.163431 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9931 10:05:23.169910 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9932 10:05:23.173064 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9933 10:05:23.179956 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9934 10:05:23.183405 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9935 10:05:23.186187 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9936 10:05:23.193137 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9937 10:05:23.196345 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9938 10:05:23.203041 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9939 10:05:23.206053 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9940 10:05:23.212505 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9941 10:05:23.216015 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9942 10:05:23.219901 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9943 10:05:23.225790 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9944 10:05:23.229952 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9945 10:05:23.236349 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9946 10:05:23.239258 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9947 10:05:23.245821 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9948 10:05:23.249671 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9949 10:05:23.252418 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9950 10:05:23.259513 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9951 10:05:23.262716 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9952 10:05:23.269205 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9953 10:05:23.272757 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9954 10:05:23.275547 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9955 10:05:23.282515 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9956 10:05:23.285541 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9957 10:05:23.292315 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9958 10:05:23.295395 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9959 10:05:23.302200 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9960 10:05:23.305681 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9961 10:05:23.308879 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9962 10:05:23.315284 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9963 10:05:23.318767 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9964 10:05:23.325249 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9965 10:05:23.328349 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9966 10:05:23.335619 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9967 10:05:23.338260 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9968 10:05:23.341822 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9969 10:05:23.348386 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9970 10:05:23.351427 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9971 10:05:23.358122 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9972 10:05:23.361254 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9973 10:05:23.368237 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9974 10:05:23.370988 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9975 10:05:23.377709 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9976 10:05:23.381308 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9977 10:05:23.384398 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9978 10:05:23.391065 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9979 10:05:23.394219 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9980 10:05:23.400902 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9981 10:05:23.404287 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9982 10:05:23.410563 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9983 10:05:23.413997 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9984 10:05:23.420607 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9985 10:05:23.424274 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9986 10:05:23.427091 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9987 10:05:23.433810 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9988 10:05:23.437047 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9989 10:05:23.444018 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9990 10:05:23.446889 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9991 10:05:23.453714 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9992 10:05:23.456707 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9993 10:05:23.463322 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9994 10:05:23.467192 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9995 10:05:23.470477 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9996 10:05:23.476977 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9997 10:05:23.479976 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9998 10:05:23.486438 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9999 10:05:23.490254 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
10000 10:05:23.496469 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
10001 10:05:23.499712 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
10002 10:05:23.506463 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
10003 10:05:23.509559 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
10004 10:05:23.513254 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
10005 10:05:23.519712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
10006 10:05:23.523047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
10007 10:05:23.529231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
10008 10:05:23.532786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
10009 10:05:23.539271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
10010 10:05:23.542571 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
10011 10:05:23.549502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
10012 10:05:23.552422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
10013 10:05:23.559647 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10014 10:05:23.562767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10015 10:05:23.569191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10016 10:05:23.572243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10017 10:05:23.578777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10018 10:05:23.582286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10019 10:05:23.589149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10020 10:05:23.592041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10021 10:05:23.598710 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10022 10:05:23.602381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10023 10:05:23.605242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10024 10:05:23.612071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10025 10:05:23.618401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10026 10:05:23.621726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10027 10:05:23.628251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10028 10:05:23.631808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10029 10:05:23.638527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10030 10:05:23.641461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10031 10:05:23.648096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10032 10:05:23.651580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10033 10:05:23.658380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10034 10:05:23.662320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10035 10:05:23.669111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10036 10:05:23.671645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10037 10:05:23.675383 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10038 10:05:23.678039 INFO: [APUAPC] vio 0
10039 10:05:23.684720 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10040 10:05:23.687819 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10041 10:05:23.691088 INFO: [APUAPC] D0_APC_0: 0x400510
10042 10:05:23.694716 INFO: [APUAPC] D0_APC_1: 0x0
10043 10:05:23.697849 INFO: [APUAPC] D0_APC_2: 0x1540
10044 10:05:23.700986 INFO: [APUAPC] D0_APC_3: 0x0
10045 10:05:23.704146 INFO: [APUAPC] D1_APC_0: 0xffffffff
10046 10:05:23.708191 INFO: [APUAPC] D1_APC_1: 0xffffffff
10047 10:05:23.711007 INFO: [APUAPC] D1_APC_2: 0x3fffff
10048 10:05:23.714223 INFO: [APUAPC] D1_APC_3: 0x0
10049 10:05:23.717575 INFO: [APUAPC] D2_APC_0: 0xffffffff
10050 10:05:23.721027 INFO: [APUAPC] D2_APC_1: 0xffffffff
10051 10:05:23.724354 INFO: [APUAPC] D2_APC_2: 0x3fffff
10052 10:05:23.727344 INFO: [APUAPC] D2_APC_3: 0x0
10053 10:05:23.730722 INFO: [APUAPC] D3_APC_0: 0xffffffff
10054 10:05:23.734214 INFO: [APUAPC] D3_APC_1: 0xffffffff
10055 10:05:23.737461 INFO: [APUAPC] D3_APC_2: 0x3fffff
10056 10:05:23.740720 INFO: [APUAPC] D3_APC_3: 0x0
10057 10:05:23.743636 INFO: [APUAPC] D4_APC_0: 0xffffffff
10058 10:05:23.747312 INFO: [APUAPC] D4_APC_1: 0xffffffff
10059 10:05:23.750812 INFO: [APUAPC] D4_APC_2: 0x3fffff
10060 10:05:23.751237 INFO: [APUAPC] D4_APC_3: 0x0
10061 10:05:23.754293 INFO: [APUAPC] D5_APC_0: 0xffffffff
10062 10:05:23.760628 INFO: [APUAPC] D5_APC_1: 0xffffffff
10063 10:05:23.763492 INFO: [APUAPC] D5_APC_2: 0x3fffff
10064 10:05:23.763962 INFO: [APUAPC] D5_APC_3: 0x0
10065 10:05:23.767717 INFO: [APUAPC] D6_APC_0: 0xffffffff
10066 10:05:23.771135 INFO: [APUAPC] D6_APC_1: 0xffffffff
10067 10:05:23.773627 INFO: [APUAPC] D6_APC_2: 0x3fffff
10068 10:05:23.776840 INFO: [APUAPC] D6_APC_3: 0x0
10069 10:05:23.780838 INFO: [APUAPC] D7_APC_0: 0xffffffff
10070 10:05:23.783434 INFO: [APUAPC] D7_APC_1: 0xffffffff
10071 10:05:23.787011 INFO: [APUAPC] D7_APC_2: 0x3fffff
10072 10:05:23.790456 INFO: [APUAPC] D7_APC_3: 0x0
10073 10:05:23.793820 INFO: [APUAPC] D8_APC_0: 0xffffffff
10074 10:05:23.797071 INFO: [APUAPC] D8_APC_1: 0xffffffff
10075 10:05:23.800322 INFO: [APUAPC] D8_APC_2: 0x3fffff
10076 10:05:23.803340 INFO: [APUAPC] D8_APC_3: 0x0
10077 10:05:23.807086 INFO: [APUAPC] D9_APC_0: 0xffffffff
10078 10:05:23.810419 INFO: [APUAPC] D9_APC_1: 0xffffffff
10079 10:05:23.813461 INFO: [APUAPC] D9_APC_2: 0x3fffff
10080 10:05:23.816406 INFO: [APUAPC] D9_APC_3: 0x0
10081 10:05:23.820026 INFO: [APUAPC] D10_APC_0: 0xffffffff
10082 10:05:23.823449 INFO: [APUAPC] D10_APC_1: 0xffffffff
10083 10:05:23.826753 INFO: [APUAPC] D10_APC_2: 0x3fffff
10084 10:05:23.830018 INFO: [APUAPC] D10_APC_3: 0x0
10085 10:05:23.833157 INFO: [APUAPC] D11_APC_0: 0xffffffff
10086 10:05:23.836767 INFO: [APUAPC] D11_APC_1: 0xffffffff
10087 10:05:23.839724 INFO: [APUAPC] D11_APC_2: 0x3fffff
10088 10:05:23.843006 INFO: [APUAPC] D11_APC_3: 0x0
10089 10:05:23.846306 INFO: [APUAPC] D12_APC_0: 0xffffffff
10090 10:05:23.849793 INFO: [APUAPC] D12_APC_1: 0xffffffff
10091 10:05:23.852942 INFO: [APUAPC] D12_APC_2: 0x3fffff
10092 10:05:23.856550 INFO: [APUAPC] D12_APC_3: 0x0
10093 10:05:23.859581 INFO: [APUAPC] D13_APC_0: 0xffffffff
10094 10:05:23.863021 INFO: [APUAPC] D13_APC_1: 0xffffffff
10095 10:05:23.866364 INFO: [APUAPC] D13_APC_2: 0x3fffff
10096 10:05:23.869665 INFO: [APUAPC] D13_APC_3: 0x0
10097 10:05:23.872898 INFO: [APUAPC] D14_APC_0: 0xffffffff
10098 10:05:23.876241 INFO: [APUAPC] D14_APC_1: 0xffffffff
10099 10:05:23.879726 INFO: [APUAPC] D14_APC_2: 0x3fffff
10100 10:05:23.882819 INFO: [APUAPC] D14_APC_3: 0x0
10101 10:05:23.885989 INFO: [APUAPC] D15_APC_0: 0xffffffff
10102 10:05:23.889325 INFO: [APUAPC] D15_APC_1: 0xffffffff
10103 10:05:23.892556 INFO: [APUAPC] D15_APC_2: 0x3fffff
10104 10:05:23.896010 INFO: [APUAPC] D15_APC_3: 0x0
10105 10:05:23.899297 INFO: [APUAPC] APC_CON: 0x4
10106 10:05:23.902578 INFO: [NOCDAPC] D0_APC_0: 0x0
10107 10:05:23.905769 INFO: [NOCDAPC] D0_APC_1: 0x0
10108 10:05:23.909063 INFO: [NOCDAPC] D1_APC_0: 0x0
10109 10:05:23.912420 INFO: [NOCDAPC] D1_APC_1: 0xfff
10110 10:05:23.916018 INFO: [NOCDAPC] D2_APC_0: 0x0
10111 10:05:23.919385 INFO: [NOCDAPC] D2_APC_1: 0xfff
10112 10:05:23.922577 INFO: [NOCDAPC] D3_APC_0: 0x0
10113 10:05:23.923109 INFO: [NOCDAPC] D3_APC_1: 0xfff
10114 10:05:23.926323 INFO: [NOCDAPC] D4_APC_0: 0x0
10115 10:05:23.928958 INFO: [NOCDAPC] D4_APC_1: 0xfff
10116 10:05:23.932503 INFO: [NOCDAPC] D5_APC_0: 0x0
10117 10:05:23.935773 INFO: [NOCDAPC] D5_APC_1: 0xfff
10118 10:05:23.939008 INFO: [NOCDAPC] D6_APC_0: 0x0
10119 10:05:23.942367 INFO: [NOCDAPC] D6_APC_1: 0xfff
10120 10:05:23.945431 INFO: [NOCDAPC] D7_APC_0: 0x0
10121 10:05:23.948804 INFO: [NOCDAPC] D7_APC_1: 0xfff
10122 10:05:23.952077 INFO: [NOCDAPC] D8_APC_0: 0x0
10123 10:05:23.955217 INFO: [NOCDAPC] D8_APC_1: 0xfff
10124 10:05:23.958696 INFO: [NOCDAPC] D9_APC_0: 0x0
10125 10:05:23.959123 INFO: [NOCDAPC] D9_APC_1: 0xfff
10126 10:05:23.961674 INFO: [NOCDAPC] D10_APC_0: 0x0
10127 10:05:23.965393 INFO: [NOCDAPC] D10_APC_1: 0xfff
10128 10:05:23.968269 INFO: [NOCDAPC] D11_APC_0: 0x0
10129 10:05:23.971857 INFO: [NOCDAPC] D11_APC_1: 0xfff
10130 10:05:23.974983 INFO: [NOCDAPC] D12_APC_0: 0x0
10131 10:05:23.978549 INFO: [NOCDAPC] D12_APC_1: 0xfff
10132 10:05:23.981769 INFO: [NOCDAPC] D13_APC_0: 0x0
10133 10:05:23.985446 INFO: [NOCDAPC] D13_APC_1: 0xfff
10134 10:05:23.988639 INFO: [NOCDAPC] D14_APC_0: 0x0
10135 10:05:23.991645 INFO: [NOCDAPC] D14_APC_1: 0xfff
10136 10:05:23.994988 INFO: [NOCDAPC] D15_APC_0: 0x0
10137 10:05:23.997965 INFO: [NOCDAPC] D15_APC_1: 0xfff
10138 10:05:24.001205 INFO: [NOCDAPC] APC_CON: 0x4
10139 10:05:24.004997 INFO: [APUAPC] set_apusys_apc done
10140 10:05:24.008124 INFO: [DEVAPC] devapc_init done
10141 10:05:24.011238 INFO: GICv3 without legacy support detected.
10142 10:05:24.015131 INFO: ARM GICv3 driver initialized in EL3
10143 10:05:24.017763 INFO: Maximum SPI INTID supported: 639
10144 10:05:24.021326 INFO: BL31: Initializing runtime services
10145 10:05:24.028372 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10146 10:05:24.030916 INFO: SPM: enable CPC mode
10147 10:05:24.037666 INFO: mcdi ready for mcusys-off-idle and system suspend
10148 10:05:24.041059 INFO: BL31: Preparing for EL3 exit to normal world
10149 10:05:24.044483 INFO: Entry point address = 0x80000000
10150 10:05:24.047682 INFO: SPSR = 0x8
10151 10:05:24.052203
10152 10:05:24.052660
10153 10:05:24.053002
10154 10:05:24.055750 Starting depthcharge on Spherion...
10155 10:05:24.056176
10156 10:05:24.056548 Wipe memory regions:
10157 10:05:24.056883
10158 10:05:24.059124 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10159 10:05:24.059683 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10160 10:05:24.060139 Setting prompt string to ['asurada:']
10161 10:05:24.060582 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10162 10:05:24.061254 [0x00000040000000, 0x00000054600000)
10163 10:05:24.181073
10164 10:05:24.181575 [0x00000054660000, 0x00000080000000)
10165 10:05:24.442261
10166 10:05:24.442792 [0x000000821a7280, 0x000000ffe64000)
10167 10:05:25.186316
10168 10:05:25.186464 [0x00000100000000, 0x00000240000000)
10169 10:05:27.076485
10170 10:05:27.079149 Initializing XHCI USB controller at 0x11200000.
10171 10:05:28.060846
10172 10:05:28.061005 R8152: Initializing
10173 10:05:28.061091
10174 10:05:28.064171 Version 9 (ocp_data = 6010)
10175 10:05:28.064260
10176 10:05:28.067466 R8152: Done initializing
10177 10:05:28.067556
10178 10:05:28.067627 Adding net device
10179 10:05:28.589706
10180 10:05:28.592646 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10181 10:05:28.592732
10182 10:05:28.592798
10183 10:05:28.592860
10184 10:05:28.593143 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10186 10:05:28.693515 asurada: tftpboot 192.168.201.1 10670685/tftp-deploy-bg4sbiaz/kernel/image.itb 10670685/tftp-deploy-bg4sbiaz/kernel/cmdline
10187 10:05:28.693769 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10188 10:05:28.693988 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10189 10:05:28.698475 tftpboot 192.168.201.1 10670685/tftp-deploy-bg4sbiaz/kernel/image.itp-deploy-bg4sbiaz/kernel/cmdline
10190 10:05:28.698683
10191 10:05:28.698873 Waiting for link
10192 10:05:28.900555
10193 10:05:28.900702 done.
10194 10:05:28.900775
10195 10:05:28.900841 MAC: f4:f5:e8:50:de:0a
10196 10:05:28.900905
10197 10:05:28.904047 Sending DHCP discover... done.
10198 10:05:28.904144
10199 10:05:28.906885 Waiting for reply... done.
10200 10:05:28.906983
10201 10:05:28.910609 Sending DHCP request... done.
10202 10:05:28.910713
10203 10:05:28.916976 Waiting for reply... done.
10204 10:05:28.917089
10205 10:05:28.917179 My ip is 192.168.201.14
10206 10:05:28.917262
10207 10:05:28.919327 The DHCP server ip is 192.168.201.1
10208 10:05:28.919451
10209 10:05:28.926214 TFTP server IP predefined by user: 192.168.201.1
10210 10:05:28.926353
10211 10:05:28.932585 Bootfile predefined by user: 10670685/tftp-deploy-bg4sbiaz/kernel/image.itb
10212 10:05:28.932747
10213 10:05:28.936273 Sending tftp read request... done.
10214 10:05:28.936449
10215 10:05:28.940041 Waiting for the transfer...
10216 10:05:28.940124
10217 10:05:29.177261 00000000 ################################################################
10218 10:05:29.177406
10219 10:05:29.410129 00080000 ################################################################
10220 10:05:29.410265
10221 10:05:29.640185 00100000 ################################################################
10222 10:05:29.640333
10223 10:05:29.867037 00180000 ################################################################
10224 10:05:29.867187
10225 10:05:30.095363 00200000 ################################################################
10226 10:05:30.095510
10227 10:05:30.322875 00280000 ################################################################
10228 10:05:30.323022
10229 10:05:30.560733 00300000 ################################################################
10230 10:05:30.560866
10231 10:05:30.785129 00380000 ################################################################
10232 10:05:30.785272
10233 10:05:31.010398 00400000 ################################################################
10234 10:05:31.010561
10235 10:05:31.249415 00480000 ################################################################
10236 10:05:31.249544
10237 10:05:31.486499 00500000 ################################################################
10238 10:05:31.486633
10239 10:05:31.711923 00580000 ################################################################
10240 10:05:31.712066
10241 10:05:31.937984 00600000 ################################################################
10242 10:05:31.938123
10243 10:05:32.164671 00680000 ################################################################
10244 10:05:32.164801
10245 10:05:32.390182 00700000 ################################################################
10246 10:05:32.390323
10247 10:05:32.615418 00780000 ################################################################
10248 10:05:32.615560
10249 10:05:32.863350 00800000 ################################################################
10250 10:05:32.863492
10251 10:05:33.098360 00880000 ################################################################
10252 10:05:33.098512
10253 10:05:33.329651 00900000 ################################################################
10254 10:05:33.329807
10255 10:05:33.554554 00980000 ################################################################
10256 10:05:33.554708
10257 10:05:33.786671 00a00000 ################################################################
10258 10:05:33.786846
10259 10:05:34.010919 00a80000 ################################################################
10260 10:05:34.011086
10261 10:05:34.235850 00b00000 ################################################################
10262 10:05:34.235995
10263 10:05:34.460956 00b80000 ################################################################
10264 10:05:34.461094
10265 10:05:34.686093 00c00000 ################################################################
10266 10:05:34.686235
10267 10:05:34.911305 00c80000 ################################################################
10268 10:05:34.911443
10269 10:05:35.136272 00d00000 ################################################################
10270 10:05:35.136411
10271 10:05:35.366125 00d80000 ################################################################
10272 10:05:35.366272
10273 10:05:35.590601 00e00000 ################################################################
10274 10:05:35.590742
10275 10:05:35.816421 00e80000 ################################################################
10276 10:05:35.816599
10277 10:05:36.040849 00f00000 ################################################################
10278 10:05:36.040991
10279 10:05:36.266976 00f80000 ################################################################
10280 10:05:36.267123
10281 10:05:36.492486 01000000 ################################################################
10282 10:05:36.492684
10283 10:05:36.718628 01080000 ################################################################
10284 10:05:36.718767
10285 10:05:36.944935 01100000 ################################################################
10286 10:05:36.945064
10287 10:05:37.170389 01180000 ################################################################
10288 10:05:37.170541
10289 10:05:37.397242 01200000 ################################################################
10290 10:05:37.397372
10291 10:05:37.623024 01280000 ################################################################
10292 10:05:37.623185
10293 10:05:37.845294 01300000 ################################################################
10294 10:05:37.845425
10295 10:05:38.057315 01380000 ################################################################
10296 10:05:38.057447
10297 10:05:38.278019 01400000 ################################################################
10298 10:05:38.278158
10299 10:05:38.489301 01480000 ################################################################
10300 10:05:38.489457
10301 10:05:38.711599 01500000 ################################################################
10302 10:05:38.711736
10303 10:05:38.937541 01580000 ################################################################
10304 10:05:38.937674
10305 10:05:39.163309 01600000 ################################################################
10306 10:05:39.163442
10307 10:05:39.390112 01680000 ################################################################
10308 10:05:39.390246
10309 10:05:39.616978 01700000 ################################################################
10310 10:05:39.617109
10311 10:05:39.845791 01780000 ################################################################
10312 10:05:39.845921
10313 10:05:40.076781 01800000 ################################################################
10314 10:05:40.076911
10315 10:05:40.303254 01880000 ################################################################
10316 10:05:40.303381
10317 10:05:40.529077 01900000 ################################################################
10318 10:05:40.529206
10319 10:05:40.755084 01980000 ################################################################
10320 10:05:40.755215
10321 10:05:40.993448 01a00000 ################################################################ done.
10322 10:05:40.993579
10323 10:05:40.997549 The bootfile was 27782598 bytes long.
10324 10:05:40.997640
10325 10:05:41.000155 Sending tftp read request... done.
10326 10:05:41.000251
10327 10:05:41.003164 Waiting for the transfer...
10328 10:05:41.003336
10329 10:05:41.003411 00000000 # done.
10330 10:05:41.003484
10331 10:05:41.013407 Command line loaded dynamically from TFTP file: 10670685/tftp-deploy-bg4sbiaz/kernel/cmdline
10332 10:05:41.013602
10333 10:05:41.032956 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10670685/extract-nfsrootfs-fbgtgk4p,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10334 10:05:41.033227
10335 10:05:41.033389 Loading FIT.
10336 10:05:41.033540
10337 10:05:41.036608 Image ramdisk-1 has 17646324 bytes.
10338 10:05:41.036863
10339 10:05:41.040031 Image fdt-1 has 46924 bytes.
10340 10:05:41.040322
10341 10:05:41.043248 Image kernel-1 has 10087317 bytes.
10342 10:05:41.043582
10343 10:05:41.049914 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10344 10:05:41.053051
10345 10:05:41.069559 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10346 10:05:41.070160
10347 10:05:41.072944 Choosing best match conf-1 for compat google,spherion-rev2.
10348 10:05:41.078910
10349 10:05:41.083013 Connected to device vid:did:rid of 1ae0:0028:00
10350 10:05:41.090133
10351 10:05:41.093562 tpm_get_response: command 0x17b, return code 0x0
10352 10:05:41.094036
10353 10:05:41.096595 ec_init: CrosEC protocol v3 supported (256, 248)
10354 10:05:41.101172
10355 10:05:41.105200 tpm_cleanup: add release locality here.
10356 10:05:41.105773
10357 10:05:41.106148 Shutting down all USB controllers.
10358 10:05:41.108097
10359 10:05:41.108715 Removing current net device
10360 10:05:41.109103
10361 10:05:41.115105 Exiting depthcharge with code 4 at timestamp: 46535379
10362 10:05:41.115675
10363 10:05:41.118155 LZMA decompressing kernel-1 to 0x821a6718
10364 10:05:41.118728
10365 10:05:41.121002 LZMA decompressing kernel-1 to 0x40000000
10366 10:05:42.389090
10367 10:05:42.389663 jumping to kernel
10368 10:05:42.391105 end: 2.2.4 bootloader-commands (duration 00:00:18) [common]
10369 10:05:42.391716 start: 2.2.5 auto-login-action (timeout 00:04:07) [common]
10370 10:05:42.392291 Setting prompt string to ['Linux version [0-9]']
10371 10:05:42.392735 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10372 10:05:42.393124 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10373 10:05:42.470867
10374 10:05:42.474663 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10375 10:05:42.478414 start: 2.2.5.1 login-action (timeout 00:04:07) [common]
10376 10:05:42.478981 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10377 10:05:42.479432 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10378 10:05:42.479840 Using line separator: #'\n'#
10379 10:05:42.480184 No login prompt set.
10380 10:05:42.480553 Parsing kernel messages
10381 10:05:42.480874 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10382 10:05:42.481438 [login-action] Waiting for messages, (timeout 00:04:07)
10383 10:05:42.496718 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j19381-arm64-gcc-10-defconfig-arm64-chromebook-d6qsg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023
10384 10:05:42.500250 [ 0.000000] random: crng init done
10385 10:05:42.503577 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10386 10:05:42.507189 [ 0.000000] efi: UEFI not found.
10387 10:05:42.516613 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10388 10:05:42.523237 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10389 10:05:42.533330 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10390 10:05:42.543103 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10391 10:05:42.550299 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10392 10:05:42.557198 [ 0.000000] printk: bootconsole [mtk8250] enabled
10393 10:05:42.563367 [ 0.000000] NUMA: No NUMA configuration found
10394 10:05:42.569934 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10395 10:05:42.573189 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10396 10:05:42.576837 [ 0.000000] Zone ranges:
10397 10:05:42.582985 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10398 10:05:42.586250 [ 0.000000] DMA32 empty
10399 10:05:42.592552 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10400 10:05:42.595801 [ 0.000000] Movable zone start for each node
10401 10:05:42.599623 [ 0.000000] Early memory node ranges
10402 10:05:42.606057 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10403 10:05:42.613135 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10404 10:05:42.620748 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10405 10:05:42.625991 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10406 10:05:42.629414 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10407 10:05:42.638797 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10408 10:05:42.694595 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10409 10:05:42.701391 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10410 10:05:42.707922 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10411 10:05:42.711464 [ 0.000000] psci: probing for conduit method from DT.
10412 10:05:42.717901 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10413 10:05:42.721570 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10414 10:05:42.727532 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10415 10:05:42.731380 [ 0.000000] psci: SMC Calling Convention v1.2
10416 10:05:42.737921 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10417 10:05:42.741425 [ 0.000000] Detected VIPT I-cache on CPU0
10418 10:05:42.747564 [ 0.000000] CPU features: detected: GIC system register CPU interface
10419 10:05:42.754365 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10420 10:05:42.760723 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10421 10:05:42.767539 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10422 10:05:42.774313 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10423 10:05:42.784089 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10424 10:05:42.787165 [ 0.000000] alternatives: applying boot alternatives
10425 10:05:42.794111 [ 0.000000] Fallback order for Node 0: 0
10426 10:05:42.800199 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10427 10:05:42.803423 [ 0.000000] Policy zone: Normal
10428 10:05:42.823523 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10670685/extract-nfsrootfs-fbgtgk4p,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10429 10:05:42.833430 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10430 10:05:42.845433 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10431 10:05:42.854922 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10432 10:05:42.861506 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10433 10:05:42.865180 <6>[ 0.000000] software IO TLB: area num 8.
10434 10:05:42.921601 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10435 10:05:43.071066 <6>[ 0.000000] Memory: 7955708K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397060K reserved, 32768K cma-reserved)
10436 10:05:43.077336 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10437 10:05:43.084408 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10438 10:05:43.087590 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10439 10:05:43.094206 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10440 10:05:43.100691 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10441 10:05:43.103598 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10442 10:05:43.113795 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10443 10:05:43.120492 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10444 10:05:43.126782 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10445 10:05:43.133425 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10446 10:05:43.137134 <6>[ 0.000000] GICv3: 608 SPIs implemented
10447 10:05:43.140281 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10448 10:05:43.147252 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10449 10:05:43.150014 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10450 10:05:43.156386 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10451 10:05:43.170440 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10452 10:05:43.182988 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10453 10:05:43.189426 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10454 10:05:43.197550 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10455 10:05:43.210721 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10456 10:05:43.217035 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10457 10:05:43.223913 <6>[ 0.009176] Console: colour dummy device 80x25
10458 10:05:43.233639 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10459 10:05:43.240418 <6>[ 0.024346] pid_max: default: 32768 minimum: 301
10460 10:05:43.243614 <6>[ 0.029219] LSM: Security Framework initializing
10461 10:05:43.250295 <6>[ 0.034189] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10462 10:05:43.259957 <6>[ 0.042003] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10463 10:05:43.270377 <6>[ 0.051424] cblist_init_generic: Setting adjustable number of callback queues.
10464 10:05:43.274054 <6>[ 0.058923] cblist_init_generic: Setting shift to 3 and lim to 1.
10465 10:05:43.280066 <6>[ 0.065302] cblist_init_generic: Setting shift to 3 and lim to 1.
10466 10:05:43.287110 <6>[ 0.071707] rcu: Hierarchical SRCU implementation.
10467 10:05:43.293471 <6>[ 0.076734] rcu: Max phase no-delay instances is 1000.
10468 10:05:43.299434 <6>[ 0.083747] EFI services will not be available.
10469 10:05:43.303293 <6>[ 0.088719] smp: Bringing up secondary CPUs ...
10470 10:05:43.310807 <6>[ 0.093799] Detected VIPT I-cache on CPU1
10471 10:05:43.317683 <6>[ 0.093871] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10472 10:05:43.324296 <6>[ 0.093901] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10473 10:05:43.327222 <6>[ 0.094229] Detected VIPT I-cache on CPU2
10474 10:05:43.337339 <6>[ 0.094276] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10475 10:05:43.344061 <6>[ 0.094292] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10476 10:05:43.347518 <6>[ 0.094550] Detected VIPT I-cache on CPU3
10477 10:05:43.353907 <6>[ 0.094596] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10478 10:05:43.360075 <6>[ 0.094610] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10479 10:05:43.363584 <6>[ 0.094913] CPU features: detected: Spectre-v4
10480 10:05:43.370149 <6>[ 0.094920] CPU features: detected: Spectre-BHB
10481 10:05:43.373645 <6>[ 0.094926] Detected PIPT I-cache on CPU4
10482 10:05:43.380172 <6>[ 0.094983] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10483 10:05:43.386409 <6>[ 0.094999] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10484 10:05:43.393163 <6>[ 0.095293] Detected PIPT I-cache on CPU5
10485 10:05:43.399490 <6>[ 0.095356] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10486 10:05:43.406796 <6>[ 0.095372] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10487 10:05:43.410291 <6>[ 0.095654] Detected PIPT I-cache on CPU6
10488 10:05:43.416197 <6>[ 0.095718] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10489 10:05:43.426392 <6>[ 0.095734] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10490 10:05:43.430381 <6>[ 0.096032] Detected PIPT I-cache on CPU7
10491 10:05:43.435799 <6>[ 0.096097] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10492 10:05:43.442345 <6>[ 0.096113] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10493 10:05:43.446038 <6>[ 0.096159] smp: Brought up 1 node, 8 CPUs
10494 10:05:43.452264 <6>[ 0.237349] SMP: Total of 8 processors activated.
10495 10:05:43.455726 <6>[ 0.242300] CPU features: detected: 32-bit EL0 Support
10496 10:05:43.465844 <6>[ 0.247697] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10497 10:05:43.472435 <6>[ 0.256497] CPU features: detected: Common not Private translations
10498 10:05:43.479025 <6>[ 0.262973] CPU features: detected: CRC32 instructions
10499 10:05:43.485730 <6>[ 0.268324] CPU features: detected: RCpc load-acquire (LDAPR)
10500 10:05:43.489033 <6>[ 0.274284] CPU features: detected: LSE atomic instructions
10501 10:05:43.495366 <6>[ 0.280101] CPU features: detected: Privileged Access Never
10502 10:05:43.501970 <6>[ 0.285880] CPU features: detected: RAS Extension Support
10503 10:05:43.508311 <6>[ 0.291489] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10504 10:05:43.511629 <6>[ 0.298754] CPU: All CPU(s) started at EL2
10505 10:05:43.518230 <6>[ 0.303071] alternatives: applying system-wide alternatives
10506 10:05:43.528723 <6>[ 0.313771] devtmpfs: initialized
10507 10:05:43.544238 <6>[ 0.322660] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10508 10:05:43.551366 <6>[ 0.332625] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10509 10:05:43.556870 <6>[ 0.340649] pinctrl core: initialized pinctrl subsystem
10510 10:05:43.560652 <6>[ 0.347323] DMI not present or invalid.
10511 10:05:43.566701 <6>[ 0.351730] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10512 10:05:43.576691 <6>[ 0.358608] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10513 10:05:43.583818 <6>[ 0.366186] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10514 10:05:43.593845 <6>[ 0.374395] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10515 10:05:43.597032 <6>[ 0.382637] audit: initializing netlink subsys (disabled)
10516 10:05:43.606516 <5>[ 0.388332] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10517 10:05:43.613168 <6>[ 0.389039] thermal_sys: Registered thermal governor 'step_wise'
10518 10:05:43.620556 <6>[ 0.396299] thermal_sys: Registered thermal governor 'power_allocator'
10519 10:05:43.622864 <6>[ 0.402556] cpuidle: using governor menu
10520 10:05:43.629391 <6>[ 0.413518] NET: Registered PF_QIPCRTR protocol family
10521 10:05:43.635981 <6>[ 0.419015] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10522 10:05:43.642724 <6>[ 0.426119] ASID allocator initialised with 32768 entries
10523 10:05:43.646308 <6>[ 0.432681] Serial: AMBA PL011 UART driver
10524 10:05:43.656015 <4>[ 0.441354] Trying to register duplicate clock ID: 134
10525 10:05:43.709865 <6>[ 0.498638] KASLR enabled
10526 10:05:43.724472 <6>[ 0.506474] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10527 10:05:43.730973 <6>[ 0.513487] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10528 10:05:43.737529 <6>[ 0.519978] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10529 10:05:43.744309 <6>[ 0.526983] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10530 10:05:43.750678 <6>[ 0.533470] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10531 10:05:43.757522 <6>[ 0.540477] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10532 10:05:43.764400 <6>[ 0.546964] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10533 10:05:43.770764 <6>[ 0.553966] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10534 10:05:43.773636 <6>[ 0.561436] ACPI: Interpreter disabled.
10535 10:05:43.782551 <6>[ 0.567865] iommu: Default domain type: Translated
10536 10:05:43.789345 <6>[ 0.572976] iommu: DMA domain TLB invalidation policy: strict mode
10537 10:05:43.792641 <5>[ 0.579644] SCSI subsystem initialized
10538 10:05:43.799358 <6>[ 0.583880] usbcore: registered new interface driver usbfs
10539 10:05:43.805795 <6>[ 0.589608] usbcore: registered new interface driver hub
10540 10:05:43.809109 <6>[ 0.595158] usbcore: registered new device driver usb
10541 10:05:43.815996 <6>[ 0.601259] pps_core: LinuxPPS API ver. 1 registered
10542 10:05:43.826691 <6>[ 0.606452] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10543 10:05:43.829313 <6>[ 0.615789] PTP clock support registered
10544 10:05:43.832971 <6>[ 0.620030] EDAC MC: Ver: 3.0.0
10545 10:05:43.839786 <6>[ 0.625213] FPGA manager framework
10546 10:05:43.846690 <6>[ 0.628888] Advanced Linux Sound Architecture Driver Initialized.
10547 10:05:43.849575 <6>[ 0.635661] vgaarb: loaded
10548 10:05:43.856322 <6>[ 0.638834] clocksource: Switched to clocksource arch_sys_counter
10549 10:05:43.859708 <5>[ 0.645285] VFS: Disk quotas dquot_6.6.0
10550 10:05:43.866299 <6>[ 0.649469] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10551 10:05:43.869518 <6>[ 0.656659] pnp: PnP ACPI: disabled
10552 10:05:43.878089 <6>[ 0.663288] NET: Registered PF_INET protocol family
10553 10:05:43.888154 <6>[ 0.668876] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10554 10:05:43.899684 <6>[ 0.681194] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10555 10:05:43.909168 <6>[ 0.690005] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10556 10:05:43.916142 <6>[ 0.697971] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10557 10:05:43.922910 <6>[ 0.706666] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10558 10:05:43.934658 <6>[ 0.716419] TCP: Hash tables configured (established 65536 bind 65536)
10559 10:05:43.941267 <6>[ 0.723281] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10560 10:05:43.948023 <6>[ 0.730480] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10561 10:05:43.954447 <6>[ 0.738178] NET: Registered PF_UNIX/PF_LOCAL protocol family
10562 10:05:43.960995 <6>[ 0.744341] RPC: Registered named UNIX socket transport module.
10563 10:05:43.964393 <6>[ 0.750493] RPC: Registered udp transport module.
10564 10:05:43.970737 <6>[ 0.755427] RPC: Registered tcp transport module.
10565 10:05:43.976991 <6>[ 0.760356] RPC: Registered tcp NFSv4.1 backchannel transport module.
10566 10:05:43.980255 <6>[ 0.767027] PCI: CLS 0 bytes, default 64
10567 10:05:43.984207 <6>[ 0.771413] Unpacking initramfs...
10568 10:05:44.001432 <6>[ 0.783401] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10569 10:05:44.011643 <6>[ 0.792054] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10570 10:05:44.014346 <6>[ 0.800900] kvm [1]: IPA Size Limit: 40 bits
10571 10:05:44.020967 <6>[ 0.805425] kvm [1]: GICv3: no GICV resource entry
10572 10:05:44.025395 <6>[ 0.810443] kvm [1]: disabling GICv2 emulation
10573 10:05:44.031095 <6>[ 0.815131] kvm [1]: GIC system register CPU interface enabled
10574 10:05:44.034434 <6>[ 0.821286] kvm [1]: vgic interrupt IRQ18
10575 10:05:44.042045 <6>[ 0.826932] kvm [1]: VHE mode initialized successfully
10576 10:05:44.048833 <5>[ 0.833319] Initialise system trusted keyrings
10577 10:05:44.055028 <6>[ 0.838136] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10578 10:05:44.062434 <6>[ 0.848144] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10579 10:05:44.069293 <5>[ 0.854536] NFS: Registering the id_resolver key type
10580 10:05:44.073127 <5>[ 0.859848] Key type id_resolver registered
10581 10:05:44.078980 <5>[ 0.864261] Key type id_legacy registered
10582 10:05:44.085600 <6>[ 0.868547] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10583 10:05:44.092718 <6>[ 0.875471] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10584 10:05:44.099780 <6>[ 0.883201] 9p: Installing v9fs 9p2000 file system support
10585 10:05:44.135302 <5>[ 0.920084] Key type asymmetric registered
10586 10:05:44.138397 <5>[ 0.924422] Asymmetric key parser 'x509' registered
10587 10:05:44.148170 <6>[ 0.929575] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10588 10:05:44.151010 <6>[ 0.937191] io scheduler mq-deadline registered
10589 10:05:44.154488 <6>[ 0.941968] io scheduler kyber registered
10590 10:05:44.173512 <6>[ 0.959003] EINJ: ACPI disabled.
10591 10:05:44.206312 <4>[ 0.984612] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10592 10:05:44.215575 <4>[ 0.995262] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10593 10:05:44.231118 <6>[ 1.015945] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10594 10:05:44.239492 <6>[ 1.023980] printk: console [ttyS0] disabled
10595 10:05:44.267049 <6>[ 1.048627] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10596 10:05:44.273725 <6>[ 1.058101] printk: console [ttyS0] enabled
10597 10:05:44.276121 <6>[ 1.058101] printk: console [ttyS0] enabled
10598 10:05:44.282857 <6>[ 1.066996] printk: bootconsole [mtk8250] disabled
10599 10:05:44.287170 <6>[ 1.066996] printk: bootconsole [mtk8250] disabled
10600 10:05:44.292823 <6>[ 1.078240] SuperH (H)SCI(F) driver initialized
10601 10:05:44.296048 <6>[ 1.083507] msm_serial: driver initialized
10602 10:05:44.310117 <6>[ 1.092459] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10603 10:05:44.320025 <6>[ 1.101006] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10604 10:05:44.326626 <6>[ 1.109549] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10605 10:05:44.337319 <6>[ 1.118176] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10606 10:05:44.347458 <6>[ 1.126882] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10607 10:05:44.353166 <6>[ 1.135596] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10608 10:05:44.363529 <6>[ 1.144138] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10609 10:05:44.370044 <6>[ 1.152949] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10610 10:05:44.379985 <6>[ 1.161492] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10611 10:05:44.391770 <6>[ 1.177025] loop: module loaded
10612 10:05:44.398844 <6>[ 1.182963] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10613 10:05:44.420941 <4>[ 1.206142] mtk-pmic-keys: Failed to locate of_node [id: -1]
10614 10:05:44.427574 <6>[ 1.212931] megasas: 07.719.03.00-rc1
10615 10:05:44.436842 <6>[ 1.222470] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10616 10:05:44.445213 <6>[ 1.230213] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10617 10:05:44.461442 <6>[ 1.246878] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10618 10:05:44.521937 <6>[ 1.300865] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10619 10:05:44.712062 <6>[ 1.497230] Freeing initrd memory: 17228K
10620 10:05:44.722338 <6>[ 1.507658] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10621 10:05:44.732904 <6>[ 1.518513] tun: Universal TUN/TAP device driver, 1.6
10622 10:05:44.736302 <6>[ 1.524564] thunder_xcv, ver 1.0
10623 10:05:44.739881 <6>[ 1.528067] thunder_bgx, ver 1.0
10624 10:05:44.743074 <6>[ 1.531564] nicpf, ver 1.0
10625 10:05:44.753244 <6>[ 1.535556] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10626 10:05:44.756573 <6>[ 1.543032] hns3: Copyright (c) 2017 Huawei Corporation.
10627 10:05:44.762952 <6>[ 1.548618] hclge is initializing
10628 10:05:44.766803 <6>[ 1.552199] e1000: Intel(R) PRO/1000 Network Driver
10629 10:05:44.773239 <6>[ 1.557328] e1000: Copyright (c) 1999-2006 Intel Corporation.
10630 10:05:44.779470 <6>[ 1.563343] e1000e: Intel(R) PRO/1000 Network Driver
10631 10:05:44.783336 <6>[ 1.568558] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10632 10:05:44.790122 <6>[ 1.574743] igb: Intel(R) Gigabit Ethernet Network Driver
10633 10:05:44.796630 <6>[ 1.580393] igb: Copyright (c) 2007-2014 Intel Corporation.
10634 10:05:44.803005 <6>[ 1.586227] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10635 10:05:44.809402 <6>[ 1.592745] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10636 10:05:44.812624 <6>[ 1.599204] sky2: driver version 1.30
10637 10:05:44.819930 <6>[ 1.604189] VFIO - User Level meta-driver version: 0.3
10638 10:05:44.826930 <6>[ 1.612381] usbcore: registered new interface driver usb-storage
10639 10:05:44.833548 <6>[ 1.618828] usbcore: registered new device driver onboard-usb-hub
10640 10:05:44.842452 <6>[ 1.627908] mt6397-rtc mt6359-rtc: registered as rtc0
10641 10:05:44.852451 <6>[ 1.633377] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-10T10:05:44 UTC (1686391544)
10642 10:05:44.856162 <6>[ 1.642961] i2c_dev: i2c /dev entries driver
10643 10:05:44.872936 <6>[ 1.654597] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10644 10:05:44.879584 <6>[ 1.664833] sdhci: Secure Digital Host Controller Interface driver
10645 10:05:44.886331 <6>[ 1.671272] sdhci: Copyright(c) Pierre Ossman
10646 10:05:44.892892 <6>[ 1.676661] Synopsys Designware Multimedia Card Interface Driver
10647 10:05:44.896104 <6>[ 1.683277] mmc0: CQHCI version 5.10
10648 10:05:44.902629 <6>[ 1.683809] sdhci-pltfm: SDHCI platform and OF driver helper
10649 10:05:44.909531 <6>[ 1.695152] ledtrig-cpu: registered to indicate activity on CPUs
10650 10:05:44.920321 <6>[ 1.702528] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10651 10:05:44.924017 <6>[ 1.709909] usbcore: registered new interface driver usbhid
10652 10:05:44.930706 <6>[ 1.715741] usbhid: USB HID core driver
10653 10:05:44.936875 <6>[ 1.719995] spi_master spi0: will run message pump with realtime priority
10654 10:05:44.986808 <6>[ 1.765583] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10655 10:05:44.996274 <6>[ 1.781803] mmc0: Command Queue Engine enabled
10656 10:05:45.009931 <6>[ 1.784302] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10657 10:05:45.016629 <6>[ 1.786537] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10658 10:05:45.023673 <6>[ 1.801533] cros-ec-spi spi0.0: Chrome EC device registered
10659 10:05:45.027023 <6>[ 1.807155] mmcblk0: mmc0:0001 DA4128 116 GiB
10660 10:05:45.041129 <6>[ 1.826988] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10661 10:05:45.051768 <6>[ 1.833898] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10662 10:05:45.058545 <6>[ 1.834464] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10663 10:05:45.061225 <6>[ 1.845298] NET: Registered PF_PACKET protocol family
10664 10:05:45.067785 <6>[ 1.849127] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10665 10:05:45.071424 <6>[ 1.853879] 9pnet: Installing 9P2000 support
10666 10:05:45.077632 <6>[ 1.859640] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10667 10:05:45.084681 <5>[ 1.863559] Key type dns_resolver registered
10668 10:05:45.088005 <6>[ 1.875250] registered taskstats version 1
10669 10:05:45.094661 <5>[ 1.879681] Loading compiled-in X.509 certificates
10670 10:05:45.127795 <4>[ 1.907008] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10671 10:05:45.138440 <4>[ 1.917760] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10672 10:05:45.147804 <3>[ 1.930515] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10673 10:05:45.160600 <6>[ 1.945938] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10674 10:05:45.167581 <6>[ 1.952757] xhci-mtk 11200000.usb: xHCI Host Controller
10675 10:05:45.173503 <6>[ 1.958255] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10676 10:05:45.184319 <6>[ 1.966112] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10677 10:05:45.190813 <6>[ 1.975567] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10678 10:05:45.197966 <6>[ 1.981667] xhci-mtk 11200000.usb: xHCI Host Controller
10679 10:05:45.203778 <6>[ 1.987262] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10680 10:05:45.210102 <6>[ 1.994934] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10681 10:05:45.216901 <6>[ 2.002821] hub 1-0:1.0: USB hub found
10682 10:05:45.220046 <6>[ 2.006863] hub 1-0:1.0: 1 port detected
10683 10:05:45.230200 <6>[ 2.011220] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10684 10:05:45.234088 <6>[ 2.020016] hub 2-0:1.0: USB hub found
10685 10:05:45.236711 <6>[ 2.024050] hub 2-0:1.0: 1 port detected
10686 10:05:45.245936 <6>[ 2.031258] mtk-msdc 11f70000.mmc: Got CD GPIO
10687 10:05:45.263155 <6>[ 2.045016] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10688 10:05:45.269102 <6>[ 2.053042] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10689 10:05:45.279067 <4>[ 2.061020] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10690 10:05:45.289294 <6>[ 2.070675] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10691 10:05:45.295591 <6>[ 2.078758] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10692 10:05:45.302907 <6>[ 2.086774] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10693 10:05:45.313169 <6>[ 2.094694] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10694 10:05:45.319243 <6>[ 2.102516] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10695 10:05:45.329382 <6>[ 2.110336] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10696 10:05:45.339041 <6>[ 2.120972] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10697 10:05:45.346033 <6>[ 2.129342] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10698 10:05:45.355642 <6>[ 2.137701] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10699 10:05:45.362502 <6>[ 2.146045] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10700 10:05:45.372113 <6>[ 2.154389] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10701 10:05:45.378543 <6>[ 2.162732] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10702 10:05:45.388853 <6>[ 2.171076] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10703 10:05:45.395450 <6>[ 2.179420] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10704 10:05:45.405547 <6>[ 2.187763] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10705 10:05:45.415707 <6>[ 2.196107] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10706 10:05:45.422881 <6>[ 2.204454] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10707 10:05:45.431781 <6>[ 2.212799] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10708 10:05:45.439539 <6>[ 2.221143] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10709 10:05:45.448565 <6>[ 2.229489] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10710 10:05:45.455303 <6>[ 2.237834] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10711 10:05:45.461697 <6>[ 2.246742] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10712 10:05:45.469140 <6>[ 2.254184] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10713 10:05:45.475589 <6>[ 2.261260] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10714 10:05:45.486042 <6>[ 2.268385] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10715 10:05:45.492738 <6>[ 2.275688] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10716 10:05:45.503209 <6>[ 2.282607] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10717 10:05:45.509073 <6>[ 2.291751] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10718 10:05:45.519450 <6>[ 2.300879] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10719 10:05:45.529265 <6>[ 2.310181] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10720 10:05:45.539478 <6>[ 2.319656] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10721 10:05:45.548617 <6>[ 2.329130] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10722 10:05:45.558646 <6>[ 2.338264] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10723 10:05:45.565199 <6>[ 2.347739] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10724 10:05:45.575135 <6>[ 2.356866] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10725 10:05:45.584881 <6>[ 2.366168] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10726 10:05:45.595076 <6>[ 2.376334] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10727 10:05:45.605937 <6>[ 2.387923] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10728 10:05:45.612354 <6>[ 2.398050] Trying to probe devices needed for running init ...
10729 10:05:45.652643 <6>[ 2.435111] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10730 10:05:45.807350 <6>[ 2.592378] hub 1-1:1.0: USB hub found
10731 10:05:45.810072 <6>[ 2.596798] hub 1-1:1.0: 4 ports detected
10732 10:05:45.933030 <6>[ 2.715134] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10733 10:05:45.957323 <6>[ 2.743064] hub 2-1:1.0: USB hub found
10734 10:05:45.960435 <6>[ 2.747473] hub 2-1:1.0: 3 ports detected
10735 10:05:46.132830 <6>[ 2.915133] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10736 10:05:46.263861 <6>[ 3.048974] hub 1-1.1:1.0: USB hub found
10737 10:05:46.266830 <6>[ 3.053264] hub 1-1.1:1.0: 4 ports detected
10738 10:05:46.381123 <6>[ 3.162884] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10739 10:05:46.513498 <6>[ 3.299178] hub 1-1.4:1.0: USB hub found
10740 10:05:46.516586 <6>[ 3.303830] hub 1-1.4:1.0: 2 ports detected
10741 10:05:46.592781 <6>[ 3.375107] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10742 10:05:46.780505 <6>[ 3.563108] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10743 10:05:46.865859 <3>[ 3.651320] usb 1-1.1.4: device descriptor read/64, error -32
10744 10:05:47.057407 <3>[ 3.843322] usb 1-1.1.4: device descriptor read/64, error -32
10745 10:05:47.252626 <6>[ 4.035105] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10746 10:05:47.440630 <6>[ 4.223106] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10747 10:05:47.525126 <3>[ 4.311200] usb 1-1.1.4: device descriptor read/64, error -32
10748 10:05:47.717542 <3>[ 4.503321] usb 1-1.1.4: device descriptor read/64, error -32
10749 10:05:47.829502 <6>[ 4.615673] usb 1-1.1-port4: attempt power cycle
10750 10:05:47.917142 <6>[ 4.699105] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10751 10:05:48.440349 <6>[ 5.223108] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10752 10:05:48.446571 <4>[ 5.230461] usb 1-1.1.4: Device not responding to setup address.
10753 10:05:48.657711 <4>[ 5.443373] usb 1-1.1.4: Device not responding to setup address.
10754 10:05:48.868851 <3>[ 5.654999] usb 1-1.1.4: device not accepting address 10, error -71
10755 10:05:48.956453 <6>[ 5.739003] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10756 10:05:48.962647 <4>[ 5.746449] usb 1-1.1.4: Device not responding to setup address.
10757 10:05:49.173155 <4>[ 5.959392] usb 1-1.1.4: Device not responding to setup address.
10758 10:05:49.385250 <3>[ 6.171095] usb 1-1.1.4: device not accepting address 11, error -71
10759 10:05:49.392032 <3>[ 6.178049] usb 1-1.1-port4: unable to enumerate USB device
10760 10:05:57.909192 <6>[ 14.699663] ALSA device list:
10761 10:05:57.915380 <6>[ 14.702921] No soundcards found.
10762 10:05:57.928370 <6>[ 14.715297] Freeing unused kernel memory: 8384K
10763 10:05:57.931115 <6>[ 14.720214] Run /init as init process
10764 10:05:57.941259 Loading, please wait...
10765 10:05:57.961457 Starting version 247.3-7+deb11u2
10766 10:05:58.280777 <6>[ 15.064567] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10767 10:05:58.295640 <6>[ 15.083207] remoteproc remoteproc0: scp is available
10768 10:05:58.305464 <4>[ 15.088783] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10769 10:05:58.312442 <6>[ 15.098700] remoteproc remoteproc0: powering up scp
10770 10:05:58.322983 <4>[ 15.103867] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10771 10:05:58.328439 <3>[ 15.113716] remoteproc remoteproc0: request_firmware failed: -2
10772 10:05:58.345484 <3>[ 15.129553] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10773 10:05:58.352144 <3>[ 15.137698] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10774 10:05:58.362315 <6>[ 15.139922] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10775 10:05:58.368829 <3>[ 15.145815] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10776 10:05:58.378376 <3>[ 15.155010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10777 10:05:58.385021 <3>[ 15.169682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10778 10:05:58.394703 <4>[ 15.174487] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10779 10:05:58.398393 <4>[ 15.174487] Fallback method does not support PEC.
10780 10:05:58.407934 <3>[ 15.177773] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10781 10:05:58.411762 <6>[ 15.193594] mc: Linux media interface: v0.10
10782 10:05:58.421458 <3>[ 15.199591] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10783 10:05:58.428017 <4>[ 15.202362] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10784 10:05:58.434573 <6>[ 15.204707] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10785 10:05:58.441159 <4>[ 15.211230] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10786 10:05:58.450828 <3>[ 15.212229] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10787 10:05:58.457476 <6>[ 15.219651] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10788 10:05:58.467629 <3>[ 15.227450] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10789 10:05:58.477440 <6>[ 15.234869] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10790 10:05:58.483946 <3>[ 15.243002] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 10:05:58.490643 <6>[ 15.243668] videodev: Linux video capture interface: v2.00
10792 10:05:58.494286 <6>[ 15.252293] usbcore: registered new interface driver r8152
10793 10:05:58.503985 <3>[ 15.259758] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10794 10:05:58.510908 <3>[ 15.296082] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10795 10:05:58.520394 <3>[ 15.304284] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10796 10:05:58.526855 <3>[ 15.312416] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10797 10:05:58.537010 <3>[ 15.320539] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10798 10:05:58.543254 <3>[ 15.328643] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10799 10:05:58.554143 <3>[ 15.336746] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10800 10:05:58.563642 <6>[ 15.344298] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10801 10:05:58.569661 <3>[ 15.344877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10802 10:05:58.579731 <6>[ 15.348827] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10803 10:05:58.589562 <6>[ 15.349197] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10804 10:05:58.596152 <6>[ 15.351112] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10805 10:05:58.603308 <6>[ 15.376168] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10806 10:05:58.609431 <6>[ 15.381910] usbcore: registered new interface driver cdc_ether
10807 10:05:58.615920 <6>[ 15.388664] pci_bus 0000:00: root bus resource [bus 00-ff]
10808 10:05:58.622714 <6>[ 15.402017] usbcore: registered new interface driver r8153_ecm
10809 10:05:58.629239 <6>[ 15.407393] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10810 10:05:58.638999 <6>[ 15.407401] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10811 10:05:58.642144 <6>[ 15.408343] Bluetooth: Core ver 2.22
10812 10:05:58.649251 <6>[ 15.408416] NET: Registered PF_BLUETOOTH protocol family
10813 10:05:58.652817 <6>[ 15.408420] Bluetooth: HCI device and connection manager initialized
10814 10:05:58.659193 <6>[ 15.408441] Bluetooth: HCI socket layer initialized
10815 10:05:58.665938 <6>[ 15.408447] Bluetooth: L2CAP socket layer initialized
10816 10:05:58.668986 <6>[ 15.408457] Bluetooth: SCO socket layer initialized
10817 10:05:58.675899 <6>[ 15.409086] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10818 10:05:58.689513 <6>[ 15.410498] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10819 10:05:58.696671 <6>[ 15.410628] usbcore: registered new interface driver uvcvideo
10820 10:05:58.702704 <6>[ 15.452485] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10821 10:05:58.709640 <6>[ 15.456998] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10822 10:05:58.713464 <6>[ 15.457604] usbcore: registered new interface driver btusb
10823 10:05:58.722851 <4>[ 15.458306] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10824 10:05:58.729760 <3>[ 15.458317] Bluetooth: hci0: Failed to load firmware file (-2)
10825 10:05:58.736264 <3>[ 15.458322] Bluetooth: hci0: Failed to set up firmware (-2)
10826 10:05:58.746165 <4>[ 15.458326] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10827 10:05:58.755844 <3>[ 15.466624] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10828 10:05:58.762397 <6>[ 15.469151] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10829 10:05:58.772626 <4>[ 15.470227] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10830 10:05:58.779220 <4>[ 15.470236] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10831 10:05:58.785959 <6>[ 15.482898] r8152 1-1.1.1:1.0 eth0: v1.12.13
10832 10:05:58.789794 <6>[ 15.487635] pci 0000:00:00.0: supports D1 D2
10833 10:05:58.795513 <6>[ 15.502559] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10834 10:05:58.805575 <3>[ 15.503585] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10835 10:05:58.812330 <6>[ 15.506077] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10836 10:05:58.818710 <6>[ 15.507856] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10837 10:05:58.825187 <6>[ 15.611921] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10838 10:05:58.831970 <6>[ 15.618218] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10839 10:05:58.841896 <6>[ 15.625750] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10840 10:05:58.848366 <6>[ 15.633239] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10841 10:05:58.851785 <6>[ 15.640823] pci 0000:01:00.0: supports D1 D2
10842 10:05:58.859000 <6>[ 15.645346] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10843 10:05:58.883182 <6>[ 15.667138] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10844 10:05:58.889693 <6>[ 15.674063] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10845 10:05:58.896136 <6>[ 15.682152] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10846 10:05:58.906388 <6>[ 15.690158] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10847 10:05:58.912804 <6>[ 15.698165] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10848 10:05:58.922865 <6>[ 15.706177] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10849 10:05:58.925568 <6>[ 15.714184] pci 0000:00:00.0: PCI bridge to [bus 01]
10850 10:05:58.935697 <6>[ 15.719405] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10851 10:05:58.942375 <6>[ 15.727570] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10852 10:05:58.948866 <6>[ 15.734796] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10853 10:05:58.955406 <6>[ 15.741629] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10854 10:05:58.972997 <5>[ 15.757329] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10855 10:05:58.992701 <5>[ 15.777100] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10856 10:05:58.999922 <4>[ 15.784014] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10857 10:05:59.006484 <6>[ 15.792905] cfg80211: failed to load regulatory.db
10858 10:05:59.050981 <6>[ 15.835311] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10859 10:05:59.057856 <6>[ 15.842829] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10860 10:05:59.081984 <6>[ 15.869507] mt7921e 0000:01:00.0: ASIC revision: 79610010
10861 10:05:59.190783 <4>[ 15.971152] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10862 10:05:59.193581 Begin: Loading essential drivers ... done.
10863 10:05:59.200026 Begin: Running /scripts/init-premount ... done.
10864 10:05:59.207480 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10865 10:05:59.216423 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10866 10:05:59.220349 Device /sys/class/net/enxf4f5e850de0a found
10867 10:05:59.220448 done.
10868 10:05:59.266868 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10869 10:05:59.312848 <4>[ 16.093413] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10870 10:05:59.431496 <4>[ 16.212765] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10871 10:05:59.548210 <4>[ 16.328618] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10872 10:05:59.663975 <4>[ 16.444680] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10873 10:05:59.779457 <4>[ 16.560615] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10874 10:05:59.895425 <4>[ 16.676534] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10875 10:06:00.011641 <4>[ 16.792553] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10876 10:06:00.127829 <4>[ 16.908433] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10877 10:06:00.243113 <4>[ 17.024354] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10878 10:06:00.345792 IP-Config: no response after 2 secs - giving up
10879 10:06:00.352226 <3>[ 17.138578] mt7921e 0000:01:00.0: hardware init failed
10880 10:06:00.389978 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mt<6>[ 17.175486] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10881 10:06:00.390196 u 1500 DHCP
10882 10:06:01.487188 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10883 10:06:01.493833 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10884 10:06:01.500727 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10885 10:06:01.507481 host : mt8192-asurada-spherion-r0-cbg-9
10886 10:06:01.513789 domain : lava-rack
10887 10:06:01.520319 rootserver: 192.168.201.1 rootpath:
10888 10:06:01.520450 filename :
10889 10:06:01.534903 done.
10890 10:06:01.542303 Begin: Running /scripts/nfs-bottom ... done.
10891 10:06:01.560615 Begin: Running /scripts/init-bottom ... done.
10892 10:06:02.663066 <6>[ 19.451349] NET: Registered PF_INET6 protocol family
10893 10:06:02.670080 <6>[ 19.458317] Segment Routing with IPv6
10894 10:06:02.673372 <6>[ 19.462278] In-situ OAM (IOAM) with IPv6
10895 10:06:02.784563 <30>[ 19.553214] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10896 10:06:02.787985 <30>[ 19.576981] systemd[1]: Detected architecture arm64.
10897 10:06:02.808374
10898 10:06:02.811594 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10899 10:06:02.811682
10900 10:06:02.829176 <30>[ 19.617490] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10901 10:06:03.337506 <30>[ 20.122088] systemd[1]: Queued start job for default target Graphical Interface.
10902 10:06:03.356398 <30>[ 20.144208] systemd[1]: Created slice system-getty.slice.
10903 10:06:03.362820 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10904 10:06:03.379807 <30>[ 20.167698] systemd[1]: Created slice system-modprobe.slice.
10905 10:06:03.386221 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10906 10:06:03.407684 <30>[ 20.192255] systemd[1]: Created slice system-serial\x2dgetty.slice.
10907 10:06:03.413892 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10908 10:06:03.427820 <30>[ 20.215602] systemd[1]: Created slice User and Session Slice.
10909 10:06:03.434173 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10910 10:06:03.455177 <30>[ 20.239688] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10911 10:06:03.464683 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10912 10:06:03.482476 <30>[ 20.267267] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10913 10:06:03.489240 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10914 10:06:03.509484 <30>[ 20.291249] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10915 10:06:03.516244 <30>[ 20.303404] systemd[1]: Reached target Local Encrypted Volumes.
10916 10:06:03.522849 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10917 10:06:03.539073 <30>[ 20.327341] systemd[1]: Reached target Paths.
10918 10:06:03.542318 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10919 10:06:03.559246 <30>[ 20.347419] systemd[1]: Reached target Remote File Systems.
10920 10:06:03.566024 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10921 10:06:03.583128 <30>[ 20.371164] systemd[1]: Reached target Slices.
10922 10:06:03.589566 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10923 10:06:03.603144 <30>[ 20.391172] systemd[1]: Reached target Swap.
10924 10:06:03.606628 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10925 10:06:03.626750 <30>[ 20.411474] systemd[1]: Listening on initctl Compatibility Named Pipe.
10926 10:06:03.633271 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10927 10:06:03.639728 <30>[ 20.426955] systemd[1]: Listening on Journal Audit Socket.
10928 10:06:03.646465 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10929 10:06:03.659980 <30>[ 20.447968] systemd[1]: Listening on Journal Socket (/dev/log).
10930 10:06:03.666211 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10931 10:06:03.683604 <30>[ 20.471849] systemd[1]: Listening on Journal Socket.
10932 10:06:03.690689 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10933 10:06:03.707362 <30>[ 20.492336] systemd[1]: Listening on Network Service Netlink Socket.
10934 10:06:03.714134 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10935 10:06:03.729224 <30>[ 20.516518] systemd[1]: Listening on udev Control Socket.
10936 10:06:03.734992 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10937 10:06:03.751214 <30>[ 20.539134] systemd[1]: Listening on udev Kernel Socket.
10938 10:06:03.758455 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10939 10:06:03.790982 <30>[ 20.579180] systemd[1]: Mounting Huge Pages File System...
10940 10:06:03.797416 Mounting [0;1;39mHuge Pages File System[0m...
10941 10:06:03.812964 <30>[ 20.601308] systemd[1]: Mounting POSIX Message Queue File System...
10942 10:06:03.820106 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10943 10:06:03.838051 <30>[ 20.625670] systemd[1]: Mounting Kernel Debug File System...
10944 10:06:03.844172 Mounting [0;1;39mKernel Debug File System[0m...
10945 10:06:03.862599 <30>[ 20.647478] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10946 10:06:03.906669 <30>[ 20.691498] systemd[1]: Starting Create list of static device nodes for the current kernel...
10947 10:06:03.913113 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10948 10:06:03.933276 <30>[ 20.721474] systemd[1]: Starting Load Kernel Module configfs...
10949 10:06:03.939640 Starting [0;1;39mLoad Kernel Module configfs[0m...
10950 10:06:03.957197 <30>[ 20.745434] systemd[1]: Starting Load Kernel Module drm...
10951 10:06:03.963416 Starting [0;1;39mLoad Kernel Module drm[0m...
10952 10:06:03.982224 <30>[ 20.769680] systemd[1]: Starting Load Kernel Module fuse...
10953 10:06:03.988441 Starting [0;1;39mLoad Kernel Module fuse[0m...
10954 10:06:04.023477 <30>[ 20.807850] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10955 10:06:04.029308 <6>[ 20.808283] fuse: init (API version 7.37)
10956 10:06:04.036410 <30>[ 20.824251] systemd[1]: Starting Journal Service...
10957 10:06:04.039462 Starting [0;1;39mJournal Service[0m...
10958 10:06:04.079897 <30>[ 20.867852] systemd[1]: Starting Load Kernel Modules...
10959 10:06:04.086483 Starting [0;1;39mLoad Kernel Modules[0m...
10960 10:06:04.104909 <30>[ 20.889897] systemd[1]: Starting Remount Root and Kernel File Systems...
10961 10:06:04.112016 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10962 10:06:04.130159 <30>[ 20.918418] systemd[1]: Starting Coldplug All udev Devices...
10963 10:06:04.136666 Starting [0;1;39mColdplug All udev Devices[0m...
10964 10:06:04.155426 <30>[ 20.943251] systemd[1]: Mounted Huge Pages File System.
10965 10:06:04.162458 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10966 10:06:04.175354 <30>[ 20.963480] systemd[1]: Mounted POSIX Message Queue File System.
10967 10:06:04.182203 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10968 10:06:04.194894 <3>[ 20.979638] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 10:06:04.201449 <30>[ 20.989054] systemd[1]: Mounted Kernel Debug File System.
10970 10:06:04.207888 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10971 10:06:04.227343 <3>[ 21.011887] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 10:06:04.237104 <30>[ 21.012270] systemd[1]: Finished Create list of static device nodes for the current kernel.
10973 10:06:04.243545 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10974 10:06:04.260786 <30>[ 21.048421] systemd[1]: modprobe@configfs.service: Succeeded.
10975 10:06:04.267331 <30>[ 21.055360] systemd[1]: Finished Load Kernel Module configfs.
10976 10:06:04.277120 <3>[ 21.056768] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 10:06:04.283871 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10978 10:06:04.299747 <30>[ 21.087941] systemd[1]: modprobe@drm.service: Succeeded.
10979 10:06:04.306588 <30>[ 21.094540] systemd[1]: Finished Load Kernel Module drm.
10980 10:06:04.316692 <3>[ 21.096865] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10981 10:06:04.323006 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10982 10:06:04.340164 <30>[ 21.128065] systemd[1]: modprobe@fuse.service: Succeeded.
10983 10:06:04.350515 <3>[ 21.131876] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 10:06:04.356449 <30>[ 21.134427] systemd[1]: Finished Load Kernel Module fuse.
10985 10:06:04.360146 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10986 10:06:04.377283 <3>[ 21.162112] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 10:06:04.385031 <30>[ 21.172854] systemd[1]: Finished Load Kernel Modules.
10988 10:06:04.391214 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10989 10:06:04.407341 <30>[ 21.192265] systemd[1]: Finished Remount Root and Kernel File Systems.
10990 10:06:04.414435 <3>[ 21.193445] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10991 10:06:04.420699 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10992 10:06:04.448606 <3>[ 21.233419] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10993 10:06:04.471467 <30>[ 21.258779] systemd[1]: Mounting FUSE Control File System...
10994 10:06:04.484835 Mounting [0;1;39mFUSE <3>[ 21.267095] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 10:06:04.484975 Control File System[0m...
10996 10:06:04.501275 <30>[ 21.289583] systemd[1]: Mounting Kernel Configuration File System...
10997 10:06:04.515564 Mounting [0;1;39mKernel Configuration <3>[ 21.300499] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10998 10:06:04.519098 File System[0m...
10999 10:06:04.544702 <30>[ 21.329121] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
11000 10:06:04.554525 <30>[ 21.338221] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
11001 10:06:04.575236 <30>[ 21.363560] systemd[1]: Starting Load/Save Random Seed...
11002 10:06:04.582074 Starting [0;1;39mLoad/Save Random Seed[0m...
11003 10:06:04.602825 <30>[ 21.391250] systemd[1]: Starting Apply Kernel Variables...
11004 10:06:04.609622 Starting [0;1;39mApply Kernel Variables[0m...
11005 10:06:04.626612 <30>[ 21.414673] systemd[1]: Starting Create System Users...
11006 10:06:04.632881 Starting [0;1;39mCreate System Users[0m...
11007 10:06:04.649377 <30>[ 21.436983] systemd[1]: Started Journal Service.
11008 10:06:04.655227 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11009 10:06:04.686528 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0<4>[ 21.462305] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11010 10:06:04.686707 m.
11011 10:06:04.692487 <3>[ 21.478505] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11012 10:06:04.699884 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11013 10:06:04.717427 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11014 10:06:04.740413 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
11015 10:06:04.750738 See 'systemctl status systemd-udev-trigger.service' for details.
11016 10:06:04.767960 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11017 10:06:04.784623 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11018 10:06:04.819693 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11019 10:06:04.837701 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11020 10:06:04.874249 <46>[ 21.659333] systemd-journald[293]: Received client request to flush runtime journal.
11021 10:06:04.908367 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11022 10:06:04.922383 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11023 10:06:04.935139 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11024 10:06:04.991225 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11025 10:06:06.256698 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11026 10:06:06.299228 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11027 10:06:06.325585 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11028 10:06:06.348122 Starting [0;1;39mNetwork Service[0m...
11029 10:06:06.685810 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11030 10:06:06.703575 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11031 10:06:06.758946 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11032 10:06:06.916881 <6>[ 23.705026] remoteproc remoteproc0: powering up scp
11033 10:06:06.942697 <4>[ 23.727995] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11034 10:06:06.949335 <3>[ 23.737855] remoteproc remoteproc0: request_firmware failed: -2
11035 10:06:06.959073 <3>[ 23.744109] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11036 10:06:07.086341 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11037 10:06:07.103089 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11038 10:06:07.133422 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11039 10:06:07.174454 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11040 10:06:07.194069 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11041 10:06:07.231377 Starting [0;1;39mNetwork Name Resolution[0m...
11042 10:06:07.255706 Starting [0;1;39mNetwork Time Synchronization[0m...
11043 10:06:07.274138 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11044 10:06:07.300273 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11045 10:06:07.332689 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11046 10:06:07.351765 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11047 10:06:07.694711 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11048 10:06:07.715283 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11049 10:06:07.738009 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11050 10:06:07.754767 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11051 10:06:07.771067 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11052 10:06:07.821935 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11053 10:06:07.848384 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11054 10:06:07.871763 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11055 10:06:07.891752 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11056 10:06:07.902276 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11057 10:06:07.922581 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11058 10:06:07.934404 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11059 10:06:07.954836 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11060 10:06:08.003211 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11061 10:06:08.066854 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11062 10:06:08.101438 Starting [0;1;39mUser Login Management[0m...
11063 10:06:08.115562 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11064 10:06:08.135807 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11065 10:06:08.157627 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11066 10:06:08.199424 Starting [0;1;39mPermit User Sessions[0m...
11067 10:06:08.330910 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11068 10:06:08.382226 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11069 10:06:08.399462 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11070 10:06:08.416082 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11071 10:06:08.436368 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11072 10:06:08.452443 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11073 10:06:08.470891 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11074 10:06:08.485087 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11075 10:06:08.516708 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11076 10:06:08.561140 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11077 10:06:08.662863
11078 10:06:08.663027
11079 10:06:08.665251 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11080 10:06:08.665329
11081 10:06:08.668431 debian-bullseye-arm64 login: root (automatic login)
11082 10:06:08.668580
11083 10:06:08.668662
11084 10:06:08.963213 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023 aarch64
11085 10:06:08.963358
11086 10:06:08.970011 The programs included with the Debian GNU/Linux system are free software;
11087 10:06:08.976189 the exact distribution terms for each program are described in the
11088 10:06:08.979698 individual files in /usr/share/doc/*/copyright.
11089 10:06:08.979778
11090 10:06:08.986846 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11091 10:06:08.989505 permitted by applicable law.
11092 10:06:09.733413 Matched prompt #10: / #
11094 10:06:09.733696 Setting prompt string to ['/ #']
11095 10:06:09.733794 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11097 10:06:09.733987 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11098 10:06:09.734074 start: 2.2.6 expect-shell-connection (timeout 00:03:39) [common]
11099 10:06:09.734152 Setting prompt string to ['/ #']
11100 10:06:09.734213 Forcing a shell prompt, looking for ['/ #']
11102 10:06:09.784428 / #
11103 10:06:09.784586 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11104 10:06:09.784667 Waiting using forced prompt support (timeout 00:02:30)
11105 10:06:09.789447
11106 10:06:09.789724 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11107 10:06:09.789821 start: 2.2.7 export-device-env (timeout 00:03:39) [common]
11109 10:06:09.890172 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10670685/extract-nfsrootfs-fbgtgk4p'
11110 10:06:09.895034 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10670685/extract-nfsrootfs-fbgtgk4p'
11112 10:06:09.995545 / # export NFS_SERVER_IP='192.168.201.1'
11113 10:06:10.000394 export NFS_SERVER_IP='192.168.201.1'
11114 10:06:10.000686 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11115 10:06:10.000789 end: 2.2 depthcharge-retry (duration 00:01:21) [common]
11116 10:06:10.000882 end: 2 depthcharge-action (duration 00:01:21) [common]
11117 10:06:10.000973 start: 3 lava-test-retry (timeout 00:08:00) [common]
11118 10:06:10.001064 start: 3.1 lava-test-shell (timeout 00:08:00) [common]
11119 10:06:10.001154 Using namespace: common
11121 10:06:10.101445 / # #
11122 10:06:10.101608 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11123 10:06:10.106892 #
11124 10:06:10.107168 Using /lava-10670685
11126 10:06:10.207480 / # export SHELL=/bin/bash
11127 10:06:10.212455 export SHELL=/bin/bash
11129 10:06:10.312970 / # . /lava-10670685/environment
11130 10:06:10.318110 . /lava-10670685/environment
11132 10:06:10.424311 / # /lava-10670685/bin/lava-test-runner /lava-10670685/0
11133 10:06:10.424470 Test shell timeout: 10s (minimum of the action and connection timeout)
11134 10:06:10.430301 /lava-10670685/bin/lava-test-runner /lava-10670685/0
11135 10:06:10.652169 + export TESTRUN_ID=0_timesync-off
11136 10:06:10.655776 + TESTRUN_ID=0_timesync-off
11137 10:06:10.658995 + cd /lava-10670685/0/tests/0_timesync-off
11138 10:06:10.662170 ++ cat uuid
11139 10:06:10.662255 + UUID=10670685_1.6.2.3.1
11140 10:06:10.665612 + set +x
11141 10:06:10.668491 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10670685_1.6.2.3.1>
11142 10:06:10.668823 Received signal: <STARTRUN> 0_timesync-off 10670685_1.6.2.3.1
11143 10:06:10.668905 Starting test lava.0_timesync-off (10670685_1.6.2.3.1)
11144 10:06:10.668995 Skipping test definition patterns.
11145 10:06:10.671807 + systemctl stop systemd-timesyncd
11146 10:06:10.697525 + set +x
11147 10:06:10.701063 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10670685_1.6.2.3.1>
11148 10:06:10.701318 Received signal: <ENDRUN> 0_timesync-off 10670685_1.6.2.3.1
11149 10:06:10.701403 Ending use of test pattern.
11150 10:06:10.701467 Ending test lava.0_timesync-off (10670685_1.6.2.3.1), duration 0.03
11152 10:06:10.758581 + export TESTRUN_ID=1_kselftest-rtc
11153 10:06:10.762179 + TESTRUN_ID=1_kselftest-rtc
11154 10:06:10.765117 + cd /lava-10670685/0/tests/1_kselftest-rtc
11155 10:06:10.768393 ++ cat uuid
11156 10:06:10.772021 + UUID=10670685_1.6.2.3.5
11157 10:06:10.772127 + set +x
11158 10:06:10.778444 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 10670685_1.6.2.3.5>
11159 10:06:10.778704 Received signal: <STARTRUN> 1_kselftest-rtc 10670685_1.6.2.3.5
11160 10:06:10.778782 Starting test lava.1_kselftest-rtc (10670685_1.6.2.3.5)
11161 10:06:10.778889 Skipping test definition patterns.
11162 10:06:10.781706 + cd ./automated/linux/kselftest/
11163 10:06:10.808180 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11164 10:06:10.836360 INFO: install_deps skipped
11165 10:06:10.947525 --2023-06-10 10:06:10-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11166 10:06:10.954284 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11167 10:06:11.078490 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11168 10:06:11.207882 HTTP request sent, awaiting response... 200 OK
11169 10:06:11.211019 Length: 2883260 (2.7M) [application/octet-stream]
11170 10:06:11.214647 Saving to: 'kselftest.tar.xz'
11171 10:06:11.214739
11172 10:06:11.214806
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11178 10:06:12.755221 kselftest.tar.xz 17%[==> ] 480.03K 363KB/s
11179 10:06:13.013036 kselftest.tar.xz 22%[===> ] 640.30K 403KB/s
11180 10:06:13.270718 kselftest.tar.xz 26%[====> ] 743.53K 401KB/s
11181 10:06:13.529240 kselftest.tar.xz 30%[=====> ] 852.41K 403KB/s
11182 10:06:13.787026 kselftest.tar.xz 34%[=====> ] 966.95K 406KB/s
11183 10:06:14.045193 kselftest.tar.xz 38%[======> ] 1.05M 408KB/s
11184 10:06:14.302601 kselftest.tar.xz 42%[=======> ] 1.17M 411KB/s
11185 10:06:14.561292 kselftest.tar.xz 46%[========> ] 1.28M 414KB/s eta 4s
11186 10:06:14.788027 kselftest.tar.xz 50%[=========> ] 1.39M 416KB/s eta 4s
11187 10:06:15.078537 kselftest.tar.xz 54%[=========> ] 1.50M 420KB/s eta 4s
11188 10:06:15.305979 kselftest.tar.xz 59%[==========> ] 1.63M 421KB/s eta 4s
11189 10:06:15.517955 kselftest.tar.xz 63%[===========> ] 1.74M 426KB/s eta 2s
11190 10:06:15.725404 kselftest.tar.xz 67%[============> ] 1.86M 433KB/s eta 2s
11191 10:06:15.951013 kselftest.tar.xz 70%[=============> ] 1.94M 429KB/s eta 2s
11192 10:06:16.161847 kselftest.tar.xz 74%[=============> ] 2.06M 435KB/s eta 2s
11193 10:06:16.370517 kselftest.tar.xz 79%[==============> ] 2.18M 456KB/s eta 2s
11194 10:06:16.606659 kselftest.tar.xz 82%[===============> ] 2.26M 454KB/s eta 1s
11195 10:06:16.806683 kselftest.tar.xz 86%[================> ] 2.39M 457KB/s eta 1s
11196 10:06:17.016068 kselftest.tar.xz 91%[=================> ] 2.51M 476KB/s eta 1s
11197 10:06:17.240810 kselftest.tar.xz 94%[=================> ] 2.61M 472KB/s eta 1s
11198 10:06:17.277563 kselftest.tar.xz 99%[==================> ] 2.73M 481KB/s eta 1s
11199 10:06:17.284322 kselftest.tar.xz 100%[===================>] 2.75M 481KB/s in 6.2s
11200 10:06:17.284437
11201 10:06:17.534636 2023-06-10 10:06:17 (455 KB/s) - 'kselftest.tar.xz' saved [2883260/2883260]
11202 10:06:17.534787
11203 10:06:22.357391 skiplist:
11204 10:06:22.360663 ========================================
11205 10:06:22.364048 ========================================
11206 10:06:22.402405 rtc:rtctest
11207 10:06:22.421541 ============== Tests to run ===============
11208 10:06:22.421658 rtc:rtctest
11209 10:06:22.424921 ===========End Tests to run ===============
11210 10:06:22.506595 <12>[ 39.297067] kselftest: Running tests in rtc
11211 10:06:22.515383 TAP version 13
11212 10:06:22.527019 1..1
11213 10:06:22.554381 # selftests: rtc: rtctest
11214 10:06:22.914533 # TAP version 13
11215 10:06:22.914692 # 1..8
11216 10:06:22.918223 # # Starting 8 tests from 2 test cases.
11217 10:06:22.921294 # # RUN rtc.date_read ...
11218 10:06:22.927971 # # rtctest.c:49:date_read:Current RTC date/time is 10/06/2023 10:06:22.
11219 10:06:22.930994 # # OK rtc.date_read
11220 10:06:22.934472 # ok 1 rtc.date_read
11221 10:06:22.938053 # # RUN rtc.date_read_loop ...
11222 10:06:22.947521 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11223 10:06:29.052215 <6>[ 45.846280] vpu: disabling
11224 10:06:29.055185 <6>[ 45.849328] vproc2: disabling
11225 10:06:29.058435 <6>[ 45.852612] vproc1: disabling
11226 10:06:29.061650 <6>[ 45.855874] vaud18: disabling
11227 10:06:29.069173 <6>[ 45.859280] vsram_others: disabling
11228 10:06:29.071626 <6>[ 45.863155] va09: disabling
11229 10:06:29.075093 <6>[ 45.866260] vsram_md: disabling
11230 10:06:29.078232 <6>[ 45.869745] Vgpu: disabling
11231 10:06:53.308205 # # rtctest.c:115:date_read_loop:Performed 2723 RTC time reads.
11232 10:06:53.311262 # # OK rtc.date_read_loop
11233 10:06:53.315096 # ok 2 rtc.date_read_loop
11234 10:06:53.318671 # # RUN rtc.uie_read ...
11235 10:06:56.293779 # # OK rtc.uie_read
11236 10:06:56.297382 # ok 3 rtc.uie_read
11237 10:06:56.300722 # # RUN rtc.uie_select ...
11238 10:06:59.293149 # # OK rtc.uie_select
11239 10:06:59.296335 # ok 4 rtc.uie_select
11240 10:06:59.299884 # # RUN rtc.alarm_alm_set ...
11241 10:06:59.306184 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 10:07:02.
11242 10:06:59.309611 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11243 10:06:59.316362 # # alarm_alm_set: Test terminated by assertion
11244 10:06:59.319570 # # FAIL rtc.alarm_alm_set
11245 10:06:59.322938 # not ok 5 rtc.alarm_alm_set
11246 10:06:59.326269 # # RUN rtc.alarm_wkalm_set ...
11247 10:06:59.332353 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 10/06/2023 10:07:02.
11248 10:07:02.296802 # # OK rtc.alarm_wkalm_set
11249 10:07:02.297370 # ok 6 rtc.alarm_wkalm_set
11250 10:07:02.302877 # # RUN rtc.alarm_alm_set_minute ...
11251 10:07:02.306111 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 10:08:00.
11252 10:07:02.312886 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11253 10:07:02.319397 # # alarm_alm_set_minute: Test terminated by assertion
11254 10:07:02.322832 # # FAIL rtc.alarm_alm_set_minute
11255 10:07:02.326219 # not ok 7 rtc.alarm_alm_set_minute
11256 10:07:02.328992 # # RUN rtc.alarm_wkalm_set_minute ...
11257 10:07:02.335704 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 10/06/2023 10:08:00.
11258 10:08:00.289494 # # OK rtc.alarm_wkalm_set_minute
11259 10:08:00.293139 # ok 8 rtc.alarm_wkalm_set_minute
11260 10:08:00.296241 # # FAILED: 6 / 8 tests passed.
11261 10:08:00.299625 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11262 10:08:00.302876 not ok 1 selftests: rtc: rtctest # exit=1
11263 10:08:00.801605 rtc_rtctest_rtc_date_read pass
11264 10:08:00.804844 rtc_rtctest_rtc_date_read_loop pass
11265 10:08:00.808274 rtc_rtctest_rtc_uie_read pass
11266 10:08:00.811575 rtc_rtctest_rtc_uie_select pass
11267 10:08:00.814512 rtc_rtctest_rtc_alarm_alm_set fail
11268 10:08:00.817723 rtc_rtctest_rtc_alarm_wkalm_set pass
11269 10:08:00.821445 rtc_rtctest_rtc_alarm_alm_set_minute fail
11270 10:08:00.824167 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11271 10:08:00.828037 rtc_rtctest fail
11272 10:08:00.831266 + ../../utils/send-to-lava.sh ./output/result.txt
11273 10:08:00.893861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11274 10:08:00.894612 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11276 10:08:00.943259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11277 10:08:00.943524 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11279 10:08:00.979711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11280 10:08:00.979967 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11282 10:08:01.018953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11283 10:08:01.019209 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11285 10:08:01.058445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11286 10:08:01.058729 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11288 10:08:01.095208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11289 10:08:01.095475 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11291 10:08:01.134302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11292 10:08:01.134556 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11294 10:08:01.167785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11295 10:08:01.168038 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11297 10:08:01.198273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11298 10:08:01.198363 + set +x
11299 10:08:01.198600 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11301 10:08:01.203908 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 10670685_1.6.2.3.5>
11302 10:08:01.204169 Received signal: <ENDRUN> 1_kselftest-rtc 10670685_1.6.2.3.5
11303 10:08:01.204250 Ending use of test pattern.
11304 10:08:01.204316 Ending test lava.1_kselftest-rtc (10670685_1.6.2.3.5), duration 110.43
11306 10:08:01.204557 ok: lava_test_shell seems to have completed
11307 10:08:01.204693 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
11308 10:08:01.204789 end: 3.1 lava-test-shell (duration 00:01:51) [common]
11309 10:08:01.204878 end: 3 lava-test-retry (duration 00:01:51) [common]
11310 10:08:01.204966 start: 4 finalize (timeout 00:06:08) [common]
11311 10:08:01.205063 start: 4.1 power-off (timeout 00:00:30) [common]
11312 10:08:01.205227 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11313 10:08:01.286588 >> Command sent successfully.
11314 10:08:01.293894 Returned 0 in 0 seconds
11315 10:08:01.395157 end: 4.1 power-off (duration 00:00:00) [common]
11317 10:08:01.396954 start: 4.2 read-feedback (timeout 00:06:08) [common]
11319 10:08:01.399225 Listened to connection for namespace 'common' for up to 1s
11320 10:08:02.399050 Finalising connection for namespace 'common'
11321 10:08:02.399739 Disconnecting from shell: Finalise
11322 10:08:02.400179 / #
11323 10:08:02.501227 end: 4.2 read-feedback (duration 00:00:01) [common]
11324 10:08:02.501935 end: 4 finalize (duration 00:00:01) [common]
11325 10:08:02.502517 Cleaning after the job
11326 10:08:02.503024 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/ramdisk
11327 10:08:02.513249 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/kernel
11328 10:08:02.542964 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/dtb
11329 10:08:02.543322 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/nfsrootfs
11330 10:08:02.617032 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670685/tftp-deploy-bg4sbiaz/modules
11331 10:08:02.622465 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10670685
11332 10:08:03.137721 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10670685
11333 10:08:03.137913 Job finished correctly