Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 41
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 29
- Errors: 0
1 10:06:14.690368 lava-dispatcher, installed at version: 2023.05.1
2 10:06:14.690633 start: 0 validate
3 10:06:14.690808 Start time: 2023-06-10 10:06:14.690797+00:00 (UTC)
4 10:06:14.690983 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:06:14.691179 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 10:06:14.955777 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:06:14.955977 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:06:15.205496 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:06:15.205746 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:06:15.472635 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:06:15.472881 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:06:15.737870 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:06:15.738045 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:06:15.988989 validate duration: 1.30
16 10:06:15.989269 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:06:15.989377 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:06:15.989469 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:06:15.989602 Not decompressing ramdisk as can be used compressed.
20 10:06:15.989690 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/initrd.cpio.gz
21 10:06:15.989765 saving as /var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/ramdisk/initrd.cpio.gz
22 10:06:15.989830 total size: 4665273 (4MB)
23 10:06:15.990938 progress 0% (0MB)
24 10:06:15.992543 progress 5% (0MB)
25 10:06:15.993869 progress 10% (0MB)
26 10:06:15.995268 progress 15% (0MB)
27 10:06:15.996603 progress 20% (0MB)
28 10:06:15.997948 progress 25% (1MB)
29 10:06:15.999247 progress 30% (1MB)
30 10:06:16.000570 progress 35% (1MB)
31 10:06:16.001906 progress 40% (1MB)
32 10:06:16.003422 progress 45% (2MB)
33 10:06:16.004727 progress 50% (2MB)
34 10:06:16.006012 progress 55% (2MB)
35 10:06:16.007360 progress 60% (2MB)
36 10:06:16.008662 progress 65% (2MB)
37 10:06:16.009953 progress 70% (3MB)
38 10:06:16.011236 progress 75% (3MB)
39 10:06:16.012541 progress 80% (3MB)
40 10:06:16.013985 progress 85% (3MB)
41 10:06:16.015258 progress 90% (4MB)
42 10:06:16.016565 progress 95% (4MB)
43 10:06:16.017889 progress 100% (4MB)
44 10:06:16.018078 4MB downloaded in 0.03s (157.53MB/s)
45 10:06:16.018276 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:06:16.018617 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:06:16.018710 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:06:16.018799 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:06:16.018930 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:06:16.019005 saving as /var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/kernel/Image
52 10:06:16.019068 total size: 45746688 (43MB)
53 10:06:16.019146 No compression specified
54 10:06:16.020257 progress 0% (0MB)
55 10:06:16.032103 progress 5% (2MB)
56 10:06:16.044082 progress 10% (4MB)
57 10:06:16.056794 progress 15% (6MB)
58 10:06:16.069302 progress 20% (8MB)
59 10:06:16.081659 progress 25% (10MB)
60 10:06:16.093816 progress 30% (13MB)
61 10:06:16.106270 progress 35% (15MB)
62 10:06:16.118525 progress 40% (17MB)
63 10:06:16.130798 progress 45% (19MB)
64 10:06:16.142839 progress 50% (21MB)
65 10:06:16.154704 progress 55% (24MB)
66 10:06:16.166762 progress 60% (26MB)
67 10:06:16.178923 progress 65% (28MB)
68 10:06:16.191007 progress 70% (30MB)
69 10:06:16.203066 progress 75% (32MB)
70 10:06:16.215188 progress 80% (34MB)
71 10:06:16.227704 progress 85% (37MB)
72 10:06:16.239868 progress 90% (39MB)
73 10:06:16.251703 progress 95% (41MB)
74 10:06:16.263464 progress 100% (43MB)
75 10:06:16.263598 43MB downloaded in 0.24s (178.42MB/s)
76 10:06:16.263753 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:06:16.264001 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:06:16.264091 start: 1.3 download-retry (timeout 00:10:00) [common]
80 10:06:16.264177 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 10:06:16.264319 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 10:06:16.264396 saving as /var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/dtb/mt8192-asurada-spherion-r0.dtb
83 10:06:16.264468 total size: 46924 (0MB)
84 10:06:16.264531 No compression specified
85 10:06:16.265702 progress 69% (0MB)
86 10:06:16.265978 progress 100% (0MB)
87 10:06:16.266145 0MB downloaded in 0.00s (26.73MB/s)
88 10:06:16.266276 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:06:16.266515 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:06:16.266605 start: 1.4 download-retry (timeout 00:10:00) [common]
92 10:06:16.266699 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 10:06:16.266810 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/full.rootfs.tar.xz
94 10:06:16.266890 saving as /var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/nfsrootfs/full.rootfs.tar
95 10:06:16.266954 total size: 89386020 (85MB)
96 10:06:16.267016 Using unxz to decompress xz
97 10:06:16.270644 progress 0% (0MB)
98 10:06:16.483715 progress 5% (4MB)
99 10:06:16.702270 progress 10% (8MB)
100 10:06:16.966690 progress 15% (12MB)
101 10:06:17.165740 progress 20% (17MB)
102 10:06:17.260477 progress 25% (21MB)
103 10:06:17.524362 progress 30% (25MB)
104 10:06:17.828413 progress 35% (29MB)
105 10:06:18.108437 progress 40% (34MB)
106 10:06:18.384391 progress 45% (38MB)
107 10:06:18.646559 progress 50% (42MB)
108 10:06:18.923965 progress 55% (46MB)
109 10:06:19.188079 progress 60% (51MB)
110 10:06:19.466608 progress 65% (55MB)
111 10:06:19.781923 progress 70% (59MB)
112 10:06:20.101811 progress 75% (63MB)
113 10:06:20.415109 progress 80% (68MB)
114 10:06:20.680729 progress 85% (72MB)
115 10:06:20.921109 progress 90% (76MB)
116 10:06:21.187890 progress 95% (81MB)
117 10:06:21.462350 progress 100% (85MB)
118 10:06:21.468543 85MB downloaded in 5.20s (16.39MB/s)
119 10:06:21.468890 end: 1.4.1 http-download (duration 00:00:05) [common]
121 10:06:21.469153 end: 1.4 download-retry (duration 00:00:05) [common]
122 10:06:21.469246 start: 1.5 download-retry (timeout 00:09:55) [common]
123 10:06:21.469335 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 10:06:21.469482 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:06:21.469555 saving as /var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/modules/modules.tar
126 10:06:21.469619 total size: 8540248 (8MB)
127 10:06:21.469683 Using unxz to decompress xz
128 10:06:21.473415 progress 0% (0MB)
129 10:06:21.495489 progress 5% (0MB)
130 10:06:21.520009 progress 10% (0MB)
131 10:06:21.543994 progress 15% (1MB)
132 10:06:21.569091 progress 20% (1MB)
133 10:06:21.593472 progress 25% (2MB)
134 10:06:21.616105 progress 30% (2MB)
135 10:06:21.641987 progress 35% (2MB)
136 10:06:21.666780 progress 40% (3MB)
137 10:06:21.690529 progress 45% (3MB)
138 10:06:21.718761 progress 50% (4MB)
139 10:06:21.744798 progress 55% (4MB)
140 10:06:21.771212 progress 60% (4MB)
141 10:06:21.796882 progress 65% (5MB)
142 10:06:21.821622 progress 70% (5MB)
143 10:06:21.845784 progress 75% (6MB)
144 10:06:21.869199 progress 80% (6MB)
145 10:06:21.893350 progress 85% (6MB)
146 10:06:21.922307 progress 90% (7MB)
147 10:06:21.947804 progress 95% (7MB)
148 10:06:21.972967 progress 100% (8MB)
149 10:06:21.978329 8MB downloaded in 0.51s (16.01MB/s)
150 10:06:21.978606 end: 1.5.1 http-download (duration 00:00:01) [common]
152 10:06:21.978876 end: 1.5 download-retry (duration 00:00:01) [common]
153 10:06:21.978970 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 10:06:21.979067 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 10:06:23.588671 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10670702/extract-nfsrootfs-897hv1o9
156 10:06:23.588934 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 10:06:23.589074 start: 1.6.2 lava-overlay (timeout 00:09:52) [common]
158 10:06:23.589286 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt
159 10:06:23.589445 makedir: /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin
160 10:06:23.589564 makedir: /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/tests
161 10:06:23.589694 makedir: /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/results
162 10:06:23.589799 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-add-keys
163 10:06:23.589940 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-add-sources
164 10:06:23.590068 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-background-process-start
165 10:06:23.590198 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-background-process-stop
166 10:06:23.590323 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-common-functions
167 10:06:23.590447 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-echo-ipv4
168 10:06:23.590586 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-install-packages
169 10:06:23.590724 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-installed-packages
170 10:06:23.590848 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-os-build
171 10:06:23.590971 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-probe-channel
172 10:06:23.591095 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-probe-ip
173 10:06:23.591219 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-target-ip
174 10:06:23.591342 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-target-mac
175 10:06:23.591466 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-target-storage
176 10:06:23.591592 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-test-case
177 10:06:23.591718 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-test-event
178 10:06:23.591857 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-test-feedback
179 10:06:23.591994 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-test-raise
180 10:06:23.592117 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-test-reference
181 10:06:23.592242 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-test-runner
182 10:06:23.592366 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-test-set
183 10:06:23.592489 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-test-shell
184 10:06:23.592615 Updating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-install-packages (oe)
185 10:06:23.592761 Updating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/bin/lava-installed-packages (oe)
186 10:06:23.592899 Creating /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/environment
187 10:06:23.593001 LAVA metadata
188 10:06:23.593075 - LAVA_JOB_ID=10670702
189 10:06:23.593142 - LAVA_DISPATCHER_IP=192.168.201.1
190 10:06:23.593243 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:52) [common]
191 10:06:23.593312 skipped lava-vland-overlay
192 10:06:23.593389 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 10:06:23.593489 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
194 10:06:23.593557 skipped lava-multinode-overlay
195 10:06:23.593633 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 10:06:23.593717 start: 1.6.2.3 test-definition (timeout 00:09:52) [common]
197 10:06:23.593793 Loading test definitions
198 10:06:23.593886 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:52) [common]
199 10:06:23.593957 Using /lava-10670702 at stage 0
200 10:06:23.594252 uuid=10670702_1.6.2.3.1 testdef=None
201 10:06:23.594345 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 10:06:23.594433 start: 1.6.2.3.2 test-overlay (timeout 00:09:52) [common]
203 10:06:23.594923 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 10:06:23.595153 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:52) [common]
206 10:06:23.595760 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 10:06:23.596022 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
209 10:06:23.596652 runner path: /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/0/tests/0_lc-compliance test_uuid 10670702_1.6.2.3.1
210 10:06:23.596843 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 10:06:23.597100 Creating lava-test-runner.conf files
213 10:06:23.597198 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10670702/lava-overlay-0opj64gt/lava-10670702/0 for stage 0
214 10:06:23.597288 - 0_lc-compliance
215 10:06:23.597417 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 10:06:23.597504 start: 1.6.2.4 compress-overlay (timeout 00:09:52) [common]
217 10:06:23.603471 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 10:06:23.603589 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
219 10:06:23.603706 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 10:06:23.603824 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 10:06:23.603912 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
222 10:06:23.718958 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 10:06:23.719321 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 10:06:23.719469 extracting modules file /var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670702/extract-nfsrootfs-897hv1o9
225 10:06:23.920492 extracting modules file /var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670702/extract-overlay-ramdisk-_qfc9qmk/ramdisk
226 10:06:24.129428 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 10:06:24.129599 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 10:06:24.129693 [common] Applying overlay to NFS
229 10:06:24.129799 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670702/compress-overlay-uyj_nubq/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10670702/extract-nfsrootfs-897hv1o9
230 10:06:24.136291 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 10:06:24.136406 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 10:06:24.136499 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 10:06:24.136589 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 10:06:24.136670 Building ramdisk /var/lib/lava/dispatcher/tmp/10670702/extract-overlay-ramdisk-_qfc9qmk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10670702/extract-overlay-ramdisk-_qfc9qmk/ramdisk
235 10:06:24.401438 >> 117806 blocks
236 10:06:26.477910 rename /var/lib/lava/dispatcher/tmp/10670702/extract-overlay-ramdisk-_qfc9qmk/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/ramdisk/ramdisk.cpio.gz
237 10:06:26.478420 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 10:06:26.478542 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 10:06:26.478648 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 10:06:26.478754 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/kernel/Image'
241 10:06:38.460868 Returned 0 in 11 seconds
242 10:06:38.561537 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/kernel/image.itb
243 10:06:38.871985 output: FIT description: Kernel Image image with one or more FDT blobs
244 10:06:38.872481 output: Created: Sat Jun 10 11:06:38 2023
245 10:06:38.872602 output: Image 0 (kernel-1)
246 10:06:38.872700 output: Description:
247 10:06:38.872805 output: Created: Sat Jun 10 11:06:38 2023
248 10:06:38.872898 output: Type: Kernel Image
249 10:06:38.872990 output: Compression: lzma compressed
250 10:06:38.873082 output: Data Size: 10087317 Bytes = 9850.90 KiB = 9.62 MiB
251 10:06:38.873175 output: Architecture: AArch64
252 10:06:38.873267 output: OS: Linux
253 10:06:38.873357 output: Load Address: 0x00000000
254 10:06:38.873449 output: Entry Point: 0x00000000
255 10:06:38.873540 output: Hash algo: crc32
256 10:06:38.873626 output: Hash value: c9e456fd
257 10:06:38.873711 output: Image 1 (fdt-1)
258 10:06:38.873796 output: Description: mt8192-asurada-spherion-r0
259 10:06:38.873882 output: Created: Sat Jun 10 11:06:38 2023
260 10:06:38.873968 output: Type: Flat Device Tree
261 10:06:38.874053 output: Compression: uncompressed
262 10:06:38.874138 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
263 10:06:38.874224 output: Architecture: AArch64
264 10:06:38.874310 output: Hash algo: crc32
265 10:06:38.874395 output: Hash value: 1df858fa
266 10:06:38.874480 output: Image 2 (ramdisk-1)
267 10:06:38.874565 output: Description: unavailable
268 10:06:38.874650 output: Created: Sat Jun 10 11:06:38 2023
269 10:06:38.874736 output: Type: RAMDisk Image
270 10:06:38.874821 output: Compression: Unknown Compression
271 10:06:38.874906 output: Data Size: 17645802 Bytes = 17232.23 KiB = 16.83 MiB
272 10:06:38.874992 output: Architecture: AArch64
273 10:06:38.875077 output: OS: Linux
274 10:06:38.875161 output: Load Address: unavailable
275 10:06:38.875246 output: Entry Point: unavailable
276 10:06:38.875331 output: Hash algo: crc32
277 10:06:38.875416 output: Hash value: 5b67f68b
278 10:06:38.875501 output: Default Configuration: 'conf-1'
279 10:06:38.875586 output: Configuration 0 (conf-1)
280 10:06:38.875670 output: Description: mt8192-asurada-spherion-r0
281 10:06:38.875755 output: Kernel: kernel-1
282 10:06:38.875840 output: Init Ramdisk: ramdisk-1
283 10:06:38.875925 output: FDT: fdt-1
284 10:06:38.876010 output: Loadables: kernel-1
285 10:06:38.876095 output:
286 10:06:38.876326 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
287 10:06:38.876458 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
288 10:06:38.876592 end: 1.6 prepare-tftp-overlay (duration 00:00:17) [common]
289 10:06:38.876716 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 10:06:38.876841 No LXC device requested
291 10:06:38.876955 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 10:06:38.877078 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 10:06:38.877191 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 10:06:38.877290 Checking files for TFTP limit of 4294967296 bytes.
295 10:06:38.877938 end: 1 tftp-deploy (duration 00:00:23) [common]
296 10:06:38.878072 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 10:06:38.878200 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 10:06:38.878370 substitutions:
299 10:06:38.878465 - {DTB}: 10670702/tftp-deploy-vgedlg5m/dtb/mt8192-asurada-spherion-r0.dtb
300 10:06:38.878563 - {INITRD}: 10670702/tftp-deploy-vgedlg5m/ramdisk/ramdisk.cpio.gz
301 10:06:38.878655 - {KERNEL}: 10670702/tftp-deploy-vgedlg5m/kernel/Image
302 10:06:38.878744 - {LAVA_MAC}: None
303 10:06:38.878833 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10670702/extract-nfsrootfs-897hv1o9
304 10:06:38.878922 - {NFS_SERVER_IP}: 192.168.201.1
305 10:06:38.879009 - {PRESEED_CONFIG}: None
306 10:06:38.879096 - {PRESEED_LOCAL}: None
307 10:06:38.879183 - {RAMDISK}: 10670702/tftp-deploy-vgedlg5m/ramdisk/ramdisk.cpio.gz
308 10:06:38.879269 - {ROOT_PART}: None
309 10:06:38.879355 - {ROOT}: None
310 10:06:38.879442 - {SERVER_IP}: 192.168.201.1
311 10:06:38.879528 - {TEE}: None
312 10:06:38.879614 Parsed boot commands:
313 10:06:38.879699 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 10:06:38.879922 Parsed boot commands: tftpboot 192.168.201.1 10670702/tftp-deploy-vgedlg5m/kernel/image.itb 10670702/tftp-deploy-vgedlg5m/kernel/cmdline
315 10:06:38.880045 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 10:06:38.880168 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 10:06:38.880293 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 10:06:38.880411 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 10:06:38.880514 Not connected, no need to disconnect.
320 10:06:38.880622 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 10:06:38.880745 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 10:06:38.880835 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
323 10:06:38.884262 Setting prompt string to ['lava-test: # ']
324 10:06:38.884605 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 10:06:38.884713 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 10:06:38.884827 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 10:06:38.884984 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 10:06:38.885184 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
329 10:06:44.021274 >> Command sent successfully.
330 10:06:44.024287 Returned 0 in 5 seconds
331 10:06:44.124663 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 10:06:44.125035 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 10:06:44.125137 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 10:06:44.125228 Setting prompt string to 'Starting depthcharge on Spherion...'
336 10:06:44.125300 Changing prompt to 'Starting depthcharge on Spherion...'
337 10:06:44.125371 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 10:06:44.125638 [Enter `^Ec?' for help]
339 10:06:44.299179
340 10:06:44.299389
341 10:06:44.299512 F0: 102B 0000
342 10:06:44.299628
343 10:06:44.299751 F3: 1001 0000 [0200]
344 10:06:44.302566
345 10:06:44.302676 F3: 1001 0000
346 10:06:44.302786
347 10:06:44.302886 F7: 102D 0000
348 10:06:44.302983
349 10:06:44.303076 F1: 0000 0000
350 10:06:44.306510
351 10:06:44.306619 V0: 0000 0000 [0001]
352 10:06:44.306722
353 10:06:44.306835 00: 0007 8000
354 10:06:44.306939
355 10:06:44.310217 01: 0000 0000
356 10:06:44.310329
357 10:06:44.310425 BP: 0C00 0209 [0000]
358 10:06:44.310534
359 10:06:44.313772 G0: 1182 0000
360 10:06:44.313887
361 10:06:44.313997 EC: 0000 0021 [4000]
362 10:06:44.314103
363 10:06:44.317454 S7: 0000 0000 [0000]
364 10:06:44.317572
365 10:06:44.317687 CC: 0000 0000 [0001]
366 10:06:44.317799
367 10:06:44.320589 T0: 0000 0040 [010F]
368 10:06:44.320706
369 10:06:44.320819 Jump to BL
370 10:06:44.320936
371 10:06:44.346278
372 10:06:44.346403
373 10:06:44.346474
374 10:06:44.352654 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 10:06:44.355933 ARM64: Exception handlers installed.
376 10:06:44.359453 ARM64: Testing exception
377 10:06:44.363193 ARM64: Done test exception
378 10:06:44.370363 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 10:06:44.381174 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 10:06:44.387867 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 10:06:44.397991 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 10:06:44.404238 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 10:06:44.411041 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 10:06:44.422614 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 10:06:44.429296 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 10:06:44.449019 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 10:06:44.452142 WDT: Last reset was cold boot
388 10:06:44.455109 SPI1(PAD0) initialized at 2873684 Hz
389 10:06:44.458771 SPI5(PAD0) initialized at 992727 Hz
390 10:06:44.462064 VBOOT: Loading verstage.
391 10:06:44.468608 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 10:06:44.471922 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 10:06:44.475094 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 10:06:44.478462 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 10:06:44.486134 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 10:06:44.492841 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 10:06:44.503640 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
398 10:06:44.503757
399 10:06:44.503860
400 10:06:44.513830 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 10:06:44.517009 ARM64: Exception handlers installed.
402 10:06:44.520033 ARM64: Testing exception
403 10:06:44.523575 ARM64: Done test exception
404 10:06:44.526733 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 10:06:44.529890 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 10:06:44.544492 Probing TPM: . done!
407 10:06:44.544617 TPM ready after 0 ms
408 10:06:44.551416 Connected to device vid:did:rid of 1ae0:0028:00
409 10:06:44.558627 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
410 10:06:44.616189 Initialized TPM device CR50 revision 0
411 10:06:44.627525 tlcl_send_startup: Startup return code is 0
412 10:06:44.627653 TPM: setup succeeded
413 10:06:44.639074 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 10:06:44.647691 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 10:06:44.654678 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 10:06:44.666719 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 10:06:44.670108 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 10:06:44.678691 in-header: 03 07 00 00 08 00 00 00
419 10:06:44.682326 in-data: aa e4 47 04 13 02 00 00
420 10:06:44.686026 Chrome EC: UHEPI supported
421 10:06:44.693032 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 10:06:44.696984 in-header: 03 ad 00 00 08 00 00 00
423 10:06:44.700408 in-data: 00 20 20 08 00 00 00 00
424 10:06:44.700497 Phase 1
425 10:06:44.704398 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 10:06:44.711312 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 10:06:44.715185 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 10:06:44.718700 Recovery requested (1009000e)
429 10:06:44.728670 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 10:06:44.734531 tlcl_extend: response is 0
431 10:06:44.744589 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 10:06:44.750585 tlcl_extend: response is 0
433 10:06:44.757753 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 10:06:44.778374 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 10:06:44.784859 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 10:06:44.784955
437 10:06:44.785026
438 10:06:44.794927 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 10:06:44.798626 ARM64: Exception handlers installed.
440 10:06:44.798709 ARM64: Testing exception
441 10:06:44.801696 ARM64: Done test exception
442 10:06:44.823261 pmic_efuse_setting: Set efuses in 11 msecs
443 10:06:44.826662 pmwrap_interface_init: Select PMIF_VLD_RDY
444 10:06:44.833793 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 10:06:44.837246 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 10:06:44.840354 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 10:06:44.847007 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 10:06:44.850625 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 10:06:44.857763 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 10:06:44.861762 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 10:06:44.865251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 10:06:44.871615 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 10:06:44.875243 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 10:06:44.878921 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 10:06:44.885318 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 10:06:44.888805 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 10:06:44.895471 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 10:06:44.902383 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 10:06:44.905747 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 10:06:44.913119 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 10:06:44.916865 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 10:06:44.924178 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 10:06:44.930294 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 10:06:44.934360 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 10:06:44.941151 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 10:06:44.947895 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 10:06:44.950928 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 10:06:44.957681 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 10:06:44.964325 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 10:06:44.967960 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 10:06:44.970930 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 10:06:44.977714 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 10:06:44.981067 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 10:06:44.987663 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 10:06:44.990996 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 10:06:44.997692 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 10:06:45.000932 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 10:06:45.007671 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 10:06:45.010686 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 10:06:45.017298 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 10:06:45.021018 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 10:06:45.027526 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 10:06:45.030865 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 10:06:45.033861 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 10:06:45.040911 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 10:06:45.044291 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 10:06:45.047894 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 10:06:45.054085 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 10:06:45.057498 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 10:06:45.060843 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 10:06:45.064407 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 10:06:45.070796 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 10:06:45.074055 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 10:06:45.077676 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 10:06:45.085300 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 10:06:45.095778 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 10:06:45.098998 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 10:06:45.106490 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 10:06:45.116775 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 10:06:45.120476 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 10:06:45.124617 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 10:06:45.128179 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 10:06:45.136658 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x13
504 10:06:45.143319 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 10:06:45.146560 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 10:06:45.150176 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 10:06:45.160714 [RTC]rtc_get_frequency_meter,154: input=15, output=772
508 10:06:45.169797 [RTC]rtc_get_frequency_meter,154: input=23, output=956
509 10:06:45.179557 [RTC]rtc_get_frequency_meter,154: input=19, output=864
510 10:06:45.189034 [RTC]rtc_get_frequency_meter,154: input=17, output=817
511 10:06:45.199077 [RTC]rtc_get_frequency_meter,154: input=16, output=793
512 10:06:45.202475 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
513 10:06:45.206038 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
514 10:06:45.213580 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
515 10:06:45.217155 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
516 10:06:45.220658 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
517 10:06:45.224067 ADC[4]: Raw value=903245 ID=7
518 10:06:45.224169 ADC[3]: Raw value=213179 ID=1
519 10:06:45.227521 RAM Code: 0x71
520 10:06:45.230732 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
521 10:06:45.237259 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
522 10:06:45.244110 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
523 10:06:45.250732 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
524 10:06:45.253789 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
525 10:06:45.257494 in-header: 03 07 00 00 08 00 00 00
526 10:06:45.260966 in-data: aa e4 47 04 13 02 00 00
527 10:06:45.263909 Chrome EC: UHEPI supported
528 10:06:45.270380 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
529 10:06:45.273943 in-header: 03 ed 00 00 08 00 00 00
530 10:06:45.277324 in-data: 80 20 60 08 00 00 00 00
531 10:06:45.280888 MRC: failed to locate region type 0.
532 10:06:45.287537 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
533 10:06:45.290835 DRAM-K: Running full calibration
534 10:06:45.297311 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
535 10:06:45.300463 header.status = 0x0
536 10:06:45.303848 header.version = 0x6 (expected: 0x6)
537 10:06:45.307162 header.size = 0xd00 (expected: 0xd00)
538 10:06:45.307270 header.flags = 0x0
539 10:06:45.313563 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
540 10:06:45.331158 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
541 10:06:45.337793 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
542 10:06:45.341196 dram_init: ddr_geometry: 2
543 10:06:45.344868 [EMI] MDL number = 2
544 10:06:45.344978 [EMI] Get MDL freq = 0
545 10:06:45.347746 dram_init: ddr_type: 0
546 10:06:45.347830 is_discrete_lpddr4: 1
547 10:06:45.351285 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
548 10:06:45.351381
549 10:06:45.351454
550 10:06:45.354263 [Bian_co] ETT version 0.0.0.1
551 10:06:45.361211 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
552 10:06:45.361338
553 10:06:45.364331 dramc_set_vcore_voltage set vcore to 650000
554 10:06:45.364430 Read voltage for 800, 4
555 10:06:45.367840 Vio18 = 0
556 10:06:45.367938 Vcore = 650000
557 10:06:45.368030 Vdram = 0
558 10:06:45.370946 Vddq = 0
559 10:06:45.371043 Vmddr = 0
560 10:06:45.374354 dram_init: config_dvfs: 1
561 10:06:45.377937 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
562 10:06:45.384575 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
563 10:06:45.387624 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
564 10:06:45.391095 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
565 10:06:45.394540 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
566 10:06:45.397745 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
567 10:06:45.401289 MEM_TYPE=3, freq_sel=18
568 10:06:45.404574 sv_algorithm_assistance_LP4_1600
569 10:06:45.407602 ============ PULL DRAM RESETB DOWN ============
570 10:06:45.410838 ========== PULL DRAM RESETB DOWN end =========
571 10:06:45.417578 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
572 10:06:45.421124 ===================================
573 10:06:45.424238 LPDDR4 DRAM CONFIGURATION
574 10:06:45.427910 ===================================
575 10:06:45.428022 EX_ROW_EN[0] = 0x0
576 10:06:45.430913 EX_ROW_EN[1] = 0x0
577 10:06:45.431029 LP4Y_EN = 0x0
578 10:06:45.434237 WORK_FSP = 0x0
579 10:06:45.434369 WL = 0x2
580 10:06:45.437497 RL = 0x2
581 10:06:45.437586 BL = 0x2
582 10:06:45.441062 RPST = 0x0
583 10:06:45.441152 RD_PRE = 0x0
584 10:06:45.444508 WR_PRE = 0x1
585 10:06:45.444629 WR_PST = 0x0
586 10:06:45.447365 DBI_WR = 0x0
587 10:06:45.447478 DBI_RD = 0x0
588 10:06:45.450778 OTF = 0x1
589 10:06:45.454178 ===================================
590 10:06:45.457360 ===================================
591 10:06:45.457484 ANA top config
592 10:06:45.460852 ===================================
593 10:06:45.464320 DLL_ASYNC_EN = 0
594 10:06:45.467382 ALL_SLAVE_EN = 1
595 10:06:45.470972 NEW_RANK_MODE = 1
596 10:06:45.471105 DLL_IDLE_MODE = 1
597 10:06:45.474407 LP45_APHY_COMB_EN = 1
598 10:06:45.477248 TX_ODT_DIS = 1
599 10:06:45.480798 NEW_8X_MODE = 1
600 10:06:45.484336 ===================================
601 10:06:45.487616 ===================================
602 10:06:45.491044 data_rate = 1600
603 10:06:45.491165 CKR = 1
604 10:06:45.494301 DQ_P2S_RATIO = 8
605 10:06:45.497435 ===================================
606 10:06:45.500959 CA_P2S_RATIO = 8
607 10:06:45.504180 DQ_CA_OPEN = 0
608 10:06:45.507261 DQ_SEMI_OPEN = 0
609 10:06:45.510746 CA_SEMI_OPEN = 0
610 10:06:45.510867 CA_FULL_RATE = 0
611 10:06:45.513852 DQ_CKDIV4_EN = 1
612 10:06:45.517245 CA_CKDIV4_EN = 1
613 10:06:45.520488 CA_PREDIV_EN = 0
614 10:06:45.524233 PH8_DLY = 0
615 10:06:45.527310 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
616 10:06:45.527432 DQ_AAMCK_DIV = 4
617 10:06:45.530748 CA_AAMCK_DIV = 4
618 10:06:45.534256 CA_ADMCK_DIV = 4
619 10:06:45.537367 DQ_TRACK_CA_EN = 0
620 10:06:45.540552 CA_PICK = 800
621 10:06:45.543875 CA_MCKIO = 800
622 10:06:45.547465 MCKIO_SEMI = 0
623 10:06:45.547567 PLL_FREQ = 3068
624 10:06:45.550562 DQ_UI_PI_RATIO = 32
625 10:06:45.554190 CA_UI_PI_RATIO = 0
626 10:06:45.557351 ===================================
627 10:06:45.560620 ===================================
628 10:06:45.563620 memory_type:LPDDR4
629 10:06:45.563711 GP_NUM : 10
630 10:06:45.567069 SRAM_EN : 1
631 10:06:45.570656 MD32_EN : 0
632 10:06:45.574306 ===================================
633 10:06:45.574397 [ANA_INIT] >>>>>>>>>>>>>>
634 10:06:45.577931 <<<<<< [CONFIGURE PHASE]: ANA_TX
635 10:06:45.581735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
636 10:06:45.585325 ===================================
637 10:06:45.589005 data_rate = 1600,PCW = 0X7600
638 10:06:45.592308 ===================================
639 10:06:45.595706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
640 10:06:45.599488 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
641 10:06:45.606230 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
642 10:06:45.609679 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
643 10:06:45.613413 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
644 10:06:45.616235 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
645 10:06:45.619510 [ANA_INIT] flow start
646 10:06:45.619601 [ANA_INIT] PLL >>>>>>>>
647 10:06:45.622967 [ANA_INIT] PLL <<<<<<<<
648 10:06:45.626376 [ANA_INIT] MIDPI >>>>>>>>
649 10:06:45.629464 [ANA_INIT] MIDPI <<<<<<<<
650 10:06:45.629557 [ANA_INIT] DLL >>>>>>>>
651 10:06:45.633030 [ANA_INIT] flow end
652 10:06:45.636219 ============ LP4 DIFF to SE enter ============
653 10:06:45.639481 ============ LP4 DIFF to SE exit ============
654 10:06:45.642824 [ANA_INIT] <<<<<<<<<<<<<
655 10:06:45.646094 [Flow] Enable top DCM control >>>>>
656 10:06:45.650143 [Flow] Enable top DCM control <<<<<
657 10:06:45.653248 Enable DLL master slave shuffle
658 10:06:45.656672 ==============================================================
659 10:06:45.659653 Gating Mode config
660 10:06:45.663463 ==============================================================
661 10:06:45.667153 Config description:
662 10:06:45.678103 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
663 10:06:45.685048 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
664 10:06:45.688639 SELPH_MODE 0: By rank 1: By Phase
665 10:06:45.692181 ==============================================================
666 10:06:45.695913 GAT_TRACK_EN = 1
667 10:06:45.699775 RX_GATING_MODE = 2
668 10:06:45.703371 RX_GATING_TRACK_MODE = 2
669 10:06:45.706859 SELPH_MODE = 1
670 10:06:45.710312 PICG_EARLY_EN = 1
671 10:06:45.710438 VALID_LAT_VALUE = 1
672 10:06:45.718338 ==============================================================
673 10:06:45.721604 Enter into Gating configuration >>>>
674 10:06:45.725411 Exit from Gating configuration <<<<
675 10:06:45.725513 Enter into DVFS_PRE_config >>>>>
676 10:06:45.736578 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
677 10:06:45.740453 Exit from DVFS_PRE_config <<<<<
678 10:06:45.744054 Enter into PICG configuration >>>>
679 10:06:45.747756 Exit from PICG configuration <<<<
680 10:06:45.752017 [RX_INPUT] configuration >>>>>
681 10:06:45.752106 [RX_INPUT] configuration <<<<<
682 10:06:45.759179 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
683 10:06:45.763181 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
684 10:06:45.770258 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
685 10:06:45.777793 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
686 10:06:45.781534 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
687 10:06:45.789295 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
688 10:06:45.792704 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
689 10:06:45.796816 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
690 10:06:45.800300 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
691 10:06:45.803850 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
692 10:06:45.807549 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
693 10:06:45.814920 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
694 10:06:45.815049 ===================================
695 10:06:45.818478 LPDDR4 DRAM CONFIGURATION
696 10:06:45.822100 ===================================
697 10:06:45.825960 EX_ROW_EN[0] = 0x0
698 10:06:45.826080 EX_ROW_EN[1] = 0x0
699 10:06:45.829739 LP4Y_EN = 0x0
700 10:06:45.829853 WORK_FSP = 0x0
701 10:06:45.829952 WL = 0x2
702 10:06:45.833138 RL = 0x2
703 10:06:45.833248 BL = 0x2
704 10:06:45.836734 RPST = 0x0
705 10:06:45.836852 RD_PRE = 0x0
706 10:06:45.840475 WR_PRE = 0x1
707 10:06:45.840583 WR_PST = 0x0
708 10:06:45.844503 DBI_WR = 0x0
709 10:06:45.844607 DBI_RD = 0x0
710 10:06:45.848132 OTF = 0x1
711 10:06:45.851131 ===================================
712 10:06:45.854878 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
713 10:06:45.858972 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
714 10:06:45.862719 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
715 10:06:45.866418 ===================================
716 10:06:45.870375 LPDDR4 DRAM CONFIGURATION
717 10:06:45.870501 ===================================
718 10:06:45.874072 EX_ROW_EN[0] = 0x10
719 10:06:45.874163 EX_ROW_EN[1] = 0x0
720 10:06:45.878113 LP4Y_EN = 0x0
721 10:06:45.878208 WORK_FSP = 0x0
722 10:06:45.881744 WL = 0x2
723 10:06:45.881846 RL = 0x2
724 10:06:45.885280 BL = 0x2
725 10:06:45.885401 RPST = 0x0
726 10:06:45.889075 RD_PRE = 0x0
727 10:06:45.889193 WR_PRE = 0x1
728 10:06:45.892869 WR_PST = 0x0
729 10:06:45.892989 DBI_WR = 0x0
730 10:06:45.896310 DBI_RD = 0x0
731 10:06:45.896419 OTF = 0x1
732 10:06:45.899903 ===================================
733 10:06:45.907084 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
734 10:06:45.911082 nWR fixed to 40
735 10:06:45.911212 [ModeRegInit_LP4] CH0 RK0
736 10:06:45.914657 [ModeRegInit_LP4] CH0 RK1
737 10:06:45.914751 [ModeRegInit_LP4] CH1 RK0
738 10:06:45.918638 [ModeRegInit_LP4] CH1 RK1
739 10:06:45.922179 match AC timing 13
740 10:06:45.925729 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
741 10:06:45.929689 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
742 10:06:45.933393 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
743 10:06:45.937145 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
744 10:06:45.944254 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
745 10:06:45.944410 [EMI DOE] emi_dcm 0
746 10:06:45.947967 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
747 10:06:45.948082 ==
748 10:06:45.951879 Dram Type= 6, Freq= 0, CH_0, rank 0
749 10:06:45.955592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 10:06:45.955688 ==
751 10:06:45.962652 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 10:06:45.969226 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 10:06:45.977459 [CA 0] Center 37 (7~68) winsize 62
754 10:06:45.980371 [CA 1] Center 38 (7~69) winsize 63
755 10:06:45.983730 [CA 2] Center 35 (5~66) winsize 62
756 10:06:45.987168 [CA 3] Center 35 (5~66) winsize 62
757 10:06:45.990704 [CA 4] Center 35 (4~66) winsize 63
758 10:06:45.993857 [CA 5] Center 33 (3~64) winsize 62
759 10:06:45.993948
760 10:06:45.997193 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 10:06:45.997282
762 10:06:46.000344 [CATrainingPosCal] consider 1 rank data
763 10:06:46.003768 u2DelayCellTimex100 = 270/100 ps
764 10:06:46.007140 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 10:06:46.010456 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
766 10:06:46.017278 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
767 10:06:46.020115 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
768 10:06:46.023743 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
769 10:06:46.026938 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 10:06:46.027037
771 10:06:46.030486 CA PerBit enable=1, Macro0, CA PI delay=33
772 10:06:46.030564
773 10:06:46.033660 [CBTSetCACLKResult] CA Dly = 33
774 10:06:46.033740 CS Dly: 6 (0~37)
775 10:06:46.036896 ==
776 10:06:46.040495 Dram Type= 6, Freq= 0, CH_0, rank 1
777 10:06:46.043770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
778 10:06:46.043879 ==
779 10:06:46.046978 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
780 10:06:46.053601 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
781 10:06:46.063550 [CA 0] Center 38 (7~69) winsize 63
782 10:06:46.067059 [CA 1] Center 38 (8~69) winsize 62
783 10:06:46.070473 [CA 2] Center 36 (5~67) winsize 63
784 10:06:46.073678 [CA 3] Center 35 (5~66) winsize 62
785 10:06:46.077184 [CA 4] Center 35 (4~66) winsize 63
786 10:06:46.080224 [CA 5] Center 34 (4~65) winsize 62
787 10:06:46.080307
788 10:06:46.083697 [CmdBusTrainingLP45] Vref(ca) range 1: 32
789 10:06:46.083797
790 10:06:46.087243 [CATrainingPosCal] consider 2 rank data
791 10:06:46.090338 u2DelayCellTimex100 = 270/100 ps
792 10:06:46.093561 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
793 10:06:46.097091 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
794 10:06:46.103479 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
795 10:06:46.107067 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
796 10:06:46.110288 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
797 10:06:46.113693 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
798 10:06:46.113786
799 10:06:46.116936 CA PerBit enable=1, Macro0, CA PI delay=34
800 10:06:46.117020
801 10:06:46.120509 [CBTSetCACLKResult] CA Dly = 34
802 10:06:46.120613 CS Dly: 6 (0~38)
803 10:06:46.120721
804 10:06:46.123451 ----->DramcWriteLeveling(PI) begin...
805 10:06:46.126999 ==
806 10:06:46.127094 Dram Type= 6, Freq= 0, CH_0, rank 0
807 10:06:46.133706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 10:06:46.133845 ==
809 10:06:46.136829 Write leveling (Byte 0): 33 => 33
810 10:06:46.140214 Write leveling (Byte 1): 29 => 29
811 10:06:46.143614 DramcWriteLeveling(PI) end<-----
812 10:06:46.143710
813 10:06:46.143781 ==
814 10:06:46.147101 Dram Type= 6, Freq= 0, CH_0, rank 0
815 10:06:46.150123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
816 10:06:46.150225 ==
817 10:06:46.154287 [Gating] SW mode calibration
818 10:06:46.161813 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
819 10:06:46.165087 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
820 10:06:46.169068 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
821 10:06:46.172336 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
822 10:06:46.178678 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 10:06:46.182736 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 10:06:46.186037 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 10:06:46.192522 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 10:06:46.195973 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 10:06:46.199434 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 10:06:46.205960 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 10:06:46.209606 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 10:06:46.212590 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 10:06:46.219411 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 10:06:46.222595 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 10:06:46.225935 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 10:06:46.229277 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 10:06:46.236032 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 10:06:46.239568 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
837 10:06:46.242895 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
838 10:06:46.249528 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
839 10:06:46.252433 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 10:06:46.256088 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 10:06:46.262827 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 10:06:46.265952 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 10:06:46.269256 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 10:06:46.275912 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 10:06:46.279219 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
846 10:06:46.282686 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
847 10:06:46.289435 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
848 10:06:46.292267 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 10:06:46.295747 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
850 10:06:46.302515 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 10:06:46.305731 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 10:06:46.309283 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
853 10:06:46.315642 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
854 10:06:46.319298 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (1 1) (1 0)
855 10:06:46.322354 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 10:06:46.329091 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 10:06:46.332308 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 10:06:46.335776 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 10:06:46.342219 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 10:06:46.345585 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 10:06:46.349128 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
862 10:06:46.352587 0 11 8 | B1->B0 | 2626 4444 | 1 0 | (0 0) (0 0)
863 10:06:46.358988 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
864 10:06:46.362683 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 10:06:46.365901 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 10:06:46.372458 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 10:06:46.375947 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 10:06:46.378876 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 10:06:46.385762 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
870 10:06:46.388923 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
871 10:06:46.392111 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 10:06:46.399177 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 10:06:46.402273 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 10:06:46.405899 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 10:06:46.412084 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 10:06:46.415367 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 10:06:46.418903 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 10:06:46.425586 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 10:06:46.428702 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 10:06:46.432221 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 10:06:46.438616 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 10:06:46.442163 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 10:06:46.445229 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 10:06:46.451878 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
885 10:06:46.455579 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
886 10:06:46.458462 Total UI for P1: 0, mck2ui 16
887 10:06:46.462113 best dqsien dly found for B0: ( 0, 14, 0)
888 10:06:46.465600 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 10:06:46.468789 Total UI for P1: 0, mck2ui 16
890 10:06:46.472318 best dqsien dly found for B1: ( 0, 14, 6)
891 10:06:46.475543 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
892 10:06:46.478642 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
893 10:06:46.478761
894 10:06:46.482309 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
895 10:06:46.485426 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
896 10:06:46.488694 [Gating] SW calibration Done
897 10:06:46.488817 ==
898 10:06:46.491957 Dram Type= 6, Freq= 0, CH_0, rank 0
899 10:06:46.498535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 10:06:46.498649 ==
901 10:06:46.498751 RX Vref Scan: 0
902 10:06:46.498847
903 10:06:46.501965 RX Vref 0 -> 0, step: 1
904 10:06:46.502074
905 10:06:46.505123 RX Delay -130 -> 252, step: 16
906 10:06:46.508657 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
907 10:06:46.511935 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
908 10:06:46.515285 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
909 10:06:46.521759 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
910 10:06:46.525382 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
911 10:06:46.528387 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
912 10:06:46.531773 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
913 10:06:46.535069 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
914 10:06:46.541477 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
915 10:06:46.545065 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
916 10:06:46.548222 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
917 10:06:46.551777 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
918 10:06:46.555148 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
919 10:06:46.561679 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
920 10:06:46.564937 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
921 10:06:46.568518 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
922 10:06:46.568628 ==
923 10:06:46.571540 Dram Type= 6, Freq= 0, CH_0, rank 0
924 10:06:46.574869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
925 10:06:46.574987 ==
926 10:06:46.578351 DQS Delay:
927 10:06:46.578463 DQS0 = 0, DQS1 = 0
928 10:06:46.582024 DQM Delay:
929 10:06:46.582128 DQM0 = 93, DQM1 = 83
930 10:06:46.582236 DQ Delay:
931 10:06:46.585267 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
932 10:06:46.588455 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
933 10:06:46.591407 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
934 10:06:46.594935 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
935 10:06:46.595053
936 10:06:46.595170
937 10:06:46.598145 ==
938 10:06:46.601621 Dram Type= 6, Freq= 0, CH_0, rank 0
939 10:06:46.605069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 10:06:46.605222 ==
941 10:06:46.605317
942 10:06:46.605435
943 10:06:46.608350 TX Vref Scan disable
944 10:06:46.608470 == TX Byte 0 ==
945 10:06:46.615148 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
946 10:06:46.618202 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
947 10:06:46.618312 == TX Byte 1 ==
948 10:06:46.624599 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
949 10:06:46.628088 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
950 10:06:46.628210 ==
951 10:06:46.631260 Dram Type= 6, Freq= 0, CH_0, rank 0
952 10:06:46.634831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 10:06:46.634938 ==
954 10:06:46.648627 TX Vref=22, minBit 6, minWin=27, winSum=441
955 10:06:46.651797 TX Vref=24, minBit 6, minWin=27, winSum=441
956 10:06:46.655351 TX Vref=26, minBit 11, minWin=27, winSum=446
957 10:06:46.658315 TX Vref=28, minBit 12, minWin=27, winSum=451
958 10:06:46.662027 TX Vref=30, minBit 11, minWin=27, winSum=455
959 10:06:46.668459 TX Vref=32, minBit 10, minWin=27, winSum=453
960 10:06:46.671711 [TxChooseVref] Worse bit 11, Min win 27, Win sum 455, Final Vref 30
961 10:06:46.671817
962 10:06:46.675149 Final TX Range 1 Vref 30
963 10:06:46.675260
964 10:06:46.675363 ==
965 10:06:46.678643 Dram Type= 6, Freq= 0, CH_0, rank 0
966 10:06:46.681953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 10:06:46.685090 ==
968 10:06:46.685196
969 10:06:46.685293
970 10:06:46.685405 TX Vref Scan disable
971 10:06:46.689202 == TX Byte 0 ==
972 10:06:46.692636 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
973 10:06:46.698901 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
974 10:06:46.699013 == TX Byte 1 ==
975 10:06:46.702271 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
976 10:06:46.705971 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
977 10:06:46.708949
978 10:06:46.709066 [DATLAT]
979 10:06:46.709162 Freq=800, CH0 RK0
980 10:06:46.709258
981 10:06:46.712238 DATLAT Default: 0xa
982 10:06:46.712351 0, 0xFFFF, sum = 0
983 10:06:46.715862 1, 0xFFFF, sum = 0
984 10:06:46.715969 2, 0xFFFF, sum = 0
985 10:06:46.718908 3, 0xFFFF, sum = 0
986 10:06:46.719056 4, 0xFFFF, sum = 0
987 10:06:46.722306 5, 0xFFFF, sum = 0
988 10:06:46.725576 6, 0xFFFF, sum = 0
989 10:06:46.725692 7, 0xFFFF, sum = 0
990 10:06:46.729190 8, 0xFFFF, sum = 0
991 10:06:46.729303 9, 0x0, sum = 1
992 10:06:46.729455 10, 0x0, sum = 2
993 10:06:46.732391 11, 0x0, sum = 3
994 10:06:46.732516 12, 0x0, sum = 4
995 10:06:46.735383 best_step = 10
996 10:06:46.735504
997 10:06:46.735614 ==
998 10:06:46.738638 Dram Type= 6, Freq= 0, CH_0, rank 0
999 10:06:46.742102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 10:06:46.742224 ==
1001 10:06:46.745288 RX Vref Scan: 1
1002 10:06:46.745394
1003 10:06:46.748886 Set Vref Range= 32 -> 127
1004 10:06:46.748995
1005 10:06:46.749063 RX Vref 32 -> 127, step: 1
1006 10:06:46.749195
1007 10:06:46.752074 RX Delay -79 -> 252, step: 8
1008 10:06:46.752147
1009 10:06:46.755476 Set Vref, RX VrefLevel [Byte0]: 32
1010 10:06:46.758576 [Byte1]: 32
1011 10:06:46.758651
1012 10:06:46.762144 Set Vref, RX VrefLevel [Byte0]: 33
1013 10:06:46.765534 [Byte1]: 33
1014 10:06:46.769451
1015 10:06:46.769541 Set Vref, RX VrefLevel [Byte0]: 34
1016 10:06:46.772386 [Byte1]: 34
1017 10:06:46.776737
1018 10:06:46.776841 Set Vref, RX VrefLevel [Byte0]: 35
1019 10:06:46.779945 [Byte1]: 35
1020 10:06:46.784326
1021 10:06:46.784438 Set Vref, RX VrefLevel [Byte0]: 36
1022 10:06:46.787793 [Byte1]: 36
1023 10:06:46.791792
1024 10:06:46.791898 Set Vref, RX VrefLevel [Byte0]: 37
1025 10:06:46.795239 [Byte1]: 37
1026 10:06:46.799777
1027 10:06:46.799897 Set Vref, RX VrefLevel [Byte0]: 38
1028 10:06:46.803394 [Byte1]: 38
1029 10:06:46.806872
1030 10:06:46.806959 Set Vref, RX VrefLevel [Byte0]: 39
1031 10:06:46.810491 [Byte1]: 39
1032 10:06:46.814646
1033 10:06:46.814727 Set Vref, RX VrefLevel [Byte0]: 40
1034 10:06:46.817613 [Byte1]: 40
1035 10:06:46.822496
1036 10:06:46.822571 Set Vref, RX VrefLevel [Byte0]: 41
1037 10:06:46.826165 [Byte1]: 41
1038 10:06:46.829877
1039 10:06:46.829993 Set Vref, RX VrefLevel [Byte0]: 42
1040 10:06:46.833403 [Byte1]: 42
1041 10:06:46.837140
1042 10:06:46.837223 Set Vref, RX VrefLevel [Byte0]: 43
1043 10:06:46.840845 [Byte1]: 43
1044 10:06:46.845549
1045 10:06:46.845636 Set Vref, RX VrefLevel [Byte0]: 44
1046 10:06:46.848584 [Byte1]: 44
1047 10:06:46.852564
1048 10:06:46.852676 Set Vref, RX VrefLevel [Byte0]: 45
1049 10:06:46.855769 [Byte1]: 45
1050 10:06:46.860056
1051 10:06:46.860134 Set Vref, RX VrefLevel [Byte0]: 46
1052 10:06:46.863219 [Byte1]: 46
1053 10:06:46.867550
1054 10:06:46.867655 Set Vref, RX VrefLevel [Byte0]: 47
1055 10:06:46.870634 [Byte1]: 47
1056 10:06:46.874915
1057 10:06:46.874991 Set Vref, RX VrefLevel [Byte0]: 48
1058 10:06:46.878476 [Byte1]: 48
1059 10:06:46.882287
1060 10:06:46.882390 Set Vref, RX VrefLevel [Byte0]: 49
1061 10:06:46.885781 [Byte1]: 49
1062 10:06:46.890235
1063 10:06:46.890342 Set Vref, RX VrefLevel [Byte0]: 50
1064 10:06:46.893451 [Byte1]: 50
1065 10:06:46.897431
1066 10:06:46.897517 Set Vref, RX VrefLevel [Byte0]: 51
1067 10:06:46.900722 [Byte1]: 51
1068 10:06:46.905058
1069 10:06:46.905145 Set Vref, RX VrefLevel [Byte0]: 52
1070 10:06:46.908482 [Byte1]: 52
1071 10:06:46.912500
1072 10:06:46.912612 Set Vref, RX VrefLevel [Byte0]: 53
1073 10:06:46.915836 [Byte1]: 53
1074 10:06:46.920631
1075 10:06:46.920717 Set Vref, RX VrefLevel [Byte0]: 54
1076 10:06:46.923339 [Byte1]: 54
1077 10:06:46.927703
1078 10:06:46.927788 Set Vref, RX VrefLevel [Byte0]: 55
1079 10:06:46.930946 [Byte1]: 55
1080 10:06:46.935331
1081 10:06:46.935417 Set Vref, RX VrefLevel [Byte0]: 56
1082 10:06:46.938548 [Byte1]: 56
1083 10:06:46.942833
1084 10:06:46.942918 Set Vref, RX VrefLevel [Byte0]: 57
1085 10:06:46.945926 [Byte1]: 57
1086 10:06:46.950290
1087 10:06:46.950406 Set Vref, RX VrefLevel [Byte0]: 58
1088 10:06:46.953596 [Byte1]: 58
1089 10:06:46.957800
1090 10:06:46.957933 Set Vref, RX VrefLevel [Byte0]: 59
1091 10:06:46.961349 [Byte1]: 59
1092 10:06:46.965649
1093 10:06:46.965733 Set Vref, RX VrefLevel [Byte0]: 60
1094 10:06:46.968958 [Byte1]: 60
1095 10:06:46.972781
1096 10:06:46.972906 Set Vref, RX VrefLevel [Byte0]: 61
1097 10:06:46.976519 [Byte1]: 61
1098 10:06:46.980716
1099 10:06:46.980828 Set Vref, RX VrefLevel [Byte0]: 62
1100 10:06:46.983719 [Byte1]: 62
1101 10:06:46.988444
1102 10:06:46.988554 Set Vref, RX VrefLevel [Byte0]: 63
1103 10:06:46.991254 [Byte1]: 63
1104 10:06:46.995640
1105 10:06:46.995724 Set Vref, RX VrefLevel [Byte0]: 64
1106 10:06:46.999247 [Byte1]: 64
1107 10:06:47.003283
1108 10:06:47.003370 Set Vref, RX VrefLevel [Byte0]: 65
1109 10:06:47.006793 [Byte1]: 65
1110 10:06:47.011109
1111 10:06:47.011212 Set Vref, RX VrefLevel [Byte0]: 66
1112 10:06:47.014213 [Byte1]: 66
1113 10:06:47.018602
1114 10:06:47.018688 Set Vref, RX VrefLevel [Byte0]: 67
1115 10:06:47.021470 [Byte1]: 67
1116 10:06:47.025922
1117 10:06:47.026009 Set Vref, RX VrefLevel [Byte0]: 68
1118 10:06:47.029051 [Byte1]: 68
1119 10:06:47.033382
1120 10:06:47.033476 Set Vref, RX VrefLevel [Byte0]: 69
1121 10:06:47.036476 [Byte1]: 69
1122 10:06:47.040785
1123 10:06:47.040863 Set Vref, RX VrefLevel [Byte0]: 70
1124 10:06:47.044404 [Byte1]: 70
1125 10:06:47.048496
1126 10:06:47.048610 Set Vref, RX VrefLevel [Byte0]: 71
1127 10:06:47.051862 [Byte1]: 71
1128 10:06:47.056300
1129 10:06:47.056411 Set Vref, RX VrefLevel [Byte0]: 72
1130 10:06:47.059147 [Byte1]: 72
1131 10:06:47.063378
1132 10:06:47.063490 Set Vref, RX VrefLevel [Byte0]: 73
1133 10:06:47.066909 [Byte1]: 73
1134 10:06:47.071453
1135 10:06:47.071539 Set Vref, RX VrefLevel [Byte0]: 74
1136 10:06:47.074450 [Byte1]: 74
1137 10:06:47.078700
1138 10:06:47.078814 Set Vref, RX VrefLevel [Byte0]: 75
1139 10:06:47.082272 [Byte1]: 75
1140 10:06:47.086329
1141 10:06:47.086459 Set Vref, RX VrefLevel [Byte0]: 76
1142 10:06:47.089645 [Byte1]: 76
1143 10:06:47.093693
1144 10:06:47.093804 Set Vref, RX VrefLevel [Byte0]: 77
1145 10:06:47.097172 [Byte1]: 77
1146 10:06:47.101291
1147 10:06:47.101398 Final RX Vref Byte 0 = 62 to rank0
1148 10:06:47.104617 Final RX Vref Byte 1 = 55 to rank0
1149 10:06:47.107832 Final RX Vref Byte 0 = 62 to rank1
1150 10:06:47.111246 Final RX Vref Byte 1 = 55 to rank1==
1151 10:06:47.114676 Dram Type= 6, Freq= 0, CH_0, rank 0
1152 10:06:47.121246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1153 10:06:47.121357 ==
1154 10:06:47.121458 DQS Delay:
1155 10:06:47.121552 DQS0 = 0, DQS1 = 0
1156 10:06:47.124566 DQM Delay:
1157 10:06:47.124674 DQM0 = 93, DQM1 = 82
1158 10:06:47.127967 DQ Delay:
1159 10:06:47.131109 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1160 10:06:47.134742 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1161 10:06:47.138198 DQ8 =76, DQ9 =72, DQ10 =80, DQ11 =76
1162 10:06:47.141279 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1163 10:06:47.141366
1164 10:06:47.141433
1165 10:06:47.147912 [DQSOSCAuto] RK0, (LSB)MR18= 0x3732, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
1166 10:06:47.151070 CH0 RK0: MR19=606, MR18=3732
1167 10:06:47.158083 CH0_RK0: MR19=0x606, MR18=0x3732, DQSOSC=395, MR23=63, INC=94, DEC=63
1168 10:06:47.158194
1169 10:06:47.161126 ----->DramcWriteLeveling(PI) begin...
1170 10:06:47.161243 ==
1171 10:06:47.164432 Dram Type= 6, Freq= 0, CH_0, rank 1
1172 10:06:47.167909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1173 10:06:47.168027 ==
1174 10:06:47.171463 Write leveling (Byte 0): 35 => 35
1175 10:06:47.174641 Write leveling (Byte 1): 29 => 29
1176 10:06:47.177811 DramcWriteLeveling(PI) end<-----
1177 10:06:47.177930
1178 10:06:47.178036 ==
1179 10:06:47.181472 Dram Type= 6, Freq= 0, CH_0, rank 1
1180 10:06:47.184474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 10:06:47.184587 ==
1182 10:06:47.187931 [Gating] SW mode calibration
1183 10:06:47.194709 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1184 10:06:47.201064 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1185 10:06:47.204287 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1186 10:06:47.207668 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1187 10:06:47.214586 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 10:06:47.217574 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 10:06:47.221285 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 10:06:47.268416 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 10:06:47.268559 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 10:06:47.268956 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 10:06:47.269215 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 10:06:47.269286 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 10:06:47.269362 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 10:06:47.269431 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 10:06:47.269506 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 10:06:47.269584 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 10:06:47.269829 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 10:06:47.298598 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 10:06:47.298738 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 10:06:47.299026 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1203 10:06:47.299126 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1204 10:06:47.299408 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 10:06:47.299984 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 10:06:47.300085 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 10:06:47.302580 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 10:06:47.305732 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 10:06:47.308908 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 10:06:47.315523 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1211 10:06:47.318858 0 9 8 | B1->B0 | 2c2c 3333 | 0 0 | (0 0) (0 0)
1212 10:06:47.322222 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1213 10:06:47.328943 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1214 10:06:47.332380 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1215 10:06:47.335838 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1216 10:06:47.342341 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1217 10:06:47.345604 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 10:06:47.349061 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1219 10:06:47.355536 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
1220 10:06:47.358801 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 10:06:47.362313 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 10:06:47.368979 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 10:06:47.372078 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 10:06:47.375571 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 10:06:47.382047 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 10:06:47.385353 0 11 4 | B1->B0 | 2424 3231 | 0 1 | (0 0) (0 0)
1227 10:06:47.388672 0 11 8 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
1228 10:06:47.395407 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1229 10:06:47.398766 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1230 10:06:47.402327 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1231 10:06:47.405869 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 10:06:47.412395 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 10:06:47.416445 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 10:06:47.419968 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1235 10:06:47.423421 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1236 10:06:47.429519 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 10:06:47.433103 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 10:06:47.437083 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 10:06:47.443324 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 10:06:47.446894 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 10:06:47.449949 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 10:06:47.456669 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 10:06:47.459949 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 10:06:47.463102 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 10:06:47.469670 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 10:06:47.473106 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 10:06:47.476565 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 10:06:47.483060 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 10:06:47.486287 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 10:06:47.489832 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1251 10:06:47.496432 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 10:06:47.496520 Total UI for P1: 0, mck2ui 16
1253 10:06:47.499674 best dqsien dly found for B0: ( 0, 14, 4)
1254 10:06:47.502868 Total UI for P1: 0, mck2ui 16
1255 10:06:47.506503 best dqsien dly found for B1: ( 0, 14, 4)
1256 10:06:47.509633 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1257 10:06:47.516308 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1258 10:06:47.516425
1259 10:06:47.519844 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1260 10:06:47.522875 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1261 10:06:47.526567 [Gating] SW calibration Done
1262 10:06:47.526675 ==
1263 10:06:47.529854 Dram Type= 6, Freq= 0, CH_0, rank 1
1264 10:06:47.532905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1265 10:06:47.532993 ==
1266 10:06:47.533060 RX Vref Scan: 0
1267 10:06:47.536385
1268 10:06:47.536470 RX Vref 0 -> 0, step: 1
1269 10:06:47.536538
1270 10:06:47.539386 RX Delay -130 -> 252, step: 16
1271 10:06:47.542880 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1272 10:06:47.546064 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1273 10:06:47.552878 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1274 10:06:47.556204 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1275 10:06:47.559463 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1276 10:06:47.563070 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1277 10:06:47.566224 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1278 10:06:47.572542 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1279 10:06:47.576220 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1280 10:06:47.579480 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1281 10:06:47.582892 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1282 10:06:47.586350 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1283 10:06:47.592734 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1284 10:06:47.596304 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1285 10:06:47.599337 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1286 10:06:47.602928 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1287 10:06:47.603016 ==
1288 10:06:47.606208 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 10:06:47.612511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 10:06:47.612598 ==
1291 10:06:47.612666 DQS Delay:
1292 10:06:47.615979 DQS0 = 0, DQS1 = 0
1293 10:06:47.616088 DQM Delay:
1294 10:06:47.616157 DQM0 = 90, DQM1 = 83
1295 10:06:47.619472 DQ Delay:
1296 10:06:47.622810 DQ0 =85, DQ1 =93, DQ2 =93, DQ3 =77
1297 10:06:47.625799 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1298 10:06:47.629447 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1299 10:06:47.632722 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1300 10:06:47.632826
1301 10:06:47.632913
1302 10:06:47.632978 ==
1303 10:06:47.635846 Dram Type= 6, Freq= 0, CH_0, rank 1
1304 10:06:47.639370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1305 10:06:47.639457 ==
1306 10:06:47.639526
1307 10:06:47.639589
1308 10:06:47.642546 TX Vref Scan disable
1309 10:06:47.645919 == TX Byte 0 ==
1310 10:06:47.649214 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1311 10:06:47.652337 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1312 10:06:47.655765 == TX Byte 1 ==
1313 10:06:47.659316 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1314 10:06:47.662563 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1315 10:06:47.662649 ==
1316 10:06:47.665738 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 10:06:47.669167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 10:06:47.672270 ==
1319 10:06:47.684672 TX Vref=22, minBit 0, minWin=27, winSum=439
1320 10:06:47.687622 TX Vref=24, minBit 1, minWin=27, winSum=445
1321 10:06:47.690985 TX Vref=26, minBit 8, minWin=27, winSum=450
1322 10:06:47.694186 TX Vref=28, minBit 8, minWin=27, winSum=452
1323 10:06:47.697566 TX Vref=30, minBit 10, minWin=27, winSum=456
1324 10:06:47.704341 TX Vref=32, minBit 6, minWin=28, winSum=456
1325 10:06:47.707750 [TxChooseVref] Worse bit 6, Min win 28, Win sum 456, Final Vref 32
1326 10:06:47.707830
1327 10:06:47.711087 Final TX Range 1 Vref 32
1328 10:06:47.711163
1329 10:06:47.711227 ==
1330 10:06:47.714381 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 10:06:47.717635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 10:06:47.717724 ==
1333 10:06:47.720987
1334 10:06:47.721070
1335 10:06:47.721133 TX Vref Scan disable
1336 10:06:47.724862 == TX Byte 0 ==
1337 10:06:47.727908 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1338 10:06:47.734279 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1339 10:06:47.734361 == TX Byte 1 ==
1340 10:06:47.738036 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1341 10:06:47.744436 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1342 10:06:47.744527
1343 10:06:47.744594 [DATLAT]
1344 10:06:47.744665 Freq=800, CH0 RK1
1345 10:06:47.744737
1346 10:06:47.747984 DATLAT Default: 0xa
1347 10:06:47.748088 0, 0xFFFF, sum = 0
1348 10:06:47.751161 1, 0xFFFF, sum = 0
1349 10:06:47.751271 2, 0xFFFF, sum = 0
1350 10:06:47.754330 3, 0xFFFF, sum = 0
1351 10:06:47.754433 4, 0xFFFF, sum = 0
1352 10:06:47.757862 5, 0xFFFF, sum = 0
1353 10:06:47.760936 6, 0xFFFF, sum = 0
1354 10:06:47.761043 7, 0xFFFF, sum = 0
1355 10:06:47.764356 8, 0xFFFF, sum = 0
1356 10:06:47.764459 9, 0x0, sum = 1
1357 10:06:47.764527 10, 0x0, sum = 2
1358 10:06:47.767897 11, 0x0, sum = 3
1359 10:06:47.767983 12, 0x0, sum = 4
1360 10:06:47.771034 best_step = 10
1361 10:06:47.771127
1362 10:06:47.771193 ==
1363 10:06:47.774447 Dram Type= 6, Freq= 0, CH_0, rank 1
1364 10:06:47.777654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1365 10:06:47.777728 ==
1366 10:06:47.780793 RX Vref Scan: 0
1367 10:06:47.780878
1368 10:06:47.780944 RX Vref 0 -> 0, step: 1
1369 10:06:47.784141
1370 10:06:47.784212 RX Delay -79 -> 252, step: 8
1371 10:06:47.791206 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1372 10:06:47.794450 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1373 10:06:47.797598 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1374 10:06:47.801321 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1375 10:06:47.804234 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1376 10:06:47.810916 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1377 10:06:47.814429 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1378 10:06:47.817553 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1379 10:06:47.821158 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1380 10:06:47.824419 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1381 10:06:47.831081 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1382 10:06:47.834613 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1383 10:06:47.837672 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1384 10:06:47.840922 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1385 10:06:47.847502 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1386 10:06:47.850998 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1387 10:06:47.851081 ==
1388 10:06:47.854417 Dram Type= 6, Freq= 0, CH_0, rank 1
1389 10:06:47.857705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1390 10:06:47.857790 ==
1391 10:06:47.857856 DQS Delay:
1392 10:06:47.861132 DQS0 = 0, DQS1 = 0
1393 10:06:47.861216 DQM Delay:
1394 10:06:47.864165 DQM0 = 91, DQM1 = 83
1395 10:06:47.864248 DQ Delay:
1396 10:06:47.867598 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1397 10:06:47.871008 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1398 10:06:47.874481 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =80
1399 10:06:47.877615 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1400 10:06:47.877698
1401 10:06:47.877764
1402 10:06:47.887713 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
1403 10:06:47.887799 CH0 RK1: MR19=606, MR18=3E19
1404 10:06:47.894478 CH0_RK1: MR19=0x606, MR18=0x3E19, DQSOSC=394, MR23=63, INC=95, DEC=63
1405 10:06:47.897362 [RxdqsGatingPostProcess] freq 800
1406 10:06:47.904041 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1407 10:06:47.907532 Pre-setting of DQS Precalculation
1408 10:06:47.910965 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1409 10:06:47.911049 ==
1410 10:06:47.914127 Dram Type= 6, Freq= 0, CH_1, rank 0
1411 10:06:47.917440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 10:06:47.920956 ==
1413 10:06:47.924396 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1414 10:06:47.930439 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1415 10:06:47.939368 [CA 0] Center 36 (6~67) winsize 62
1416 10:06:47.943032 [CA 1] Center 36 (6~67) winsize 62
1417 10:06:47.946322 [CA 2] Center 35 (5~65) winsize 61
1418 10:06:47.949405 [CA 3] Center 34 (3~65) winsize 63
1419 10:06:47.952911 [CA 4] Center 34 (3~65) winsize 63
1420 10:06:47.956055 [CA 5] Center 33 (3~64) winsize 62
1421 10:06:47.956143
1422 10:06:47.959367 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1423 10:06:47.959456
1424 10:06:47.962792 [CATrainingPosCal] consider 1 rank data
1425 10:06:47.966268 u2DelayCellTimex100 = 270/100 ps
1426 10:06:47.969371 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1427 10:06:47.972819 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1428 10:06:47.979399 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1429 10:06:47.982962 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1430 10:06:47.986092 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1431 10:06:47.989225 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1432 10:06:47.989309
1433 10:06:47.993060 CA PerBit enable=1, Macro0, CA PI delay=33
1434 10:06:47.993139
1435 10:06:47.996257 [CBTSetCACLKResult] CA Dly = 33
1436 10:06:47.996343 CS Dly: 5 (0~36)
1437 10:06:47.999120 ==
1438 10:06:48.002943 Dram Type= 6, Freq= 0, CH_1, rank 1
1439 10:06:48.006080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 10:06:48.006172 ==
1441 10:06:48.009741 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1442 10:06:48.015854 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1443 10:06:48.025972 [CA 0] Center 36 (6~67) winsize 62
1444 10:06:48.029066 [CA 1] Center 37 (6~68) winsize 63
1445 10:06:48.032518 [CA 2] Center 35 (4~66) winsize 63
1446 10:06:48.035688 [CA 3] Center 34 (4~65) winsize 62
1447 10:06:48.039106 [CA 4] Center 34 (4~65) winsize 62
1448 10:06:48.042316 [CA 5] Center 34 (4~64) winsize 61
1449 10:06:48.042398
1450 10:06:48.045620 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1451 10:06:48.045698
1452 10:06:48.049155 [CATrainingPosCal] consider 2 rank data
1453 10:06:48.052252 u2DelayCellTimex100 = 270/100 ps
1454 10:06:48.055588 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1455 10:06:48.062520 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1456 10:06:48.065622 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1457 10:06:48.069704 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1458 10:06:48.073225 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1459 10:06:48.076669 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1460 10:06:48.076785
1461 10:06:48.080173 CA PerBit enable=1, Macro0, CA PI delay=34
1462 10:06:48.080270
1463 10:06:48.084202 [CBTSetCACLKResult] CA Dly = 34
1464 10:06:48.084282 CS Dly: 6 (0~38)
1465 10:06:48.084350
1466 10:06:48.087398 ----->DramcWriteLeveling(PI) begin...
1467 10:06:48.087478 ==
1468 10:06:48.091097 Dram Type= 6, Freq= 0, CH_1, rank 0
1469 10:06:48.094504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1470 10:06:48.094587 ==
1471 10:06:48.098107 Write leveling (Byte 0): 28 => 28
1472 10:06:48.101615 Write leveling (Byte 1): 29 => 29
1473 10:06:48.105098 DramcWriteLeveling(PI) end<-----
1474 10:06:48.105188
1475 10:06:48.105260 ==
1476 10:06:48.108677 Dram Type= 6, Freq= 0, CH_1, rank 0
1477 10:06:48.111618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1478 10:06:48.111729 ==
1479 10:06:48.114991 [Gating] SW mode calibration
1480 10:06:48.121747 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1481 10:06:48.128273 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1482 10:06:48.131451 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1483 10:06:48.134839 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1484 10:06:48.141697 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 10:06:48.144631 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 10:06:48.148281 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 10:06:48.154647 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 10:06:48.158072 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 10:06:48.161585 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 10:06:48.167937 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 10:06:48.171633 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 10:06:48.175044 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 10:06:48.181318 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 10:06:48.184553 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 10:06:48.188194 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 10:06:48.194862 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 10:06:48.197839 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 10:06:48.201218 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1499 10:06:48.208239 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1500 10:06:48.211490 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 10:06:48.214495 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 10:06:48.217984 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 10:06:48.224417 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 10:06:48.228044 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 10:06:48.231546 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 10:06:48.237687 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 10:06:48.241139 0 9 4 | B1->B0 | 2424 2929 | 0 0 | (1 1) (0 0)
1508 10:06:48.244663 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1509 10:06:48.251276 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1510 10:06:48.254324 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1511 10:06:48.257819 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1512 10:06:48.264404 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1513 10:06:48.267770 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1514 10:06:48.271329 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 10:06:48.277792 0 10 4 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
1516 10:06:48.280865 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 10:06:48.284433 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 10:06:48.290896 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 10:06:48.294611 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 10:06:48.297772 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 10:06:48.304292 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 10:06:48.307847 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 10:06:48.311353 0 11 4 | B1->B0 | 3131 3d3d | 1 0 | (0 0) (1 1)
1524 10:06:48.318021 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 10:06:48.320896 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 10:06:48.324466 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 10:06:48.331143 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 10:06:48.334414 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1529 10:06:48.337858 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 10:06:48.344327 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 10:06:48.347499 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1532 10:06:48.350475 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1533 10:06:48.357487 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 10:06:48.360861 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 10:06:48.364046 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 10:06:48.367471 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 10:06:48.373899 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 10:06:48.376987 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 10:06:48.380612 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 10:06:48.387271 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 10:06:48.390371 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 10:06:48.393858 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 10:06:48.400502 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 10:06:48.403575 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 10:06:48.407086 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 10:06:48.413778 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 10:06:48.417162 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1548 10:06:48.420637 Total UI for P1: 0, mck2ui 16
1549 10:06:48.423697 best dqsien dly found for B1: ( 0, 14, 2)
1550 10:06:48.427199 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 10:06:48.430397 Total UI for P1: 0, mck2ui 16
1552 10:06:48.433653 best dqsien dly found for B0: ( 0, 14, 4)
1553 10:06:48.437283 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1554 10:06:48.440345 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1555 10:06:48.440431
1556 10:06:48.447019 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1557 10:06:48.450208 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1558 10:06:48.450296 [Gating] SW calibration Done
1559 10:06:48.453635 ==
1560 10:06:48.453721 Dram Type= 6, Freq= 0, CH_1, rank 0
1561 10:06:48.460353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1562 10:06:48.460440 ==
1563 10:06:48.460520 RX Vref Scan: 0
1564 10:06:48.460585
1565 10:06:48.463608 RX Vref 0 -> 0, step: 1
1566 10:06:48.463721
1567 10:06:48.467139 RX Delay -130 -> 252, step: 16
1568 10:06:48.470210 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1569 10:06:48.473428 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1570 10:06:48.477272 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1571 10:06:48.483738 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1572 10:06:48.486793 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1573 10:06:48.490017 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1574 10:06:48.493305 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1575 10:06:48.496658 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1576 10:06:48.503448 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1577 10:06:48.506621 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1578 10:06:48.510080 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1579 10:06:48.513731 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1580 10:06:48.519916 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1581 10:06:48.523399 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1582 10:06:48.526727 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1583 10:06:48.530312 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1584 10:06:48.530400 ==
1585 10:06:48.533333 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 10:06:48.536539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 10:06:48.539929 ==
1588 10:06:48.540016 DQS Delay:
1589 10:06:48.540084 DQS0 = 0, DQS1 = 0
1590 10:06:48.543686 DQM Delay:
1591 10:06:48.543759 DQM0 = 86, DQM1 = 81
1592 10:06:48.546833 DQ Delay:
1593 10:06:48.549871 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1594 10:06:48.549957 DQ4 =77, DQ5 =93, DQ6 =101, DQ7 =85
1595 10:06:48.553505 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1596 10:06:48.559671 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1597 10:06:48.559757
1598 10:06:48.559825
1599 10:06:48.559888 ==
1600 10:06:48.563252 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 10:06:48.566438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 10:06:48.566525 ==
1603 10:06:48.566593
1604 10:06:48.566656
1605 10:06:48.569757 TX Vref Scan disable
1606 10:06:48.569843 == TX Byte 0 ==
1607 10:06:48.576621 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1608 10:06:48.579703 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1609 10:06:48.579816 == TX Byte 1 ==
1610 10:06:48.586385 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1611 10:06:48.590069 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1612 10:06:48.590185 ==
1613 10:06:48.593165 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 10:06:48.596239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 10:06:48.596319 ==
1616 10:06:48.610079 TX Vref=22, minBit 8, minWin=27, winSum=444
1617 10:06:48.613462 TX Vref=24, minBit 10, minWin=27, winSum=452
1618 10:06:48.616894 TX Vref=26, minBit 15, minWin=27, winSum=456
1619 10:06:48.620052 TX Vref=28, minBit 15, minWin=27, winSum=458
1620 10:06:48.623218 TX Vref=30, minBit 15, minWin=27, winSum=456
1621 10:06:48.629837 TX Vref=32, minBit 8, minWin=28, winSum=458
1622 10:06:48.633186 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
1623 10:06:48.633276
1624 10:06:48.636755 Final TX Range 1 Vref 32
1625 10:06:48.636882
1626 10:06:48.636950 ==
1627 10:06:48.639735 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 10:06:48.646202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 10:06:48.646324 ==
1630 10:06:48.646422
1631 10:06:48.646522
1632 10:06:48.646613 TX Vref Scan disable
1633 10:06:48.650764 == TX Byte 0 ==
1634 10:06:48.654010 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1635 10:06:48.657050 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1636 10:06:48.660749 == TX Byte 1 ==
1637 10:06:48.663832 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1638 10:06:48.667294 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1639 10:06:48.667432
1640 10:06:48.670550 [DATLAT]
1641 10:06:48.670657 Freq=800, CH1 RK0
1642 10:06:48.670784
1643 10:06:48.674045 DATLAT Default: 0xa
1644 10:06:48.674152 0, 0xFFFF, sum = 0
1645 10:06:48.677378 1, 0xFFFF, sum = 0
1646 10:06:48.677468 2, 0xFFFF, sum = 0
1647 10:06:48.680609 3, 0xFFFF, sum = 0
1648 10:06:48.680716 4, 0xFFFF, sum = 0
1649 10:06:48.683602 5, 0xFFFF, sum = 0
1650 10:06:48.683711 6, 0xFFFF, sum = 0
1651 10:06:48.686893 7, 0xFFFF, sum = 0
1652 10:06:48.687010 8, 0xFFFF, sum = 0
1653 10:06:48.690477 9, 0x0, sum = 1
1654 10:06:48.690597 10, 0x0, sum = 2
1655 10:06:48.693843 11, 0x0, sum = 3
1656 10:06:48.693968 12, 0x0, sum = 4
1657 10:06:48.697063 best_step = 10
1658 10:06:48.697154
1659 10:06:48.697220 ==
1660 10:06:48.700430 Dram Type= 6, Freq= 0, CH_1, rank 0
1661 10:06:48.703688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1662 10:06:48.703785 ==
1663 10:06:48.706981 RX Vref Scan: 1
1664 10:06:48.707055
1665 10:06:48.707118 Set Vref Range= 32 -> 127
1666 10:06:48.707193
1667 10:06:48.710512 RX Vref 32 -> 127, step: 1
1668 10:06:48.710584
1669 10:06:48.713756 RX Delay -95 -> 252, step: 8
1670 10:06:48.713829
1671 10:06:48.717063 Set Vref, RX VrefLevel [Byte0]: 32
1672 10:06:48.720358 [Byte1]: 32
1673 10:06:48.720474
1674 10:06:48.723802 Set Vref, RX VrefLevel [Byte0]: 33
1675 10:06:48.727223 [Byte1]: 33
1676 10:06:48.730663
1677 10:06:48.730750 Set Vref, RX VrefLevel [Byte0]: 34
1678 10:06:48.733947 [Byte1]: 34
1679 10:06:48.738085
1680 10:06:48.738165 Set Vref, RX VrefLevel [Byte0]: 35
1681 10:06:48.741611 [Byte1]: 35
1682 10:06:48.745792
1683 10:06:48.745899 Set Vref, RX VrefLevel [Byte0]: 36
1684 10:06:48.749200 [Byte1]: 36
1685 10:06:48.753279
1686 10:06:48.753356 Set Vref, RX VrefLevel [Byte0]: 37
1687 10:06:48.757017 [Byte1]: 37
1688 10:06:48.760772
1689 10:06:48.760888 Set Vref, RX VrefLevel [Byte0]: 38
1690 10:06:48.764335 [Byte1]: 38
1691 10:06:48.768710
1692 10:06:48.768811 Set Vref, RX VrefLevel [Byte0]: 39
1693 10:06:48.771813 [Byte1]: 39
1694 10:06:48.776292
1695 10:06:48.776409 Set Vref, RX VrefLevel [Byte0]: 40
1696 10:06:48.779413 [Byte1]: 40
1697 10:06:48.783620
1698 10:06:48.783712 Set Vref, RX VrefLevel [Byte0]: 41
1699 10:06:48.786991 [Byte1]: 41
1700 10:06:48.791449
1701 10:06:48.791540 Set Vref, RX VrefLevel [Byte0]: 42
1702 10:06:48.794435 [Byte1]: 42
1703 10:06:48.799156
1704 10:06:48.799256 Set Vref, RX VrefLevel [Byte0]: 43
1705 10:06:48.802171 [Byte1]: 43
1706 10:06:48.806405
1707 10:06:48.806486 Set Vref, RX VrefLevel [Byte0]: 44
1708 10:06:48.809900 [Byte1]: 44
1709 10:06:48.814378
1710 10:06:48.814453 Set Vref, RX VrefLevel [Byte0]: 45
1711 10:06:48.817487 [Byte1]: 45
1712 10:06:48.821847
1713 10:06:48.821924 Set Vref, RX VrefLevel [Byte0]: 46
1714 10:06:48.824963 [Byte1]: 46
1715 10:06:48.829231
1716 10:06:48.829351 Set Vref, RX VrefLevel [Byte0]: 47
1717 10:06:48.832896 [Byte1]: 47
1718 10:06:48.837004
1719 10:06:48.837090 Set Vref, RX VrefLevel [Byte0]: 48
1720 10:06:48.840284 [Byte1]: 48
1721 10:06:48.844329
1722 10:06:48.844415 Set Vref, RX VrefLevel [Byte0]: 49
1723 10:06:48.847894 [Byte1]: 49
1724 10:06:48.852289
1725 10:06:48.852376 Set Vref, RX VrefLevel [Byte0]: 50
1726 10:06:48.855360 [Byte1]: 50
1727 10:06:48.859780
1728 10:06:48.859893 Set Vref, RX VrefLevel [Byte0]: 51
1729 10:06:48.862871 [Byte1]: 51
1730 10:06:48.867343
1731 10:06:48.867429 Set Vref, RX VrefLevel [Byte0]: 52
1732 10:06:48.870566 [Byte1]: 52
1733 10:06:48.874952
1734 10:06:48.875037 Set Vref, RX VrefLevel [Byte0]: 53
1735 10:06:48.878206 [Byte1]: 53
1736 10:06:48.882364
1737 10:06:48.882479 Set Vref, RX VrefLevel [Byte0]: 54
1738 10:06:48.886074 [Byte1]: 54
1739 10:06:48.890191
1740 10:06:48.890311 Set Vref, RX VrefLevel [Byte0]: 55
1741 10:06:48.893356 [Byte1]: 55
1742 10:06:48.897720
1743 10:06:48.897839 Set Vref, RX VrefLevel [Byte0]: 56
1744 10:06:48.901005 [Byte1]: 56
1745 10:06:48.905270
1746 10:06:48.905364 Set Vref, RX VrefLevel [Byte0]: 57
1747 10:06:48.908718 [Byte1]: 57
1748 10:06:48.912960
1749 10:06:48.913050 Set Vref, RX VrefLevel [Byte0]: 58
1750 10:06:48.916080 [Byte1]: 58
1751 10:06:48.920436
1752 10:06:48.920554 Set Vref, RX VrefLevel [Byte0]: 59
1753 10:06:48.924000 [Byte1]: 59
1754 10:06:48.928187
1755 10:06:48.928272 Set Vref, RX VrefLevel [Byte0]: 60
1756 10:06:48.931593 [Byte1]: 60
1757 10:06:48.935862
1758 10:06:48.935949 Set Vref, RX VrefLevel [Byte0]: 61
1759 10:06:48.939009 [Byte1]: 61
1760 10:06:48.943181
1761 10:06:48.943267 Set Vref, RX VrefLevel [Byte0]: 62
1762 10:06:48.946547 [Byte1]: 62
1763 10:06:48.950700
1764 10:06:48.950787 Set Vref, RX VrefLevel [Byte0]: 63
1765 10:06:48.954264 [Byte1]: 63
1766 10:06:48.958297
1767 10:06:48.958397 Set Vref, RX VrefLevel [Byte0]: 64
1768 10:06:48.961874 [Byte1]: 64
1769 10:06:48.966198
1770 10:06:48.966284 Set Vref, RX VrefLevel [Byte0]: 65
1771 10:06:48.969343 [Byte1]: 65
1772 10:06:48.973794
1773 10:06:48.973907 Set Vref, RX VrefLevel [Byte0]: 66
1774 10:06:48.976798 [Byte1]: 66
1775 10:06:48.981388
1776 10:06:48.981501 Set Vref, RX VrefLevel [Byte0]: 67
1777 10:06:48.984552 [Byte1]: 67
1778 10:06:48.988628
1779 10:06:48.988749 Set Vref, RX VrefLevel [Byte0]: 68
1780 10:06:48.992311 [Byte1]: 68
1781 10:06:48.996216
1782 10:06:48.996325 Set Vref, RX VrefLevel [Byte0]: 69
1783 10:06:48.999566 [Byte1]: 69
1784 10:06:49.003836
1785 10:06:49.003945 Set Vref, RX VrefLevel [Byte0]: 70
1786 10:06:49.007384 [Byte1]: 70
1787 10:06:49.011867
1788 10:06:49.011976 Set Vref, RX VrefLevel [Byte0]: 71
1789 10:06:49.014758 [Byte1]: 71
1790 10:06:49.019162
1791 10:06:49.019247 Set Vref, RX VrefLevel [Byte0]: 72
1792 10:06:49.022677 [Byte1]: 72
1793 10:06:49.027229
1794 10:06:49.027314 Set Vref, RX VrefLevel [Byte0]: 73
1795 10:06:49.030170 [Byte1]: 73
1796 10:06:49.034400
1797 10:06:49.034521 Set Vref, RX VrefLevel [Byte0]: 74
1798 10:06:49.038030 [Byte1]: 74
1799 10:06:49.041993
1800 10:06:49.042081 Set Vref, RX VrefLevel [Byte0]: 75
1801 10:06:49.045534 [Byte1]: 75
1802 10:06:49.049754
1803 10:06:49.049870 Set Vref, RX VrefLevel [Byte0]: 76
1804 10:06:49.052824 [Byte1]: 76
1805 10:06:49.057220
1806 10:06:49.057303 Set Vref, RX VrefLevel [Byte0]: 77
1807 10:06:49.060478 [Byte1]: 77
1808 10:06:49.064808
1809 10:06:49.064895 Set Vref, RX VrefLevel [Byte0]: 78
1810 10:06:49.068404 [Byte1]: 78
1811 10:06:49.072406
1812 10:06:49.072524 Set Vref, RX VrefLevel [Byte0]: 79
1813 10:06:49.075899 [Byte1]: 79
1814 10:06:49.079866
1815 10:06:49.079978 Final RX Vref Byte 0 = 51 to rank0
1816 10:06:49.083503 Final RX Vref Byte 1 = 62 to rank0
1817 10:06:49.086579 Final RX Vref Byte 0 = 51 to rank1
1818 10:06:49.089794 Final RX Vref Byte 1 = 62 to rank1==
1819 10:06:49.093249 Dram Type= 6, Freq= 0, CH_1, rank 0
1820 10:06:49.099826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1821 10:06:49.099913 ==
1822 10:06:49.100012 DQS Delay:
1823 10:06:49.103213 DQS0 = 0, DQS1 = 0
1824 10:06:49.103305 DQM Delay:
1825 10:06:49.103374 DQM0 = 93, DQM1 = 83
1826 10:06:49.106458 DQ Delay:
1827 10:06:49.109674 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1828 10:06:49.113366 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1829 10:06:49.116450 DQ8 =72, DQ9 =68, DQ10 =88, DQ11 =80
1830 10:06:49.119767 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1831 10:06:49.119849
1832 10:06:49.119920
1833 10:06:49.126327 [DQSOSCAuto] RK0, (LSB)MR18= 0x3350, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1834 10:06:49.129950 CH1 RK0: MR19=606, MR18=3350
1835 10:06:49.136340 CH1_RK0: MR19=0x606, MR18=0x3350, DQSOSC=389, MR23=63, INC=97, DEC=65
1836 10:06:49.136456
1837 10:06:49.139514 ----->DramcWriteLeveling(PI) begin...
1838 10:06:49.139667 ==
1839 10:06:49.143005 Dram Type= 6, Freq= 0, CH_1, rank 1
1840 10:06:49.146162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1841 10:06:49.146249 ==
1842 10:06:49.149586 Write leveling (Byte 0): 26 => 26
1843 10:06:49.152578 Write leveling (Byte 1): 31 => 31
1844 10:06:49.155995 DramcWriteLeveling(PI) end<-----
1845 10:06:49.156089
1846 10:06:49.156158 ==
1847 10:06:49.159379 Dram Type= 6, Freq= 0, CH_1, rank 1
1848 10:06:49.162729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1849 10:06:49.162845 ==
1850 10:06:49.165998 [Gating] SW mode calibration
1851 10:06:49.172730 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1852 10:06:49.179384 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1853 10:06:49.182596 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1854 10:06:49.189550 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1855 10:06:49.192761 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1856 10:06:49.195916 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 10:06:49.202482 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 10:06:49.205949 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 10:06:49.209058 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 10:06:49.215635 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 10:06:49.219241 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 10:06:49.222409 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 10:06:49.229102 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 10:06:49.232225 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 10:06:49.235350 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 10:06:49.242294 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 10:06:49.245350 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 10:06:49.248681 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 10:06:49.255369 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1870 10:06:49.258591 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1871 10:06:49.262132 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1872 10:06:49.265214 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 10:06:49.271904 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 10:06:49.275540 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 10:06:49.278669 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 10:06:49.285325 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 10:06:49.288730 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 10:06:49.292018 0 9 4 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
1879 10:06:49.298736 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1880 10:06:49.301864 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 10:06:49.305317 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1882 10:06:49.312226 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1883 10:06:49.315158 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1884 10:06:49.318898 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1885 10:06:49.325363 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1886 10:06:49.328547 0 10 4 | B1->B0 | 2f2f 3131 | 1 1 | (1 0) (1 1)
1887 10:06:49.332050 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 10:06:49.338544 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 10:06:49.341739 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 10:06:49.345127 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 10:06:49.352099 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 10:06:49.355051 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 10:06:49.358654 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 10:06:49.365368 0 11 4 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
1895 10:06:49.368363 0 11 8 | B1->B0 | 4545 4242 | 0 0 | (0 0) (0 0)
1896 10:06:49.371945 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 10:06:49.378664 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 10:06:49.382226 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 10:06:49.385154 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 10:06:49.388811 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 10:06:49.395065 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 10:06:49.398607 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1903 10:06:49.401595 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1904 10:06:49.408287 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 10:06:49.411907 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 10:06:49.414938 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 10:06:49.421851 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 10:06:49.425225 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 10:06:49.428451 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 10:06:49.435010 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 10:06:49.438118 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 10:06:49.441686 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 10:06:49.448848 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 10:06:49.451558 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 10:06:49.454773 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 10:06:49.461723 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 10:06:49.464817 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 10:06:49.468143 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1919 10:06:49.475175 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 10:06:49.475281 Total UI for P1: 0, mck2ui 16
1921 10:06:49.481518 best dqsien dly found for B0: ( 0, 14, 4)
1922 10:06:49.481604 Total UI for P1: 0, mck2ui 16
1923 10:06:49.485129 best dqsien dly found for B1: ( 0, 14, 4)
1924 10:06:49.491709 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1925 10:06:49.494843 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1926 10:06:49.494928
1927 10:06:49.498366 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1928 10:06:49.501537 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1929 10:06:49.504960 [Gating] SW calibration Done
1930 10:06:49.505046 ==
1931 10:06:49.508226 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 10:06:49.511326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 10:06:49.511444 ==
1934 10:06:49.514869 RX Vref Scan: 0
1935 10:06:49.514977
1936 10:06:49.515072 RX Vref 0 -> 0, step: 1
1937 10:06:49.515177
1938 10:06:49.518037 RX Delay -130 -> 252, step: 16
1939 10:06:49.529948 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1940 10:06:49.530058 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1941 10:06:49.531368 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1942 10:06:49.534942 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1943 10:06:49.538124 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1944 10:06:49.541346 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1945 10:06:49.544603 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1946 10:06:49.551329 iDelay=222, Bit 7, Center 85 (-18 ~ 189) 208
1947 10:06:49.554845 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1948 10:06:49.558354 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1949 10:06:49.561421 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1950 10:06:49.564970 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1951 10:06:49.571178 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1952 10:06:49.574861 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1953 10:06:49.578445 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1954 10:06:49.581626 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1955 10:06:49.581703 ==
1956 10:06:49.584569 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 10:06:49.591213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 10:06:49.591343 ==
1959 10:06:49.591441 DQS Delay:
1960 10:06:49.594637 DQS0 = 0, DQS1 = 0
1961 10:06:49.594726 DQM Delay:
1962 10:06:49.597695 DQM0 = 91, DQM1 = 84
1963 10:06:49.597782 DQ Delay:
1964 10:06:49.601282 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1965 10:06:49.604543 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =85
1966 10:06:49.607985 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1967 10:06:49.611146 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1968 10:06:49.611248
1969 10:06:49.611352
1970 10:06:49.611442 ==
1971 10:06:49.614519 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 10:06:49.617669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 10:06:49.617747 ==
1974 10:06:49.617811
1975 10:06:49.617879
1976 10:06:49.621095 TX Vref Scan disable
1977 10:06:49.624637 == TX Byte 0 ==
1978 10:06:49.627738 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1979 10:06:49.631018 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1980 10:06:49.634401 == TX Byte 1 ==
1981 10:06:49.637458 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1982 10:06:49.640849 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1983 10:06:49.640930 ==
1984 10:06:49.644363 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 10:06:49.647873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 10:06:49.650722 ==
1987 10:06:49.662828 TX Vref=22, minBit 8, minWin=27, winSum=450
1988 10:06:49.666066 TX Vref=24, minBit 8, minWin=27, winSum=450
1989 10:06:49.669200 TX Vref=26, minBit 12, minWin=27, winSum=452
1990 10:06:49.672650 TX Vref=28, minBit 13, minWin=27, winSum=456
1991 10:06:49.675768 TX Vref=30, minBit 8, minWin=28, winSum=459
1992 10:06:49.682663 TX Vref=32, minBit 8, minWin=28, winSum=458
1993 10:06:49.686346 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
1994 10:06:49.686430
1995 10:06:49.689433 Final TX Range 1 Vref 30
1996 10:06:49.689514
1997 10:06:49.689584 ==
1998 10:06:49.692435 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 10:06:49.696267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 10:06:49.699324 ==
2001 10:06:49.699403
2002 10:06:49.699473
2003 10:06:49.699534 TX Vref Scan disable
2004 10:06:49.702889 == TX Byte 0 ==
2005 10:06:49.706015 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2006 10:06:49.712587 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2007 10:06:49.712665 == TX Byte 1 ==
2008 10:06:49.716114 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2009 10:06:49.722645 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2010 10:06:49.722765
2011 10:06:49.722863 [DATLAT]
2012 10:06:49.722958 Freq=800, CH1 RK1
2013 10:06:49.723048
2014 10:06:49.725697 DATLAT Default: 0xa
2015 10:06:49.725806 0, 0xFFFF, sum = 0
2016 10:06:49.729041 1, 0xFFFF, sum = 0
2017 10:06:49.732358 2, 0xFFFF, sum = 0
2018 10:06:49.732473 3, 0xFFFF, sum = 0
2019 10:06:49.736026 4, 0xFFFF, sum = 0
2020 10:06:49.736136 5, 0xFFFF, sum = 0
2021 10:06:49.739372 6, 0xFFFF, sum = 0
2022 10:06:49.739488 7, 0xFFFF, sum = 0
2023 10:06:49.742418 8, 0xFFFF, sum = 0
2024 10:06:49.742542 9, 0x0, sum = 1
2025 10:06:49.745975 10, 0x0, sum = 2
2026 10:06:49.746078 11, 0x0, sum = 3
2027 10:06:49.746173 12, 0x0, sum = 4
2028 10:06:49.749477 best_step = 10
2029 10:06:49.749562
2030 10:06:49.749629 ==
2031 10:06:49.752517 Dram Type= 6, Freq= 0, CH_1, rank 1
2032 10:06:49.756064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2033 10:06:49.756175 ==
2034 10:06:49.759137 RX Vref Scan: 0
2035 10:06:49.759247
2036 10:06:49.759342 RX Vref 0 -> 0, step: 1
2037 10:06:49.762507
2038 10:06:49.762592 RX Delay -95 -> 252, step: 8
2039 10:06:49.769271 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2040 10:06:49.772592 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2041 10:06:49.776154 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2042 10:06:49.779592 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2043 10:06:49.782572 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2044 10:06:49.789319 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2045 10:06:49.793022 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2046 10:06:49.796007 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2047 10:06:49.799435 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2048 10:06:49.802523 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2049 10:06:49.809203 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2050 10:06:49.812384 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2051 10:06:49.815908 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2052 10:06:49.819094 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2053 10:06:49.822561 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2054 10:06:49.829226 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2055 10:06:49.829311 ==
2056 10:06:49.832270 Dram Type= 6, Freq= 0, CH_1, rank 1
2057 10:06:49.835832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2058 10:06:49.835945 ==
2059 10:06:49.836041 DQS Delay:
2060 10:06:49.839430 DQS0 = 0, DQS1 = 0
2061 10:06:49.839533 DQM Delay:
2062 10:06:49.842412 DQM0 = 90, DQM1 = 84
2063 10:06:49.842498 DQ Delay:
2064 10:06:49.845733 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2065 10:06:49.849223 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2066 10:06:49.852403 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2067 10:06:49.855814 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =96
2068 10:06:49.855923
2069 10:06:49.856020
2070 10:06:49.865974 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2071 10:06:49.866104 CH1 RK1: MR19=606, MR18=3C11
2072 10:06:49.872610 CH1_RK1: MR19=0x606, MR18=0x3C11, DQSOSC=394, MR23=63, INC=95, DEC=63
2073 10:06:49.875900 [RxdqsGatingPostProcess] freq 800
2074 10:06:49.882663 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2075 10:06:49.885602 Pre-setting of DQS Precalculation
2076 10:06:49.889129 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2077 10:06:49.895499 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2078 10:06:49.902301 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2079 10:06:49.905502
2080 10:06:49.905631
2081 10:06:49.905746 [Calibration Summary] 1600 Mbps
2082 10:06:49.909006 CH 0, Rank 0
2083 10:06:49.909126 SW Impedance : PASS
2084 10:06:49.912216 DUTY Scan : NO K
2085 10:06:49.915646 ZQ Calibration : PASS
2086 10:06:49.915753 Jitter Meter : NO K
2087 10:06:49.918768 CBT Training : PASS
2088 10:06:49.922046 Write leveling : PASS
2089 10:06:49.922155 RX DQS gating : PASS
2090 10:06:49.925506 RX DQ/DQS(RDDQC) : PASS
2091 10:06:49.928711 TX DQ/DQS : PASS
2092 10:06:49.928814 RX DATLAT : PASS
2093 10:06:49.932253 RX DQ/DQS(Engine): PASS
2094 10:06:49.935310 TX OE : NO K
2095 10:06:49.935418 All Pass.
2096 10:06:49.935521
2097 10:06:49.935623 CH 0, Rank 1
2098 10:06:49.938584 SW Impedance : PASS
2099 10:06:49.941913 DUTY Scan : NO K
2100 10:06:49.942018 ZQ Calibration : PASS
2101 10:06:49.945757 Jitter Meter : NO K
2102 10:06:49.948743 CBT Training : PASS
2103 10:06:49.948833 Write leveling : PASS
2104 10:06:49.952151 RX DQS gating : PASS
2105 10:06:49.952270 RX DQ/DQS(RDDQC) : PASS
2106 10:06:49.955308 TX DQ/DQS : PASS
2107 10:06:49.958748 RX DATLAT : PASS
2108 10:06:49.958858 RX DQ/DQS(Engine): PASS
2109 10:06:49.962140 TX OE : NO K
2110 10:06:49.962246 All Pass.
2111 10:06:49.962353
2112 10:06:49.965246 CH 1, Rank 0
2113 10:06:49.965356 SW Impedance : PASS
2114 10:06:49.968626 DUTY Scan : NO K
2115 10:06:49.971797 ZQ Calibration : PASS
2116 10:06:49.971910 Jitter Meter : NO K
2117 10:06:49.975642 CBT Training : PASS
2118 10:06:49.978609 Write leveling : PASS
2119 10:06:49.978719 RX DQS gating : PASS
2120 10:06:49.982040 RX DQ/DQS(RDDQC) : PASS
2121 10:06:49.985101 TX DQ/DQS : PASS
2122 10:06:49.985185 RX DATLAT : PASS
2123 10:06:49.988375 RX DQ/DQS(Engine): PASS
2124 10:06:49.992083 TX OE : NO K
2125 10:06:49.992192 All Pass.
2126 10:06:49.992300
2127 10:06:49.992402 CH 1, Rank 1
2128 10:06:49.995032 SW Impedance : PASS
2129 10:06:49.998491 DUTY Scan : NO K
2130 10:06:49.998598 ZQ Calibration : PASS
2131 10:06:50.001988 Jitter Meter : NO K
2132 10:06:50.005067 CBT Training : PASS
2133 10:06:50.005166 Write leveling : PASS
2134 10:06:50.008699 RX DQS gating : PASS
2135 10:06:50.008791 RX DQ/DQS(RDDQC) : PASS
2136 10:06:50.011656 TX DQ/DQS : PASS
2137 10:06:50.015244 RX DATLAT : PASS
2138 10:06:50.015329 RX DQ/DQS(Engine): PASS
2139 10:06:50.018457 TX OE : NO K
2140 10:06:50.018542 All Pass.
2141 10:06:50.018608
2142 10:06:50.021936 DramC Write-DBI off
2143 10:06:50.025715 PER_BANK_REFRESH: Hybrid Mode
2144 10:06:50.025801 TX_TRACKING: ON
2145 10:06:50.028553 [GetDramInforAfterCalByMRR] Vendor 6.
2146 10:06:50.031752 [GetDramInforAfterCalByMRR] Revision 606.
2147 10:06:50.035247 [GetDramInforAfterCalByMRR] Revision 2 0.
2148 10:06:50.038456 MR0 0x3b3b
2149 10:06:50.038542 MR8 0x5151
2150 10:06:50.041920 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2151 10:06:50.042005
2152 10:06:50.045221 MR0 0x3b3b
2153 10:06:50.045307 MR8 0x5151
2154 10:06:50.048095 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2155 10:06:50.048206
2156 10:06:50.058176 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2157 10:06:50.061549 [FAST_K] Save calibration result to emmc
2158 10:06:50.064998 [FAST_K] Save calibration result to emmc
2159 10:06:50.068242 dram_init: config_dvfs: 1
2160 10:06:50.071703 dramc_set_vcore_voltage set vcore to 662500
2161 10:06:50.071790 Read voltage for 1200, 2
2162 10:06:50.075098 Vio18 = 0
2163 10:06:50.075184 Vcore = 662500
2164 10:06:50.075251 Vdram = 0
2165 10:06:50.078207 Vddq = 0
2166 10:06:50.078345 Vmddr = 0
2167 10:06:50.081505 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2168 10:06:50.088219 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2169 10:06:50.091377 MEM_TYPE=3, freq_sel=15
2170 10:06:50.094566 sv_algorithm_assistance_LP4_1600
2171 10:06:50.098196 ============ PULL DRAM RESETB DOWN ============
2172 10:06:50.101284 ========== PULL DRAM RESETB DOWN end =========
2173 10:06:50.107989 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2174 10:06:50.111524 ===================================
2175 10:06:50.111680 LPDDR4 DRAM CONFIGURATION
2176 10:06:50.114745 ===================================
2177 10:06:50.118288 EX_ROW_EN[0] = 0x0
2178 10:06:50.118411 EX_ROW_EN[1] = 0x0
2179 10:06:50.121348 LP4Y_EN = 0x0
2180 10:06:50.121471 WORK_FSP = 0x0
2181 10:06:50.124620 WL = 0x4
2182 10:06:50.127825 RL = 0x4
2183 10:06:50.127949 BL = 0x2
2184 10:06:50.131310 RPST = 0x0
2185 10:06:50.131445 RD_PRE = 0x0
2186 10:06:50.134799 WR_PRE = 0x1
2187 10:06:50.134934 WR_PST = 0x0
2188 10:06:50.137776 DBI_WR = 0x0
2189 10:06:50.137889 DBI_RD = 0x0
2190 10:06:50.141450 OTF = 0x1
2191 10:06:50.144337 ===================================
2192 10:06:50.148008 ===================================
2193 10:06:50.148124 ANA top config
2194 10:06:50.151175 ===================================
2195 10:06:50.154826 DLL_ASYNC_EN = 0
2196 10:06:50.157649 ALL_SLAVE_EN = 0
2197 10:06:50.157723 NEW_RANK_MODE = 1
2198 10:06:50.161505 DLL_IDLE_MODE = 1
2199 10:06:50.164419 LP45_APHY_COMB_EN = 1
2200 10:06:50.167784 TX_ODT_DIS = 1
2201 10:06:50.170995 NEW_8X_MODE = 1
2202 10:06:50.171094 ===================================
2203 10:06:50.174601 ===================================
2204 10:06:50.177918 data_rate = 2400
2205 10:06:50.181092 CKR = 1
2206 10:06:50.184284 DQ_P2S_RATIO = 8
2207 10:06:50.187741 ===================================
2208 10:06:50.191095 CA_P2S_RATIO = 8
2209 10:06:50.194217 DQ_CA_OPEN = 0
2210 10:06:50.353901 DQ_SEMI_OPEN = 0
2211 10:06:50.354126 CA_SEMI_OPEN = 0
2212 10:06:50.354488 CA_FULL_RATE = 0
2213 10:06:50.354601 DQ_CKDIV4_EN = 0
2214 10:06:50.354728 CA_CKDIV4_EN = 0
2215 10:06:50.354856 CA_PREDIV_EN = 0
2216 10:06:50.354973 PH8_DLY = 17
2217 10:06:50.355080 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2218 10:06:50.355195 DQ_AAMCK_DIV = 4
2219 10:06:50.355290 CA_AAMCK_DIV = 4
2220 10:06:50.355395 CA_ADMCK_DIV = 4
2221 10:06:50.355535 DQ_TRACK_CA_EN = 0
2222 10:06:50.355659 CA_PICK = 1200
2223 10:06:50.355752 CA_MCKIO = 1200
2224 10:06:50.355874 MCKIO_SEMI = 0
2225 10:06:50.355990 PLL_FREQ = 2366
2226 10:06:50.356108 DQ_UI_PI_RATIO = 32
2227 10:06:50.356227 CA_UI_PI_RATIO = 0
2228 10:06:50.356346 ===================================
2229 10:06:50.356466 ===================================
2230 10:06:50.356575 memory_type:LPDDR4
2231 10:06:50.356684 GP_NUM : 10
2232 10:06:50.356787 SRAM_EN : 1
2233 10:06:50.356857 MD32_EN : 0
2234 10:06:50.356945 ===================================
2235 10:06:50.357031 [ANA_INIT] >>>>>>>>>>>>>>
2236 10:06:50.357117 <<<<<< [CONFIGURE PHASE]: ANA_TX
2237 10:06:50.357203 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2238 10:06:50.357299 ===================================
2239 10:06:50.357385 data_rate = 2400,PCW = 0X5b00
2240 10:06:50.357469 ===================================
2241 10:06:50.357527 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2242 10:06:50.357603 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2243 10:06:50.357692 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2244 10:06:50.357779 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2245 10:06:50.357864 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2246 10:06:50.357949 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2247 10:06:50.358034 [ANA_INIT] flow start
2248 10:06:50.358138 [ANA_INIT] PLL >>>>>>>>
2249 10:06:50.358207 [ANA_INIT] PLL <<<<<<<<
2250 10:06:50.358275 [ANA_INIT] MIDPI >>>>>>>>
2251 10:06:50.358342 [ANA_INIT] MIDPI <<<<<<<<
2252 10:06:50.358395 [ANA_INIT] DLL >>>>>>>>
2253 10:06:50.358463 [ANA_INIT] DLL <<<<<<<<
2254 10:06:50.358517 [ANA_INIT] flow end
2255 10:06:50.358571 ============ LP4 DIFF to SE enter ============
2256 10:06:50.358626 ============ LP4 DIFF to SE exit ============
2257 10:06:50.358681 [ANA_INIT] <<<<<<<<<<<<<
2258 10:06:50.358734 [Flow] Enable top DCM control >>>>>
2259 10:06:50.358789 [Flow] Enable top DCM control <<<<<
2260 10:06:50.358843 Enable DLL master slave shuffle
2261 10:06:50.358897 ==============================================================
2262 10:06:50.358952 Gating Mode config
2263 10:06:50.359025 ==============================================================
2264 10:06:50.360154 Config description:
2265 10:06:50.366663 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2266 10:06:50.373462 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2267 10:06:50.379982 SELPH_MODE 0: By rank 1: By Phase
2268 10:06:50.386764 ==============================================================
2269 10:06:50.389862 GAT_TRACK_EN = 1
2270 10:06:50.389945 RX_GATING_MODE = 2
2271 10:06:50.393417 RX_GATING_TRACK_MODE = 2
2272 10:06:50.396604 SELPH_MODE = 1
2273 10:06:50.399958 PICG_EARLY_EN = 1
2274 10:06:50.403150 VALID_LAT_VALUE = 1
2275 10:06:50.409950 ==============================================================
2276 10:06:50.413057 Enter into Gating configuration >>>>
2277 10:06:50.416227 Exit from Gating configuration <<<<
2278 10:06:50.420038 Enter into DVFS_PRE_config >>>>>
2279 10:06:50.429644 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2280 10:06:50.432796 Exit from DVFS_PRE_config <<<<<
2281 10:06:50.436313 Enter into PICG configuration >>>>
2282 10:06:50.439890 Exit from PICG configuration <<<<
2283 10:06:50.442837 [RX_INPUT] configuration >>>>>
2284 10:06:50.446075 [RX_INPUT] configuration <<<<<
2285 10:06:50.449604 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2286 10:06:50.456249 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2287 10:06:50.462872 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2288 10:06:50.466421 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2289 10:06:50.473059 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2290 10:06:50.479533 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2291 10:06:50.482583 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2292 10:06:50.489254 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2293 10:06:50.492723 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2294 10:06:50.496223 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2295 10:06:50.499113 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2296 10:06:50.505846 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2297 10:06:50.509226 ===================================
2298 10:06:50.509311 LPDDR4 DRAM CONFIGURATION
2299 10:06:50.512544 ===================================
2300 10:06:50.515847 EX_ROW_EN[0] = 0x0
2301 10:06:50.519314 EX_ROW_EN[1] = 0x0
2302 10:06:50.519398 LP4Y_EN = 0x0
2303 10:06:50.522420 WORK_FSP = 0x0
2304 10:06:50.522504 WL = 0x4
2305 10:06:50.526188 RL = 0x4
2306 10:06:50.526272 BL = 0x2
2307 10:06:50.529390 RPST = 0x0
2308 10:06:50.529473 RD_PRE = 0x0
2309 10:06:50.532481 WR_PRE = 0x1
2310 10:06:50.532603 WR_PST = 0x0
2311 10:06:50.536333 DBI_WR = 0x0
2312 10:06:50.536416 DBI_RD = 0x0
2313 10:06:50.539235 OTF = 0x1
2314 10:06:50.542433 ===================================
2315 10:06:50.545945 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2316 10:06:50.549051 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2317 10:06:50.555834 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2318 10:06:50.559033 ===================================
2319 10:06:50.559117 LPDDR4 DRAM CONFIGURATION
2320 10:06:50.562460 ===================================
2321 10:06:50.565619 EX_ROW_EN[0] = 0x10
2322 10:06:50.569252 EX_ROW_EN[1] = 0x0
2323 10:06:50.569363 LP4Y_EN = 0x0
2324 10:06:50.572320 WORK_FSP = 0x0
2325 10:06:50.572403 WL = 0x4
2326 10:06:50.575677 RL = 0x4
2327 10:06:50.575760 BL = 0x2
2328 10:06:50.579060 RPST = 0x0
2329 10:06:50.579143 RD_PRE = 0x0
2330 10:06:50.582068 WR_PRE = 0x1
2331 10:06:50.582150 WR_PST = 0x0
2332 10:06:50.585632 DBI_WR = 0x0
2333 10:06:50.585714 DBI_RD = 0x0
2334 10:06:50.589199 OTF = 0x1
2335 10:06:50.592436 ===================================
2336 10:06:50.598715 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2337 10:06:50.598797 ==
2338 10:06:50.602237 Dram Type= 6, Freq= 0, CH_0, rank 0
2339 10:06:50.605285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2340 10:06:50.605372 ==
2341 10:06:50.608745 [Duty_Offset_Calibration]
2342 10:06:50.608877 B0:2 B1:0 CA:1
2343 10:06:50.608984
2344 10:06:50.612066 [DutyScan_Calibration_Flow] k_type=0
2345 10:06:50.621621
2346 10:06:50.621752 ==CLK 0==
2347 10:06:50.624754 Final CLK duty delay cell = -4
2348 10:06:50.628154 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2349 10:06:50.631679 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2350 10:06:50.634920 [-4] AVG Duty = 4953%(X100)
2351 10:06:50.635074
2352 10:06:50.638418 CH0 CLK Duty spec in!! Max-Min= 156%
2353 10:06:50.641901 [DutyScan_Calibration_Flow] ====Done====
2354 10:06:50.642073
2355 10:06:50.644928 [DutyScan_Calibration_Flow] k_type=1
2356 10:06:50.660588
2357 10:06:50.661092 ==DQS 0 ==
2358 10:06:50.663849 Final DQS duty delay cell = 0
2359 10:06:50.667594 [0] MAX Duty = 5187%(X100), DQS PI = 30
2360 10:06:50.670691 [0] MIN Duty = 4938%(X100), DQS PI = 0
2361 10:06:50.671107 [0] AVG Duty = 5062%(X100)
2362 10:06:50.673837
2363 10:06:50.674247 ==DQS 1 ==
2364 10:06:50.677371 Final DQS duty delay cell = -4
2365 10:06:50.680696 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2366 10:06:50.683841 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2367 10:06:50.687155 [-4] AVG Duty = 5031%(X100)
2368 10:06:50.687571
2369 10:06:50.690614 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2370 10:06:50.691030
2371 10:06:50.694117 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2372 10:06:50.697348 [DutyScan_Calibration_Flow] ====Done====
2373 10:06:50.697769
2374 10:06:50.700375 [DutyScan_Calibration_Flow] k_type=3
2375 10:06:50.717596
2376 10:06:50.718020 ==DQM 0 ==
2377 10:06:50.720855 Final DQM duty delay cell = 0
2378 10:06:50.724129 [0] MAX Duty = 5062%(X100), DQS PI = 22
2379 10:06:50.727230 [0] MIN Duty = 4844%(X100), DQS PI = 2
2380 10:06:50.727655 [0] AVG Duty = 4953%(X100)
2381 10:06:50.730694
2382 10:06:50.731118 ==DQM 1 ==
2383 10:06:50.734003 Final DQM duty delay cell = 0
2384 10:06:50.737215 [0] MAX Duty = 5187%(X100), DQS PI = 48
2385 10:06:50.740651 [0] MIN Duty = 5000%(X100), DQS PI = 24
2386 10:06:50.743588 [0] AVG Duty = 5093%(X100)
2387 10:06:50.744099
2388 10:06:50.746947 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2389 10:06:50.747560
2390 10:06:50.750246 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2391 10:06:50.753552 [DutyScan_Calibration_Flow] ====Done====
2392 10:06:50.754023
2393 10:06:50.757137 [DutyScan_Calibration_Flow] k_type=2
2394 10:06:50.773676
2395 10:06:50.774185 ==DQ 0 ==
2396 10:06:50.776838 Final DQ duty delay cell = -4
2397 10:06:50.780072 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2398 10:06:50.783511 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2399 10:06:50.786824 [-4] AVG Duty = 4953%(X100)
2400 10:06:50.787279
2401 10:06:50.787850 ==DQ 1 ==
2402 10:06:50.790103 Final DQ duty delay cell = 4
2403 10:06:50.793921 [4] MAX Duty = 5093%(X100), DQS PI = 4
2404 10:06:50.796826 [4] MIN Duty = 5031%(X100), DQS PI = 2
2405 10:06:50.800000 [4] AVG Duty = 5062%(X100)
2406 10:06:50.800433
2407 10:06:50.803089 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2408 10:06:50.803544
2409 10:06:50.806485 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2410 10:06:50.810008 [DutyScan_Calibration_Flow] ====Done====
2411 10:06:50.810479 ==
2412 10:06:50.813177 Dram Type= 6, Freq= 0, CH_1, rank 0
2413 10:06:50.816919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2414 10:06:50.817352 ==
2415 10:06:50.820047 [Duty_Offset_Calibration]
2416 10:06:50.820481 B0:0 B1:-1 CA:2
2417 10:06:50.820867
2418 10:06:50.823156 [DutyScan_Calibration_Flow] k_type=0
2419 10:06:50.834023
2420 10:06:50.834638 ==CLK 0==
2421 10:06:50.837533 Final CLK duty delay cell = 0
2422 10:06:50.840410 [0] MAX Duty = 5156%(X100), DQS PI = 16
2423 10:06:50.843980 [0] MIN Duty = 4938%(X100), DQS PI = 44
2424 10:06:50.847006 [0] AVG Duty = 5047%(X100)
2425 10:06:50.847433
2426 10:06:50.850693 CH1 CLK Duty spec in!! Max-Min= 218%
2427 10:06:50.853957 [DutyScan_Calibration_Flow] ====Done====
2428 10:06:50.854383
2429 10:06:50.856889 [DutyScan_Calibration_Flow] k_type=1
2430 10:06:50.873466
2431 10:06:50.873891 ==DQS 0 ==
2432 10:06:50.876497 Final DQS duty delay cell = 0
2433 10:06:50.880056 [0] MAX Duty = 5093%(X100), DQS PI = 24
2434 10:06:50.883321 [0] MIN Duty = 4969%(X100), DQS PI = 0
2435 10:06:50.886862 [0] AVG Duty = 5031%(X100)
2436 10:06:50.887288
2437 10:06:50.887624 ==DQS 1 ==
2438 10:06:50.889900 Final DQS duty delay cell = 0
2439 10:06:50.893352 [0] MAX Duty = 5156%(X100), DQS PI = 0
2440 10:06:50.896821 [0] MIN Duty = 4844%(X100), DQS PI = 36
2441 10:06:50.900139 [0] AVG Duty = 5000%(X100)
2442 10:06:50.900616
2443 10:06:50.903290 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2444 10:06:50.903760
2445 10:06:50.906641 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2446 10:06:50.909798 [DutyScan_Calibration_Flow] ====Done====
2447 10:06:50.910224
2448 10:06:50.912943 [DutyScan_Calibration_Flow] k_type=3
2449 10:06:50.930549
2450 10:06:50.930979 ==DQM 0 ==
2451 10:06:50.934017 Final DQM duty delay cell = 4
2452 10:06:50.937413 [4] MAX Duty = 5093%(X100), DQS PI = 20
2453 10:06:50.940694 [4] MIN Duty = 4938%(X100), DQS PI = 44
2454 10:06:50.944049 [4] AVG Duty = 5015%(X100)
2455 10:06:50.944477
2456 10:06:50.944865 ==DQM 1 ==
2457 10:06:50.947342 Final DQM duty delay cell = 0
2458 10:06:50.950275 [0] MAX Duty = 5280%(X100), DQS PI = 60
2459 10:06:50.953780 [0] MIN Duty = 4907%(X100), DQS PI = 36
2460 10:06:50.957300 [0] AVG Duty = 5093%(X100)
2461 10:06:50.957727
2462 10:06:50.960586 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2463 10:06:50.961065
2464 10:06:50.964348 CH1 DQM 1 Duty spec in!! Max-Min= 373%
2465 10:06:50.967285 [DutyScan_Calibration_Flow] ====Done====
2466 10:06:50.967711
2467 10:06:50.970630 [DutyScan_Calibration_Flow] k_type=2
2468 10:06:50.987969
2469 10:06:50.988546 ==DQ 0 ==
2470 10:06:50.990736 Final DQ duty delay cell = 0
2471 10:06:50.994329 [0] MAX Duty = 5062%(X100), DQS PI = 20
2472 10:06:50.997657 [0] MIN Duty = 4938%(X100), DQS PI = 30
2473 10:06:50.998235 [0] AVG Duty = 5000%(X100)
2474 10:06:51.000410
2475 10:06:51.000926 ==DQ 1 ==
2476 10:06:51.004395 Final DQ duty delay cell = 0
2477 10:06:51.007417 [0] MAX Duty = 5031%(X100), DQS PI = 2
2478 10:06:51.010536 [0] MIN Duty = 4813%(X100), DQS PI = 34
2479 10:06:51.011014 [0] AVG Duty = 4922%(X100)
2480 10:06:51.014143
2481 10:06:51.017409 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2482 10:06:51.017994
2483 10:06:51.020899 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2484 10:06:51.023913 [DutyScan_Calibration_Flow] ====Done====
2485 10:06:51.027380 nWR fixed to 30
2486 10:06:51.027860 [ModeRegInit_LP4] CH0 RK0
2487 10:06:51.030588 [ModeRegInit_LP4] CH0 RK1
2488 10:06:51.033634 [ModeRegInit_LP4] CH1 RK0
2489 10:06:51.034111 [ModeRegInit_LP4] CH1 RK1
2490 10:06:51.037148 match AC timing 7
2491 10:06:51.040816 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2492 10:06:51.043708 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2493 10:06:51.050244 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2494 10:06:51.053925 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2495 10:06:51.060568 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2496 10:06:51.061151 ==
2497 10:06:51.063891 Dram Type= 6, Freq= 0, CH_0, rank 0
2498 10:06:51.067278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2499 10:06:51.067715 ==
2500 10:06:51.073557 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2501 10:06:51.080226 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2502 10:06:51.087350 [CA 0] Center 38 (7~69) winsize 63
2503 10:06:51.090375 [CA 1] Center 38 (7~69) winsize 63
2504 10:06:51.093817 [CA 2] Center 34 (4~65) winsize 62
2505 10:06:51.097174 [CA 3] Center 34 (4~65) winsize 62
2506 10:06:51.100546 [CA 4] Center 33 (3~64) winsize 62
2507 10:06:51.103726 [CA 5] Center 32 (2~63) winsize 62
2508 10:06:51.104144
2509 10:06:51.106806 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2510 10:06:51.107501
2511 10:06:51.110435 [CATrainingPosCal] consider 1 rank data
2512 10:06:51.113622 u2DelayCellTimex100 = 270/100 ps
2513 10:06:51.117014 CA0 delay=38 (7~69),Diff = 6 PI (28 cell)
2514 10:06:51.120518 CA1 delay=38 (7~69),Diff = 6 PI (28 cell)
2515 10:06:51.127257 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2516 10:06:51.130242 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2517 10:06:51.133516 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2518 10:06:51.137254 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2519 10:06:51.137676
2520 10:06:51.140434 CA PerBit enable=1, Macro0, CA PI delay=32
2521 10:06:51.140892
2522 10:06:51.143501 [CBTSetCACLKResult] CA Dly = 32
2523 10:06:51.143927 CS Dly: 6 (0~37)
2524 10:06:51.147044 ==
2525 10:06:51.150359 Dram Type= 6, Freq= 0, CH_0, rank 1
2526 10:06:51.153933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 10:06:51.154360 ==
2528 10:06:51.156830 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2529 10:06:51.163419 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2530 10:06:51.172746 [CA 0] Center 38 (7~69) winsize 63
2531 10:06:51.176411 [CA 1] Center 38 (7~69) winsize 63
2532 10:06:51.179500 [CA 2] Center 35 (5~66) winsize 62
2533 10:06:51.182579 [CA 3] Center 35 (4~66) winsize 63
2534 10:06:51.186213 [CA 4] Center 34 (4~65) winsize 62
2535 10:06:51.189431 [CA 5] Center 33 (3~64) winsize 62
2536 10:06:51.189852
2537 10:06:51.192968 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2538 10:06:51.193411
2539 10:06:51.196495 [CATrainingPosCal] consider 2 rank data
2540 10:06:51.199386 u2DelayCellTimex100 = 270/100 ps
2541 10:06:51.202931 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2542 10:06:51.209084 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2543 10:06:51.212600 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2544 10:06:51.216097 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2545 10:06:51.219342 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2546 10:06:51.222866 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2547 10:06:51.223441
2548 10:06:51.226059 CA PerBit enable=1, Macro0, CA PI delay=33
2549 10:06:51.226630
2550 10:06:51.229251 [CBTSetCACLKResult] CA Dly = 33
2551 10:06:51.229652 CS Dly: 7 (0~39)
2552 10:06:51.230024
2553 10:06:51.235931 ----->DramcWriteLeveling(PI) begin...
2554 10:06:51.236627 ==
2555 10:06:51.239176 Dram Type= 6, Freq= 0, CH_0, rank 0
2556 10:06:51.242759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2557 10:06:51.243237 ==
2558 10:06:51.245888 Write leveling (Byte 0): 33 => 33
2559 10:06:51.248992 Write leveling (Byte 1): 30 => 30
2560 10:06:51.252705 DramcWriteLeveling(PI) end<-----
2561 10:06:51.253333
2562 10:06:51.253718 ==
2563 10:06:51.256015 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 10:06:51.259306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 10:06:51.259786 ==
2566 10:06:51.262328 [Gating] SW mode calibration
2567 10:06:51.269030 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2568 10:06:51.275713 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2569 10:06:51.278665 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2570 10:06:51.282395 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
2571 10:06:51.289050 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2572 10:06:51.292076 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2573 10:06:51.295466 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2574 10:06:51.302473 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2575 10:06:51.305381 0 15 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
2576 10:06:51.308716 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2577 10:06:51.315045 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2578 10:06:51.318911 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 10:06:51.322486 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 10:06:51.329231 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2581 10:06:51.332259 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2582 10:06:51.335425 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 10:06:51.338531 1 0 24 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
2584 10:06:51.345205 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2585 10:06:51.348373 1 1 0 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
2586 10:06:51.351919 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 10:06:51.358471 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 10:06:51.361809 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2589 10:06:51.364951 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 10:06:51.371649 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 10:06:51.375207 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 10:06:51.378859 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2593 10:06:51.384852 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2594 10:06:51.388896 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 10:06:51.391868 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 10:06:51.398532 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 10:06:51.402216 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 10:06:51.405145 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 10:06:51.411596 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 10:06:51.415134 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 10:06:51.418347 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 10:06:51.424641 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 10:06:51.428165 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 10:06:51.431295 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 10:06:51.438192 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 10:06:51.441187 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 10:06:51.444546 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 10:06:51.451329 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2609 10:06:51.454479 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2610 10:06:51.457932 Total UI for P1: 0, mck2ui 16
2611 10:06:51.460996 best dqsien dly found for B0: ( 1, 3, 28)
2612 10:06:51.464549 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 10:06:51.467530 Total UI for P1: 0, mck2ui 16
2614 10:06:51.471062 best dqsien dly found for B1: ( 1, 4, 0)
2615 10:06:51.474071 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2616 10:06:51.477577 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2617 10:06:51.477819
2618 10:06:51.480513 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2619 10:06:51.487340 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2620 10:06:51.487511 [Gating] SW calibration Done
2621 10:06:51.487673 ==
2622 10:06:51.490355 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 10:06:51.497181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 10:06:51.497306 ==
2625 10:06:51.497432 RX Vref Scan: 0
2626 10:06:51.497548
2627 10:06:51.500312 RX Vref 0 -> 0, step: 1
2628 10:06:51.500461
2629 10:06:51.504071 RX Delay -40 -> 252, step: 8
2630 10:06:51.507081 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2631 10:06:51.510826 iDelay=208, Bit 1, Center 127 (56 ~ 199) 144
2632 10:06:51.513858 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2633 10:06:51.520111 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2634 10:06:51.523465 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2635 10:06:51.526953 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2636 10:06:51.530108 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2637 10:06:51.533884 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2638 10:06:51.540171 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2639 10:06:51.543643 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2640 10:06:51.546664 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2641 10:06:51.550518 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2642 10:06:51.553644 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2643 10:06:51.560253 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2644 10:06:51.563260 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2645 10:06:51.566669 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2646 10:06:51.566761 ==
2647 10:06:51.570153 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 10:06:51.573713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 10:06:51.573806 ==
2650 10:06:51.576891 DQS Delay:
2651 10:06:51.576981 DQS0 = 0, DQS1 = 0
2652 10:06:51.580316 DQM Delay:
2653 10:06:51.580409 DQM0 = 123, DQM1 = 110
2654 10:06:51.583326 DQ Delay:
2655 10:06:51.586656 DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119
2656 10:06:51.590445 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2657 10:06:51.593252 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2658 10:06:51.596446 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2659 10:06:51.596560
2660 10:06:51.596657
2661 10:06:51.596754 ==
2662 10:06:51.599719 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 10:06:51.603019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 10:06:51.603127 ==
2665 10:06:51.603225
2666 10:06:51.603323
2667 10:06:51.606443 TX Vref Scan disable
2668 10:06:51.610178 == TX Byte 0 ==
2669 10:06:51.613038 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2670 10:06:51.616444 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2671 10:06:51.620017 == TX Byte 1 ==
2672 10:06:51.623066 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2673 10:06:51.626496 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2674 10:06:51.626608 ==
2675 10:06:51.629972 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 10:06:51.633359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 10:06:51.636496 ==
2678 10:06:51.646730 TX Vref=22, minBit 4, minWin=23, winSum=399
2679 10:06:51.649771 TX Vref=24, minBit 1, minWin=24, winSum=407
2680 10:06:51.653347 TX Vref=26, minBit 0, minWin=25, winSum=411
2681 10:06:51.656790 TX Vref=28, minBit 0, minWin=25, winSum=418
2682 10:06:51.659809 TX Vref=30, minBit 1, minWin=25, winSum=420
2683 10:06:51.663383 TX Vref=32, minBit 1, minWin=25, winSum=417
2684 10:06:51.670041 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 30
2685 10:06:51.670141
2686 10:06:51.673604 Final TX Range 1 Vref 30
2687 10:06:51.673693
2688 10:06:51.673762 ==
2689 10:06:51.676686 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 10:06:51.680203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 10:06:51.680298 ==
2692 10:06:51.680367
2693 10:06:51.683378
2694 10:06:51.683463 TX Vref Scan disable
2695 10:06:51.686651 == TX Byte 0 ==
2696 10:06:51.690100 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2697 10:06:51.693260 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2698 10:06:51.696658 == TX Byte 1 ==
2699 10:06:51.700042 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2700 10:06:51.703240 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2701 10:06:51.703347
2702 10:06:51.706400 [DATLAT]
2703 10:06:51.706488 Freq=1200, CH0 RK0
2704 10:06:51.706559
2705 10:06:51.710003 DATLAT Default: 0xd
2706 10:06:51.710090 0, 0xFFFF, sum = 0
2707 10:06:51.713553 1, 0xFFFF, sum = 0
2708 10:06:51.713643 2, 0xFFFF, sum = 0
2709 10:06:51.716592 3, 0xFFFF, sum = 0
2710 10:06:51.716685 4, 0xFFFF, sum = 0
2711 10:06:51.719826 5, 0xFFFF, sum = 0
2712 10:06:51.719924 6, 0xFFFF, sum = 0
2713 10:06:51.723344 7, 0xFFFF, sum = 0
2714 10:06:51.726704 8, 0xFFFF, sum = 0
2715 10:06:51.726822 9, 0xFFFF, sum = 0
2716 10:06:51.729730 10, 0xFFFF, sum = 0
2717 10:06:51.729841 11, 0xFFFF, sum = 0
2718 10:06:51.733253 12, 0x0, sum = 1
2719 10:06:51.733344 13, 0x0, sum = 2
2720 10:06:51.736293 14, 0x0, sum = 3
2721 10:06:51.736404 15, 0x0, sum = 4
2722 10:06:51.736512 best_step = 13
2723 10:06:51.736614
2724 10:06:51.739759 ==
2725 10:06:51.743398 Dram Type= 6, Freq= 0, CH_0, rank 0
2726 10:06:51.746474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2727 10:06:51.746564 ==
2728 10:06:51.746655 RX Vref Scan: 1
2729 10:06:51.746738
2730 10:06:51.750104 Set Vref Range= 32 -> 127
2731 10:06:51.750182
2732 10:06:51.753181 RX Vref 32 -> 127, step: 1
2733 10:06:51.753261
2734 10:06:51.756593 RX Delay -13 -> 252, step: 4
2735 10:06:51.756709
2736 10:06:51.759949 Set Vref, RX VrefLevel [Byte0]: 32
2737 10:06:51.763206 [Byte1]: 32
2738 10:06:51.763290
2739 10:06:51.766654 Set Vref, RX VrefLevel [Byte0]: 33
2740 10:06:51.769814 [Byte1]: 33
2741 10:06:51.769899
2742 10:06:51.773366 Set Vref, RX VrefLevel [Byte0]: 34
2743 10:06:51.776351 [Byte1]: 34
2744 10:06:51.780606
2745 10:06:51.780704 Set Vref, RX VrefLevel [Byte0]: 35
2746 10:06:51.784090 [Byte1]: 35
2747 10:06:51.788415
2748 10:06:51.788502 Set Vref, RX VrefLevel [Byte0]: 36
2749 10:06:51.791856 [Byte1]: 36
2750 10:06:51.796243
2751 10:06:51.796329 Set Vref, RX VrefLevel [Byte0]: 37
2752 10:06:51.799840 [Byte1]: 37
2753 10:06:51.804329
2754 10:06:51.804412 Set Vref, RX VrefLevel [Byte0]: 38
2755 10:06:51.807629 [Byte1]: 38
2756 10:06:51.812223
2757 10:06:51.812311 Set Vref, RX VrefLevel [Byte0]: 39
2758 10:06:51.815480 [Byte1]: 39
2759 10:06:51.820132
2760 10:06:51.820255 Set Vref, RX VrefLevel [Byte0]: 40
2761 10:06:51.823337 [Byte1]: 40
2762 10:06:51.828077
2763 10:06:51.828157 Set Vref, RX VrefLevel [Byte0]: 41
2764 10:06:51.831188 [Byte1]: 41
2765 10:06:51.835790
2766 10:06:51.835865 Set Vref, RX VrefLevel [Byte0]: 42
2767 10:06:51.838990 [Byte1]: 42
2768 10:06:51.843884
2769 10:06:51.843960 Set Vref, RX VrefLevel [Byte0]: 43
2770 10:06:51.846825 [Byte1]: 43
2771 10:06:51.851964
2772 10:06:51.852040 Set Vref, RX VrefLevel [Byte0]: 44
2773 10:06:51.855107 [Byte1]: 44
2774 10:06:51.859762
2775 10:06:51.859837 Set Vref, RX VrefLevel [Byte0]: 45
2776 10:06:51.862828 [Byte1]: 45
2777 10:06:51.867225
2778 10:06:51.867300 Set Vref, RX VrefLevel [Byte0]: 46
2779 10:06:51.870810 [Byte1]: 46
2780 10:06:51.875101
2781 10:06:51.875192 Set Vref, RX VrefLevel [Byte0]: 47
2782 10:06:51.878580 [Byte1]: 47
2783 10:06:51.883316
2784 10:06:51.883441 Set Vref, RX VrefLevel [Byte0]: 48
2785 10:06:51.886533 [Byte1]: 48
2786 10:06:51.891010
2787 10:06:51.891123 Set Vref, RX VrefLevel [Byte0]: 49
2788 10:06:51.894391 [Byte1]: 49
2789 10:06:51.898793
2790 10:06:51.898925 Set Vref, RX VrefLevel [Byte0]: 50
2791 10:06:51.902399 [Byte1]: 50
2792 10:06:51.906804
2793 10:06:51.906940 Set Vref, RX VrefLevel [Byte0]: 51
2794 10:06:51.910334 [Byte1]: 51
2795 10:06:51.915108
2796 10:06:51.915251 Set Vref, RX VrefLevel [Byte0]: 52
2797 10:06:51.918053 [Byte1]: 52
2798 10:06:51.922675
2799 10:06:51.922781 Set Vref, RX VrefLevel [Byte0]: 53
2800 10:06:51.926075 [Byte1]: 53
2801 10:06:51.930604
2802 10:06:51.930726 Set Vref, RX VrefLevel [Byte0]: 54
2803 10:06:51.933809 [Byte1]: 54
2804 10:06:51.938573
2805 10:06:51.938698 Set Vref, RX VrefLevel [Byte0]: 55
2806 10:06:51.941771 [Byte1]: 55
2807 10:06:51.946351
2808 10:06:51.946434 Set Vref, RX VrefLevel [Byte0]: 56
2809 10:06:51.949786 [Byte1]: 56
2810 10:06:51.954187
2811 10:06:51.954270 Set Vref, RX VrefLevel [Byte0]: 57
2812 10:06:51.957309 [Byte1]: 57
2813 10:06:51.962271
2814 10:06:51.962354 Set Vref, RX VrefLevel [Byte0]: 58
2815 10:06:51.965354 [Byte1]: 58
2816 10:06:51.969903
2817 10:06:51.969986 Set Vref, RX VrefLevel [Byte0]: 59
2818 10:06:51.973093 [Byte1]: 59
2819 10:06:51.978021
2820 10:06:51.978104 Set Vref, RX VrefLevel [Byte0]: 60
2821 10:06:51.981233 [Byte1]: 60
2822 10:06:51.985957
2823 10:06:51.986077 Set Vref, RX VrefLevel [Byte0]: 61
2824 10:06:51.988916 [Byte1]: 61
2825 10:06:51.993455
2826 10:06:51.993575 Set Vref, RX VrefLevel [Byte0]: 62
2827 10:06:51.996843 [Byte1]: 62
2828 10:06:52.001550
2829 10:06:52.001713 Set Vref, RX VrefLevel [Byte0]: 63
2830 10:06:52.004638 [Byte1]: 63
2831 10:06:52.009363
2832 10:06:52.009485 Set Vref, RX VrefLevel [Byte0]: 64
2833 10:06:52.012739 [Byte1]: 64
2834 10:06:52.017152
2835 10:06:52.017265 Set Vref, RX VrefLevel [Byte0]: 65
2836 10:06:52.020496 [Byte1]: 65
2837 10:06:52.025494
2838 10:06:52.025615 Set Vref, RX VrefLevel [Byte0]: 66
2839 10:06:52.028512 [Byte1]: 66
2840 10:06:52.033287
2841 10:06:52.033374 Set Vref, RX VrefLevel [Byte0]: 67
2842 10:06:52.036242 [Byte1]: 67
2843 10:06:52.040816
2844 10:06:52.040904 Set Vref, RX VrefLevel [Byte0]: 68
2845 10:06:52.044202 [Byte1]: 68
2846 10:06:52.048817
2847 10:06:52.048904 Set Vref, RX VrefLevel [Byte0]: 69
2848 10:06:52.052333 [Byte1]: 69
2849 10:06:52.056985
2850 10:06:52.057098 Set Vref, RX VrefLevel [Byte0]: 70
2851 10:06:52.059881 [Byte1]: 70
2852 10:06:52.064685
2853 10:06:52.064806 Set Vref, RX VrefLevel [Byte0]: 71
2854 10:06:52.067807 [Byte1]: 71
2855 10:06:52.072609
2856 10:06:52.072733 Final RX Vref Byte 0 = 59 to rank0
2857 10:06:52.075678 Final RX Vref Byte 1 = 49 to rank0
2858 10:06:52.079163 Final RX Vref Byte 0 = 59 to rank1
2859 10:06:52.082675 Final RX Vref Byte 1 = 49 to rank1==
2860 10:06:52.085908 Dram Type= 6, Freq= 0, CH_0, rank 0
2861 10:06:52.092404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 10:06:52.092519 ==
2863 10:06:52.092629 DQS Delay:
2864 10:06:52.092742 DQS0 = 0, DQS1 = 0
2865 10:06:52.095945 DQM Delay:
2866 10:06:52.096069 DQM0 = 123, DQM1 = 108
2867 10:06:52.098910 DQ Delay:
2868 10:06:52.102467 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2869 10:06:52.105839 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =130
2870 10:06:52.108975 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =104
2871 10:06:52.112775 DQ12 =114, DQ13 =110, DQ14 =122, DQ15 =116
2872 10:06:52.112893
2873 10:06:52.113004
2874 10:06:52.118898 [DQSOSCAuto] RK0, (LSB)MR18= 0xa06, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2875 10:06:52.122451 CH0 RK0: MR19=404, MR18=A06
2876 10:06:52.128863 CH0_RK0: MR19=0x404, MR18=0xA06, DQSOSC=406, MR23=63, INC=39, DEC=26
2877 10:06:52.128986
2878 10:06:52.132369 ----->DramcWriteLeveling(PI) begin...
2879 10:06:52.132496 ==
2880 10:06:52.135812 Dram Type= 6, Freq= 0, CH_0, rank 1
2881 10:06:52.138996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 10:06:52.142270 ==
2883 10:06:52.142369 Write leveling (Byte 0): 34 => 34
2884 10:06:52.145360 Write leveling (Byte 1): 30 => 30
2885 10:06:52.148916 DramcWriteLeveling(PI) end<-----
2886 10:06:52.148999
2887 10:06:52.149102 ==
2888 10:06:52.152415 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 10:06:52.159034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 10:06:52.159134 ==
2891 10:06:52.159230 [Gating] SW mode calibration
2892 10:06:52.168748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2893 10:06:52.172095 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2894 10:06:52.178733 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2895 10:06:52.182066 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 10:06:52.185610 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 10:06:52.188918 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 10:06:52.195331 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 10:06:52.198565 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 10:06:52.202076 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2901 10:06:52.208429 0 15 28 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 1)
2902 10:06:52.212101 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2903 10:06:52.215026 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 10:06:52.221736 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 10:06:52.225214 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 10:06:52.228394 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 10:06:52.235074 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 10:06:52.238700 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 10:06:52.241773 1 0 28 | B1->B0 | 3c3c 4645 | 0 1 | (0 0) (0 0)
2910 10:06:52.248385 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 10:06:52.252019 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 10:06:52.255402 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 10:06:52.261825 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 10:06:52.265127 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 10:06:52.268375 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 10:06:52.275046 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2917 10:06:52.278414 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2918 10:06:52.281376 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 10:06:52.288298 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 10:06:52.291568 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 10:06:52.294806 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 10:06:52.301488 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 10:06:52.304562 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 10:06:52.308195 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 10:06:52.314611 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 10:06:52.318059 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 10:06:52.321597 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 10:06:52.328385 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 10:06:52.331377 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 10:06:52.334606 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 10:06:52.341249 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 10:06:52.344637 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 10:06:52.347811 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2934 10:06:52.354637 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 10:06:52.354749 Total UI for P1: 0, mck2ui 16
2936 10:06:52.357758 best dqsien dly found for B0: ( 1, 3, 28)
2937 10:06:52.361589 Total UI for P1: 0, mck2ui 16
2938 10:06:52.364383 best dqsien dly found for B1: ( 1, 3, 28)
2939 10:06:52.367710 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2940 10:06:52.374344 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2941 10:06:52.374453
2942 10:06:52.377713 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2943 10:06:52.380829 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2944 10:06:52.384309 [Gating] SW calibration Done
2945 10:06:52.384392 ==
2946 10:06:52.387999 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 10:06:52.391032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 10:06:52.391110 ==
2949 10:06:52.394461 RX Vref Scan: 0
2950 10:06:52.394534
2951 10:06:52.394598 RX Vref 0 -> 0, step: 1
2952 10:06:52.394664
2953 10:06:52.397470 RX Delay -40 -> 252, step: 8
2954 10:06:52.400828 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2955 10:06:52.404578 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2956 10:06:52.411127 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2957 10:06:52.414210 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2958 10:06:52.417602 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2959 10:06:52.421148 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2960 10:06:52.424160 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2961 10:06:52.430840 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2962 10:06:52.434531 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2963 10:06:52.437453 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2964 10:06:52.440652 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2965 10:06:52.444291 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2966 10:06:52.450676 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2967 10:06:52.454061 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2968 10:06:52.457346 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2969 10:06:52.461028 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2970 10:06:52.461108 ==
2971 10:06:52.464201 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 10:06:52.470695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 10:06:52.470805 ==
2974 10:06:52.470901 DQS Delay:
2975 10:06:52.473999 DQS0 = 0, DQS1 = 0
2976 10:06:52.474081 DQM Delay:
2977 10:06:52.474146 DQM0 = 120, DQM1 = 108
2978 10:06:52.477272 DQ Delay:
2979 10:06:52.480718 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2980 10:06:52.484130 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2981 10:06:52.487535 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2982 10:06:52.490704 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2983 10:06:52.490809
2984 10:06:52.490904
2985 10:06:52.491000 ==
2986 10:06:52.494282 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 10:06:52.497350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 10:06:52.497429 ==
2989 10:06:52.500738
2990 10:06:52.500824
2991 10:06:52.500896 TX Vref Scan disable
2992 10:06:52.504087 == TX Byte 0 ==
2993 10:06:52.507218 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2994 10:06:52.510457 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2995 10:06:52.514100 == TX Byte 1 ==
2996 10:06:52.517497 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2997 10:06:52.520375 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2998 10:06:52.520487 ==
2999 10:06:52.523788 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 10:06:52.530627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 10:06:52.530742 ==
3002 10:06:52.541516 TX Vref=22, minBit 1, minWin=23, winSum=399
3003 10:06:52.545033 TX Vref=24, minBit 3, minWin=24, winSum=410
3004 10:06:52.548148 TX Vref=26, minBit 1, minWin=24, winSum=413
3005 10:06:52.551778 TX Vref=28, minBit 1, minWin=24, winSum=419
3006 10:06:52.554881 TX Vref=30, minBit 1, minWin=25, winSum=420
3007 10:06:52.558303 TX Vref=32, minBit 0, minWin=25, winSum=416
3008 10:06:52.564680 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 30
3009 10:06:52.564803
3010 10:06:52.568110 Final TX Range 1 Vref 30
3011 10:06:52.568227
3012 10:06:52.568337 ==
3013 10:06:52.571613 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 10:06:52.574965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 10:06:52.575079 ==
3016 10:06:52.575189
3017 10:06:52.578206
3018 10:06:52.578318 TX Vref Scan disable
3019 10:06:52.581473 == TX Byte 0 ==
3020 10:06:52.585152 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3021 10:06:52.588176 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3022 10:06:52.591581 == TX Byte 1 ==
3023 10:06:52.595070 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3024 10:06:52.598189 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3025 10:06:52.601815
3026 10:06:52.601900 [DATLAT]
3027 10:06:52.601967 Freq=1200, CH0 RK1
3028 10:06:52.602030
3029 10:06:52.604750 DATLAT Default: 0xd
3030 10:06:52.604845 0, 0xFFFF, sum = 0
3031 10:06:52.608165 1, 0xFFFF, sum = 0
3032 10:06:52.608278 2, 0xFFFF, sum = 0
3033 10:06:52.611682 3, 0xFFFF, sum = 0
3034 10:06:52.611795 4, 0xFFFF, sum = 0
3035 10:06:52.614686 5, 0xFFFF, sum = 0
3036 10:06:52.617830 6, 0xFFFF, sum = 0
3037 10:06:52.617917 7, 0xFFFF, sum = 0
3038 10:06:52.621233 8, 0xFFFF, sum = 0
3039 10:06:52.621325 9, 0xFFFF, sum = 0
3040 10:06:52.624576 10, 0xFFFF, sum = 0
3041 10:06:52.624689 11, 0xFFFF, sum = 0
3042 10:06:52.628149 12, 0x0, sum = 1
3043 10:06:52.628262 13, 0x0, sum = 2
3044 10:06:52.631414 14, 0x0, sum = 3
3045 10:06:52.631490 15, 0x0, sum = 4
3046 10:06:52.631555 best_step = 13
3047 10:06:52.634632
3048 10:06:52.634703 ==
3049 10:06:52.638113 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 10:06:52.641252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 10:06:52.641332 ==
3052 10:06:52.641405 RX Vref Scan: 0
3053 10:06:52.641498
3054 10:06:52.644775 RX Vref 0 -> 0, step: 1
3055 10:06:52.644848
3056 10:06:52.648001 RX Delay -21 -> 252, step: 4
3057 10:06:52.651144 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3058 10:06:52.658059 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3059 10:06:52.661259 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3060 10:06:52.664428 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3061 10:06:52.668084 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3062 10:06:52.671029 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3063 10:06:52.678132 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3064 10:06:52.681399 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3065 10:06:52.684543 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3066 10:06:52.688232 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3067 10:06:52.691163 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3068 10:06:52.698038 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3069 10:06:52.700969 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3070 10:06:52.704515 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3071 10:06:52.707499 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3072 10:06:52.710955 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3073 10:06:52.714305 ==
3074 10:06:52.714380 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 10:06:52.721047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 10:06:52.721125 ==
3077 10:06:52.721189 DQS Delay:
3078 10:06:52.724310 DQS0 = 0, DQS1 = 0
3079 10:06:52.724381 DQM Delay:
3080 10:06:52.727644 DQM0 = 119, DQM1 = 108
3081 10:06:52.727714 DQ Delay:
3082 10:06:52.730656 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3083 10:06:52.734187 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3084 10:06:52.737235 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3085 10:06:52.740979 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3086 10:06:52.741057
3087 10:06:52.741146
3088 10:06:52.750630 [DQSOSCAuto] RK1, (LSB)MR18= 0xff7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 404 ps
3089 10:06:52.750714 CH0 RK1: MR19=403, MR18=FF7
3090 10:06:52.757400 CH0_RK1: MR19=0x403, MR18=0xFF7, DQSOSC=404, MR23=63, INC=40, DEC=26
3091 10:06:52.761098 [RxdqsGatingPostProcess] freq 1200
3092 10:06:52.767359 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3093 10:06:52.770912 best DQS0 dly(2T, 0.5T) = (0, 11)
3094 10:06:52.774089 best DQS1 dly(2T, 0.5T) = (0, 12)
3095 10:06:52.777618 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3096 10:06:52.780899 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3097 10:06:52.783939 best DQS0 dly(2T, 0.5T) = (0, 11)
3098 10:06:52.784027 best DQS1 dly(2T, 0.5T) = (0, 11)
3099 10:06:52.787750 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3100 10:06:52.790695 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3101 10:06:52.794072 Pre-setting of DQS Precalculation
3102 10:06:52.800407 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3103 10:06:52.800591 ==
3104 10:06:52.803938 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 10:06:52.807119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 10:06:52.807211 ==
3107 10:06:52.813721 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3108 10:06:52.820521 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3109 10:06:52.827661 [CA 0] Center 37 (7~67) winsize 61
3110 10:06:52.830737 [CA 1] Center 37 (7~68) winsize 62
3111 10:06:52.833991 [CA 2] Center 35 (5~65) winsize 61
3112 10:06:52.837628 [CA 3] Center 33 (3~64) winsize 62
3113 10:06:52.840685 [CA 4] Center 33 (3~64) winsize 62
3114 10:06:52.843885 [CA 5] Center 33 (3~63) winsize 61
3115 10:06:52.843958
3116 10:06:52.847268 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3117 10:06:52.847369
3118 10:06:52.850888 [CATrainingPosCal] consider 1 rank data
3119 10:06:52.854051 u2DelayCellTimex100 = 270/100 ps
3120 10:06:52.857223 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3121 10:06:52.864318 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3122 10:06:52.867345 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3123 10:06:52.870685 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3124 10:06:52.873849 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3125 10:06:52.877572 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3126 10:06:52.877656
3127 10:06:52.880624 CA PerBit enable=1, Macro0, CA PI delay=33
3128 10:06:52.880709
3129 10:06:52.883896 [CBTSetCACLKResult] CA Dly = 33
3130 10:06:52.884028 CS Dly: 5 (0~36)
3131 10:06:52.887120 ==
3132 10:06:52.887219 Dram Type= 6, Freq= 0, CH_1, rank 1
3133 10:06:52.893885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 10:06:52.893971 ==
3135 10:06:52.897009 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3136 10:06:52.903831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3137 10:06:52.913151 [CA 0] Center 37 (7~68) winsize 62
3138 10:06:52.916248 [CA 1] Center 37 (7~68) winsize 62
3139 10:06:52.919717 [CA 2] Center 35 (5~66) winsize 62
3140 10:06:52.922783 [CA 3] Center 34 (4~65) winsize 62
3141 10:06:52.926293 [CA 4] Center 34 (4~64) winsize 61
3142 10:06:52.929955 [CA 5] Center 33 (3~64) winsize 62
3143 10:06:52.930031
3144 10:06:52.933112 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3145 10:06:52.933213
3146 10:06:52.936172 [CATrainingPosCal] consider 2 rank data
3147 10:06:52.939811 u2DelayCellTimex100 = 270/100 ps
3148 10:06:52.943019 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3149 10:06:52.946431 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3150 10:06:52.953019 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3151 10:06:52.956031 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3152 10:06:52.959598 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3153 10:06:52.962746 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3154 10:06:52.962831
3155 10:06:52.966367 CA PerBit enable=1, Macro0, CA PI delay=33
3156 10:06:52.966453
3157 10:06:52.969794 [CBTSetCACLKResult] CA Dly = 33
3158 10:06:52.969880 CS Dly: 6 (0~38)
3159 10:06:52.969948
3160 10:06:52.972674 ----->DramcWriteLeveling(PI) begin...
3161 10:06:52.976182 ==
3162 10:06:52.979445 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 10:06:52.982827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 10:06:52.982913 ==
3165 10:06:52.986310 Write leveling (Byte 0): 23 => 23
3166 10:06:52.989385 Write leveling (Byte 1): 27 => 27
3167 10:06:52.992736 DramcWriteLeveling(PI) end<-----
3168 10:06:52.992835
3169 10:06:52.992903 ==
3170 10:06:52.996008 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 10:06:52.999293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 10:06:52.999379 ==
3173 10:06:53.002805 [Gating] SW mode calibration
3174 10:06:53.009252 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3175 10:06:53.016133 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3176 10:06:53.019247 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 10:06:53.022744 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 10:06:53.029077 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 10:06:53.032712 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 10:06:53.036314 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 10:06:53.039284 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3182 10:06:53.046107 0 15 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
3183 10:06:53.049270 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3184 10:06:53.052619 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 10:06:53.059243 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 10:06:53.062828 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 10:06:53.065757 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 10:06:53.072527 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 10:06:53.075613 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
3190 10:06:53.079060 1 0 24 | B1->B0 | 4343 4545 | 0 0 | (0 0) (0 0)
3191 10:06:53.085639 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 10:06:53.089302 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 10:06:53.092562 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 10:06:53.099211 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 10:06:53.102303 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 10:06:53.105620 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 10:06:53.112283 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 10:06:53.115340 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3199 10:06:53.119040 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3200 10:06:53.125516 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 10:06:53.128878 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 10:06:53.132453 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 10:06:53.139024 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 10:06:53.142083 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 10:06:53.145484 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 10:06:53.152327 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 10:06:53.155446 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 10:06:53.159028 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 10:06:53.165258 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 10:06:53.168598 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 10:06:53.172099 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 10:06:53.178891 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 10:06:53.182137 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3214 10:06:53.185112 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3215 10:06:53.188778 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3216 10:06:53.191872 Total UI for P1: 0, mck2ui 16
3217 10:06:53.195304 best dqsien dly found for B0: ( 1, 3, 22)
3218 10:06:53.201974 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 10:06:53.205021 Total UI for P1: 0, mck2ui 16
3220 10:06:53.208532 best dqsien dly found for B1: ( 1, 3, 26)
3221 10:06:53.211807 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3222 10:06:53.215054 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3223 10:06:53.215142
3224 10:06:53.218570 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3225 10:06:53.221729 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3226 10:06:53.225412 [Gating] SW calibration Done
3227 10:06:53.225494 ==
3228 10:06:53.228604 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 10:06:53.231704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 10:06:53.231808 ==
3231 10:06:53.234960 RX Vref Scan: 0
3232 10:06:53.235067
3233 10:06:53.238541 RX Vref 0 -> 0, step: 1
3234 10:06:53.238619
3235 10:06:53.238685 RX Delay -40 -> 252, step: 8
3236 10:06:53.245288 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3237 10:06:53.248567 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3238 10:06:53.251707 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3239 10:06:53.255085 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3240 10:06:53.258269 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3241 10:06:53.264987 iDelay=200, Bit 5, Center 131 (72 ~ 191) 120
3242 10:06:53.268617 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3243 10:06:53.271801 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3244 10:06:53.275252 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3245 10:06:53.278276 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3246 10:06:53.281925 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3247 10:06:53.288443 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3248 10:06:53.291656 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3249 10:06:53.295146 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3250 10:06:53.298111 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3251 10:06:53.305091 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3252 10:06:53.305184 ==
3253 10:06:53.308155 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 10:06:53.311680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 10:06:53.311757 ==
3256 10:06:53.311823 DQS Delay:
3257 10:06:53.315088 DQS0 = 0, DQS1 = 0
3258 10:06:53.315158 DQM Delay:
3259 10:06:53.318024 DQM0 = 121, DQM1 = 112
3260 10:06:53.318113 DQ Delay:
3261 10:06:53.321277 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3262 10:06:53.324580 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =123
3263 10:06:53.327858 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3264 10:06:53.331368 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3265 10:06:53.331455
3266 10:06:53.331523
3267 10:06:53.334594 ==
3268 10:06:53.338195 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 10:06:53.341244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 10:06:53.341408 ==
3271 10:06:53.341603
3272 10:06:53.341726
3273 10:06:53.344906 TX Vref Scan disable
3274 10:06:53.344998 == TX Byte 0 ==
3275 10:06:53.347828 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3276 10:06:53.354614 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3277 10:06:53.354710 == TX Byte 1 ==
3278 10:06:53.358365 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3279 10:06:53.364577 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3280 10:06:53.364696 ==
3281 10:06:53.367795 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 10:06:53.371219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 10:06:53.371295 ==
3284 10:06:53.382951 TX Vref=22, minBit 10, minWin=24, winSum=402
3285 10:06:53.386570 TX Vref=24, minBit 10, minWin=23, winSum=401
3286 10:06:53.390175 TX Vref=26, minBit 10, minWin=24, winSum=407
3287 10:06:53.392972 TX Vref=28, minBit 1, minWin=25, winSum=413
3288 10:06:53.396475 TX Vref=30, minBit 10, minWin=25, winSum=418
3289 10:06:53.403087 TX Vref=32, minBit 10, minWin=24, winSum=417
3290 10:06:53.406516 [TxChooseVref] Worse bit 10, Min win 25, Win sum 418, Final Vref 30
3291 10:06:53.409631
3292 10:06:53.409715 Final TX Range 1 Vref 30
3293 10:06:53.409784
3294 10:06:53.409846 ==
3295 10:06:53.413166 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 10:06:53.419296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 10:06:53.419379 ==
3298 10:06:53.419447
3299 10:06:53.419511
3300 10:06:53.419581 TX Vref Scan disable
3301 10:06:53.423096 == TX Byte 0 ==
3302 10:06:53.426454 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3303 10:06:53.433169 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3304 10:06:53.433256 == TX Byte 1 ==
3305 10:06:53.436602 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3306 10:06:53.443330 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3307 10:06:53.443420
3308 10:06:53.443489 [DATLAT]
3309 10:06:53.443554 Freq=1200, CH1 RK0
3310 10:06:53.443616
3311 10:06:53.446537 DATLAT Default: 0xd
3312 10:06:53.446622 0, 0xFFFF, sum = 0
3313 10:06:53.449942 1, 0xFFFF, sum = 0
3314 10:06:53.450027 2, 0xFFFF, sum = 0
3315 10:06:53.453159 3, 0xFFFF, sum = 0
3316 10:06:53.456654 4, 0xFFFF, sum = 0
3317 10:06:53.456731 5, 0xFFFF, sum = 0
3318 10:06:53.460050 6, 0xFFFF, sum = 0
3319 10:06:53.460137 7, 0xFFFF, sum = 0
3320 10:06:53.463277 8, 0xFFFF, sum = 0
3321 10:06:53.463372 9, 0xFFFF, sum = 0
3322 10:06:53.466538 10, 0xFFFF, sum = 0
3323 10:06:53.466627 11, 0xFFFF, sum = 0
3324 10:06:53.469687 12, 0x0, sum = 1
3325 10:06:53.469765 13, 0x0, sum = 2
3326 10:06:53.473095 14, 0x0, sum = 3
3327 10:06:53.473174 15, 0x0, sum = 4
3328 10:06:53.473239 best_step = 13
3329 10:06:53.476212
3330 10:06:53.476293 ==
3331 10:06:53.479704 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 10:06:53.483278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 10:06:53.483365 ==
3334 10:06:53.483432 RX Vref Scan: 1
3335 10:06:53.483510
3336 10:06:53.486437 Set Vref Range= 32 -> 127
3337 10:06:53.486568
3338 10:06:53.490073 RX Vref 32 -> 127, step: 1
3339 10:06:53.490206
3340 10:06:53.493074 RX Delay -13 -> 252, step: 4
3341 10:06:53.493203
3342 10:06:53.496490 Set Vref, RX VrefLevel [Byte0]: 32
3343 10:06:53.499666 [Byte1]: 32
3344 10:06:53.499779
3345 10:06:53.503182 Set Vref, RX VrefLevel [Byte0]: 33
3346 10:06:53.506372 [Byte1]: 33
3347 10:06:53.509696
3348 10:06:53.509815 Set Vref, RX VrefLevel [Byte0]: 34
3349 10:06:53.513150 [Byte1]: 34
3350 10:06:53.517612
3351 10:06:53.517731 Set Vref, RX VrefLevel [Byte0]: 35
3352 10:06:53.521060 [Byte1]: 35
3353 10:06:53.525716
3354 10:06:53.525838 Set Vref, RX VrefLevel [Byte0]: 36
3355 10:06:53.529128 [Byte1]: 36
3356 10:06:53.533384
3357 10:06:53.533494 Set Vref, RX VrefLevel [Byte0]: 37
3358 10:06:53.536917 [Byte1]: 37
3359 10:06:53.541350
3360 10:06:53.541465 Set Vref, RX VrefLevel [Byte0]: 38
3361 10:06:53.544587 [Byte1]: 38
3362 10:06:53.549377
3363 10:06:53.549491 Set Vref, RX VrefLevel [Byte0]: 39
3364 10:06:53.552562 [Byte1]: 39
3365 10:06:53.556986
3366 10:06:53.557114 Set Vref, RX VrefLevel [Byte0]: 40
3367 10:06:53.560347 [Byte1]: 40
3368 10:06:53.564984
3369 10:06:53.565097 Set Vref, RX VrefLevel [Byte0]: 41
3370 10:06:53.568314 [Byte1]: 41
3371 10:06:53.572723
3372 10:06:53.572842 Set Vref, RX VrefLevel [Byte0]: 42
3373 10:06:53.576174 [Byte1]: 42
3374 10:06:53.580613
3375 10:06:53.580723 Set Vref, RX VrefLevel [Byte0]: 43
3376 10:06:53.584078 [Byte1]: 43
3377 10:06:53.588709
3378 10:06:53.588851 Set Vref, RX VrefLevel [Byte0]: 44
3379 10:06:53.591707 [Byte1]: 44
3380 10:06:53.596596
3381 10:06:53.596708 Set Vref, RX VrefLevel [Byte0]: 45
3382 10:06:53.600073 [Byte1]: 45
3383 10:06:53.604363
3384 10:06:53.604478 Set Vref, RX VrefLevel [Byte0]: 46
3385 10:06:53.607555 [Byte1]: 46
3386 10:06:53.612289
3387 10:06:53.612398 Set Vref, RX VrefLevel [Byte0]: 47
3388 10:06:53.615707 [Byte1]: 47
3389 10:06:53.620336
3390 10:06:53.620442 Set Vref, RX VrefLevel [Byte0]: 48
3391 10:06:53.626494 [Byte1]: 48
3392 10:06:53.626616
3393 10:06:53.629637 Set Vref, RX VrefLevel [Byte0]: 49
3394 10:06:53.633084 [Byte1]: 49
3395 10:06:53.633192
3396 10:06:53.636370 Set Vref, RX VrefLevel [Byte0]: 50
3397 10:06:53.639743 [Byte1]: 50
3398 10:06:53.643976
3399 10:06:53.644070 Set Vref, RX VrefLevel [Byte0]: 51
3400 10:06:53.646989 [Byte1]: 51
3401 10:06:53.651651
3402 10:06:53.651764 Set Vref, RX VrefLevel [Byte0]: 52
3403 10:06:53.655115 [Byte1]: 52
3404 10:06:53.659697
3405 10:06:53.659800 Set Vref, RX VrefLevel [Byte0]: 53
3406 10:06:53.662686 [Byte1]: 53
3407 10:06:53.667717
3408 10:06:53.667802 Set Vref, RX VrefLevel [Byte0]: 54
3409 10:06:53.670801 [Byte1]: 54
3410 10:06:53.675244
3411 10:06:53.675355 Set Vref, RX VrefLevel [Byte0]: 55
3412 10:06:53.678989 [Byte1]: 55
3413 10:06:53.683479
3414 10:06:53.683582 Set Vref, RX VrefLevel [Byte0]: 56
3415 10:06:53.686465 [Byte1]: 56
3416 10:06:53.691356
3417 10:06:53.691467 Set Vref, RX VrefLevel [Byte0]: 57
3418 10:06:53.694484 [Byte1]: 57
3419 10:06:53.698972
3420 10:06:53.699082 Set Vref, RX VrefLevel [Byte0]: 58
3421 10:06:53.702337 [Byte1]: 58
3422 10:06:53.707165
3423 10:06:53.707248 Set Vref, RX VrefLevel [Byte0]: 59
3424 10:06:53.710353 [Byte1]: 59
3425 10:06:53.714745
3426 10:06:53.714829 Set Vref, RX VrefLevel [Byte0]: 60
3427 10:06:53.718266 [Byte1]: 60
3428 10:06:53.722670
3429 10:06:53.726187 Set Vref, RX VrefLevel [Byte0]: 61
3430 10:06:53.726271 [Byte1]: 61
3431 10:06:53.730759
3432 10:06:53.730884 Set Vref, RX VrefLevel [Byte0]: 62
3433 10:06:53.733704 [Byte1]: 62
3434 10:06:53.738313
3435 10:06:53.738424 Set Vref, RX VrefLevel [Byte0]: 63
3436 10:06:53.741997 [Byte1]: 63
3437 10:06:53.746214
3438 10:06:53.746317 Set Vref, RX VrefLevel [Byte0]: 64
3439 10:06:53.749843 [Byte1]: 64
3440 10:06:53.754224
3441 10:06:53.754316 Set Vref, RX VrefLevel [Byte0]: 65
3442 10:06:53.757543 [Byte1]: 65
3443 10:06:53.762243
3444 10:06:53.762347 Set Vref, RX VrefLevel [Byte0]: 66
3445 10:06:53.765315 [Byte1]: 66
3446 10:06:53.770050
3447 10:06:53.770197 Set Vref, RX VrefLevel [Byte0]: 67
3448 10:06:53.773435 [Byte1]: 67
3449 10:06:53.777693
3450 10:06:53.777799 Final RX Vref Byte 0 = 50 to rank0
3451 10:06:53.781314 Final RX Vref Byte 1 = 50 to rank0
3452 10:06:53.784485 Final RX Vref Byte 0 = 50 to rank1
3453 10:06:53.788125 Final RX Vref Byte 1 = 50 to rank1==
3454 10:06:53.791185 Dram Type= 6, Freq= 0, CH_1, rank 0
3455 10:06:53.798184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3456 10:06:53.798288 ==
3457 10:06:53.798390 DQS Delay:
3458 10:06:53.798492 DQS0 = 0, DQS1 = 0
3459 10:06:53.801280 DQM Delay:
3460 10:06:53.801382 DQM0 = 118, DQM1 = 111
3461 10:06:53.804395 DQ Delay:
3462 10:06:53.807653 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =116
3463 10:06:53.811124 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3464 10:06:53.814349 DQ8 =100, DQ9 =100, DQ10 =114, DQ11 =104
3465 10:06:53.817849 DQ12 =122, DQ13 =116, DQ14 =118, DQ15 =116
3466 10:06:53.817969
3467 10:06:53.818074
3468 10:06:53.827885 [DQSOSCAuto] RK0, (LSB)MR18= 0x417, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3469 10:06:53.828001 CH1 RK0: MR19=404, MR18=417
3470 10:06:53.834461 CH1_RK0: MR19=0x404, MR18=0x417, DQSOSC=401, MR23=63, INC=40, DEC=27
3471 10:06:53.834552
3472 10:06:53.837725 ----->DramcWriteLeveling(PI) begin...
3473 10:06:53.837814 ==
3474 10:06:53.840741 Dram Type= 6, Freq= 0, CH_1, rank 1
3475 10:06:53.844244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3476 10:06:53.847536 ==
3477 10:06:53.847622 Write leveling (Byte 0): 26 => 26
3478 10:06:53.850848 Write leveling (Byte 1): 28 => 28
3479 10:06:53.854196 DramcWriteLeveling(PI) end<-----
3480 10:06:53.854297
3481 10:06:53.854372 ==
3482 10:06:53.857533 Dram Type= 6, Freq= 0, CH_1, rank 1
3483 10:06:53.864082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 10:06:53.864169 ==
3485 10:06:53.867352 [Gating] SW mode calibration
3486 10:06:53.874455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3487 10:06:53.877478 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3488 10:06:53.883990 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 10:06:53.887607 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 10:06:53.890629 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 10:06:53.894216 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 10:06:53.901035 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 10:06:53.904083 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3494 10:06:53.907489 0 15 24 | B1->B0 | 2828 3333 | 0 1 | (0 0) (1 0)
3495 10:06:53.913965 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
3496 10:06:53.917582 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 10:06:53.920693 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 10:06:53.927391 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 10:06:53.930851 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 10:06:53.934131 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 10:06:53.940801 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3502 10:06:53.944328 1 0 24 | B1->B0 | 4040 2d2d | 0 0 | (0 0) (0 0)
3503 10:06:53.947264 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3504 10:06:53.953922 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 10:06:53.957169 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 10:06:53.960473 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 10:06:53.967116 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 10:06:53.970423 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 10:06:53.973918 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 10:06:53.980352 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3511 10:06:53.983486 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3512 10:06:53.986744 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 10:06:53.993693 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 10:06:53.996789 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 10:06:54.000438 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 10:06:54.006661 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 10:06:54.010170 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 10:06:54.013245 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 10:06:54.019755 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 10:06:54.023421 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 10:06:54.026640 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 10:06:54.032989 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 10:06:54.036619 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 10:06:54.039739 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 10:06:54.046414 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 10:06:54.049459 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3527 10:06:54.052932 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 10:06:54.056070 Total UI for P1: 0, mck2ui 16
3529 10:06:54.059512 best dqsien dly found for B0: ( 1, 3, 24)
3530 10:06:54.062543 Total UI for P1: 0, mck2ui 16
3531 10:06:54.066378 best dqsien dly found for B1: ( 1, 3, 24)
3532 10:06:54.069637 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3533 10:06:54.072657 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3534 10:06:54.072768
3535 10:06:54.079491 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3536 10:06:54.082476 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3537 10:06:54.085891 [Gating] SW calibration Done
3538 10:06:54.086011 ==
3539 10:06:54.088891 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 10:06:54.092267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 10:06:54.092372 ==
3542 10:06:54.092474 RX Vref Scan: 0
3543 10:06:54.092578
3544 10:06:54.095840 RX Vref 0 -> 0, step: 1
3545 10:06:54.095942
3546 10:06:54.099009 RX Delay -40 -> 252, step: 8
3547 10:06:54.102397 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3548 10:06:54.105401 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3549 10:06:54.112082 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3550 10:06:54.115721 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3551 10:06:54.118669 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3552 10:06:54.122136 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3553 10:06:54.125319 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3554 10:06:54.132258 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3555 10:06:54.135151 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3556 10:06:54.138624 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3557 10:06:54.142235 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3558 10:06:54.145293 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3559 10:06:54.151815 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3560 10:06:54.154993 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3561 10:06:54.158603 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3562 10:06:54.161722 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3563 10:06:54.161827 ==
3564 10:06:54.165233 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 10:06:54.171642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 10:06:54.171752 ==
3567 10:06:54.171856 DQS Delay:
3568 10:06:54.174816 DQS0 = 0, DQS1 = 0
3569 10:06:54.174926 DQM Delay:
3570 10:06:54.178416 DQM0 = 119, DQM1 = 112
3571 10:06:54.178500 DQ Delay:
3572 10:06:54.181498 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3573 10:06:54.184961 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3574 10:06:54.188184 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3575 10:06:54.191462 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3576 10:06:54.191545
3577 10:06:54.191610
3578 10:06:54.191671 ==
3579 10:06:54.194796 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 10:06:54.201598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 10:06:54.201681 ==
3582 10:06:54.201748
3583 10:06:54.201808
3584 10:06:54.201865 TX Vref Scan disable
3585 10:06:54.204718 == TX Byte 0 ==
3586 10:06:54.208333 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3587 10:06:54.214771 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3588 10:06:54.214854 == TX Byte 1 ==
3589 10:06:54.217954 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3590 10:06:54.224658 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3591 10:06:54.224742 ==
3592 10:06:54.227746 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 10:06:54.231292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 10:06:54.231376 ==
3595 10:06:54.242777 TX Vref=22, minBit 3, minWin=24, winSum=412
3596 10:06:54.245820 TX Vref=24, minBit 1, minWin=25, winSum=415
3597 10:06:54.249333 TX Vref=26, minBit 1, minWin=25, winSum=420
3598 10:06:54.252028 TX Vref=28, minBit 1, minWin=26, winSum=426
3599 10:06:54.255555 TX Vref=30, minBit 8, minWin=26, winSum=429
3600 10:06:54.262309 TX Vref=32, minBit 1, minWin=26, winSum=427
3601 10:06:54.265481 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 30
3602 10:06:54.265565
3603 10:06:54.268615 Final TX Range 1 Vref 30
3604 10:06:54.268725
3605 10:06:54.268834 ==
3606 10:06:54.272064 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 10:06:54.275462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 10:06:54.278665 ==
3609 10:06:54.278744
3610 10:06:54.278808
3611 10:06:54.278866 TX Vref Scan disable
3612 10:06:54.282104 == TX Byte 0 ==
3613 10:06:54.285657 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3614 10:06:54.292220 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3615 10:06:54.292344 == TX Byte 1 ==
3616 10:06:54.295625 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3617 10:06:54.302282 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3618 10:06:54.302371
3619 10:06:54.302435 [DATLAT]
3620 10:06:54.302495 Freq=1200, CH1 RK1
3621 10:06:54.302571
3622 10:06:54.305409 DATLAT Default: 0xd
3623 10:06:54.305488 0, 0xFFFF, sum = 0
3624 10:06:54.308469 1, 0xFFFF, sum = 0
3625 10:06:54.311930 2, 0xFFFF, sum = 0
3626 10:06:54.312014 3, 0xFFFF, sum = 0
3627 10:06:54.315437 4, 0xFFFF, sum = 0
3628 10:06:54.315526 5, 0xFFFF, sum = 0
3629 10:06:54.318496 6, 0xFFFF, sum = 0
3630 10:06:54.318576 7, 0xFFFF, sum = 0
3631 10:06:54.321661 8, 0xFFFF, sum = 0
3632 10:06:54.321765 9, 0xFFFF, sum = 0
3633 10:06:54.325242 10, 0xFFFF, sum = 0
3634 10:06:54.325314 11, 0xFFFF, sum = 0
3635 10:06:54.328606 12, 0x0, sum = 1
3636 10:06:54.328694 13, 0x0, sum = 2
3637 10:06:54.331640 14, 0x0, sum = 3
3638 10:06:54.331726 15, 0x0, sum = 4
3639 10:06:54.335057 best_step = 13
3640 10:06:54.335142
3641 10:06:54.335228 ==
3642 10:06:54.338341 Dram Type= 6, Freq= 0, CH_1, rank 1
3643 10:06:54.341539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3644 10:06:54.341643 ==
3645 10:06:54.344682 RX Vref Scan: 0
3646 10:06:54.344775
3647 10:06:54.344857 RX Vref 0 -> 0, step: 1
3648 10:06:54.344919
3649 10:06:54.348236 RX Delay -13 -> 252, step: 4
3650 10:06:54.354818 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3651 10:06:54.358080 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3652 10:06:54.361662 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3653 10:06:54.364696 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3654 10:06:54.367963 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3655 10:06:54.374312 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3656 10:06:54.377620 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3657 10:06:54.381015 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3658 10:06:54.384009 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3659 10:06:54.387590 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3660 10:06:54.394098 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3661 10:06:54.397517 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3662 10:06:54.400589 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3663 10:06:54.404127 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3664 10:06:54.410565 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3665 10:06:54.413868 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3666 10:06:54.413952 ==
3667 10:06:54.417235 Dram Type= 6, Freq= 0, CH_1, rank 1
3668 10:06:54.420678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3669 10:06:54.420786 ==
3670 10:06:54.423838 DQS Delay:
3671 10:06:54.423924 DQS0 = 0, DQS1 = 0
3672 10:06:54.424011 DQM Delay:
3673 10:06:54.427237 DQM0 = 119, DQM1 = 113
3674 10:06:54.427322 DQ Delay:
3675 10:06:54.430462 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3676 10:06:54.433844 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3677 10:06:54.437078 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3678 10:06:54.443713 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3679 10:06:54.443800
3680 10:06:54.443885
3681 10:06:54.450113 [DQSOSCAuto] RK1, (LSB)MR18= 0xcef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3682 10:06:54.453379 CH1 RK1: MR19=403, MR18=CEF
3683 10:06:54.460085 CH1_RK1: MR19=0x403, MR18=0xCEF, DQSOSC=405, MR23=63, INC=39, DEC=26
3684 10:06:54.463550 [RxdqsGatingPostProcess] freq 1200
3685 10:06:54.466703 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3686 10:06:54.470276 best DQS0 dly(2T, 0.5T) = (0, 11)
3687 10:06:54.473502 best DQS1 dly(2T, 0.5T) = (0, 11)
3688 10:06:54.476550 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3689 10:06:54.480136 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3690 10:06:54.483209 best DQS0 dly(2T, 0.5T) = (0, 11)
3691 10:06:54.486538 best DQS1 dly(2T, 0.5T) = (0, 11)
3692 10:06:54.490018 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3693 10:06:54.493920 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3694 10:06:54.496643 Pre-setting of DQS Precalculation
3695 10:06:54.499787 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3696 10:06:54.509693 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3697 10:06:54.516365 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3698 10:06:54.516451
3699 10:06:54.516522
3700 10:06:54.519409 [Calibration Summary] 2400 Mbps
3701 10:06:54.519494 CH 0, Rank 0
3702 10:06:54.523090 SW Impedance : PASS
3703 10:06:54.523174 DUTY Scan : NO K
3704 10:06:54.526368 ZQ Calibration : PASS
3705 10:06:54.529290 Jitter Meter : NO K
3706 10:06:54.529374 CBT Training : PASS
3707 10:06:54.532580 Write leveling : PASS
3708 10:06:54.535981 RX DQS gating : PASS
3709 10:06:54.536069 RX DQ/DQS(RDDQC) : PASS
3710 10:06:54.539229 TX DQ/DQS : PASS
3711 10:06:54.542995 RX DATLAT : PASS
3712 10:06:54.543106 RX DQ/DQS(Engine): PASS
3713 10:06:54.546019 TX OE : NO K
3714 10:06:54.546103 All Pass.
3715 10:06:54.546169
3716 10:06:54.549234 CH 0, Rank 1
3717 10:06:54.549317 SW Impedance : PASS
3718 10:06:54.552177 DUTY Scan : NO K
3719 10:06:54.555652 ZQ Calibration : PASS
3720 10:06:54.555729 Jitter Meter : NO K
3721 10:06:54.558739 CBT Training : PASS
3722 10:06:54.562187 Write leveling : PASS
3723 10:06:54.562274 RX DQS gating : PASS
3724 10:06:54.565318 RX DQ/DQS(RDDQC) : PASS
3725 10:06:54.568872 TX DQ/DQS : PASS
3726 10:06:54.568961 RX DATLAT : PASS
3727 10:06:54.572270 RX DQ/DQS(Engine): PASS
3728 10:06:54.575469 TX OE : NO K
3729 10:06:54.575557 All Pass.
3730 10:06:54.575627
3731 10:06:54.575695 CH 1, Rank 0
3732 10:06:54.578959 SW Impedance : PASS
3733 10:06:54.581975 DUTY Scan : NO K
3734 10:06:54.582054 ZQ Calibration : PASS
3735 10:06:54.585441 Jitter Meter : NO K
3736 10:06:54.585514 CBT Training : PASS
3737 10:06:54.588975 Write leveling : PASS
3738 10:06:54.591967 RX DQS gating : PASS
3739 10:06:54.592050 RX DQ/DQS(RDDQC) : PASS
3740 10:06:54.595387 TX DQ/DQS : PASS
3741 10:06:54.598575 RX DATLAT : PASS
3742 10:06:54.598661 RX DQ/DQS(Engine): PASS
3743 10:06:54.602146 TX OE : NO K
3744 10:06:54.602234 All Pass.
3745 10:06:54.602301
3746 10:06:54.605960 CH 1, Rank 1
3747 10:06:54.606034 SW Impedance : PASS
3748 10:06:54.608714 DUTY Scan : NO K
3749 10:06:54.612301 ZQ Calibration : PASS
3750 10:06:54.612487 Jitter Meter : NO K
3751 10:06:54.615528 CBT Training : PASS
3752 10:06:54.618770 Write leveling : PASS
3753 10:06:54.618860 RX DQS gating : PASS
3754 10:06:54.622006 RX DQ/DQS(RDDQC) : PASS
3755 10:06:54.625358 TX DQ/DQS : PASS
3756 10:06:54.625443 RX DATLAT : PASS
3757 10:06:54.628346 RX DQ/DQS(Engine): PASS
3758 10:06:54.631827 TX OE : NO K
3759 10:06:54.631914 All Pass.
3760 10:06:54.631983
3761 10:06:54.632046 DramC Write-DBI off
3762 10:06:54.634960 PER_BANK_REFRESH: Hybrid Mode
3763 10:06:54.638283 TX_TRACKING: ON
3764 10:06:54.644947 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3765 10:06:54.648085 [FAST_K] Save calibration result to emmc
3766 10:06:54.654958 dramc_set_vcore_voltage set vcore to 650000
3767 10:06:54.655042 Read voltage for 600, 5
3768 10:06:54.657985 Vio18 = 0
3769 10:06:54.658080 Vcore = 650000
3770 10:06:54.658147 Vdram = 0
3771 10:06:54.661569 Vddq = 0
3772 10:06:54.661653 Vmddr = 0
3773 10:06:54.664693 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3774 10:06:54.671081 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3775 10:06:54.674786 MEM_TYPE=3, freq_sel=19
3776 10:06:54.677830 sv_algorithm_assistance_LP4_1600
3777 10:06:54.681085 ============ PULL DRAM RESETB DOWN ============
3778 10:06:54.684541 ========== PULL DRAM RESETB DOWN end =========
3779 10:06:54.691135 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3780 10:06:54.694258 ===================================
3781 10:06:54.694339 LPDDR4 DRAM CONFIGURATION
3782 10:06:54.697712 ===================================
3783 10:06:54.701257 EX_ROW_EN[0] = 0x0
3784 10:06:54.701328 EX_ROW_EN[1] = 0x0
3785 10:06:54.704435 LP4Y_EN = 0x0
3786 10:06:54.704508 WORK_FSP = 0x0
3787 10:06:54.707745 WL = 0x2
3788 10:06:54.710971 RL = 0x2
3789 10:06:54.711045 BL = 0x2
3790 10:06:54.714289 RPST = 0x0
3791 10:06:54.714368 RD_PRE = 0x0
3792 10:06:54.717391 WR_PRE = 0x1
3793 10:06:54.717470 WR_PST = 0x0
3794 10:06:54.720632 DBI_WR = 0x0
3795 10:06:54.720739 DBI_RD = 0x0
3796 10:06:54.724289 OTF = 0x1
3797 10:06:54.727278 ===================================
3798 10:06:54.730583 ===================================
3799 10:06:54.730692 ANA top config
3800 10:06:54.733855 ===================================
3801 10:06:54.737420 DLL_ASYNC_EN = 0
3802 10:06:54.740542 ALL_SLAVE_EN = 1
3803 10:06:54.740629 NEW_RANK_MODE = 1
3804 10:06:54.743862 DLL_IDLE_MODE = 1
3805 10:06:54.747180 LP45_APHY_COMB_EN = 1
3806 10:06:54.750277 TX_ODT_DIS = 1
3807 10:06:54.753808 NEW_8X_MODE = 1
3808 10:06:54.756867 ===================================
3809 10:06:54.760150 ===================================
3810 10:06:54.760238 data_rate = 1200
3811 10:06:54.763613 CKR = 1
3812 10:06:54.766808 DQ_P2S_RATIO = 8
3813 10:06:54.770370 ===================================
3814 10:06:54.773455 CA_P2S_RATIO = 8
3815 10:06:54.776684 DQ_CA_OPEN = 0
3816 10:06:54.780298 DQ_SEMI_OPEN = 0
3817 10:06:54.780384 CA_SEMI_OPEN = 0
3818 10:06:54.783365 CA_FULL_RATE = 0
3819 10:06:54.787023 DQ_CKDIV4_EN = 1
3820 10:06:54.790100 CA_CKDIV4_EN = 1
3821 10:06:54.793325 CA_PREDIV_EN = 0
3822 10:06:54.796663 PH8_DLY = 0
3823 10:06:54.796750 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3824 10:06:54.800041 DQ_AAMCK_DIV = 4
3825 10:06:54.803385 CA_AAMCK_DIV = 4
3826 10:06:54.806501 CA_ADMCK_DIV = 4
3827 10:06:54.810031 DQ_TRACK_CA_EN = 0
3828 10:06:54.813450 CA_PICK = 600
3829 10:06:54.817026 CA_MCKIO = 600
3830 10:06:54.817112 MCKIO_SEMI = 0
3831 10:06:54.819893 PLL_FREQ = 2288
3832 10:06:54.823325 DQ_UI_PI_RATIO = 32
3833 10:06:54.826465 CA_UI_PI_RATIO = 0
3834 10:06:54.830058 ===================================
3835 10:06:54.833291 ===================================
3836 10:06:54.836400 memory_type:LPDDR4
3837 10:06:54.836491 GP_NUM : 10
3838 10:06:54.839500 SRAM_EN : 1
3839 10:06:54.843085 MD32_EN : 0
3840 10:06:54.846166 ===================================
3841 10:06:54.846254 [ANA_INIT] >>>>>>>>>>>>>>
3842 10:06:54.849425 <<<<<< [CONFIGURE PHASE]: ANA_TX
3843 10:06:54.853066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3844 10:06:54.856052 ===================================
3845 10:06:54.859300 data_rate = 1200,PCW = 0X5800
3846 10:06:54.862631 ===================================
3847 10:06:54.866055 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3848 10:06:54.872441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3849 10:06:54.875662 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3850 10:06:54.882622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3851 10:06:54.885847 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3852 10:06:54.888886 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3853 10:06:54.892579 [ANA_INIT] flow start
3854 10:06:54.892654 [ANA_INIT] PLL >>>>>>>>
3855 10:06:54.895525 [ANA_INIT] PLL <<<<<<<<
3856 10:06:54.898858 [ANA_INIT] MIDPI >>>>>>>>
3857 10:06:54.898931 [ANA_INIT] MIDPI <<<<<<<<
3858 10:06:54.902227 [ANA_INIT] DLL >>>>>>>>
3859 10:06:54.905512 [ANA_INIT] flow end
3860 10:06:54.908800 ============ LP4 DIFF to SE enter ============
3861 10:06:54.912356 ============ LP4 DIFF to SE exit ============
3862 10:06:54.915409 [ANA_INIT] <<<<<<<<<<<<<
3863 10:06:54.918670 [Flow] Enable top DCM control >>>>>
3864 10:06:54.922232 [Flow] Enable top DCM control <<<<<
3865 10:06:54.925473 Enable DLL master slave shuffle
3866 10:06:54.928612 ==============================================================
3867 10:06:54.931780 Gating Mode config
3868 10:06:54.938625 ==============================================================
3869 10:06:54.938710 Config description:
3870 10:06:54.948472 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3871 10:06:54.955270 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3872 10:06:54.961583 SELPH_MODE 0: By rank 1: By Phase
3873 10:06:54.965209 ==============================================================
3874 10:06:54.968267 GAT_TRACK_EN = 1
3875 10:06:54.971688 RX_GATING_MODE = 2
3876 10:06:54.974861 RX_GATING_TRACK_MODE = 2
3877 10:06:54.978309 SELPH_MODE = 1
3878 10:06:54.981460 PICG_EARLY_EN = 1
3879 10:06:54.984598 VALID_LAT_VALUE = 1
3880 10:06:54.988038 ==============================================================
3881 10:06:54.991143 Enter into Gating configuration >>>>
3882 10:06:54.994559 Exit from Gating configuration <<<<
3883 10:06:54.997747 Enter into DVFS_PRE_config >>>>>
3884 10:06:55.011281 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3885 10:06:55.014331 Exit from DVFS_PRE_config <<<<<
3886 10:06:55.017954 Enter into PICG configuration >>>>
3887 10:06:55.020954 Exit from PICG configuration <<<<
3888 10:06:55.021040 [RX_INPUT] configuration >>>>>
3889 10:06:55.024054 [RX_INPUT] configuration <<<<<
3890 10:06:55.030744 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3891 10:06:55.034439 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3892 10:06:55.040798 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3893 10:06:55.047395 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3894 10:06:55.053984 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3895 10:06:55.060514 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3896 10:06:55.063604 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3897 10:06:55.067180 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3898 10:06:55.073457 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3899 10:06:55.077318 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3900 10:06:55.080339 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3901 10:06:55.086903 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3902 10:06:55.090142 ===================================
3903 10:06:55.090228 LPDDR4 DRAM CONFIGURATION
3904 10:06:55.093326 ===================================
3905 10:06:55.096734 EX_ROW_EN[0] = 0x0
3906 10:06:55.096834 EX_ROW_EN[1] = 0x0
3907 10:06:55.099921 LP4Y_EN = 0x0
3908 10:06:55.099998 WORK_FSP = 0x0
3909 10:06:55.103464 WL = 0x2
3910 10:06:55.106603 RL = 0x2
3911 10:06:55.106716 BL = 0x2
3912 10:06:55.109777 RPST = 0x0
3913 10:06:55.109891 RD_PRE = 0x0
3914 10:06:55.113165 WR_PRE = 0x1
3915 10:06:55.113250 WR_PST = 0x0
3916 10:06:55.116702 DBI_WR = 0x0
3917 10:06:55.116822 DBI_RD = 0x0
3918 10:06:55.120069 OTF = 0x1
3919 10:06:55.123100 ===================================
3920 10:06:55.126863 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3921 10:06:55.130012 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3922 10:06:55.136955 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3923 10:06:55.139634 ===================================
3924 10:06:55.139739 LPDDR4 DRAM CONFIGURATION
3925 10:06:55.143270 ===================================
3926 10:06:55.146226 EX_ROW_EN[0] = 0x10
3927 10:06:55.146336 EX_ROW_EN[1] = 0x0
3928 10:06:55.149581 LP4Y_EN = 0x0
3929 10:06:55.149662 WORK_FSP = 0x0
3930 10:06:55.153288 WL = 0x2
3931 10:06:55.156413 RL = 0x2
3932 10:06:55.156519 BL = 0x2
3933 10:06:55.159608 RPST = 0x0
3934 10:06:55.159712 RD_PRE = 0x0
3935 10:06:55.162688 WR_PRE = 0x1
3936 10:06:55.162792 WR_PST = 0x0
3937 10:06:55.166291 DBI_WR = 0x0
3938 10:06:55.166390 DBI_RD = 0x0
3939 10:06:55.169718 OTF = 0x1
3940 10:06:55.172721 ===================================
3941 10:06:55.179190 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3942 10:06:55.182654 nWR fixed to 30
3943 10:06:55.182758 [ModeRegInit_LP4] CH0 RK0
3944 10:06:55.185867 [ModeRegInit_LP4] CH0 RK1
3945 10:06:55.189334 [ModeRegInit_LP4] CH1 RK0
3946 10:06:55.189432 [ModeRegInit_LP4] CH1 RK1
3947 10:06:55.192520 match AC timing 17
3948 10:06:55.195744 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3949 10:06:55.202646 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3950 10:06:55.205753 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3951 10:06:55.212359 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3952 10:06:55.215742 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3953 10:06:55.215850 ==
3954 10:06:55.219071 Dram Type= 6, Freq= 0, CH_0, rank 0
3955 10:06:55.222164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3956 10:06:55.222250 ==
3957 10:06:55.228896 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3958 10:06:55.235595 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3959 10:06:55.238777 [CA 0] Center 36 (5~67) winsize 63
3960 10:06:55.241847 [CA 1] Center 36 (6~67) winsize 62
3961 10:06:55.245223 [CA 2] Center 34 (4~65) winsize 62
3962 10:06:55.248477 [CA 3] Center 34 (3~65) winsize 63
3963 10:06:55.252171 [CA 4] Center 33 (3~64) winsize 62
3964 10:06:55.255283 [CA 5] Center 33 (2~64) winsize 63
3965 10:06:55.255368
3966 10:06:55.258245 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3967 10:06:55.258330
3968 10:06:55.261711 [CATrainingPosCal] consider 1 rank data
3969 10:06:55.264884 u2DelayCellTimex100 = 270/100 ps
3970 10:06:55.268479 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3971 10:06:55.271769 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3972 10:06:55.275306 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3973 10:06:55.278294 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3974 10:06:55.281959 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3975 10:06:55.284909 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3976 10:06:55.287926
3977 10:06:55.291228 CA PerBit enable=1, Macro0, CA PI delay=33
3978 10:06:55.291334
3979 10:06:55.294803 [CBTSetCACLKResult] CA Dly = 33
3980 10:06:55.294887 CS Dly: 5 (0~36)
3981 10:06:55.294954 ==
3982 10:06:55.298017 Dram Type= 6, Freq= 0, CH_0, rank 1
3983 10:06:55.301346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 10:06:55.301488 ==
3985 10:06:55.307968 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3986 10:06:55.314858 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3987 10:06:55.317810 [CA 0] Center 36 (6~67) winsize 62
3988 10:06:55.321159 [CA 1] Center 36 (6~67) winsize 62
3989 10:06:55.324618 [CA 2] Center 35 (4~66) winsize 63
3990 10:06:55.327791 [CA 3] Center 34 (4~65) winsize 62
3991 10:06:55.331379 [CA 4] Center 34 (3~65) winsize 63
3992 10:06:55.334456 [CA 5] Center 33 (3~64) winsize 62
3993 10:06:55.334570
3994 10:06:55.337739 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3995 10:06:55.337842
3996 10:06:55.341407 [CATrainingPosCal] consider 2 rank data
3997 10:06:55.344390 u2DelayCellTimex100 = 270/100 ps
3998 10:06:55.347889 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3999 10:06:55.351660 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4000 10:06:55.354283 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4001 10:06:55.357897 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4002 10:06:55.364241 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4003 10:06:55.367510 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4004 10:06:55.367610
4005 10:06:55.371093 CA PerBit enable=1, Macro0, CA PI delay=33
4006 10:06:55.371198
4007 10:06:55.374103 [CBTSetCACLKResult] CA Dly = 33
4008 10:06:55.374205 CS Dly: 6 (0~38)
4009 10:06:55.374311
4010 10:06:55.377486 ----->DramcWriteLeveling(PI) begin...
4011 10:06:55.377564 ==
4012 10:06:55.381062 Dram Type= 6, Freq= 0, CH_0, rank 0
4013 10:06:55.387613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4014 10:06:55.387719 ==
4015 10:06:55.390677 Write leveling (Byte 0): 34 => 34
4016 10:06:55.394236 Write leveling (Byte 1): 29 => 29
4017 10:06:55.394325 DramcWriteLeveling(PI) end<-----
4018 10:06:55.397323
4019 10:06:55.397408 ==
4020 10:06:55.400756 Dram Type= 6, Freq= 0, CH_0, rank 0
4021 10:06:55.404316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4022 10:06:55.404402 ==
4023 10:06:55.407525 [Gating] SW mode calibration
4024 10:06:55.414145 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4025 10:06:55.417428 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4026 10:06:55.424077 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4027 10:06:55.427296 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4028 10:06:55.430958 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4029 10:06:55.437021 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4030 10:06:55.440660 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
4031 10:06:55.444249 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 10:06:55.450824 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 10:06:55.454063 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 10:06:55.457241 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 10:06:55.463537 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 10:06:55.466866 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 10:06:55.470333 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4038 10:06:55.476891 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
4039 10:06:55.480095 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 10:06:55.483348 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 10:06:55.489911 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 10:06:55.493164 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 10:06:55.496700 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 10:06:55.503327 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 10:06:55.506572 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4046 10:06:55.509758 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4047 10:06:55.516435 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 10:06:55.520099 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 10:06:55.523218 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 10:06:55.529427 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 10:06:55.532824 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 10:06:55.536452 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 10:06:55.542630 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 10:06:55.546277 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 10:06:55.549300 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 10:06:55.556034 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 10:06:55.559141 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 10:06:55.562419 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 10:06:55.569327 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 10:06:55.572587 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4061 10:06:55.575739 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4062 10:06:55.582209 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4063 10:06:55.582292 Total UI for P1: 0, mck2ui 16
4064 10:06:55.588755 best dqsien dly found for B0: ( 0, 13, 10)
4065 10:06:55.592364 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 10:06:55.595559 Total UI for P1: 0, mck2ui 16
4067 10:06:55.598728 best dqsien dly found for B1: ( 0, 13, 16)
4068 10:06:55.602217 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4069 10:06:55.605361 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4070 10:06:55.605453
4071 10:06:55.608854 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4072 10:06:55.612268 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4073 10:06:55.615285 [Gating] SW calibration Done
4074 10:06:55.615361 ==
4075 10:06:55.618978 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 10:06:55.622103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 10:06:55.625569 ==
4078 10:06:55.625651 RX Vref Scan: 0
4079 10:06:55.625716
4080 10:06:55.628650 RX Vref 0 -> 0, step: 1
4081 10:06:55.628758
4082 10:06:55.631821 RX Delay -230 -> 252, step: 16
4083 10:06:55.635225 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4084 10:06:55.638830 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4085 10:06:55.642078 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4086 10:06:55.648617 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4087 10:06:55.651730 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4088 10:06:55.655227 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4089 10:06:55.658374 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4090 10:06:55.665224 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4091 10:06:55.668172 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4092 10:06:55.671666 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4093 10:06:55.674651 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4094 10:06:55.678162 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4095 10:06:55.684605 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4096 10:06:55.688130 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4097 10:06:55.691470 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4098 10:06:55.694570 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4099 10:06:55.697946 ==
4100 10:06:55.701451 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 10:06:55.704582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 10:06:55.704667 ==
4103 10:06:55.704734 DQS Delay:
4104 10:06:55.707805 DQS0 = 0, DQS1 = 0
4105 10:06:55.707892 DQM Delay:
4106 10:06:55.711390 DQM0 = 53, DQM1 = 42
4107 10:06:55.711474 DQ Delay:
4108 10:06:55.714461 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4109 10:06:55.717611 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4110 10:06:55.721120 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4111 10:06:55.724559 DQ12 =49, DQ13 =41, DQ14 =57, DQ15 =49
4112 10:06:55.724674
4113 10:06:55.724777
4114 10:06:55.724877 ==
4115 10:06:55.727621 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 10:06:55.730821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 10:06:55.730936 ==
4118 10:06:55.731031
4119 10:06:55.731123
4120 10:06:55.734415 TX Vref Scan disable
4121 10:06:55.737694 == TX Byte 0 ==
4122 10:06:55.740822 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4123 10:06:55.744175 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4124 10:06:55.747297 == TX Byte 1 ==
4125 10:06:55.751049 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4126 10:06:55.754017 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4127 10:06:55.754101 ==
4128 10:06:55.757593 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 10:06:55.764003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 10:06:55.764086 ==
4131 10:06:55.764153
4132 10:06:55.764214
4133 10:06:55.764280 TX Vref Scan disable
4134 10:06:55.768648 == TX Byte 0 ==
4135 10:06:55.771597 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4136 10:06:55.778281 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4137 10:06:55.778364 == TX Byte 1 ==
4138 10:06:55.781754 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4139 10:06:55.788153 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4140 10:06:55.788279
4141 10:06:55.788348 [DATLAT]
4142 10:06:55.788411 Freq=600, CH0 RK0
4143 10:06:55.788472
4144 10:06:55.791885 DATLAT Default: 0x9
4145 10:06:55.795086 0, 0xFFFF, sum = 0
4146 10:06:55.795171 1, 0xFFFF, sum = 0
4147 10:06:55.798207 2, 0xFFFF, sum = 0
4148 10:06:55.798292 3, 0xFFFF, sum = 0
4149 10:06:55.801728 4, 0xFFFF, sum = 0
4150 10:06:55.801813 5, 0xFFFF, sum = 0
4151 10:06:55.804624 6, 0xFFFF, sum = 0
4152 10:06:55.804723 7, 0xFFFF, sum = 0
4153 10:06:55.808116 8, 0x0, sum = 1
4154 10:06:55.808215 9, 0x0, sum = 2
4155 10:06:55.811280 10, 0x0, sum = 3
4156 10:06:55.811364 11, 0x0, sum = 4
4157 10:06:55.811431 best_step = 9
4158 10:06:55.811490
4159 10:06:55.814899 ==
4160 10:06:55.818158 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 10:06:55.821640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 10:06:55.821726 ==
4163 10:06:55.821793 RX Vref Scan: 1
4164 10:06:55.821854
4165 10:06:55.824724 RX Vref 0 -> 0, step: 1
4166 10:06:55.824857
4167 10:06:55.827755 RX Delay -163 -> 252, step: 8
4168 10:06:55.827838
4169 10:06:55.831298 Set Vref, RX VrefLevel [Byte0]: 59
4170 10:06:55.834409 [Byte1]: 49
4171 10:06:55.834492
4172 10:06:55.837630 Final RX Vref Byte 0 = 59 to rank0
4173 10:06:55.840781 Final RX Vref Byte 1 = 49 to rank0
4174 10:06:55.844160 Final RX Vref Byte 0 = 59 to rank1
4175 10:06:55.847677 Final RX Vref Byte 1 = 49 to rank1==
4176 10:06:55.850919 Dram Type= 6, Freq= 0, CH_0, rank 0
4177 10:06:55.854432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 10:06:55.857605 ==
4179 10:06:55.857688 DQS Delay:
4180 10:06:55.857755 DQS0 = 0, DQS1 = 0
4181 10:06:55.860504 DQM Delay:
4182 10:06:55.860588 DQM0 = 50, DQM1 = 37
4183 10:06:55.864090 DQ Delay:
4184 10:06:55.867600 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =48
4185 10:06:55.867683 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4186 10:06:55.873819 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4187 10:06:55.877063 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4188 10:06:55.877146
4189 10:06:55.877215
4190 10:06:55.884036 [DQSOSCAuto] RK0, (LSB)MR18= 0x5852, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4191 10:06:55.887253 CH0 RK0: MR19=808, MR18=5852
4192 10:06:55.893400 CH0_RK0: MR19=0x808, MR18=0x5852, DQSOSC=393, MR23=63, INC=169, DEC=113
4193 10:06:55.893486
4194 10:06:55.896911 ----->DramcWriteLeveling(PI) begin...
4195 10:06:55.896995 ==
4196 10:06:55.900266 Dram Type= 6, Freq= 0, CH_0, rank 1
4197 10:06:55.903242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 10:06:55.903325 ==
4199 10:06:55.906725 Write leveling (Byte 0): 37 => 37
4200 10:06:55.909926 Write leveling (Byte 1): 30 => 30
4201 10:06:55.913007 DramcWriteLeveling(PI) end<-----
4202 10:06:55.913090
4203 10:06:55.913156 ==
4204 10:06:55.916575 Dram Type= 6, Freq= 0, CH_0, rank 1
4205 10:06:55.919673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 10:06:55.923264 ==
4207 10:06:55.923347 [Gating] SW mode calibration
4208 10:06:55.933157 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4209 10:06:55.936200 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4210 10:06:55.939846 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4211 10:06:55.946382 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4212 10:06:55.949412 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4213 10:06:55.952966 0 9 12 | B1->B0 | 3434 3232 | 0 0 | (0 1) (0 1)
4214 10:06:55.959593 0 9 16 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
4215 10:06:55.962752 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 10:06:55.965923 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 10:06:55.972972 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 10:06:55.976298 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 10:06:55.979310 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 10:06:55.986169 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 10:06:55.989403 0 10 12 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
4222 10:06:55.992553 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4223 10:06:55.999203 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 10:06:56.002362 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 10:06:56.005827 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 10:06:56.012255 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 10:06:56.015768 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 10:06:56.018573 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 10:06:56.025395 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4230 10:06:56.028577 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4231 10:06:56.032167 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 10:06:56.038512 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 10:06:56.042008 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 10:06:56.045160 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 10:06:56.051736 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 10:06:56.055306 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 10:06:56.058280 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 10:06:56.065073 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 10:06:56.068516 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 10:06:56.071639 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 10:06:56.078395 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 10:06:56.081504 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 10:06:56.084660 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 10:06:56.091284 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 10:06:56.094724 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 10:06:56.098026 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 10:06:56.101362 Total UI for P1: 0, mck2ui 16
4248 10:06:56.104558 best dqsien dly found for B0: ( 0, 13, 14)
4249 10:06:56.107683 Total UI for P1: 0, mck2ui 16
4250 10:06:56.111088 best dqsien dly found for B1: ( 0, 13, 14)
4251 10:06:56.114432 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4252 10:06:56.117595 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4253 10:06:56.117675
4254 10:06:56.124388 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4255 10:06:56.127716 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4256 10:06:56.130896 [Gating] SW calibration Done
4257 10:06:56.130971 ==
4258 10:06:56.134099 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 10:06:56.137427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 10:06:56.137514 ==
4261 10:06:56.137583 RX Vref Scan: 0
4262 10:06:56.140949
4263 10:06:56.141034 RX Vref 0 -> 0, step: 1
4264 10:06:56.141103
4265 10:06:56.144127 RX Delay -230 -> 252, step: 16
4266 10:06:56.147314 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4267 10:06:56.154039 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4268 10:06:56.157524 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4269 10:06:56.160753 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4270 10:06:56.164076 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4271 10:06:56.167423 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4272 10:06:56.174214 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4273 10:06:56.177290 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4274 10:06:56.180314 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4275 10:06:56.183776 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4276 10:06:56.190208 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4277 10:06:56.193716 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4278 10:06:56.196733 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4279 10:06:56.200451 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4280 10:06:56.206919 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4281 10:06:56.209988 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4282 10:06:56.210100 ==
4283 10:06:56.213588 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 10:06:56.216733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 10:06:56.216831 ==
4286 10:06:56.219901 DQS Delay:
4287 10:06:56.219994 DQS0 = 0, DQS1 = 0
4288 10:06:56.220088 DQM Delay:
4289 10:06:56.223508 DQM0 = 52, DQM1 = 45
4290 10:06:56.223597 DQ Delay:
4291 10:06:56.226766 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4292 10:06:56.230202 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4293 10:06:56.233274 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4294 10:06:56.237015 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4295 10:06:56.237101
4296 10:06:56.237168
4297 10:06:56.237230 ==
4298 10:06:56.239675 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 10:06:56.246389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 10:06:56.246505 ==
4301 10:06:56.246606
4302 10:06:56.246699
4303 10:06:56.246792 TX Vref Scan disable
4304 10:06:56.250377 == TX Byte 0 ==
4305 10:06:56.253519 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4306 10:06:56.260226 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4307 10:06:56.260343 == TX Byte 1 ==
4308 10:06:56.263520 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4309 10:06:56.270375 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4310 10:06:56.270486 ==
4311 10:06:56.273506 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 10:06:56.276580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 10:06:56.276686 ==
4314 10:06:56.276792
4315 10:06:56.276887
4316 10:06:56.280362 TX Vref Scan disable
4317 10:06:56.283277 == TX Byte 0 ==
4318 10:06:56.286438 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4319 10:06:56.289975 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4320 10:06:56.293091 == TX Byte 1 ==
4321 10:06:56.296269 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4322 10:06:56.299710 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4323 10:06:56.299829
4324 10:06:56.302836 [DATLAT]
4325 10:06:56.302943 Freq=600, CH0 RK1
4326 10:06:56.303038
4327 10:06:56.306251 DATLAT Default: 0x9
4328 10:06:56.306362 0, 0xFFFF, sum = 0
4329 10:06:56.309250 1, 0xFFFF, sum = 0
4330 10:06:56.309363 2, 0xFFFF, sum = 0
4331 10:06:56.312990 3, 0xFFFF, sum = 0
4332 10:06:56.313100 4, 0xFFFF, sum = 0
4333 10:06:56.316243 5, 0xFFFF, sum = 0
4334 10:06:56.316355 6, 0xFFFF, sum = 0
4335 10:06:56.319570 7, 0xFFFF, sum = 0
4336 10:06:56.319686 8, 0x0, sum = 1
4337 10:06:56.322736 9, 0x0, sum = 2
4338 10:06:56.322848 10, 0x0, sum = 3
4339 10:06:56.325963 11, 0x0, sum = 4
4340 10:06:56.326070 best_step = 9
4341 10:06:56.326168
4342 10:06:56.326261 ==
4343 10:06:56.329362 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 10:06:56.332448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 10:06:56.336029 ==
4346 10:06:56.336138 RX Vref Scan: 0
4347 10:06:56.336234
4348 10:06:56.339341 RX Vref 0 -> 0, step: 1
4349 10:06:56.339453
4350 10:06:56.342400 RX Delay -163 -> 252, step: 8
4351 10:06:56.345981 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4352 10:06:56.349020 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4353 10:06:56.355901 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4354 10:06:56.358885 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4355 10:06:56.362429 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4356 10:06:56.365822 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4357 10:06:56.368751 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4358 10:06:56.375538 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4359 10:06:56.378599 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4360 10:06:56.382235 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4361 10:06:56.385380 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4362 10:06:56.391926 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4363 10:06:56.395503 iDelay=205, Bit 12, Center 44 (-99 ~ 188) 288
4364 10:06:56.398629 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4365 10:06:56.401796 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4366 10:06:56.408778 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4367 10:06:56.408893 ==
4368 10:06:56.411880 Dram Type= 6, Freq= 0, CH_0, rank 1
4369 10:06:56.415178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 10:06:56.415292 ==
4371 10:06:56.415377 DQS Delay:
4372 10:06:56.418159 DQS0 = 0, DQS1 = 0
4373 10:06:56.418276 DQM Delay:
4374 10:06:56.421568 DQM0 = 48, DQM1 = 41
4375 10:06:56.421669 DQ Delay:
4376 10:06:56.425082 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4377 10:06:56.428905 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4378 10:06:56.431761 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4379 10:06:56.434882 DQ12 =44, DQ13 =48, DQ14 =52, DQ15 =52
4380 10:06:56.434991
4381 10:06:56.435094
4382 10:06:56.441800 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f2d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
4383 10:06:56.444680 CH0 RK1: MR19=808, MR18=5F2D
4384 10:06:56.451540 CH0_RK1: MR19=0x808, MR18=0x5F2D, DQSOSC=391, MR23=63, INC=171, DEC=114
4385 10:06:56.454980 [RxdqsGatingPostProcess] freq 600
4386 10:06:56.461318 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4387 10:06:56.464588 Pre-setting of DQS Precalculation
4388 10:06:56.468006 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4389 10:06:56.468100 ==
4390 10:06:56.471261 Dram Type= 6, Freq= 0, CH_1, rank 0
4391 10:06:56.474459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 10:06:56.474568 ==
4393 10:06:56.481322 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4394 10:06:56.487432 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4395 10:06:56.491004 [CA 0] Center 35 (5~66) winsize 62
4396 10:06:56.494311 [CA 1] Center 35 (5~66) winsize 62
4397 10:06:56.497871 [CA 2] Center 34 (4~65) winsize 62
4398 10:06:56.500906 [CA 3] Center 33 (3~64) winsize 62
4399 10:06:56.504381 [CA 4] Center 34 (3~65) winsize 63
4400 10:06:56.507456 [CA 5] Center 33 (3~64) winsize 62
4401 10:06:56.507610
4402 10:06:56.510794 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4403 10:06:56.510897
4404 10:06:56.514233 [CATrainingPosCal] consider 1 rank data
4405 10:06:56.517785 u2DelayCellTimex100 = 270/100 ps
4406 10:06:56.521061 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4407 10:06:56.524299 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4408 10:06:56.527722 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4409 10:06:56.530975 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4410 10:06:56.537134 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4411 10:06:56.540333 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4412 10:06:56.540443
4413 10:06:56.543987 CA PerBit enable=1, Macro0, CA PI delay=33
4414 10:06:56.544070
4415 10:06:56.547045 [CBTSetCACLKResult] CA Dly = 33
4416 10:06:56.547157 CS Dly: 5 (0~36)
4417 10:06:56.547288 ==
4418 10:06:56.550525 Dram Type= 6, Freq= 0, CH_1, rank 1
4419 10:06:56.556879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 10:06:56.556994 ==
4421 10:06:56.560471 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4422 10:06:56.567099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4423 10:06:56.570480 [CA 0] Center 35 (5~66) winsize 62
4424 10:06:56.573787 [CA 1] Center 35 (5~66) winsize 62
4425 10:06:56.576848 [CA 2] Center 34 (4~65) winsize 62
4426 10:06:56.580067 [CA 3] Center 34 (4~65) winsize 62
4427 10:06:56.583521 [CA 4] Center 34 (4~64) winsize 61
4428 10:06:56.586838 [CA 5] Center 34 (3~65) winsize 63
4429 10:06:56.586922
4430 10:06:56.589884 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4431 10:06:56.589960
4432 10:06:56.593367 [CATrainingPosCal] consider 2 rank data
4433 10:06:56.596784 u2DelayCellTimex100 = 270/100 ps
4434 10:06:56.599961 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4435 10:06:56.606673 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4436 10:06:56.609866 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4437 10:06:56.613479 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4438 10:06:56.616461 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4439 10:06:56.620128 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4440 10:06:56.620207
4441 10:06:56.623517 CA PerBit enable=1, Macro0, CA PI delay=33
4442 10:06:56.623639
4443 10:06:56.626671 [CBTSetCACLKResult] CA Dly = 33
4444 10:06:56.626774 CS Dly: 5 (0~36)
4445 10:06:56.629998
4446 10:06:56.633154 ----->DramcWriteLeveling(PI) begin...
4447 10:06:56.633240 ==
4448 10:06:56.636537 Dram Type= 6, Freq= 0, CH_1, rank 0
4449 10:06:56.639807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4450 10:06:56.639893 ==
4451 10:06:56.643010 Write leveling (Byte 0): 29 => 29
4452 10:06:56.646297 Write leveling (Byte 1): 29 => 29
4453 10:06:56.649917 DramcWriteLeveling(PI) end<-----
4454 10:06:56.650004
4455 10:06:56.650072 ==
4456 10:06:56.653078 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 10:06:56.656531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 10:06:56.656617 ==
4459 10:06:56.659602 [Gating] SW mode calibration
4460 10:06:56.666202 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4461 10:06:56.672785 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4462 10:06:56.676092 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4463 10:06:56.679613 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4464 10:06:56.685993 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4465 10:06:56.689145 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (1 1)
4466 10:06:56.692609 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 10:06:56.699038 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 10:06:56.702443 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 10:06:56.705894 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 10:06:56.712210 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 10:06:56.715730 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 10:06:56.719312 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4473 10:06:56.725862 0 10 12 | B1->B0 | 3737 3a3a | 0 0 | (0 0) (0 0)
4474 10:06:56.729020 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 10:06:56.732038 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 10:06:56.738735 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 10:06:56.742095 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 10:06:56.745421 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 10:06:56.751982 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 10:06:56.755158 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4481 10:06:56.758779 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4482 10:06:56.765075 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 10:06:56.768646 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 10:06:56.771797 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 10:06:56.778379 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 10:06:56.781786 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 10:06:56.784952 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 10:06:56.791687 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 10:06:56.795320 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 10:06:56.798351 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 10:06:56.805155 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 10:06:56.808464 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 10:06:56.811612 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 10:06:56.818308 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 10:06:56.821347 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 10:06:56.824601 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4497 10:06:56.831427 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4498 10:06:56.834662 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 10:06:56.837813 Total UI for P1: 0, mck2ui 16
4500 10:06:56.841253 best dqsien dly found for B0: ( 0, 13, 10)
4501 10:06:56.844456 Total UI for P1: 0, mck2ui 16
4502 10:06:56.847683 best dqsien dly found for B1: ( 0, 13, 12)
4503 10:06:56.851406 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4504 10:06:56.854289 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4505 10:06:56.854403
4506 10:06:56.857627 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4507 10:06:56.861000 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4508 10:06:56.864340 [Gating] SW calibration Done
4509 10:06:56.864444 ==
4510 10:06:56.867774 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 10:06:56.871092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 10:06:56.874353 ==
4513 10:06:56.874599 RX Vref Scan: 0
4514 10:06:56.874695
4515 10:06:56.877592 RX Vref 0 -> 0, step: 1
4516 10:06:56.877720
4517 10:06:56.880673 RX Delay -230 -> 252, step: 16
4518 10:06:56.884082 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4519 10:06:56.887362 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4520 10:06:56.890910 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4521 10:06:56.897188 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4522 10:06:56.900821 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4523 10:06:56.903892 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4524 10:06:56.907042 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4525 10:06:56.910550 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4526 10:06:56.916892 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4527 10:06:56.920305 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4528 10:06:56.923437 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4529 10:06:56.927122 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4530 10:06:56.933572 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4531 10:06:56.936667 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4532 10:06:56.940258 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4533 10:06:56.943346 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4534 10:06:56.943473 ==
4535 10:06:56.946381 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 10:06:56.953562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 10:06:56.953674 ==
4538 10:06:56.953783 DQS Delay:
4539 10:06:56.956445 DQS0 = 0, DQS1 = 0
4540 10:06:56.956548 DQM Delay:
4541 10:06:56.959657 DQM0 = 54, DQM1 = 45
4542 10:06:56.959744 DQ Delay:
4543 10:06:56.963112 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4544 10:06:56.966396 DQ4 =57, DQ5 =57, DQ6 =65, DQ7 =49
4545 10:06:56.969755 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4546 10:06:56.973019 DQ12 =65, DQ13 =49, DQ14 =49, DQ15 =49
4547 10:06:56.973104
4548 10:06:56.973169
4549 10:06:56.973231 ==
4550 10:06:56.976469 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 10:06:56.979624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 10:06:56.979734 ==
4553 10:06:56.979830
4554 10:06:56.979906
4555 10:06:56.983155 TX Vref Scan disable
4556 10:06:56.986483 == TX Byte 0 ==
4557 10:06:56.989323 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4558 10:06:56.992821 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4559 10:06:56.995945 == TX Byte 1 ==
4560 10:06:56.999566 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4561 10:06:57.002737 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4562 10:06:57.002843 ==
4563 10:06:57.005844 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 10:06:57.009573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 10:06:57.012679 ==
4566 10:06:57.012809
4567 10:06:57.012878
4568 10:06:57.012940 TX Vref Scan disable
4569 10:06:57.016616 == TX Byte 0 ==
4570 10:06:57.020268 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4571 10:06:57.026524 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4572 10:06:57.026609 == TX Byte 1 ==
4573 10:06:57.029932 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4574 10:06:57.036651 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4575 10:06:57.036763
4576 10:06:57.036840 [DATLAT]
4577 10:06:57.036904 Freq=600, CH1 RK0
4578 10:06:57.036982
4579 10:06:57.039770 DATLAT Default: 0x9
4580 10:06:57.039855 0, 0xFFFF, sum = 0
4581 10:06:57.043429 1, 0xFFFF, sum = 0
4582 10:06:57.046404 2, 0xFFFF, sum = 0
4583 10:06:57.046491 3, 0xFFFF, sum = 0
4584 10:06:57.050016 4, 0xFFFF, sum = 0
4585 10:06:57.050102 5, 0xFFFF, sum = 0
4586 10:06:57.053134 6, 0xFFFF, sum = 0
4587 10:06:57.053222 7, 0xFFFF, sum = 0
4588 10:06:57.056359 8, 0x0, sum = 1
4589 10:06:57.056446 9, 0x0, sum = 2
4590 10:06:57.056528 10, 0x0, sum = 3
4591 10:06:57.059456 11, 0x0, sum = 4
4592 10:06:57.059550 best_step = 9
4593 10:06:57.059627
4594 10:06:57.063045 ==
4595 10:06:57.063124 Dram Type= 6, Freq= 0, CH_1, rank 0
4596 10:06:57.069570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 10:06:57.069667 ==
4598 10:06:57.069740 RX Vref Scan: 1
4599 10:06:57.069813
4600 10:06:57.073143 RX Vref 0 -> 0, step: 1
4601 10:06:57.073222
4602 10:06:57.076114 RX Delay -179 -> 252, step: 8
4603 10:06:57.076203
4604 10:06:57.079525 Set Vref, RX VrefLevel [Byte0]: 50
4605 10:06:57.082705 [Byte1]: 50
4606 10:06:57.082790
4607 10:06:57.085997 Final RX Vref Byte 0 = 50 to rank0
4608 10:06:57.089596 Final RX Vref Byte 1 = 50 to rank0
4609 10:06:57.092778 Final RX Vref Byte 0 = 50 to rank1
4610 10:06:57.095813 Final RX Vref Byte 1 = 50 to rank1==
4611 10:06:57.099282 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 10:06:57.102968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 10:06:57.103055 ==
4614 10:06:57.106071 DQS Delay:
4615 10:06:57.106147 DQS0 = 0, DQS1 = 0
4616 10:06:57.108974 DQM Delay:
4617 10:06:57.109061 DQM0 = 49, DQM1 = 41
4618 10:06:57.112466 DQ Delay:
4619 10:06:57.112552 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4620 10:06:57.116049 DQ4 =52, DQ5 =60, DQ6 =60, DQ7 =44
4621 10:06:57.119172 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4622 10:06:57.122324 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4623 10:06:57.122419
4624 10:06:57.125783
4625 10:06:57.132009 [DQSOSCAuto] RK0, (LSB)MR18= 0x486f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4626 10:06:57.135456 CH1 RK0: MR19=808, MR18=486F
4627 10:06:57.141988 CH1_RK0: MR19=0x808, MR18=0x486F, DQSOSC=389, MR23=63, INC=173, DEC=115
4628 10:06:57.142072
4629 10:06:57.145224 ----->DramcWriteLeveling(PI) begin...
4630 10:06:57.145309 ==
4631 10:06:57.148709 Dram Type= 6, Freq= 0, CH_1, rank 1
4632 10:06:57.152004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 10:06:57.152090 ==
4634 10:06:57.155127 Write leveling (Byte 0): 30 => 30
4635 10:06:57.158682 Write leveling (Byte 1): 29 => 29
4636 10:06:57.162002 DramcWriteLeveling(PI) end<-----
4637 10:06:57.162086
4638 10:06:57.162151 ==
4639 10:06:57.165432 Dram Type= 6, Freq= 0, CH_1, rank 1
4640 10:06:57.168505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 10:06:57.168589 ==
4642 10:06:57.171879 [Gating] SW mode calibration
4643 10:06:57.178176 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4644 10:06:57.185207 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4645 10:06:57.188306 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4646 10:06:57.195272 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4647 10:06:57.198130 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
4648 10:06:57.201648 0 9 12 | B1->B0 | 2a2a 3232 | 0 0 | (1 0) (0 1)
4649 10:06:57.208052 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 10:06:57.211591 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 10:06:57.214730 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 10:06:57.221387 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 10:06:57.224883 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 10:06:57.228063 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 10:06:57.231666 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 10:06:57.238317 0 10 12 | B1->B0 | 3a3a 2f2f | 1 0 | (0 0) (0 0)
4657 10:06:57.241429 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4658 10:06:57.244335 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 10:06:57.251183 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 10:06:57.254310 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 10:06:57.257876 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 10:06:57.264139 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 10:06:57.267804 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 10:06:57.270972 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4665 10:06:57.277246 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 10:06:57.280567 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 10:06:57.283963 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 10:06:57.290770 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 10:06:57.294000 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 10:06:57.297040 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 10:06:57.303616 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 10:06:57.307341 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 10:06:57.310431 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 10:06:57.317304 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 10:06:57.320366 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 10:06:57.326956 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 10:06:57.330168 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 10:06:57.333241 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 10:06:57.336739 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 10:06:57.343187 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 10:06:57.346671 Total UI for P1: 0, mck2ui 16
4682 10:06:57.349698 best dqsien dly found for B0: ( 0, 13, 10)
4683 10:06:57.353325 Total UI for P1: 0, mck2ui 16
4684 10:06:57.356471 best dqsien dly found for B1: ( 0, 13, 10)
4685 10:06:57.360002 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4686 10:06:57.363083 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4687 10:06:57.363161
4688 10:06:57.366328 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4689 10:06:57.369744 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4690 10:06:57.372981 [Gating] SW calibration Done
4691 10:06:57.373070 ==
4692 10:06:57.376092 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 10:06:57.379665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 10:06:57.382848 ==
4695 10:06:57.382934 RX Vref Scan: 0
4696 10:06:57.383008
4697 10:06:57.386005 RX Vref 0 -> 0, step: 1
4698 10:06:57.386091
4699 10:06:57.389496 RX Delay -230 -> 252, step: 16
4700 10:06:57.392946 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4701 10:06:57.395968 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4702 10:06:57.399293 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4703 10:06:57.402615 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4704 10:06:57.409457 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4705 10:06:57.412524 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4706 10:06:57.415768 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4707 10:06:57.418987 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4708 10:06:57.425958 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4709 10:06:57.429396 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4710 10:06:57.432435 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4711 10:06:57.435962 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4712 10:06:57.442322 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4713 10:06:57.445441 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4714 10:06:57.449066 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4715 10:06:57.452453 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4716 10:06:57.452563 ==
4717 10:06:57.455637 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 10:06:57.462214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 10:06:57.462299 ==
4720 10:06:57.462367 DQS Delay:
4721 10:06:57.465281 DQS0 = 0, DQS1 = 0
4722 10:06:57.465366 DQM Delay:
4723 10:06:57.465434 DQM0 = 51, DQM1 = 46
4724 10:06:57.468848 DQ Delay:
4725 10:06:57.472340 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4726 10:06:57.475418 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4727 10:06:57.478993 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4728 10:06:57.482160 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4729 10:06:57.482244
4730 10:06:57.482310
4731 10:06:57.482372 ==
4732 10:06:57.485586 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 10:06:57.488481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 10:06:57.488591 ==
4735 10:06:57.488686
4736 10:06:57.488797
4737 10:06:57.492020 TX Vref Scan disable
4738 10:06:57.495013 == TX Byte 0 ==
4739 10:06:57.498509 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4740 10:06:57.502250 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4741 10:06:57.505384 == TX Byte 1 ==
4742 10:06:57.508582 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4743 10:06:57.511769 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4744 10:06:57.511854 ==
4745 10:06:57.515117 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 10:06:57.518481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 10:06:57.518569 ==
4748 10:06:57.521995
4749 10:06:57.522091
4750 10:06:57.522165 TX Vref Scan disable
4751 10:06:57.525356 == TX Byte 0 ==
4752 10:06:57.528784 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4753 10:06:57.535334 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4754 10:06:57.535446 == TX Byte 1 ==
4755 10:06:57.538734 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4756 10:06:57.545071 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4757 10:06:57.545175
4758 10:06:57.545244 [DATLAT]
4759 10:06:57.545308 Freq=600, CH1 RK1
4760 10:06:57.545394
4761 10:06:57.548706 DATLAT Default: 0x9
4762 10:06:57.551892 0, 0xFFFF, sum = 0
4763 10:06:57.551980 1, 0xFFFF, sum = 0
4764 10:06:57.555155 2, 0xFFFF, sum = 0
4765 10:06:57.555270 3, 0xFFFF, sum = 0
4766 10:06:57.558146 4, 0xFFFF, sum = 0
4767 10:06:57.558233 5, 0xFFFF, sum = 0
4768 10:06:57.561843 6, 0xFFFF, sum = 0
4769 10:06:57.561931 7, 0xFFFF, sum = 0
4770 10:06:57.564834 8, 0x0, sum = 1
4771 10:06:57.564922 9, 0x0, sum = 2
4772 10:06:57.567940 10, 0x0, sum = 3
4773 10:06:57.568054 11, 0x0, sum = 4
4774 10:06:57.568155 best_step = 9
4775 10:06:57.568224
4776 10:06:57.571521 ==
4777 10:06:57.574713 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 10:06:57.578343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 10:06:57.578421 ==
4780 10:06:57.578487 RX Vref Scan: 0
4781 10:06:57.578549
4782 10:06:57.581570 RX Vref 0 -> 0, step: 1
4783 10:06:57.581656
4784 10:06:57.584996 RX Delay -163 -> 252, step: 8
4785 10:06:57.591104 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4786 10:06:57.594588 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4787 10:06:57.597955 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4788 10:06:57.601429 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4789 10:06:57.604528 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4790 10:06:57.611070 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4791 10:06:57.614488 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4792 10:06:57.617811 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4793 10:06:57.620860 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4794 10:06:57.624266 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4795 10:06:57.630832 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4796 10:06:57.634356 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4797 10:06:57.637803 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4798 10:06:57.640869 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4799 10:06:57.647515 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4800 10:06:57.650773 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4801 10:06:57.650856 ==
4802 10:06:57.653887 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 10:06:57.657454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 10:06:57.657537 ==
4805 10:06:57.657603 DQS Delay:
4806 10:06:57.660933 DQS0 = 0, DQS1 = 0
4807 10:06:57.661016 DQM Delay:
4808 10:06:57.663994 DQM0 = 49, DQM1 = 43
4809 10:06:57.664075 DQ Delay:
4810 10:06:57.667344 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =48
4811 10:06:57.670579 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4812 10:06:57.673692 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4813 10:06:57.677332 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4814 10:06:57.677415
4815 10:06:57.677484
4816 10:06:57.687279 [DQSOSCAuto] RK1, (LSB)MR18= 0x591f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4817 10:06:57.687367 CH1 RK1: MR19=808, MR18=591F
4818 10:06:57.694124 CH1_RK1: MR19=0x808, MR18=0x591F, DQSOSC=393, MR23=63, INC=169, DEC=113
4819 10:06:57.697213 [RxdqsGatingPostProcess] freq 600
4820 10:06:57.703807 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4821 10:06:57.707449 Pre-setting of DQS Precalculation
4822 10:06:57.710526 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4823 10:06:57.717152 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4824 10:06:57.726934 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4825 10:06:57.727044
4826 10:06:57.727151
4827 10:06:57.730503 [Calibration Summary] 1200 Mbps
4828 10:06:57.730586 CH 0, Rank 0
4829 10:06:57.733503 SW Impedance : PASS
4830 10:06:57.733586 DUTY Scan : NO K
4831 10:06:57.736706 ZQ Calibration : PASS
4832 10:06:57.736827 Jitter Meter : NO K
4833 10:06:57.740347 CBT Training : PASS
4834 10:06:57.743415 Write leveling : PASS
4835 10:06:57.743498 RX DQS gating : PASS
4836 10:06:57.747113 RX DQ/DQS(RDDQC) : PASS
4837 10:06:57.750206 TX DQ/DQS : PASS
4838 10:06:57.750289 RX DATLAT : PASS
4839 10:06:57.753402 RX DQ/DQS(Engine): PASS
4840 10:06:57.756502 TX OE : NO K
4841 10:06:57.756611 All Pass.
4842 10:06:57.756719
4843 10:06:57.756820 CH 0, Rank 1
4844 10:06:57.760074 SW Impedance : PASS
4845 10:06:57.763349 DUTY Scan : NO K
4846 10:06:57.763431 ZQ Calibration : PASS
4847 10:06:57.766727 Jitter Meter : NO K
4848 10:06:57.769844 CBT Training : PASS
4849 10:06:57.769926 Write leveling : PASS
4850 10:06:57.773395 RX DQS gating : PASS
4851 10:06:57.776583 RX DQ/DQS(RDDQC) : PASS
4852 10:06:57.776693 TX DQ/DQS : PASS
4853 10:06:57.779655 RX DATLAT : PASS
4854 10:06:57.782916 RX DQ/DQS(Engine): PASS
4855 10:06:57.782998 TX OE : NO K
4856 10:06:57.786534 All Pass.
4857 10:06:57.786617
4858 10:06:57.786682 CH 1, Rank 0
4859 10:06:57.789555 SW Impedance : PASS
4860 10:06:57.789669 DUTY Scan : NO K
4861 10:06:57.792661 ZQ Calibration : PASS
4862 10:06:57.796308 Jitter Meter : NO K
4863 10:06:57.796390 CBT Training : PASS
4864 10:06:57.799706 Write leveling : PASS
4865 10:06:57.802931 RX DQS gating : PASS
4866 10:06:57.803014 RX DQ/DQS(RDDQC) : PASS
4867 10:06:57.806168 TX DQ/DQS : PASS
4868 10:06:57.809168 RX DATLAT : PASS
4869 10:06:57.809251 RX DQ/DQS(Engine): PASS
4870 10:06:57.812720 TX OE : NO K
4871 10:06:57.812858 All Pass.
4872 10:06:57.812942
4873 10:06:57.816043 CH 1, Rank 1
4874 10:06:57.816138 SW Impedance : PASS
4875 10:06:57.819159 DUTY Scan : NO K
4876 10:06:57.819244 ZQ Calibration : PASS
4877 10:06:57.822349 Jitter Meter : NO K
4878 10:06:57.825649 CBT Training : PASS
4879 10:06:57.825733 Write leveling : PASS
4880 10:06:57.829036 RX DQS gating : PASS
4881 10:06:57.832310 RX DQ/DQS(RDDQC) : PASS
4882 10:06:57.832421 TX DQ/DQS : PASS
4883 10:06:57.835861 RX DATLAT : PASS
4884 10:06:57.838811 RX DQ/DQS(Engine): PASS
4885 10:06:57.838929 TX OE : NO K
4886 10:06:57.842185 All Pass.
4887 10:06:57.842270
4888 10:06:57.842336 DramC Write-DBI off
4889 10:06:57.845405 PER_BANK_REFRESH: Hybrid Mode
4890 10:06:57.848647 TX_TRACKING: ON
4891 10:06:57.855221 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4892 10:06:57.858757 [FAST_K] Save calibration result to emmc
4893 10:06:57.861845 dramc_set_vcore_voltage set vcore to 662500
4894 10:06:57.865615 Read voltage for 933, 3
4895 10:06:57.865699 Vio18 = 0
4896 10:06:57.868597 Vcore = 662500
4897 10:06:57.868681 Vdram = 0
4898 10:06:57.868748 Vddq = 0
4899 10:06:57.872040 Vmddr = 0
4900 10:06:57.875229 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4901 10:06:57.881833 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4902 10:06:57.881920 MEM_TYPE=3, freq_sel=17
4903 10:06:57.885360 sv_algorithm_assistance_LP4_1600
4904 10:06:57.891643 ============ PULL DRAM RESETB DOWN ============
4905 10:06:57.895243 ========== PULL DRAM RESETB DOWN end =========
4906 10:06:57.898224 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4907 10:06:57.901637 ===================================
4908 10:06:57.905052 LPDDR4 DRAM CONFIGURATION
4909 10:06:57.908119 ===================================
4910 10:06:57.911556 EX_ROW_EN[0] = 0x0
4911 10:06:57.911641 EX_ROW_EN[1] = 0x0
4912 10:06:57.914587 LP4Y_EN = 0x0
4913 10:06:57.914671 WORK_FSP = 0x0
4914 10:06:57.918300 WL = 0x3
4915 10:06:57.918383 RL = 0x3
4916 10:06:57.921439 BL = 0x2
4917 10:06:57.921522 RPST = 0x0
4918 10:06:57.924613 RD_PRE = 0x0
4919 10:06:57.924696 WR_PRE = 0x1
4920 10:06:57.927857 WR_PST = 0x0
4921 10:06:57.928097 DBI_WR = 0x0
4922 10:06:57.931236 DBI_RD = 0x0
4923 10:06:57.934354 OTF = 0x1
4924 10:06:57.937754 ===================================
4925 10:06:57.941211 ===================================
4926 10:06:57.941313 ANA top config
4927 10:06:57.944595 ===================================
4928 10:06:57.947924 DLL_ASYNC_EN = 0
4929 10:06:57.948035 ALL_SLAVE_EN = 1
4930 10:06:57.951078 NEW_RANK_MODE = 1
4931 10:06:57.954398 DLL_IDLE_MODE = 1
4932 10:06:57.957434 LP45_APHY_COMB_EN = 1
4933 10:06:57.960963 TX_ODT_DIS = 1
4934 10:06:57.961096 NEW_8X_MODE = 1
4935 10:06:57.964135 ===================================
4936 10:06:57.967774 ===================================
4937 10:06:57.970816 data_rate = 1866
4938 10:06:57.974303 CKR = 1
4939 10:06:57.977455 DQ_P2S_RATIO = 8
4940 10:06:57.980592 ===================================
4941 10:06:57.984190 CA_P2S_RATIO = 8
4942 10:06:57.987355 DQ_CA_OPEN = 0
4943 10:06:57.987474 DQ_SEMI_OPEN = 0
4944 10:06:57.990822 CA_SEMI_OPEN = 0
4945 10:06:57.993817 CA_FULL_RATE = 0
4946 10:06:57.997500 DQ_CKDIV4_EN = 1
4947 10:06:58.000404 CA_CKDIV4_EN = 1
4948 10:06:58.003970 CA_PREDIV_EN = 0
4949 10:06:58.004083 PH8_DLY = 0
4950 10:06:58.007248 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4951 10:06:58.010354 DQ_AAMCK_DIV = 4
4952 10:06:58.013746 CA_AAMCK_DIV = 4
4953 10:06:58.017144 CA_ADMCK_DIV = 4
4954 10:06:58.020640 DQ_TRACK_CA_EN = 0
4955 10:06:58.020753 CA_PICK = 933
4956 10:06:58.023840 CA_MCKIO = 933
4957 10:06:58.026896 MCKIO_SEMI = 0
4958 10:06:58.030504 PLL_FREQ = 3732
4959 10:06:58.033417 DQ_UI_PI_RATIO = 32
4960 10:06:58.036932 CA_UI_PI_RATIO = 0
4961 10:06:58.039945 ===================================
4962 10:06:58.043549 ===================================
4963 10:06:58.046701 memory_type:LPDDR4
4964 10:06:58.046816 GP_NUM : 10
4965 10:06:58.050185 SRAM_EN : 1
4966 10:06:58.050310 MD32_EN : 0
4967 10:06:58.053449 ===================================
4968 10:06:58.056704 [ANA_INIT] >>>>>>>>>>>>>>
4969 10:06:58.059818 <<<<<< [CONFIGURE PHASE]: ANA_TX
4970 10:06:58.063133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4971 10:06:58.066622 ===================================
4972 10:06:58.069815 data_rate = 1866,PCW = 0X8f00
4973 10:06:58.073020 ===================================
4974 10:06:58.076575 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4975 10:06:58.082950 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4976 10:06:58.086601 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4977 10:06:58.092688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4978 10:06:58.096184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4979 10:06:58.099577 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4980 10:06:58.099695 [ANA_INIT] flow start
4981 10:06:58.102709 [ANA_INIT] PLL >>>>>>>>
4982 10:06:58.106150 [ANA_INIT] PLL <<<<<<<<
4983 10:06:58.106263 [ANA_INIT] MIDPI >>>>>>>>
4984 10:06:58.109411 [ANA_INIT] MIDPI <<<<<<<<
4985 10:06:58.113029 [ANA_INIT] DLL >>>>>>>>
4986 10:06:58.113141 [ANA_INIT] flow end
4987 10:06:58.119363 ============ LP4 DIFF to SE enter ============
4988 10:06:58.122704 ============ LP4 DIFF to SE exit ============
4989 10:06:58.125695 [ANA_INIT] <<<<<<<<<<<<<
4990 10:06:58.129237 [Flow] Enable top DCM control >>>>>
4991 10:06:58.132330 [Flow] Enable top DCM control <<<<<
4992 10:06:58.135497 Enable DLL master slave shuffle
4993 10:06:58.138954 ==============================================================
4994 10:06:58.142550 Gating Mode config
4995 10:06:58.145627 ==============================================================
4996 10:06:58.148712 Config description:
4997 10:06:58.158987 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4998 10:06:58.165515 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4999 10:06:58.168652 SELPH_MODE 0: By rank 1: By Phase
5000 10:06:58.175284 ==============================================================
5001 10:06:58.178884 GAT_TRACK_EN = 1
5002 10:06:58.182004 RX_GATING_MODE = 2
5003 10:06:58.185399 RX_GATING_TRACK_MODE = 2
5004 10:06:58.188470 SELPH_MODE = 1
5005 10:06:58.192262 PICG_EARLY_EN = 1
5006 10:06:58.195429 VALID_LAT_VALUE = 1
5007 10:06:58.198538 ==============================================================
5008 10:06:58.201926 Enter into Gating configuration >>>>
5009 10:06:58.205464 Exit from Gating configuration <<<<
5010 10:06:58.208418 Enter into DVFS_PRE_config >>>>>
5011 10:06:58.218699 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5012 10:06:58.221797 Exit from DVFS_PRE_config <<<<<
5013 10:06:58.225113 Enter into PICG configuration >>>>
5014 10:06:58.228415 Exit from PICG configuration <<<<
5015 10:06:58.231932 [RX_INPUT] configuration >>>>>
5016 10:06:58.235079 [RX_INPUT] configuration <<<<<
5017 10:06:58.241573 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5018 10:06:58.244682 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5019 10:06:58.251545 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5020 10:06:58.257970 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5021 10:06:58.264656 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5022 10:06:58.271151 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5023 10:06:58.274614 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5024 10:06:58.278136 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5025 10:06:58.281250 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5026 10:06:58.287831 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5027 10:06:58.291207 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5028 10:06:58.294330 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5029 10:06:58.297985 ===================================
5030 10:06:58.300949 LPDDR4 DRAM CONFIGURATION
5031 10:06:58.304370 ===================================
5032 10:06:58.307517 EX_ROW_EN[0] = 0x0
5033 10:06:58.307601 EX_ROW_EN[1] = 0x0
5034 10:06:58.311003 LP4Y_EN = 0x0
5035 10:06:58.311088 WORK_FSP = 0x0
5036 10:06:58.313975 WL = 0x3
5037 10:06:58.314059 RL = 0x3
5038 10:06:58.317509 BL = 0x2
5039 10:06:58.317595 RPST = 0x0
5040 10:06:58.320715 RD_PRE = 0x0
5041 10:06:58.320806 WR_PRE = 0x1
5042 10:06:58.323870 WR_PST = 0x0
5043 10:06:58.323956 DBI_WR = 0x0
5044 10:06:58.327334 DBI_RD = 0x0
5045 10:06:58.327431 OTF = 0x1
5046 10:06:58.330451 ===================================
5047 10:06:58.337118 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5048 10:06:58.340647 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5049 10:06:58.343739 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5050 10:06:58.347363 ===================================
5051 10:06:58.350509 LPDDR4 DRAM CONFIGURATION
5052 10:06:58.353722 ===================================
5053 10:06:58.357141 EX_ROW_EN[0] = 0x10
5054 10:06:58.357261 EX_ROW_EN[1] = 0x0
5055 10:06:58.360336 LP4Y_EN = 0x0
5056 10:06:58.360422 WORK_FSP = 0x0
5057 10:06:58.363586 WL = 0x3
5058 10:06:58.363691 RL = 0x3
5059 10:06:58.366971 BL = 0x2
5060 10:06:58.367073 RPST = 0x0
5061 10:06:58.370380 RD_PRE = 0x0
5062 10:06:58.370485 WR_PRE = 0x1
5063 10:06:58.373453 WR_PST = 0x0
5064 10:06:58.373532 DBI_WR = 0x0
5065 10:06:58.376670 DBI_RD = 0x0
5066 10:06:58.376776 OTF = 0x1
5067 10:06:58.380247 ===================================
5068 10:06:58.386731 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5069 10:06:58.391642 nWR fixed to 30
5070 10:06:58.394813 [ModeRegInit_LP4] CH0 RK0
5071 10:06:58.394925 [ModeRegInit_LP4] CH0 RK1
5072 10:06:58.398049 [ModeRegInit_LP4] CH1 RK0
5073 10:06:58.401304 [ModeRegInit_LP4] CH1 RK1
5074 10:06:58.401389 match AC timing 9
5075 10:06:58.407845 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5076 10:06:58.411599 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5077 10:06:58.414872 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5078 10:06:58.421465 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5079 10:06:58.424367 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5080 10:06:58.424453 ==
5081 10:06:58.427822 Dram Type= 6, Freq= 0, CH_0, rank 0
5082 10:06:58.431350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5083 10:06:58.431449 ==
5084 10:06:58.437870 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5085 10:06:58.444549 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5086 10:06:58.447626 [CA 0] Center 37 (7~68) winsize 62
5087 10:06:58.450626 [CA 1] Center 37 (7~68) winsize 62
5088 10:06:58.454269 [CA 2] Center 35 (5~65) winsize 61
5089 10:06:58.457475 [CA 3] Center 34 (4~65) winsize 62
5090 10:06:58.460988 [CA 4] Center 34 (4~64) winsize 61
5091 10:06:58.463970 [CA 5] Center 33 (3~64) winsize 62
5092 10:06:58.464080
5093 10:06:58.467300 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5094 10:06:58.467410
5095 10:06:58.470427 [CATrainingPosCal] consider 1 rank data
5096 10:06:58.474051 u2DelayCellTimex100 = 270/100 ps
5097 10:06:58.477319 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5098 10:06:58.480415 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5099 10:06:58.483650 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5100 10:06:58.490416 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5101 10:06:58.493785 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5102 10:06:58.497050 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5103 10:06:58.497145
5104 10:06:58.500548 CA PerBit enable=1, Macro0, CA PI delay=33
5105 10:06:58.500669
5106 10:06:58.503596 [CBTSetCACLKResult] CA Dly = 33
5107 10:06:58.503699 CS Dly: 6 (0~37)
5108 10:06:58.503767 ==
5109 10:06:58.506822 Dram Type= 6, Freq= 0, CH_0, rank 1
5110 10:06:58.513428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 10:06:58.513522 ==
5112 10:06:58.516629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5113 10:06:58.523516 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5114 10:06:58.526725 [CA 0] Center 38 (7~69) winsize 63
5115 10:06:58.529794 [CA 1] Center 38 (8~68) winsize 61
5116 10:06:58.533465 [CA 2] Center 35 (5~66) winsize 62
5117 10:06:58.536761 [CA 3] Center 35 (5~66) winsize 62
5118 10:06:58.539813 [CA 4] Center 34 (4~65) winsize 62
5119 10:06:58.543422 [CA 5] Center 34 (4~64) winsize 61
5120 10:06:58.543507
5121 10:06:58.546575 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5122 10:06:58.546681
5123 10:06:58.550092 [CATrainingPosCal] consider 2 rank data
5124 10:06:58.553119 u2DelayCellTimex100 = 270/100 ps
5125 10:06:58.556559 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5126 10:06:58.559747 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5127 10:06:58.566380 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5128 10:06:58.569640 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5129 10:06:58.572972 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5130 10:06:58.576386 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5131 10:06:58.576497
5132 10:06:58.579725 CA PerBit enable=1, Macro0, CA PI delay=34
5133 10:06:58.579828
5134 10:06:58.583015 [CBTSetCACLKResult] CA Dly = 34
5135 10:06:58.583090 CS Dly: 7 (0~39)
5136 10:06:58.586350
5137 10:06:58.589545 ----->DramcWriteLeveling(PI) begin...
5138 10:06:58.589631 ==
5139 10:06:58.592684 Dram Type= 6, Freq= 0, CH_0, rank 0
5140 10:06:58.596111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5141 10:06:58.596222 ==
5142 10:06:58.599742 Write leveling (Byte 0): 33 => 33
5143 10:06:58.602709 Write leveling (Byte 1): 29 => 29
5144 10:06:58.605826 DramcWriteLeveling(PI) end<-----
5145 10:06:58.605936
5146 10:06:58.606032 ==
5147 10:06:58.609231 Dram Type= 6, Freq= 0, CH_0, rank 0
5148 10:06:58.612860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5149 10:06:58.612946 ==
5150 10:06:58.615943 [Gating] SW mode calibration
5151 10:06:58.622367 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5152 10:06:58.629158 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5153 10:06:58.632642 0 14 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5154 10:06:58.635952 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 10:06:58.642300 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 10:06:58.645893 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 10:06:58.648920 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 10:06:58.655649 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 10:06:58.659132 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5160 10:06:58.662209 0 14 28 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
5161 10:06:58.668775 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5162 10:06:58.672356 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 10:06:58.675461 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 10:06:58.682213 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 10:06:58.685437 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 10:06:58.688702 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 10:06:58.695556 0 15 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5168 10:06:58.698581 0 15 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
5169 10:06:58.702227 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
5170 10:06:58.708584 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 10:06:58.712182 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 10:06:58.715293 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 10:06:58.721847 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 10:06:58.725332 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 10:06:58.728834 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 10:06:58.735010 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5177 10:06:58.738572 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5178 10:06:58.741660 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 10:06:58.748096 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 10:06:58.751639 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 10:06:58.754783 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 10:06:58.761511 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 10:06:58.764628 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 10:06:58.768044 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 10:06:58.774749 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 10:06:58.778242 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 10:06:58.781170 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 10:06:58.788013 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 10:06:58.791461 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 10:06:58.794403 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 10:06:58.801183 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5192 10:06:58.804277 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5193 10:06:58.807533 Total UI for P1: 0, mck2ui 16
5194 10:06:58.810781 best dqsien dly found for B0: ( 1, 2, 24)
5195 10:06:58.814557 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5196 10:06:58.820953 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 10:06:58.821047 Total UI for P1: 0, mck2ui 16
5198 10:06:58.824034 best dqsien dly found for B1: ( 1, 3, 0)
5199 10:06:58.830572 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5200 10:06:58.833983 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5201 10:06:58.834070
5202 10:06:58.837328 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5203 10:06:58.840775 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5204 10:06:58.843638 [Gating] SW calibration Done
5205 10:06:58.843726 ==
5206 10:06:58.847236 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 10:06:58.850585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 10:06:58.850670 ==
5209 10:06:58.853840 RX Vref Scan: 0
5210 10:06:58.853925
5211 10:06:58.853991 RX Vref 0 -> 0, step: 1
5212 10:06:58.854054
5213 10:06:58.857107 RX Delay -80 -> 252, step: 8
5214 10:06:58.860530 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5215 10:06:58.867148 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5216 10:06:58.870148 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5217 10:06:58.873611 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5218 10:06:58.877226 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5219 10:06:58.880104 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5220 10:06:58.887165 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5221 10:06:58.890300 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5222 10:06:58.893478 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5223 10:06:58.896689 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5224 10:06:58.900226 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5225 10:06:58.903360 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5226 10:06:58.909953 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5227 10:06:58.913203 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5228 10:06:58.916854 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5229 10:06:58.919871 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5230 10:06:58.919975 ==
5231 10:06:58.923136 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 10:06:58.929829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 10:06:58.929916 ==
5234 10:06:58.929985 DQS Delay:
5235 10:06:58.930047 DQS0 = 0, DQS1 = 0
5236 10:06:58.933262 DQM Delay:
5237 10:06:58.933348 DQM0 = 106, DQM1 = 91
5238 10:06:58.936242 DQ Delay:
5239 10:06:58.939852 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5240 10:06:58.943357 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5241 10:06:58.946212 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5242 10:06:58.949721 DQ12 =91, DQ13 =91, DQ14 =103, DQ15 =103
5243 10:06:58.949805
5244 10:06:58.949871
5245 10:06:58.949932 ==
5246 10:06:58.952877 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 10:06:58.956396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 10:06:58.956481 ==
5249 10:06:58.956548
5250 10:06:58.956610
5251 10:06:58.959449 TX Vref Scan disable
5252 10:06:58.962944 == TX Byte 0 ==
5253 10:06:58.966255 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5254 10:06:58.969277 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5255 10:06:58.972628 == TX Byte 1 ==
5256 10:06:58.975849 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5257 10:06:58.979367 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5258 10:06:58.979451 ==
5259 10:06:58.982474 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 10:06:58.989340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 10:06:58.989425 ==
5262 10:06:58.989493
5263 10:06:58.989555
5264 10:06:58.989614 TX Vref Scan disable
5265 10:06:58.993430 == TX Byte 0 ==
5266 10:06:58.996398 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5267 10:06:59.003404 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5268 10:06:59.003488 == TX Byte 1 ==
5269 10:06:59.006630 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5270 10:06:59.013128 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5271 10:06:59.013213
5272 10:06:59.013279 [DATLAT]
5273 10:06:59.013342 Freq=933, CH0 RK0
5274 10:06:59.013402
5275 10:06:59.016365 DATLAT Default: 0xd
5276 10:06:59.016480 0, 0xFFFF, sum = 0
5277 10:06:59.020106 1, 0xFFFF, sum = 0
5278 10:06:59.023077 2, 0xFFFF, sum = 0
5279 10:06:59.023190 3, 0xFFFF, sum = 0
5280 10:06:59.026769 4, 0xFFFF, sum = 0
5281 10:06:59.026872 5, 0xFFFF, sum = 0
5282 10:06:59.030029 6, 0xFFFF, sum = 0
5283 10:06:59.030114 7, 0xFFFF, sum = 0
5284 10:06:59.033035 8, 0xFFFF, sum = 0
5285 10:06:59.033146 9, 0xFFFF, sum = 0
5286 10:06:59.036315 10, 0x0, sum = 1
5287 10:06:59.036394 11, 0x0, sum = 2
5288 10:06:59.039837 12, 0x0, sum = 3
5289 10:06:59.039913 13, 0x0, sum = 4
5290 10:06:59.039978 best_step = 11
5291 10:06:59.040038
5292 10:06:59.042807 ==
5293 10:06:59.046023 Dram Type= 6, Freq= 0, CH_0, rank 0
5294 10:06:59.049345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 10:06:59.049417 ==
5296 10:06:59.049494 RX Vref Scan: 1
5297 10:06:59.049555
5298 10:06:59.052921 RX Vref 0 -> 0, step: 1
5299 10:06:59.053019
5300 10:06:59.055829 RX Delay -53 -> 252, step: 4
5301 10:06:59.055911
5302 10:06:59.059189 Set Vref, RX VrefLevel [Byte0]: 59
5303 10:06:59.062735 [Byte1]: 49
5304 10:06:59.065864
5305 10:06:59.065946 Final RX Vref Byte 0 = 59 to rank0
5306 10:06:59.069046 Final RX Vref Byte 1 = 49 to rank0
5307 10:06:59.072790 Final RX Vref Byte 0 = 59 to rank1
5308 10:06:59.076015 Final RX Vref Byte 1 = 49 to rank1==
5309 10:06:59.079120 Dram Type= 6, Freq= 0, CH_0, rank 0
5310 10:06:59.085852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 10:06:59.085936 ==
5312 10:06:59.086002 DQS Delay:
5313 10:06:59.086063 DQS0 = 0, DQS1 = 0
5314 10:06:59.088961 DQM Delay:
5315 10:06:59.089044 DQM0 = 108, DQM1 = 92
5316 10:06:59.092399 DQ Delay:
5317 10:06:59.095708 DQ0 =108, DQ1 =108, DQ2 =106, DQ3 =106
5318 10:06:59.099270 DQ4 =108, DQ5 =100, DQ6 =116, DQ7 =116
5319 10:06:59.102051 DQ8 =86, DQ9 =78, DQ10 =92, DQ11 =90
5320 10:06:59.105703 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =100
5321 10:06:59.105779
5322 10:06:59.105844
5323 10:06:59.111855 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
5324 10:06:59.115412 CH0 RK0: MR19=505, MR18=2622
5325 10:06:59.121925 CH0_RK0: MR19=0x505, MR18=0x2622, DQSOSC=409, MR23=63, INC=64, DEC=43
5326 10:06:59.122022
5327 10:06:59.125056 ----->DramcWriteLeveling(PI) begin...
5328 10:06:59.125153 ==
5329 10:06:59.128626 Dram Type= 6, Freq= 0, CH_0, rank 1
5330 10:06:59.134962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5331 10:06:59.135046 ==
5332 10:06:59.138191 Write leveling (Byte 0): 34 => 34
5333 10:06:59.138277 Write leveling (Byte 1): 27 => 27
5334 10:06:59.141785 DramcWriteLeveling(PI) end<-----
5335 10:06:59.141927
5336 10:06:59.142008 ==
5337 10:06:59.144701 Dram Type= 6, Freq= 0, CH_0, rank 1
5338 10:06:59.151294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 10:06:59.151378 ==
5340 10:06:59.154702 [Gating] SW mode calibration
5341 10:06:59.161581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5342 10:06:59.164537 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5343 10:06:59.171731 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 10:06:59.174844 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 10:06:59.177938 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 10:06:59.184646 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 10:06:59.187763 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 10:06:59.191204 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 10:06:59.197532 0 14 24 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 0)
5350 10:06:59.200845 0 14 28 | B1->B0 | 2e2e 2626 | 0 0 | (1 1) (0 0)
5351 10:06:59.204292 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 10:06:59.210815 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 10:06:59.214284 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 10:06:59.217573 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 10:06:59.224277 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 10:06:59.227730 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 10:06:59.230754 0 15 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5358 10:06:59.237305 0 15 28 | B1->B0 | 3c3c 3c3c | 0 1 | (0 0) (0 0)
5359 10:06:59.240685 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 10:06:59.244112 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 10:06:59.250917 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 10:06:59.253954 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 10:06:59.257429 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 10:06:59.263922 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 10:06:59.267428 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5366 10:06:59.270529 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5367 10:06:59.277253 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 10:06:59.280403 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 10:06:59.283561 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 10:06:59.290165 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 10:06:59.293740 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 10:06:59.296777 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 10:06:59.303496 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 10:06:59.307104 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 10:06:59.310209 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 10:06:59.316589 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 10:06:59.320112 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 10:06:59.323476 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 10:06:59.329686 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 10:06:59.333480 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 10:06:59.336340 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5382 10:06:59.343288 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5383 10:06:59.346331 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 10:06:59.349747 Total UI for P1: 0, mck2ui 16
5385 10:06:59.352851 best dqsien dly found for B0: ( 1, 2, 26)
5386 10:06:59.356409 Total UI for P1: 0, mck2ui 16
5387 10:06:59.359495 best dqsien dly found for B1: ( 1, 2, 26)
5388 10:06:59.362824 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5389 10:06:59.366368 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5390 10:06:59.366480
5391 10:06:59.369411 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5392 10:06:59.372799 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5393 10:06:59.375891 [Gating] SW calibration Done
5394 10:06:59.375978 ==
5395 10:06:59.379500 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 10:06:59.382671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 10:06:59.382762 ==
5398 10:06:59.386286 RX Vref Scan: 0
5399 10:06:59.386372
5400 10:06:59.389306 RX Vref 0 -> 0, step: 1
5401 10:06:59.389392
5402 10:06:59.389467 RX Delay -80 -> 252, step: 8
5403 10:06:59.396022 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5404 10:06:59.399471 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5405 10:06:59.402670 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5406 10:06:59.405882 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5407 10:06:59.409334 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5408 10:06:59.415922 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5409 10:06:59.418934 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5410 10:06:59.422722 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5411 10:06:59.425854 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5412 10:06:59.429149 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5413 10:06:59.432608 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5414 10:06:59.438738 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5415 10:06:59.442164 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5416 10:06:59.445764 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5417 10:06:59.448859 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5418 10:06:59.452561 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5419 10:06:59.452687 ==
5420 10:06:59.455419 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 10:06:59.462032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 10:06:59.462186 ==
5423 10:06:59.462299 DQS Delay:
5424 10:06:59.465413 DQS0 = 0, DQS1 = 0
5425 10:06:59.465542 DQM Delay:
5426 10:06:59.465744 DQM0 = 105, DQM1 = 90
5427 10:06:59.469049 DQ Delay:
5428 10:06:59.472039 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5429 10:06:59.475121 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5430 10:06:59.478718 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5431 10:06:59.482048 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5432 10:06:59.482141
5433 10:06:59.482237
5434 10:06:59.482327 ==
5435 10:06:59.485117 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 10:06:59.488247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 10:06:59.488372 ==
5438 10:06:59.488540
5439 10:06:59.491713
5440 10:06:59.491830 TX Vref Scan disable
5441 10:06:59.494921 == TX Byte 0 ==
5442 10:06:59.498538 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5443 10:06:59.501612 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5444 10:06:59.504713 == TX Byte 1 ==
5445 10:06:59.508034 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5446 10:06:59.511614 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5447 10:06:59.511700 ==
5448 10:06:59.514787 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 10:06:59.521565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 10:06:59.521684 ==
5451 10:06:59.521788
5452 10:06:59.521882
5453 10:06:59.521980 TX Vref Scan disable
5454 10:06:59.525752 == TX Byte 0 ==
5455 10:06:59.529181 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5456 10:06:59.535608 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5457 10:06:59.535720 == TX Byte 1 ==
5458 10:06:59.538876 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5459 10:06:59.545445 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5460 10:06:59.545555
5461 10:06:59.545657 [DATLAT]
5462 10:06:59.545749 Freq=933, CH0 RK1
5463 10:06:59.545839
5464 10:06:59.548732 DATLAT Default: 0xb
5465 10:06:59.548853 0, 0xFFFF, sum = 0
5466 10:06:59.552590 1, 0xFFFF, sum = 0
5467 10:06:59.555262 2, 0xFFFF, sum = 0
5468 10:06:59.555374 3, 0xFFFF, sum = 0
5469 10:06:59.558801 4, 0xFFFF, sum = 0
5470 10:06:59.558913 5, 0xFFFF, sum = 0
5471 10:06:59.562163 6, 0xFFFF, sum = 0
5472 10:06:59.562282 7, 0xFFFF, sum = 0
5473 10:06:59.565233 8, 0xFFFF, sum = 0
5474 10:06:59.565352 9, 0xFFFF, sum = 0
5475 10:06:59.568379 10, 0x0, sum = 1
5476 10:06:59.568485 11, 0x0, sum = 2
5477 10:06:59.571752 12, 0x0, sum = 3
5478 10:06:59.571853 13, 0x0, sum = 4
5479 10:06:59.575362 best_step = 11
5480 10:06:59.575449
5481 10:06:59.575515 ==
5482 10:06:59.578216 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 10:06:59.581665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 10:06:59.581753 ==
5485 10:06:59.581821 RX Vref Scan: 0
5486 10:06:59.584777
5487 10:06:59.584904 RX Vref 0 -> 0, step: 1
5488 10:06:59.584977
5489 10:06:59.587975 RX Delay -53 -> 252, step: 4
5490 10:06:59.594940 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5491 10:06:59.598027 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5492 10:06:59.601550 iDelay=199, Bit 2, Center 104 (19 ~ 190) 172
5493 10:06:59.604657 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5494 10:06:59.608154 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5495 10:06:59.614901 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5496 10:06:59.617852 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5497 10:06:59.621499 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5498 10:06:59.624595 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5499 10:06:59.627715 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5500 10:06:59.631033 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5501 10:06:59.637686 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5502 10:06:59.640995 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5503 10:06:59.644687 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5504 10:06:59.648041 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5505 10:06:59.650916 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5506 10:06:59.654233 ==
5507 10:06:59.657513 Dram Type= 6, Freq= 0, CH_0, rank 1
5508 10:06:59.660779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 10:06:59.660897 ==
5510 10:06:59.660962 DQS Delay:
5511 10:06:59.664276 DQS0 = 0, DQS1 = 0
5512 10:06:59.664359 DQM Delay:
5513 10:06:59.667938 DQM0 = 104, DQM1 = 93
5514 10:06:59.668021 DQ Delay:
5515 10:06:59.670949 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =98
5516 10:06:59.673926 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =112
5517 10:06:59.677384 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =90
5518 10:06:59.680980 DQ12 =96, DQ13 =96, DQ14 =104, DQ15 =98
5519 10:06:59.681063
5520 10:06:59.681129
5521 10:06:59.690580 [DQSOSCAuto] RK1, (LSB)MR18= 0x290a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5522 10:06:59.690665 CH0 RK1: MR19=505, MR18=290A
5523 10:06:59.697158 CH0_RK1: MR19=0x505, MR18=0x290A, DQSOSC=408, MR23=63, INC=65, DEC=43
5524 10:06:59.700697 [RxdqsGatingPostProcess] freq 933
5525 10:06:59.707072 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5526 10:06:59.710336 best DQS0 dly(2T, 0.5T) = (0, 10)
5527 10:06:59.713768 best DQS1 dly(2T, 0.5T) = (0, 11)
5528 10:06:59.717436 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5529 10:06:59.720414 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5530 10:06:59.723853 best DQS0 dly(2T, 0.5T) = (0, 10)
5531 10:06:59.723938 best DQS1 dly(2T, 0.5T) = (0, 10)
5532 10:06:59.727048 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5533 10:06:59.730245 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5534 10:06:59.733828 Pre-setting of DQS Precalculation
5535 10:06:59.740167 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5536 10:06:59.740252 ==
5537 10:06:59.743308 Dram Type= 6, Freq= 0, CH_1, rank 0
5538 10:06:59.746922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 10:06:59.747013 ==
5540 10:06:59.753555 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5541 10:06:59.759859 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5542 10:06:59.763296 [CA 0] Center 36 (6~67) winsize 62
5543 10:06:59.766366 [CA 1] Center 37 (7~68) winsize 62
5544 10:06:59.769648 [CA 2] Center 34 (4~65) winsize 62
5545 10:06:59.773297 [CA 3] Center 34 (4~64) winsize 61
5546 10:06:59.776292 [CA 4] Center 34 (4~65) winsize 62
5547 10:06:59.779576 [CA 5] Center 33 (3~64) winsize 62
5548 10:06:59.779661
5549 10:06:59.783061 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5550 10:06:59.783222
5551 10:06:59.786609 [CATrainingPosCal] consider 1 rank data
5552 10:06:59.789797 u2DelayCellTimex100 = 270/100 ps
5553 10:06:59.793039 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5554 10:06:59.796398 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5555 10:06:59.799569 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5556 10:06:59.803242 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5557 10:06:59.806388 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5558 10:06:59.809410 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5559 10:06:59.813019
5560 10:06:59.816262 CA PerBit enable=1, Macro0, CA PI delay=33
5561 10:06:59.816335
5562 10:06:59.819241 [CBTSetCACLKResult] CA Dly = 33
5563 10:06:59.819327 CS Dly: 5 (0~36)
5564 10:06:59.819396 ==
5565 10:06:59.822757 Dram Type= 6, Freq= 0, CH_1, rank 1
5566 10:06:59.825926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 10:06:59.829467 ==
5568 10:06:59.832598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5569 10:06:59.839312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5570 10:06:59.842516 [CA 0] Center 37 (7~68) winsize 62
5571 10:06:59.845740 [CA 1] Center 37 (7~68) winsize 62
5572 10:06:59.849034 [CA 2] Center 35 (5~66) winsize 62
5573 10:06:59.852464 [CA 3] Center 35 (5~65) winsize 61
5574 10:06:59.855653 [CA 4] Center 34 (4~65) winsize 62
5575 10:06:59.858850 [CA 5] Center 33 (3~64) winsize 62
5576 10:06:59.858937
5577 10:06:59.862375 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5578 10:06:59.862491
5579 10:06:59.865606 [CATrainingPosCal] consider 2 rank data
5580 10:06:59.868852 u2DelayCellTimex100 = 270/100 ps
5581 10:06:59.872815 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5582 10:06:59.875433 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5583 10:06:59.878888 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5584 10:06:59.885330 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5585 10:06:59.888793 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5586 10:06:59.892260 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5587 10:06:59.892334
5588 10:06:59.895392 CA PerBit enable=1, Macro0, CA PI delay=33
5589 10:06:59.895479
5590 10:06:59.898631 [CBTSetCACLKResult] CA Dly = 33
5591 10:06:59.898717 CS Dly: 6 (0~38)
5592 10:06:59.898787
5593 10:06:59.901786 ----->DramcWriteLeveling(PI) begin...
5594 10:06:59.901874 ==
5595 10:06:59.905269 Dram Type= 6, Freq= 0, CH_1, rank 0
5596 10:06:59.912033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5597 10:06:59.912128 ==
5598 10:06:59.915131 Write leveling (Byte 0): 24 => 24
5599 10:06:59.918773 Write leveling (Byte 1): 30 => 30
5600 10:06:59.921715 DramcWriteLeveling(PI) end<-----
5601 10:06:59.921838
5602 10:06:59.921963 ==
5603 10:06:59.924956 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 10:06:59.928540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 10:06:59.928639 ==
5606 10:06:59.931601 [Gating] SW mode calibration
5607 10:06:59.938649 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5608 10:06:59.941796 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5609 10:06:59.948499 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 10:06:59.951572 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 10:06:59.954873 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 10:06:59.961572 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 10:06:59.964779 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 10:06:59.971111 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5615 10:06:59.974437 0 14 24 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 0)
5616 10:06:59.978067 0 14 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5617 10:06:59.981378 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 10:06:59.987990 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 10:06:59.990902 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 10:06:59.994636 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 10:07:00.001350 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 10:07:00.004323 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 10:07:00.007607 0 15 24 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
5624 10:07:00.014260 0 15 28 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
5625 10:07:00.017449 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 10:07:00.021080 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 10:07:00.027416 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 10:07:00.030668 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 10:07:00.034266 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 10:07:00.040450 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 10:07:00.043987 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5632 10:07:00.047178 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 10:07:00.053824 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 10:07:00.057246 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 10:07:00.060307 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 10:07:00.067092 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 10:07:00.069979 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 10:07:00.073494 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 10:07:00.080219 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 10:07:00.083721 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 10:07:00.086966 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 10:07:00.093577 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 10:07:00.096799 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 10:07:00.100056 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 10:07:00.106672 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 10:07:00.110248 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5647 10:07:00.112995 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5648 10:07:00.119584 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 10:07:00.123222 Total UI for P1: 0, mck2ui 16
5650 10:07:00.126314 best dqsien dly found for B0: ( 1, 2, 22)
5651 10:07:00.129574 Total UI for P1: 0, mck2ui 16
5652 10:07:00.133046 best dqsien dly found for B1: ( 1, 2, 26)
5653 10:07:00.136406 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5654 10:07:00.139514 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5655 10:07:00.139598
5656 10:07:00.142978 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5657 10:07:00.146179 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5658 10:07:00.149622 [Gating] SW calibration Done
5659 10:07:00.149726 ==
5660 10:07:00.152960 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 10:07:00.155944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 10:07:00.156059 ==
5663 10:07:00.159633 RX Vref Scan: 0
5664 10:07:00.159718
5665 10:07:00.162797 RX Vref 0 -> 0, step: 1
5666 10:07:00.162882
5667 10:07:00.162948 RX Delay -80 -> 252, step: 8
5668 10:07:00.169352 iDelay=208, Bit 0, Center 111 (32 ~ 191) 160
5669 10:07:00.172402 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5670 10:07:00.176076 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5671 10:07:00.179005 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5672 10:07:00.182227 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5673 10:07:00.189013 iDelay=208, Bit 5, Center 115 (32 ~ 199) 168
5674 10:07:00.192242 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5675 10:07:00.195309 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5676 10:07:00.199157 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5677 10:07:00.202038 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5678 10:07:00.208627 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5679 10:07:00.212133 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5680 10:07:00.215711 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5681 10:07:00.218781 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5682 10:07:00.222268 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5683 10:07:00.228525 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5684 10:07:00.228679 ==
5685 10:07:00.231762 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 10:07:00.235413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 10:07:00.235565 ==
5688 10:07:00.235715 DQS Delay:
5689 10:07:00.238465 DQS0 = 0, DQS1 = 0
5690 10:07:00.238599 DQM Delay:
5691 10:07:00.241722 DQM0 = 106, DQM1 = 97
5692 10:07:00.241874 DQ Delay:
5693 10:07:00.245189 DQ0 =111, DQ1 =99, DQ2 =95, DQ3 =103
5694 10:07:00.248311 DQ4 =103, DQ5 =115, DQ6 =119, DQ7 =103
5695 10:07:00.251866 DQ8 =83, DQ9 =83, DQ10 =103, DQ11 =91
5696 10:07:00.255077 DQ12 =107, DQ13 =103, DQ14 =107, DQ15 =99
5697 10:07:00.255163
5698 10:07:00.255229
5699 10:07:00.255291 ==
5700 10:07:00.258547 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 10:07:00.265204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 10:07:00.265288 ==
5703 10:07:00.265354
5704 10:07:00.265415
5705 10:07:00.265474 TX Vref Scan disable
5706 10:07:00.268627 == TX Byte 0 ==
5707 10:07:00.272264 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5708 10:07:00.278608 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5709 10:07:00.278693 == TX Byte 1 ==
5710 10:07:00.281734 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5711 10:07:00.288992 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5712 10:07:00.289078 ==
5713 10:07:00.291832 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 10:07:00.295242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 10:07:00.295327 ==
5716 10:07:00.295394
5717 10:07:00.295455
5718 10:07:00.298478 TX Vref Scan disable
5719 10:07:00.298562 == TX Byte 0 ==
5720 10:07:00.305048 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5721 10:07:00.308192 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5722 10:07:00.311850 == TX Byte 1 ==
5723 10:07:00.314770 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5724 10:07:00.318230 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5725 10:07:00.318360
5726 10:07:00.318460 [DATLAT]
5727 10:07:00.321323 Freq=933, CH1 RK0
5728 10:07:00.321432
5729 10:07:00.324793 DATLAT Default: 0xd
5730 10:07:00.324892 0, 0xFFFF, sum = 0
5731 10:07:00.328080 1, 0xFFFF, sum = 0
5732 10:07:00.328166 2, 0xFFFF, sum = 0
5733 10:07:00.331489 3, 0xFFFF, sum = 0
5734 10:07:00.331574 4, 0xFFFF, sum = 0
5735 10:07:00.334519 5, 0xFFFF, sum = 0
5736 10:07:00.334641 6, 0xFFFF, sum = 0
5737 10:07:00.337683 7, 0xFFFF, sum = 0
5738 10:07:00.337813 8, 0xFFFF, sum = 0
5739 10:07:00.341273 9, 0xFFFF, sum = 0
5740 10:07:00.341364 10, 0x0, sum = 1
5741 10:07:00.344275 11, 0x0, sum = 2
5742 10:07:00.344349 12, 0x0, sum = 3
5743 10:07:00.347731 13, 0x0, sum = 4
5744 10:07:00.347844 best_step = 11
5745 10:07:00.347939
5746 10:07:00.348029 ==
5747 10:07:00.350978 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 10:07:00.354488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 10:07:00.357441 ==
5750 10:07:00.357530 RX Vref Scan: 1
5751 10:07:00.357610
5752 10:07:00.360911 RX Vref 0 -> 0, step: 1
5753 10:07:00.361033
5754 10:07:00.364081 RX Delay -53 -> 252, step: 4
5755 10:07:00.364190
5756 10:07:00.367731 Set Vref, RX VrefLevel [Byte0]: 50
5757 10:07:00.367816 [Byte1]: 50
5758 10:07:00.372938
5759 10:07:00.373037 Final RX Vref Byte 0 = 50 to rank0
5760 10:07:00.375972 Final RX Vref Byte 1 = 50 to rank0
5761 10:07:00.379079 Final RX Vref Byte 0 = 50 to rank1
5762 10:07:00.382471 Final RX Vref Byte 1 = 50 to rank1==
5763 10:07:00.385859 Dram Type= 6, Freq= 0, CH_1, rank 0
5764 10:07:00.392558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 10:07:00.392643 ==
5766 10:07:00.392710 DQS Delay:
5767 10:07:00.395595 DQS0 = 0, DQS1 = 0
5768 10:07:00.395679 DQM Delay:
5769 10:07:00.395766 DQM0 = 108, DQM1 = 100
5770 10:07:00.398843 DQ Delay:
5771 10:07:00.402184 DQ0 =110, DQ1 =102, DQ2 =100, DQ3 =108
5772 10:07:00.405714 DQ4 =108, DQ5 =116, DQ6 =118, DQ7 =104
5773 10:07:00.409029 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =94
5774 10:07:00.412334 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =104
5775 10:07:00.412425
5776 10:07:00.412536
5777 10:07:00.422287 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e36, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 412 ps
5778 10:07:00.422375 CH1 RK0: MR19=505, MR18=1E36
5779 10:07:00.428659 CH1_RK0: MR19=0x505, MR18=0x1E36, DQSOSC=404, MR23=63, INC=66, DEC=44
5780 10:07:00.428777
5781 10:07:00.431802 ----->DramcWriteLeveling(PI) begin...
5782 10:07:00.431879 ==
5783 10:07:00.435347 Dram Type= 6, Freq= 0, CH_1, rank 1
5784 10:07:00.442005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 10:07:00.442086 ==
5786 10:07:00.445483 Write leveling (Byte 0): 26 => 26
5787 10:07:00.448523 Write leveling (Byte 1): 28 => 28
5788 10:07:00.448604 DramcWriteLeveling(PI) end<-----
5789 10:07:00.448670
5790 10:07:00.451694 ==
5791 10:07:00.455210 Dram Type= 6, Freq= 0, CH_1, rank 1
5792 10:07:00.458360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 10:07:00.458458 ==
5794 10:07:00.461836 [Gating] SW mode calibration
5795 10:07:00.468181 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5796 10:07:00.471840 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5797 10:07:00.478001 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 10:07:00.481659 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 10:07:00.485227 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 10:07:00.491252 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 10:07:00.494678 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 10:07:00.498252 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 10:07:00.504458 0 14 24 | B1->B0 | 3131 3434 | 0 1 | (1 0) (1 0)
5804 10:07:00.508191 0 14 28 | B1->B0 | 2323 2d2d | 0 0 | (1 0) (1 0)
5805 10:07:00.511020 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5806 10:07:00.517812 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 10:07:00.521243 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 10:07:00.524326 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 10:07:00.531201 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 10:07:00.534281 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 10:07:00.537537 0 15 24 | B1->B0 | 2626 2525 | 1 0 | (0 0) (0 0)
5812 10:07:00.544119 0 15 28 | B1->B0 | 4646 3b3a | 0 1 | (0 0) (0 0)
5813 10:07:00.547696 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5814 10:07:00.550899 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 10:07:00.557547 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 10:07:00.561223 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 10:07:00.564338 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 10:07:00.570810 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 10:07:00.574096 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5820 10:07:00.577588 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 10:07:00.583893 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 10:07:00.587221 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 10:07:00.590641 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 10:07:00.597115 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 10:07:00.600657 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 10:07:00.604164 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 10:07:00.610320 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 10:07:00.613933 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 10:07:00.617014 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 10:07:00.623668 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 10:07:00.627250 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 10:07:00.630428 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 10:07:00.636797 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 10:07:00.640301 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 10:07:00.643761 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5836 10:07:00.650408 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 10:07:00.650494 Total UI for P1: 0, mck2ui 16
5838 10:07:00.653701 best dqsien dly found for B0: ( 1, 2, 24)
5839 10:07:00.656711 Total UI for P1: 0, mck2ui 16
5840 10:07:00.660262 best dqsien dly found for B1: ( 1, 2, 24)
5841 10:07:00.667114 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5842 10:07:00.670165 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5843 10:07:00.670278
5844 10:07:00.673203 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5845 10:07:00.676855 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5846 10:07:00.680419 [Gating] SW calibration Done
5847 10:07:00.680532 ==
5848 10:07:00.683377 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 10:07:00.686619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 10:07:00.686737 ==
5851 10:07:00.690105 RX Vref Scan: 0
5852 10:07:00.690220
5853 10:07:00.690326 RX Vref 0 -> 0, step: 1
5854 10:07:00.690422
5855 10:07:00.693151 RX Delay -80 -> 252, step: 8
5856 10:07:00.696400 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
5857 10:07:00.703048 iDelay=200, Bit 1, Center 103 (24 ~ 183) 160
5858 10:07:00.706586 iDelay=200, Bit 2, Center 95 (16 ~ 175) 160
5859 10:07:00.709649 iDelay=200, Bit 3, Center 107 (24 ~ 191) 168
5860 10:07:00.713377 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5861 10:07:00.716493 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5862 10:07:00.723301 iDelay=200, Bit 6, Center 107 (24 ~ 191) 168
5863 10:07:00.726402 iDelay=200, Bit 7, Center 107 (24 ~ 191) 168
5864 10:07:00.729596 iDelay=200, Bit 8, Center 87 (0 ~ 175) 176
5865 10:07:00.732953 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5866 10:07:00.736352 iDelay=200, Bit 10, Center 103 (16 ~ 191) 176
5867 10:07:00.739656 iDelay=200, Bit 11, Center 95 (8 ~ 183) 176
5868 10:07:00.745939 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5869 10:07:00.749457 iDelay=200, Bit 13, Center 103 (16 ~ 191) 176
5870 10:07:00.753013 iDelay=200, Bit 14, Center 107 (16 ~ 199) 184
5871 10:07:00.756204 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5872 10:07:00.756283 ==
5873 10:07:00.759455 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 10:07:00.766073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 10:07:00.766193 ==
5876 10:07:00.766260 DQS Delay:
5877 10:07:00.769510 DQS0 = 0, DQS1 = 0
5878 10:07:00.769606 DQM Delay:
5879 10:07:00.769673 DQM0 = 105, DQM1 = 99
5880 10:07:00.772774 DQ Delay:
5881 10:07:00.776215 DQ0 =111, DQ1 =103, DQ2 =95, DQ3 =107
5882 10:07:00.779307 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =107
5883 10:07:00.782645 DQ8 =87, DQ9 =87, DQ10 =103, DQ11 =95
5884 10:07:00.786051 DQ12 =107, DQ13 =103, DQ14 =107, DQ15 =107
5885 10:07:00.786164
5886 10:07:00.786259
5887 10:07:00.786348 ==
5888 10:07:00.789595 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 10:07:00.792659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 10:07:00.792788 ==
5891 10:07:00.792873
5892 10:07:00.796438
5893 10:07:00.796542 TX Vref Scan disable
5894 10:07:00.799400 == TX Byte 0 ==
5895 10:07:00.802807 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5896 10:07:00.806227 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5897 10:07:00.809308 == TX Byte 1 ==
5898 10:07:00.812718 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5899 10:07:00.816144 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5900 10:07:00.816253 ==
5901 10:07:00.819136 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 10:07:00.825774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 10:07:00.825857 ==
5904 10:07:00.826040
5905 10:07:00.826146
5906 10:07:00.826277 TX Vref Scan disable
5907 10:07:00.830294 == TX Byte 0 ==
5908 10:07:00.833258 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5909 10:07:00.839989 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5910 10:07:00.840145 == TX Byte 1 ==
5911 10:07:00.843207 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5912 10:07:00.850070 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5913 10:07:00.850155
5914 10:07:00.850222 [DATLAT]
5915 10:07:00.850321 Freq=933, CH1 RK1
5916 10:07:00.850382
5917 10:07:00.853164 DATLAT Default: 0xb
5918 10:07:00.853284 0, 0xFFFF, sum = 0
5919 10:07:00.856778 1, 0xFFFF, sum = 0
5920 10:07:00.859761 2, 0xFFFF, sum = 0
5921 10:07:00.859868 3, 0xFFFF, sum = 0
5922 10:07:00.863322 4, 0xFFFF, sum = 0
5923 10:07:00.863434 5, 0xFFFF, sum = 0
5924 10:07:00.866625 6, 0xFFFF, sum = 0
5925 10:07:00.866727 7, 0xFFFF, sum = 0
5926 10:07:00.869654 8, 0xFFFF, sum = 0
5927 10:07:00.869725 9, 0xFFFF, sum = 0
5928 10:07:00.873289 10, 0x0, sum = 1
5929 10:07:00.873374 11, 0x0, sum = 2
5930 10:07:00.876480 12, 0x0, sum = 3
5931 10:07:00.876553 13, 0x0, sum = 4
5932 10:07:00.876617 best_step = 11
5933 10:07:00.876675
5934 10:07:00.880017 ==
5935 10:07:00.883246 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 10:07:00.886383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 10:07:00.886493 ==
5938 10:07:00.886588 RX Vref Scan: 0
5939 10:07:00.886679
5940 10:07:00.889661 RX Vref 0 -> 0, step: 1
5941 10:07:00.889746
5942 10:07:00.892810 RX Delay -45 -> 252, step: 4
5943 10:07:00.899552 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
5944 10:07:00.902894 iDelay=199, Bit 1, Center 102 (27 ~ 178) 152
5945 10:07:00.906078 iDelay=199, Bit 2, Center 96 (23 ~ 170) 148
5946 10:07:00.909644 iDelay=199, Bit 3, Center 106 (31 ~ 182) 152
5947 10:07:00.912759 iDelay=199, Bit 4, Center 110 (35 ~ 186) 152
5948 10:07:00.916160 iDelay=199, Bit 5, Center 118 (39 ~ 198) 160
5949 10:07:00.922812 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5950 10:07:00.926041 iDelay=199, Bit 7, Center 106 (31 ~ 182) 152
5951 10:07:00.929374 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5952 10:07:00.932489 iDelay=199, Bit 9, Center 92 (15 ~ 170) 156
5953 10:07:00.936224 iDelay=199, Bit 10, Center 100 (19 ~ 182) 164
5954 10:07:00.942996 iDelay=199, Bit 11, Center 96 (15 ~ 178) 164
5955 10:07:00.946127 iDelay=199, Bit 12, Center 108 (27 ~ 190) 164
5956 10:07:00.949518 iDelay=199, Bit 13, Center 106 (27 ~ 186) 160
5957 10:07:00.952598 iDelay=199, Bit 14, Center 108 (27 ~ 190) 164
5958 10:07:00.956130 iDelay=199, Bit 15, Center 110 (27 ~ 194) 168
5959 10:07:00.959311 ==
5960 10:07:00.962495 Dram Type= 6, Freq= 0, CH_1, rank 1
5961 10:07:00.966000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5962 10:07:00.966089 ==
5963 10:07:00.966176 DQS Delay:
5964 10:07:00.969070 DQS0 = 0, DQS1 = 0
5965 10:07:00.969158 DQM Delay:
5966 10:07:00.972219 DQM0 = 108, DQM1 = 101
5967 10:07:00.972307 DQ Delay:
5968 10:07:00.975653 DQ0 =114, DQ1 =102, DQ2 =96, DQ3 =106
5969 10:07:00.978927 DQ4 =110, DQ5 =118, DQ6 =114, DQ7 =106
5970 10:07:00.982410 DQ8 =88, DQ9 =92, DQ10 =100, DQ11 =96
5971 10:07:00.985489 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =110
5972 10:07:00.985578
5973 10:07:00.985665
5974 10:07:00.995511 [DQSOSCAuto] RK1, (LSB)MR18= 0x2502, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
5975 10:07:00.998685 CH1 RK1: MR19=505, MR18=2502
5976 10:07:01.002226 CH1_RK1: MR19=0x505, MR18=0x2502, DQSOSC=410, MR23=63, INC=64, DEC=42
5977 10:07:01.005395 [RxdqsGatingPostProcess] freq 933
5978 10:07:01.011826 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5979 10:07:01.015245 best DQS0 dly(2T, 0.5T) = (0, 10)
5980 10:07:01.018886 best DQS1 dly(2T, 0.5T) = (0, 10)
5981 10:07:01.021963 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5982 10:07:01.025294 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5983 10:07:01.028793 best DQS0 dly(2T, 0.5T) = (0, 10)
5984 10:07:01.032309 best DQS1 dly(2T, 0.5T) = (0, 10)
5985 10:07:01.035151 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5986 10:07:01.038698 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5987 10:07:01.038784 Pre-setting of DQS Precalculation
5988 10:07:01.045309 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5989 10:07:01.051734 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5990 10:07:01.058628 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5991 10:07:01.058713
5992 10:07:01.058781
5993 10:07:01.062117 [Calibration Summary] 1866 Mbps
5994 10:07:01.065207 CH 0, Rank 0
5995 10:07:01.065291 SW Impedance : PASS
5996 10:07:01.068379 DUTY Scan : NO K
5997 10:07:01.071959 ZQ Calibration : PASS
5998 10:07:01.072043 Jitter Meter : NO K
5999 10:07:01.074816 CBT Training : PASS
6000 10:07:01.078428 Write leveling : PASS
6001 10:07:01.078532 RX DQS gating : PASS
6002 10:07:01.081642 RX DQ/DQS(RDDQC) : PASS
6003 10:07:01.085107 TX DQ/DQS : PASS
6004 10:07:01.085217 RX DATLAT : PASS
6005 10:07:01.088162 RX DQ/DQS(Engine): PASS
6006 10:07:01.091403 TX OE : NO K
6007 10:07:01.091488 All Pass.
6008 10:07:01.091611
6009 10:07:01.091711 CH 0, Rank 1
6010 10:07:01.094845 SW Impedance : PASS
6011 10:07:01.097937 DUTY Scan : NO K
6012 10:07:01.098045 ZQ Calibration : PASS
6013 10:07:01.101185 Jitter Meter : NO K
6014 10:07:01.101286 CBT Training : PASS
6015 10:07:01.104436 Write leveling : PASS
6016 10:07:01.107951 RX DQS gating : PASS
6017 10:07:01.108061 RX DQ/DQS(RDDQC) : PASS
6018 10:07:01.111470 TX DQ/DQS : PASS
6019 10:07:01.114828 RX DATLAT : PASS
6020 10:07:01.114912 RX DQ/DQS(Engine): PASS
6021 10:07:01.118089 TX OE : NO K
6022 10:07:01.118199 All Pass.
6023 10:07:01.118293
6024 10:07:01.121088 CH 1, Rank 0
6025 10:07:01.121172 SW Impedance : PASS
6026 10:07:01.124660 DUTY Scan : NO K
6027 10:07:01.127920 ZQ Calibration : PASS
6028 10:07:01.128029 Jitter Meter : NO K
6029 10:07:01.131326 CBT Training : PASS
6030 10:07:01.134704 Write leveling : PASS
6031 10:07:01.134820 RX DQS gating : PASS
6032 10:07:01.137808 RX DQ/DQS(RDDQC) : PASS
6033 10:07:01.140741 TX DQ/DQS : PASS
6034 10:07:01.140873 RX DATLAT : PASS
6035 10:07:01.144503 RX DQ/DQS(Engine): PASS
6036 10:07:01.147594 TX OE : NO K
6037 10:07:01.147681 All Pass.
6038 10:07:01.147748
6039 10:07:01.147811 CH 1, Rank 1
6040 10:07:01.150744 SW Impedance : PASS
6041 10:07:01.154153 DUTY Scan : NO K
6042 10:07:01.154248 ZQ Calibration : PASS
6043 10:07:01.157611 Jitter Meter : NO K
6044 10:07:01.160681 CBT Training : PASS
6045 10:07:01.160850 Write leveling : PASS
6046 10:07:01.163971 RX DQS gating : PASS
6047 10:07:01.167152 RX DQ/DQS(RDDQC) : PASS
6048 10:07:01.167261 TX DQ/DQS : PASS
6049 10:07:01.170555 RX DATLAT : PASS
6050 10:07:01.170724 RX DQ/DQS(Engine): PASS
6051 10:07:01.173715 TX OE : NO K
6052 10:07:01.173790 All Pass.
6053 10:07:01.173854
6054 10:07:01.177354 DramC Write-DBI off
6055 10:07:01.180618 PER_BANK_REFRESH: Hybrid Mode
6056 10:07:01.180718 TX_TRACKING: ON
6057 10:07:01.190514 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6058 10:07:01.193584 [FAST_K] Save calibration result to emmc
6059 10:07:01.197154 dramc_set_vcore_voltage set vcore to 650000
6060 10:07:01.200333 Read voltage for 400, 6
6061 10:07:01.200411 Vio18 = 0
6062 10:07:01.203796 Vcore = 650000
6063 10:07:01.203875 Vdram = 0
6064 10:07:01.203950 Vddq = 0
6065 10:07:01.204016 Vmddr = 0
6066 10:07:01.209947 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6067 10:07:01.216992 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6068 10:07:01.217082 MEM_TYPE=3, freq_sel=20
6069 10:07:01.220112 sv_algorithm_assistance_LP4_800
6070 10:07:01.223605 ============ PULL DRAM RESETB DOWN ============
6071 10:07:01.230194 ========== PULL DRAM RESETB DOWN end =========
6072 10:07:01.233457 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6073 10:07:01.236534 ===================================
6074 10:07:01.240147 LPDDR4 DRAM CONFIGURATION
6075 10:07:01.243323 ===================================
6076 10:07:01.243408 EX_ROW_EN[0] = 0x0
6077 10:07:01.246724 EX_ROW_EN[1] = 0x0
6078 10:07:01.246799 LP4Y_EN = 0x0
6079 10:07:01.249992 WORK_FSP = 0x0
6080 10:07:01.250069 WL = 0x2
6081 10:07:01.253355 RL = 0x2
6082 10:07:01.256558 BL = 0x2
6083 10:07:01.256665 RPST = 0x0
6084 10:07:01.260029 RD_PRE = 0x0
6085 10:07:01.260108 WR_PRE = 0x1
6086 10:07:01.263312 WR_PST = 0x0
6087 10:07:01.263386 DBI_WR = 0x0
6088 10:07:01.266561 DBI_RD = 0x0
6089 10:07:01.266641 OTF = 0x1
6090 10:07:01.269853 ===================================
6091 10:07:01.273172 ===================================
6092 10:07:01.276491 ANA top config
6093 10:07:01.279811 ===================================
6094 10:07:01.279889 DLL_ASYNC_EN = 0
6095 10:07:01.283138 ALL_SLAVE_EN = 1
6096 10:07:01.286296 NEW_RANK_MODE = 1
6097 10:07:01.289798 DLL_IDLE_MODE = 1
6098 10:07:01.289879 LP45_APHY_COMB_EN = 1
6099 10:07:01.292698 TX_ODT_DIS = 1
6100 10:07:01.296458 NEW_8X_MODE = 1
6101 10:07:01.299470 ===================================
6102 10:07:01.303001 ===================================
6103 10:07:01.306283 data_rate = 800
6104 10:07:01.309360 CKR = 1
6105 10:07:01.312563 DQ_P2S_RATIO = 4
6106 10:07:01.315601 ===================================
6107 10:07:01.315682 CA_P2S_RATIO = 4
6108 10:07:01.319027 DQ_CA_OPEN = 0
6109 10:07:01.322366 DQ_SEMI_OPEN = 1
6110 10:07:01.325850 CA_SEMI_OPEN = 1
6111 10:07:01.328937 CA_FULL_RATE = 0
6112 10:07:01.332392 DQ_CKDIV4_EN = 0
6113 10:07:01.332468 CA_CKDIV4_EN = 1
6114 10:07:01.335742 CA_PREDIV_EN = 0
6115 10:07:01.339252 PH8_DLY = 0
6116 10:07:01.342387 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6117 10:07:01.345563 DQ_AAMCK_DIV = 0
6118 10:07:01.349043 CA_AAMCK_DIV = 0
6119 10:07:01.349121 CA_ADMCK_DIV = 4
6120 10:07:01.352130 DQ_TRACK_CA_EN = 0
6121 10:07:01.355556 CA_PICK = 800
6122 10:07:01.358680 CA_MCKIO = 400
6123 10:07:01.362260 MCKIO_SEMI = 400
6124 10:07:01.365380 PLL_FREQ = 3016
6125 10:07:01.368999 DQ_UI_PI_RATIO = 32
6126 10:07:01.371701 CA_UI_PI_RATIO = 32
6127 10:07:01.375169 ===================================
6128 10:07:01.378466 ===================================
6129 10:07:01.378553 memory_type:LPDDR4
6130 10:07:01.381738 GP_NUM : 10
6131 10:07:01.385184 SRAM_EN : 1
6132 10:07:01.385271 MD32_EN : 0
6133 10:07:01.388313 ===================================
6134 10:07:01.391553 [ANA_INIT] >>>>>>>>>>>>>>
6135 10:07:01.395328 <<<<<< [CONFIGURE PHASE]: ANA_TX
6136 10:07:01.398501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6137 10:07:01.401561 ===================================
6138 10:07:01.405039 data_rate = 800,PCW = 0X7400
6139 10:07:01.408214 ===================================
6140 10:07:01.411637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6141 10:07:01.415190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6142 10:07:01.428356 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6143 10:07:01.431402 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6144 10:07:01.434915 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6145 10:07:01.438027 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6146 10:07:01.441266 [ANA_INIT] flow start
6147 10:07:01.444658 [ANA_INIT] PLL >>>>>>>>
6148 10:07:01.444792 [ANA_INIT] PLL <<<<<<<<
6149 10:07:01.447794 [ANA_INIT] MIDPI >>>>>>>>
6150 10:07:01.451360 [ANA_INIT] MIDPI <<<<<<<<
6151 10:07:01.451461 [ANA_INIT] DLL >>>>>>>>
6152 10:07:01.454478 [ANA_INIT] flow end
6153 10:07:01.457727 ============ LP4 DIFF to SE enter ============
6154 10:07:01.464461 ============ LP4 DIFF to SE exit ============
6155 10:07:01.464573 [ANA_INIT] <<<<<<<<<<<<<
6156 10:07:01.467677 [Flow] Enable top DCM control >>>>>
6157 10:07:01.470715 [Flow] Enable top DCM control <<<<<
6158 10:07:01.474110 Enable DLL master slave shuffle
6159 10:07:01.480584 ==============================================================
6160 10:07:01.480708 Gating Mode config
6161 10:07:01.487341 ==============================================================
6162 10:07:01.490747 Config description:
6163 10:07:01.500783 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6164 10:07:01.507362 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6165 10:07:01.510262 SELPH_MODE 0: By rank 1: By Phase
6166 10:07:01.517154 ==============================================================
6167 10:07:01.520293 GAT_TRACK_EN = 0
6168 10:07:01.520379 RX_GATING_MODE = 2
6169 10:07:01.523489 RX_GATING_TRACK_MODE = 2
6170 10:07:01.526745 SELPH_MODE = 1
6171 10:07:01.530085 PICG_EARLY_EN = 1
6172 10:07:01.533747 VALID_LAT_VALUE = 1
6173 10:07:01.540277 ==============================================================
6174 10:07:01.543627 Enter into Gating configuration >>>>
6175 10:07:01.546741 Exit from Gating configuration <<<<
6176 10:07:01.550284 Enter into DVFS_PRE_config >>>>>
6177 10:07:01.560129 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6178 10:07:01.563096 Exit from DVFS_PRE_config <<<<<
6179 10:07:01.566576 Enter into PICG configuration >>>>
6180 10:07:01.569641 Exit from PICG configuration <<<<
6181 10:07:01.573327 [RX_INPUT] configuration >>>>>
6182 10:07:01.576366 [RX_INPUT] configuration <<<<<
6183 10:07:01.579749 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6184 10:07:01.586181 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6185 10:07:01.592874 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6186 10:07:01.599332 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6187 10:07:01.605995 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6188 10:07:01.609400 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6189 10:07:01.616170 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6190 10:07:01.619280 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6191 10:07:01.622766 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6192 10:07:01.625950 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6193 10:07:01.629468 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6194 10:07:01.635861 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6195 10:07:01.639112 ===================================
6196 10:07:01.642623 LPDDR4 DRAM CONFIGURATION
6197 10:07:01.646142 ===================================
6198 10:07:01.646228 EX_ROW_EN[0] = 0x0
6199 10:07:01.649139 EX_ROW_EN[1] = 0x0
6200 10:07:01.649239 LP4Y_EN = 0x0
6201 10:07:01.652522 WORK_FSP = 0x0
6202 10:07:01.652632 WL = 0x2
6203 10:07:01.655587 RL = 0x2
6204 10:07:01.655704 BL = 0x2
6205 10:07:01.659120 RPST = 0x0
6206 10:07:01.659232 RD_PRE = 0x0
6207 10:07:01.662281 WR_PRE = 0x1
6208 10:07:01.662410 WR_PST = 0x0
6209 10:07:01.665706 DBI_WR = 0x0
6210 10:07:01.665838 DBI_RD = 0x0
6211 10:07:01.669093 OTF = 0x1
6212 10:07:01.672273 ===================================
6213 10:07:01.675741 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6214 10:07:01.678968 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6215 10:07:01.685490 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6216 10:07:01.688756 ===================================
6217 10:07:01.692278 LPDDR4 DRAM CONFIGURATION
6218 10:07:01.695447 ===================================
6219 10:07:01.695564 EX_ROW_EN[0] = 0x10
6220 10:07:01.698726 EX_ROW_EN[1] = 0x0
6221 10:07:01.698811 LP4Y_EN = 0x0
6222 10:07:01.701975 WORK_FSP = 0x0
6223 10:07:01.702060 WL = 0x2
6224 10:07:01.705255 RL = 0x2
6225 10:07:01.705363 BL = 0x2
6226 10:07:01.708512 RPST = 0x0
6227 10:07:01.708624 RD_PRE = 0x0
6228 10:07:01.711663 WR_PRE = 0x1
6229 10:07:01.711775 WR_PST = 0x0
6230 10:07:01.715203 DBI_WR = 0x0
6231 10:07:01.718510 DBI_RD = 0x0
6232 10:07:01.718633 OTF = 0x1
6233 10:07:01.721932 ===================================
6234 10:07:01.728199 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6235 10:07:01.731832 nWR fixed to 30
6236 10:07:01.735345 [ModeRegInit_LP4] CH0 RK0
6237 10:07:01.735448 [ModeRegInit_LP4] CH0 RK1
6238 10:07:01.738482 [ModeRegInit_LP4] CH1 RK0
6239 10:07:01.742048 [ModeRegInit_LP4] CH1 RK1
6240 10:07:01.742125 match AC timing 19
6241 10:07:01.748332 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6242 10:07:01.751807 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6243 10:07:01.755100 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6244 10:07:01.761486 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6245 10:07:01.764931 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6246 10:07:01.765018 ==
6247 10:07:01.767955 Dram Type= 6, Freq= 0, CH_0, rank 0
6248 10:07:01.771296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6249 10:07:01.771383 ==
6250 10:07:01.777915 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6251 10:07:01.784689 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6252 10:07:01.787742 [CA 0] Center 36 (8~64) winsize 57
6253 10:07:01.790919 [CA 1] Center 36 (8~64) winsize 57
6254 10:07:01.794178 [CA 2] Center 36 (8~64) winsize 57
6255 10:07:01.797623 [CA 3] Center 36 (8~64) winsize 57
6256 10:07:01.800864 [CA 4] Center 36 (8~64) winsize 57
6257 10:07:01.804562 [CA 5] Center 36 (8~64) winsize 57
6258 10:07:01.804676
6259 10:07:01.807449 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6260 10:07:01.807572
6261 10:07:01.811083 [CATrainingPosCal] consider 1 rank data
6262 10:07:01.814316 u2DelayCellTimex100 = 270/100 ps
6263 10:07:01.817312 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 10:07:01.821015 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 10:07:01.824210 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 10:07:01.827225 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 10:07:01.830417 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 10:07:01.833879 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 10:07:01.833983
6270 10:07:01.840384 CA PerBit enable=1, Macro0, CA PI delay=36
6271 10:07:01.840470
6272 10:07:01.840537 [CBTSetCACLKResult] CA Dly = 36
6273 10:07:01.843725 CS Dly: 1 (0~32)
6274 10:07:01.843809 ==
6275 10:07:01.846881 Dram Type= 6, Freq= 0, CH_0, rank 1
6276 10:07:01.850454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6277 10:07:01.850545 ==
6278 10:07:01.857045 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6279 10:07:01.863691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6280 10:07:01.866760 [CA 0] Center 36 (8~64) winsize 57
6281 10:07:01.870451 [CA 1] Center 36 (8~64) winsize 57
6282 10:07:01.873527 [CA 2] Center 36 (8~64) winsize 57
6283 10:07:01.876734 [CA 3] Center 36 (8~64) winsize 57
6284 10:07:01.879893 [CA 4] Center 36 (8~64) winsize 57
6285 10:07:01.879968 [CA 5] Center 36 (8~64) winsize 57
6286 10:07:01.883555
6287 10:07:01.886740 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6288 10:07:01.886840
6289 10:07:01.889788 [CATrainingPosCal] consider 2 rank data
6290 10:07:01.893485 u2DelayCellTimex100 = 270/100 ps
6291 10:07:01.896417 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 10:07:01.899983 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 10:07:01.903025 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 10:07:01.906286 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 10:07:01.909734 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 10:07:01.912934 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 10:07:01.913022
6298 10:07:01.916659 CA PerBit enable=1, Macro0, CA PI delay=36
6299 10:07:01.916787
6300 10:07:01.919386 [CBTSetCACLKResult] CA Dly = 36
6301 10:07:01.923147 CS Dly: 1 (0~32)
6302 10:07:01.923249
6303 10:07:01.926338 ----->DramcWriteLeveling(PI) begin...
6304 10:07:01.926429 ==
6305 10:07:01.929725 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 10:07:01.933016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 10:07:01.933107 ==
6308 10:07:01.936297 Write leveling (Byte 0): 40 => 8
6309 10:07:01.939458 Write leveling (Byte 1): 32 => 0
6310 10:07:01.942873 DramcWriteLeveling(PI) end<-----
6311 10:07:01.942960
6312 10:07:01.943028 ==
6313 10:07:01.946202 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 10:07:01.949319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 10:07:01.949406 ==
6316 10:07:01.952787 [Gating] SW mode calibration
6317 10:07:01.959402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6318 10:07:01.966088 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6319 10:07:01.969156 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6320 10:07:01.975722 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6321 10:07:01.979017 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6322 10:07:01.982574 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6323 10:07:01.988850 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 10:07:01.992450 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 10:07:01.995596 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 10:07:02.002012 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 10:07:02.005521 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6328 10:07:02.008576 Total UI for P1: 0, mck2ui 16
6329 10:07:02.012116 best dqsien dly found for B0: ( 0, 14, 24)
6330 10:07:02.015424 Total UI for P1: 0, mck2ui 16
6331 10:07:02.018627 best dqsien dly found for B1: ( 0, 14, 24)
6332 10:07:02.022125 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6333 10:07:02.025237 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6334 10:07:02.025312
6335 10:07:02.028248 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6336 10:07:02.031653 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6337 10:07:02.034967 [Gating] SW calibration Done
6338 10:07:02.035048 ==
6339 10:07:02.038240 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 10:07:02.044692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 10:07:02.044796 ==
6342 10:07:02.044876 RX Vref Scan: 0
6343 10:07:02.044937
6344 10:07:02.048153 RX Vref 0 -> 0, step: 1
6345 10:07:02.048235
6346 10:07:02.051528 RX Delay -410 -> 252, step: 16
6347 10:07:02.054661 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6348 10:07:02.058122 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6349 10:07:02.064750 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6350 10:07:02.067699 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6351 10:07:02.071352 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6352 10:07:02.074759 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6353 10:07:02.081332 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6354 10:07:02.084331 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6355 10:07:02.087827 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6356 10:07:02.091065 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6357 10:07:02.097660 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6358 10:07:02.100958 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6359 10:07:02.104478 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6360 10:07:02.107454 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6361 10:07:02.114430 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6362 10:07:02.117539 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6363 10:07:02.117611 ==
6364 10:07:02.120973 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 10:07:02.124118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 10:07:02.124197 ==
6367 10:07:02.127351 DQS Delay:
6368 10:07:02.127431 DQS0 = 27, DQS1 = 43
6369 10:07:02.130693 DQM Delay:
6370 10:07:02.130777 DQM0 = 12, DQM1 = 13
6371 10:07:02.130841 DQ Delay:
6372 10:07:02.134221 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6373 10:07:02.137350 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6374 10:07:02.140462 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6375 10:07:02.143770 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6376 10:07:02.143885
6377 10:07:02.143979
6378 10:07:02.144071 ==
6379 10:07:02.147027 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 10:07:02.153961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 10:07:02.154063 ==
6382 10:07:02.154127
6383 10:07:02.154186
6384 10:07:02.154243 TX Vref Scan disable
6385 10:07:02.157391 == TX Byte 0 ==
6386 10:07:02.160534 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6387 10:07:02.163729 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6388 10:07:02.167153 == TX Byte 1 ==
6389 10:07:02.170495 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6390 10:07:02.173666 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6391 10:07:02.176799 ==
6392 10:07:02.180218 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 10:07:02.183817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 10:07:02.183896 ==
6395 10:07:02.183983
6396 10:07:02.184068
6397 10:07:02.186696 TX Vref Scan disable
6398 10:07:02.186776 == TX Byte 0 ==
6399 10:07:02.189963 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6400 10:07:02.196446 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6401 10:07:02.196552 == TX Byte 1 ==
6402 10:07:02.200195 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6403 10:07:02.206775 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6404 10:07:02.206854
6405 10:07:02.206935 [DATLAT]
6406 10:07:02.207012 Freq=400, CH0 RK0
6407 10:07:02.207105
6408 10:07:02.210219 DATLAT Default: 0xf
6409 10:07:02.212956 0, 0xFFFF, sum = 0
6410 10:07:02.213037 1, 0xFFFF, sum = 0
6411 10:07:02.216430 2, 0xFFFF, sum = 0
6412 10:07:02.216511 3, 0xFFFF, sum = 0
6413 10:07:02.219532 4, 0xFFFF, sum = 0
6414 10:07:02.219611 5, 0xFFFF, sum = 0
6415 10:07:02.222878 6, 0xFFFF, sum = 0
6416 10:07:02.222963 7, 0xFFFF, sum = 0
6417 10:07:02.226549 8, 0xFFFF, sum = 0
6418 10:07:02.226627 9, 0xFFFF, sum = 0
6419 10:07:02.229701 10, 0xFFFF, sum = 0
6420 10:07:02.229778 11, 0xFFFF, sum = 0
6421 10:07:02.232897 12, 0xFFFF, sum = 0
6422 10:07:02.232978 13, 0x0, sum = 1
6423 10:07:02.236028 14, 0x0, sum = 2
6424 10:07:02.236146 15, 0x0, sum = 3
6425 10:07:02.239263 16, 0x0, sum = 4
6426 10:07:02.239344 best_step = 14
6427 10:07:02.239442
6428 10:07:02.239519 ==
6429 10:07:02.242677 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 10:07:02.249262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 10:07:02.249356 ==
6432 10:07:02.249442 RX Vref Scan: 1
6433 10:07:02.249526
6434 10:07:02.252634 RX Vref 0 -> 0, step: 1
6435 10:07:02.252711
6436 10:07:02.255905 RX Delay -327 -> 252, step: 8
6437 10:07:02.256024
6438 10:07:02.259210 Set Vref, RX VrefLevel [Byte0]: 59
6439 10:07:02.262399 [Byte1]: 49
6440 10:07:02.262474
6441 10:07:02.265792 Final RX Vref Byte 0 = 59 to rank0
6442 10:07:02.269463 Final RX Vref Byte 1 = 49 to rank0
6443 10:07:02.272449 Final RX Vref Byte 0 = 59 to rank1
6444 10:07:02.275858 Final RX Vref Byte 1 = 49 to rank1==
6445 10:07:02.278905 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 10:07:02.282650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 10:07:02.285530 ==
6448 10:07:02.285621 DQS Delay:
6449 10:07:02.285720 DQS0 = 28, DQS1 = 48
6450 10:07:02.289219 DQM Delay:
6451 10:07:02.289296 DQM0 = 12, DQM1 = 16
6452 10:07:02.292598 DQ Delay:
6453 10:07:02.295583 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6454 10:07:02.295655 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6455 10:07:02.298702 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6456 10:07:02.302209 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6457 10:07:02.305388
6458 10:07:02.305541
6459 10:07:02.311953 [DQSOSCAuto] RK0, (LSB)MR18= 0xb3ab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6460 10:07:02.315325 CH0 RK0: MR19=C0C, MR18=B3AB
6461 10:07:02.321878 CH0_RK0: MR19=0xC0C, MR18=0xB3AB, DQSOSC=387, MR23=63, INC=394, DEC=262
6462 10:07:02.321998 ==
6463 10:07:02.325428 Dram Type= 6, Freq= 0, CH_0, rank 1
6464 10:07:02.328556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 10:07:02.328663 ==
6466 10:07:02.331659 [Gating] SW mode calibration
6467 10:07:02.338221 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6468 10:07:02.344910 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6469 10:07:02.348415 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6470 10:07:02.351507 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6471 10:07:02.358275 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 10:07:02.361460 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6473 10:07:02.364972 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 10:07:02.371697 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 10:07:02.374785 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 10:07:02.378220 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 10:07:02.384911 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6478 10:07:02.384991 Total UI for P1: 0, mck2ui 16
6479 10:07:02.391512 best dqsien dly found for B0: ( 0, 14, 24)
6480 10:07:02.391591 Total UI for P1: 0, mck2ui 16
6481 10:07:02.397925 best dqsien dly found for B1: ( 0, 14, 24)
6482 10:07:02.401396 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6483 10:07:02.404636 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6484 10:07:02.404746
6485 10:07:02.407855 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6486 10:07:02.411085 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6487 10:07:02.414522 [Gating] SW calibration Done
6488 10:07:02.414600 ==
6489 10:07:02.417713 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 10:07:02.421345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 10:07:02.421448 ==
6492 10:07:02.424572 RX Vref Scan: 0
6493 10:07:02.424696
6494 10:07:02.424831 RX Vref 0 -> 0, step: 1
6495 10:07:02.424917
6496 10:07:02.427583 RX Delay -410 -> 252, step: 16
6497 10:07:02.434241 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6498 10:07:02.437780 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6499 10:07:02.441268 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6500 10:07:02.444317 iDelay=230, Bit 3, Center -11 (-234 ~ 213) 448
6501 10:07:02.451119 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6502 10:07:02.454231 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6503 10:07:02.457367 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6504 10:07:02.460938 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6505 10:07:02.467241 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6506 10:07:02.470573 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6507 10:07:02.473796 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6508 10:07:02.477437 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6509 10:07:02.483765 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6510 10:07:02.487248 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6511 10:07:02.490281 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6512 10:07:02.497038 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6513 10:07:02.497127 ==
6514 10:07:02.500362 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 10:07:02.503514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 10:07:02.503592 ==
6517 10:07:02.503691 DQS Delay:
6518 10:07:02.506993 DQS0 = 27, DQS1 = 43
6519 10:07:02.507069 DQM Delay:
6520 10:07:02.510125 DQM0 = 14, DQM1 = 16
6521 10:07:02.510204 DQ Delay:
6522 10:07:02.513741 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =16
6523 10:07:02.516857 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6524 10:07:02.519986 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6525 10:07:02.523402 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6526 10:07:02.523522
6527 10:07:02.523622
6528 10:07:02.523709 ==
6529 10:07:02.526710 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 10:07:02.529908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 10:07:02.529999 ==
6532 10:07:02.530079
6533 10:07:02.530157
6534 10:07:02.533308 TX Vref Scan disable
6535 10:07:02.536520 == TX Byte 0 ==
6536 10:07:02.540064 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6537 10:07:02.542998 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6538 10:07:02.546272 == TX Byte 1 ==
6539 10:07:02.549696 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6540 10:07:02.552756 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6541 10:07:02.552864 ==
6542 10:07:02.556085 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 10:07:02.559594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 10:07:02.559691 ==
6545 10:07:02.562757
6546 10:07:02.562837
6547 10:07:02.562919 TX Vref Scan disable
6548 10:07:02.566095 == TX Byte 0 ==
6549 10:07:02.569739 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6550 10:07:02.572925 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6551 10:07:02.576352 == TX Byte 1 ==
6552 10:07:02.579445 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6553 10:07:02.582577 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6554 10:07:02.582659
6555 10:07:02.582758 [DATLAT]
6556 10:07:02.585998 Freq=400, CH0 RK1
6557 10:07:02.586086
6558 10:07:02.589106 DATLAT Default: 0xe
6559 10:07:02.589186 0, 0xFFFF, sum = 0
6560 10:07:02.592673 1, 0xFFFF, sum = 0
6561 10:07:02.592785 2, 0xFFFF, sum = 0
6562 10:07:02.595868 3, 0xFFFF, sum = 0
6563 10:07:02.595961 4, 0xFFFF, sum = 0
6564 10:07:02.599318 5, 0xFFFF, sum = 0
6565 10:07:02.599401 6, 0xFFFF, sum = 0
6566 10:07:02.602446 7, 0xFFFF, sum = 0
6567 10:07:02.602538 8, 0xFFFF, sum = 0
6568 10:07:02.605800 9, 0xFFFF, sum = 0
6569 10:07:02.605893 10, 0xFFFF, sum = 0
6570 10:07:02.609313 11, 0xFFFF, sum = 0
6571 10:07:02.609394 12, 0xFFFF, sum = 0
6572 10:07:02.612380 13, 0x0, sum = 1
6573 10:07:02.612492 14, 0x0, sum = 2
6574 10:07:02.615316 15, 0x0, sum = 3
6575 10:07:02.615396 16, 0x0, sum = 4
6576 10:07:02.618909 best_step = 14
6577 10:07:02.618993
6578 10:07:02.619058 ==
6579 10:07:02.621922 Dram Type= 6, Freq= 0, CH_0, rank 1
6580 10:07:02.625433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 10:07:02.625517 ==
6582 10:07:02.628915 RX Vref Scan: 0
6583 10:07:02.628998
6584 10:07:02.629063 RX Vref 0 -> 0, step: 1
6585 10:07:02.629123
6586 10:07:02.632044 RX Delay -327 -> 252, step: 8
6587 10:07:02.640255 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6588 10:07:02.643243 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6589 10:07:02.646678 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6590 10:07:02.653371 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6591 10:07:02.656413 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6592 10:07:02.659961 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6593 10:07:02.663278 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6594 10:07:02.669754 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6595 10:07:02.673059 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6596 10:07:02.676250 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6597 10:07:02.679500 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6598 10:07:02.686572 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6599 10:07:02.689420 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6600 10:07:02.692632 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6601 10:07:02.696283 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6602 10:07:02.702883 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6603 10:07:02.702966 ==
6604 10:07:02.705990 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 10:07:02.709269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 10:07:02.709355 ==
6607 10:07:02.709421 DQS Delay:
6608 10:07:02.712562 DQS0 = 28, DQS1 = 40
6609 10:07:02.712645 DQM Delay:
6610 10:07:02.715670 DQM0 = 10, DQM1 = 12
6611 10:07:02.715780 DQ Delay:
6612 10:07:02.719362 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6613 10:07:02.722284 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6614 10:07:02.725826 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6615 10:07:02.729355 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6616 10:07:02.729440
6617 10:07:02.729507
6618 10:07:02.735860 [DQSOSCAuto] RK1, (LSB)MR18= 0xb86a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6619 10:07:02.739031 CH0 RK1: MR19=C0C, MR18=B86A
6620 10:07:02.745682 CH0_RK1: MR19=0xC0C, MR18=0xB86A, DQSOSC=386, MR23=63, INC=396, DEC=264
6621 10:07:02.749209 [RxdqsGatingPostProcess] freq 400
6622 10:07:02.755532 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6623 10:07:02.758759 best DQS0 dly(2T, 0.5T) = (0, 10)
6624 10:07:02.762274 best DQS1 dly(2T, 0.5T) = (0, 10)
6625 10:07:02.765322 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6626 10:07:02.768791 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6627 10:07:02.772440 best DQS0 dly(2T, 0.5T) = (0, 10)
6628 10:07:02.772525 best DQS1 dly(2T, 0.5T) = (0, 10)
6629 10:07:02.775121 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6630 10:07:02.778423 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6631 10:07:02.781752 Pre-setting of DQS Precalculation
6632 10:07:02.788222 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6633 10:07:02.788309 ==
6634 10:07:02.791699 Dram Type= 6, Freq= 0, CH_1, rank 0
6635 10:07:02.795075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 10:07:02.795160 ==
6637 10:07:02.801685 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6638 10:07:02.808367 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6639 10:07:02.811490 [CA 0] Center 36 (8~64) winsize 57
6640 10:07:02.814862 [CA 1] Center 36 (8~64) winsize 57
6641 10:07:02.818493 [CA 2] Center 36 (8~64) winsize 57
6642 10:07:02.818577 [CA 3] Center 36 (8~64) winsize 57
6643 10:07:02.821397 [CA 4] Center 36 (8~64) winsize 57
6644 10:07:02.824656 [CA 5] Center 36 (8~64) winsize 57
6645 10:07:02.824739
6646 10:07:02.831251 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6647 10:07:02.831362
6648 10:07:02.834933 [CATrainingPosCal] consider 1 rank data
6649 10:07:02.837824 u2DelayCellTimex100 = 270/100 ps
6650 10:07:02.841364 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 10:07:02.844413 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 10:07:02.848097 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 10:07:02.851431 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 10:07:02.854488 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 10:07:02.857803 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 10:07:02.857913
6657 10:07:02.860932 CA PerBit enable=1, Macro0, CA PI delay=36
6658 10:07:02.861005
6659 10:07:02.864244 [CBTSetCACLKResult] CA Dly = 36
6660 10:07:02.867819 CS Dly: 1 (0~32)
6661 10:07:02.867902 ==
6662 10:07:02.871222 Dram Type= 6, Freq= 0, CH_1, rank 1
6663 10:07:02.874598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6664 10:07:02.874681 ==
6665 10:07:02.880995 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6666 10:07:02.884238 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6667 10:07:02.887736 [CA 0] Center 36 (8~64) winsize 57
6668 10:07:02.890935 [CA 1] Center 36 (8~64) winsize 57
6669 10:07:02.894150 [CA 2] Center 36 (8~64) winsize 57
6670 10:07:02.897436 [CA 3] Center 36 (8~64) winsize 57
6671 10:07:02.900807 [CA 4] Center 36 (8~64) winsize 57
6672 10:07:02.903921 [CA 5] Center 36 (8~64) winsize 57
6673 10:07:02.904005
6674 10:07:02.907525 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6675 10:07:02.907609
6676 10:07:02.910753 [CATrainingPosCal] consider 2 rank data
6677 10:07:02.914182 u2DelayCellTimex100 = 270/100 ps
6678 10:07:02.917179 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 10:07:02.924081 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 10:07:02.927129 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 10:07:02.930591 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 10:07:02.933811 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 10:07:02.936978 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 10:07:02.937061
6685 10:07:02.940322 CA PerBit enable=1, Macro0, CA PI delay=36
6686 10:07:02.940405
6687 10:07:02.943947 [CBTSetCACLKResult] CA Dly = 36
6688 10:07:02.946784 CS Dly: 1 (0~32)
6689 10:07:02.946919
6690 10:07:02.950426 ----->DramcWriteLeveling(PI) begin...
6691 10:07:02.950510 ==
6692 10:07:02.953531 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 10:07:02.957065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 10:07:02.957150 ==
6695 10:07:02.960362 Write leveling (Byte 0): 40 => 8
6696 10:07:02.963453 Write leveling (Byte 1): 32 => 0
6697 10:07:02.967188 DramcWriteLeveling(PI) end<-----
6698 10:07:02.967343
6699 10:07:02.967413 ==
6700 10:07:02.970278 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 10:07:02.973250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 10:07:02.973335 ==
6703 10:07:02.976813 [Gating] SW mode calibration
6704 10:07:02.983529 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6705 10:07:02.990062 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6706 10:07:02.993250 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6707 10:07:02.996474 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6708 10:07:03.002923 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6709 10:07:03.006179 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6710 10:07:03.009730 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 10:07:03.016053 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 10:07:03.019557 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 10:07:03.022951 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 10:07:03.029686 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6715 10:07:03.032735 Total UI for P1: 0, mck2ui 16
6716 10:07:03.036267 best dqsien dly found for B0: ( 0, 14, 24)
6717 10:07:03.036344 Total UI for P1: 0, mck2ui 16
6718 10:07:03.042583 best dqsien dly found for B1: ( 0, 14, 24)
6719 10:07:03.046032 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6720 10:07:03.049106 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6721 10:07:03.049189
6722 10:07:03.052712 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6723 10:07:03.055816 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6724 10:07:03.059400 [Gating] SW calibration Done
6725 10:07:03.059519 ==
6726 10:07:03.062683 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 10:07:03.065663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 10:07:03.065738 ==
6729 10:07:03.069086 RX Vref Scan: 0
6730 10:07:03.069161
6731 10:07:03.069229 RX Vref 0 -> 0, step: 1
6732 10:07:03.072355
6733 10:07:03.072431 RX Delay -410 -> 252, step: 16
6734 10:07:03.078865 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6735 10:07:03.082457 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6736 10:07:03.085679 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6737 10:07:03.088890 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6738 10:07:03.095685 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6739 10:07:03.098484 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6740 10:07:03.101864 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6741 10:07:03.105211 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6742 10:07:03.112177 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6743 10:07:03.115231 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6744 10:07:03.118333 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6745 10:07:03.125422 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6746 10:07:03.128646 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6747 10:07:03.131621 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6748 10:07:03.135127 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6749 10:07:03.141468 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6750 10:07:03.141543 ==
6751 10:07:03.145111 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 10:07:03.148322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 10:07:03.148414 ==
6754 10:07:03.148481 DQS Delay:
6755 10:07:03.151515 DQS0 = 27, DQS1 = 35
6756 10:07:03.151592 DQM Delay:
6757 10:07:03.155157 DQM0 = 5, DQM1 = 10
6758 10:07:03.155243 DQ Delay:
6759 10:07:03.158057 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6760 10:07:03.161517 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6761 10:07:03.164683 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6762 10:07:03.168054 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =16
6763 10:07:03.168127
6764 10:07:03.168208
6765 10:07:03.168271 ==
6766 10:07:03.171118 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 10:07:03.174584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 10:07:03.174672 ==
6769 10:07:03.174736
6770 10:07:03.174807
6771 10:07:03.178172 TX Vref Scan disable
6772 10:07:03.178245 == TX Byte 0 ==
6773 10:07:03.184747 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 10:07:03.187800 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 10:07:03.187889 == TX Byte 1 ==
6776 10:07:03.194395 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6777 10:07:03.197858 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6778 10:07:03.197937 ==
6779 10:07:03.200975 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 10:07:03.204496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 10:07:03.204575 ==
6782 10:07:03.207377
6783 10:07:03.207446
6784 10:07:03.207514 TX Vref Scan disable
6785 10:07:03.211151 == TX Byte 0 ==
6786 10:07:03.214127 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6787 10:07:03.217651 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6788 10:07:03.220533 == TX Byte 1 ==
6789 10:07:03.224166 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6790 10:07:03.227489 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6791 10:07:03.227568
6792 10:07:03.230544 [DATLAT]
6793 10:07:03.230621 Freq=400, CH1 RK0
6794 10:07:03.230683
6795 10:07:03.233798 DATLAT Default: 0xf
6796 10:07:03.233873 0, 0xFFFF, sum = 0
6797 10:07:03.237001 1, 0xFFFF, sum = 0
6798 10:07:03.237072 2, 0xFFFF, sum = 0
6799 10:07:03.240442 3, 0xFFFF, sum = 0
6800 10:07:03.240521 4, 0xFFFF, sum = 0
6801 10:07:03.243612 5, 0xFFFF, sum = 0
6802 10:07:03.243703 6, 0xFFFF, sum = 0
6803 10:07:03.247124 7, 0xFFFF, sum = 0
6804 10:07:03.247220 8, 0xFFFF, sum = 0
6805 10:07:03.250116 9, 0xFFFF, sum = 0
6806 10:07:03.250215 10, 0xFFFF, sum = 0
6807 10:07:03.253579 11, 0xFFFF, sum = 0
6808 10:07:03.257000 12, 0xFFFF, sum = 0
6809 10:07:03.257080 13, 0x0, sum = 1
6810 10:07:03.257147 14, 0x0, sum = 2
6811 10:07:03.260283 15, 0x0, sum = 3
6812 10:07:03.260370 16, 0x0, sum = 4
6813 10:07:03.263835 best_step = 14
6814 10:07:03.263917
6815 10:07:03.263998 ==
6816 10:07:03.266982 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 10:07:03.270436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 10:07:03.270545 ==
6819 10:07:03.273395 RX Vref Scan: 1
6820 10:07:03.273475
6821 10:07:03.273564 RX Vref 0 -> 0, step: 1
6822 10:07:03.273638
6823 10:07:03.276741 RX Delay -311 -> 252, step: 8
6824 10:07:03.276842
6825 10:07:03.279983 Set Vref, RX VrefLevel [Byte0]: 50
6826 10:07:03.283679 [Byte1]: 50
6827 10:07:03.288286
6828 10:07:03.288388 Final RX Vref Byte 0 = 50 to rank0
6829 10:07:03.291516 Final RX Vref Byte 1 = 50 to rank0
6830 10:07:03.294980 Final RX Vref Byte 0 = 50 to rank1
6831 10:07:03.298320 Final RX Vref Byte 1 = 50 to rank1==
6832 10:07:03.301724 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 10:07:03.308246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 10:07:03.308332 ==
6835 10:07:03.308433 DQS Delay:
6836 10:07:03.311604 DQS0 = 32, DQS1 = 40
6837 10:07:03.311708 DQM Delay:
6838 10:07:03.311810 DQM0 = 10, DQM1 = 11
6839 10:07:03.314770 DQ Delay:
6840 10:07:03.318036 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6841 10:07:03.318116 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6842 10:07:03.321400 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6843 10:07:03.325010 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6844 10:07:03.325089
6845 10:07:03.328145
6846 10:07:03.334986 [DQSOSCAuto] RK0, (LSB)MR18= 0x95ce, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6847 10:07:03.337918 CH1 RK0: MR19=C0C, MR18=95CE
6848 10:07:03.344729 CH1_RK0: MR19=0xC0C, MR18=0x95CE, DQSOSC=384, MR23=63, INC=400, DEC=267
6849 10:07:03.344836 ==
6850 10:07:03.347928 Dram Type= 6, Freq= 0, CH_1, rank 1
6851 10:07:03.351521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 10:07:03.351601 ==
6853 10:07:03.354698 [Gating] SW mode calibration
6854 10:07:03.360966 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6855 10:07:03.367536 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6856 10:07:03.370830 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6857 10:07:03.374223 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6858 10:07:03.380672 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6859 10:07:03.384073 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6860 10:07:03.387713 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 10:07:03.394242 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 10:07:03.397314 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 10:07:03.400984 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 10:07:03.407280 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6865 10:07:03.407390 Total UI for P1: 0, mck2ui 16
6866 10:07:03.414286 best dqsien dly found for B0: ( 0, 14, 24)
6867 10:07:03.414368 Total UI for P1: 0, mck2ui 16
6868 10:07:03.420674 best dqsien dly found for B1: ( 0, 14, 24)
6869 10:07:03.423926 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6870 10:07:03.427097 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6871 10:07:03.427215
6872 10:07:03.430561 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6873 10:07:03.433709 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6874 10:07:03.437092 [Gating] SW calibration Done
6875 10:07:03.437184 ==
6876 10:07:03.440213 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 10:07:03.443835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 10:07:03.443913 ==
6879 10:07:03.447081 RX Vref Scan: 0
6880 10:07:03.447159
6881 10:07:03.447245 RX Vref 0 -> 0, step: 1
6882 10:07:03.447322
6883 10:07:03.450129 RX Delay -410 -> 252, step: 16
6884 10:07:03.456862 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6885 10:07:03.460401 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6886 10:07:03.463254 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6887 10:07:03.466885 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6888 10:07:03.473116 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6889 10:07:03.476624 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6890 10:07:03.480124 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6891 10:07:03.483051 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6892 10:07:03.489713 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6893 10:07:03.493137 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6894 10:07:03.496515 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6895 10:07:03.499638 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6896 10:07:03.506550 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6897 10:07:03.509603 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6898 10:07:03.512979 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6899 10:07:03.519306 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6900 10:07:03.519529 ==
6901 10:07:03.522914 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 10:07:03.526180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 10:07:03.526259 ==
6904 10:07:03.526330 DQS Delay:
6905 10:07:03.529356 DQS0 = 35, DQS1 = 35
6906 10:07:03.529438 DQM Delay:
6907 10:07:03.532571 DQM0 = 16, DQM1 = 12
6908 10:07:03.532673 DQ Delay:
6909 10:07:03.535980 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6910 10:07:03.539394 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6911 10:07:03.542660 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6912 10:07:03.545608 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =24
6913 10:07:03.545691
6914 10:07:03.545756
6915 10:07:03.545815 ==
6916 10:07:03.549260 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 10:07:03.552417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 10:07:03.552514 ==
6919 10:07:03.555425
6920 10:07:03.555495
6921 10:07:03.555555 TX Vref Scan disable
6922 10:07:03.558998 == TX Byte 0 ==
6923 10:07:03.562603 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6924 10:07:03.565445 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6925 10:07:03.568901 == TX Byte 1 ==
6926 10:07:03.572364 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6927 10:07:03.575788 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6928 10:07:03.575868 ==
6929 10:07:03.578994 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 10:07:03.581998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 10:07:03.582071 ==
6932 10:07:03.585509
6933 10:07:03.585639
6934 10:07:03.585726 TX Vref Scan disable
6935 10:07:03.588974 == TX Byte 0 ==
6936 10:07:03.592193 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6937 10:07:03.595418 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6938 10:07:03.598462 == TX Byte 1 ==
6939 10:07:03.602085 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6940 10:07:03.605296 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6941 10:07:03.605378
6942 10:07:03.605444 [DATLAT]
6943 10:07:03.608610 Freq=400, CH1 RK1
6944 10:07:03.608730
6945 10:07:03.611873 DATLAT Default: 0xe
6946 10:07:03.611983 0, 0xFFFF, sum = 0
6947 10:07:03.615107 1, 0xFFFF, sum = 0
6948 10:07:03.615191 2, 0xFFFF, sum = 0
6949 10:07:03.618538 3, 0xFFFF, sum = 0
6950 10:07:03.618622 4, 0xFFFF, sum = 0
6951 10:07:03.621653 5, 0xFFFF, sum = 0
6952 10:07:03.621767 6, 0xFFFF, sum = 0
6953 10:07:03.625060 7, 0xFFFF, sum = 0
6954 10:07:03.625144 8, 0xFFFF, sum = 0
6955 10:07:03.628621 9, 0xFFFF, sum = 0
6956 10:07:03.628732 10, 0xFFFF, sum = 0
6957 10:07:03.631623 11, 0xFFFF, sum = 0
6958 10:07:03.631764 12, 0xFFFF, sum = 0
6959 10:07:03.634856 13, 0x0, sum = 1
6960 10:07:03.634940 14, 0x0, sum = 2
6961 10:07:03.638385 15, 0x0, sum = 3
6962 10:07:03.638488 16, 0x0, sum = 4
6963 10:07:03.641553 best_step = 14
6964 10:07:03.641635
6965 10:07:03.641718 ==
6966 10:07:03.645097 Dram Type= 6, Freq= 0, CH_1, rank 1
6967 10:07:03.648095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6968 10:07:03.648178 ==
6969 10:07:03.651819 RX Vref Scan: 0
6970 10:07:03.651902
6971 10:07:03.651968 RX Vref 0 -> 0, step: 1
6972 10:07:03.652029
6973 10:07:03.654733 RX Delay -311 -> 252, step: 8
6974 10:07:03.662853 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6975 10:07:03.666047 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6976 10:07:03.669439 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6977 10:07:03.672675 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6978 10:07:03.679357 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6979 10:07:03.682535 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6980 10:07:03.685752 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6981 10:07:03.689410 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6982 10:07:03.696035 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6983 10:07:03.699403 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6984 10:07:03.702588 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6985 10:07:03.709231 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6986 10:07:03.712390 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6987 10:07:03.715378 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6988 10:07:03.719048 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6989 10:07:03.725810 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6990 10:07:03.725904 ==
6991 10:07:03.729094 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 10:07:03.732179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 10:07:03.732265 ==
6994 10:07:03.732332 DQS Delay:
6995 10:07:03.736022 DQS0 = 32, DQS1 = 36
6996 10:07:03.736107 DQM Delay:
6997 10:07:03.738986 DQM0 = 12, DQM1 = 11
6998 10:07:03.739071 DQ Delay:
6999 10:07:03.742386 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7000 10:07:03.745363 DQ4 =16, DQ5 =20, DQ6 =20, DQ7 =12
7001 10:07:03.748655 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7002 10:07:03.752213 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7003 10:07:03.752298
7004 10:07:03.752365
7005 10:07:03.758973 [DQSOSCAuto] RK1, (LSB)MR18= 0xa74f, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
7006 10:07:03.762207 CH1 RK1: MR19=C0C, MR18=A74F
7007 10:07:03.768383 CH1_RK1: MR19=0xC0C, MR18=0xA74F, DQSOSC=389, MR23=63, INC=390, DEC=260
7008 10:07:03.771619 [RxdqsGatingPostProcess] freq 400
7009 10:07:03.778324 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7010 10:07:03.781842 best DQS0 dly(2T, 0.5T) = (0, 10)
7011 10:07:03.784961 best DQS1 dly(2T, 0.5T) = (0, 10)
7012 10:07:03.788294 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7013 10:07:03.791836 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7014 10:07:03.791951 best DQS0 dly(2T, 0.5T) = (0, 10)
7015 10:07:03.795002 best DQS1 dly(2T, 0.5T) = (0, 10)
7016 10:07:03.798132 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7017 10:07:03.801659 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7018 10:07:03.804845 Pre-setting of DQS Precalculation
7019 10:07:03.811589 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7020 10:07:03.817811 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7021 10:07:03.824450 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7022 10:07:03.824553
7023 10:07:03.824645
7024 10:07:03.828006 [Calibration Summary] 800 Mbps
7025 10:07:03.828080 CH 0, Rank 0
7026 10:07:03.830932 SW Impedance : PASS
7027 10:07:03.834324 DUTY Scan : NO K
7028 10:07:03.834396 ZQ Calibration : PASS
7029 10:07:03.837750 Jitter Meter : NO K
7030 10:07:03.840944 CBT Training : PASS
7031 10:07:03.841046 Write leveling : PASS
7032 10:07:03.844460 RX DQS gating : PASS
7033 10:07:03.847955 RX DQ/DQS(RDDQC) : PASS
7034 10:07:03.848052 TX DQ/DQS : PASS
7035 10:07:03.851101 RX DATLAT : PASS
7036 10:07:03.854412 RX DQ/DQS(Engine): PASS
7037 10:07:03.854495 TX OE : NO K
7038 10:07:03.857433 All Pass.
7039 10:07:03.857515
7040 10:07:03.857580 CH 0, Rank 1
7041 10:07:03.860854 SW Impedance : PASS
7042 10:07:03.860940 DUTY Scan : NO K
7043 10:07:03.863951 ZQ Calibration : PASS
7044 10:07:03.867722 Jitter Meter : NO K
7045 10:07:03.867821 CBT Training : PASS
7046 10:07:03.870642 Write leveling : NO K
7047 10:07:03.874307 RX DQS gating : PASS
7048 10:07:03.874390 RX DQ/DQS(RDDQC) : PASS
7049 10:07:03.877321 TX DQ/DQS : PASS
7050 10:07:03.880577 RX DATLAT : PASS
7051 10:07:03.880659 RX DQ/DQS(Engine): PASS
7052 10:07:03.883740 TX OE : NO K
7053 10:07:03.883824 All Pass.
7054 10:07:03.883891
7055 10:07:03.887310 CH 1, Rank 0
7056 10:07:03.887395 SW Impedance : PASS
7057 10:07:03.890359 DUTY Scan : NO K
7058 10:07:03.893922 ZQ Calibration : PASS
7059 10:07:03.894005 Jitter Meter : NO K
7060 10:07:03.897416 CBT Training : PASS
7061 10:07:03.897498 Write leveling : PASS
7062 10:07:03.900405 RX DQS gating : PASS
7063 10:07:03.903858 RX DQ/DQS(RDDQC) : PASS
7064 10:07:03.903940 TX DQ/DQS : PASS
7065 10:07:03.906868 RX DATLAT : PASS
7066 10:07:03.910596 RX DQ/DQS(Engine): PASS
7067 10:07:03.910679 TX OE : NO K
7068 10:07:03.913774 All Pass.
7069 10:07:03.913856
7070 10:07:03.913921 CH 1, Rank 1
7071 10:07:03.916993 SW Impedance : PASS
7072 10:07:03.917078 DUTY Scan : NO K
7073 10:07:03.920571 ZQ Calibration : PASS
7074 10:07:03.923606 Jitter Meter : NO K
7075 10:07:03.923694 CBT Training : PASS
7076 10:07:03.927102 Write leveling : NO K
7077 10:07:03.930206 RX DQS gating : PASS
7078 10:07:03.930291 RX DQ/DQS(RDDQC) : PASS
7079 10:07:03.933456 TX DQ/DQS : PASS
7080 10:07:03.936982 RX DATLAT : PASS
7081 10:07:03.937067 RX DQ/DQS(Engine): PASS
7082 10:07:03.940040 TX OE : NO K
7083 10:07:03.940124 All Pass.
7084 10:07:03.940191
7085 10:07:03.943332 DramC Write-DBI off
7086 10:07:03.946859 PER_BANK_REFRESH: Hybrid Mode
7087 10:07:03.946945 TX_TRACKING: ON
7088 10:07:03.956618 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7089 10:07:03.959990 [FAST_K] Save calibration result to emmc
7090 10:07:03.963350 dramc_set_vcore_voltage set vcore to 725000
7091 10:07:03.966636 Read voltage for 1600, 0
7092 10:07:03.966734 Vio18 = 0
7093 10:07:03.966802 Vcore = 725000
7094 10:07:03.969676 Vdram = 0
7095 10:07:03.969761 Vddq = 0
7096 10:07:03.969829 Vmddr = 0
7097 10:07:03.976217 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7098 10:07:03.979752 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7099 10:07:03.983211 MEM_TYPE=3, freq_sel=13
7100 10:07:03.986303 sv_algorithm_assistance_LP4_3733
7101 10:07:03.989883 ============ PULL DRAM RESETB DOWN ============
7102 10:07:03.993012 ========== PULL DRAM RESETB DOWN end =========
7103 10:07:03.999631 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7104 10:07:04.002886 ===================================
7105 10:07:04.006407 LPDDR4 DRAM CONFIGURATION
7106 10:07:04.009487 ===================================
7107 10:07:04.009574 EX_ROW_EN[0] = 0x0
7108 10:07:04.013039 EX_ROW_EN[1] = 0x0
7109 10:07:04.013125 LP4Y_EN = 0x0
7110 10:07:04.016096 WORK_FSP = 0x1
7111 10:07:04.016181 WL = 0x5
7112 10:07:04.019731 RL = 0x5
7113 10:07:04.019816 BL = 0x2
7114 10:07:04.022960 RPST = 0x0
7115 10:07:04.023045 RD_PRE = 0x0
7116 10:07:04.025951 WR_PRE = 0x1
7117 10:07:04.026064 WR_PST = 0x1
7118 10:07:04.029410 DBI_WR = 0x0
7119 10:07:04.029495 DBI_RD = 0x0
7120 10:07:04.032571 OTF = 0x1
7121 10:07:04.035874 ===================================
7122 10:07:04.039419 ===================================
7123 10:07:04.039503 ANA top config
7124 10:07:04.042524 ===================================
7125 10:07:04.045816 DLL_ASYNC_EN = 0
7126 10:07:04.049241 ALL_SLAVE_EN = 0
7127 10:07:04.052683 NEW_RANK_MODE = 1
7128 10:07:04.056043 DLL_IDLE_MODE = 1
7129 10:07:04.056131 LP45_APHY_COMB_EN = 1
7130 10:07:04.059300 TX_ODT_DIS = 0
7131 10:07:04.062547 NEW_8X_MODE = 1
7132 10:07:04.065655 ===================================
7133 10:07:04.069308 ===================================
7134 10:07:04.072462 data_rate = 3200
7135 10:07:04.075663 CKR = 1
7136 10:07:04.075810 DQ_P2S_RATIO = 8
7137 10:07:04.078794 ===================================
7138 10:07:04.082268 CA_P2S_RATIO = 8
7139 10:07:04.085426 DQ_CA_OPEN = 0
7140 10:07:04.088786 DQ_SEMI_OPEN = 0
7141 10:07:04.091927 CA_SEMI_OPEN = 0
7142 10:07:04.095251 CA_FULL_RATE = 0
7143 10:07:04.095364 DQ_CKDIV4_EN = 0
7144 10:07:04.098366 CA_CKDIV4_EN = 0
7145 10:07:04.101987 CA_PREDIV_EN = 0
7146 10:07:04.105414 PH8_DLY = 12
7147 10:07:04.108428 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7148 10:07:04.111883 DQ_AAMCK_DIV = 4
7149 10:07:04.111989 CA_AAMCK_DIV = 4
7150 10:07:04.115315 CA_ADMCK_DIV = 4
7151 10:07:04.118589 DQ_TRACK_CA_EN = 0
7152 10:07:04.121625 CA_PICK = 1600
7153 10:07:04.125314 CA_MCKIO = 1600
7154 10:07:04.128252 MCKIO_SEMI = 0
7155 10:07:04.131864 PLL_FREQ = 3068
7156 10:07:04.134953 DQ_UI_PI_RATIO = 32
7157 10:07:04.135042 CA_UI_PI_RATIO = 0
7158 10:07:04.138548 ===================================
7159 10:07:04.141520 ===================================
7160 10:07:04.145168 memory_type:LPDDR4
7161 10:07:04.148313 GP_NUM : 10
7162 10:07:04.148427 SRAM_EN : 1
7163 10:07:04.151469 MD32_EN : 0
7164 10:07:04.154568 ===================================
7165 10:07:04.157910 [ANA_INIT] >>>>>>>>>>>>>>
7166 10:07:04.161306 <<<<<< [CONFIGURE PHASE]: ANA_TX
7167 10:07:04.164507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7168 10:07:04.167994 ===================================
7169 10:07:04.168106 data_rate = 3200,PCW = 0X7600
7170 10:07:04.171046 ===================================
7171 10:07:04.177814 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7172 10:07:04.180991 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7173 10:07:04.187565 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7174 10:07:04.191083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7175 10:07:04.194560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7176 10:07:04.197524 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7177 10:07:04.200666 [ANA_INIT] flow start
7178 10:07:04.204133 [ANA_INIT] PLL >>>>>>>>
7179 10:07:04.204249 [ANA_INIT] PLL <<<<<<<<
7180 10:07:04.207198 [ANA_INIT] MIDPI >>>>>>>>
7181 10:07:04.210548 [ANA_INIT] MIDPI <<<<<<<<
7182 10:07:04.210638 [ANA_INIT] DLL >>>>>>>>
7183 10:07:04.214249 [ANA_INIT] DLL <<<<<<<<
7184 10:07:04.217661 [ANA_INIT] flow end
7185 10:07:04.220425 ============ LP4 DIFF to SE enter ============
7186 10:07:04.223871 ============ LP4 DIFF to SE exit ============
7187 10:07:04.227060 [ANA_INIT] <<<<<<<<<<<<<
7188 10:07:04.230608 [Flow] Enable top DCM control >>>>>
7189 10:07:04.233957 [Flow] Enable top DCM control <<<<<
7190 10:07:04.237321 Enable DLL master slave shuffle
7191 10:07:04.240486 ==============================================================
7192 10:07:04.243805 Gating Mode config
7193 10:07:04.250558 ==============================================================
7194 10:07:04.250697 Config description:
7195 10:07:04.260577 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7196 10:07:04.266903 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7197 10:07:04.273746 SELPH_MODE 0: By rank 1: By Phase
7198 10:07:04.276857 ==============================================================
7199 10:07:04.280219 GAT_TRACK_EN = 1
7200 10:07:04.283420 RX_GATING_MODE = 2
7201 10:07:04.286946 RX_GATING_TRACK_MODE = 2
7202 10:07:04.290198 SELPH_MODE = 1
7203 10:07:04.293663 PICG_EARLY_EN = 1
7204 10:07:04.296622 VALID_LAT_VALUE = 1
7205 10:07:04.300147 ==============================================================
7206 10:07:04.303699 Enter into Gating configuration >>>>
7207 10:07:04.306772 Exit from Gating configuration <<<<
7208 10:07:04.310354 Enter into DVFS_PRE_config >>>>>
7209 10:07:04.323410 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7210 10:07:04.326865 Exit from DVFS_PRE_config <<<<<
7211 10:07:04.329891 Enter into PICG configuration >>>>
7212 10:07:04.333524 Exit from PICG configuration <<<<
7213 10:07:04.333614 [RX_INPUT] configuration >>>>>
7214 10:07:04.336515 [RX_INPUT] configuration <<<<<
7215 10:07:04.343138 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7216 10:07:04.346431 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7217 10:07:04.353370 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7218 10:07:04.359441 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7219 10:07:04.366096 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7220 10:07:04.372690 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7221 10:07:04.376120 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7222 10:07:04.379571 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7223 10:07:04.386065 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7224 10:07:04.389400 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7225 10:07:04.392451 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7226 10:07:04.395987 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7227 10:07:04.399153 ===================================
7228 10:07:04.402532 LPDDR4 DRAM CONFIGURATION
7229 10:07:04.405956 ===================================
7230 10:07:04.409114 EX_ROW_EN[0] = 0x0
7231 10:07:04.409227 EX_ROW_EN[1] = 0x0
7232 10:07:04.412333 LP4Y_EN = 0x0
7233 10:07:04.412439 WORK_FSP = 0x1
7234 10:07:04.415947 WL = 0x5
7235 10:07:04.416037 RL = 0x5
7236 10:07:04.419276 BL = 0x2
7237 10:07:04.419391 RPST = 0x0
7238 10:07:04.422387 RD_PRE = 0x0
7239 10:07:04.425896 WR_PRE = 0x1
7240 10:07:04.425985 WR_PST = 0x1
7241 10:07:04.429049 DBI_WR = 0x0
7242 10:07:04.429138 DBI_RD = 0x0
7243 10:07:04.432599 OTF = 0x1
7244 10:07:04.435733 ===================================
7245 10:07:04.438874 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7246 10:07:04.442356 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7247 10:07:04.445751 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7248 10:07:04.448763 ===================================
7249 10:07:04.452269 LPDDR4 DRAM CONFIGURATION
7250 10:07:04.455417 ===================================
7251 10:07:04.458849 EX_ROW_EN[0] = 0x10
7252 10:07:04.458973 EX_ROW_EN[1] = 0x0
7253 10:07:04.461935 LP4Y_EN = 0x0
7254 10:07:04.462030 WORK_FSP = 0x1
7255 10:07:04.465153 WL = 0x5
7256 10:07:04.465242 RL = 0x5
7257 10:07:04.468665 BL = 0x2
7258 10:07:04.468753 RPST = 0x0
7259 10:07:04.472314 RD_PRE = 0x0
7260 10:07:04.475244 WR_PRE = 0x1
7261 10:07:04.475362 WR_PST = 0x1
7262 10:07:04.478704 DBI_WR = 0x0
7263 10:07:04.478820 DBI_RD = 0x0
7264 10:07:04.481940 OTF = 0x1
7265 10:07:04.485283 ===================================
7266 10:07:04.488532 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7267 10:07:04.491658 ==
7268 10:07:04.495098 Dram Type= 6, Freq= 0, CH_0, rank 0
7269 10:07:04.498271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7270 10:07:04.498388 ==
7271 10:07:04.501499 [Duty_Offset_Calibration]
7272 10:07:04.501610 B0:2 B1:0 CA:1
7273 10:07:04.501726
7274 10:07:04.504927 [DutyScan_Calibration_Flow] k_type=0
7275 10:07:04.514106
7276 10:07:04.514223 ==CLK 0==
7277 10:07:04.517711 Final CLK duty delay cell = -4
7278 10:07:04.520718 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7279 10:07:04.524202 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7280 10:07:04.527247 [-4] AVG Duty = 4937%(X100)
7281 10:07:04.527380
7282 10:07:04.530759 CH0 CLK Duty spec in!! Max-Min= 187%
7283 10:07:04.533910 [DutyScan_Calibration_Flow] ====Done====
7284 10:07:04.534025
7285 10:07:04.537441 [DutyScan_Calibration_Flow] k_type=1
7286 10:07:04.553473
7287 10:07:04.553640 ==DQS 0 ==
7288 10:07:04.556842 Final DQS duty delay cell = 0
7289 10:07:04.560200 [0] MAX Duty = 5218%(X100), DQS PI = 32
7290 10:07:04.563461 [0] MIN Duty = 4969%(X100), DQS PI = 0
7291 10:07:04.567219 [0] AVG Duty = 5093%(X100)
7292 10:07:04.567340
7293 10:07:04.567442 ==DQS 1 ==
7294 10:07:04.570061 Final DQS duty delay cell = -4
7295 10:07:04.573674 [-4] MAX Duty = 5125%(X100), DQS PI = 44
7296 10:07:04.576720 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7297 10:07:04.580271 [-4] AVG Duty = 5000%(X100)
7298 10:07:04.580389
7299 10:07:04.583432 CH0 DQS 0 Duty spec in!! Max-Min= 249%
7300 10:07:04.583541
7301 10:07:04.586977 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7302 10:07:04.589970 [DutyScan_Calibration_Flow] ====Done====
7303 10:07:04.590085
7304 10:07:04.593041 [DutyScan_Calibration_Flow] k_type=3
7305 10:07:04.610101
7306 10:07:04.610274 ==DQM 0 ==
7307 10:07:04.613740 Final DQM duty delay cell = 0
7308 10:07:04.617043 [0] MAX Duty = 5124%(X100), DQS PI = 26
7309 10:07:04.620180 [0] MIN Duty = 4844%(X100), DQS PI = 0
7310 10:07:04.623608 [0] AVG Duty = 4984%(X100)
7311 10:07:04.623695
7312 10:07:04.623759 ==DQM 1 ==
7313 10:07:04.626892 Final DQM duty delay cell = -4
7314 10:07:04.630380 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7315 10:07:04.633510 [-4] MIN Duty = 4751%(X100), DQS PI = 10
7316 10:07:04.636681 [-4] AVG Duty = 4875%(X100)
7317 10:07:04.636810
7318 10:07:04.640144 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7319 10:07:04.640259
7320 10:07:04.643343 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7321 10:07:04.646932 [DutyScan_Calibration_Flow] ====Done====
7322 10:07:04.647020
7323 10:07:04.649955 [DutyScan_Calibration_Flow] k_type=2
7324 10:07:04.668096
7325 10:07:04.668249 ==DQ 0 ==
7326 10:07:04.671024 Final DQ duty delay cell = 0
7327 10:07:04.674661 [0] MAX Duty = 5156%(X100), DQS PI = 38
7328 10:07:04.677679 [0] MIN Duty = 5000%(X100), DQS PI = 0
7329 10:07:04.677797 [0] AVG Duty = 5078%(X100)
7330 10:07:04.680959
7331 10:07:04.681074 ==DQ 1 ==
7332 10:07:04.684060 Final DQ duty delay cell = 0
7333 10:07:04.687246 [0] MAX Duty = 4969%(X100), DQS PI = 44
7334 10:07:04.690662 [0] MIN Duty = 4875%(X100), DQS PI = 10
7335 10:07:04.690780 [0] AVG Duty = 4922%(X100)
7336 10:07:04.693817
7337 10:07:04.697497 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7338 10:07:04.697614
7339 10:07:04.700660 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7340 10:07:04.703984 [DutyScan_Calibration_Flow] ====Done====
7341 10:07:04.704107 ==
7342 10:07:04.707160 Dram Type= 6, Freq= 0, CH_1, rank 0
7343 10:07:04.710472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7344 10:07:04.710667 ==
7345 10:07:04.713752 [Duty_Offset_Calibration]
7346 10:07:04.713875 B0:0 B1:-1 CA:2
7347 10:07:04.713983
7348 10:07:04.716960 [DutyScan_Calibration_Flow] k_type=0
7349 10:07:04.727969
7350 10:07:04.728165 ==CLK 0==
7351 10:07:04.730959 Final CLK duty delay cell = 0
7352 10:07:04.734450 [0] MAX Duty = 5156%(X100), DQS PI = 10
7353 10:07:04.737536 [0] MIN Duty = 4906%(X100), DQS PI = 46
7354 10:07:04.741178 [0] AVG Duty = 5031%(X100)
7355 10:07:04.741285
7356 10:07:04.744359 CH1 CLK Duty spec in!! Max-Min= 250%
7357 10:07:04.747654 [DutyScan_Calibration_Flow] ====Done====
7358 10:07:04.747756
7359 10:07:04.750829 [DutyScan_Calibration_Flow] k_type=1
7360 10:07:04.767679
7361 10:07:04.767853 ==DQS 0 ==
7362 10:07:04.770754 Final DQS duty delay cell = 0
7363 10:07:04.774353 [0] MAX Duty = 5124%(X100), DQS PI = 26
7364 10:07:04.777370 [0] MIN Duty = 5000%(X100), DQS PI = 0
7365 10:07:04.780953 [0] AVG Duty = 5062%(X100)
7366 10:07:04.781043
7367 10:07:04.781110 ==DQS 1 ==
7368 10:07:04.784088 Final DQS duty delay cell = 0
7369 10:07:04.787155 [0] MAX Duty = 5187%(X100), DQS PI = 0
7370 10:07:04.790906 [0] MIN Duty = 4844%(X100), DQS PI = 32
7371 10:07:04.793849 [0] AVG Duty = 5015%(X100)
7372 10:07:04.793960
7373 10:07:04.797359 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7374 10:07:04.797462
7375 10:07:04.800198 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7376 10:07:04.803857 [DutyScan_Calibration_Flow] ====Done====
7377 10:07:04.803972
7378 10:07:04.806940 [DutyScan_Calibration_Flow] k_type=3
7379 10:07:04.824949
7380 10:07:04.825146 ==DQM 0 ==
7381 10:07:04.828464 Final DQM duty delay cell = 4
7382 10:07:04.831747 [4] MAX Duty = 5125%(X100), DQS PI = 22
7383 10:07:04.835132 [4] MIN Duty = 4969%(X100), DQS PI = 46
7384 10:07:04.838320 [4] AVG Duty = 5047%(X100)
7385 10:07:04.838415
7386 10:07:04.838503 ==DQM 1 ==
7387 10:07:04.842051 Final DQM duty delay cell = 0
7388 10:07:04.844911 [0] MAX Duty = 5281%(X100), DQS PI = 58
7389 10:07:04.848469 [0] MIN Duty = 4907%(X100), DQS PI = 34
7390 10:07:04.851597 [0] AVG Duty = 5094%(X100)
7391 10:07:04.851715
7392 10:07:04.855140 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7393 10:07:04.855233
7394 10:07:04.858453 CH1 DQM 1 Duty spec in!! Max-Min= 374%
7395 10:07:04.861478 [DutyScan_Calibration_Flow] ====Done====
7396 10:07:04.861576
7397 10:07:04.864841 [DutyScan_Calibration_Flow] k_type=2
7398 10:07:04.882005
7399 10:07:04.882167 ==DQ 0 ==
7400 10:07:04.885590 Final DQ duty delay cell = 0
7401 10:07:04.888663 [0] MAX Duty = 5093%(X100), DQS PI = 20
7402 10:07:04.891880 [0] MIN Duty = 4969%(X100), DQS PI = 0
7403 10:07:04.892000 [0] AVG Duty = 5031%(X100)
7404 10:07:04.895330
7405 10:07:04.895445 ==DQ 1 ==
7406 10:07:04.898538 Final DQ duty delay cell = 0
7407 10:07:04.901714 [0] MAX Duty = 5062%(X100), DQS PI = 0
7408 10:07:04.905024 [0] MIN Duty = 4813%(X100), DQS PI = 34
7409 10:07:04.905121 [0] AVG Duty = 4937%(X100)
7410 10:07:04.905194
7411 10:07:04.911972 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7412 10:07:04.912103
7413 10:07:04.915148 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7414 10:07:04.918411 [DutyScan_Calibration_Flow] ====Done====
7415 10:07:04.921567 nWR fixed to 30
7416 10:07:04.921666 [ModeRegInit_LP4] CH0 RK0
7417 10:07:04.924784 [ModeRegInit_LP4] CH0 RK1
7418 10:07:04.928091 [ModeRegInit_LP4] CH1 RK0
7419 10:07:04.931562 [ModeRegInit_LP4] CH1 RK1
7420 10:07:04.931672 match AC timing 5
7421 10:07:04.938127 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7422 10:07:04.941260 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7423 10:07:04.944752 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7424 10:07:04.951619 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7425 10:07:04.954833 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7426 10:07:04.954930 [MiockJmeterHQA]
7427 10:07:04.955000
7428 10:07:04.957958 [DramcMiockJmeter] u1RxGatingPI = 0
7429 10:07:04.961010 0 : 4366, 4137
7430 10:07:04.961109 4 : 4365, 4140
7431 10:07:04.964234 8 : 4255, 4029
7432 10:07:04.964326 12 : 4366, 4140
7433 10:07:04.967604 16 : 4252, 4027
7434 10:07:04.967695 20 : 4252, 4027
7435 10:07:04.967765 24 : 4253, 4026
7436 10:07:04.971040 28 : 4252, 4027
7437 10:07:04.971130 32 : 4363, 4137
7438 10:07:04.974171 36 : 4250, 4027
7439 10:07:04.974262 40 : 4252, 4027
7440 10:07:04.977606 44 : 4250, 4026
7441 10:07:04.977698 48 : 4255, 4030
7442 10:07:04.981103 52 : 4249, 4027
7443 10:07:04.981212 56 : 4361, 4137
7444 10:07:04.981318 60 : 4360, 4138
7445 10:07:04.984096 64 : 4252, 4029
7446 10:07:04.984187 68 : 4252, 4027
7447 10:07:04.987587 72 : 4249, 4027
7448 10:07:04.987679 76 : 4250, 4026
7449 10:07:04.990731 80 : 4252, 4030
7450 10:07:04.990811 84 : 4361, 4137
7451 10:07:04.994343 88 : 4250, 3641
7452 10:07:04.994432 92 : 4250, 0
7453 10:07:04.994499 96 : 4252, 0
7454 10:07:04.997486 100 : 4250, 0
7455 10:07:04.997579 104 : 4361, 0
7456 10:07:04.997652 108 : 4249, 0
7457 10:07:05.000583 112 : 4250, 0
7458 10:07:05.000662 116 : 4250, 0
7459 10:07:05.004075 120 : 4250, 0
7460 10:07:05.004154 124 : 4253, 0
7461 10:07:05.004219 128 : 4361, 0
7462 10:07:05.007186 132 : 4250, 0
7463 10:07:05.007280 136 : 4360, 0
7464 10:07:05.010895 140 : 4250, 0
7465 10:07:05.010987 144 : 4363, 0
7466 10:07:05.011057 148 : 4249, 0
7467 10:07:05.013861 152 : 4250, 0
7468 10:07:05.013951 156 : 4250, 0
7469 10:07:05.014021 160 : 4249, 0
7470 10:07:05.017441 164 : 4252, 0
7471 10:07:05.017535 168 : 4250, 0
7472 10:07:05.020799 172 : 4250, 0
7473 10:07:05.020892 176 : 4250, 0
7474 10:07:05.020962 180 : 4253, 0
7475 10:07:05.024132 184 : 4361, 0
7476 10:07:05.024222 188 : 4250, 0
7477 10:07:05.027334 192 : 4250, 0
7478 10:07:05.027459 196 : 4361, 0
7479 10:07:05.027569 200 : 4250, 2
7480 10:07:05.030536 204 : 4250, 2450
7481 10:07:05.030662 208 : 4363, 4140
7482 10:07:05.034039 212 : 4252, 4030
7483 10:07:05.034133 216 : 4250, 4027
7484 10:07:05.037002 220 : 4250, 4027
7485 10:07:05.037120 224 : 4252, 4030
7486 10:07:05.040488 228 : 4249, 4027
7487 10:07:05.040599 232 : 4250, 4026
7488 10:07:05.043684 236 : 4361, 4137
7489 10:07:05.043792 240 : 4250, 4027
7490 10:07:05.047182 244 : 4249, 4027
7491 10:07:05.047273 248 : 4360, 4137
7492 10:07:05.047344 252 : 4250, 4026
7493 10:07:05.050302 256 : 4250, 4027
7494 10:07:05.050418 260 : 4363, 4140
7495 10:07:05.053723 264 : 4249, 4027
7496 10:07:05.053843 268 : 4250, 4027
7497 10:07:05.056937 272 : 4250, 4027
7498 10:07:05.057058 276 : 4252, 4030
7499 10:07:05.060065 280 : 4250, 4027
7500 10:07:05.060197 284 : 4250, 4026
7501 10:07:05.063613 288 : 4361, 4137
7502 10:07:05.063742 292 : 4250, 4027
7503 10:07:05.067210 296 : 4251, 4027
7504 10:07:05.067326 300 : 4360, 4137
7505 10:07:05.070316 304 : 4250, 4026
7506 10:07:05.070410 308 : 4252, 4027
7507 10:07:05.073868 312 : 4363, 4002
7508 10:07:05.073962 316 : 4249, 2091
7509 10:07:05.074071
7510 10:07:05.077109 MIOCK jitter meter ch=0
7511 10:07:05.077202
7512 10:07:05.080111 1T = (316-92) = 224 dly cells
7513 10:07:05.083328 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7514 10:07:05.083453 ==
7515 10:07:05.086681 Dram Type= 6, Freq= 0, CH_0, rank 0
7516 10:07:05.093275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7517 10:07:05.093383 ==
7518 10:07:05.096724 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7519 10:07:05.103448 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7520 10:07:05.106414 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7521 10:07:05.113211 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7522 10:07:05.121045 [CA 0] Center 43 (13~73) winsize 61
7523 10:07:05.124045 [CA 1] Center 43 (13~73) winsize 61
7524 10:07:05.127442 [CA 2] Center 38 (8~68) winsize 61
7525 10:07:05.130819 [CA 3] Center 37 (8~67) winsize 60
7526 10:07:05.134154 [CA 4] Center 36 (6~66) winsize 61
7527 10:07:05.137153 [CA 5] Center 35 (5~65) winsize 61
7528 10:07:05.137239
7529 10:07:05.140489 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7530 10:07:05.140603
7531 10:07:05.143970 [CATrainingPosCal] consider 1 rank data
7532 10:07:05.147169 u2DelayCellTimex100 = 290/100 ps
7533 10:07:05.153841 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7534 10:07:05.156948 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7535 10:07:05.160473 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7536 10:07:05.163531 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7537 10:07:05.167077 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7538 10:07:05.170105 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7539 10:07:05.170186
7540 10:07:05.173615 CA PerBit enable=1, Macro0, CA PI delay=35
7541 10:07:05.173693
7542 10:07:05.176952 [CBTSetCACLKResult] CA Dly = 35
7543 10:07:05.180325 CS Dly: 9 (0~40)
7544 10:07:05.183519 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7545 10:07:05.186895 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7546 10:07:05.186978 ==
7547 10:07:05.190056 Dram Type= 6, Freq= 0, CH_0, rank 1
7548 10:07:05.196640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 10:07:05.196743 ==
7550 10:07:05.199895 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7551 10:07:05.206373 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7552 10:07:05.209903 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7553 10:07:05.216661 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7554 10:07:05.224312 [CA 0] Center 43 (13~73) winsize 61
7555 10:07:05.227380 [CA 1] Center 43 (13~73) winsize 61
7556 10:07:05.230739 [CA 2] Center 37 (8~67) winsize 60
7557 10:07:05.234171 [CA 3] Center 37 (8~67) winsize 60
7558 10:07:05.237543 [CA 4] Center 36 (6~66) winsize 61
7559 10:07:05.240679 [CA 5] Center 36 (6~66) winsize 61
7560 10:07:05.240820
7561 10:07:05.243780 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7562 10:07:05.243892
7563 10:07:05.247184 [CATrainingPosCal] consider 2 rank data
7564 10:07:05.250381 u2DelayCellTimex100 = 290/100 ps
7565 10:07:05.257380 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7566 10:07:05.260389 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7567 10:07:05.263913 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7568 10:07:05.267047 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7569 10:07:05.270187 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7570 10:07:05.273700 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7571 10:07:05.273799
7572 10:07:05.276726 CA PerBit enable=1, Macro0, CA PI delay=35
7573 10:07:05.276832
7574 10:07:05.280430 [CBTSetCACLKResult] CA Dly = 35
7575 10:07:05.283691 CS Dly: 10 (0~43)
7576 10:07:05.286821 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7577 10:07:05.289846 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7578 10:07:05.289935
7579 10:07:05.293642 ----->DramcWriteLeveling(PI) begin...
7580 10:07:05.293732 ==
7581 10:07:05.296575 Dram Type= 6, Freq= 0, CH_0, rank 0
7582 10:07:05.303271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 10:07:05.303372 ==
7584 10:07:05.306655 Write leveling (Byte 0): 37 => 37
7585 10:07:05.309961 Write leveling (Byte 1): 31 => 31
7586 10:07:05.310050 DramcWriteLeveling(PI) end<-----
7587 10:07:05.313205
7588 10:07:05.313292 ==
7589 10:07:05.316435 Dram Type= 6, Freq= 0, CH_0, rank 0
7590 10:07:05.319633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 10:07:05.319791 ==
7592 10:07:05.323102 [Gating] SW mode calibration
7593 10:07:05.329716 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7594 10:07:05.333303 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7595 10:07:05.339580 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 10:07:05.343129 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 10:07:05.346248 1 4 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7598 10:07:05.352729 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7599 10:07:05.356050 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7600 10:07:05.359465 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 10:07:05.366416 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 10:07:05.369337 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7603 10:07:05.372605 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7604 10:07:05.379202 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7605 10:07:05.382426 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
7606 10:07:05.385735 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7607 10:07:05.392323 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7608 10:07:05.395896 1 5 20 | B1->B0 | 2c2c 2323 | 1 0 | (0 1) (0 0)
7609 10:07:05.398913 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 10:07:05.405960 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 10:07:05.409154 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 10:07:05.412599 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 10:07:05.418767 1 6 8 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7614 10:07:05.422307 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7615 10:07:05.425697 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (1 1) (0 0)
7616 10:07:05.432214 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7617 10:07:05.435490 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 10:07:05.438871 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 10:07:05.445413 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 10:07:05.448560 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 10:07:05.452160 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 10:07:05.458795 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7623 10:07:05.461843 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7624 10:07:05.465023 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7625 10:07:05.471867 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 10:07:05.475055 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 10:07:05.478617 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 10:07:05.485220 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 10:07:05.488271 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 10:07:05.491625 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 10:07:05.498185 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 10:07:05.501376 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 10:07:05.504869 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 10:07:05.511319 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 10:07:05.515044 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 10:07:05.518335 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 10:07:05.524564 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7638 10:07:05.527963 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7639 10:07:05.531574 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7640 10:07:05.534573 Total UI for P1: 0, mck2ui 16
7641 10:07:05.537982 best dqsien dly found for B0: ( 1, 9, 10)
7642 10:07:05.544398 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7643 10:07:05.548183 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 10:07:05.551173 Total UI for P1: 0, mck2ui 16
7645 10:07:05.554138 best dqsien dly found for B1: ( 1, 9, 20)
7646 10:07:05.557698 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7647 10:07:05.561128 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7648 10:07:05.561267
7649 10:07:05.564235 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7650 10:07:05.567619 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7651 10:07:05.570840 [Gating] SW calibration Done
7652 10:07:05.570951 ==
7653 10:07:05.574084 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 10:07:05.580729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 10:07:05.580882 ==
7656 10:07:05.580984 RX Vref Scan: 0
7657 10:07:05.581094
7658 10:07:05.584094 RX Vref 0 -> 0, step: 1
7659 10:07:05.584200
7660 10:07:05.587134 RX Delay 0 -> 252, step: 8
7661 10:07:05.590707 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7662 10:07:05.593883 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7663 10:07:05.596972 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7664 10:07:05.600488 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7665 10:07:05.606936 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7666 10:07:05.610389 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7667 10:07:05.613924 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7668 10:07:05.616991 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7669 10:07:05.620185 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7670 10:07:05.626796 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7671 10:07:05.630242 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7672 10:07:05.633309 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7673 10:07:05.636845 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7674 10:07:05.640064 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7675 10:07:05.646521 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7676 10:07:05.649822 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7677 10:07:05.649952 ==
7678 10:07:05.653445 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 10:07:05.656493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 10:07:05.656611 ==
7681 10:07:05.659942 DQS Delay:
7682 10:07:05.660057 DQS0 = 0, DQS1 = 0
7683 10:07:05.663017 DQM Delay:
7684 10:07:05.663134 DQM0 = 138, DQM1 = 126
7685 10:07:05.663234 DQ Delay:
7686 10:07:05.666200 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7687 10:07:05.673189 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7688 10:07:05.676193 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7689 10:07:05.679315 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7690 10:07:05.679418
7691 10:07:05.679490
7692 10:07:05.679559 ==
7693 10:07:05.683026 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 10:07:05.685927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 10:07:05.686018 ==
7696 10:07:05.686083
7697 10:07:05.686144
7698 10:07:05.689399 TX Vref Scan disable
7699 10:07:05.692501 == TX Byte 0 ==
7700 10:07:05.695953 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7701 10:07:05.699127 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7702 10:07:05.702563 == TX Byte 1 ==
7703 10:07:05.705810 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7704 10:07:05.709334 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7705 10:07:05.709421 ==
7706 10:07:05.712427 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 10:07:05.719306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 10:07:05.719405 ==
7709 10:07:05.730843
7710 10:07:05.734291 TX Vref early break, caculate TX vref
7711 10:07:05.737524 TX Vref=16, minBit 6, minWin=22, winSum=379
7712 10:07:05.740572 TX Vref=18, minBit 6, minWin=23, winSum=389
7713 10:07:05.744191 TX Vref=20, minBit 6, minWin=23, winSum=394
7714 10:07:05.747213 TX Vref=22, minBit 0, minWin=25, winSum=409
7715 10:07:05.750700 TX Vref=24, minBit 0, minWin=25, winSum=417
7716 10:07:05.757277 TX Vref=26, minBit 12, minWin=25, winSum=428
7717 10:07:05.760592 TX Vref=28, minBit 2, minWin=26, winSum=430
7718 10:07:05.763861 TX Vref=30, minBit 0, minWin=25, winSum=421
7719 10:07:05.767223 TX Vref=32, minBit 7, minWin=24, winSum=408
7720 10:07:05.770349 TX Vref=34, minBit 1, minWin=24, winSum=397
7721 10:07:05.776780 [TxChooseVref] Worse bit 2, Min win 26, Win sum 430, Final Vref 28
7722 10:07:05.776907
7723 10:07:05.780038 Final TX Range 0 Vref 28
7724 10:07:05.780133
7725 10:07:05.780232 ==
7726 10:07:05.783641 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 10:07:05.786845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 10:07:05.786970 ==
7729 10:07:05.787070
7730 10:07:05.787170
7731 10:07:05.790248 TX Vref Scan disable
7732 10:07:05.797140 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7733 10:07:05.797266 == TX Byte 0 ==
7734 10:07:05.800041 u2DelayCellOfst[0]=13 cells (4 PI)
7735 10:07:05.803672 u2DelayCellOfst[1]=20 cells (6 PI)
7736 10:07:05.806645 u2DelayCellOfst[2]=13 cells (4 PI)
7737 10:07:05.809908 u2DelayCellOfst[3]=13 cells (4 PI)
7738 10:07:05.813436 u2DelayCellOfst[4]=10 cells (3 PI)
7739 10:07:05.816504 u2DelayCellOfst[5]=0 cells (0 PI)
7740 10:07:05.820329 u2DelayCellOfst[6]=20 cells (6 PI)
7741 10:07:05.823274 u2DelayCellOfst[7]=16 cells (5 PI)
7742 10:07:05.826439 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7743 10:07:05.829800 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7744 10:07:05.833036 == TX Byte 1 ==
7745 10:07:05.836290 u2DelayCellOfst[8]=0 cells (0 PI)
7746 10:07:05.839627 u2DelayCellOfst[9]=0 cells (0 PI)
7747 10:07:05.842810 u2DelayCellOfst[10]=3 cells (1 PI)
7748 10:07:05.842899 u2DelayCellOfst[11]=0 cells (0 PI)
7749 10:07:05.846227 u2DelayCellOfst[12]=6 cells (2 PI)
7750 10:07:05.849354 u2DelayCellOfst[13]=6 cells (2 PI)
7751 10:07:05.853015 u2DelayCellOfst[14]=10 cells (3 PI)
7752 10:07:05.856046 u2DelayCellOfst[15]=6 cells (2 PI)
7753 10:07:05.863074 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7754 10:07:05.866123 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7755 10:07:05.866226 DramC Write-DBI on
7756 10:07:05.866303 ==
7757 10:07:05.869494 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 10:07:05.876120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 10:07:05.876259 ==
7760 10:07:05.876379
7761 10:07:05.876473
7762 10:07:05.876564 TX Vref Scan disable
7763 10:07:05.880003 == TX Byte 0 ==
7764 10:07:05.883479 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7765 10:07:05.886457 == TX Byte 1 ==
7766 10:07:05.890018 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7767 10:07:05.893358 DramC Write-DBI off
7768 10:07:05.893466
7769 10:07:05.893538 [DATLAT]
7770 10:07:05.893601 Freq=1600, CH0 RK0
7771 10:07:05.893666
7772 10:07:05.896621 DATLAT Default: 0xf
7773 10:07:05.900054 0, 0xFFFF, sum = 0
7774 10:07:05.900139 1, 0xFFFF, sum = 0
7775 10:07:05.903033 2, 0xFFFF, sum = 0
7776 10:07:05.903146 3, 0xFFFF, sum = 0
7777 10:07:05.906317 4, 0xFFFF, sum = 0
7778 10:07:05.906399 5, 0xFFFF, sum = 0
7779 10:07:05.909684 6, 0xFFFF, sum = 0
7780 10:07:05.909771 7, 0xFFFF, sum = 0
7781 10:07:05.913093 8, 0xFFFF, sum = 0
7782 10:07:05.913174 9, 0xFFFF, sum = 0
7783 10:07:05.916437 10, 0xFFFF, sum = 0
7784 10:07:05.916542 11, 0xFFFF, sum = 0
7785 10:07:05.919846 12, 0xFFFF, sum = 0
7786 10:07:05.919940 13, 0xFFFF, sum = 0
7787 10:07:05.923153 14, 0x0, sum = 1
7788 10:07:05.923265 15, 0x0, sum = 2
7789 10:07:05.926720 16, 0x0, sum = 3
7790 10:07:05.926832 17, 0x0, sum = 4
7791 10:07:05.929656 best_step = 15
7792 10:07:05.929744
7793 10:07:05.929822 ==
7794 10:07:05.933164 Dram Type= 6, Freq= 0, CH_0, rank 0
7795 10:07:05.936377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7796 10:07:05.936497 ==
7797 10:07:05.939506 RX Vref Scan: 1
7798 10:07:05.939585
7799 10:07:05.939651 Set Vref Range= 24 -> 127
7800 10:07:05.939722
7801 10:07:05.942962 RX Vref 24 -> 127, step: 1
7802 10:07:05.943043
7803 10:07:05.946080 RX Delay 19 -> 252, step: 4
7804 10:07:05.946160
7805 10:07:05.949681 Set Vref, RX VrefLevel [Byte0]: 24
7806 10:07:05.952591 [Byte1]: 24
7807 10:07:05.952697
7808 10:07:05.955890 Set Vref, RX VrefLevel [Byte0]: 25
7809 10:07:05.959032 [Byte1]: 25
7810 10:07:05.962657
7811 10:07:05.962763 Set Vref, RX VrefLevel [Byte0]: 26
7812 10:07:05.966333 [Byte1]: 26
7813 10:07:05.970494
7814 10:07:05.970622 Set Vref, RX VrefLevel [Byte0]: 27
7815 10:07:05.973613 [Byte1]: 27
7816 10:07:05.978024
7817 10:07:05.978111 Set Vref, RX VrefLevel [Byte0]: 28
7818 10:07:05.981106 [Byte1]: 28
7819 10:07:05.985786
7820 10:07:05.985872 Set Vref, RX VrefLevel [Byte0]: 29
7821 10:07:05.988907 [Byte1]: 29
7822 10:07:05.993302
7823 10:07:05.993427 Set Vref, RX VrefLevel [Byte0]: 30
7824 10:07:05.996558 [Byte1]: 30
7825 10:07:06.000887
7826 10:07:06.001001 Set Vref, RX VrefLevel [Byte0]: 31
7827 10:07:06.004048 [Byte1]: 31
7828 10:07:06.008251
7829 10:07:06.008344 Set Vref, RX VrefLevel [Byte0]: 32
7830 10:07:06.011475 [Byte1]: 32
7831 10:07:06.015772
7832 10:07:06.019111 Set Vref, RX VrefLevel [Byte0]: 33
7833 10:07:06.022145 [Byte1]: 33
7834 10:07:06.022228
7835 10:07:06.025640 Set Vref, RX VrefLevel [Byte0]: 34
7836 10:07:06.028984 [Byte1]: 34
7837 10:07:06.029074
7838 10:07:06.032213 Set Vref, RX VrefLevel [Byte0]: 35
7839 10:07:06.035293 [Byte1]: 35
7840 10:07:06.035379
7841 10:07:06.038871 Set Vref, RX VrefLevel [Byte0]: 36
7842 10:07:06.042022 [Byte1]: 36
7843 10:07:06.046396
7844 10:07:06.046478 Set Vref, RX VrefLevel [Byte0]: 37
7845 10:07:06.049613 [Byte1]: 37
7846 10:07:06.053799
7847 10:07:06.053890 Set Vref, RX VrefLevel [Byte0]: 38
7848 10:07:06.056948 [Byte1]: 38
7849 10:07:06.061299
7850 10:07:06.061385 Set Vref, RX VrefLevel [Byte0]: 39
7851 10:07:06.064617 [Byte1]: 39
7852 10:07:06.069158
7853 10:07:06.069254 Set Vref, RX VrefLevel [Byte0]: 40
7854 10:07:06.072207 [Byte1]: 40
7855 10:07:06.076302
7856 10:07:06.076386 Set Vref, RX VrefLevel [Byte0]: 41
7857 10:07:06.079991 [Byte1]: 41
7858 10:07:06.084291
7859 10:07:06.084380 Set Vref, RX VrefLevel [Byte0]: 42
7860 10:07:06.087251 [Byte1]: 42
7861 10:07:06.091486
7862 10:07:06.091578 Set Vref, RX VrefLevel [Byte0]: 43
7863 10:07:06.095066 [Byte1]: 43
7864 10:07:06.099127
7865 10:07:06.099254 Set Vref, RX VrefLevel [Byte0]: 44
7866 10:07:06.102551 [Byte1]: 44
7867 10:07:06.106538
7868 10:07:06.106630 Set Vref, RX VrefLevel [Byte0]: 45
7869 10:07:06.110171 [Byte1]: 45
7870 10:07:06.114225
7871 10:07:06.117404 Set Vref, RX VrefLevel [Byte0]: 46
7872 10:07:06.117506 [Byte1]: 46
7873 10:07:06.121773
7874 10:07:06.121867 Set Vref, RX VrefLevel [Byte0]: 47
7875 10:07:06.125066 [Byte1]: 47
7876 10:07:06.129610
7877 10:07:06.129720 Set Vref, RX VrefLevel [Byte0]: 48
7878 10:07:06.132624 [Byte1]: 48
7879 10:07:06.136983
7880 10:07:06.137079 Set Vref, RX VrefLevel [Byte0]: 49
7881 10:07:06.140270 [Byte1]: 49
7882 10:07:06.144698
7883 10:07:06.144819 Set Vref, RX VrefLevel [Byte0]: 50
7884 10:07:06.150929 [Byte1]: 50
7885 10:07:06.151061
7886 10:07:06.154238 Set Vref, RX VrefLevel [Byte0]: 51
7887 10:07:06.157673 [Byte1]: 51
7888 10:07:06.157756
7889 10:07:06.160733 Set Vref, RX VrefLevel [Byte0]: 52
7890 10:07:06.164358 [Byte1]: 52
7891 10:07:06.164482
7892 10:07:06.167759 Set Vref, RX VrefLevel [Byte0]: 53
7893 10:07:06.171010 [Byte1]: 53
7894 10:07:06.174634
7895 10:07:06.174720 Set Vref, RX VrefLevel [Byte0]: 54
7896 10:07:06.178068 [Byte1]: 54
7897 10:07:06.182499
7898 10:07:06.182587 Set Vref, RX VrefLevel [Byte0]: 55
7899 10:07:06.185696 [Byte1]: 55
7900 10:07:06.189927
7901 10:07:06.190012 Set Vref, RX VrefLevel [Byte0]: 56
7902 10:07:06.193227 [Byte1]: 56
7903 10:07:06.197544
7904 10:07:06.197661 Set Vref, RX VrefLevel [Byte0]: 57
7905 10:07:06.201013 [Byte1]: 57
7906 10:07:06.205239
7907 10:07:06.205360 Set Vref, RX VrefLevel [Byte0]: 58
7908 10:07:06.208395 [Byte1]: 58
7909 10:07:06.212553
7910 10:07:06.212664 Set Vref, RX VrefLevel [Byte0]: 59
7911 10:07:06.215919 [Byte1]: 59
7912 10:07:06.220161
7913 10:07:06.220254 Set Vref, RX VrefLevel [Byte0]: 60
7914 10:07:06.223758 [Byte1]: 60
7915 10:07:06.227732
7916 10:07:06.227815 Set Vref, RX VrefLevel [Byte0]: 61
7917 10:07:06.231188 [Byte1]: 61
7918 10:07:06.235767
7919 10:07:06.235878 Set Vref, RX VrefLevel [Byte0]: 62
7920 10:07:06.238661 [Byte1]: 62
7921 10:07:06.243205
7922 10:07:06.243318 Set Vref, RX VrefLevel [Byte0]: 63
7923 10:07:06.246234 [Byte1]: 63
7924 10:07:06.250781
7925 10:07:06.250862 Set Vref, RX VrefLevel [Byte0]: 64
7926 10:07:06.253825 [Byte1]: 64
7927 10:07:06.258396
7928 10:07:06.258481 Set Vref, RX VrefLevel [Byte0]: 65
7929 10:07:06.261523 [Byte1]: 65
7930 10:07:06.265748
7931 10:07:06.265840 Set Vref, RX VrefLevel [Byte0]: 66
7932 10:07:06.269176 [Byte1]: 66
7933 10:07:06.273317
7934 10:07:06.273419 Set Vref, RX VrefLevel [Byte0]: 67
7935 10:07:06.276490 [Byte1]: 67
7936 10:07:06.280884
7937 10:07:06.280964 Set Vref, RX VrefLevel [Byte0]: 68
7938 10:07:06.284152 [Byte1]: 68
7939 10:07:06.288509
7940 10:07:06.288627 Set Vref, RX VrefLevel [Byte0]: 69
7941 10:07:06.291629 [Byte1]: 69
7942 10:07:06.295914
7943 10:07:06.296006 Set Vref, RX VrefLevel [Byte0]: 70
7944 10:07:06.299372 [Byte1]: 70
7945 10:07:06.303711
7946 10:07:06.303794 Set Vref, RX VrefLevel [Byte0]: 71
7947 10:07:06.306694 [Byte1]: 71
7948 10:07:06.311090
7949 10:07:06.311196 Set Vref, RX VrefLevel [Byte0]: 72
7950 10:07:06.314689 [Byte1]: 72
7951 10:07:06.318906
7952 10:07:06.318989 Set Vref, RX VrefLevel [Byte0]: 73
7953 10:07:06.322137 [Byte1]: 73
7954 10:07:06.326395
7955 10:07:06.326482 Set Vref, RX VrefLevel [Byte0]: 74
7956 10:07:06.329592 [Byte1]: 74
7957 10:07:06.333734
7958 10:07:06.333816 Set Vref, RX VrefLevel [Byte0]: 75
7959 10:07:06.337427 [Byte1]: 75
7960 10:07:06.341850
7961 10:07:06.341941 Set Vref, RX VrefLevel [Byte0]: 76
7962 10:07:06.344776 [Byte1]: 76
7963 10:07:06.349120
7964 10:07:06.349203 Set Vref, RX VrefLevel [Byte0]: 77
7965 10:07:06.352156 [Byte1]: 77
7966 10:07:06.356745
7967 10:07:06.356832 Set Vref, RX VrefLevel [Byte0]: 78
7968 10:07:06.359823 [Byte1]: 78
7969 10:07:06.364172
7970 10:07:06.364273 Set Vref, RX VrefLevel [Byte0]: 79
7971 10:07:06.367240 [Byte1]: 79
7972 10:07:06.371699
7973 10:07:06.371792 Set Vref, RX VrefLevel [Byte0]: 80
7974 10:07:06.375142 [Byte1]: 80
7975 10:07:06.379103
7976 10:07:06.382577 Final RX Vref Byte 0 = 63 to rank0
7977 10:07:06.382669 Final RX Vref Byte 1 = 62 to rank0
7978 10:07:06.385671 Final RX Vref Byte 0 = 63 to rank1
7979 10:07:06.388957 Final RX Vref Byte 1 = 62 to rank1==
7980 10:07:06.392499 Dram Type= 6, Freq= 0, CH_0, rank 0
7981 10:07:06.398797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7982 10:07:06.398899 ==
7983 10:07:06.398970 DQS Delay:
7984 10:07:06.402185 DQS0 = 0, DQS1 = 0
7985 10:07:06.402261 DQM Delay:
7986 10:07:06.405509 DQM0 = 136, DQM1 = 124
7987 10:07:06.405588 DQ Delay:
7988 10:07:06.409005 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =134
7989 10:07:06.411993 DQ4 =140, DQ5 =126, DQ6 =144, DQ7 =142
7990 10:07:06.415579 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =118
7991 10:07:06.418759 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =132
7992 10:07:06.418841
7993 10:07:06.418907
7994 10:07:06.418984
7995 10:07:06.422053 [DramC_TX_OE_Calibration] TA2
7996 10:07:06.425379 Original DQ_B0 (3 6) =30, OEN = 27
7997 10:07:06.428962 Original DQ_B1 (3 6) =30, OEN = 27
7998 10:07:06.431964 24, 0x0, End_B0=24 End_B1=24
7999 10:07:06.435199 25, 0x0, End_B0=25 End_B1=25
8000 10:07:06.435317 26, 0x0, End_B0=26 End_B1=26
8001 10:07:06.438807 27, 0x0, End_B0=27 End_B1=27
8002 10:07:06.442046 28, 0x0, End_B0=28 End_B1=28
8003 10:07:06.445160 29, 0x0, End_B0=29 End_B1=29
8004 10:07:06.445260 30, 0x0, End_B0=30 End_B1=30
8005 10:07:06.448243 31, 0x5151, End_B0=30 End_B1=30
8006 10:07:06.451586 Byte0 end_step=30 best_step=27
8007 10:07:06.455178 Byte1 end_step=30 best_step=27
8008 10:07:06.458609 Byte0 TX OE(2T, 0.5T) = (3, 3)
8009 10:07:06.461927 Byte1 TX OE(2T, 0.5T) = (3, 3)
8010 10:07:06.462043
8011 10:07:06.462142
8012 10:07:06.468146 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
8013 10:07:06.471743 CH0 RK0: MR19=303, MR18=1C1A
8014 10:07:06.478316 CH0_RK0: MR19=0x303, MR18=0x1C1A, DQSOSC=395, MR23=63, INC=23, DEC=15
8015 10:07:06.478472
8016 10:07:06.481571 ----->DramcWriteLeveling(PI) begin...
8017 10:07:06.481668 ==
8018 10:07:06.484601 Dram Type= 6, Freq= 0, CH_0, rank 1
8019 10:07:06.488278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8020 10:07:06.488372 ==
8021 10:07:06.491573 Write leveling (Byte 0): 37 => 37
8022 10:07:06.494577 Write leveling (Byte 1): 31 => 31
8023 10:07:06.498279 DramcWriteLeveling(PI) end<-----
8024 10:07:06.498376
8025 10:07:06.498445 ==
8026 10:07:06.501330 Dram Type= 6, Freq= 0, CH_0, rank 1
8027 10:07:06.504655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8028 10:07:06.507802 ==
8029 10:07:06.507896 [Gating] SW mode calibration
8030 10:07:06.518170 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8031 10:07:06.521224 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8032 10:07:06.524155 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 10:07:06.530910 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 10:07:06.534114 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
8035 10:07:06.537739 1 4 12 | B1->B0 | 2727 3030 | 1 0 | (1 1) (0 0)
8036 10:07:06.544468 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 10:07:06.547619 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 10:07:06.551137 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8039 10:07:06.557445 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8040 10:07:06.560592 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 10:07:06.564048 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8042 10:07:06.570664 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8043 10:07:06.573789 1 5 12 | B1->B0 | 3232 2525 | 1 0 | (1 0) (1 0)
8044 10:07:06.577239 1 5 16 | B1->B0 | 2727 2323 | 0 0 | (0 1) (0 0)
8045 10:07:06.583483 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 10:07:06.586806 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 10:07:06.590396 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 10:07:06.596925 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 10:07:06.600476 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 10:07:06.603497 1 6 8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8051 10:07:06.609978 1 6 12 | B1->B0 | 2f2f 4343 | 0 0 | (0 0) (0 0)
8052 10:07:06.613139 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8053 10:07:06.616555 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 10:07:06.622964 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 10:07:06.626407 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 10:07:06.629562 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 10:07:06.636239 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 10:07:06.639623 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 10:07:06.642838 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8060 10:07:06.649361 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8061 10:07:06.653163 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 10:07:06.656162 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 10:07:06.662802 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 10:07:06.666447 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 10:07:06.669585 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 10:07:06.676189 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 10:07:06.679142 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 10:07:06.682692 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 10:07:06.689191 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 10:07:06.692324 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 10:07:06.695999 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 10:07:06.702338 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 10:07:06.705899 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 10:07:06.709035 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8075 10:07:06.715905 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8076 10:07:06.718922 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 10:07:06.722389 Total UI for P1: 0, mck2ui 16
8078 10:07:06.725619 best dqsien dly found for B0: ( 1, 9, 10)
8079 10:07:06.728953 Total UI for P1: 0, mck2ui 16
8080 10:07:06.732342 best dqsien dly found for B1: ( 1, 9, 14)
8081 10:07:06.735957 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8082 10:07:06.739029 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8083 10:07:06.739117
8084 10:07:06.742059 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8085 10:07:06.745756 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8086 10:07:06.748786 [Gating] SW calibration Done
8087 10:07:06.748882 ==
8088 10:07:06.752134 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 10:07:06.758711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 10:07:06.758817 ==
8091 10:07:06.758889 RX Vref Scan: 0
8092 10:07:06.758973
8093 10:07:06.762007 RX Vref 0 -> 0, step: 1
8094 10:07:06.762090
8095 10:07:06.765468 RX Delay 0 -> 252, step: 8
8096 10:07:06.768836 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8097 10:07:06.771957 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8098 10:07:06.775178 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8099 10:07:06.778598 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8100 10:07:06.784889 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8101 10:07:06.788379 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8102 10:07:06.791879 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8103 10:07:06.795100 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8104 10:07:06.798307 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8105 10:07:06.804892 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8106 10:07:06.808352 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8107 10:07:06.811581 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8108 10:07:06.814672 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8109 10:07:06.821767 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8110 10:07:06.824866 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8111 10:07:06.828244 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8112 10:07:06.828343 ==
8113 10:07:06.831409 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 10:07:06.834902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 10:07:06.834983 ==
8116 10:07:06.838154 DQS Delay:
8117 10:07:06.838232 DQS0 = 0, DQS1 = 0
8118 10:07:06.841182 DQM Delay:
8119 10:07:06.841289 DQM0 = 136, DQM1 = 125
8120 10:07:06.841403 DQ Delay:
8121 10:07:06.848125 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8122 10:07:06.851313 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8123 10:07:06.854385 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
8124 10:07:06.857966 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8125 10:07:06.858050
8126 10:07:06.858122
8127 10:07:06.858183 ==
8128 10:07:06.861376 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 10:07:06.864428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 10:07:06.864576 ==
8131 10:07:06.864677
8132 10:07:06.864780
8133 10:07:06.867913 TX Vref Scan disable
8134 10:07:06.871108 == TX Byte 0 ==
8135 10:07:06.874597 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8136 10:07:06.877560 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8137 10:07:06.881002 == TX Byte 1 ==
8138 10:07:06.884608 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8139 10:07:06.887683 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8140 10:07:06.887776 ==
8141 10:07:06.890700 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 10:07:06.897573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 10:07:06.897678 ==
8144 10:07:06.909320
8145 10:07:06.912668 TX Vref early break, caculate TX vref
8146 10:07:06.916359 TX Vref=16, minBit 1, minWin=23, winSum=392
8147 10:07:06.919403 TX Vref=18, minBit 0, minWin=24, winSum=400
8148 10:07:06.922654 TX Vref=20, minBit 3, minWin=24, winSum=407
8149 10:07:06.926187 TX Vref=22, minBit 0, minWin=25, winSum=416
8150 10:07:06.929356 TX Vref=24, minBit 0, minWin=25, winSum=420
8151 10:07:06.936008 TX Vref=26, minBit 0, minWin=26, winSum=428
8152 10:07:06.939240 TX Vref=28, minBit 1, minWin=26, winSum=427
8153 10:07:06.942370 TX Vref=30, minBit 0, minWin=25, winSum=422
8154 10:07:06.945861 TX Vref=32, minBit 0, minWin=25, winSum=410
8155 10:07:06.949402 TX Vref=34, minBit 0, minWin=24, winSum=402
8156 10:07:06.955673 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 26
8157 10:07:06.955839
8158 10:07:06.958729 Final TX Range 0 Vref 26
8159 10:07:06.958818
8160 10:07:06.958886 ==
8161 10:07:06.962248 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 10:07:06.965917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 10:07:06.966019 ==
8164 10:07:06.966120
8165 10:07:06.966187
8166 10:07:06.968762 TX Vref Scan disable
8167 10:07:06.975322 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8168 10:07:06.975429 == TX Byte 0 ==
8169 10:07:06.979004 u2DelayCellOfst[0]=13 cells (4 PI)
8170 10:07:06.982171 u2DelayCellOfst[1]=20 cells (6 PI)
8171 10:07:06.985355 u2DelayCellOfst[2]=13 cells (4 PI)
8172 10:07:06.988566 u2DelayCellOfst[3]=13 cells (4 PI)
8173 10:07:06.992134 u2DelayCellOfst[4]=10 cells (3 PI)
8174 10:07:06.995268 u2DelayCellOfst[5]=0 cells (0 PI)
8175 10:07:06.998805 u2DelayCellOfst[6]=20 cells (6 PI)
8176 10:07:07.001729 u2DelayCellOfst[7]=20 cells (6 PI)
8177 10:07:07.005221 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8178 10:07:07.008312 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8179 10:07:07.011708 == TX Byte 1 ==
8180 10:07:07.015255 u2DelayCellOfst[8]=3 cells (1 PI)
8181 10:07:07.018211 u2DelayCellOfst[9]=0 cells (0 PI)
8182 10:07:07.021803 u2DelayCellOfst[10]=6 cells (2 PI)
8183 10:07:07.021944 u2DelayCellOfst[11]=3 cells (1 PI)
8184 10:07:07.025073 u2DelayCellOfst[12]=13 cells (4 PI)
8185 10:07:07.028048 u2DelayCellOfst[13]=13 cells (4 PI)
8186 10:07:07.031617 u2DelayCellOfst[14]=16 cells (5 PI)
8187 10:07:07.034610 u2DelayCellOfst[15]=10 cells (3 PI)
8188 10:07:07.041513 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8189 10:07:07.044597 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8190 10:07:07.044717 DramC Write-DBI on
8191 10:07:07.047699 ==
8192 10:07:07.051407 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 10:07:07.054451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 10:07:07.054542 ==
8195 10:07:07.054609
8196 10:07:07.054670
8197 10:07:07.057842 TX Vref Scan disable
8198 10:07:07.057929 == TX Byte 0 ==
8199 10:07:07.064558 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8200 10:07:07.064712 == TX Byte 1 ==
8201 10:07:07.067638 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8202 10:07:07.071117 DramC Write-DBI off
8203 10:07:07.071217
8204 10:07:07.071304 [DATLAT]
8205 10:07:07.074324 Freq=1600, CH0 RK1
8206 10:07:07.074414
8207 10:07:07.074509 DATLAT Default: 0xf
8208 10:07:07.077627 0, 0xFFFF, sum = 0
8209 10:07:07.077710 1, 0xFFFF, sum = 0
8210 10:07:07.080897 2, 0xFFFF, sum = 0
8211 10:07:07.080991 3, 0xFFFF, sum = 0
8212 10:07:07.084169 4, 0xFFFF, sum = 0
8213 10:07:07.084275 5, 0xFFFF, sum = 0
8214 10:07:07.087844 6, 0xFFFF, sum = 0
8215 10:07:07.087926 7, 0xFFFF, sum = 0
8216 10:07:07.090889 8, 0xFFFF, sum = 0
8217 10:07:07.094312 9, 0xFFFF, sum = 0
8218 10:07:07.094493 10, 0xFFFF, sum = 0
8219 10:07:07.097470 11, 0xFFFF, sum = 0
8220 10:07:07.097619 12, 0xFFFF, sum = 0
8221 10:07:07.100943 13, 0xFFFF, sum = 0
8222 10:07:07.101031 14, 0x0, sum = 1
8223 10:07:07.104121 15, 0x0, sum = 2
8224 10:07:07.104255 16, 0x0, sum = 3
8225 10:07:07.107714 17, 0x0, sum = 4
8226 10:07:07.107803 best_step = 15
8227 10:07:07.107926
8228 10:07:07.108004 ==
8229 10:07:07.110893 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 10:07:07.114093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 10:07:07.114184 ==
8232 10:07:07.117528 RX Vref Scan: 0
8233 10:07:07.117620
8234 10:07:07.120693 RX Vref 0 -> 0, step: 1
8235 10:07:07.120801
8236 10:07:07.120871 RX Delay 11 -> 252, step: 4
8237 10:07:07.127718 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8238 10:07:07.131200 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8239 10:07:07.134173 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8240 10:07:07.137608 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8241 10:07:07.140815 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8242 10:07:07.147495 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8243 10:07:07.151036 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8244 10:07:07.154140 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8245 10:07:07.157682 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8246 10:07:07.160879 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8247 10:07:07.167685 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8248 10:07:07.171126 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8249 10:07:07.174177 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8250 10:07:07.177608 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8251 10:07:07.183869 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8252 10:07:07.187536 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8253 10:07:07.187671 ==
8254 10:07:07.190785 Dram Type= 6, Freq= 0, CH_0, rank 1
8255 10:07:07.194080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8256 10:07:07.194167 ==
8257 10:07:07.197337 DQS Delay:
8258 10:07:07.197416 DQS0 = 0, DQS1 = 0
8259 10:07:07.197481 DQM Delay:
8260 10:07:07.200429 DQM0 = 133, DQM1 = 123
8261 10:07:07.200547 DQ Delay:
8262 10:07:07.203673 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8263 10:07:07.207024 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8264 10:07:07.210379 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8265 10:07:07.217013 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8266 10:07:07.217122
8267 10:07:07.217193
8268 10:07:07.217255
8269 10:07:07.220266 [DramC_TX_OE_Calibration] TA2
8270 10:07:07.223955 Original DQ_B0 (3 6) =30, OEN = 27
8271 10:07:07.224037 Original DQ_B1 (3 6) =30, OEN = 27
8272 10:07:07.226904 24, 0x0, End_B0=24 End_B1=24
8273 10:07:07.230448 25, 0x0, End_B0=25 End_B1=25
8274 10:07:07.233468 26, 0x0, End_B0=26 End_B1=26
8275 10:07:07.236958 27, 0x0, End_B0=27 End_B1=27
8276 10:07:07.237049 28, 0x0, End_B0=28 End_B1=28
8277 10:07:07.240425 29, 0x0, End_B0=29 End_B1=29
8278 10:07:07.243362 30, 0x0, End_B0=30 End_B1=30
8279 10:07:07.246603 31, 0x4141, End_B0=30 End_B1=30
8280 10:07:07.250144 Byte0 end_step=30 best_step=27
8281 10:07:07.253406 Byte1 end_step=30 best_step=27
8282 10:07:07.253525 Byte0 TX OE(2T, 0.5T) = (3, 3)
8283 10:07:07.256785 Byte1 TX OE(2T, 0.5T) = (3, 3)
8284 10:07:07.256866
8285 10:07:07.256932
8286 10:07:07.266850 [DQSOSCAuto] RK1, (LSB)MR18= 0x2310, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8287 10:07:07.270061 CH0 RK1: MR19=303, MR18=2310
8288 10:07:07.273024 CH0_RK1: MR19=0x303, MR18=0x2310, DQSOSC=392, MR23=63, INC=24, DEC=16
8289 10:07:07.276363 [RxdqsGatingPostProcess] freq 1600
8290 10:07:07.282983 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8291 10:07:07.286526 best DQS0 dly(2T, 0.5T) = (1, 1)
8292 10:07:07.289682 best DQS1 dly(2T, 0.5T) = (1, 1)
8293 10:07:07.293175 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8294 10:07:07.296198 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8295 10:07:07.300066 best DQS0 dly(2T, 0.5T) = (1, 1)
8296 10:07:07.300194 best DQS1 dly(2T, 0.5T) = (1, 1)
8297 10:07:07.303062 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8298 10:07:07.306387 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8299 10:07:07.309526 Pre-setting of DQS Precalculation
8300 10:07:07.316421 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8301 10:07:07.316553 ==
8302 10:07:07.319528 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 10:07:07.323054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 10:07:07.323157 ==
8305 10:07:07.329615 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8306 10:07:07.332561 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8307 10:07:07.336074 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8308 10:07:07.342532 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8309 10:07:07.351960 [CA 0] Center 40 (11~70) winsize 60
8310 10:07:07.355406 [CA 1] Center 41 (11~71) winsize 61
8311 10:07:07.358513 [CA 2] Center 37 (8~67) winsize 60
8312 10:07:07.361764 [CA 3] Center 36 (7~66) winsize 60
8313 10:07:07.365296 [CA 4] Center 36 (7~66) winsize 60
8314 10:07:07.368364 [CA 5] Center 36 (6~66) winsize 61
8315 10:07:07.368505
8316 10:07:07.372105 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8317 10:07:07.372216
8318 10:07:07.375023 [CATrainingPosCal] consider 1 rank data
8319 10:07:07.378563 u2DelayCellTimex100 = 290/100 ps
8320 10:07:07.385226 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8321 10:07:07.388363 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8322 10:07:07.391555 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8323 10:07:07.394850 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8324 10:07:07.398237 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8325 10:07:07.401398 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8326 10:07:07.401495
8327 10:07:07.405205 CA PerBit enable=1, Macro0, CA PI delay=36
8328 10:07:07.405327
8329 10:07:07.408033 [CBTSetCACLKResult] CA Dly = 36
8330 10:07:07.411309 CS Dly: 9 (0~40)
8331 10:07:07.414455 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8332 10:07:07.417960 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8333 10:07:07.418049 ==
8334 10:07:07.421488 Dram Type= 6, Freq= 0, CH_1, rank 1
8335 10:07:07.427872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 10:07:07.427976 ==
8337 10:07:07.431366 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8338 10:07:07.437608 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8339 10:07:07.440972 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8340 10:07:07.447623 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8341 10:07:07.455036 [CA 0] Center 42 (13~72) winsize 60
8342 10:07:07.458494 [CA 1] Center 42 (13~72) winsize 60
8343 10:07:07.461820 [CA 2] Center 39 (9~69) winsize 61
8344 10:07:07.465365 [CA 3] Center 37 (8~67) winsize 60
8345 10:07:07.468357 [CA 4] Center 38 (9~68) winsize 60
8346 10:07:07.471807 [CA 5] Center 37 (8~67) winsize 60
8347 10:07:07.471894
8348 10:07:07.475085 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8349 10:07:07.475173
8350 10:07:07.478150 [CATrainingPosCal] consider 2 rank data
8351 10:07:07.481807 u2DelayCellTimex100 = 290/100 ps
8352 10:07:07.484763 CA0 delay=41 (13~70),Diff = 4 PI (13 cell)
8353 10:07:07.491488 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8354 10:07:07.494989 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8355 10:07:07.498098 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8356 10:07:07.501758 CA4 delay=37 (9~66),Diff = 0 PI (0 cell)
8357 10:07:07.504584 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8358 10:07:07.504677
8359 10:07:07.508332 CA PerBit enable=1, Macro0, CA PI delay=37
8360 10:07:07.508426
8361 10:07:07.511275 [CBTSetCACLKResult] CA Dly = 37
8362 10:07:07.515002 CS Dly: 9 (0~41)
8363 10:07:07.518309 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8364 10:07:07.521389 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8365 10:07:07.521493
8366 10:07:07.524639 ----->DramcWriteLeveling(PI) begin...
8367 10:07:07.524753 ==
8368 10:07:07.527913 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 10:07:07.534557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 10:07:07.534701 ==
8371 10:07:07.537998 Write leveling (Byte 0): 25 => 25
8372 10:07:07.538108 Write leveling (Byte 1): 28 => 28
8373 10:07:07.541066 DramcWriteLeveling(PI) end<-----
8374 10:07:07.541144
8375 10:07:07.541208 ==
8376 10:07:07.544485 Dram Type= 6, Freq= 0, CH_1, rank 0
8377 10:07:07.551296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8378 10:07:07.551535 ==
8379 10:07:07.554369 [Gating] SW mode calibration
8380 10:07:07.561183 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8381 10:07:07.564355 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8382 10:07:07.571167 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 10:07:07.574256 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 10:07:07.577442 1 4 8 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (1 1)
8385 10:07:07.584344 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 10:07:07.587303 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 10:07:07.590807 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 10:07:07.597593 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 10:07:07.600626 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 10:07:07.603689 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 10:07:07.610407 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 10:07:07.614070 1 5 8 | B1->B0 | 2d2d 2828 | 0 0 | (0 0) (1 0)
8393 10:07:07.617322 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8394 10:07:07.623619 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8395 10:07:07.626824 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 10:07:07.630397 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 10:07:07.636933 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 10:07:07.640441 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 10:07:07.643615 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 10:07:07.650239 1 6 8 | B1->B0 | 3434 4343 | 0 0 | (0 0) (0 0)
8401 10:07:07.653608 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 10:07:07.656690 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 10:07:07.663490 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 10:07:07.666726 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 10:07:07.669973 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 10:07:07.676653 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 10:07:07.680069 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8408 10:07:07.683495 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8409 10:07:07.689672 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8410 10:07:07.693199 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 10:07:07.696365 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 10:07:07.703209 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 10:07:07.706381 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 10:07:07.710033 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 10:07:07.716445 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 10:07:07.720241 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 10:07:07.723326 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 10:07:07.729408 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 10:07:07.732604 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 10:07:07.736282 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 10:07:07.742543 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 10:07:07.746204 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 10:07:07.749180 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 10:07:07.756027 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8425 10:07:07.759167 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8426 10:07:07.762805 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 10:07:07.765890 Total UI for P1: 0, mck2ui 16
8428 10:07:07.769355 best dqsien dly found for B0: ( 1, 9, 10)
8429 10:07:07.772497 Total UI for P1: 0, mck2ui 16
8430 10:07:07.775699 best dqsien dly found for B1: ( 1, 9, 10)
8431 10:07:07.779147 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8432 10:07:07.782745 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8433 10:07:07.782885
8434 10:07:07.786009 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8435 10:07:07.792272 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8436 10:07:07.792424 [Gating] SW calibration Done
8437 10:07:07.792554 ==
8438 10:07:07.795535 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 10:07:07.802413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 10:07:07.802564 ==
8441 10:07:07.802697 RX Vref Scan: 0
8442 10:07:07.802823
8443 10:07:07.805563 RX Vref 0 -> 0, step: 1
8444 10:07:07.805653
8445 10:07:07.808804 RX Delay 0 -> 252, step: 8
8446 10:07:07.812387 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8447 10:07:07.815348 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8448 10:07:07.818922 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8449 10:07:07.825384 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8450 10:07:07.828715 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8451 10:07:07.831734 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8452 10:07:07.835189 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8453 10:07:07.838508 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8454 10:07:07.845127 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8455 10:07:07.848329 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8456 10:07:07.851569 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8457 10:07:07.854661 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8458 10:07:07.858161 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8459 10:07:07.864973 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8460 10:07:07.867875 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8461 10:07:07.871219 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8462 10:07:07.871327 ==
8463 10:07:07.874560 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 10:07:07.878046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 10:07:07.881189 ==
8466 10:07:07.881285 DQS Delay:
8467 10:07:07.881355 DQS0 = 0, DQS1 = 0
8468 10:07:07.884690 DQM Delay:
8469 10:07:07.884812 DQM0 = 137, DQM1 = 130
8470 10:07:07.887929 DQ Delay:
8471 10:07:07.891340 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =139
8472 10:07:07.894780 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8473 10:07:07.897900 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8474 10:07:07.901414 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
8475 10:07:07.901513
8476 10:07:07.901582
8477 10:07:07.901646 ==
8478 10:07:07.904562 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 10:07:07.907667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 10:07:07.907757 ==
8481 10:07:07.907827
8482 10:07:07.911149
8483 10:07:07.911237 TX Vref Scan disable
8484 10:07:07.914605 == TX Byte 0 ==
8485 10:07:07.917715 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8486 10:07:07.921008 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8487 10:07:07.924175 == TX Byte 1 ==
8488 10:07:07.927724 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8489 10:07:07.931192 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8490 10:07:07.931312 ==
8491 10:07:07.934402 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 10:07:07.940728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 10:07:07.940872 ==
8494 10:07:07.951134
8495 10:07:07.954800 TX Vref early break, caculate TX vref
8496 10:07:07.957707 TX Vref=16, minBit 10, minWin=21, winSum=367
8497 10:07:07.961202 TX Vref=18, minBit 10, minWin=22, winSum=382
8498 10:07:07.964389 TX Vref=20, minBit 10, minWin=22, winSum=391
8499 10:07:07.967726 TX Vref=22, minBit 10, minWin=23, winSum=397
8500 10:07:07.974353 TX Vref=24, minBit 15, minWin=24, winSum=414
8501 10:07:07.977645 TX Vref=26, minBit 1, minWin=25, winSum=416
8502 10:07:07.980919 TX Vref=28, minBit 13, minWin=23, winSum=414
8503 10:07:07.984089 TX Vref=30, minBit 10, minWin=23, winSum=407
8504 10:07:07.987488 TX Vref=32, minBit 10, minWin=23, winSum=394
8505 10:07:07.994165 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 26
8506 10:07:07.994300
8507 10:07:07.997633 Final TX Range 0 Vref 26
8508 10:07:07.997727
8509 10:07:07.997797 ==
8510 10:07:08.000783 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 10:07:08.004215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 10:07:08.004324 ==
8513 10:07:08.004420
8514 10:07:08.004512
8515 10:07:08.007276 TX Vref Scan disable
8516 10:07:08.013993 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8517 10:07:08.014100 == TX Byte 0 ==
8518 10:07:08.017237 u2DelayCellOfst[0]=13 cells (4 PI)
8519 10:07:08.020473 u2DelayCellOfst[1]=10 cells (3 PI)
8520 10:07:08.023981 u2DelayCellOfst[2]=0 cells (0 PI)
8521 10:07:08.026945 u2DelayCellOfst[3]=3 cells (1 PI)
8522 10:07:08.030451 u2DelayCellOfst[4]=6 cells (2 PI)
8523 10:07:08.033797 u2DelayCellOfst[5]=16 cells (5 PI)
8524 10:07:08.037129 u2DelayCellOfst[6]=13 cells (4 PI)
8525 10:07:08.040245 u2DelayCellOfst[7]=3 cells (1 PI)
8526 10:07:08.043863 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8527 10:07:08.047241 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8528 10:07:08.050171 == TX Byte 1 ==
8529 10:07:08.053529 u2DelayCellOfst[8]=0 cells (0 PI)
8530 10:07:08.053654 u2DelayCellOfst[9]=3 cells (1 PI)
8531 10:07:08.057006 u2DelayCellOfst[10]=10 cells (3 PI)
8532 10:07:08.060506 u2DelayCellOfst[11]=3 cells (1 PI)
8533 10:07:08.063563 u2DelayCellOfst[12]=16 cells (5 PI)
8534 10:07:08.066662 u2DelayCellOfst[13]=20 cells (6 PI)
8535 10:07:08.070109 u2DelayCellOfst[14]=20 cells (6 PI)
8536 10:07:08.073256 u2DelayCellOfst[15]=16 cells (5 PI)
8537 10:07:08.080140 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8538 10:07:08.083062 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8539 10:07:08.083188 DramC Write-DBI on
8540 10:07:08.083291 ==
8541 10:07:08.086602 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 10:07:08.093264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 10:07:08.093390 ==
8544 10:07:08.093488
8545 10:07:08.093581
8546 10:07:08.093673 TX Vref Scan disable
8547 10:07:08.097465 == TX Byte 0 ==
8548 10:07:08.100798 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8549 10:07:08.104258 == TX Byte 1 ==
8550 10:07:08.107425 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8551 10:07:08.110641 DramC Write-DBI off
8552 10:07:08.110732
8553 10:07:08.110801 [DATLAT]
8554 10:07:08.110865 Freq=1600, CH1 RK0
8555 10:07:08.110928
8556 10:07:08.113710 DATLAT Default: 0xf
8557 10:07:08.113798 0, 0xFFFF, sum = 0
8558 10:07:08.117024 1, 0xFFFF, sum = 0
8559 10:07:08.120565 2, 0xFFFF, sum = 0
8560 10:07:08.120682 3, 0xFFFF, sum = 0
8561 10:07:08.123658 4, 0xFFFF, sum = 0
8562 10:07:08.123749 5, 0xFFFF, sum = 0
8563 10:07:08.127186 6, 0xFFFF, sum = 0
8564 10:07:08.127277 7, 0xFFFF, sum = 0
8565 10:07:08.130409 8, 0xFFFF, sum = 0
8566 10:07:08.130526 9, 0xFFFF, sum = 0
8567 10:07:08.134136 10, 0xFFFF, sum = 0
8568 10:07:08.134227 11, 0xFFFF, sum = 0
8569 10:07:08.137134 12, 0xFFFF, sum = 0
8570 10:07:08.137223 13, 0xFFFF, sum = 0
8571 10:07:08.140175 14, 0x0, sum = 1
8572 10:07:08.140264 15, 0x0, sum = 2
8573 10:07:08.143594 16, 0x0, sum = 3
8574 10:07:08.143684 17, 0x0, sum = 4
8575 10:07:08.146964 best_step = 15
8576 10:07:08.147060
8577 10:07:08.147161 ==
8578 10:07:08.150347 Dram Type= 6, Freq= 0, CH_1, rank 0
8579 10:07:08.153495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8580 10:07:08.153614 ==
8581 10:07:08.157066 RX Vref Scan: 1
8582 10:07:08.157173
8583 10:07:08.157267 Set Vref Range= 24 -> 127
8584 10:07:08.157358
8585 10:07:08.160230 RX Vref 24 -> 127, step: 1
8586 10:07:08.160344
8587 10:07:08.163417 RX Delay 19 -> 252, step: 4
8588 10:07:08.163505
8589 10:07:08.167199 Set Vref, RX VrefLevel [Byte0]: 24
8590 10:07:08.170290 [Byte1]: 24
8591 10:07:08.170415
8592 10:07:08.173460 Set Vref, RX VrefLevel [Byte0]: 25
8593 10:07:08.177058 [Byte1]: 25
8594 10:07:08.180197
8595 10:07:08.180303 Set Vref, RX VrefLevel [Byte0]: 26
8596 10:07:08.183538 [Byte1]: 26
8597 10:07:08.187528
8598 10:07:08.187620 Set Vref, RX VrefLevel [Byte0]: 27
8599 10:07:08.190917 [Byte1]: 27
8600 10:07:08.195060
8601 10:07:08.195158 Set Vref, RX VrefLevel [Byte0]: 28
8602 10:07:08.198567 [Byte1]: 28
8603 10:07:08.202864
8604 10:07:08.202958 Set Vref, RX VrefLevel [Byte0]: 29
8605 10:07:08.206088 [Byte1]: 29
8606 10:07:08.210537
8607 10:07:08.210633 Set Vref, RX VrefLevel [Byte0]: 30
8608 10:07:08.213600 [Byte1]: 30
8609 10:07:08.217968
8610 10:07:08.218062 Set Vref, RX VrefLevel [Byte0]: 31
8611 10:07:08.221039 [Byte1]: 31
8612 10:07:08.225486
8613 10:07:08.225578 Set Vref, RX VrefLevel [Byte0]: 32
8614 10:07:08.228957 [Byte1]: 32
8615 10:07:08.232998
8616 10:07:08.233089 Set Vref, RX VrefLevel [Byte0]: 33
8617 10:07:08.236408 [Byte1]: 33
8618 10:07:08.240716
8619 10:07:08.240825 Set Vref, RX VrefLevel [Byte0]: 34
8620 10:07:08.243697 [Byte1]: 34
8621 10:07:08.248041
8622 10:07:08.248161 Set Vref, RX VrefLevel [Byte0]: 35
8623 10:07:08.251479 [Byte1]: 35
8624 10:07:08.255802
8625 10:07:08.255921 Set Vref, RX VrefLevel [Byte0]: 36
8626 10:07:08.259069 [Byte1]: 36
8627 10:07:08.263140
8628 10:07:08.266816 Set Vref, RX VrefLevel [Byte0]: 37
8629 10:07:08.266942 [Byte1]: 37
8630 10:07:08.271075
8631 10:07:08.271183 Set Vref, RX VrefLevel [Byte0]: 38
8632 10:07:08.274363 [Byte1]: 38
8633 10:07:08.278450
8634 10:07:08.278559 Set Vref, RX VrefLevel [Byte0]: 39
8635 10:07:08.281858 [Byte1]: 39
8636 10:07:08.286134
8637 10:07:08.286251 Set Vref, RX VrefLevel [Byte0]: 40
8638 10:07:08.289063 [Byte1]: 40
8639 10:07:08.293486
8640 10:07:08.293600 Set Vref, RX VrefLevel [Byte0]: 41
8641 10:07:08.300303 [Byte1]: 41
8642 10:07:08.300430
8643 10:07:08.303320 Set Vref, RX VrefLevel [Byte0]: 42
8644 10:07:08.306743 [Byte1]: 42
8645 10:07:08.306862
8646 10:07:08.309772 Set Vref, RX VrefLevel [Byte0]: 43
8647 10:07:08.313346 [Byte1]: 43
8648 10:07:08.313455
8649 10:07:08.316692 Set Vref, RX VrefLevel [Byte0]: 44
8650 10:07:08.319899 [Byte1]: 44
8651 10:07:08.323819
8652 10:07:08.323925 Set Vref, RX VrefLevel [Byte0]: 45
8653 10:07:08.327463 [Byte1]: 45
8654 10:07:08.331357
8655 10:07:08.331499 Set Vref, RX VrefLevel [Byte0]: 46
8656 10:07:08.334934 [Byte1]: 46
8657 10:07:08.338950
8658 10:07:08.339096 Set Vref, RX VrefLevel [Byte0]: 47
8659 10:07:08.342142 [Byte1]: 47
8660 10:07:08.346472
8661 10:07:08.346588 Set Vref, RX VrefLevel [Byte0]: 48
8662 10:07:08.349944 [Byte1]: 48
8663 10:07:08.354013
8664 10:07:08.354160 Set Vref, RX VrefLevel [Byte0]: 49
8665 10:07:08.357437 [Byte1]: 49
8666 10:07:08.361818
8667 10:07:08.361957 Set Vref, RX VrefLevel [Byte0]: 50
8668 10:07:08.364822 [Byte1]: 50
8669 10:07:08.369899
8670 10:07:08.370019 Set Vref, RX VrefLevel [Byte0]: 51
8671 10:07:08.373077 [Byte1]: 51
8672 10:07:08.376946
8673 10:07:08.377097 Set Vref, RX VrefLevel [Byte0]: 52
8674 10:07:08.380070 [Byte1]: 52
8675 10:07:08.384340
8676 10:07:08.384483 Set Vref, RX VrefLevel [Byte0]: 53
8677 10:07:08.387530 [Byte1]: 53
8678 10:07:08.392257
8679 10:07:08.392403 Set Vref, RX VrefLevel [Byte0]: 54
8680 10:07:08.398571 [Byte1]: 54
8681 10:07:08.398688
8682 10:07:08.401647 Set Vref, RX VrefLevel [Byte0]: 55
8683 10:07:08.405117 [Byte1]: 55
8684 10:07:08.405222
8685 10:07:08.408670 Set Vref, RX VrefLevel [Byte0]: 56
8686 10:07:08.411673 [Byte1]: 56
8687 10:07:08.411761
8688 10:07:08.415056 Set Vref, RX VrefLevel [Byte0]: 57
8689 10:07:08.418651 [Byte1]: 57
8690 10:07:08.422113
8691 10:07:08.422274 Set Vref, RX VrefLevel [Byte0]: 58
8692 10:07:08.425629 [Byte1]: 58
8693 10:07:08.430094
8694 10:07:08.430202 Set Vref, RX VrefLevel [Byte0]: 59
8695 10:07:08.433318 [Byte1]: 59
8696 10:07:08.437400
8697 10:07:08.437495 Set Vref, RX VrefLevel [Byte0]: 60
8698 10:07:08.440947 [Byte1]: 60
8699 10:07:08.445118
8700 10:07:08.445232 Set Vref, RX VrefLevel [Byte0]: 61
8701 10:07:08.448460 [Byte1]: 61
8702 10:07:08.452743
8703 10:07:08.452858 Set Vref, RX VrefLevel [Byte0]: 62
8704 10:07:08.455918 [Byte1]: 62
8705 10:07:08.460309
8706 10:07:08.460398 Set Vref, RX VrefLevel [Byte0]: 63
8707 10:07:08.463286 [Byte1]: 63
8708 10:07:08.467650
8709 10:07:08.467781 Set Vref, RX VrefLevel [Byte0]: 64
8710 10:07:08.471000 [Byte1]: 64
8711 10:07:08.475456
8712 10:07:08.475589 Set Vref, RX VrefLevel [Byte0]: 65
8713 10:07:08.478456 [Byte1]: 65
8714 10:07:08.482888
8715 10:07:08.482997 Set Vref, RX VrefLevel [Byte0]: 66
8716 10:07:08.486631 [Byte1]: 66
8717 10:07:08.490495
8718 10:07:08.490620 Set Vref, RX VrefLevel [Byte0]: 67
8719 10:07:08.493623 [Byte1]: 67
8720 10:07:08.497939
8721 10:07:08.498029 Set Vref, RX VrefLevel [Byte0]: 68
8722 10:07:08.501303 [Byte1]: 68
8723 10:07:08.505519
8724 10:07:08.505647 Set Vref, RX VrefLevel [Byte0]: 69
8725 10:07:08.508666 [Byte1]: 69
8726 10:07:08.513124
8727 10:07:08.513300 Set Vref, RX VrefLevel [Byte0]: 70
8728 10:07:08.516515 [Byte1]: 70
8729 10:07:08.520786
8730 10:07:08.520896 Set Vref, RX VrefLevel [Byte0]: 71
8731 10:07:08.523894 [Byte1]: 71
8732 10:07:08.528206
8733 10:07:08.528338 Set Vref, RX VrefLevel [Byte0]: 72
8734 10:07:08.531408 [Byte1]: 72
8735 10:07:08.535777
8736 10:07:08.535875 Set Vref, RX VrefLevel [Byte0]: 73
8737 10:07:08.538956 [Byte1]: 73
8738 10:07:08.543358
8739 10:07:08.543488 Set Vref, RX VrefLevel [Byte0]: 74
8740 10:07:08.546864 [Byte1]: 74
8741 10:07:08.551222
8742 10:07:08.551360 Set Vref, RX VrefLevel [Byte0]: 75
8743 10:07:08.554281 [Byte1]: 75
8744 10:07:08.558732
8745 10:07:08.558833 Set Vref, RX VrefLevel [Byte0]: 76
8746 10:07:08.561751 [Byte1]: 76
8747 10:07:08.566141
8748 10:07:08.566235 Final RX Vref Byte 0 = 52 to rank0
8749 10:07:08.569548 Final RX Vref Byte 1 = 61 to rank0
8750 10:07:08.572555 Final RX Vref Byte 0 = 52 to rank1
8751 10:07:08.576194 Final RX Vref Byte 1 = 61 to rank1==
8752 10:07:08.579613 Dram Type= 6, Freq= 0, CH_1, rank 0
8753 10:07:08.586080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8754 10:07:08.586225 ==
8755 10:07:08.586341 DQS Delay:
8756 10:07:08.589488 DQS0 = 0, DQS1 = 0
8757 10:07:08.589599 DQM Delay:
8758 10:07:08.589694 DQM0 = 133, DQM1 = 128
8759 10:07:08.592597 DQ Delay:
8760 10:07:08.595677 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8761 10:07:08.598959 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8762 10:07:08.602545 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8763 10:07:08.605864 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =134
8764 10:07:08.605985
8765 10:07:08.606086
8766 10:07:08.606177
8767 10:07:08.609007 [DramC_TX_OE_Calibration] TA2
8768 10:07:08.612344 Original DQ_B0 (3 6) =30, OEN = 27
8769 10:07:08.615912 Original DQ_B1 (3 6) =30, OEN = 27
8770 10:07:08.619053 24, 0x0, End_B0=24 End_B1=24
8771 10:07:08.619145 25, 0x0, End_B0=25 End_B1=25
8772 10:07:08.622442 26, 0x0, End_B0=26 End_B1=26
8773 10:07:08.625575 27, 0x0, End_B0=27 End_B1=27
8774 10:07:08.629156 28, 0x0, End_B0=28 End_B1=28
8775 10:07:08.631899 29, 0x0, End_B0=29 End_B1=29
8776 10:07:08.631995 30, 0x0, End_B0=30 End_B1=30
8777 10:07:08.635316 31, 0x4141, End_B0=30 End_B1=30
8778 10:07:08.638492 Byte0 end_step=30 best_step=27
8779 10:07:08.641969 Byte1 end_step=30 best_step=27
8780 10:07:08.645119 Byte0 TX OE(2T, 0.5T) = (3, 3)
8781 10:07:08.648675 Byte1 TX OE(2T, 0.5T) = (3, 3)
8782 10:07:08.648800
8783 10:07:08.648883
8784 10:07:08.655016 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8785 10:07:08.658580 CH1 RK0: MR19=303, MR18=1624
8786 10:07:08.665146 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8787 10:07:08.665262
8788 10:07:08.668499 ----->DramcWriteLeveling(PI) begin...
8789 10:07:08.668598 ==
8790 10:07:08.671743 Dram Type= 6, Freq= 0, CH_1, rank 1
8791 10:07:08.674940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8792 10:07:08.675037 ==
8793 10:07:08.678266 Write leveling (Byte 0): 24 => 24
8794 10:07:08.681950 Write leveling (Byte 1): 31 => 31
8795 10:07:08.684824 DramcWriteLeveling(PI) end<-----
8796 10:07:08.684927
8797 10:07:08.684999 ==
8798 10:07:08.688353 Dram Type= 6, Freq= 0, CH_1, rank 1
8799 10:07:08.691577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8800 10:07:08.694764 ==
8801 10:07:08.694882 [Gating] SW mode calibration
8802 10:07:08.704832 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8803 10:07:08.708078 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8804 10:07:08.711155 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 10:07:08.718037 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 10:07:08.721416 1 4 8 | B1->B0 | 2e2d 2323 | 1 0 | (0 0) (0 0)
8807 10:07:08.724511 1 4 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
8808 10:07:08.731340 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8809 10:07:08.734404 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 10:07:08.737838 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 10:07:08.744582 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8812 10:07:08.747785 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 10:07:08.751315 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8814 10:07:08.758156 1 5 8 | B1->B0 | 2b2b 3434 | 0 1 | (1 0) (1 0)
8815 10:07:08.761109 1 5 12 | B1->B0 | 2323 3030 | 0 1 | (1 0) (1 0)
8816 10:07:08.764473 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 10:07:08.771191 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 10:07:08.774469 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 10:07:08.777724 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 10:07:08.784272 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 10:07:08.787475 1 6 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8822 10:07:08.790952 1 6 8 | B1->B0 | 4343 2424 | 0 0 | (0 0) (0 0)
8823 10:07:08.797588 1 6 12 | B1->B0 | 4646 3838 | 0 0 | (0 0) (0 0)
8824 10:07:08.800629 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 10:07:08.804346 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 10:07:08.810857 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 10:07:08.813981 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 10:07:08.817302 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 10:07:08.823733 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 10:07:08.827467 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8831 10:07:08.830576 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8832 10:07:08.837225 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 10:07:08.840481 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 10:07:08.844074 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 10:07:08.850216 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 10:07:08.853829 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 10:07:08.856964 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 10:07:08.863602 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 10:07:08.867121 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 10:07:08.870140 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 10:07:08.873564 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 10:07:08.880017 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 10:07:08.883593 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 10:07:08.886719 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 10:07:08.893343 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 10:07:08.896634 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8847 10:07:08.903276 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8848 10:07:08.906363 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 10:07:08.909817 Total UI for P1: 0, mck2ui 16
8850 10:07:08.913287 best dqsien dly found for B0: ( 1, 9, 10)
8851 10:07:08.916916 Total UI for P1: 0, mck2ui 16
8852 10:07:08.919779 best dqsien dly found for B1: ( 1, 9, 10)
8853 10:07:08.922853 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8854 10:07:08.926102 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8855 10:07:08.926210
8856 10:07:08.929574 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8857 10:07:08.932732 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8858 10:07:08.936029 [Gating] SW calibration Done
8859 10:07:08.936123 ==
8860 10:07:08.939516 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 10:07:08.942599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 10:07:08.946052 ==
8863 10:07:08.946163 RX Vref Scan: 0
8864 10:07:08.946234
8865 10:07:08.949643 RX Vref 0 -> 0, step: 1
8866 10:07:08.949733
8867 10:07:08.949812 RX Delay 0 -> 252, step: 8
8868 10:07:08.955767 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8869 10:07:08.959331 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8870 10:07:08.962755 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8871 10:07:08.965958 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8872 10:07:08.969456 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8873 10:07:08.976151 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8874 10:07:08.979061 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8875 10:07:08.982451 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8876 10:07:08.985904 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8877 10:07:08.989029 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8878 10:07:08.995735 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8879 10:07:08.999363 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8880 10:07:09.002365 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8881 10:07:09.005658 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8882 10:07:09.012250 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8883 10:07:09.015361 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8884 10:07:09.015489 ==
8885 10:07:09.018861 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 10:07:09.022089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 10:07:09.022179 ==
8888 10:07:09.025299 DQS Delay:
8889 10:07:09.025386 DQS0 = 0, DQS1 = 0
8890 10:07:09.025453 DQM Delay:
8891 10:07:09.028863 DQM0 = 137, DQM1 = 133
8892 10:07:09.028952 DQ Delay:
8893 10:07:09.032141 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8894 10:07:09.035267 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =139
8895 10:07:09.038475 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8896 10:07:09.045156 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8897 10:07:09.045276
8898 10:07:09.045348
8899 10:07:09.045411 ==
8900 10:07:09.048744 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 10:07:09.051976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 10:07:09.052066 ==
8903 10:07:09.052134
8904 10:07:09.052197
8905 10:07:09.055132 TX Vref Scan disable
8906 10:07:09.055220 == TX Byte 0 ==
8907 10:07:09.061461 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8908 10:07:09.065130 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8909 10:07:09.065226 == TX Byte 1 ==
8910 10:07:09.071724 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8911 10:07:09.074732 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8912 10:07:09.074839 ==
8913 10:07:09.078106 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 10:07:09.081598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 10:07:09.081689 ==
8916 10:07:09.095252
8917 10:07:09.098399 TX Vref early break, caculate TX vref
8918 10:07:09.101512 TX Vref=16, minBit 3, minWin=23, winSum=380
8919 10:07:09.105129 TX Vref=18, minBit 8, minWin=22, winSum=388
8920 10:07:09.107893 TX Vref=20, minBit 13, minWin=23, winSum=401
8921 10:07:09.111547 TX Vref=22, minBit 8, minWin=24, winSum=407
8922 10:07:09.118067 TX Vref=24, minBit 8, minWin=24, winSum=412
8923 10:07:09.121346 TX Vref=26, minBit 8, minWin=24, winSum=422
8924 10:07:09.124568 TX Vref=28, minBit 9, minWin=24, winSum=411
8925 10:07:09.127787 TX Vref=30, minBit 8, minWin=24, winSum=407
8926 10:07:09.131227 TX Vref=32, minBit 9, minWin=23, winSum=397
8927 10:07:09.137860 [TxChooseVref] Worse bit 8, Min win 24, Win sum 422, Final Vref 26
8928 10:07:09.137979
8929 10:07:09.141091 Final TX Range 0 Vref 26
8930 10:07:09.141218
8931 10:07:09.141325 ==
8932 10:07:09.144437 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 10:07:09.147587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 10:07:09.147677 ==
8935 10:07:09.147746
8936 10:07:09.147809
8937 10:07:09.150918 TX Vref Scan disable
8938 10:07:09.157697 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8939 10:07:09.157811 == TX Byte 0 ==
8940 10:07:09.161281 u2DelayCellOfst[0]=13 cells (4 PI)
8941 10:07:09.164779 u2DelayCellOfst[1]=10 cells (3 PI)
8942 10:07:09.167747 u2DelayCellOfst[2]=0 cells (0 PI)
8943 10:07:09.170975 u2DelayCellOfst[3]=3 cells (1 PI)
8944 10:07:09.174452 u2DelayCellOfst[4]=6 cells (2 PI)
8945 10:07:09.177615 u2DelayCellOfst[5]=16 cells (5 PI)
8946 10:07:09.181027 u2DelayCellOfst[6]=13 cells (4 PI)
8947 10:07:09.181131 u2DelayCellOfst[7]=3 cells (1 PI)
8948 10:07:09.187342 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8949 10:07:09.190633 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8950 10:07:09.190726 == TX Byte 1 ==
8951 10:07:09.194029 u2DelayCellOfst[8]=0 cells (0 PI)
8952 10:07:09.197207 u2DelayCellOfst[9]=6 cells (2 PI)
8953 10:07:09.200683 u2DelayCellOfst[10]=10 cells (3 PI)
8954 10:07:09.203904 u2DelayCellOfst[11]=3 cells (1 PI)
8955 10:07:09.207273 u2DelayCellOfst[12]=13 cells (4 PI)
8956 10:07:09.210351 u2DelayCellOfst[13]=16 cells (5 PI)
8957 10:07:09.213915 u2DelayCellOfst[14]=16 cells (5 PI)
8958 10:07:09.216924 u2DelayCellOfst[15]=16 cells (5 PI)
8959 10:07:09.220586 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8960 10:07:09.226714 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8961 10:07:09.226829 DramC Write-DBI on
8962 10:07:09.226902 ==
8963 10:07:09.230289 Dram Type= 6, Freq= 0, CH_1, rank 1
8964 10:07:09.236862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8965 10:07:09.236968 ==
8966 10:07:09.237041
8967 10:07:09.237105
8968 10:07:09.237166 TX Vref Scan disable
8969 10:07:09.240468 == TX Byte 0 ==
8970 10:07:09.243777 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8971 10:07:09.247243 == TX Byte 1 ==
8972 10:07:09.250292 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8973 10:07:09.253567 DramC Write-DBI off
8974 10:07:09.253663
8975 10:07:09.253734 [DATLAT]
8976 10:07:09.253798 Freq=1600, CH1 RK1
8977 10:07:09.253861
8978 10:07:09.256859 DATLAT Default: 0xf
8979 10:07:09.260112 0, 0xFFFF, sum = 0
8980 10:07:09.260203 1, 0xFFFF, sum = 0
8981 10:07:09.263484 2, 0xFFFF, sum = 0
8982 10:07:09.263575 3, 0xFFFF, sum = 0
8983 10:07:09.266995 4, 0xFFFF, sum = 0
8984 10:07:09.267087 5, 0xFFFF, sum = 0
8985 10:07:09.270431 6, 0xFFFF, sum = 0
8986 10:07:09.270528 7, 0xFFFF, sum = 0
8987 10:07:09.273684 8, 0xFFFF, sum = 0
8988 10:07:09.273775 9, 0xFFFF, sum = 0
8989 10:07:09.277070 10, 0xFFFF, sum = 0
8990 10:07:09.277161 11, 0xFFFF, sum = 0
8991 10:07:09.280091 12, 0xFFFF, sum = 0
8992 10:07:09.280180 13, 0xFFFF, sum = 0
8993 10:07:09.283432 14, 0x0, sum = 1
8994 10:07:09.283523 15, 0x0, sum = 2
8995 10:07:09.286822 16, 0x0, sum = 3
8996 10:07:09.286913 17, 0x0, sum = 4
8997 10:07:09.289907 best_step = 15
8998 10:07:09.289996
8999 10:07:09.290079 ==
9000 10:07:09.293269 Dram Type= 6, Freq= 0, CH_1, rank 1
9001 10:07:09.296698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9002 10:07:09.296805 ==
9003 10:07:09.299872 RX Vref Scan: 0
9004 10:07:09.299966
9005 10:07:09.300036 RX Vref 0 -> 0, step: 1
9006 10:07:09.300101
9007 10:07:09.303443 RX Delay 19 -> 252, step: 4
9008 10:07:09.306491 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
9009 10:07:09.313095 iDelay=195, Bit 1, Center 132 (87 ~ 178) 92
9010 10:07:09.316640 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9011 10:07:09.319743 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9012 10:07:09.323190 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9013 10:07:09.326313 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9014 10:07:09.332911 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9015 10:07:09.336172 iDelay=195, Bit 7, Center 132 (87 ~ 178) 92
9016 10:07:09.339641 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9017 10:07:09.342943 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9018 10:07:09.346086 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9019 10:07:09.353225 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9020 10:07:09.355924 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9021 10:07:09.359361 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9022 10:07:09.362686 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9023 10:07:09.366311 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9024 10:07:09.369387 ==
9025 10:07:09.372611 Dram Type= 6, Freq= 0, CH_1, rank 1
9026 10:07:09.376030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9027 10:07:09.376144 ==
9028 10:07:09.376244 DQS Delay:
9029 10:07:09.379096 DQS0 = 0, DQS1 = 0
9030 10:07:09.379184 DQM Delay:
9031 10:07:09.382619 DQM0 = 134, DQM1 = 130
9032 10:07:09.382712 DQ Delay:
9033 10:07:09.385514 DQ0 =138, DQ1 =132, DQ2 =120, DQ3 =130
9034 10:07:09.388933 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =132
9035 10:07:09.392390 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
9036 10:07:09.395621 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9037 10:07:09.395716
9038 10:07:09.395786
9039 10:07:09.395849
9040 10:07:09.398886 [DramC_TX_OE_Calibration] TA2
9041 10:07:09.402321 Original DQ_B0 (3 6) =30, OEN = 27
9042 10:07:09.405478 Original DQ_B1 (3 6) =30, OEN = 27
9043 10:07:09.409062 24, 0x0, End_B0=24 End_B1=24
9044 10:07:09.412604 25, 0x0, End_B0=25 End_B1=25
9045 10:07:09.412700 26, 0x0, End_B0=26 End_B1=26
9046 10:07:09.415567 27, 0x0, End_B0=27 End_B1=27
9047 10:07:09.418721 28, 0x0, End_B0=28 End_B1=28
9048 10:07:09.421946 29, 0x0, End_B0=29 End_B1=29
9049 10:07:09.425462 30, 0x0, End_B0=30 End_B1=30
9050 10:07:09.428440 31, 0x4141, End_B0=30 End_B1=30
9051 10:07:09.428535 Byte0 end_step=30 best_step=27
9052 10:07:09.431978 Byte1 end_step=30 best_step=27
9053 10:07:09.435061 Byte0 TX OE(2T, 0.5T) = (3, 3)
9054 10:07:09.438456 Byte1 TX OE(2T, 0.5T) = (3, 3)
9055 10:07:09.438551
9056 10:07:09.438620
9057 10:07:09.444924 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9058 10:07:09.448456 CH1 RK1: MR19=303, MR18=1C07
9059 10:07:09.455070 CH1_RK1: MR19=0x303, MR18=0x1C07, DQSOSC=395, MR23=63, INC=23, DEC=15
9060 10:07:09.458652 [RxdqsGatingPostProcess] freq 1600
9061 10:07:09.464823 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9062 10:07:09.468481 best DQS0 dly(2T, 0.5T) = (1, 1)
9063 10:07:09.468630 best DQS1 dly(2T, 0.5T) = (1, 1)
9064 10:07:09.471771 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9065 10:07:09.474999 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9066 10:07:09.478208 best DQS0 dly(2T, 0.5T) = (1, 1)
9067 10:07:09.481576 best DQS1 dly(2T, 0.5T) = (1, 1)
9068 10:07:09.485132 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9069 10:07:09.488335 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9070 10:07:09.491306 Pre-setting of DQS Precalculation
9071 10:07:09.497934 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9072 10:07:09.504645 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9073 10:07:09.511330 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9074 10:07:09.511465
9075 10:07:09.511570
9076 10:07:09.514903 [Calibration Summary] 3200 Mbps
9077 10:07:09.515008 CH 0, Rank 0
9078 10:07:09.518377 SW Impedance : PASS
9079 10:07:09.521335 DUTY Scan : NO K
9080 10:07:09.521455 ZQ Calibration : PASS
9081 10:07:09.524524 Jitter Meter : NO K
9082 10:07:09.527628 CBT Training : PASS
9083 10:07:09.527732 Write leveling : PASS
9084 10:07:09.531371 RX DQS gating : PASS
9085 10:07:09.531481 RX DQ/DQS(RDDQC) : PASS
9086 10:07:09.534263 TX DQ/DQS : PASS
9087 10:07:09.537693 RX DATLAT : PASS
9088 10:07:09.537800 RX DQ/DQS(Engine): PASS
9089 10:07:09.540927 TX OE : PASS
9090 10:07:09.541031 All Pass.
9091 10:07:09.541127
9092 10:07:09.544518 CH 0, Rank 1
9093 10:07:09.544681 SW Impedance : PASS
9094 10:07:09.547559 DUTY Scan : NO K
9095 10:07:09.550852 ZQ Calibration : PASS
9096 10:07:09.550956 Jitter Meter : NO K
9097 10:07:09.554337 CBT Training : PASS
9098 10:07:09.557406 Write leveling : PASS
9099 10:07:09.557511 RX DQS gating : PASS
9100 10:07:09.561006 RX DQ/DQS(RDDQC) : PASS
9101 10:07:09.564264 TX DQ/DQS : PASS
9102 10:07:09.564386 RX DATLAT : PASS
9103 10:07:09.567169 RX DQ/DQS(Engine): PASS
9104 10:07:09.570590 TX OE : PASS
9105 10:07:09.570710 All Pass.
9106 10:07:09.570809
9107 10:07:09.570900 CH 1, Rank 0
9108 10:07:09.574118 SW Impedance : PASS
9109 10:07:09.577275 DUTY Scan : NO K
9110 10:07:09.577387 ZQ Calibration : PASS
9111 10:07:09.580527 Jitter Meter : NO K
9112 10:07:09.583865 CBT Training : PASS
9113 10:07:09.583984 Write leveling : PASS
9114 10:07:09.587117 RX DQS gating : PASS
9115 10:07:09.590544 RX DQ/DQS(RDDQC) : PASS
9116 10:07:09.590713 TX DQ/DQS : PASS
9117 10:07:09.593662 RX DATLAT : PASS
9118 10:07:09.597079 RX DQ/DQS(Engine): PASS
9119 10:07:09.597171 TX OE : PASS
9120 10:07:09.597238 All Pass.
9121 10:07:09.597300
9122 10:07:09.600447 CH 1, Rank 1
9123 10:07:09.604063 SW Impedance : PASS
9124 10:07:09.604150 DUTY Scan : NO K
9125 10:07:09.606921 ZQ Calibration : PASS
9126 10:07:09.607007 Jitter Meter : NO K
9127 10:07:09.610382 CBT Training : PASS
9128 10:07:09.613515 Write leveling : PASS
9129 10:07:09.613622 RX DQS gating : PASS
9130 10:07:09.616962 RX DQ/DQS(RDDQC) : PASS
9131 10:07:09.619950 TX DQ/DQS : PASS
9132 10:07:09.620038 RX DATLAT : PASS
9133 10:07:09.623573 RX DQ/DQS(Engine): PASS
9134 10:07:09.626605 TX OE : PASS
9135 10:07:09.626694 All Pass.
9136 10:07:09.626761
9137 10:07:09.630106 DramC Write-DBI on
9138 10:07:09.630193 PER_BANK_REFRESH: Hybrid Mode
9139 10:07:09.633766 TX_TRACKING: ON
9140 10:07:09.643364 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9141 10:07:09.650137 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9142 10:07:09.656567 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9143 10:07:09.659796 [FAST_K] Save calibration result to emmc
9144 10:07:09.663176 sync common calibartion params.
9145 10:07:09.666333 sync cbt_mode0:1, 1:1
9146 10:07:09.666425 dram_init: ddr_geometry: 2
9147 10:07:09.670082 dram_init: ddr_geometry: 2
9148 10:07:09.673235 dram_init: ddr_geometry: 2
9149 10:07:09.676116 0:dram_rank_size:100000000
9150 10:07:09.676200 1:dram_rank_size:100000000
9151 10:07:09.682999 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9152 10:07:09.686054 DFS_SHUFFLE_HW_MODE: ON
9153 10:07:09.689617 dramc_set_vcore_voltage set vcore to 725000
9154 10:07:09.693046 Read voltage for 1600, 0
9155 10:07:09.693136 Vio18 = 0
9156 10:07:09.693216 Vcore = 725000
9157 10:07:09.696286 Vdram = 0
9158 10:07:09.696368 Vddq = 0
9159 10:07:09.696432 Vmddr = 0
9160 10:07:09.699624 switch to 3200 Mbps bootup
9161 10:07:09.699704 [DramcRunTimeConfig]
9162 10:07:09.702705 PHYPLL
9163 10:07:09.702809 DPM_CONTROL_AFTERK: ON
9164 10:07:09.705848 PER_BANK_REFRESH: ON
9165 10:07:09.709196 REFRESH_OVERHEAD_REDUCTION: ON
9166 10:07:09.709281 CMD_PICG_NEW_MODE: OFF
9167 10:07:09.712428 XRTWTW_NEW_MODE: ON
9168 10:07:09.712515 XRTRTR_NEW_MODE: ON
9169 10:07:09.715989 TX_TRACKING: ON
9170 10:07:09.716090 RDSEL_TRACKING: OFF
9171 10:07:09.719125 DQS Precalculation for DVFS: ON
9172 10:07:09.722407 RX_TRACKING: OFF
9173 10:07:09.722491 HW_GATING DBG: ON
9174 10:07:09.725845 ZQCS_ENABLE_LP4: ON
9175 10:07:09.725937 RX_PICG_NEW_MODE: ON
9176 10:07:09.728913 TX_PICG_NEW_MODE: ON
9177 10:07:09.732464 ENABLE_RX_DCM_DPHY: ON
9178 10:07:09.732571 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9179 10:07:09.735900 DUMMY_READ_FOR_TRACKING: OFF
9180 10:07:09.739085 !!! SPM_CONTROL_AFTERK: OFF
9181 10:07:09.742070 !!! SPM could not control APHY
9182 10:07:09.742152 IMPEDANCE_TRACKING: ON
9183 10:07:09.745749 TEMP_SENSOR: ON
9184 10:07:09.745827 HW_SAVE_FOR_SR: OFF
9185 10:07:09.749005 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9186 10:07:09.755543 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9187 10:07:09.755675 Read ODT Tracking: ON
9188 10:07:09.759102 Refresh Rate DeBounce: ON
9189 10:07:09.759216 DFS_NO_QUEUE_FLUSH: ON
9190 10:07:09.762109 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9191 10:07:09.765274 ENABLE_DFS_RUNTIME_MRW: OFF
9192 10:07:09.768854 DDR_RESERVE_NEW_MODE: ON
9193 10:07:09.768967 MR_CBT_SWITCH_FREQ: ON
9194 10:07:09.771898 =========================
9195 10:07:09.791544 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9196 10:07:09.794578 dram_init: ddr_geometry: 2
9197 10:07:09.812789 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9198 10:07:09.816086 dram_init: dram init end (result: 0)
9199 10:07:09.822847 DRAM-K: Full calibration passed in 24520 msecs
9200 10:07:09.826141 MRC: failed to locate region type 0.
9201 10:07:09.826260 DRAM rank0 size:0x100000000,
9202 10:07:09.829196 DRAM rank1 size=0x100000000
9203 10:07:09.839291 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9204 10:07:09.845848 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9205 10:07:09.852396 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9206 10:07:09.862165 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9207 10:07:09.862369 DRAM rank0 size:0x100000000,
9208 10:07:09.865619 DRAM rank1 size=0x100000000
9209 10:07:09.865766 CBMEM:
9210 10:07:09.869089 IMD: root @ 0xfffff000 254 entries.
9211 10:07:09.872130 IMD: root @ 0xffffec00 62 entries.
9212 10:07:09.875654 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9213 10:07:09.882227 WARNING: RO_VPD is uninitialized or empty.
9214 10:07:09.885186 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9215 10:07:09.893152 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9216 10:07:09.905754 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9217 10:07:09.916961 BS: romstage times (exec / console): total (unknown) / 24015 ms
9218 10:07:09.917105
9219 10:07:09.917175
9220 10:07:09.926887 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9221 10:07:09.930152 ARM64: Exception handlers installed.
9222 10:07:09.933499 ARM64: Testing exception
9223 10:07:09.936999 ARM64: Done test exception
9224 10:07:09.937096 Enumerating buses...
9225 10:07:09.940113 Show all devs... Before device enumeration.
9226 10:07:09.943565 Root Device: enabled 1
9227 10:07:09.946705 CPU_CLUSTER: 0: enabled 1
9228 10:07:09.946795 CPU: 00: enabled 1
9229 10:07:09.950064 Compare with tree...
9230 10:07:09.950153 Root Device: enabled 1
9231 10:07:09.953228 CPU_CLUSTER: 0: enabled 1
9232 10:07:09.956737 CPU: 00: enabled 1
9233 10:07:09.956890 Root Device scanning...
9234 10:07:09.959994 scan_static_bus for Root Device
9235 10:07:09.963088 CPU_CLUSTER: 0 enabled
9236 10:07:09.966651 scan_static_bus for Root Device done
9237 10:07:09.969758 scan_bus: bus Root Device finished in 8 msecs
9238 10:07:09.969857 done
9239 10:07:09.976351 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9240 10:07:09.979893 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9241 10:07:09.986441 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9242 10:07:09.989474 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9243 10:07:09.993201 Allocating resources...
9244 10:07:09.996144 Reading resources...
9245 10:07:09.999412 Root Device read_resources bus 0 link: 0
9246 10:07:10.002829 DRAM rank0 size:0x100000000,
9247 10:07:10.002929 DRAM rank1 size=0x100000000
9248 10:07:10.006436 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9249 10:07:10.009506 CPU: 00 missing read_resources
9250 10:07:10.016030 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9251 10:07:10.019646 Root Device read_resources bus 0 link: 0 done
9252 10:07:10.019746 Done reading resources.
9253 10:07:10.026138 Show resources in subtree (Root Device)...After reading.
9254 10:07:10.029530 Root Device child on link 0 CPU_CLUSTER: 0
9255 10:07:10.033082 CPU_CLUSTER: 0 child on link 0 CPU: 00
9256 10:07:10.042640 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9257 10:07:10.042758 CPU: 00
9258 10:07:10.046239 Root Device assign_resources, bus 0 link: 0
9259 10:07:10.049440 CPU_CLUSTER: 0 missing set_resources
9260 10:07:10.055740 Root Device assign_resources, bus 0 link: 0 done
9261 10:07:10.055858 Done setting resources.
9262 10:07:10.062651 Show resources in subtree (Root Device)...After assigning values.
9263 10:07:10.066108 Root Device child on link 0 CPU_CLUSTER: 0
9264 10:07:10.069141 CPU_CLUSTER: 0 child on link 0 CPU: 00
9265 10:07:10.079325 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9266 10:07:10.079464 CPU: 00
9267 10:07:10.082878 Done allocating resources.
9268 10:07:10.089149 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9269 10:07:10.089255 Enabling resources...
9270 10:07:10.089327 done.
9271 10:07:10.095566 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9272 10:07:10.095693 Initializing devices...
9273 10:07:10.099113 Root Device init
9274 10:07:10.099196 init hardware done!
9275 10:07:10.102411 0x00000018: ctrlr->caps
9276 10:07:10.105888 52.000 MHz: ctrlr->f_max
9277 10:07:10.105969 0.400 MHz: ctrlr->f_min
9278 10:07:10.109000 0x40ff8080: ctrlr->voltages
9279 10:07:10.112161 sclk: 390625
9280 10:07:10.112262 Bus Width = 1
9281 10:07:10.112330 sclk: 390625
9282 10:07:10.115667 Bus Width = 1
9283 10:07:10.115749 Early init status = 3
9284 10:07:10.122332 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9285 10:07:10.125415 in-header: 03 fc 00 00 01 00 00 00
9286 10:07:10.128708 in-data: 00
9287 10:07:10.132072 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9288 10:07:10.135641 in-header: 03 fd 00 00 00 00 00 00
9289 10:07:10.139144 in-data:
9290 10:07:10.142425 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9291 10:07:10.146241 in-header: 03 fc 00 00 01 00 00 00
9292 10:07:10.149385 in-data: 00
9293 10:07:10.152573 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9294 10:07:10.158159 in-header: 03 fd 00 00 00 00 00 00
9295 10:07:10.161356 in-data:
9296 10:07:10.164787 [SSUSB] Setting up USB HOST controller...
9297 10:07:10.167970 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9298 10:07:10.171198 [SSUSB] phy power-on done.
9299 10:07:10.174820 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9300 10:07:10.181341 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9301 10:07:10.184478 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9302 10:07:10.191044 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9303 10:07:10.197745 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9304 10:07:10.204290 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9305 10:07:10.210902 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9306 10:07:10.217246 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9307 10:07:10.220738 SPM: binary array size = 0x9dc
9308 10:07:10.224191 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9309 10:07:10.230600 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9310 10:07:10.237369 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9311 10:07:10.244039 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9312 10:07:10.247351 configure_display: Starting display init
9313 10:07:10.281029 anx7625_power_on_init: Init interface.
9314 10:07:10.284630 anx7625_disable_pd_protocol: Disabled PD feature.
9315 10:07:10.287788 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9316 10:07:10.315493 anx7625_start_dp_work: Secure OCM version=00
9317 10:07:10.318916 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9318 10:07:10.333658 sp_tx_get_edid_block: EDID Block = 1
9319 10:07:10.436203 Extracted contents:
9320 10:07:10.439723 header: 00 ff ff ff ff ff ff 00
9321 10:07:10.442891 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9322 10:07:10.446281 version: 01 04
9323 10:07:10.449685 basic params: 95 1f 11 78 0a
9324 10:07:10.452733 chroma info: 76 90 94 55 54 90 27 21 50 54
9325 10:07:10.455874 established: 00 00 00
9326 10:07:10.462992 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9327 10:07:10.466038 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9328 10:07:10.472430 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9329 10:07:10.479099 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9330 10:07:10.485850 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9331 10:07:10.488978 extensions: 00
9332 10:07:10.489071 checksum: fb
9333 10:07:10.489141
9334 10:07:10.492387 Manufacturer: IVO Model 57d Serial Number 0
9335 10:07:10.495929 Made week 0 of 2020
9336 10:07:10.496034 EDID version: 1.4
9337 10:07:10.498951 Digital display
9338 10:07:10.502636 6 bits per primary color channel
9339 10:07:10.502743 DisplayPort interface
9340 10:07:10.505768 Maximum image size: 31 cm x 17 cm
9341 10:07:10.508884 Gamma: 220%
9342 10:07:10.508964 Check DPMS levels
9343 10:07:10.512259 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9344 10:07:10.519025 First detailed timing is preferred timing
9345 10:07:10.519151 Established timings supported:
9346 10:07:10.522053 Standard timings supported:
9347 10:07:10.525413 Detailed timings
9348 10:07:10.528967 Hex of detail: 383680a07038204018303c0035ae10000019
9349 10:07:10.535759 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9350 10:07:10.539046 0780 0798 07c8 0820 hborder 0
9351 10:07:10.542046 0438 043b 0447 0458 vborder 0
9352 10:07:10.545681 -hsync -vsync
9353 10:07:10.545775 Did detailed timing
9354 10:07:10.552075 Hex of detail: 000000000000000000000000000000000000
9355 10:07:10.555181 Manufacturer-specified data, tag 0
9356 10:07:10.558701 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9357 10:07:10.561878 ASCII string: InfoVision
9358 10:07:10.565394 Hex of detail: 000000fe00523134304e574635205248200a
9359 10:07:10.568597 ASCII string: R140NWF5 RH
9360 10:07:10.568709 Checksum
9361 10:07:10.572248 Checksum: 0xfb (valid)
9362 10:07:10.575148 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9363 10:07:10.578649 DSI data_rate: 832800000 bps
9364 10:07:10.585067 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9365 10:07:10.588581 anx7625_parse_edid: pixelclock(138800).
9366 10:07:10.591713 hactive(1920), hsync(48), hfp(24), hbp(88)
9367 10:07:10.595302 vactive(1080), vsync(12), vfp(3), vbp(17)
9368 10:07:10.598378 anx7625_dsi_config: config dsi.
9369 10:07:10.605137 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9370 10:07:10.618507 anx7625_dsi_config: success to config DSI
9371 10:07:10.621699 anx7625_dp_start: MIPI phy setup OK.
9372 10:07:10.624872 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9373 10:07:10.628360 mtk_ddp_mode_set invalid vrefresh 60
9374 10:07:10.631698 main_disp_path_setup
9375 10:07:10.631803 ovl_layer_smi_id_en
9376 10:07:10.634785 ovl_layer_smi_id_en
9377 10:07:10.634871 ccorr_config
9378 10:07:10.634936 aal_config
9379 10:07:10.637975 gamma_config
9380 10:07:10.638084 postmask_config
9381 10:07:10.641442 dither_config
9382 10:07:10.644720 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9383 10:07:10.651524 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9384 10:07:10.654742 Root Device init finished in 552 msecs
9385 10:07:10.658033 CPU_CLUSTER: 0 init
9386 10:07:10.664399 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9387 10:07:10.668346 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9388 10:07:10.671314 APU_MBOX 0x190000b0 = 0x10001
9389 10:07:10.674457 APU_MBOX 0x190001b0 = 0x10001
9390 10:07:10.677948 APU_MBOX 0x190005b0 = 0x10001
9391 10:07:10.681097 APU_MBOX 0x190006b0 = 0x10001
9392 10:07:10.684642 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9393 10:07:10.697113 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9394 10:07:10.709967 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9395 10:07:10.716338 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9396 10:07:10.728192 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9397 10:07:10.736973 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9398 10:07:10.740313 CPU_CLUSTER: 0 init finished in 81 msecs
9399 10:07:10.743711 Devices initialized
9400 10:07:10.746928 Show all devs... After init.
9401 10:07:10.747035 Root Device: enabled 1
9402 10:07:10.750389 CPU_CLUSTER: 0: enabled 1
9403 10:07:10.753687 CPU: 00: enabled 1
9404 10:07:10.756977 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9405 10:07:10.760527 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9406 10:07:10.763448 ELOG: NV offset 0x57f000 size 0x1000
9407 10:07:10.770243 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9408 10:07:10.776633 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9409 10:07:10.780084 ELOG: Event(17) added with size 13 at 2023-06-10 10:07:08 UTC
9410 10:07:10.786741 out: cmd=0x121: 03 db 21 01 00 00 00 00
9411 10:07:10.789924 in-header: 03 1c 00 00 2c 00 00 00
9412 10:07:10.799755 in-data: 43 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9413 10:07:10.806482 ELOG: Event(A1) added with size 10 at 2023-06-10 10:07:08 UTC
9414 10:07:10.813230 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9415 10:07:10.819800 ELOG: Event(A0) added with size 9 at 2023-06-10 10:07:08 UTC
9416 10:07:10.822730 elog_add_boot_reason: Logged dev mode boot
9417 10:07:10.829489 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9418 10:07:10.829638 Finalize devices...
9419 10:07:10.832895 Devices finalized
9420 10:07:10.835903 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9421 10:07:10.839477 Writing coreboot table at 0xffe64000
9422 10:07:10.842533 0. 000000000010a000-0000000000113fff: RAMSTAGE
9423 10:07:10.849152 1. 0000000040000000-00000000400fffff: RAM
9424 10:07:10.852280 2. 0000000040100000-000000004032afff: RAMSTAGE
9425 10:07:10.855589 3. 000000004032b000-00000000545fffff: RAM
9426 10:07:10.858940 4. 0000000054600000-000000005465ffff: BL31
9427 10:07:10.862256 5. 0000000054660000-00000000ffe63fff: RAM
9428 10:07:10.868745 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9429 10:07:10.872030 7. 0000000100000000-000000023fffffff: RAM
9430 10:07:10.875495 Passing 5 GPIOs to payload:
9431 10:07:10.879148 NAME | PORT | POLARITY | VALUE
9432 10:07:10.885310 EC in RW | 0x000000aa | low | undefined
9433 10:07:10.888739 EC interrupt | 0x00000005 | low | undefined
9434 10:07:10.895383 TPM interrupt | 0x000000ab | high | undefined
9435 10:07:10.898524 SD card detect | 0x00000011 | high | undefined
9436 10:07:10.901910 speaker enable | 0x00000093 | high | undefined
9437 10:07:10.905024 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9438 10:07:10.908485 in-header: 03 f9 00 00 02 00 00 00
9439 10:07:10.911751 in-data: 02 00
9440 10:07:10.915269 ADC[4]: Raw value=900663 ID=7
9441 10:07:10.918459 ADC[3]: Raw value=213179 ID=1
9442 10:07:10.918545 RAM Code: 0x71
9443 10:07:10.921643 ADC[6]: Raw value=74502 ID=0
9444 10:07:10.925177 ADC[5]: Raw value=212072 ID=1
9445 10:07:10.925263 SKU Code: 0x1
9446 10:07:10.931539 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9447 10:07:10.931653 coreboot table: 964 bytes.
9448 10:07:10.934808 IMD ROOT 0. 0xfffff000 0x00001000
9449 10:07:10.938298 IMD SMALL 1. 0xffffe000 0x00001000
9450 10:07:10.941557 RO MCACHE 2. 0xffffc000 0x00001104
9451 10:07:10.944757 CONSOLE 3. 0xfff7c000 0x00080000
9452 10:07:10.948084 FMAP 4. 0xfff7b000 0x00000452
9453 10:07:10.951532 TIME STAMP 5. 0xfff7a000 0x00000910
9454 10:07:10.954525 VBOOT WORK 6. 0xfff66000 0x00014000
9455 10:07:10.958300 RAMOOPS 7. 0xffe66000 0x00100000
9456 10:07:10.961322 COREBOOT 8. 0xffe64000 0x00002000
9457 10:07:10.964917 IMD small region:
9458 10:07:10.967745 IMD ROOT 0. 0xffffec00 0x00000400
9459 10:07:10.971185 VPD 1. 0xffffeba0 0x0000004c
9460 10:07:10.974686 MMC STATUS 2. 0xffffeb80 0x00000004
9461 10:07:10.981223 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9462 10:07:10.981307 Probing TPM: done!
9463 10:07:10.987959 Connected to device vid:did:rid of 1ae0:0028:00
9464 10:07:10.994628 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9465 10:07:10.998064 Initialized TPM device CR50 revision 0
9466 10:07:11.001068 Checking cr50 for pending updates
9467 10:07:11.006639 Reading cr50 TPM mode
9468 10:07:11.015390 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9469 10:07:11.022038 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9470 10:07:11.061838 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9471 10:07:11.065191 Checking segment from ROM address 0x40100000
9472 10:07:11.068896 Checking segment from ROM address 0x4010001c
9473 10:07:11.075596 Loading segment from ROM address 0x40100000
9474 10:07:11.075682 code (compression=0)
9475 10:07:11.085293 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9476 10:07:11.092068 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9477 10:07:11.092147 it's not compressed!
9478 10:07:11.098504 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9479 10:07:11.101690 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9480 10:07:11.122450 Loading segment from ROM address 0x4010001c
9481 10:07:11.122544 Entry Point 0x80000000
9482 10:07:11.125408 Loaded segments
9483 10:07:11.128965 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9484 10:07:11.135533 Jumping to boot code at 0x80000000(0xffe64000)
9485 10:07:11.142071 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9486 10:07:11.148591 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9487 10:07:11.156777 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9488 10:07:11.160127 Checking segment from ROM address 0x40100000
9489 10:07:11.163505 Checking segment from ROM address 0x4010001c
9490 10:07:11.169971 Loading segment from ROM address 0x40100000
9491 10:07:11.170087 code (compression=1)
9492 10:07:11.176578 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9493 10:07:11.186350 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9494 10:07:11.186441 using LZMA
9495 10:07:11.195108 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9496 10:07:11.201972 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9497 10:07:11.204973 Loading segment from ROM address 0x4010001c
9498 10:07:11.205057 Entry Point 0x54601000
9499 10:07:11.208410 Loaded segments
9500 10:07:11.211680 NOTICE: MT8192 bl31_setup
9501 10:07:11.218851 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9502 10:07:11.222172 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9503 10:07:11.225228 WARNING: region 0:
9504 10:07:11.228913 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9505 10:07:11.228984 WARNING: region 1:
9506 10:07:11.235534 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9507 10:07:11.238457 WARNING: region 2:
9508 10:07:11.241810 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9509 10:07:11.245018 WARNING: region 3:
9510 10:07:11.248523 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9511 10:07:11.252069 WARNING: region 4:
9512 10:07:11.258335 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9513 10:07:11.258409 WARNING: region 5:
9514 10:07:11.261831 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9515 10:07:11.264989 WARNING: region 6:
9516 10:07:11.268360 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9517 10:07:11.271967 WARNING: region 7:
9518 10:07:11.275198 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9519 10:07:11.281594 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9520 10:07:11.284640 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9521 10:07:11.291277 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9522 10:07:11.294755 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9523 10:07:11.297948 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9524 10:07:11.304698 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9525 10:07:11.308165 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9526 10:07:11.311153 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9527 10:07:11.318249 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9528 10:07:11.321333 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9529 10:07:11.324615 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9530 10:07:11.331174 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9531 10:07:11.334841 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9532 10:07:11.341379 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9533 10:07:11.344310 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9534 10:07:11.347918 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9535 10:07:11.354568 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9536 10:07:11.357733 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9537 10:07:11.364556 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9538 10:07:11.367582 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9539 10:07:11.371095 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9540 10:07:11.377673 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9541 10:07:11.381194 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9542 10:07:11.383990 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9543 10:07:11.390716 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9544 10:07:11.394187 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9545 10:07:13.073460 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9546 10:07:13.073636 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9547 10:07:13.073717 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9548 10:07:13.073788 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9549 10:07:13.073858 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9550 10:07:13.073920 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9551 10:07:13.073986 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9552 10:07:13.074097 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9553 10:07:13.074200 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9554 10:07:13.074288 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9555 10:07:13.074361 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9556 10:07:13.074422 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9557 10:07:13.074481 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9558 10:07:13.074539 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9559 10:07:13.074602 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9560 10:07:13.074659 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9561 10:07:13.074716 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9562 10:07:13.074773 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9563 10:07:13.074844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9564 10:07:13.074904 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9565 10:07:13.074962 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9566 10:07:13.075025 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9567 10:07:13.075088 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9568 10:07:13.075145 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9569 10:07:13.075200 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9570 10:07:13.075256 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9571 10:07:13.075312 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9572 10:07:13.075382 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9573 10:07:13.075439 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9574 10:07:13.075495 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9575 10:07:13.075552 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9576 10:07:13.075618 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9577 10:07:13.075675 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9578 10:07:13.075731 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9579 10:07:13.075786 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9580 10:07:13.075841 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9581 10:07:13.075904 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9582 10:07:13.075960 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9583 10:07:13.076015 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9584 10:07:13.076071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9585 10:07:13.076134 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9586 10:07:13.076191 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9587 10:07:13.076247 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9588 10:07:13.076302 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9589 10:07:13.076373 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9590 10:07:13.076433 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9591 10:07:13.076490 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9592 10:07:13.076551 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9593 10:07:13.076615 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9594 10:07:13.076673 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9595 10:07:13.076728 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9596 10:07:13.076821 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9597 10:07:13.076885 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9598 10:07:13.076940 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9599 10:07:13.076994 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9600 10:07:13.077048 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9601 10:07:13.077109 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9602 10:07:13.077164 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9603 10:07:13.077217 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9604 10:07:13.077271 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9605 10:07:13.077336 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9606 10:07:13.077395 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9607 10:07:13.077451 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9608 10:07:13.077509 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9609 10:07:13.077565 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9610 10:07:13.077626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9611 10:07:13.077680 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9612 10:07:13.077734 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9613 10:07:13.077788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9614 10:07:13.077841 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9615 10:07:13.077902 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9616 10:07:13.077957 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9617 10:07:13.078010 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9618 10:07:13.078064 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9619 10:07:13.078117 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9620 10:07:13.078178 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9621 10:07:13.078231 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9622 10:07:13.078474 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9623 10:07:13.078540 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9624 10:07:13.078652 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9625 10:07:13.078724 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9626 10:07:13.078779 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9627 10:07:13.078833 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9628 10:07:13.078895 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9629 10:07:13.078949 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9630 10:07:13.079003 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9631 10:07:13.079057 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9632 10:07:13.079111 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9633 10:07:13.079173 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9634 10:07:13.079226 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9635 10:07:13.079280 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9636 10:07:13.079334 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9637 10:07:13.079402 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9638 10:07:13.079459 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9639 10:07:13.079515 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9640 10:07:13.079590 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9641 10:07:13.079659 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9642 10:07:13.079724 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9643 10:07:13.079780 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9644 10:07:13.079834 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9645 10:07:13.079888 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9646 10:07:13.079944 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9647 10:07:13.079998 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9648 10:07:13.080052 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9649 10:07:13.080112 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9650 10:07:13.080166 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9651 10:07:13.080244 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9652 10:07:13.080340 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9653 10:07:13.080394 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9654 10:07:13.080455 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9655 10:07:13.080509 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9656 10:07:13.080563 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9657 10:07:13.080617 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9658 10:07:13.080683 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9659 10:07:13.080741 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9660 10:07:13.080840 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9661 10:07:13.080896 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9662 10:07:13.080958 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9663 10:07:13.081013 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9664 10:07:13.081066 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9665 10:07:13.081120 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9666 10:07:13.081180 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9667 10:07:13.081235 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9668 10:07:13.081288 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9669 10:07:13.081342 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9670 10:07:13.081396 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9671 10:07:13.081465 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9672 10:07:13.081522 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9673 10:07:13.081579 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9674 10:07:13.081635 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9675 10:07:13.081688 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9676 10:07:13.081750 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9677 10:07:13.081804 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9678 10:07:13.081858 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9679 10:07:13.081911 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9680 10:07:13.081972 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9681 10:07:13.082027 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9682 10:07:13.082081 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9683 10:07:13.082134 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9684 10:07:13.082188 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9685 10:07:13.082248 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9686 10:07:13.082302 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9687 10:07:13.082356 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9688 10:07:13.082410 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9689 10:07:13.082477 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9690 10:07:13.082535 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9691 10:07:13.082642 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9692 10:07:13.082720 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9693 10:07:13.082775 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9694 10:07:13.082828 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9695 10:07:13.082882 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9696 10:07:13.082959 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9697 10:07:13.083059 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9698 10:07:13.083113 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9699 10:07:13.083400 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9700 10:07:13.083477 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9701 10:07:13.083553 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9702 10:07:13.083625 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9703 10:07:13.083688 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9704 10:07:13.083746 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9705 10:07:13.083801 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9706 10:07:13.083857 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9707 10:07:13.083912 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9708 10:07:13.083973 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9709 10:07:13.084030 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9710 10:07:13.084086 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9711 10:07:13.084141 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9712 10:07:13.084197 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9713 10:07:13.084259 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9714 10:07:13.084314 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9715 10:07:13.084370 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9716 10:07:13.084425 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9717 10:07:13.084495 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9718 10:07:13.084554 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9719 10:07:13.084610 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9720 10:07:13.084671 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9721 10:07:13.084733 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9722 10:07:13.084811 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9723 10:07:13.084866 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9724 10:07:13.084920 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9725 10:07:13.084981 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9726 10:07:13.085036 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9727 10:07:13.085091 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9728 10:07:13.085144 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9729 10:07:13.085204 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9730 10:07:13.085259 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9731 10:07:13.085313 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9732 10:07:13.085367 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9733 10:07:13.085421 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9734 10:07:13.085482 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9735 10:07:13.085536 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9736 10:07:13.085590 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9737 10:07:13.085643 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9738 10:07:13.085697 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9739 10:07:13.085750 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9740 10:07:13.085819 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9741 10:07:13.085875 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9742 10:07:13.085933 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9743 10:07:13.085989 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9744 10:07:13.086077 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9745 10:07:13.086132 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9746 10:07:13.086185 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9747 10:07:13.086238 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9748 10:07:13.086299 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9749 10:07:13.086353 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9750 10:07:13.086408 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9751 10:07:13.086461 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9752 10:07:13.086521 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9753 10:07:13.086576 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9754 10:07:13.086629 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9755 10:07:13.086683 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9756 10:07:13.086736 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9757 10:07:13.086807 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9758 10:07:13.086863 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9759 10:07:13.086922 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9760 10:07:13.086978 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9761 10:07:13.087039 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9762 10:07:13.087093 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9763 10:07:13.087147 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9764 10:07:13.087200 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9765 10:07:13.087261 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9766 10:07:13.087316 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9767 10:07:13.087370 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9768 10:07:13.087423 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9769 10:07:13.087477 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9770 10:07:13.087545 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9771 10:07:13.087603 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9772 10:07:13.087659 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9773 10:07:13.087712 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9774 10:07:13.087766 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9775 10:07:13.087827 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9776 10:07:13.088066 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9777 10:07:13.088130 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9778 10:07:13.088185 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9779 10:07:13.088240 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9780 10:07:13.088302 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9781 10:07:13.088357 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9782 10:07:13.088411 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9783 10:07:13.088464 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9784 10:07:13.088518 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9785 10:07:13.088589 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9786 10:07:13.088645 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9787 10:07:13.088703 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9788 10:07:13.088759 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9789 10:07:13.088868 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9790 10:07:13.088923 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9791 10:07:13.088977 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9792 10:07:13.089038 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9793 10:07:13.089093 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9794 10:07:13.089147 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9795 10:07:13.089201 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9796 10:07:13.089260 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9797 10:07:13.089331 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9798 10:07:13.089428 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9799 10:07:13.089499 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9800 10:07:13.089583 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9801 10:07:13.089639 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9802 10:07:13.089698 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9803 10:07:13.089761 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9804 10:07:13.089816 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9805 10:07:13.089869 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9806 10:07:13.089923 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9807 10:07:13.089994 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9808 10:07:13.090056 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9809 10:07:13.090127 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9810 10:07:13.090210 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9811 10:07:13.090263 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9812 10:07:13.090324 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9813 10:07:13.090425 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9814 10:07:13.090480 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9815 10:07:13.090547 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9816 10:07:13.090607 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9817 10:07:13.090664 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9818 10:07:13.090725 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9819 10:07:13.090786 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9820 10:07:13.090843 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9821 10:07:13.090898 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9822 10:07:13.090953 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9823 10:07:13.091007 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9824 10:07:13.091069 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9825 10:07:13.091125 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9826 10:07:13.091179 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9827 10:07:13.091241 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9828 10:07:13.091318 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9829 10:07:13.091375 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9830 10:07:13.091430 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9831 10:07:13.091486 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9832 10:07:13.091548 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9833 10:07:13.091604 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9834 10:07:13.091659 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9835 10:07:13.091714 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9836 10:07:13.091769 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9837 10:07:13.091841 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9838 10:07:13.091901 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9839 10:07:13.091957 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9840 10:07:13.092012 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9841 10:07:13.092066 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9842 10:07:13.092131 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9843 10:07:13.092186 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9844 10:07:13.092241 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9845 10:07:13.092303 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9846 10:07:13.092367 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9847 10:07:13.092466 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9848 10:07:13.092555 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9849 10:07:13.092641 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9850 10:07:13.092735 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9851 10:07:13.092824 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9852 10:07:13.092898 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9853 10:07:13.093136 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9854 10:07:13.093214 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9855 10:07:13.093337 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9856 10:07:13.093408 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9857 10:07:13.093464 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9858 10:07:13.093518 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9859 10:07:13.093583 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9860 10:07:13.093642 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9861 10:07:13.093699 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9862 10:07:13.093757 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9863 10:07:13.093813 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9864 10:07:13.093873 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9865 10:07:13.093929 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9866 10:07:13.093983 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9867 10:07:13.094037 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9868 10:07:13.094091 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9869 10:07:13.094153 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9870 10:07:13.094206 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9871 10:07:13.094260 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9872 10:07:13.094314 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9873 10:07:13.094391 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9874 10:07:13.094506 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9875 10:07:13.094574 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9876 10:07:13.094645 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9877 10:07:13.094701 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9878 10:07:13.094790 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9879 10:07:13.094869 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9880 10:07:13.094953 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9881 10:07:13.095008 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9882 10:07:13.095077 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9883 10:07:13.095155 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9884 10:07:13.095210 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9885 10:07:13.095265 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9886 10:07:13.095320 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9887 10:07:13.095382 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9888 10:07:13.095437 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9889 10:07:13.095492 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9890 10:07:13.095547 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9891 10:07:13.095616 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9892 10:07:13.095677 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9893 10:07:13.095734 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9894 10:07:13.095789 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9895 10:07:13.095851 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9896 10:07:13.095908 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9897 10:07:13.095963 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9898 10:07:13.096018 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9899 10:07:13.096072 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9900 10:07:13.096134 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9901 10:07:13.096191 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9902 10:07:13.096246 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9903 10:07:13.096300 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9904 10:07:13.096356 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9905 10:07:13.096417 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9906 10:07:13.096472 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9907 10:07:13.096527 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9908 10:07:13.096582 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9909 10:07:13.096652 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9910 10:07:13.096711 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9911 10:07:13.096773 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9912 10:07:13.096835 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9913 10:07:13.096913 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9914 10:07:13.099176 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9915 10:07:13.106228 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9916 10:07:13.109561 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9917 10:07:13.116204 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9918 10:07:13.119102 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9919 10:07:13.125822 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9920 10:07:13.128968 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9921 10:07:13.132485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9922 10:07:13.138747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9923 10:07:13.142280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9924 10:07:13.149077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9925 10:07:13.152069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9926 10:07:13.158629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9927 10:07:13.162227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9928 10:07:13.168562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9929 10:07:13.171703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9930 10:07:13.178465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9931 10:07:13.182083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9932 10:07:13.188294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9933 10:07:13.191894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9934 10:07:13.198512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9935 10:07:13.201397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9936 10:07:13.208298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9937 10:07:13.211381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9938 10:07:13.218041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9939 10:07:13.221092 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9940 10:07:13.227578 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9941 10:07:13.231091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9942 10:07:13.237595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9943 10:07:13.241104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9944 10:07:13.247547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9945 10:07:13.250991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9946 10:07:13.257736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9947 10:07:13.260646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9948 10:07:13.267387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9949 10:07:13.270843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9950 10:07:13.277189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9951 10:07:13.280477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9952 10:07:13.287157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9953 10:07:13.290682 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9954 10:07:13.293697 INFO: [APUAPC] vio 0
9955 10:07:13.297244 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9956 10:07:13.303707 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9957 10:07:13.307138 INFO: [APUAPC] D0_APC_0: 0x400510
9958 10:07:13.307221 INFO: [APUAPC] D0_APC_1: 0x0
9959 10:07:13.310328 INFO: [APUAPC] D0_APC_2: 0x1540
9960 10:07:13.313704 INFO: [APUAPC] D0_APC_3: 0x0
9961 10:07:13.316800 INFO: [APUAPC] D1_APC_0: 0xffffffff
9962 10:07:13.320226 INFO: [APUAPC] D1_APC_1: 0xffffffff
9963 10:07:13.323470 INFO: [APUAPC] D1_APC_2: 0x3fffff
9964 10:07:13.326536 INFO: [APUAPC] D1_APC_3: 0x0
9965 10:07:13.330078 INFO: [APUAPC] D2_APC_0: 0xffffffff
9966 10:07:13.333706 INFO: [APUAPC] D2_APC_1: 0xffffffff
9967 10:07:13.336596 INFO: [APUAPC] D2_APC_2: 0x3fffff
9968 10:07:13.339888 INFO: [APUAPC] D2_APC_3: 0x0
9969 10:07:13.343355 INFO: [APUAPC] D3_APC_0: 0xffffffff
9970 10:07:13.346506 INFO: [APUAPC] D3_APC_1: 0xffffffff
9971 10:07:13.349972 INFO: [APUAPC] D3_APC_2: 0x3fffff
9972 10:07:13.353409 INFO: [APUAPC] D3_APC_3: 0x0
9973 10:07:13.356513 INFO: [APUAPC] D4_APC_0: 0xffffffff
9974 10:07:13.360240 INFO: [APUAPC] D4_APC_1: 0xffffffff
9975 10:07:13.363283 INFO: [APUAPC] D4_APC_2: 0x3fffff
9976 10:07:13.366447 INFO: [APUAPC] D4_APC_3: 0x0
9977 10:07:13.369983 INFO: [APUAPC] D5_APC_0: 0xffffffff
9978 10:07:13.373011 INFO: [APUAPC] D5_APC_1: 0xffffffff
9979 10:07:13.376408 INFO: [APUAPC] D5_APC_2: 0x3fffff
9980 10:07:13.379619 INFO: [APUAPC] D5_APC_3: 0x0
9981 10:07:13.383074 INFO: [APUAPC] D6_APC_0: 0xffffffff
9982 10:07:13.386521 INFO: [APUAPC] D6_APC_1: 0xffffffff
9983 10:07:13.389689 INFO: [APUAPC] D6_APC_2: 0x3fffff
9984 10:07:13.392852 INFO: [APUAPC] D6_APC_3: 0x0
9985 10:07:13.396298 INFO: [APUAPC] D7_APC_0: 0xffffffff
9986 10:07:13.399368 INFO: [APUAPC] D7_APC_1: 0xffffffff
9987 10:07:13.402537 INFO: [APUAPC] D7_APC_2: 0x3fffff
9988 10:07:13.406062 INFO: [APUAPC] D7_APC_3: 0x0
9989 10:07:13.409636 INFO: [APUAPC] D8_APC_0: 0xffffffff
9990 10:07:13.413085 INFO: [APUAPC] D8_APC_1: 0xffffffff
9991 10:07:13.416054 INFO: [APUAPC] D8_APC_2: 0x3fffff
9992 10:07:13.419156 INFO: [APUAPC] D8_APC_3: 0x0
9993 10:07:13.422365 INFO: [APUAPC] D9_APC_0: 0xffffffff
9994 10:07:13.425710 INFO: [APUAPC] D9_APC_1: 0xffffffff
9995 10:07:13.428994 INFO: [APUAPC] D9_APC_2: 0x3fffff
9996 10:07:13.432388 INFO: [APUAPC] D9_APC_3: 0x0
9997 10:07:13.435764 INFO: [APUAPC] D10_APC_0: 0xffffffff
9998 10:07:13.439062 INFO: [APUAPC] D10_APC_1: 0xffffffff
9999 10:07:13.442660 INFO: [APUAPC] D10_APC_2: 0x3fffff
10000 10:07:13.445774 INFO: [APUAPC] D10_APC_3: 0x0
10001 10:07:13.449180 INFO: [APUAPC] D11_APC_0: 0xffffffff
10002 10:07:13.452218 INFO: [APUAPC] D11_APC_1: 0xffffffff
10003 10:07:13.455434 INFO: [APUAPC] D11_APC_2: 0x3fffff
10004 10:07:13.458984 INFO: [APUAPC] D11_APC_3: 0x0
10005 10:07:13.461981 INFO: [APUAPC] D12_APC_0: 0xffffffff
10006 10:07:13.465225 INFO: [APUAPC] D12_APC_1: 0xffffffff
10007 10:07:13.468751 INFO: [APUAPC] D12_APC_2: 0x3fffff
10008 10:07:13.471808 INFO: [APUAPC] D12_APC_3: 0x0
10009 10:07:13.475276 INFO: [APUAPC] D13_APC_0: 0xffffffff
10010 10:07:13.478425 INFO: [APUAPC] D13_APC_1: 0xffffffff
10011 10:07:13.481820 INFO: [APUAPC] D13_APC_2: 0x3fffff
10012 10:07:13.485452 INFO: [APUAPC] D13_APC_3: 0x0
10013 10:07:13.488489 INFO: [APUAPC] D14_APC_0: 0xffffffff
10014 10:07:13.491667 INFO: [APUAPC] D14_APC_1: 0xffffffff
10015 10:07:13.495320 INFO: [APUAPC] D14_APC_2: 0x3fffff
10016 10:07:13.498438 INFO: [APUAPC] D14_APC_3: 0x0
10017 10:07:13.501441 INFO: [APUAPC] D15_APC_0: 0xffffffff
10018 10:07:13.505101 INFO: [APUAPC] D15_APC_1: 0xffffffff
10019 10:07:13.508372 INFO: [APUAPC] D15_APC_2: 0x3fffff
10020 10:07:13.511439 INFO: [APUAPC] D15_APC_3: 0x0
10021 10:07:13.514968 INFO: [APUAPC] APC_CON: 0x4
10022 10:07:13.518274 INFO: [NOCDAPC] D0_APC_0: 0x0
10023 10:07:13.521533 INFO: [NOCDAPC] D0_APC_1: 0x0
10024 10:07:13.524845 INFO: [NOCDAPC] D1_APC_0: 0x0
10025 10:07:13.524951 INFO: [NOCDAPC] D1_APC_1: 0xfff
10026 10:07:13.528116 INFO: [NOCDAPC] D2_APC_0: 0x0
10027 10:07:13.531084 INFO: [NOCDAPC] D2_APC_1: 0xfff
10028 10:07:13.534569 INFO: [NOCDAPC] D3_APC_0: 0x0
10029 10:07:13.537926 INFO: [NOCDAPC] D3_APC_1: 0xfff
10030 10:07:13.541085 INFO: [NOCDAPC] D4_APC_0: 0x0
10031 10:07:13.544527 INFO: [NOCDAPC] D4_APC_1: 0xfff
10032 10:07:13.547969 INFO: [NOCDAPC] D5_APC_0: 0x0
10033 10:07:13.551237 INFO: [NOCDAPC] D5_APC_1: 0xfff
10034 10:07:13.554229 INFO: [NOCDAPC] D6_APC_0: 0x0
10035 10:07:13.557701 INFO: [NOCDAPC] D6_APC_1: 0xfff
10036 10:07:13.561238 INFO: [NOCDAPC] D7_APC_0: 0x0
10037 10:07:13.561345 INFO: [NOCDAPC] D7_APC_1: 0xfff
10038 10:07:13.564004 INFO: [NOCDAPC] D8_APC_0: 0x0
10039 10:07:13.567646 INFO: [NOCDAPC] D8_APC_1: 0xfff
10040 10:07:13.570551 INFO: [NOCDAPC] D9_APC_0: 0x0
10041 10:07:13.574180 INFO: [NOCDAPC] D9_APC_1: 0xfff
10042 10:07:13.577707 INFO: [NOCDAPC] D10_APC_0: 0x0
10043 10:07:13.580954 INFO: [NOCDAPC] D10_APC_1: 0xfff
10044 10:07:13.583926 INFO: [NOCDAPC] D11_APC_0: 0x0
10045 10:07:13.587551 INFO: [NOCDAPC] D11_APC_1: 0xfff
10046 10:07:13.590586 INFO: [NOCDAPC] D12_APC_0: 0x0
10047 10:07:13.594191 INFO: [NOCDAPC] D12_APC_1: 0xfff
10048 10:07:13.597401 INFO: [NOCDAPC] D13_APC_0: 0x0
10049 10:07:13.600875 INFO: [NOCDAPC] D13_APC_1: 0xfff
10050 10:07:13.600961 INFO: [NOCDAPC] D14_APC_0: 0x0
10051 10:07:13.604066 INFO: [NOCDAPC] D14_APC_1: 0xfff
10052 10:07:13.607206 INFO: [NOCDAPC] D15_APC_0: 0x0
10053 10:07:13.610695 INFO: [NOCDAPC] D15_APC_1: 0xfff
10054 10:07:13.613896 INFO: [NOCDAPC] APC_CON: 0x4
10055 10:07:13.617321 INFO: [APUAPC] set_apusys_apc done
10056 10:07:13.620435 INFO: [DEVAPC] devapc_init done
10057 10:07:13.623764 INFO: GICv3 without legacy support detected.
10058 10:07:13.630453 INFO: ARM GICv3 driver initialized in EL3
10059 10:07:13.633629 INFO: Maximum SPI INTID supported: 639
10060 10:07:13.636802 INFO: BL31: Initializing runtime services
10061 10:07:13.643683 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10062 10:07:13.646578 INFO: SPM: enable CPC mode
10063 10:07:13.649886 INFO: mcdi ready for mcusys-off-idle and system suspend
10064 10:07:13.656782 INFO: BL31: Preparing for EL3 exit to normal world
10065 10:07:13.659973 INFO: Entry point address = 0x80000000
10066 10:07:13.660091 INFO: SPSR = 0x8
10067 10:07:13.666786
10068 10:07:13.666879
10069 10:07:13.666967
10070 10:07:13.670181 Starting depthcharge on Spherion...
10071 10:07:13.670264
10072 10:07:13.670348 Wipe memory regions:
10073 10:07:13.670434
10074 10:07:13.671060 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10075 10:07:13.671181 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10076 10:07:13.671278 Setting prompt string to ['asurada:']
10077 10:07:13.671370 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10078 10:07:13.673468 [0x00000040000000, 0x00000054600000)
10079 10:07:13.795544
10080 10:07:13.795705 [0x00000054660000, 0x00000080000000)
10081 10:07:14.055431
10082 10:07:14.055619 [0x000000821a7280, 0x000000ffe64000)
10083 10:07:14.799527
10084 10:07:14.799692 [0x00000100000000, 0x00000240000000)
10085 10:07:16.685884
10086 10:07:16.689030 Initializing XHCI USB controller at 0x11200000.
10087 10:07:17.726881
10088 10:07:17.730041 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10089 10:07:17.730136
10090 10:07:17.730206
10091 10:07:17.730270
10092 10:07:17.730551 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10094 10:07:17.830898 asurada: tftpboot 192.168.201.1 10670702/tftp-deploy-vgedlg5m/kernel/image.itb 10670702/tftp-deploy-vgedlg5m/kernel/cmdline
10095 10:07:17.831093 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10096 10:07:17.831188 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10097 10:07:17.835361 tftpboot 192.168.201.1 10670702/tftp-deploy-vgedlg5m/kernel/image.itp-deploy-vgedlg5m/kernel/cmdline
10098 10:07:17.835452
10099 10:07:17.835521 Waiting for link
10100 10:07:17.995595
10101 10:07:17.995768 R8152: Initializing
10102 10:07:17.995857
10103 10:07:17.998832 Version 9 (ocp_data = 6010)
10104 10:07:17.998941
10105 10:07:18.001986 R8152: Done initializing
10106 10:07:18.002104
10107 10:07:18.002198 Adding net device
10108 10:07:19.948493
10109 10:07:19.948660 done.
10110 10:07:19.948735
10111 10:07:19.948849 MAC: 00:e0:4c:72:2d:d6
10112 10:07:19.948911
10113 10:07:19.951424 Sending DHCP discover... done.
10114 10:07:19.951510
10115 10:07:19.954856 Waiting for reply... done.
10116 10:07:19.954941
10117 10:07:19.958195 Sending DHCP request... done.
10118 10:07:19.958280
10119 10:07:22.020406 Waiting for reply... done.
10120 10:07:22.020589
10121 10:07:22.020693 My ip is 192.168.201.21
10122 10:07:22.020799
10123 10:07:22.023567 The DHCP server ip is 192.168.201.1
10124 10:07:22.023682
10125 10:07:22.030487 TFTP server IP predefined by user: 192.168.201.1
10126 10:07:22.030612
10127 10:07:22.037018 Bootfile predefined by user: 10670702/tftp-deploy-vgedlg5m/kernel/image.itb
10128 10:07:22.037110
10129 10:07:22.040244 Sending tftp read request... done.
10130 10:07:22.040363
10131 10:07:22.043458 Waiting for the transfer...
10132 10:07:22.043574
10133 10:07:22.315220 00000000 ################################################################
10134 10:07:22.315378
10135 10:07:22.588018 00080000 ################################################################
10136 10:07:22.588175
10137 10:07:22.894291 00100000 ################################################################
10138 10:07:22.894473
10139 10:07:23.176883 00180000 ################################################################
10140 10:07:23.177036
10141 10:07:23.455888 00200000 ################################################################
10142 10:07:23.456032
10143 10:07:23.731261 00280000 ################################################################
10144 10:07:23.731441
10145 10:07:24.003933 00300000 ################################################################
10146 10:07:24.004126
10147 10:07:24.288722 00380000 ################################################################
10148 10:07:24.288871
10149 10:07:24.564689 00400000 ################################################################
10150 10:07:24.564870
10151 10:07:24.852518 00480000 ################################################################
10152 10:07:24.852683
10153 10:07:25.132537 00500000 ################################################################
10154 10:07:25.132674
10155 10:07:25.421473 00580000 ################################################################
10156 10:07:25.421618
10157 10:07:25.708120 00600000 ################################################################
10158 10:07:25.708319
10159 10:07:26.018280 00680000 ################################################################
10160 10:07:26.018440
10161 10:07:26.315305 00700000 ################################################################
10162 10:07:26.315454
10163 10:07:26.589212 00780000 ################################################################
10164 10:07:26.589364
10165 10:07:26.863590 00800000 ################################################################
10166 10:07:26.863743
10167 10:07:27.155472 00880000 ################################################################
10168 10:07:27.155656
10169 10:07:27.433629 00900000 ################################################################
10170 10:07:27.433822
10171 10:07:27.699323 00980000 ################################################################
10172 10:07:27.699509
10173 10:07:27.980422 00a00000 ################################################################
10174 10:07:27.980611
10175 10:07:28.260441 00a80000 ################################################################
10176 10:07:28.260606
10177 10:07:28.510171 00b00000 ################################################################
10178 10:07:28.510321
10179 10:07:28.780534 00b80000 ################################################################
10180 10:07:28.780690
10181 10:07:29.046719 00c00000 ################################################################
10182 10:07:29.046897
10183 10:07:29.293886 00c80000 ################################################################
10184 10:07:29.294037
10185 10:07:29.559523 00d00000 ################################################################
10186 10:07:29.559703
10187 10:07:29.810759 00d80000 ################################################################
10188 10:07:29.810936
10189 10:07:30.063919 00e00000 ################################################################
10190 10:07:30.064066
10191 10:07:30.311293 00e80000 ################################################################
10192 10:07:30.311443
10193 10:07:30.573491 00f00000 ################################################################
10194 10:07:30.573636
10195 10:07:30.820758 00f80000 ################################################################
10196 10:07:30.820937
10197 10:07:31.079521 01000000 ################################################################
10198 10:07:31.079701
10199 10:07:31.330654 01080000 ################################################################
10200 10:07:31.330799
10201 10:07:31.580165 01100000 ################################################################
10202 10:07:31.580363
10203 10:07:31.826015 01180000 ################################################################
10204 10:07:31.826164
10205 10:07:32.072368 01200000 ################################################################
10206 10:07:32.072525
10207 10:07:32.330713 01280000 ################################################################
10208 10:07:32.330868
10209 10:07:32.592745 01300000 ################################################################
10210 10:07:32.592900
10211 10:07:32.842267 01380000 ################################################################
10212 10:07:32.842425
10213 10:07:33.087780 01400000 ################################################################
10214 10:07:33.087957
10215 10:07:33.340162 01480000 ################################################################
10216 10:07:33.340314
10217 10:07:33.599617 01500000 ################################################################
10218 10:07:33.599827
10219 10:07:33.847403 01580000 ################################################################
10220 10:07:33.847581
10221 10:07:34.106548 01600000 ################################################################
10222 10:07:34.106723
10223 10:07:34.353082 01680000 ################################################################
10224 10:07:34.353262
10225 10:07:34.604894 01700000 ################################################################
10226 10:07:34.605041
10227 10:07:34.866535 01780000 ################################################################
10228 10:07:34.866693
10229 10:07:35.126330 01800000 ################################################################
10230 10:07:35.126510
10231 10:07:35.386606 01880000 ################################################################
10232 10:07:35.386745
10233 10:07:35.636083 01900000 ################################################################
10234 10:07:35.636226
10235 10:07:35.883008 01980000 ################################################################
10236 10:07:35.883161
10237 10:07:36.124470 01a00000 ################################################################ done.
10238 10:07:36.124647
10239 10:07:36.128170 The bootfile was 27782078 bytes long.
10240 10:07:36.128272
10241 10:07:36.131141 Sending tftp read request... done.
10242 10:07:36.131242
10243 10:07:36.134402 Waiting for the transfer...
10244 10:07:36.134501
10245 10:07:36.134596 00000000 # done.
10246 10:07:36.134687
10247 10:07:36.144306 Command line loaded dynamically from TFTP file: 10670702/tftp-deploy-vgedlg5m/kernel/cmdline
10248 10:07:36.144411
10249 10:07:36.164501 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10670702/extract-nfsrootfs-897hv1o9,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10250 10:07:36.164621
10251 10:07:36.164717 Loading FIT.
10252 10:07:36.164824
10253 10:07:36.167494 Image ramdisk-1 has 17645802 bytes.
10254 10:07:36.167591
10255 10:07:36.170795 Image fdt-1 has 46924 bytes.
10256 10:07:36.170894
10257 10:07:36.174011 Image kernel-1 has 10087317 bytes.
10258 10:07:36.174113
10259 10:07:36.180682 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10260 10:07:36.183939
10261 10:07:36.200394 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10262 10:07:36.200505
10263 10:07:36.203561 Choosing best match conf-1 for compat google,spherion-rev2.
10264 10:07:36.209151
10265 10:07:36.213388 Connected to device vid:did:rid of 1ae0:0028:00
10266 10:07:36.220995
10267 10:07:36.224209 tpm_get_response: command 0x17b, return code 0x0
10268 10:07:36.224313
10269 10:07:36.230517 ec_init: CrosEC protocol v3 supported (256, 248)
10270 10:07:36.230620
10271 10:07:36.234167 tpm_cleanup: add release locality here.
10272 10:07:36.234266
10273 10:07:36.237563 Shutting down all USB controllers.
10274 10:07:36.237663
10275 10:07:36.241036 Removing current net device
10276 10:07:36.241136
10277 10:07:36.244279 Exiting depthcharge with code 4 at timestamp: 51896857
10278 10:07:36.244383
10279 10:07:36.247160 LZMA decompressing kernel-1 to 0x821a6718
10280 10:07:36.250495
10281 10:07:36.253946 LZMA decompressing kernel-1 to 0x40000000
10282 10:07:37.520688
10283 10:07:37.520871 jumping to kernel
10284 10:07:37.521526 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10285 10:07:37.521658 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10286 10:07:37.521772 Setting prompt string to ['Linux version [0-9]']
10287 10:07:37.521873 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10288 10:07:37.521986 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10289 10:07:37.602121
10290 10:07:37.605191 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10291 10:07:37.608968 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10292 10:07:37.609097 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10293 10:07:37.609214 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10294 10:07:37.609323 Using line separator: #'\n'#
10295 10:07:37.609418 No login prompt set.
10296 10:07:37.609511 Parsing kernel messages
10297 10:07:37.609607 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10298 10:07:37.609779 [login-action] Waiting for messages, (timeout 00:04:01)
10299 10:07:37.628304 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j19381-arm64-gcc-10-defconfig-arm64-chromebook-d6qsg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023
10300 10:07:37.631595 [ 0.000000] random: crng init done
10301 10:07:37.635078 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10302 10:07:37.638494 [ 0.000000] efi: UEFI not found.
10303 10:07:37.648256 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10304 10:07:37.655087 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10305 10:07:37.664588 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10306 10:07:37.674838 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10307 10:07:37.681418 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10308 10:07:37.684628 [ 0.000000] printk: bootconsole [mtk8250] enabled
10309 10:07:37.693232 [ 0.000000] NUMA: No NUMA configuration found
10310 10:07:37.699909 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10311 10:07:37.706869 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10312 10:07:37.706954 [ 0.000000] Zone ranges:
10313 10:07:37.713353 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10314 10:07:37.716552 [ 0.000000] DMA32 empty
10315 10:07:37.723152 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10316 10:07:37.726305 [ 0.000000] Movable zone start for each node
10317 10:07:37.729494 [ 0.000000] Early memory node ranges
10318 10:07:37.736324 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10319 10:07:37.742847 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10320 10:07:37.749871 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10321 10:07:37.755973 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10322 10:07:37.762542 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10323 10:07:37.769270 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10324 10:07:37.825924 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10325 10:07:37.832657 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10326 10:07:37.839144 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10327 10:07:37.842733 [ 0.000000] psci: probing for conduit method from DT.
10328 10:07:37.849204 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10329 10:07:37.852876 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10330 10:07:37.858851 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10331 10:07:37.862352 [ 0.000000] psci: SMC Calling Convention v1.2
10332 10:07:37.868947 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10333 10:07:37.871927 [ 0.000000] Detected VIPT I-cache on CPU0
10334 10:07:37.878916 [ 0.000000] CPU features: detected: GIC system register CPU interface
10335 10:07:37.885403 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10336 10:07:37.892398 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10337 10:07:37.898785 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10338 10:07:37.908514 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10339 10:07:37.915319 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10340 10:07:37.918622 [ 0.000000] alternatives: applying boot alternatives
10341 10:07:37.925086 [ 0.000000] Fallback order for Node 0: 0
10342 10:07:37.931848 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10343 10:07:37.935131 [ 0.000000] Policy zone: Normal
10344 10:07:37.954675 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10670702/extract-nfsrootfs-897hv1o9,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10345 10:07:37.964714 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10346 10:07:37.976895 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10347 10:07:37.986744 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10348 10:07:37.993014 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10349 10:07:37.996302 <6>[ 0.000000] software IO TLB: area num 8.
10350 10:07:38.053206 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10351 10:07:38.202129 <6>[ 0.000000] Memory: 7955708K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397060K reserved, 32768K cma-reserved)
10352 10:07:38.208725 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10353 10:07:38.215186 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10354 10:07:38.218253 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10355 10:07:38.225121 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10356 10:07:38.231860 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10357 10:07:38.235249 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10358 10:07:38.245419 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10359 10:07:38.251645 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10360 10:07:38.258471 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10361 10:07:38.264908 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10362 10:07:38.268241 <6>[ 0.000000] GICv3: 608 SPIs implemented
10363 10:07:38.271452 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10364 10:07:38.278457 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10365 10:07:38.281254 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10366 10:07:38.287894 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10367 10:07:38.301224 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10368 10:07:38.311182 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10369 10:07:38.321290 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10370 10:07:38.328855 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10371 10:07:38.341502 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10372 10:07:38.348434 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10373 10:07:38.354788 <6>[ 0.009179] Console: colour dummy device 80x25
10374 10:07:38.365057 <6>[ 0.013938] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10375 10:07:38.371436 <6>[ 0.024380] pid_max: default: 32768 minimum: 301
10376 10:07:38.374738 <6>[ 0.029252] LSM: Security Framework initializing
10377 10:07:38.381637 <6>[ 0.034191] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10378 10:07:38.391043 <6>[ 0.042005] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10379 10:07:38.401334 <6>[ 0.051491] cblist_init_generic: Setting adjustable number of callback queues.
10380 10:07:38.404357 <6>[ 0.058990] cblist_init_generic: Setting shift to 3 and lim to 1.
10381 10:07:38.410805 <6>[ 0.065368] cblist_init_generic: Setting shift to 3 and lim to 1.
10382 10:07:38.417542 <6>[ 0.071814] rcu: Hierarchical SRCU implementation.
10383 10:07:38.424165 <6>[ 0.076828] rcu: Max phase no-delay instances is 1000.
10384 10:07:38.430807 <6>[ 0.083847] EFI services will not be available.
10385 10:07:38.433992 <6>[ 0.088819] smp: Bringing up secondary CPUs ...
10386 10:07:38.442078 <6>[ 0.093872] Detected VIPT I-cache on CPU1
10387 10:07:38.448665 <6>[ 0.093944] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10388 10:07:38.454958 <6>[ 0.093975] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10389 10:07:38.458696 <6>[ 0.094309] Detected VIPT I-cache on CPU2
10390 10:07:38.465304 <6>[ 0.094357] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10391 10:07:38.474943 <6>[ 0.094372] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10392 10:07:38.478199 <6>[ 0.094630] Detected VIPT I-cache on CPU3
10393 10:07:38.484795 <6>[ 0.094678] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10394 10:07:38.491504 <6>[ 0.094692] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10395 10:07:38.494835 <6>[ 0.094997] CPU features: detected: Spectre-v4
10396 10:07:38.501578 <6>[ 0.095004] CPU features: detected: Spectre-BHB
10397 10:07:38.504753 <6>[ 0.095010] Detected PIPT I-cache on CPU4
10398 10:07:38.511198 <6>[ 0.095066] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10399 10:07:38.518077 <6>[ 0.095082] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10400 10:07:38.524567 <6>[ 0.095375] Detected PIPT I-cache on CPU5
10401 10:07:38.531197 <6>[ 0.095438] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10402 10:07:38.537864 <6>[ 0.095454] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10403 10:07:38.541211 <6>[ 0.095736] Detected PIPT I-cache on CPU6
10404 10:07:38.547438 <6>[ 0.095803] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10405 10:07:38.553986 <6>[ 0.095819] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10406 10:07:38.560829 <6>[ 0.096116] Detected PIPT I-cache on CPU7
10407 10:07:38.567286 <6>[ 0.096182] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10408 10:07:38.573850 <6>[ 0.096198] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10409 10:07:38.577175 <6>[ 0.096247] smp: Brought up 1 node, 8 CPUs
10410 10:07:38.584190 <6>[ 0.237521] SMP: Total of 8 processors activated.
10411 10:07:38.587597 <6>[ 0.242442] CPU features: detected: 32-bit EL0 Support
10412 10:07:38.596919 <6>[ 0.247806] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10413 10:07:38.603791 <6>[ 0.256606] CPU features: detected: Common not Private translations
10414 10:07:38.610182 <6>[ 0.263081] CPU features: detected: CRC32 instructions
10415 10:07:38.613495 <6>[ 0.268433] CPU features: detected: RCpc load-acquire (LDAPR)
10416 10:07:38.620254 <6>[ 0.274430] CPU features: detected: LSE atomic instructions
10417 10:07:38.626657 <6>[ 0.280247] CPU features: detected: Privileged Access Never
10418 10:07:38.633117 <6>[ 0.286063] CPU features: detected: RAS Extension Support
10419 10:07:38.639853 <6>[ 0.291706] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10420 10:07:38.643097 <6>[ 0.298973] CPU: All CPU(s) started at EL2
10421 10:07:38.649781 <6>[ 0.303289] alternatives: applying system-wide alternatives
10422 10:07:38.659382 <6>[ 0.314006] devtmpfs: initialized
10423 10:07:38.674918 <6>[ 0.322735] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10424 10:07:38.681395 <6>[ 0.332696] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10425 10:07:38.688549 <6>[ 0.340719] pinctrl core: initialized pinctrl subsystem
10426 10:07:38.691314 <6>[ 0.347388] DMI not present or invalid.
10427 10:07:38.697808 <6>[ 0.351796] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10428 10:07:38.707681 <6>[ 0.358665] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10429 10:07:38.714653 <6>[ 0.366244] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10430 10:07:38.724289 <6>[ 0.374452] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10431 10:07:38.727667 <6>[ 0.382695] audit: initializing netlink subsys (disabled)
10432 10:07:38.737625 <5>[ 0.388391] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10433 10:07:38.744290 <6>[ 0.389097] thermal_sys: Registered thermal governor 'step_wise'
10434 10:07:38.751001 <6>[ 0.396358] thermal_sys: Registered thermal governor 'power_allocator'
10435 10:07:38.754257 <6>[ 0.402613] cpuidle: using governor menu
10436 10:07:38.760488 <6>[ 0.413571] NET: Registered PF_QIPCRTR protocol family
10437 10:07:38.767310 <6>[ 0.419062] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10438 10:07:38.773896 <6>[ 0.426166] ASID allocator initialised with 32768 entries
10439 10:07:38.777250 <6>[ 0.432725] Serial: AMBA PL011 UART driver
10440 10:07:38.787092 <4>[ 0.441382] Trying to register duplicate clock ID: 134
10441 10:07:38.840636 <6>[ 0.498503] KASLR enabled
10442 10:07:38.855339 <6>[ 0.506248] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10443 10:07:38.861601 <6>[ 0.513260] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10444 10:07:38.868242 <6>[ 0.519749] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10445 10:07:38.875267 <6>[ 0.526755] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10446 10:07:38.881690 <6>[ 0.533242] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10447 10:07:38.888158 <6>[ 0.540246] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10448 10:07:38.894669 <6>[ 0.546733] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10449 10:07:38.901145 <6>[ 0.553737] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10450 10:07:38.904640 <6>[ 0.561250] ACPI: Interpreter disabled.
10451 10:07:38.913437 <6>[ 0.567634] iommu: Default domain type: Translated
10452 10:07:38.919739 <6>[ 0.572747] iommu: DMA domain TLB invalidation policy: strict mode
10453 10:07:38.923175 <5>[ 0.579400] SCSI subsystem initialized
10454 10:07:38.930010 <6>[ 0.583564] usbcore: registered new interface driver usbfs
10455 10:07:38.936196 <6>[ 0.589298] usbcore: registered new interface driver hub
10456 10:07:38.939692 <6>[ 0.594852] usbcore: registered new device driver usb
10457 10:07:38.946738 <6>[ 0.600930] pps_core: LinuxPPS API ver. 1 registered
10458 10:07:38.956487 <6>[ 0.606122] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10459 10:07:38.959821 <6>[ 0.615468] PTP clock support registered
10460 10:07:38.963135 <6>[ 0.619710] EDAC MC: Ver: 3.0.0
10461 10:07:38.970412 <6>[ 0.624847] FPGA manager framework
10462 10:07:38.977119 <6>[ 0.628526] Advanced Linux Sound Architecture Driver Initialized.
10463 10:07:38.980283 <6>[ 0.635293] vgaarb: loaded
10464 10:07:38.986901 <6>[ 0.638464] clocksource: Switched to clocksource arch_sys_counter
10465 10:07:38.990094 <5>[ 0.644894] VFS: Disk quotas dquot_6.6.0
10466 10:07:38.997128 <6>[ 0.649078] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10467 10:07:39.000441 <6>[ 0.656265] pnp: PnP ACPI: disabled
10468 10:07:39.008598 <6>[ 0.662936] NET: Registered PF_INET protocol family
10469 10:07:39.018122 <6>[ 0.668515] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10470 10:07:39.029856 <6>[ 0.680818] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10471 10:07:39.039515 <6>[ 0.689630] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10472 10:07:39.046178 <6>[ 0.697601] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10473 10:07:39.056097 <6>[ 0.706301] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10474 10:07:39.062926 <6>[ 0.716046] TCP: Hash tables configured (established 65536 bind 65536)
10475 10:07:39.069336 <6>[ 0.722902] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10476 10:07:39.079447 <6>[ 0.730101] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10477 10:07:39.085764 <6>[ 0.737798] NET: Registered PF_UNIX/PF_LOCAL protocol family
10478 10:07:39.092307 <6>[ 0.743965] RPC: Registered named UNIX socket transport module.
10479 10:07:39.095672 <6>[ 0.750115] RPC: Registered udp transport module.
10480 10:07:39.102008 <6>[ 0.755047] RPC: Registered tcp transport module.
10481 10:07:39.108979 <6>[ 0.759979] RPC: Registered tcp NFSv4.1 backchannel transport module.
10482 10:07:39.111975 <6>[ 0.766651] PCI: CLS 0 bytes, default 64
10483 10:07:39.115643 <6>[ 0.771039] Unpacking initramfs...
10484 10:07:39.125290 <6>[ 0.775105] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10485 10:07:39.132023 <6>[ 0.783780] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10486 10:07:39.138541 <6>[ 0.792615] kvm [1]: IPA Size Limit: 40 bits
10487 10:07:39.141886 <6>[ 0.797138] kvm [1]: GICv3: no GICV resource entry
10488 10:07:39.148074 <6>[ 0.802158] kvm [1]: disabling GICv2 emulation
10489 10:07:39.154713 <6>[ 0.806843] kvm [1]: GIC system register CPU interface enabled
10490 10:07:39.158053 <6>[ 0.813004] kvm [1]: vgic interrupt IRQ18
10491 10:07:39.164976 <6>[ 0.817361] kvm [1]: VHE mode initialized successfully
10492 10:07:39.168158 <5>[ 0.823725] Initialise system trusted keyrings
10493 10:07:39.174704 <6>[ 0.828505] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10494 10:07:39.183881 <6>[ 0.838422] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10495 10:07:39.190355 <5>[ 0.844796] NFS: Registering the id_resolver key type
10496 10:07:39.194165 <5>[ 0.850089] Key type id_resolver registered
10497 10:07:39.200225 <5>[ 0.854504] Key type id_legacy registered
10498 10:07:39.206747 <6>[ 0.858779] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10499 10:07:39.213518 <6>[ 0.865699] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10500 10:07:39.220242 <6>[ 0.873406] 9p: Installing v9fs 9p2000 file system support
10501 10:07:39.255730 <5>[ 0.910062] Key type asymmetric registered
10502 10:07:39.259138 <5>[ 0.914393] Asymmetric key parser 'x509' registered
10503 10:07:39.268705 <6>[ 0.919529] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10504 10:07:39.272043 <6>[ 0.927143] io scheduler mq-deadline registered
10505 10:07:39.275498 <6>[ 0.931903] io scheduler kyber registered
10506 10:07:39.293941 <6>[ 0.948479] EINJ: ACPI disabled.
10507 10:07:39.326144 <4>[ 0.973651] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10508 10:07:39.335902 <4>[ 0.984263] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10509 10:07:39.350161 <6>[ 1.004726] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10510 10:07:39.358415 <6>[ 1.012845] printk: console [ttyS0] disabled
10511 10:07:39.386142 <6>[ 1.037491] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10512 10:07:39.392702 <6>[ 1.046971] printk: console [ttyS0] enabled
10513 10:07:39.396047 <6>[ 1.046971] printk: console [ttyS0] enabled
10514 10:07:39.402821 <6>[ 1.055885] printk: bootconsole [mtk8250] disabled
10515 10:07:39.406084 <6>[ 1.055885] printk: bootconsole [mtk8250] disabled
10516 10:07:39.412713 <6>[ 1.066940] SuperH (H)SCI(F) driver initialized
10517 10:07:39.415936 <6>[ 1.072198] msm_serial: driver initialized
10518 10:07:39.430004 <6>[ 1.080988] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10519 10:07:39.439791 <6>[ 1.089533] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10520 10:07:39.446376 <6>[ 1.098074] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10521 10:07:39.456460 <6>[ 1.106700] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10522 10:07:39.466149 <6>[ 1.115406] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10523 10:07:39.473011 <6>[ 1.124119] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10524 10:07:39.482838 <6>[ 1.132658] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10525 10:07:39.489401 <6>[ 1.141455] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10526 10:07:39.499081 <6>[ 1.149997] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10527 10:07:39.510789 <6>[ 1.165345] loop: module loaded
10528 10:07:39.517352 <6>[ 1.171425] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10529 10:07:39.540214 <4>[ 1.194261] mtk-pmic-keys: Failed to locate of_node [id: -1]
10530 10:07:39.546590 <6>[ 1.200992] megasas: 07.719.03.00-rc1
10531 10:07:39.556024 <6>[ 1.210439] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10532 10:07:39.563758 <6>[ 1.217874] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10533 10:07:39.579990 <6>[ 1.233961] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10534 10:07:39.639412 <6>[ 1.287455] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10535 10:07:39.890640 <6>[ 1.545048] Freeing initrd memory: 17228K
10536 10:07:39.900920 <6>[ 1.555402] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10537 10:07:39.911898 <6>[ 1.566214] tun: Universal TUN/TAP device driver, 1.6
10538 10:07:39.915304 <6>[ 1.572262] thunder_xcv, ver 1.0
10539 10:07:39.918526 <6>[ 1.575765] thunder_bgx, ver 1.0
10540 10:07:39.921898 <6>[ 1.579258] nicpf, ver 1.0
10541 10:07:39.932102 <6>[ 1.583250] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10542 10:07:39.935428 <6>[ 1.590726] hns3: Copyright (c) 2017 Huawei Corporation.
10543 10:07:39.941999 <6>[ 1.596311] hclge is initializing
10544 10:07:39.945301 <6>[ 1.599886] e1000: Intel(R) PRO/1000 Network Driver
10545 10:07:39.951749 <6>[ 1.605015] e1000: Copyright (c) 1999-2006 Intel Corporation.
10546 10:07:39.955453 <6>[ 1.611030] e1000e: Intel(R) PRO/1000 Network Driver
10547 10:07:39.962041 <6>[ 1.616246] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10548 10:07:39.968577 <6>[ 1.622432] igb: Intel(R) Gigabit Ethernet Network Driver
10549 10:07:39.975045 <6>[ 1.628083] igb: Copyright (c) 2007-2014 Intel Corporation.
10550 10:07:39.981753 <6>[ 1.633918] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10551 10:07:39.988268 <6>[ 1.640436] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10552 10:07:39.991698 <6>[ 1.646891] sky2: driver version 1.30
10553 10:07:39.998234 <6>[ 1.651860] VFIO - User Level meta-driver version: 0.3
10554 10:07:40.005537 <6>[ 1.660057] usbcore: registered new interface driver usb-storage
10555 10:07:40.012065 <6>[ 1.666504] usbcore: registered new device driver onboard-usb-hub
10556 10:07:40.021235 <6>[ 1.675600] mt6397-rtc mt6359-rtc: registered as rtc0
10557 10:07:40.031045 <6>[ 1.681072] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-10T10:07:37 UTC (1686391657)
10558 10:07:40.034211 <6>[ 1.690656] i2c_dev: i2c /dev entries driver
10559 10:07:40.050890 <6>[ 1.702164] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10560 10:07:40.057823 <6>[ 1.712349] sdhci: Secure Digital Host Controller Interface driver
10561 10:07:40.064381 <6>[ 1.718786] sdhci: Copyright(c) Pierre Ossman
10562 10:07:40.071257 <6>[ 1.724175] Synopsys Designware Multimedia Card Interface Driver
10563 10:07:40.074581 <6>[ 1.730758] mmc0: CQHCI version 5.10
10564 10:07:40.081078 <6>[ 1.731322] sdhci-pltfm: SDHCI platform and OF driver helper
10565 10:07:40.088275 <6>[ 1.742914] ledtrig-cpu: registered to indicate activity on CPUs
10566 10:07:40.099068 <6>[ 1.750318] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10567 10:07:40.102263 <6>[ 1.757721] usbcore: registered new interface driver usbhid
10568 10:07:40.109207 <6>[ 1.763554] usbhid: USB HID core driver
10569 10:07:40.115543 <6>[ 1.767801] spi_master spi0: will run message pump with realtime priority
10570 10:07:40.158601 <6>[ 1.806653] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10571 10:07:40.167355 <6>[ 1.821662] mmc0: Command Queue Engine enabled
10572 10:07:40.180317 <6>[ 1.821775] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10573 10:07:40.187240 <6>[ 1.826414] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10574 10:07:40.190898 <6>[ 1.846990] mmcblk0: mmc0:0001 DA4128 116 GiB
10575 10:07:40.197680 <6>[ 1.852026] cros-ec-spi spi0.0: Chrome EC device registered
10576 10:07:40.204301 <6>[ 1.856803] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10577 10:07:40.210818 <6>[ 1.865431] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10578 10:07:40.217542 <6>[ 1.871406] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10579 10:07:40.224291 <6>[ 1.877311] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10580 10:07:40.244535 <6>[ 1.895312] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10581 10:07:40.252260 <6>[ 1.906721] NET: Registered PF_PACKET protocol family
10582 10:07:40.255635 <6>[ 1.912152] 9pnet: Installing 9P2000 support
10583 10:07:40.262432 <5>[ 1.916730] Key type dns_resolver registered
10584 10:07:40.265687 <6>[ 1.921801] registered taskstats version 1
10585 10:07:40.272106 <5>[ 1.926200] Loading compiled-in X.509 certificates
10586 10:07:40.305383 <4>[ 1.953041] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10587 10:07:40.315105 <4>[ 1.963793] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10588 10:07:40.325475 <3>[ 1.976685] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10589 10:07:40.338149 <6>[ 1.992758] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10590 10:07:40.345164 <6>[ 1.999501] xhci-mtk 11200000.usb: xHCI Host Controller
10591 10:07:40.351391 <6>[ 2.005001] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10592 10:07:40.361571 <6>[ 2.012857] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10593 10:07:40.368403 <6>[ 2.022310] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10594 10:07:40.374896 <6>[ 2.028515] xhci-mtk 11200000.usb: xHCI Host Controller
10595 10:07:40.381341 <6>[ 2.034012] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10596 10:07:40.388151 <6>[ 2.041673] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10597 10:07:40.395057 <6>[ 2.049549] hub 1-0:1.0: USB hub found
10598 10:07:40.398257 <6>[ 2.053592] hub 1-0:1.0: 1 port detected
10599 10:07:40.408301 <6>[ 2.057940] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10600 10:07:40.411496 <6>[ 2.066743] hub 2-0:1.0: USB hub found
10601 10:07:40.414795 <6>[ 2.070775] hub 2-0:1.0: 1 port detected
10602 10:07:40.423395 <6>[ 2.077894] mtk-msdc 11f70000.mmc: Got CD GPIO
10603 10:07:40.439846 <6>[ 2.091124] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10604 10:07:40.446387 <6>[ 2.099149] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10605 10:07:40.456359 <4>[ 2.107123] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10606 10:07:40.466501 <6>[ 2.116787] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10607 10:07:40.473016 <6>[ 2.124870] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10608 10:07:40.479869 <6>[ 2.132866] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10609 10:07:40.489772 <6>[ 2.140782] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10610 10:07:40.496091 <6>[ 2.148602] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10611 10:07:40.506156 <6>[ 2.156423] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10612 10:07:40.516214 <6>[ 2.166942] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10613 10:07:40.522825 <6>[ 2.175313] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10614 10:07:40.532759 <6>[ 2.183657] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10615 10:07:40.539613 <6>[ 2.192005] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10616 10:07:40.549391 <6>[ 2.200350] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10617 10:07:40.555852 <6>[ 2.208693] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10618 10:07:40.566220 <6>[ 2.217036] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10619 10:07:40.575997 <6>[ 2.225380] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10620 10:07:40.582543 <6>[ 2.233722] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10621 10:07:40.592558 <6>[ 2.242066] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10622 10:07:40.598949 <6>[ 2.250416] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10623 10:07:40.609226 <6>[ 2.258761] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10624 10:07:40.615675 <6>[ 2.267105] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10625 10:07:40.625494 <6>[ 2.275451] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10626 10:07:40.632277 <6>[ 2.283799] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10627 10:07:40.638546 <6>[ 2.292717] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10628 10:07:40.645748 <6>[ 2.300165] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10629 10:07:40.652445 <6>[ 2.307232] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10630 10:07:40.663191 <6>[ 2.314356] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10631 10:07:40.669944 <6>[ 2.321639] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10632 10:07:40.679450 <6>[ 2.328558] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10633 10:07:40.686491 <6>[ 2.337697] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10634 10:07:40.696084 <6>[ 2.346825] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10635 10:07:40.706360 <6>[ 2.356127] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10636 10:07:40.715982 <6>[ 2.365603] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10637 10:07:40.725736 <6>[ 2.375077] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10638 10:07:40.735702 <6>[ 2.384203] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10639 10:07:40.742161 <6>[ 2.393678] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10640 10:07:40.752286 <6>[ 2.402816] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10641 10:07:40.762115 <6>[ 2.412118] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10642 10:07:40.771899 <6>[ 2.422285] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10643 10:07:40.782943 <6>[ 2.434192] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10644 10:07:40.789530 <6>[ 2.444096] Trying to probe devices needed for running init ...
10645 10:07:40.827443 <6>[ 2.478721] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10646 10:07:40.982122 <6>[ 2.635943] hub 1-1:1.0: USB hub found
10647 10:07:40.985075 <6>[ 2.640301] hub 1-1:1.0: 4 ports detected
10648 10:07:41.108198 <6>[ 2.758909] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10649 10:07:41.133247 <6>[ 2.787213] hub 2-1:1.0: USB hub found
10650 10:07:41.136433 <6>[ 2.791651] hub 2-1:1.0: 3 ports detected
10651 10:07:41.304062 <6>[ 2.954742] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10652 10:07:41.436878 <6>[ 3.090847] hub 1-1.4:1.0: USB hub found
10653 10:07:41.440122 <6>[ 3.095485] hub 1-1.4:1.0: 2 ports detected
10654 10:07:41.516431 <6>[ 3.166991] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10655 10:07:41.736365 <6>[ 3.386737] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10656 10:07:41.927592 <6>[ 3.578738] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10657 10:07:53.072309 <6>[ 14.731287] ALSA device list:
10658 10:07:53.079086 <6>[ 14.734545] No soundcards found.
10659 10:07:53.091246 <6>[ 14.746939] Freeing unused kernel memory: 8384K
10660 10:07:53.094456 <6>[ 14.751847] Run /init as init process
10661 10:07:53.104682 Loading, please wait...
10662 10:07:53.124027 Starting version 247.3-7+deb11u2
10663 10:07:53.453438 <6>[ 15.105478] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10664 10:07:53.466516 <6>[ 15.118740] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10665 10:07:53.476547 <6>[ 15.127161] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10666 10:07:53.479981 <6>[ 15.127324] remoteproc remoteproc0: scp is available
10667 10:07:53.489425 <6>[ 15.135999] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10668 10:07:53.499646 <4>[ 15.142161] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10669 10:07:53.506149 <6>[ 15.160219] remoteproc remoteproc0: powering up scp
10670 10:07:53.515786 <4>[ 15.165436] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10671 10:07:53.522616 <3>[ 15.175702] remoteproc remoteproc0: request_firmware failed: -2
10672 10:07:53.547604 <3>[ 15.200063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10673 10:07:53.554601 <3>[ 15.208330] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 10:07:53.564418 <4>[ 15.212953] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10675 10:07:53.570893 <3>[ 15.216469] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 10:07:53.577553 <4>[ 15.224370] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10677 10:07:53.584223 <6>[ 15.224411] mc: Linux media interface: v0.10
10678 10:07:53.587422 <6>[ 15.225804] Bluetooth: Core ver 2.22
10679 10:07:53.593869 <6>[ 15.225875] NET: Registered PF_BLUETOOTH protocol family
10680 10:07:53.600804 <6>[ 15.225878] Bluetooth: HCI device and connection manager initialized
10681 10:07:53.604224 <6>[ 15.225901] Bluetooth: HCI socket layer initialized
10682 10:07:53.610688 <6>[ 15.225907] Bluetooth: L2CAP socket layer initialized
10683 10:07:53.613965 <6>[ 15.225918] Bluetooth: SCO socket layer initialized
10684 10:07:53.623597 <3>[ 15.232466] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 10:07:53.630065 <6>[ 15.248405] usbcore: registered new interface driver r8152
10686 10:07:53.636906 <6>[ 15.248524] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10687 10:07:53.644016 <3>[ 15.253567] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 10:07:53.653990 <4>[ 15.272968] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10689 10:07:53.657274 <4>[ 15.272968] Fallback method does not support PEC.
10690 10:07:53.663615 <6>[ 15.273468] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10691 10:07:53.670450 <6>[ 15.273476] pci_bus 0000:00: root bus resource [bus 00-ff]
10692 10:07:53.677782 <6>[ 15.273487] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10693 10:07:53.687696 <6>[ 15.273495] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10694 10:07:53.694906 <6>[ 15.273534] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10695 10:07:53.701293 <6>[ 15.273558] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10696 10:07:53.704687 <6>[ 15.273641] pci 0000:00:00.0: supports D1 D2
10697 10:07:53.714804 <6>[ 15.273646] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10698 10:07:53.721423 <6>[ 15.275355] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10699 10:07:53.727518 <6>[ 15.275519] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10700 10:07:53.734280 <6>[ 15.275552] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10701 10:07:53.741053 <6>[ 15.275572] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10702 10:07:53.750790 <6>[ 15.275591] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10703 10:07:53.753901 <6>[ 15.275722] pci 0000:01:00.0: supports D1 D2
10704 10:07:53.764050 <3>[ 15.275823] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 10:07:53.771043 <3>[ 15.275835] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 10:07:53.777281 <3>[ 15.275843] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 10:07:53.787288 <3>[ 15.275892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 10:07:53.793890 <3>[ 15.275933] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 10:07:53.803959 <3>[ 15.275940] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 10:07:53.810139 <3>[ 15.275946] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 10:07:53.819858 <3>[ 15.276007] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 10:07:53.827039 <3>[ 15.276014] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 10:07:53.836417 <3>[ 15.276020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 10:07:53.843036 <3>[ 15.276027] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 10:07:53.852885 <3>[ 15.276033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 10:07:53.859855 <3>[ 15.276060] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 10:07:53.869589 <3>[ 15.304539] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10718 10:07:53.876084 <6>[ 15.305334] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10719 10:07:53.883046 <3>[ 15.340474] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10720 10:07:53.889604 <3>[ 15.354783] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10721 10:07:53.899467 <6>[ 15.358547] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10722 10:07:53.905908 <6>[ 15.358688] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10723 10:07:53.915674 <6>[ 15.358724] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10724 10:07:53.922545 <6>[ 15.358732] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10725 10:07:53.932145 <6>[ 15.358744] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10726 10:07:53.938769 <6>[ 15.358761] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10727 10:07:53.948475 <6>[ 15.358777] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10728 10:07:53.951869 <6>[ 15.358792] pci 0000:00:00.0: PCI bridge to [bus 01]
10729 10:07:53.962101 <6>[ 15.358800] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10730 10:07:53.968589 <6>[ 15.358972] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10731 10:07:53.971631 <6>[ 15.359843] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10732 10:07:53.978564 <6>[ 15.360205] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10733 10:07:53.985065 <6>[ 15.362936] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10734 10:07:53.994913 <6>[ 15.367183] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10735 10:07:54.004599 <4>[ 15.394180] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10736 10:07:54.011474 <3>[ 15.462832] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10737 10:07:54.017762 <4>[ 15.464135] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10738 10:07:54.024558 <3>[ 15.570753] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10739 10:07:54.027872 <6>[ 15.582587] r8152 2-1.3:1.0 eth0: v1.12.13
10740 10:07:54.037603 <3>[ 15.584442] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10741 10:07:54.044093 <6>[ 15.697118] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10742 10:07:54.061658 <6>[ 15.717821] usbcore: registered new interface driver cdc_ether
10743 10:07:54.068414 <6>[ 15.717909] videodev: Linux video capture interface: v2.00
10744 10:07:54.075398 <6>[ 15.731504] usbcore: registered new interface driver r8153_ecm
10745 10:07:54.085467 <5>[ 15.733195] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10746 10:07:54.091952 <6>[ 15.739306] usbcore: registered new interface driver btusb
10747 10:07:54.102034 <4>[ 15.739958] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10748 10:07:54.108431 <3>[ 15.739971] Bluetooth: hci0: Failed to load firmware file (-2)
10749 10:07:54.111843 <3>[ 15.739975] Bluetooth: hci0: Failed to set up firmware (-2)
10750 10:07:54.121875 <4>[ 15.739979] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10751 10:07:54.128516 <6>[ 15.747237] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10752 10:07:54.134947 <5>[ 15.757269] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10753 10:07:54.145174 <6>[ 15.775104] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10754 10:07:54.148511 <6>[ 15.798029] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10755 10:07:54.161614 <6>[ 15.805655] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10756 10:07:54.168167 <6>[ 15.823475] usbcore: registered new interface driver uvcvideo
10757 10:07:54.186708 <4>[ 15.839045] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10758 10:07:54.192964 <6>[ 15.847948] cfg80211: failed to load regulatory.db
10759 10:07:54.231400 <6>[ 15.884254] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10760 10:07:54.237862 <6>[ 15.891811] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10761 10:07:54.262289 <6>[ 15.918601] mt7921e 0000:01:00.0: ASIC revision: 79610010
10762 10:07:54.369370 <4>[ 16.018777] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10763 10:07:54.372973 Begin: Loading essential drivers ... done.
10764 10:07:54.379312 Begin: Running /scripts/init-premount ... done.
10765 10:07:54.386154 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10766 10:07:54.392592 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10767 10:07:54.399638 Device /sys/class/net/enx00e04c722dd6 found
10768 10:07:54.400153 done.
10769 10:07:54.442249 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10770 10:07:54.491458 <4>[ 16.140946] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10771 10:07:54.611108 <4>[ 16.260437] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 10:07:54.726474 <4>[ 16.376163] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10773 10:07:54.842899 <4>[ 16.492250] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10774 10:07:54.958740 <4>[ 16.608096] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 10:07:55.074781 <4>[ 16.724031] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 10:07:55.191080 <4>[ 16.840179] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 10:07:55.307147 <4>[ 16.956036] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 10:07:55.422942 <4>[ 17.071989] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 10:07:55.525555 IP-Config: no response after 2 secs - giving up
10780 10:07:55.531667 <3>[ 17.186095] mt7921e 0000:01:00.0: hardware init failed
10781 10:07:55.566302 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10782 10:07:55.790744 <6>[ 17.446523] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10783 10:07:56.668621 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10784 10:07:56.675295 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10785 10:07:56.681742 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10786 10:07:56.688182 host : mt8192-asurada-spherion-r0-cbg-1
10787 10:07:56.695024 domain : lava-rack
10788 10:07:56.698360 rootserver: 192.168.201.1 rootpath:
10789 10:07:56.701258 filename :
10790 10:07:56.743188 done.
10791 10:07:56.750195 Begin: Running /scripts/nfs-bottom ... done.
10792 10:07:56.767261 Begin: Running /scripts/init-bottom ... done.
10793 10:07:57.842953 <6>[ 19.499256] NET: Registered PF_INET6 protocol family
10794 10:07:57.849398 <6>[ 19.505927] Segment Routing with IPv6
10795 10:07:57.852453 <6>[ 19.509895] In-situ OAM (IOAM) with IPv6
10796 10:07:57.960866 <30>[ 19.597282] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10797 10:07:57.963992 <30>[ 19.621050] systemd[1]: Detected architecture arm64.
10798 10:07:57.982275
10799 10:07:57.985673 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10800 10:07:57.985780
10801 10:07:58.000308 <30>[ 19.656476] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10802 10:07:58.507209 <30>[ 20.160038] systemd[1]: Queued start job for default target Graphical Interface.
10803 10:07:58.531497 <30>[ 20.187809] systemd[1]: Created slice system-getty.slice.
10804 10:07:58.538438 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10805 10:07:58.555577 <30>[ 20.211437] systemd[1]: Created slice system-modprobe.slice.
10806 10:07:58.561719 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10807 10:07:58.579262 <30>[ 20.235328] systemd[1]: Created slice system-serial\x2dgetty.slice.
10808 10:07:58.589129 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10809 10:07:58.603572 <30>[ 20.259813] systemd[1]: Created slice User and Session Slice.
10810 10:07:58.610729 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10811 10:07:58.630317 <30>[ 20.283303] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10812 10:07:58.639987 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10813 10:07:58.658008 <30>[ 20.310895] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10814 10:07:58.664392 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10815 10:07:58.685151 <30>[ 20.334819] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10816 10:07:58.691578 <30>[ 20.346845] systemd[1]: Reached target Local Encrypted Volumes.
10817 10:07:58.698331 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10818 10:07:58.714645 <30>[ 20.370856] systemd[1]: Reached target Paths.
10819 10:07:58.717603 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10820 10:07:58.733886 <30>[ 20.390726] systemd[1]: Reached target Remote File Systems.
10821 10:07:58.740710 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10822 10:07:58.754077 <30>[ 20.410759] systemd[1]: Reached target Slices.
10823 10:07:58.757187 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10824 10:07:58.773842 <30>[ 20.430774] systemd[1]: Reached target Swap.
10825 10:07:58.777199 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10826 10:07:58.797375 <30>[ 20.451032] systemd[1]: Listening on initctl Compatibility Named Pipe.
10827 10:07:58.804174 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10828 10:07:58.811035 <30>[ 20.466216] systemd[1]: Listening on Journal Audit Socket.
10829 10:07:58.817306 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10830 10:07:58.831116 <30>[ 20.487641] systemd[1]: Listening on Journal Socket (/dev/log).
10831 10:07:58.837620 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10832 10:07:58.854968 <30>[ 20.511552] systemd[1]: Listening on Journal Socket.
10833 10:07:58.861222 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10834 10:07:58.878414 <30>[ 20.531961] systemd[1]: Listening on Network Service Netlink Socket.
10835 10:07:58.885310 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10836 10:07:58.900086 <30>[ 20.557037] systemd[1]: Listening on udev Control Socket.
10837 10:07:58.906858 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10838 10:07:58.922198 <30>[ 20.579039] systemd[1]: Listening on udev Kernel Socket.
10839 10:07:58.929184 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10840 10:07:58.978087 <30>[ 20.634939] systemd[1]: Mounting Huge Pages File System...
10841 10:07:58.984569 Mounting [0;1;39mHuge Pages File System[0m...
10842 10:07:59.000432 <30>[ 20.657022] systemd[1]: Mounting POSIX Message Queue File System...
10843 10:07:59.007043 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10844 10:07:59.024303 <30>[ 20.681109] systemd[1]: Mounting Kernel Debug File System...
10845 10:07:59.030854 Mounting [0;1;39mKernel Debug File System[0m...
10846 10:07:59.049589 <30>[ 20.702979] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10847 10:07:59.066303 <30>[ 20.719583] systemd[1]: Starting Create list of static device nodes for the current kernel...
10848 10:07:59.073066 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10849 10:07:59.092618 <30>[ 20.749147] systemd[1]: Starting Load Kernel Module configfs...
10850 10:07:59.098892 Starting [0;1;39mLoad Kernel Module configfs[0m...
10851 10:07:59.116573 <30>[ 20.773142] systemd[1]: Starting Load Kernel Module drm...
10852 10:07:59.123500 Starting [0;1;39mLoad Kernel Module drm[0m...
10853 10:07:59.141035 <30>[ 20.797092] systemd[1]: Starting Load Kernel Module fuse...
10854 10:07:59.147450 Starting [0;1;39mLoad Kernel Module fuse[0m...
10855 10:07:59.177027 <6>[ 20.833351] fuse: init (API version 7.37)
10856 10:07:59.186685 <30>[ 20.833420] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10857 10:07:59.223210 <30>[ 20.879151] systemd[1]: Starting Journal Service...
10858 10:07:59.225991 Starting [0;1;39mJournal Service[0m...
10859 10:07:59.250119 <30>[ 20.906303] systemd[1]: Starting Load Kernel Modules...
10860 10:07:59.256431 Starting [0;1;39mLoad Kernel Modules[0m...
10861 10:07:59.314065 <30>[ 20.967245] systemd[1]: Starting Remount Root and Kernel File Systems...
10862 10:07:59.320828 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10863 10:07:59.341179 <30>[ 20.997744] systemd[1]: Starting Coldplug All udev Devices...
10864 10:07:59.347663 Starting [0;1;39mColdplug All udev Devices[0m...
10865 10:07:59.370494 <30>[ 21.027326] systemd[1]: Mounted Huge Pages File System.
10866 10:07:59.376990 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10867 10:07:59.397330 <3>[ 21.050938] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10868 10:07:59.403952 <30>[ 21.051190] systemd[1]: Mounted POSIX Message Queue File System.
10869 10:07:59.410491 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10870 10:07:59.427174 <3>[ 21.080725] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10871 10:07:59.434146 <30>[ 21.090278] systemd[1]: Mounted Kernel Debug File System.
10872 10:07:59.440513 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10873 10:07:59.458596 <30>[ 21.111683] systemd[1]: Finished Create list of static device nodes for the current kernel.
10874 10:07:59.472234 [[0;32m OK [0m] Finished [0;1;39mCreate lis<3>[ 21.124005] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 10:07:59.475122 t of st… nodes for the current kernel[0m.
10876 10:07:59.490865 <30>[ 21.147622] systemd[1]: modprobe@configfs.service: Succeeded.
10877 10:07:59.497732 <30>[ 21.154369] systemd[1]: Finished Load Kernel Module configfs.
10878 10:07:59.507569 <3>[ 21.156697] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 10:07:59.514445 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10880 10:07:59.531248 <30>[ 21.187425] systemd[1]: modprobe@drm.service: Succeeded.
10881 10:07:59.541164 <3>[ 21.192020] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 10:07:59.544945 <30>[ 21.193670] systemd[1]: Finished Load Kernel Module drm.
10883 10:07:59.551203 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10884 10:07:59.570002 <3>[ 21.223205] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 10:07:59.576647 <30>[ 21.223752] systemd[1]: modprobe@fuse.service: Succeeded.
10886 10:07:59.583346 <30>[ 21.238840] systemd[1]: Finished Load Kernel Module fuse.
10887 10:07:59.590300 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10888 10:07:59.600012 <3>[ 21.253253] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 10:07:59.607383 <30>[ 21.263759] systemd[1]: Finished Load Kernel Modules.
10890 10:07:59.613979 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10891 10:07:59.630118 <30>[ 21.283721] systemd[1]: Finished Remount Root and Kernel File Systems.
10892 10:07:59.636949 <3>[ 21.285593] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 10:07:59.643279 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10894 10:07:59.667624 <3>[ 21.321025] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 10:07:59.697705 <3>[ 21.350754] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 10:07:59.726096 <30>[ 21.382430] systemd[1]: Mounting FUSE Control File System...
10897 10:07:59.732598 Mounting [0;1;39mFUSE Control File System[0m...
10898 10:07:59.752563 <30>[ 21.405449] systemd[1]: Mounting Kernel Configuration File System...
10899 10:07:59.755351 Mounting [0;1;39mKernel Configuration File System[0m...
10900 10:07:59.782596 <30>[ 21.435970] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10901 10:07:59.792763 <30>[ 21.445021] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10902 10:07:59.801102 <30>[ 21.457556] systemd[1]: Starting Load/Save Random Seed...
10903 10:07:59.807810 Starting [0;1;39mLoad/Save Random Seed[0m...
10904 10:07:59.824918 <30>[ 21.481538] systemd[1]: Starting Apply Kernel Variables...
10905 10:07:59.831185 Starting [0;1;39mApply Kernel Variables[0m...
10906 10:07:59.849828 <30>[ 21.506418] systemd[1]: Starting Create System Users...
10907 10:07:59.856148 Starting [0;1;39mCreate System Users[0m...
10908 10:07:59.875624 <30>[ 21.532438] systemd[1]: Started Journal Service.
10909 10:07:59.882094 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10910 10:07:59.900328 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10911 10:07:59.932021 [[0;32m OK [0m] Mounted [0;<4>[ 21.577394] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10912 10:07:59.938636 <3>[ 21.593695] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10913 10:07:59.941928 1;39mKernel Configuration File System[0m.
10914 10:07:59.959505 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10915 10:07:59.983756 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10916 10:07:59.994528 See 'systemctl status systemd-udev-trigger.service' for details.
10917 10:08:00.011614 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10918 10:08:00.027220 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10919 10:08:00.091126 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10920 10:08:00.113124 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10921 10:08:00.133492 <46>[ 21.787112] systemd-journald[290]: Received client request to flush runtime journal.
10922 10:08:00.350813 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10923 10:08:00.366498 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10924 10:08:00.386072 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10925 10:08:00.441517 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10926 10:08:01.512492 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10927 10:08:01.546689 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10928 10:08:01.570750 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10929 10:08:01.603737 Starting [0;1;39mNetwork Service[0m...
10930 10:08:01.765194 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10931 10:08:01.918644 Starting [0;1;39mNetwork Time Synchronization[0m...
10932 10:08:01.944593 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10933 10:08:02.080471 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10934 10:08:02.162919 <6>[ 23.820066] remoteproc remoteproc0: powering up scp
10935 10:08:02.181509 <4>[ 23.835121] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10936 10:08:02.187888 <3>[ 23.845173] remoteproc remoteproc0: request_firmware failed: -2
10937 10:08:02.199117 <3>[ 23.852832] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10938 10:08:02.320984 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10939 10:08:02.339040 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10940 10:08:02.389341 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10941 10:08:02.402415 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10942 10:08:02.421648 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10943 10:08:02.470158 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10944 10:08:02.498543 Starting [0;1;39mNetwork Name Resolution[0m...
10945 10:08:02.518697 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10946 10:08:02.543448 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10947 10:08:02.561700 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10948 10:08:02.580006 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10949 10:08:02.592315 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10950 10:08:02.607970 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10951 10:08:02.630240 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10952 10:08:02.653236 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10953 10:08:02.681499 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10954 10:08:02.706604 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10955 10:08:02.721069 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10956 10:08:02.746010 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10957 10:08:02.759766 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10958 10:08:02.775280 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10959 10:08:02.807616 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10960 10:08:02.899560 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10961 10:08:03.044817 Starting [0;1;39mUser Login Management[0m...
10962 10:08:03.062827 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10963 10:08:03.280053 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10964 10:08:03.296775 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10965 10:08:03.319744 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10966 10:08:03.371755 Starting [0;1;39mPermit User Sessions[0m...
10967 10:08:03.386886 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10968 10:08:03.415370 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10969 10:08:03.431446 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10970 10:08:03.484028 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10971 10:08:03.502045 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10972 10:08:03.518729 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10973 10:08:03.535109 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10974 10:08:03.551027 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10975 10:08:03.565530 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10976 10:08:03.620945 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10977 10:08:03.655038 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10978 10:08:03.689780
10979 10:08:03.689878
10980 10:08:03.693097 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10981 10:08:03.693189
10982 10:08:03.696172 debian-bullseye-arm64 login: root (automatic login)
10983 10:08:03.696257
10984 10:08:03.696337
10985 10:08:03.930843 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023 aarch64
10986 10:08:03.930985
10987 10:08:03.937780 The programs included with the Debian GNU/Linux system are free software;
10988 10:08:03.944045 the exact distribution terms for each program are described in the
10989 10:08:03.947276 individual files in /usr/share/doc/*/copyright.
10990 10:08:03.947362
10991 10:08:03.954028 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10992 10:08:03.957298 permitted by applicable law.
10993 10:08:04.017912 Matched prompt #10: / #
10995 10:08:04.018178 Setting prompt string to ['/ #']
10996 10:08:04.018275 end: 2.2.5.1 login-action (duration 00:00:26) [common]
10998 10:08:04.018496 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
10999 10:08:04.018600 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
11000 10:08:04.018672 Setting prompt string to ['/ #']
11001 10:08:04.018733 Forcing a shell prompt, looking for ['/ #']
11003 10:08:04.068926 / #
11004 10:08:04.069088 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11005 10:08:04.069214 Waiting using forced prompt support (timeout 00:02:30)
11006 10:08:04.073616
11007 10:08:04.073988 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11008 10:08:04.074160 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
11010 10:08:04.174808 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10670702/extract-nfsrootfs-897hv1o9'
11011 10:08:04.180823 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10670702/extract-nfsrootfs-897hv1o9'
11013 10:08:04.282623 / # export NFS_SERVER_IP='192.168.201.1'
11014 10:08:04.289207 export NFS_SERVER_IP='192.168.201.1'
11015 10:08:04.290006 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11016 10:08:04.290486 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
11017 10:08:04.290930 end: 2 depthcharge-action (duration 00:01:25) [common]
11018 10:08:04.291380 start: 3 lava-test-retry (timeout 00:30:00) [common]
11019 10:08:04.291824 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11020 10:08:04.292284 Using namespace: common
11022 10:08:04.393685 / # #
11023 10:08:04.393869 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11024 10:08:04.398909 #
11025 10:08:04.399185 Using /lava-10670702
11027 10:08:04.499748 / # export SHELL=/bin/sh
11028 10:08:04.505627 export SHELL=/bin/sh
11030 10:08:04.607018 / # . /lava-10670702/environment
11031 10:08:04.613040 . /lava-10670702/environment
11033 10:08:04.718997 / # /lava-10670702/bin/lava-test-runner /lava-10670702/0
11034 10:08:04.719598 Test shell timeout: 10s (minimum of the action and connection timeout)
11035 10:08:04.725032 /lava-10670702/bin/lava-test-runner /lava-10670702/0
11036 10:08:04.904554 + export TESTRUN_ID=0_lc-compliance
11037 10:08:04.911289 + cd /lava-10670702/0/tests/0_lc-compliance
11038 10:08:04.911400 + cat uuid
11039 10:08:04.914473 + UUID=10670702_1.6.2.3.1
11040 10:08:04.914557 + set +x
11041 10:08:04.917803 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 10670702_1.6.2.3.1>
11042 10:08:04.918075 Received signal: <STARTRUN> 0_lc-compliance 10670702_1.6.2.3.1
11043 10:08:04.918157 Starting test lava.0_lc-compliance (10670702_1.6.2.3.1)
11044 10:08:04.918249 Skipping test definition patterns.
11045 10:08:04.920883 + /usr/bin/lc-compliance-parser.sh
11046 10:08:06.050316 [0:00:27.671919200] [411] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:298 [0mlibcamera v0.0.0+1-76e1cb9f
11047 10:08:06.053627 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11048 10:08:06.063075 [0:00:27.686957025] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11049 10:08:06.107722 [==========] Running 120 tests from 1 test suite.
11050 10:08:06.117140 [0:00:27.742335055] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11051 10:08:06.159898 [----------] Global test environment set-up.
11052 10:08:06.175122 [0:00:27.799603467] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11053 10:08:06.218032 [----------] 120 tests from CaptureTests/SingleStream
11054 10:08:06.233715 [0:00:27.858757560] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11055 10:08:06.275762 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11056 10:08:06.314875 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11057 10:08:06.315195 Received signal: <TESTSET> START CaptureTests/SingleStream
11058 10:08:06.315274 Starting test_set CaptureTests/SingleStream
11059 10:08:06.318364 Camera needs 4 requests, can't test only 1
11060 10:08:06.365900 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11061 10:08:06.407733
11062 10:08:06.461023 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (55 ms)
11063 10:08:06.527595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11064 10:08:06.527913 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11066 10:08:06.538774 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11067 10:08:06.578947 Camera needs 4 requests, can't test only 2
11068 10:08:06.636618 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11069 10:08:06.665333 [0:00:28.297914497] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11070 10:08:06.698875
11071 10:08:06.760409 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (59 ms)
11072 10:08:06.825397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11073 10:08:06.825762 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11075 10:08:06.837538 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11076 10:08:06.876489 Camera needs 4 requests, can't test only 3
11077 10:08:06.931800 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11078 10:08:06.987616
11079 10:08:07.048126 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (58 ms)
11080 10:08:07.119496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11081 10:08:07.119861 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11083 10:08:07.131012 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11084 10:08:07.165802 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (439 ms)
11085 10:08:07.196904 [0:00:28.838288175] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11086 10:08:07.242509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11087 10:08:07.242892 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11089 10:08:07.254302 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11090 10:08:07.296194 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (541 ms)
11091 10:08:07.363666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11092 10:08:07.363987 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11094 10:08:07.376311 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11095 10:08:07.824870 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (646 ms)
11096 10:08:07.835004 [0:00:29.484662151] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11097 10:08:07.903474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11098 10:08:07.904394 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11100 10:08:07.914859 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11101 10:08:08.725051 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (912 ms)
11102 10:08:08.734282 [0:00:30.396679666] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11103 10:08:08.799649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11104 10:08:08.800036 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11106 10:08:08.810232 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11107 10:08:10.122961 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1414 ms)
11108 10:08:10.132400 [0:00:31.811615313] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11109 10:08:10.185620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11110 10:08:10.185893 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11112 10:08:10.194262 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11113 10:08:12.254324 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2151 ms)
11114 10:08:12.263840 [0:00:33.962508698] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11115 10:08:12.316066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11116 10:08:12.316383 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11118 10:08:12.326149 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11119 10:08:15.485925 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3252 ms)
11120 10:08:15.495142 [0:00:37.213638664] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11121 10:08:15.551605 [0:00:37.271166513] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11122 10:08:15.574044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11123 10:08:15.574947 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11125 10:08:15.585538 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11126 10:08:15.608025 [0:00:37.328060624] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11127 10:08:15.628667 Camera needs 4 requests, can't test only 1
11128 10:08:15.664074 [0:00:37.384060747] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11129 10:08:15.693200 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11130 10:08:15.752302
11131 10:08:15.808103 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (57 ms)
11132 10:08:15.868719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11133 10:08:15.869552 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11135 10:08:15.879483 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11136 10:08:15.920641 Camera needs 4 requests, can't test only 2
11137 10:08:15.982006 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11138 10:08:16.031777 [0:00:37.754020836] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11139 10:08:16.040089
11140 10:08:16.098657 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (58 ms)
11141 10:08:16.153121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11142 10:08:16.153396 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11144 10:08:16.162605 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11145 10:08:16.192953 Camera needs 4 requests, can't test only 3
11146 10:08:16.238737 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11147 10:08:16.283936
11148 10:08:16.340164 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (56 ms)
11149 10:08:16.414928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11150 10:08:16.415320 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11152 10:08:16.426720 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11153 10:08:16.464524 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (369 ms)
11154 10:08:16.522000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11155 10:08:16.522273 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11157 10:08:16.533453 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11158 10:08:16.563147 [0:00:38.287984443] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11159 10:08:16.576092 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (535 ms)
11160 10:08:16.636832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11161 10:08:16.637656 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11163 10:08:16.648832 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11164 10:08:17.254638 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (702 ms)
11165 10:08:17.267765 [0:00:38.991584419] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11166 10:08:17.346556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11167 10:08:17.347449 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11169 10:08:17.359713 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11170 10:08:18.155437 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (904 ms)
11171 10:08:18.168229 [0:00:39.895724486] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11172 10:08:18.235637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11173 10:08:18.236428 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11175 10:08:18.250084 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11176 10:08:19.554399 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1404 ms)
11177 10:08:19.567017 [0:00:41.299310384] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11178 10:08:19.650519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11179 10:08:19.651343 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11181 10:08:19.663428 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11182 10:08:21.651754 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2103 ms)
11183 10:08:21.664937 [0:00:43.400774284] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11184 10:08:21.721374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11185 10:08:21.721675 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11187 10:08:21.730665 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11188 10:08:24.287744 <6>[ 45.950195] vpu: disabling
11189 10:08:24.290902 <6>[ 45.953245] vproc2: disabling
11190 10:08:24.294082 <6>[ 45.956516] vproc1: disabling
11191 10:08:24.297386 <6>[ 45.959775] vaud18: disabling
11192 10:08:24.304019 <6>[ 45.963178] vsram_others: disabling
11193 10:08:24.304454 <6>[ 45.967049] va09: disabling
11194 10:08:24.310656 <6>[ 45.970154] vsram_md: disabling
11195 10:08:24.311089 <6>[ 45.973637] Vgpu: disabling
11196 10:08:24.880680 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3235 ms)
11197 10:08:24.893770 [0:00:46.636921004] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11198 10:08:24.947040 [0:00:46.694529445] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11199 10:08:24.960435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11200 10:08:24.961441 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11202 10:08:24.971701 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11203 10:08:25.003598 [0:00:46.751628533] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11204 10:08:25.020574 Camera needs 4 requests, can't test only 1
11205 10:08:25.062013 [0:00:46.809930749] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11206 10:08:25.088429 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11207 10:08:25.137672
11208 10:08:25.197500 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (58 ms)
11209 10:08:25.261320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11210 10:08:25.261663 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11212 10:08:25.270494 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11213 10:08:25.306180 Camera needs 4 requests, can't test only 2
11214 10:08:25.351630 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11215 10:08:25.394455
11216 10:08:25.432869 [0:00:47.181140193] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11217 10:08:25.459636 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (58 ms)
11218 10:08:25.529551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11219 10:08:25.530289 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11221 10:08:25.541025 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11222 10:08:25.585136 Camera needs 4 requests, can't test only 3
11223 10:08:25.647162 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11224 10:08:25.706107
11225 10:08:25.769700 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (58 ms)
11226 10:08:25.835088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11227 10:08:25.835396 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11229 10:08:25.845029 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11230 10:08:25.878931 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (371 ms)
11231 10:08:25.901801 [0:00:47.651376660] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11232 10:08:25.942493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11233 10:08:25.942755 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11235 10:08:25.952303 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11236 10:08:25.989790 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (471 ms)
11237 10:08:26.051933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11238 10:08:26.052212 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11240 10:08:26.062370 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11241 10:08:26.625348 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (731 ms)
11242 10:08:26.638496 [0:00:48.383823352] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11243 10:08:26.701920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11244 10:08:26.702229 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11246 10:08:26.713120 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11247 10:08:27.527986 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (904 ms)
11248 10:08:27.541112 [0:00:49.287973872] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11249 10:08:27.594764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11250 10:08:27.595059 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11252 10:08:27.604686 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11253 10:08:28.930820 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1400 ms)
11254 10:08:28.940293 [0:00:50.688651913] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11255 10:08:28.994905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11256 10:08:28.995213 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11258 10:08:29.004487 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11259 10:08:31.026098 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2101 ms)
11260 10:08:31.039135 [0:00:52.788591039] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11261 10:08:31.118027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11262 10:08:31.118313 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11264 10:08:31.131687 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11265 10:08:34.194976 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3171 ms)
11266 10:08:34.208157 [0:00:55.959990465] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11267 10:08:34.261518 [0:00:56.018227105] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11268 10:08:34.284725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11269 10:08:34.285676 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11271 10:08:34.299266 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11272 10:08:34.319946 [0:00:56.075974552] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11273 10:08:34.349781 Camera needs 4 requests, can't test only 1
11274 10:08:34.378371 [0:00:56.134952610] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11275 10:08:34.420985 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11276 10:08:34.481152
11277 10:08:34.542101 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (58 ms)
11278 10:08:34.603364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11279 10:08:34.603745 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11281 10:08:34.613314 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11282 10:08:34.645313 Camera needs 4 requests, can't test only 2
11283 10:08:34.688483 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11284 10:08:34.729612
11285 10:08:34.778590 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (58 ms)
11286 10:08:34.809844 [0:00:56.567126808] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11287 10:08:34.846105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11288 10:08:34.846447 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11290 10:08:34.856200 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11291 10:08:34.892150 Camera needs 4 requests, can't test only 3
11292 10:08:34.944669 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11293 10:08:34.997059
11294 10:08:35.051720 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (59 ms)
11295 10:08:35.106348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11296 10:08:35.106689 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11298 10:08:35.117005 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11299 10:08:35.159401 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (432 ms)
11300 10:08:35.225385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11301 10:08:35.225698 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11303 10:08:35.237318 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11304 10:08:35.276530 [0:00:57.033980012] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11305 10:08:35.283415 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (467 ms)
11306 10:08:35.338163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11307 10:08:35.338448 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11309 10:08:35.350998 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11310 10:08:35.966879 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (698 ms)
11311 10:08:35.980038 [0:00:57.732764576] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11312 10:08:36.038341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11313 10:08:36.038675 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11315 10:08:36.048502 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11316 10:08:36.867777 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (901 ms)
11317 10:08:36.881014 [0:00:58.633079996] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11318 10:08:36.944456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11319 10:08:36.945422 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11321 10:08:36.956947 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11322 10:08:38.202832 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1335 ms)
11323 10:08:38.216263 [0:00:59.968357280] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11324 10:08:38.283572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11325 10:08:38.284588 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11327 10:08:38.295785 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11328 10:08:40.333820 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2131 ms)
11329 10:08:40.346496 [0:01:02.099728451] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11330 10:08:40.411529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11331 10:08:40.412411 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11333 10:08:40.426245 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11334 10:08:43.564780 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3232 ms)
11335 10:08:43.577912 [0:01:05.331647250] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11336 10:08:43.628637 [0:01:05.388352598] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11337 10:08:43.632564 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11339 10:08:43.635439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11340 10:08:43.641786 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11341 10:08:43.674309 Camera needs 4 requests, can't test only 1
11342 10:08:43.684170 [0:01:05.446174382] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11343 10:08:43.730118 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11344 10:08:43.743917 [0:01:05.503419253] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11345 10:08:43.781705
11346 10:08:43.827838 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (57 ms)
11347 10:08:43.879409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11348 10:08:43.879779 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11350 10:08:43.890000 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11351 10:08:43.920404 Camera needs 4 requests, can't test only 2
11352 10:08:43.962939 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11353 10:08:44.006147
11354 10:08:44.056698 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (56 ms)
11355 10:08:44.112713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11356 10:08:44.113098 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11358 10:08:44.122290 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11359 10:08:44.154874 Camera needs 4 requests, can't test only 3
11360 10:08:44.205903 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11361 10:08:44.242991
11362 10:08:44.296471 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (58 ms)
11363 10:08:44.349339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11364 10:08:44.349667 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11366 10:08:44.358842 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11367 10:08:44.960657 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1226 ms)
11368 10:08:44.973665 [0:01:06.728551555] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11369 10:08:45.024325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11370 10:08:45.024657 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11372 10:08:45.034047 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11373 10:08:46.546093 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1585 ms)
11374 10:08:46.559410 [0:01:08.315789765] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11375 10:08:46.626099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11376 10:08:46.626450 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11378 10:08:46.636463 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11379 10:08:48.601785 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2056 ms)
11380 10:08:48.615302 [0:01:10.370457635] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11381 10:08:48.669357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11382 10:08:48.669693 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11384 10:08:48.680600 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11385 10:08:51.292663 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2691 ms)
11386 10:08:51.305628 [0:01:13.061829289] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11387 10:08:51.360250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11388 10:08:51.360610 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11390 10:08:51.370522 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11391 10:08:55.413414 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4122 ms)
11392 10:08:55.426288 [0:01:17.183148935] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11393 10:08:55.486365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11394 10:08:55.486678 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11396 10:08:55.497928 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11397 10:09:01.696661 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6284 ms)
11398 10:09:01.709625 [0:01:23.467442701] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11399 10:09:01.781474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11400 10:09:01.781771 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11402 10:09:01.792324 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11403 10:09:11.379452 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9684 ms)
11404 10:09:11.392657 [0:01:33.151931627] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11405 10:09:11.446705 [0:01:33.211166110] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11406 10:09:11.481486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11407 10:09:11.482205 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11409 10:09:11.494211 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11410 10:09:11.507211 [0:01:33.268868385] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11411 10:09:11.539829 Camera needs 4 requests, can't test only 1
11412 10:09:11.561150 [0:01:33.325576625] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11413 10:09:11.598734 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11414 10:09:11.648153
11415 10:09:11.706339 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (59 ms)
11416 10:09:11.761828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11417 10:09:11.762609 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11419 10:09:11.771564 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11420 10:09:11.822750 Camera needs 4 requests, can't test only 2
11421 10:09:11.889709 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11422 10:09:11.960217
11423 10:09:12.039515 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (58 ms)
11424 10:09:12.100265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11425 10:09:12.100569 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11427 10:09:12.106534 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11428 10:09:12.137113 Camera needs 4 requests, can't test only 3
11429 10:09:12.180327 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11430 10:09:12.216955
11431 10:09:12.267075 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (57 ms)
11432 10:09:12.318711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11433 10:09:12.319032 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11435 10:09:12.325296 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11436 10:09:12.812006 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1256 ms)
11437 10:09:12.821824 [0:01:34.582031019] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11438 10:09:12.888587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11439 10:09:12.889365 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11441 10:09:12.898560 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11442 10:09:14.203232 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1391 ms)
11443 10:09:14.212675 [0:01:35.973148660] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11444 10:09:14.298751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11445 10:09:14.299759 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11447 10:09:14.307630 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11448 10:09:16.324193 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2121 ms)
11449 10:09:16.333992 [0:01:38.094571256] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11450 10:09:16.401883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11451 10:09:16.402608 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11453 10:09:16.409040 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11454 10:09:19.014011 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2691 ms)
11455 10:09:19.023941 [0:01:40.784673863] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11456 10:09:19.089646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11457 10:09:19.089951 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11459 10:09:19.098844 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11460 10:09:23.233671 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4220 ms)
11461 10:09:23.243280 [0:01:45.004501887] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11462 10:09:23.305754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11463 10:09:23.306108 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11465 10:09:23.312616 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11466 10:09:29.550884 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6318 ms)
11467 10:09:29.560392 [0:01:51.322566187] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11468 10:09:30.339375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11469 10:09:30.339758 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11471 10:09:30.348573 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11472 10:09:39.168738 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9619 ms)
11473 10:09:39.178373 [0:02:00.941952485] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11474 10:09:39.230859 [0:02:00.999742156] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11475 10:09:39.237563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11476 10:09:39.237829 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11478 10:09:39.245355 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11479 10:09:39.277722 Camera needs 4 requests, can't test only 1
11480 10:09:39.287552 [0:02:01.057275908] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11481 10:09:39.333424 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11482 10:09:39.343426 [0:02:01.114115640] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11483 10:09:39.379362
11484 10:09:39.439008 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (58 ms)
11485 10:09:39.502455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11486 10:09:39.502749 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11488 10:09:39.508773 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11489 10:09:39.537508 Camera needs 4 requests, can't test only 2
11490 10:09:39.585482 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11491 10:09:39.629900
11492 10:09:39.693787 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (57 ms)
11493 10:09:39.753937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11494 10:09:39.754238 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11496 10:09:39.761240 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11497 10:09:39.801975 Camera needs 4 requests, can't test only 3
11498 10:09:39.854368 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11499 10:09:39.903874
11500 10:09:39.965318 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (57 ms)
11501 10:09:40.028422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11502 10:09:40.029239 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11504 10:09:40.039256 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11505 10:09:40.566540 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1225 ms)
11506 10:09:40.576436 [0:02:02.338958934] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11507 10:09:40.653978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11508 10:09:40.654289 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11510 10:09:40.665420 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11511 10:09:41.955485 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1390 ms)
11512 10:09:41.965031 [0:02:03.727985993] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11513 10:09:42.020038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11514 10:09:42.020330 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11516 10:09:42.027376 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11517 10:09:44.042408 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2086 ms)
11518 10:09:44.052316 [0:02:05.814648080] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11519 10:09:44.103227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11520 10:09:44.103552 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11522 10:09:44.110330 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11523 10:09:46.829948 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2787 ms)
11524 10:09:46.839655 [0:02:08.602070117] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11525 10:09:46.891203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11526 10:09:46.891526 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11528 10:09:46.897853 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11529 10:09:51.046537 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4216 ms)
11530 10:09:51.056557 [0:02:12.818987912] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11531 10:09:51.112935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11532 10:09:51.113229 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11534 10:09:51.119374 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11535 10:09:57.364243 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6316 ms)
11536 10:09:57.373936 [0:02:19.135653699] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11537 10:09:57.438302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11538 10:09:57.439016 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11540 10:09:57.446585 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11541 10:10:07.046605 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9682 ms)
11542 10:10:07.056288 [0:02:28.817673663] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11543 10:10:07.103655 [0:02:28.869591341] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11544 10:10:07.139295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11545 10:10:07.140257 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11547 10:10:07.155179 [0:02:28.920873416] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11548 10:10:07.161821 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11549 10:10:07.192134 Camera needs 4 requests, can't test only 1
11550 10:10:07.206697 [0:02:28.972213406] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11551 10:10:07.260736 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11552 10:10:07.322801
11553 10:10:07.406275 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (53 ms)
11554 10:10:07.493595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11555 10:10:07.493933 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11557 10:10:07.501941 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11558 10:10:07.543623 Camera needs 4 requests, can't test only 2
11559 10:10:07.609842 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11560 10:10:07.662137
11561 10:10:07.734863 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (51 ms)
11562 10:10:07.803411 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11564 10:10:07.806453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11565 10:10:07.816684 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11566 10:10:07.857415 Camera needs 4 requests, can't test only 3
11567 10:10:07.903998 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11568 10:10:07.951773
11569 10:10:08.021482 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (52 ms)
11570 10:10:08.074803 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11572 10:10:08.078170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11573 10:10:08.085771 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11574 10:10:08.392569 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1190 ms)
11575 10:10:08.402504 [0:02:30.163699035] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11576 10:10:08.473835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11577 10:10:08.474578 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11579 10:10:08.485165 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11580 10:10:09.784035 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1392 ms)
11581 10:10:09.793704 [0:02:31.555325128] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11582 10:10:09.874292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11583 10:10:09.874594 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11585 10:10:09.881406 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11586 10:10:11.873443 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2089 ms)
11587 10:10:11.882718 [0:02:33.644376640] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11588 10:10:11.942601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11589 10:10:11.942876 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11591 10:10:11.948653 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11592 10:10:14.564234 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2691 ms)
11593 10:10:14.574443 [0:02:36.335463453] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11594 10:10:14.644820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11595 10:10:14.645545 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11597 10:10:14.652629 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11598 10:10:18.785283 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4221 ms)
11599 10:10:18.795341 [0:02:40.556542680] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11600 10:10:18.871746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11601 10:10:18.872036 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11603 10:10:18.879906 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11604 10:10:25.056919 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6271 ms)
11605 10:10:25.066858 [0:02:46.826989389] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11606 10:10:25.146722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11607 10:10:25.147019 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11609 10:10:25.158693 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11610 10:10:34.659723 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9604 ms)
11611 10:10:34.669862 [0:02:56.431035368] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11612 10:10:34.761346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11613 10:10:34.762322 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11615 10:10:34.774730 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11616 10:10:34.950298 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (294 ms)
11617 10:10:34.963285 [0:02:56.724170799] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11618 10:10:35.030859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11619 10:10:35.031794 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11621 10:10:35.046237 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11622 10:10:35.211306 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (261 ms)
11623 10:10:35.224103 [0:02:56.986319614] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11624 10:10:35.289749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11625 10:10:35.290065 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11627 10:10:35.301112 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11628 10:10:35.506863 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (295 ms)
11629 10:10:35.519412 [0:02:57.281207489] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11630 10:10:35.582470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11631 10:10:35.583221 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11633 10:10:35.597337 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11634 10:10:35.867483 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (361 ms)
11635 10:10:35.880739 [0:02:57.642075028] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11636 10:10:35.949295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11637 10:10:35.950011 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11639 10:10:35.962360 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11640 10:10:36.328651 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (462 ms)
11641 10:10:36.341852 [0:02:58.103364043] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11642 10:10:36.419609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11643 10:10:36.420507 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11645 10:10:36.431868 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11646 10:10:37.022026 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (693 ms)
11647 10:10:37.035582 [0:02:58.796294992] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11648 10:10:37.098952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11649 10:10:37.099840 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11651 10:10:37.113234 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11652 10:10:37.916161 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (894 ms)
11653 10:10:37.928967 [0:02:59.690612835] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11654 10:10:38.005662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11655 10:10:38.006386 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11657 10:10:38.018633 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11658 10:10:39.245204 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1329 ms)
11659 10:10:39.258299 [0:03:01.019762998] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11660 10:10:39.342819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11661 10:10:39.343707 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11663 10:10:39.357318 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11664 10:10:41.337886 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2093 ms)
11665 10:10:41.350759 [0:03:03.112256197] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11666 10:10:41.402867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11667 10:10:41.403159 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11669 10:10:41.417022 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11670 10:10:44.562292 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3224 ms)
11671 10:10:44.575606 [0:03:06.336971102] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11672 10:10:44.640107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11673 10:10:44.641105 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11675 10:10:44.653350 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11676 10:10:44.858359 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (293 ms)
11677 10:10:44.868254 [0:03:06.630267791] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11678 10:10:44.944217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11679 10:10:44.944601 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11681 10:10:44.954025 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11682 10:10:45.120725 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (262 ms)
11683 10:10:45.130367 [0:03:06.892416447] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11684 10:10:45.215498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11685 10:10:45.216272 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11687 10:10:45.229580 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11688 10:10:45.415390 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (294 ms)
11689 10:10:45.424973 [0:03:07.186862433] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11690 10:10:45.494630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11691 10:10:45.495238 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11693 10:10:45.504621 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11694 10:10:45.775919 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (361 ms)
11695 10:10:45.785615 [0:03:07.547480183] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11696 10:10:45.874578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11697 10:10:45.875404 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11699 10:10:45.887709 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11700 10:10:46.237254 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (461 ms)
11701 10:10:46.247245 [0:03:08.009054443] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11702 10:10:46.312271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11703 10:10:46.313208 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11705 10:10:46.326968 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11706 10:10:46.930233 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (693 ms)
11707 10:10:46.939647 [0:03:08.701740206] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11708 10:10:47.026293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11709 10:10:47.026621 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11711 10:10:47.035958 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11712 10:10:47.823919 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (894 ms)
11713 10:10:47.834004 [0:03:09.596151167] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11714 10:10:47.905467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11715 10:10:47.906345 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11717 10:10:47.918064 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11718 10:10:49.153779 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1330 ms)
11719 10:10:49.163581 [0:03:10.925784470] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11720 10:10:49.228831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11721 10:10:49.229839 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11723 10:10:49.241156 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11724 10:10:51.279122 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2125 ms)
11725 10:10:51.288829 [0:03:13.050730304] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11726 10:10:51.364322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11727 10:10:51.365192 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11729 10:10:51.373451 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11730 10:10:54.503192 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3225 ms)
11731 10:10:54.513200 [0:03:16.275164059] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11732 10:10:54.595258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11733 10:10:54.596109 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11735 10:10:54.607242 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11736 10:10:54.733043 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (229 ms)
11737 10:10:54.742499 [0:03:16.505449335] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11738 10:10:54.814364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11739 10:10:54.814685 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11741 10:10:54.824147 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11742 10:10:54.996022 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (264 ms)
11743 10:10:55.005983 [0:03:16.768766029] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11744 10:10:55.082073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11745 10:10:55.082364 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11747 10:10:55.092131 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11748 10:10:55.291315 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (295 ms)
11749 10:10:55.301770 [0:03:17.063901040] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11750 10:10:55.391110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11751 10:10:55.391944 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11753 10:10:55.404339 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11754 10:10:55.652756 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (362 ms)
11755 10:10:55.662704 [0:03:17.425516855] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11756 10:10:55.714791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11757 10:10:55.715075 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11759 10:10:55.721312 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11760 10:10:56.114803 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (461 ms)
11761 10:10:56.124399 [0:03:17.887099827] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11762 10:10:56.194270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11763 10:10:56.194594 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11765 10:10:56.203505 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11766 10:10:56.807390 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (693 ms)
11767 10:10:56.817285 [0:03:18.579807180] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11768 10:10:56.887823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11769 10:10:56.888152 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11771 10:10:56.896538 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11772 10:10:57.702231 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (895 ms)
11773 10:10:57.711789 [0:03:19.474764820] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11774 10:10:57.781329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11775 10:10:57.781695 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11777 10:10:57.789736 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11778 10:10:59.094912 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1393 ms)
11779 10:10:59.104758 [0:03:20.867318003] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11780 10:10:59.160661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11781 10:10:59.161023 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11783 10:10:59.167761 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11784 10:11:01.123467 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2029 ms)
11785 10:11:01.133421 [0:03:22.896449554] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11786 10:11:01.199757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11787 10:11:01.200078 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11789 10:11:01.207287 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11790 10:11:04.348504 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3225 ms)
11791 10:11:04.358599 [0:03:26.121798232] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11792 10:11:04.408936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11793 10:11:04.409281 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11795 10:11:04.418489 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11796 10:11:04.641916 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (293 ms)
11797 10:11:04.651993 [0:03:26.414782320] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11798 10:11:04.707195 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11800 10:11:04.710249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11801 10:11:04.717563 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11802 10:11:04.903290 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (262 ms)
11803 10:11:04.912774 [0:03:26.676696140] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11804 10:11:04.960822 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11806 10:11:04.963795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11807 10:11:04.971241 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11808 10:11:05.197902 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (295 ms)
11809 10:11:05.208004 [0:03:26.971318400] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11810 10:11:05.262984 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11812 10:11:05.265642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11813 10:11:05.272660 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11814 10:11:05.559201 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (361 ms)
11815 10:11:05.569040 [0:03:27.332928179] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11816 10:11:05.621343 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11818 10:11:05.624464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11819 10:11:05.634183 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11820 10:11:06.022431 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (463 ms)
11821 10:11:06.032248 [0:03:27.795911748] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11822 10:11:06.095054 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11824 10:11:06.097759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11825 10:11:06.105816 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11826 10:11:06.748387 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (726 ms)
11827 10:11:06.758341 [0:03:28.521993749] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11828 10:11:06.807949 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11830 10:11:06.811040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11831 10:11:06.820536 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11832 10:11:07.644674 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (897 ms)
11833 10:11:07.654590 [0:03:29.418631574] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11834 10:11:07.715884 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11836 10:11:07.718577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11837 10:11:07.727575 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11838 10:11:09.037698 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1392 ms)
11839 10:11:09.047211 [0:03:30.810989730] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11840 10:11:09.096472 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11842 10:11:09.099566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11843 10:11:09.108631 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11844 10:11:11.065729 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2029 ms)
11845 10:11:11.075745 [0:03:32.839772286] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11846 10:11:11.121802 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11848 10:11:11.124794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11849 10:11:11.132739 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11850 10:11:14.291089 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3225 ms)
11851 10:11:14.347619 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11853 10:11:14.350783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11854 10:11:14.358728 [----------] 120 tests from CaptureTests/SingleStream (188380 ms total)
11855 10:11:14.402863
11856 10:11:14.457480 [----------] Global test environment tear-down
11857 10:11:14.500505 [==========] 120 tests from 1 test suite ran. (188380 ms total)
11858 10:11:14.543614 <LAVA_SIGNAL_TESTSET STOP>
11859 10:11:14.543895 Received signal: <TESTSET> STOP
11860 10:11:14.543972 Closing test_set CaptureTests/SingleStream
11861 10:11:14.548896 + set +x
11862 10:11:14.552005 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 10670702_1.6.2.3.1>
11863 10:11:14.552254 Received signal: <ENDRUN> 0_lc-compliance 10670702_1.6.2.3.1
11864 10:11:14.552347 Ending use of test pattern.
11865 10:11:14.552414 Ending test lava.0_lc-compliance (10670702_1.6.2.3.1), duration 189.63
11867 10:11:14.555498 <LAVA_TEST_RUNNER EXIT>
11868 10:11:14.555756 ok: lava_test_shell seems to have completed
11869 10:11:14.557649 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11870 10:11:14.557834 end: 3.1 lava-test-shell (duration 00:03:10) [common]
11871 10:11:14.557937 end: 3 lava-test-retry (duration 00:03:10) [common]
11872 10:11:14.558042 start: 4 finalize (timeout 00:10:00) [common]
11873 10:11:14.558143 start: 4.1 power-off (timeout 00:00:30) [common]
11874 10:11:14.558311 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11875 10:11:14.633207 >> Command sent successfully.
11876 10:11:14.635478 Returned 0 in 0 seconds
11877 10:11:14.735868 end: 4.1 power-off (duration 00:00:00) [common]
11879 10:11:14.736229 start: 4.2 read-feedback (timeout 00:10:00) [common]
11880 10:11:14.736498 Listened to connection for namespace 'common' for up to 1s
11881 10:11:15.736877 Finalising connection for namespace 'common'
11882 10:11:15.737067 Disconnecting from shell: Finalise
11883 10:11:15.737171 / #
11884 10:11:15.837524 end: 4.2 read-feedback (duration 00:00:01) [common]
11885 10:11:15.837702 end: 4 finalize (duration 00:00:01) [common]
11886 10:11:15.837836 Cleaning after the job
11887 10:11:15.837947 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/ramdisk
11888 10:11:15.840011 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/kernel
11889 10:11:15.849021 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/dtb
11890 10:11:15.849221 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/nfsrootfs
11891 10:11:15.893092 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670702/tftp-deploy-vgedlg5m/modules
11892 10:11:15.898534 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10670702
11893 10:11:16.158121 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10670702
11894 10:11:16.158325 Job finished correctly