Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 132
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
- Errors: 0
1 10:00:55.372174 lava-dispatcher, installed at version: 2023.05.1
2 10:00:55.372396 start: 0 validate
3 10:00:55.372540 Start time: 2023-06-10 10:00:55.372532+00:00 (UTC)
4 10:00:55.372672 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:00:55.372802 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 10:00:55.629658 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:00:55.630477 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:01:09.391443 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:01:09.392296 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:01:09.665120 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:01:09.665961 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:01:12.936425 validate duration: 17.56
14 10:01:12.936721 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:01:12.936832 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:01:12.936934 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:01:12.937075 Not decompressing ramdisk as can be used compressed.
18 10:01:12.937199 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/rootfs.cpio.gz
19 10:01:12.937275 saving as /var/lib/lava/dispatcher/tmp/10670675/tftp-deploy-2_f07u3u/ramdisk/rootfs.cpio.gz
20 10:01:12.937355 total size: 84903995 (80MB)
21 10:01:13.215475 progress 0% (0MB)
22 10:01:13.237295 progress 5% (4MB)
23 10:01:13.258628 progress 10% (8MB)
24 10:01:13.279622 progress 15% (12MB)
25 10:01:13.301093 progress 20% (16MB)
26 10:01:13.322107 progress 25% (20MB)
27 10:01:13.343551 progress 30% (24MB)
28 10:01:13.364799 progress 35% (28MB)
29 10:01:13.386149 progress 40% (32MB)
30 10:01:13.407227 progress 45% (36MB)
31 10:01:13.428505 progress 50% (40MB)
32 10:01:13.449880 progress 55% (44MB)
33 10:01:13.471070 progress 60% (48MB)
34 10:01:13.492509 progress 65% (52MB)
35 10:01:13.513429 progress 70% (56MB)
36 10:01:13.534683 progress 75% (60MB)
37 10:01:13.555862 progress 80% (64MB)
38 10:01:13.577372 progress 85% (68MB)
39 10:01:13.598541 progress 90% (72MB)
40 10:01:13.619650 progress 95% (76MB)
41 10:01:13.640720 progress 100% (80MB)
42 10:01:13.640905 80MB downloaded in 0.70s (115.09MB/s)
43 10:01:13.641090 end: 1.1.1 http-download (duration 00:00:01) [common]
45 10:01:13.641370 end: 1.1 download-retry (duration 00:00:01) [common]
46 10:01:13.641473 start: 1.2 download-retry (timeout 00:09:59) [common]
47 10:01:13.641576 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 10:01:13.641727 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:01:13.641831 saving as /var/lib/lava/dispatcher/tmp/10670675/tftp-deploy-2_f07u3u/kernel/Image
50 10:01:13.641935 total size: 45746688 (43MB)
51 10:01:13.642039 No compression specified
52 10:01:13.643653 progress 0% (0MB)
53 10:01:13.655176 progress 5% (2MB)
54 10:01:13.666757 progress 10% (4MB)
55 10:01:13.678462 progress 15% (6MB)
56 10:01:13.690227 progress 20% (8MB)
57 10:01:13.701894 progress 25% (10MB)
58 10:01:13.713365 progress 30% (13MB)
59 10:01:13.724891 progress 35% (15MB)
60 10:01:13.736382 progress 40% (17MB)
61 10:01:13.748208 progress 45% (19MB)
62 10:01:13.759899 progress 50% (21MB)
63 10:01:13.771462 progress 55% (24MB)
64 10:01:13.783258 progress 60% (26MB)
65 10:01:13.795068 progress 65% (28MB)
66 10:01:13.806556 progress 70% (30MB)
67 10:01:13.818051 progress 75% (32MB)
68 10:01:13.829397 progress 80% (34MB)
69 10:01:13.840861 progress 85% (37MB)
70 10:01:13.852603 progress 90% (39MB)
71 10:01:13.864266 progress 95% (41MB)
72 10:01:13.875815 progress 100% (43MB)
73 10:01:13.875992 43MB downloaded in 0.23s (186.40MB/s)
74 10:01:13.876165 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:01:13.876430 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:01:13.876532 start: 1.3 download-retry (timeout 00:09:59) [common]
78 10:01:13.876641 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 10:01:13.876798 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:01:13.876904 saving as /var/lib/lava/dispatcher/tmp/10670675/tftp-deploy-2_f07u3u/dtb/mt8192-asurada-spherion-r0.dtb
81 10:01:13.877007 total size: 46924 (0MB)
82 10:01:13.877108 No compression specified
83 10:01:13.878892 progress 69% (0MB)
84 10:01:13.879192 progress 100% (0MB)
85 10:01:13.879357 0MB downloaded in 0.00s (19.05MB/s)
86 10:01:13.879531 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:01:13.879786 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:01:13.879913 start: 1.4 download-retry (timeout 00:09:59) [common]
90 10:01:13.880039 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 10:01:13.880235 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:01:13.880326 saving as /var/lib/lava/dispatcher/tmp/10670675/tftp-deploy-2_f07u3u/modules/modules.tar
93 10:01:13.880408 total size: 8540248 (8MB)
94 10:01:13.880510 Using unxz to decompress xz
95 10:01:13.884289 progress 0% (0MB)
96 10:01:13.906575 progress 5% (0MB)
97 10:01:13.930990 progress 10% (0MB)
98 10:01:13.955220 progress 15% (1MB)
99 10:01:13.980342 progress 20% (1MB)
100 10:01:14.005029 progress 25% (2MB)
101 10:01:14.028100 progress 30% (2MB)
102 10:01:14.053827 progress 35% (2MB)
103 10:01:14.078564 progress 40% (3MB)
104 10:01:14.102568 progress 45% (3MB)
105 10:01:14.129950 progress 50% (4MB)
106 10:01:14.154920 progress 55% (4MB)
107 10:01:14.180845 progress 60% (4MB)
108 10:01:14.206917 progress 65% (5MB)
109 10:01:14.232342 progress 70% (5MB)
110 10:01:14.256477 progress 75% (6MB)
111 10:01:14.279865 progress 80% (6MB)
112 10:01:14.304175 progress 85% (6MB)
113 10:01:14.334337 progress 90% (7MB)
114 10:01:14.359757 progress 95% (7MB)
115 10:01:14.384991 progress 100% (8MB)
116 10:01:14.390297 8MB downloaded in 0.51s (15.97MB/s)
117 10:01:14.390602 end: 1.4.1 http-download (duration 00:00:01) [common]
119 10:01:14.390913 end: 1.4 download-retry (duration 00:00:01) [common]
120 10:01:14.391010 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 10:01:14.391107 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 10:01:14.391193 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:01:14.391280 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 10:01:14.391539 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv
125 10:01:14.391678 makedir: /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin
126 10:01:14.391783 makedir: /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/tests
127 10:01:14.391880 makedir: /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/results
128 10:01:14.391995 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-add-keys
129 10:01:14.392140 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-add-sources
130 10:01:14.392267 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-background-process-start
131 10:01:14.392391 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-background-process-stop
132 10:01:14.392567 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-common-functions
133 10:01:14.392688 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-echo-ipv4
134 10:01:14.392807 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-install-packages
135 10:01:14.392925 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-installed-packages
136 10:01:14.393042 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-os-build
137 10:01:14.393162 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-probe-channel
138 10:01:14.393313 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-probe-ip
139 10:01:14.393473 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-target-ip
140 10:01:14.393625 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-target-mac
141 10:01:14.393746 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-target-storage
142 10:01:14.393873 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-test-case
143 10:01:14.393996 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-test-event
144 10:01:14.394115 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-test-feedback
145 10:01:14.394236 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-test-raise
146 10:01:14.394376 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-test-reference
147 10:01:14.394505 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-test-runner
148 10:01:14.394625 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-test-set
149 10:01:14.394747 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-test-shell
150 10:01:14.394907 Updating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-install-packages (oe)
151 10:01:14.395056 Updating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/bin/lava-installed-packages (oe)
152 10:01:14.395175 Creating /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/environment
153 10:01:14.395272 LAVA metadata
154 10:01:14.395348 - LAVA_JOB_ID=10670675
155 10:01:14.395412 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:01:14.395516 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 10:01:14.395584 skipped lava-vland-overlay
158 10:01:14.395657 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:01:14.395737 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 10:01:14.395799 skipped lava-multinode-overlay
161 10:01:14.395872 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:01:14.395955 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 10:01:14.396029 Loading test definitions
164 10:01:14.396116 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 10:01:14.396203 Using /lava-10670675 at stage 0
166 10:01:14.396310 Fetching tests from https://github.com/kernelci/kernelci-core
167 10:01:14.396391 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/0/tests/0_sleep'
168 10:01:15.133530 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/0/tests/0_sleep
169 10:01:15.134958 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 10:01:15.135431 uuid=10670675_1.5.2.3.1 testdef=None
171 10:01:15.135632 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 10:01:15.135938 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 10:01:15.136614 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 10:01:15.136912 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 10:01:15.137770 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 10:01:15.138063 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 10:01:15.138795 runner path: /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/0/tests/0_sleep test_uuid 10670675_1.5.2.3.1
181 10:01:15.138902 sleep_params='mem freeze'
182 10:01:15.139061 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 10:01:15.139302 Creating lava-test-runner.conf files
185 10:01:15.139375 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10670675/lava-overlay-kguijhbv/lava-10670675/0 for stage 0
186 10:01:15.139497 - 0_sleep
187 10:01:15.139656 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 10:01:15.139758 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 10:01:15.259310 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 10:01:15.259472 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 10:01:15.259571 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 10:01:15.259678 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 10:01:15.259774 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 10:01:17.599950 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 10:01:17.600339 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 10:01:17.600458 extracting modules file /var/lib/lava/dispatcher/tmp/10670675/tftp-deploy-2_f07u3u/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670675/extract-overlay-ramdisk-yz0yni3z/ramdisk
197 10:01:17.808139 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 10:01:17.808310 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 10:01:17.808407 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670675/compress-overlay-kmzmel16/overlay-1.5.2.4.tar.gz to ramdisk
200 10:01:17.808481 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670675/compress-overlay-kmzmel16/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10670675/extract-overlay-ramdisk-yz0yni3z/ramdisk
201 10:01:17.896420 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 10:01:17.896590 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 10:01:17.896686 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 10:01:17.896792 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 10:01:17.896878 Building ramdisk /var/lib/lava/dispatcher/tmp/10670675/extract-overlay-ramdisk-yz0yni3z/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10670675/extract-overlay-ramdisk-yz0yni3z/ramdisk
206 10:01:19.343183 >> 561596 blocks
207 10:01:29.088320 rename /var/lib/lava/dispatcher/tmp/10670675/extract-overlay-ramdisk-yz0yni3z/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10670675/tftp-deploy-2_f07u3u/ramdisk/ramdisk.cpio.gz
208 10:01:29.088770 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 10:01:29.088908 start: 1.5.8 prepare-kernel (timeout 00:09:44) [common]
210 10:01:29.089013 start: 1.5.8.1 prepare-fit (timeout 00:09:44) [common]
211 10:01:29.089130 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10670675/tftp-deploy-2_f07u3u/kernel/Image'
212 10:01:40.670822 Returned 0 in 11 seconds
213 10:01:40.771468 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10670675/tftp-deploy-2_f07u3u/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10670675/tftp-deploy-2_f07u3u/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10670675/tftp-deploy-2_f07u3u/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10670675/tftp-deploy-2_f07u3u/kernel/image.itb
214 10:01:42.043195 output: FIT description: Kernel Image image with one or more FDT blobs
215 10:01:42.043566 output: Created: Sat Jun 10 11:01:41 2023
216 10:01:42.043648 output: Image 0 (kernel-1)
217 10:01:42.043716 output: Description:
218 10:01:42.043783 output: Created: Sat Jun 10 11:01:41 2023
219 10:01:42.043844 output: Type: Kernel Image
220 10:01:42.043909 output: Compression: lzma compressed
221 10:01:42.043970 output: Data Size: 10087317 Bytes = 9850.90 KiB = 9.62 MiB
222 10:01:42.044034 output: Architecture: AArch64
223 10:01:42.044095 output: OS: Linux
224 10:01:42.044157 output: Load Address: 0x00000000
225 10:01:42.044218 output: Entry Point: 0x00000000
226 10:01:42.044277 output: Hash algo: crc32
227 10:01:42.044333 output: Hash value: c9e456fd
228 10:01:42.044389 output: Image 1 (fdt-1)
229 10:01:42.044449 output: Description: mt8192-asurada-spherion-r0
230 10:01:42.044504 output: Created: Sat Jun 10 11:01:41 2023
231 10:01:42.044559 output: Type: Flat Device Tree
232 10:01:42.044614 output: Compression: uncompressed
233 10:01:42.044669 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
234 10:01:42.044725 output: Architecture: AArch64
235 10:01:42.044780 output: Hash algo: crc32
236 10:01:42.044834 output: Hash value: 1df858fa
237 10:01:42.044889 output: Image 2 (ramdisk-1)
238 10:01:42.044944 output: Description: unavailable
239 10:01:42.044999 output: Created: Sat Jun 10 11:01:41 2023
240 10:01:42.045054 output: Type: RAMDisk Image
241 10:01:42.045109 output: Compression: Unknown Compression
242 10:01:42.045164 output: Data Size: 98124468 Bytes = 95824.68 KiB = 93.58 MiB
243 10:01:42.045219 output: Architecture: AArch64
244 10:01:42.045273 output: OS: Linux
245 10:01:42.045327 output: Load Address: unavailable
246 10:01:42.045381 output: Entry Point: unavailable
247 10:01:42.045435 output: Hash algo: crc32
248 10:01:42.045489 output: Hash value: c6e29e62
249 10:01:42.045544 output: Default Configuration: 'conf-1'
250 10:01:42.045603 output: Configuration 0 (conf-1)
251 10:01:42.045658 output: Description: mt8192-asurada-spherion-r0
252 10:01:42.045712 output: Kernel: kernel-1
253 10:01:42.045767 output: Init Ramdisk: ramdisk-1
254 10:01:42.045843 output: FDT: fdt-1
255 10:01:42.045902 output: Loadables: kernel-1
256 10:01:42.045958 output:
257 10:01:42.046156 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
258 10:01:42.046261 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
259 10:01:42.046369 end: 1.5 prepare-tftp-overlay (duration 00:00:28) [common]
260 10:01:42.046463 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:31) [common]
261 10:01:42.046549 No LXC device requested
262 10:01:42.046632 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 10:01:42.046722 start: 1.7 deploy-device-env (timeout 00:09:31) [common]
264 10:01:42.046803 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 10:01:42.046918 Checking files for TFTP limit of 4294967296 bytes.
266 10:01:42.047417 end: 1 tftp-deploy (duration 00:00:29) [common]
267 10:01:42.047526 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 10:01:42.047623 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 10:01:42.047746 substitutions:
270 10:01:42.047815 - {DTB}: 10670675/tftp-deploy-2_f07u3u/dtb/mt8192-asurada-spherion-r0.dtb
271 10:01:42.047881 - {INITRD}: 10670675/tftp-deploy-2_f07u3u/ramdisk/ramdisk.cpio.gz
272 10:01:42.047942 - {KERNEL}: 10670675/tftp-deploy-2_f07u3u/kernel/Image
273 10:01:42.048001 - {LAVA_MAC}: None
274 10:01:42.048062 - {PRESEED_CONFIG}: None
275 10:01:42.048121 - {PRESEED_LOCAL}: None
276 10:01:42.048179 - {RAMDISK}: 10670675/tftp-deploy-2_f07u3u/ramdisk/ramdisk.cpio.gz
277 10:01:42.048237 - {ROOT_PART}: None
278 10:01:42.048293 - {ROOT}: None
279 10:01:42.048349 - {SERVER_IP}: 192.168.201.1
280 10:01:42.048404 - {TEE}: None
281 10:01:42.048459 Parsed boot commands:
282 10:01:42.048516 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 10:01:42.048693 Parsed boot commands: tftpboot 192.168.201.1 10670675/tftp-deploy-2_f07u3u/kernel/image.itb 10670675/tftp-deploy-2_f07u3u/kernel/cmdline
284 10:01:42.048784 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 10:01:42.048873 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 10:01:42.048967 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 10:01:42.049057 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 10:01:42.049131 Not connected, no need to disconnect.
289 10:01:42.049207 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 10:01:42.049290 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 10:01:42.049359 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
292 10:01:42.052915 Setting prompt string to ['lava-test: # ']
293 10:01:42.053289 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 10:01:42.053404 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 10:01:42.053501 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 10:01:42.053598 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 10:01:42.053792 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
298 10:01:47.185778 >> Command sent successfully.
299 10:01:47.188197 Returned 0 in 5 seconds
300 10:01:47.288630 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 10:01:47.288979 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 10:01:47.289097 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 10:01:47.289192 Setting prompt string to 'Starting depthcharge on Spherion...'
305 10:01:47.289264 Changing prompt to 'Starting depthcharge on Spherion...'
306 10:01:47.289344 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 10:01:47.289617 [Enter `^Ec?' for help]
308 10:01:47.460260
309 10:01:47.460426
310 10:01:47.460500 F0: 102B 0000
311 10:01:47.460574
312 10:01:47.460637 F3: 1001 0000 [0200]
313 10:01:47.463923
314 10:01:47.464005 F3: 1001 0000
315 10:01:47.464071
316 10:01:47.464135 F7: 102D 0000
317 10:01:47.464197
318 10:01:47.466486 F1: 0000 0000
319 10:01:47.466564
320 10:01:47.466626 V0: 0000 0000 [0001]
321 10:01:47.466689
322 10:01:47.470043 00: 0007 8000
323 10:01:47.470126
324 10:01:47.470223 01: 0000 0000
325 10:01:47.470346
326 10:01:47.473096 BP: 0C00 0209 [0000]
327 10:01:47.473169
328 10:01:47.473232 G0: 1182 0000
329 10:01:47.473293
330 10:01:47.476706 EC: 0000 0021 [4000]
331 10:01:47.476783
332 10:01:47.476846 S7: 0000 0000 [0000]
333 10:01:47.476907
334 10:01:47.480225 CC: 0000 0000 [0001]
335 10:01:47.480298
336 10:01:47.480361 T0: 0000 0040 [010F]
337 10:01:47.480421
338 10:01:47.483698 Jump to BL
339 10:01:47.483779
340 10:01:47.507299
341 10:01:47.507431
342 10:01:47.507506
343 10:01:47.513861 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 10:01:47.517295 ARM64: Exception handlers installed.
345 10:01:47.521388 ARM64: Testing exception
346 10:01:47.524407 ARM64: Done test exception
347 10:01:47.530977 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 10:01:47.541155 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 10:01:47.548055 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 10:01:47.558020 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 10:01:47.564268 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 10:01:47.574817 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 10:01:47.585828 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 10:01:47.591841 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 10:01:47.609757 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 10:01:47.613503 WDT: Last reset was cold boot
357 10:01:47.616554 SPI1(PAD0) initialized at 2873684 Hz
358 10:01:47.619911 SPI5(PAD0) initialized at 992727 Hz
359 10:01:47.623384 VBOOT: Loading verstage.
360 10:01:47.629946 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 10:01:47.633223 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 10:01:47.636724 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 10:01:47.640010 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 10:01:47.647623 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 10:01:47.653860 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 10:01:47.665237 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
367 10:01:47.665326
368 10:01:47.665395
369 10:01:47.674797 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 10:01:47.678187 ARM64: Exception handlers installed.
371 10:01:47.681367 ARM64: Testing exception
372 10:01:47.681454 ARM64: Done test exception
373 10:01:47.688288 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 10:01:47.692223 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 10:01:47.706383 Probing TPM: . done!
376 10:01:47.706481 TPM ready after 0 ms
377 10:01:47.712410 Connected to device vid:did:rid of 1ae0:0028:00
378 10:01:47.761842 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
379 10:01:47.761998 Initialized TPM device CR50 revision 0
380 10:01:47.774169 tlcl_send_startup: Startup return code is 0
381 10:01:47.774261 TPM: setup succeeded
382 10:01:47.785040 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 10:01:47.793805 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 10:01:47.805453 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 10:01:47.814750 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 10:01:47.817903 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 10:01:47.821495 in-header: 03 07 00 00 08 00 00 00
388 10:01:47.825507 in-data: aa e4 47 04 13 02 00 00
389 10:01:47.828816 Chrome EC: UHEPI supported
390 10:01:47.832261 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 10:01:47.838060 in-header: 03 9d 00 00 08 00 00 00
392 10:01:47.841565 in-data: 10 20 20 08 00 00 00 00
393 10:01:47.841682 Phase 1
394 10:01:47.845267 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 10:01:47.852863 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 10:01:47.860120 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 10:01:47.860237 Recovery requested (1009000e)
398 10:01:47.869050 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 10:01:47.874223 tlcl_extend: response is 0
400 10:01:47.882478 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 10:01:47.888103 tlcl_extend: response is 0
402 10:01:47.894313 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 10:01:47.915421 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
404 10:01:47.923113 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 10:01:47.923250
406 10:01:47.923393
407 10:01:47.933350 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 10:01:47.937047 ARM64: Exception handlers installed.
409 10:01:47.937159 ARM64: Testing exception
410 10:01:47.940214 ARM64: Done test exception
411 10:01:47.960567 pmic_efuse_setting: Set efuses in 11 msecs
412 10:01:47.964339 pmwrap_interface_init: Select PMIF_VLD_RDY
413 10:01:47.971423 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 10:01:47.974737 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 10:01:47.978334 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 10:01:47.985686 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 10:01:47.988673 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 10:01:47.992499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 10:01:47.999441 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 10:01:48.003180 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 10:01:48.006148 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 10:01:48.012720 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 10:01:48.016303 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 10:01:48.023179 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 10:01:48.026223 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 10:01:48.032493 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 10:01:48.039757 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 10:01:48.042596 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 10:01:48.049477 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 10:01:48.055989 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 10:01:48.059821 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 10:01:48.066254 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 10:01:48.074123 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 10:01:48.077349 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 10:01:48.084047 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 10:01:48.087727 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 10:01:48.094420 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 10:01:48.101553 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 10:01:48.104819 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 10:01:48.108832 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 10:01:48.116127 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 10:01:48.119017 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 10:01:48.126069 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 10:01:48.129040 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 10:01:48.136333 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 10:01:48.140963 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 10:01:48.143166 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 10:01:48.150407 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 10:01:48.153894 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 10:01:48.160529 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 10:01:48.164012 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 10:01:48.167073 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 10:01:48.173776 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 10:01:48.177232 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 10:01:48.180342 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 10:01:48.187208 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 10:01:48.190474 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 10:01:48.193823 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 10:01:48.197370 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 10:01:48.203779 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 10:01:48.207454 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 10:01:48.210598 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 10:01:48.213930 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 10:01:48.223864 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 10:01:48.230166 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 10:01:48.237071 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 10:01:48.243337 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 10:01:48.253830 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 10:01:48.256866 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 10:01:48.263410 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 10:01:48.266620 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 10:01:48.273144 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
473 10:01:48.279885 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 10:01:48.283259 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
475 10:01:48.286818 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 10:01:48.297452 [RTC]rtc_get_frequency_meter,154: input=15, output=794
477 10:01:48.301085 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 10:01:48.307749 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 10:01:48.311318 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 10:01:48.314321 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 10:01:48.317799 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 10:01:48.321450 ADC[4]: Raw value=894821 ID=7
483 10:01:48.324449 ADC[3]: Raw value=213440 ID=1
484 10:01:48.327698 RAM Code: 0x71
485 10:01:48.331334 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 10:01:48.334550 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 10:01:48.344173 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 10:01:48.351374 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 10:01:48.354309 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 10:01:48.357912 in-header: 03 07 00 00 08 00 00 00
491 10:01:48.361204 in-data: aa e4 47 04 13 02 00 00
492 10:01:48.364160 Chrome EC: UHEPI supported
493 10:01:48.371078 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 10:01:48.375045 in-header: 03 d5 00 00 08 00 00 00
495 10:01:48.378496 in-data: 98 20 60 08 00 00 00 00
496 10:01:48.378588 MRC: failed to locate region type 0.
497 10:01:48.385860 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 10:01:48.389196 DRAM-K: Running full calibration
499 10:01:48.395844 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 10:01:48.399037 header.status = 0x0
501 10:01:48.402720 header.version = 0x6 (expected: 0x6)
502 10:01:48.405824 header.size = 0xd00 (expected: 0xd00)
503 10:01:48.405910 header.flags = 0x0
504 10:01:48.412451 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 10:01:48.429869 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
506 10:01:48.436366 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 10:01:48.439652 dram_init: ddr_geometry: 2
508 10:01:48.442995 [EMI] MDL number = 2
509 10:01:48.443086 [EMI] Get MDL freq = 0
510 10:01:48.446520 dram_init: ddr_type: 0
511 10:01:48.446606 is_discrete_lpddr4: 1
512 10:01:48.449536 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 10:01:48.449622
514 10:01:48.449691
515 10:01:48.453190 [Bian_co] ETT version 0.0.0.1
516 10:01:48.460251 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 10:01:48.460344
518 10:01:48.462937 dramc_set_vcore_voltage set vcore to 650000
519 10:01:48.466248 Read voltage for 800, 4
520 10:01:48.466335 Vio18 = 0
521 10:01:48.466404 Vcore = 650000
522 10:01:48.469401 Vdram = 0
523 10:01:48.469487 Vddq = 0
524 10:01:48.469555 Vmddr = 0
525 10:01:48.472772 dram_init: config_dvfs: 1
526 10:01:48.476318 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 10:01:48.482663 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 10:01:48.486357 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
529 10:01:48.489266 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
530 10:01:48.492763 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 10:01:48.499570 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 10:01:48.499660 MEM_TYPE=3, freq_sel=18
533 10:01:48.502731 sv_algorithm_assistance_LP4_1600
534 10:01:48.506137 ============ PULL DRAM RESETB DOWN ============
535 10:01:48.512920 ========== PULL DRAM RESETB DOWN end =========
536 10:01:48.515821 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 10:01:48.519303 ===================================
538 10:01:48.522699 LPDDR4 DRAM CONFIGURATION
539 10:01:48.526118 ===================================
540 10:01:48.526206 EX_ROW_EN[0] = 0x0
541 10:01:48.529276 EX_ROW_EN[1] = 0x0
542 10:01:48.529362 LP4Y_EN = 0x0
543 10:01:48.532860 WORK_FSP = 0x0
544 10:01:48.532945 WL = 0x2
545 10:01:48.536691 RL = 0x2
546 10:01:48.536777 BL = 0x2
547 10:01:48.540648 RPST = 0x0
548 10:01:48.540740 RD_PRE = 0x0
549 10:01:48.544127 WR_PRE = 0x1
550 10:01:48.544228 WR_PST = 0x0
551 10:01:48.547675 DBI_WR = 0x0
552 10:01:48.547763 DBI_RD = 0x0
553 10:01:48.551006 OTF = 0x1
554 10:01:48.551094 ===================================
555 10:01:48.555124 ===================================
556 10:01:48.558512 ANA top config
557 10:01:48.562203 ===================================
558 10:01:48.562295 DLL_ASYNC_EN = 0
559 10:01:48.565894 ALL_SLAVE_EN = 1
560 10:01:48.569376 NEW_RANK_MODE = 1
561 10:01:48.569467 DLL_IDLE_MODE = 1
562 10:01:48.573273 LP45_APHY_COMB_EN = 1
563 10:01:48.576725 TX_ODT_DIS = 1
564 10:01:48.580294 NEW_8X_MODE = 1
565 10:01:48.580386 ===================================
566 10:01:48.584049 ===================================
567 10:01:48.588089 data_rate = 1600
568 10:01:48.591610 CKR = 1
569 10:01:48.594960 DQ_P2S_RATIO = 8
570 10:01:48.598552 ===================================
571 10:01:48.598645 CA_P2S_RATIO = 8
572 10:01:48.602468 DQ_CA_OPEN = 0
573 10:01:48.606104 DQ_SEMI_OPEN = 0
574 10:01:48.609715 CA_SEMI_OPEN = 0
575 10:01:48.609805 CA_FULL_RATE = 0
576 10:01:48.613430 DQ_CKDIV4_EN = 1
577 10:01:48.616923 CA_CKDIV4_EN = 1
578 10:01:48.620903 CA_PREDIV_EN = 0
579 10:01:48.620995 PH8_DLY = 0
580 10:01:48.624062 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 10:01:48.627109 DQ_AAMCK_DIV = 4
582 10:01:48.630488 CA_AAMCK_DIV = 4
583 10:01:48.633956 CA_ADMCK_DIV = 4
584 10:01:48.637042 DQ_TRACK_CA_EN = 0
585 10:01:48.637128 CA_PICK = 800
586 10:01:48.640619 CA_MCKIO = 800
587 10:01:48.643732 MCKIO_SEMI = 0
588 10:01:48.647080 PLL_FREQ = 3068
589 10:01:48.650797 DQ_UI_PI_RATIO = 32
590 10:01:48.654282 CA_UI_PI_RATIO = 0
591 10:01:48.657232 ===================================
592 10:01:48.659992 ===================================
593 10:01:48.663681 memory_type:LPDDR4
594 10:01:48.663767 GP_NUM : 10
595 10:01:48.667084 SRAM_EN : 1
596 10:01:48.667170 MD32_EN : 0
597 10:01:48.670256 ===================================
598 10:01:48.673747 [ANA_INIT] >>>>>>>>>>>>>>
599 10:01:48.676837 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 10:01:48.680063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 10:01:48.683654 ===================================
602 10:01:48.687135 data_rate = 1600,PCW = 0X7600
603 10:01:48.690567 ===================================
604 10:01:48.693395 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 10:01:48.699707 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 10:01:48.703047 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 10:01:48.709863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 10:01:48.713922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 10:01:48.714012 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 10:01:48.717395 [ANA_INIT] flow start
611 10:01:48.720711 [ANA_INIT] PLL >>>>>>>>
612 10:01:48.720799 [ANA_INIT] PLL <<<<<<<<
613 10:01:48.723740 [ANA_INIT] MIDPI >>>>>>>>
614 10:01:48.727470 [ANA_INIT] MIDPI <<<<<<<<
615 10:01:48.727558 [ANA_INIT] DLL >>>>>>>>
616 10:01:48.731216 [ANA_INIT] flow end
617 10:01:48.735138 ============ LP4 DIFF to SE enter ============
618 10:01:48.738407 ============ LP4 DIFF to SE exit ============
619 10:01:48.742351 [ANA_INIT] <<<<<<<<<<<<<
620 10:01:48.745979 [Flow] Enable top DCM control >>>>>
621 10:01:48.749629 [Flow] Enable top DCM control <<<<<
622 10:01:48.749749 Enable DLL master slave shuffle
623 10:01:48.757366 ==============================================================
624 10:01:48.757463 Gating Mode config
625 10:01:48.763612 ==============================================================
626 10:01:48.766745 Config description:
627 10:01:48.773968 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 10:01:48.780120 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 10:01:48.786707 SELPH_MODE 0: By rank 1: By Phase
630 10:01:48.793637 ==============================================================
631 10:01:48.796748 GAT_TRACK_EN = 1
632 10:01:48.796835 RX_GATING_MODE = 2
633 10:01:48.799986 RX_GATING_TRACK_MODE = 2
634 10:01:48.803306 SELPH_MODE = 1
635 10:01:48.806652 PICG_EARLY_EN = 1
636 10:01:48.809930 VALID_LAT_VALUE = 1
637 10:01:48.816732 ==============================================================
638 10:01:48.819939 Enter into Gating configuration >>>>
639 10:01:48.823101 Exit from Gating configuration <<<<
640 10:01:48.826317 Enter into DVFS_PRE_config >>>>>
641 10:01:48.836453 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 10:01:48.839701 Exit from DVFS_PRE_config <<<<<
643 10:01:48.843320 Enter into PICG configuration >>>>
644 10:01:48.846541 Exit from PICG configuration <<<<
645 10:01:48.849604 [RX_INPUT] configuration >>>>>
646 10:01:48.853052 [RX_INPUT] configuration <<<<<
647 10:01:48.856602 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 10:01:48.863067 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 10:01:48.869397 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 10:01:48.875990 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 10:01:48.879667 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 10:01:48.886454 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 10:01:48.889835 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 10:01:48.895946 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 10:01:48.899498 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 10:01:48.902984 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 10:01:48.906059 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 10:01:48.912856 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 10:01:48.916079 ===================================
660 10:01:48.916177 LPDDR4 DRAM CONFIGURATION
661 10:01:48.919328 ===================================
662 10:01:48.922664 EX_ROW_EN[0] = 0x0
663 10:01:48.926018 EX_ROW_EN[1] = 0x0
664 10:01:48.926109 LP4Y_EN = 0x0
665 10:01:48.929089 WORK_FSP = 0x0
666 10:01:48.929177 WL = 0x2
667 10:01:48.932379 RL = 0x2
668 10:01:48.932467 BL = 0x2
669 10:01:48.935575 RPST = 0x0
670 10:01:48.935662 RD_PRE = 0x0
671 10:01:48.939265 WR_PRE = 0x1
672 10:01:48.939351 WR_PST = 0x0
673 10:01:48.942335 DBI_WR = 0x0
674 10:01:48.942422 DBI_RD = 0x0
675 10:01:48.945791 OTF = 0x1
676 10:01:48.948947 ===================================
677 10:01:48.952206 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 10:01:48.955692 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 10:01:48.962211 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 10:01:48.966041 ===================================
681 10:01:48.966132 LPDDR4 DRAM CONFIGURATION
682 10:01:48.968739 ===================================
683 10:01:48.972235 EX_ROW_EN[0] = 0x10
684 10:01:48.975973 EX_ROW_EN[1] = 0x0
685 10:01:48.976076 LP4Y_EN = 0x0
686 10:01:48.978936 WORK_FSP = 0x0
687 10:01:48.979036 WL = 0x2
688 10:01:48.982076 RL = 0x2
689 10:01:48.982191 BL = 0x2
690 10:01:48.985935 RPST = 0x0
691 10:01:48.986050 RD_PRE = 0x0
692 10:01:48.988569 WR_PRE = 0x1
693 10:01:48.988659 WR_PST = 0x0
694 10:01:48.991724 DBI_WR = 0x0
695 10:01:48.991808 DBI_RD = 0x0
696 10:01:48.995268 OTF = 0x1
697 10:01:48.999200 ===================================
698 10:01:49.005138 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 10:01:49.009029 nWR fixed to 40
700 10:01:49.012107 [ModeRegInit_LP4] CH0 RK0
701 10:01:49.012214 [ModeRegInit_LP4] CH0 RK1
702 10:01:49.015549 [ModeRegInit_LP4] CH1 RK0
703 10:01:49.018604 [ModeRegInit_LP4] CH1 RK1
704 10:01:49.018713 match AC timing 13
705 10:01:49.025904 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 10:01:49.026016 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 10:01:49.031894 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 10:01:49.035922 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 10:01:49.039455 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 10:01:49.043125 [EMI DOE] emi_dcm 0
711 10:01:49.046787 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 10:01:49.046928 ==
713 10:01:49.050542 Dram Type= 6, Freq= 0, CH_0, rank 0
714 10:01:49.054051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 10:01:49.054143 ==
716 10:01:49.061023 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 10:01:49.068334 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 10:01:49.076133 [CA 0] Center 38 (7~69) winsize 63
719 10:01:49.079519 [CA 1] Center 37 (7~68) winsize 62
720 10:01:49.083187 [CA 2] Center 35 (5~66) winsize 62
721 10:01:49.086725 [CA 3] Center 35 (5~66) winsize 62
722 10:01:49.090186 [CA 4] Center 34 (4~65) winsize 62
723 10:01:49.093862 [CA 5] Center 33 (3~64) winsize 62
724 10:01:49.094000
725 10:01:49.097271 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 10:01:49.097351
727 10:01:49.101187 [CATrainingPosCal] consider 1 rank data
728 10:01:49.104699 u2DelayCellTimex100 = 270/100 ps
729 10:01:49.108885 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
730 10:01:49.112361 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
731 10:01:49.115378 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
732 10:01:49.119021 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
733 10:01:49.122476 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
734 10:01:49.125886 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 10:01:49.125973
736 10:01:49.130078 CA PerBit enable=1, Macro0, CA PI delay=33
737 10:01:49.130170
738 10:01:49.132970 [CBTSetCACLKResult] CA Dly = 33
739 10:01:49.133047 CS Dly: 6 (0~37)
740 10:01:49.133111 ==
741 10:01:49.136413 Dram Type= 6, Freq= 0, CH_0, rank 1
742 10:01:49.140138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 10:01:49.140230 ==
744 10:01:49.147687 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 10:01:49.154363 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 10:01:49.162241 [CA 0] Center 38 (7~69) winsize 63
747 10:01:49.166048 [CA 1] Center 38 (7~69) winsize 63
748 10:01:49.169423 [CA 2] Center 35 (5~66) winsize 62
749 10:01:49.173656 [CA 3] Center 35 (5~66) winsize 62
750 10:01:49.176977 [CA 4] Center 34 (4~65) winsize 62
751 10:01:49.180876 [CA 5] Center 34 (4~65) winsize 62
752 10:01:49.180965
753 10:01:49.184444 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 10:01:49.184532
755 10:01:49.188010 [CATrainingPosCal] consider 2 rank data
756 10:01:49.191920 u2DelayCellTimex100 = 270/100 ps
757 10:01:49.192001 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
758 10:01:49.199314 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
759 10:01:49.199421 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
760 10:01:49.202822 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
761 10:01:49.206383 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
762 10:01:49.209968 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
763 10:01:49.210071
764 10:01:49.214094 CA PerBit enable=1, Macro0, CA PI delay=34
765 10:01:49.217752
766 10:01:49.217861 [CBTSetCACLKResult] CA Dly = 34
767 10:01:49.221372 CS Dly: 6 (0~37)
768 10:01:49.221450
769 10:01:49.224776 ----->DramcWriteLeveling(PI) begin...
770 10:01:49.224883 ==
771 10:01:49.228579 Dram Type= 6, Freq= 0, CH_0, rank 0
772 10:01:49.232378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 10:01:49.232464 ==
774 10:01:49.235974 Write leveling (Byte 0): 34 => 34
775 10:01:49.239828 Write leveling (Byte 1): 30 => 30
776 10:01:49.239930 DramcWriteLeveling(PI) end<-----
777 10:01:49.240007
778 10:01:49.240068 ==
779 10:01:49.243253 Dram Type= 6, Freq= 0, CH_0, rank 0
780 10:01:49.247036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 10:01:49.250997 ==
782 10:01:49.251123 [Gating] SW mode calibration
783 10:01:49.258404 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 10:01:49.265974 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 10:01:49.269066 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 10:01:49.272697 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 10:01:49.276154 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 10:01:49.279946 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 10:01:49.287436 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 10:01:49.290882 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 10:01:49.294637 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 10:01:49.297850 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 10:01:49.301847 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 10:01:49.309084 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 10:01:49.312751 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 10:01:49.316405 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 10:01:49.320531 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 10:01:49.323692 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 10:01:49.331201 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 10:01:49.334592 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 10:01:49.338579 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 10:01:49.342211 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 10:01:49.346295 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 10:01:49.352527 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 10:01:49.355790 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 10:01:49.359210 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 10:01:49.366076 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 10:01:49.369635 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 10:01:49.372764 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 10:01:49.379163 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 10:01:49.382428 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 10:01:49.385633 0 9 12 | B1->B0 | 2a2a 3333 | 1 1 | (1 1) (1 1)
813 10:01:49.392394 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 10:01:49.395542 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 10:01:49.398949 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 10:01:49.406093 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 10:01:49.408744 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 10:01:49.412052 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
819 10:01:49.418868 0 10 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
820 10:01:49.421960 0 10 12 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
821 10:01:49.425612 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 10:01:49.432330 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 10:01:49.435671 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 10:01:49.438807 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 10:01:49.445404 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 10:01:49.448597 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 10:01:49.452318 0 11 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
828 10:01:49.458897 0 11 12 | B1->B0 | 3737 4141 | 0 0 | (0 0) (0 0)
829 10:01:49.461811 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 10:01:49.465132 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 10:01:49.468514 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 10:01:49.475355 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 10:01:49.478362 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 10:01:49.482164 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 10:01:49.488402 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 10:01:49.491879 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 10:01:49.494918 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 10:01:49.501776 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 10:01:49.505027 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 10:01:49.508475 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 10:01:49.515006 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 10:01:49.518439 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 10:01:49.521777 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 10:01:49.528091 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 10:01:49.531671 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 10:01:49.535155 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 10:01:49.541377 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 10:01:49.545060 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 10:01:49.548481 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 10:01:49.554797 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 10:01:49.558408 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 10:01:49.561477 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 10:01:49.565025 Total UI for P1: 0, mck2ui 16
854 10:01:49.568260 best dqsien dly found for B0: ( 0, 14, 8)
855 10:01:49.571294 Total UI for P1: 0, mck2ui 16
856 10:01:49.574764 best dqsien dly found for B1: ( 0, 14, 10)
857 10:01:49.578598 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
858 10:01:49.581796 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
859 10:01:49.581908
860 10:01:49.585033 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
861 10:01:49.591464 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 10:01:49.591545 [Gating] SW calibration Done
863 10:01:49.594769 ==
864 10:01:49.594887 Dram Type= 6, Freq= 0, CH_0, rank 0
865 10:01:49.601459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 10:01:49.601550 ==
867 10:01:49.601618 RX Vref Scan: 0
868 10:01:49.601682
869 10:01:49.604597 RX Vref 0 -> 0, step: 1
870 10:01:49.604671
871 10:01:49.607906 RX Delay -130 -> 252, step: 16
872 10:01:49.611382 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
873 10:01:49.614410 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
874 10:01:49.617911 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
875 10:01:49.624457 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
876 10:01:49.627748 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
877 10:01:49.631398 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
878 10:01:49.634453 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
879 10:01:49.637643 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
880 10:01:49.644540 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
881 10:01:49.647656 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
882 10:01:49.651486 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
883 10:01:49.654576 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
884 10:01:49.657819 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
885 10:01:49.664607 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
886 10:01:49.667539 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
887 10:01:49.670786 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
888 10:01:49.670901 ==
889 10:01:49.674314 Dram Type= 6, Freq= 0, CH_0, rank 0
890 10:01:49.677851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 10:01:49.681246 ==
892 10:01:49.681332 DQS Delay:
893 10:01:49.681401 DQS0 = 0, DQS1 = 0
894 10:01:49.684322 DQM Delay:
895 10:01:49.684408 DQM0 = 79, DQM1 = 69
896 10:01:49.687654 DQ Delay:
897 10:01:49.687739 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =77
898 10:01:49.691084 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
899 10:01:49.694002 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
900 10:01:49.697473 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
901 10:01:49.697560
902 10:01:49.700864
903 10:01:49.700949 ==
904 10:01:49.704116 Dram Type= 6, Freq= 0, CH_0, rank 0
905 10:01:49.708027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 10:01:49.708114 ==
907 10:01:49.708183
908 10:01:49.708247
909 10:01:49.711784 TX Vref Scan disable
910 10:01:49.711871 == TX Byte 0 ==
911 10:01:49.715051 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
912 10:01:49.721858 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
913 10:01:49.721946 == TX Byte 1 ==
914 10:01:49.724956 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
915 10:01:49.731877 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
916 10:01:49.731965 ==
917 10:01:49.735154 Dram Type= 6, Freq= 0, CH_0, rank 0
918 10:01:49.738462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 10:01:49.738548 ==
920 10:01:49.751876 TX Vref=22, minBit 7, minWin=26, winSum=435
921 10:01:49.754586 TX Vref=24, minBit 14, minWin=26, winSum=438
922 10:01:49.758129 TX Vref=26, minBit 5, minWin=27, winSum=440
923 10:01:49.761769 TX Vref=28, minBit 5, minWin=27, winSum=441
924 10:01:49.764923 TX Vref=30, minBit 4, minWin=27, winSum=441
925 10:01:49.768321 TX Vref=32, minBit 4, minWin=27, winSum=441
926 10:01:49.775117 [TxChooseVref] Worse bit 5, Min win 27, Win sum 441, Final Vref 28
927 10:01:49.775204
928 10:01:49.778487 Final TX Range 1 Vref 28
929 10:01:49.778574
930 10:01:49.778643 ==
931 10:01:49.781610 Dram Type= 6, Freq= 0, CH_0, rank 0
932 10:01:49.784690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 10:01:49.784778 ==
934 10:01:49.784846
935 10:01:49.788070
936 10:01:49.788156 TX Vref Scan disable
937 10:01:49.791396 == TX Byte 0 ==
938 10:01:49.795032 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
939 10:01:49.801155 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
940 10:01:49.801241 == TX Byte 1 ==
941 10:01:49.804668 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
942 10:01:49.811402 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
943 10:01:49.811489
944 10:01:49.811558 [DATLAT]
945 10:01:49.811620 Freq=800, CH0 RK0
946 10:01:49.811682
947 10:01:49.814680 DATLAT Default: 0xa
948 10:01:49.814765 0, 0xFFFF, sum = 0
949 10:01:49.817817 1, 0xFFFF, sum = 0
950 10:01:49.817904 2, 0xFFFF, sum = 0
951 10:01:49.821419 3, 0xFFFF, sum = 0
952 10:01:49.824692 4, 0xFFFF, sum = 0
953 10:01:49.824780 5, 0xFFFF, sum = 0
954 10:01:49.828175 6, 0xFFFF, sum = 0
955 10:01:49.828263 7, 0xFFFF, sum = 0
956 10:01:49.831261 8, 0xFFFF, sum = 0
957 10:01:49.831347 9, 0x0, sum = 1
958 10:01:49.834642 10, 0x0, sum = 2
959 10:01:49.834728 11, 0x0, sum = 3
960 10:01:49.834798 12, 0x0, sum = 4
961 10:01:49.838209 best_step = 10
962 10:01:49.838294
963 10:01:49.838362 ==
964 10:01:49.841189 Dram Type= 6, Freq= 0, CH_0, rank 0
965 10:01:49.844347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 10:01:49.844433 ==
967 10:01:49.847892 RX Vref Scan: 1
968 10:01:49.847977
969 10:01:49.850877 Set Vref Range= 32 -> 127
970 10:01:49.850962
971 10:01:49.851030 RX Vref 32 -> 127, step: 1
972 10:01:49.851094
973 10:01:49.854553 RX Delay -111 -> 252, step: 8
974 10:01:49.854637
975 10:01:49.857784 Set Vref, RX VrefLevel [Byte0]: 32
976 10:01:49.860921 [Byte1]: 32
977 10:01:49.864118
978 10:01:49.864204 Set Vref, RX VrefLevel [Byte0]: 33
979 10:01:49.867789 [Byte1]: 33
980 10:01:49.871893
981 10:01:49.871977 Set Vref, RX VrefLevel [Byte0]: 34
982 10:01:49.875466 [Byte1]: 34
983 10:01:49.879841
984 10:01:49.879926 Set Vref, RX VrefLevel [Byte0]: 35
985 10:01:49.882832 [Byte1]: 35
986 10:01:49.887682
987 10:01:49.887768 Set Vref, RX VrefLevel [Byte0]: 36
988 10:01:49.890558 [Byte1]: 36
989 10:01:49.894767
990 10:01:49.894887 Set Vref, RX VrefLevel [Byte0]: 37
991 10:01:49.898167 [Byte1]: 37
992 10:01:49.902523
993 10:01:49.902612 Set Vref, RX VrefLevel [Byte0]: 38
994 10:01:49.906055 [Byte1]: 38
995 10:01:49.909881
996 10:01:49.909969 Set Vref, RX VrefLevel [Byte0]: 39
997 10:01:49.913745 [Byte1]: 39
998 10:01:49.918011
999 10:01:49.918102 Set Vref, RX VrefLevel [Byte0]: 40
1000 10:01:49.921077 [Byte1]: 40
1001 10:01:49.925241
1002 10:01:49.925323 Set Vref, RX VrefLevel [Byte0]: 41
1003 10:01:49.928522 [Byte1]: 41
1004 10:01:49.933156
1005 10:01:49.933246 Set Vref, RX VrefLevel [Byte0]: 42
1006 10:01:49.936309 [Byte1]: 42
1007 10:01:49.940809
1008 10:01:49.940888 Set Vref, RX VrefLevel [Byte0]: 43
1009 10:01:49.943842 [Byte1]: 43
1010 10:01:49.948624
1011 10:01:49.948705 Set Vref, RX VrefLevel [Byte0]: 44
1012 10:01:49.951673 [Byte1]: 44
1013 10:01:49.955763
1014 10:01:49.959470 Set Vref, RX VrefLevel [Byte0]: 45
1015 10:01:49.962849 [Byte1]: 45
1016 10:01:49.962929
1017 10:01:49.966480 Set Vref, RX VrefLevel [Byte0]: 46
1018 10:01:49.969851 [Byte1]: 46
1019 10:01:49.969934
1020 10:01:49.973512 Set Vref, RX VrefLevel [Byte0]: 47
1021 10:01:49.977118 [Byte1]: 47
1022 10:01:49.977207
1023 10:01:49.981130 Set Vref, RX VrefLevel [Byte0]: 48
1024 10:01:49.984503 [Byte1]: 48
1025 10:01:49.984594
1026 10:01:49.988574 Set Vref, RX VrefLevel [Byte0]: 49
1027 10:01:49.992113 [Byte1]: 49
1028 10:01:49.992198
1029 10:01:49.995276 Set Vref, RX VrefLevel [Byte0]: 50
1030 10:01:49.998880 [Byte1]: 50
1031 10:01:50.002188
1032 10:01:50.002341 Set Vref, RX VrefLevel [Byte0]: 51
1033 10:01:50.005648 [Byte1]: 51
1034 10:01:50.009480
1035 10:01:50.009557 Set Vref, RX VrefLevel [Byte0]: 52
1036 10:01:50.013024 [Byte1]: 52
1037 10:01:50.017312
1038 10:01:50.017388 Set Vref, RX VrefLevel [Byte0]: 53
1039 10:01:50.020440 [Byte1]: 53
1040 10:01:50.024870
1041 10:01:50.024951 Set Vref, RX VrefLevel [Byte0]: 54
1042 10:01:50.028327 [Byte1]: 54
1043 10:01:50.032389
1044 10:01:50.032466 Set Vref, RX VrefLevel [Byte0]: 55
1045 10:01:50.036020 [Byte1]: 55
1046 10:01:50.040113
1047 10:01:50.040219 Set Vref, RX VrefLevel [Byte0]: 56
1048 10:01:50.043791 [Byte1]: 56
1049 10:01:50.047978
1050 10:01:50.048057 Set Vref, RX VrefLevel [Byte0]: 57
1051 10:01:50.051148 [Byte1]: 57
1052 10:01:50.055152
1053 10:01:50.059108 Set Vref, RX VrefLevel [Byte0]: 58
1054 10:01:50.062260 [Byte1]: 58
1055 10:01:50.062338
1056 10:01:50.065068 Set Vref, RX VrefLevel [Byte0]: 59
1057 10:01:50.068726 [Byte1]: 59
1058 10:01:50.068807
1059 10:01:50.072277 Set Vref, RX VrefLevel [Byte0]: 60
1060 10:01:50.075462 [Byte1]: 60
1061 10:01:50.075542
1062 10:01:50.078536 Set Vref, RX VrefLevel [Byte0]: 61
1063 10:01:50.081631 [Byte1]: 61
1064 10:01:50.085808
1065 10:01:50.085880 Set Vref, RX VrefLevel [Byte0]: 62
1066 10:01:50.089149 [Byte1]: 62
1067 10:01:50.093542
1068 10:01:50.093618 Set Vref, RX VrefLevel [Byte0]: 63
1069 10:01:50.096948 [Byte1]: 63
1070 10:01:50.101114
1071 10:01:50.101189 Set Vref, RX VrefLevel [Byte0]: 64
1072 10:01:50.104463 [Byte1]: 64
1073 10:01:50.109464
1074 10:01:50.109548 Set Vref, RX VrefLevel [Byte0]: 65
1075 10:01:50.112340 [Byte1]: 65
1076 10:01:50.116599
1077 10:01:50.116683 Set Vref, RX VrefLevel [Byte0]: 66
1078 10:01:50.120246 [Byte1]: 66
1079 10:01:50.124271
1080 10:01:50.124412 Set Vref, RX VrefLevel [Byte0]: 67
1081 10:01:50.127679 [Byte1]: 67
1082 10:01:50.131671
1083 10:01:50.131766 Set Vref, RX VrefLevel [Byte0]: 68
1084 10:01:50.135111 [Byte1]: 68
1085 10:01:50.139694
1086 10:01:50.139800 Set Vref, RX VrefLevel [Byte0]: 69
1087 10:01:50.142718 [Byte1]: 69
1088 10:01:50.147143
1089 10:01:50.147228 Set Vref, RX VrefLevel [Byte0]: 70
1090 10:01:50.150309 [Byte1]: 70
1091 10:01:50.154785
1092 10:01:50.157760 Set Vref, RX VrefLevel [Byte0]: 71
1093 10:01:50.161318 [Byte1]: 71
1094 10:01:50.161403
1095 10:01:50.164512 Set Vref, RX VrefLevel [Byte0]: 72
1096 10:01:50.167983 [Byte1]: 72
1097 10:01:50.168068
1098 10:01:50.171084 Set Vref, RX VrefLevel [Byte0]: 73
1099 10:01:50.174382 [Byte1]: 73
1100 10:01:50.178348
1101 10:01:50.178432 Set Vref, RX VrefLevel [Byte0]: 74
1102 10:01:50.181215 [Byte1]: 74
1103 10:01:50.185244
1104 10:01:50.185328 Set Vref, RX VrefLevel [Byte0]: 75
1105 10:01:50.192095 [Byte1]: 75
1106 10:01:50.192180
1107 10:01:50.195179 Set Vref, RX VrefLevel [Byte0]: 76
1108 10:01:50.198369 [Byte1]: 76
1109 10:01:50.198454
1110 10:01:50.201997 Set Vref, RX VrefLevel [Byte0]: 77
1111 10:01:50.204823 [Byte1]: 77
1112 10:01:50.208425
1113 10:01:50.208541 Set Vref, RX VrefLevel [Byte0]: 78
1114 10:01:50.211896 [Byte1]: 78
1115 10:01:50.215670
1116 10:01:50.215755 Set Vref, RX VrefLevel [Byte0]: 79
1117 10:01:50.219209 [Byte1]: 79
1118 10:01:50.223464
1119 10:01:50.223549 Set Vref, RX VrefLevel [Byte0]: 80
1120 10:01:50.226954 [Byte1]: 80
1121 10:01:50.231243
1122 10:01:50.231328 Set Vref, RX VrefLevel [Byte0]: 81
1123 10:01:50.234648 [Byte1]: 81
1124 10:01:50.238992
1125 10:01:50.239077 Final RX Vref Byte 0 = 55 to rank0
1126 10:01:50.242229 Final RX Vref Byte 1 = 59 to rank0
1127 10:01:50.245615 Final RX Vref Byte 0 = 55 to rank1
1128 10:01:50.248821 Final RX Vref Byte 1 = 59 to rank1==
1129 10:01:50.252451 Dram Type= 6, Freq= 0, CH_0, rank 0
1130 10:01:50.258981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1131 10:01:50.259067 ==
1132 10:01:50.259135 DQS Delay:
1133 10:01:50.259198 DQS0 = 0, DQS1 = 0
1134 10:01:50.262300 DQM Delay:
1135 10:01:50.262384 DQM0 = 82, DQM1 = 67
1136 10:01:50.265367 DQ Delay:
1137 10:01:50.268978 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1138 10:01:50.272043 DQ4 =84, DQ5 =68, DQ6 =92, DQ7 =92
1139 10:01:50.275299 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1140 10:01:50.279112 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1141 10:01:50.279197
1142 10:01:50.279265
1143 10:01:50.285265 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1144 10:01:50.289044 CH0 RK0: MR19=606, MR18=2424
1145 10:01:50.295503 CH0_RK0: MR19=0x606, MR18=0x2424, DQSOSC=400, MR23=63, INC=92, DEC=61
1146 10:01:50.295590
1147 10:01:50.298789 ----->DramcWriteLeveling(PI) begin...
1148 10:01:50.298912 ==
1149 10:01:50.302243 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 10:01:50.305424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 10:01:50.305513 ==
1152 10:01:50.308797 Write leveling (Byte 0): 30 => 30
1153 10:01:50.311997 Write leveling (Byte 1): 28 => 28
1154 10:01:50.315534 DramcWriteLeveling(PI) end<-----
1155 10:01:50.315635
1156 10:01:50.315734 ==
1157 10:01:50.318452 Dram Type= 6, Freq= 0, CH_0, rank 1
1158 10:01:50.321781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1159 10:01:50.321867 ==
1160 10:01:50.325240 [Gating] SW mode calibration
1161 10:01:50.332298 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1162 10:01:50.338884 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1163 10:01:50.342066 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1164 10:01:50.345114 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1165 10:01:50.352012 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1166 10:01:50.355136 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 10:01:50.358722 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 10:01:50.365262 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 10:01:50.368790 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 10:01:50.372024 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 10:01:50.378303 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 10:01:50.381799 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 10:01:50.385186 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 10:01:50.429071 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 10:01:50.429404 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 10:01:50.429525 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 10:01:50.429804 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 10:01:50.429918 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 10:01:50.430071 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 10:01:50.430163 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 10:01:50.430511 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1182 10:01:50.430778 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 10:01:50.430888 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 10:01:50.443635 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 10:01:50.444063 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 10:01:50.446980 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 10:01:50.450806 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 10:01:50.453444 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 10:01:50.456897 0 9 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1190 10:01:50.460085 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1191 10:01:50.466522 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 10:01:50.470212 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 10:01:50.473560 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 10:01:50.480269 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 10:01:50.483433 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 10:01:50.486489 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1197 10:01:50.493341 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (1 1) (1 0)
1198 10:01:50.496293 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
1199 10:01:50.499854 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 10:01:50.506478 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 10:01:50.509818 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 10:01:50.513332 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 10:01:50.516271 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 10:01:50.522820 0 11 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1205 10:01:50.526496 0 11 8 | B1->B0 | 2f2f 3b3b | 0 0 | (0 0) (0 0)
1206 10:01:50.529602 0 11 12 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
1207 10:01:50.536275 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 10:01:50.540048 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 10:01:50.543751 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 10:01:50.547339 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 10:01:50.554373 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 10:01:50.557826 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1213 10:01:50.561305 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1214 10:01:50.567951 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 10:01:50.571466 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 10:01:50.574736 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 10:01:50.578701 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 10:01:50.585224 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 10:01:50.588330 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 10:01:50.591363 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 10:01:50.597966 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 10:01:50.601429 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 10:01:50.605025 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 10:01:50.611428 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 10:01:50.614603 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 10:01:50.618231 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 10:01:50.624511 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 10:01:50.628214 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 10:01:50.631433 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1230 10:01:50.637862 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1231 10:01:50.637968 Total UI for P1: 0, mck2ui 16
1232 10:01:50.644498 best dqsien dly found for B0: ( 0, 14, 8)
1233 10:01:50.644586 Total UI for P1: 0, mck2ui 16
1234 10:01:50.648263 best dqsien dly found for B1: ( 0, 14, 8)
1235 10:01:50.654441 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1236 10:01:50.658294 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1237 10:01:50.658377
1238 10:01:50.660890 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1239 10:01:50.664361 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1240 10:01:50.667737 [Gating] SW calibration Done
1241 10:01:50.667818 ==
1242 10:01:50.671028 Dram Type= 6, Freq= 0, CH_0, rank 1
1243 10:01:50.674488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1244 10:01:50.674566 ==
1245 10:01:50.677741 RX Vref Scan: 0
1246 10:01:50.677818
1247 10:01:50.677882 RX Vref 0 -> 0, step: 1
1248 10:01:50.677943
1249 10:01:50.680800 RX Delay -130 -> 252, step: 16
1250 10:01:50.684506 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1251 10:01:50.690883 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1252 10:01:50.694322 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1253 10:01:50.697611 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1254 10:01:50.701078 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1255 10:01:50.704206 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1256 10:01:50.710879 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1257 10:01:50.714209 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1258 10:01:50.717477 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1259 10:01:50.720925 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1260 10:01:50.724249 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1261 10:01:50.730890 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1262 10:01:50.733702 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1263 10:01:50.736989 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1264 10:01:50.740241 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1265 10:01:50.746878 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1266 10:01:50.746977 ==
1267 10:01:50.750652 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 10:01:50.753832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 10:01:50.753914 ==
1270 10:01:50.753979 DQS Delay:
1271 10:01:50.757108 DQS0 = 0, DQS1 = 0
1272 10:01:50.757183 DQM Delay:
1273 10:01:50.760522 DQM0 = 75, DQM1 = 69
1274 10:01:50.760598 DQ Delay:
1275 10:01:50.763907 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1276 10:01:50.766943 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1277 10:01:50.770316 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1278 10:01:50.773680 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1279 10:01:50.773763
1280 10:01:50.773830
1281 10:01:50.773893 ==
1282 10:01:50.777038 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 10:01:50.780010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 10:01:50.780101 ==
1285 10:01:50.780170
1286 10:01:50.780232
1287 10:01:50.783762 TX Vref Scan disable
1288 10:01:50.786973 == TX Byte 0 ==
1289 10:01:50.790467 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1290 10:01:50.793514 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1291 10:01:50.796901 == TX Byte 1 ==
1292 10:01:50.799973 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1293 10:01:50.803358 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1294 10:01:50.803444 ==
1295 10:01:50.806933 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 10:01:50.813310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 10:01:50.813397 ==
1298 10:01:50.825343 TX Vref=22, minBit 2, minWin=26, winSum=437
1299 10:01:50.828421 TX Vref=24, minBit 1, minWin=27, winSum=442
1300 10:01:50.831507 TX Vref=26, minBit 1, minWin=27, winSum=441
1301 10:01:50.835396 TX Vref=28, minBit 1, minWin=27, winSum=443
1302 10:01:50.838193 TX Vref=30, minBit 1, minWin=27, winSum=449
1303 10:01:50.844885 TX Vref=32, minBit 1, minWin=27, winSum=444
1304 10:01:50.848140 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 30
1305 10:01:50.848229
1306 10:01:50.851509 Final TX Range 1 Vref 30
1307 10:01:50.851597
1308 10:01:50.851664 ==
1309 10:01:50.854807 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 10:01:50.858201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 10:01:50.861111 ==
1312 10:01:50.861195
1313 10:01:50.861261
1314 10:01:50.861322 TX Vref Scan disable
1315 10:01:50.865032 == TX Byte 0 ==
1316 10:01:50.868574 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1317 10:01:50.875002 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1318 10:01:50.875092 == TX Byte 1 ==
1319 10:01:50.878365 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1320 10:01:50.885157 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1321 10:01:50.885260
1322 10:01:50.885387 [DATLAT]
1323 10:01:50.885464 Freq=800, CH0 RK1
1324 10:01:50.885523
1325 10:01:50.888410 DATLAT Default: 0xa
1326 10:01:50.888494 0, 0xFFFF, sum = 0
1327 10:01:50.891493 1, 0xFFFF, sum = 0
1328 10:01:50.891577 2, 0xFFFF, sum = 0
1329 10:01:50.894922 3, 0xFFFF, sum = 0
1330 10:01:50.898657 4, 0xFFFF, sum = 0
1331 10:01:50.898741 5, 0xFFFF, sum = 0
1332 10:01:50.901312 6, 0xFFFF, sum = 0
1333 10:01:50.901396 7, 0xFFFF, sum = 0
1334 10:01:50.904763 8, 0xFFFF, sum = 0
1335 10:01:50.904846 9, 0x0, sum = 1
1336 10:01:50.908430 10, 0x0, sum = 2
1337 10:01:50.908514 11, 0x0, sum = 3
1338 10:01:50.908581 12, 0x0, sum = 4
1339 10:01:50.911428 best_step = 10
1340 10:01:50.911541
1341 10:01:50.911634 ==
1342 10:01:50.914684 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 10:01:50.918219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 10:01:50.918302 ==
1345 10:01:50.921342 RX Vref Scan: 0
1346 10:01:50.921424
1347 10:01:50.921491 RX Vref 0 -> 0, step: 1
1348 10:01:50.924523
1349 10:01:50.924606 RX Delay -111 -> 252, step: 8
1350 10:01:50.931906 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1351 10:01:50.935299 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1352 10:01:50.938163 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1353 10:01:50.941767 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
1354 10:01:50.944950 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1355 10:01:50.951736 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1356 10:01:50.954854 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1357 10:01:50.958386 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1358 10:01:50.961409 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1359 10:01:50.968009 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1360 10:01:50.971460 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1361 10:01:50.974570 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1362 10:01:50.978319 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1363 10:01:50.981506 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1364 10:01:50.988208 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1365 10:01:50.991380 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1366 10:01:50.991526 ==
1367 10:01:50.994979 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 10:01:50.997661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 10:01:50.997749 ==
1370 10:01:51.000994 DQS Delay:
1371 10:01:51.001078 DQS0 = 0, DQS1 = 0
1372 10:01:51.001145 DQM Delay:
1373 10:01:51.004703 DQM0 = 79, DQM1 = 71
1374 10:01:51.004786 DQ Delay:
1375 10:01:51.007857 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =76
1376 10:01:51.011378 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =88
1377 10:01:51.014127 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1378 10:01:51.017765 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1379 10:01:51.017849
1380 10:01:51.017915
1381 10:01:51.027477 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
1382 10:01:51.031149 CH0 RK1: MR19=606, MR18=4C27
1383 10:01:51.034300 CH0_RK1: MR19=0x606, MR18=0x4C27, DQSOSC=390, MR23=63, INC=97, DEC=64
1384 10:01:51.037389 [RxdqsGatingPostProcess] freq 800
1385 10:01:51.043835 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1386 10:01:51.047356 Pre-setting of DQS Precalculation
1387 10:01:51.050536 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1388 10:01:51.050620 ==
1389 10:01:51.054038 Dram Type= 6, Freq= 0, CH_1, rank 0
1390 10:01:51.060411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1391 10:01:51.060496 ==
1392 10:01:51.063891 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1393 10:01:51.070219 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1394 10:01:51.080113 [CA 0] Center 37 (7~67) winsize 61
1395 10:01:51.083273 [CA 1] Center 37 (7~67) winsize 61
1396 10:01:51.087106 [CA 2] Center 34 (5~64) winsize 60
1397 10:01:51.090014 [CA 3] Center 34 (4~64) winsize 61
1398 10:01:51.093698 [CA 4] Center 34 (4~64) winsize 61
1399 10:01:51.096622 [CA 5] Center 34 (4~64) winsize 61
1400 10:01:51.096706
1401 10:01:51.099865 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1402 10:01:51.099951
1403 10:01:51.103374 [CATrainingPosCal] consider 1 rank data
1404 10:01:51.106718 u2DelayCellTimex100 = 270/100 ps
1405 10:01:51.110146 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1406 10:01:51.116853 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1407 10:01:51.119783 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1408 10:01:51.123434 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1409 10:01:51.126591 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1410 10:01:51.129708 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1411 10:01:51.129795
1412 10:01:51.133382 CA PerBit enable=1, Macro0, CA PI delay=34
1413 10:01:51.133470
1414 10:01:51.136716 [CBTSetCACLKResult] CA Dly = 34
1415 10:01:51.136804 CS Dly: 5 (0~36)
1416 10:01:51.139839 ==
1417 10:01:51.142879 Dram Type= 6, Freq= 0, CH_1, rank 1
1418 10:01:51.146575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 10:01:51.146663 ==
1420 10:01:51.152873 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1421 10:01:51.156198 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1422 10:01:51.166635 [CA 0] Center 37 (7~67) winsize 61
1423 10:01:51.169709 [CA 1] Center 36 (6~67) winsize 62
1424 10:01:51.172769 [CA 2] Center 34 (4~65) winsize 62
1425 10:01:51.175937 [CA 3] Center 33 (3~64) winsize 62
1426 10:01:51.179543 [CA 4] Center 34 (4~65) winsize 62
1427 10:01:51.182845 [CA 5] Center 33 (3~64) winsize 62
1428 10:01:51.182946
1429 10:01:51.185867 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1430 10:01:51.185954
1431 10:01:51.189377 [CATrainingPosCal] consider 2 rank data
1432 10:01:51.192763 u2DelayCellTimex100 = 270/100 ps
1433 10:01:51.195760 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1434 10:01:51.203141 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1435 10:01:51.206230 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1436 10:01:51.209713 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1437 10:01:51.213503 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1438 10:01:51.217586 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1439 10:01:51.217676
1440 10:01:51.221243 CA PerBit enable=1, Macro0, CA PI delay=34
1441 10:01:51.221332
1442 10:01:51.221420 [CBTSetCACLKResult] CA Dly = 34
1443 10:01:51.224896 CS Dly: 6 (0~38)
1444 10:01:51.224983
1445 10:01:51.228035 ----->DramcWriteLeveling(PI) begin...
1446 10:01:51.228124 ==
1447 10:01:51.231740 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 10:01:51.235429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 10:01:51.235517 ==
1450 10:01:51.238943 Write leveling (Byte 0): 28 => 28
1451 10:01:51.242201 Write leveling (Byte 1): 28 => 28
1452 10:01:51.245806 DramcWriteLeveling(PI) end<-----
1453 10:01:51.245897
1454 10:01:51.246003 ==
1455 10:01:51.249233 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 10:01:51.252041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 10:01:51.252129 ==
1458 10:01:51.255197 [Gating] SW mode calibration
1459 10:01:51.262482 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1460 10:01:51.269356 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1461 10:01:51.272291 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1462 10:01:51.275434 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1463 10:01:51.282242 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 10:01:51.285462 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 10:01:51.289095 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 10:01:51.295585 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 10:01:51.298868 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 10:01:51.302420 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 10:01:51.308709 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 10:01:51.312348 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 10:01:51.315117 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 10:01:51.321743 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 10:01:51.325325 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 10:01:51.328813 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 10:01:51.335220 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 10:01:51.338289 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 10:01:51.341730 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 10:01:51.348010 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 10:01:51.351318 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1480 10:01:51.354948 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 10:01:51.362152 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 10:01:51.364836 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 10:01:51.368438 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 10:01:51.374454 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 10:01:51.377851 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 10:01:51.381093 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 10:01:51.387933 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1488 10:01:51.391015 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 10:01:51.394622 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 10:01:51.397593 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 10:01:51.404415 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 10:01:51.407562 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 10:01:51.411318 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 10:01:51.417839 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
1495 10:01:51.421128 0 10 8 | B1->B0 | 2f2f 2a2a | 0 1 | (0 0) (1 0)
1496 10:01:51.424137 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 10:01:51.430674 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 10:01:51.434535 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 10:01:51.437333 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 10:01:51.444431 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 10:01:51.447348 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 10:01:51.450630 0 11 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
1503 10:01:51.457451 0 11 8 | B1->B0 | 3939 3737 | 1 1 | (0 0) (0 0)
1504 10:01:51.460562 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 10:01:51.464348 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 10:01:51.470643 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 10:01:51.473640 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 10:01:51.477443 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 10:01:51.483735 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 10:01:51.487203 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 10:01:51.490477 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1512 10:01:51.497490 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 10:01:51.500229 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 10:01:51.503887 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 10:01:51.510177 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 10:01:51.513811 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 10:01:51.516901 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 10:01:51.523434 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 10:01:51.526652 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 10:01:51.530107 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 10:01:51.536736 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 10:01:51.540157 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 10:01:51.543568 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 10:01:51.550311 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 10:01:51.553374 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 10:01:51.556593 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 10:01:51.563337 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1528 10:01:51.567067 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1529 10:01:51.570157 Total UI for P1: 0, mck2ui 16
1530 10:01:51.573765 best dqsien dly found for B0: ( 0, 14, 8)
1531 10:01:51.576804 Total UI for P1: 0, mck2ui 16
1532 10:01:51.580014 best dqsien dly found for B1: ( 0, 14, 8)
1533 10:01:51.583232 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1534 10:01:51.586662 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1535 10:01:51.586811
1536 10:01:51.589567 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1537 10:01:51.592948 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1538 10:01:51.596458 [Gating] SW calibration Done
1539 10:01:51.596583 ==
1540 10:01:51.599716 Dram Type= 6, Freq= 0, CH_1, rank 0
1541 10:01:51.602958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1542 10:01:51.603049 ==
1543 10:01:51.606429 RX Vref Scan: 0
1544 10:01:51.606538
1545 10:01:51.609646 RX Vref 0 -> 0, step: 1
1546 10:01:51.609758
1547 10:01:51.609859 RX Delay -130 -> 252, step: 16
1548 10:01:51.616444 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1549 10:01:51.619880 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1550 10:01:51.623178 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1551 10:01:51.626449 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1552 10:01:51.629542 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1553 10:01:51.636398 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1554 10:01:51.639378 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1555 10:01:51.642733 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1556 10:01:51.646440 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1557 10:01:51.649395 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1558 10:01:51.655971 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1559 10:01:51.659543 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1560 10:01:51.662680 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1561 10:01:51.666392 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1562 10:01:51.672578 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1563 10:01:51.676215 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1564 10:01:51.676294 ==
1565 10:01:51.679422 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 10:01:51.682660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 10:01:51.682743 ==
1568 10:01:51.682819 DQS Delay:
1569 10:01:51.685868 DQS0 = 0, DQS1 = 0
1570 10:01:51.685947 DQM Delay:
1571 10:01:51.689009 DQM0 = 81, DQM1 = 71
1572 10:01:51.689107 DQ Delay:
1573 10:01:51.692714 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1574 10:01:51.696051 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1575 10:01:51.699367 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1576 10:01:51.702671 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1577 10:01:51.702758
1578 10:01:51.702833
1579 10:01:51.702905 ==
1580 10:01:51.705719 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 10:01:51.712864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 10:01:51.712974 ==
1583 10:01:51.713049
1584 10:01:51.713118
1585 10:01:51.713181 TX Vref Scan disable
1586 10:01:51.715956 == TX Byte 0 ==
1587 10:01:51.719253 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1588 10:01:51.722189 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1589 10:01:51.726200 == TX Byte 1 ==
1590 10:01:51.729101 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1591 10:01:51.736235 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1592 10:01:51.736320 ==
1593 10:01:51.739717 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 10:01:51.742355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 10:01:51.742435 ==
1596 10:01:51.754502 TX Vref=22, minBit 0, minWin=27, winSum=439
1597 10:01:51.758556 TX Vref=24, minBit 0, minWin=27, winSum=438
1598 10:01:51.761497 TX Vref=26, minBit 1, minWin=27, winSum=443
1599 10:01:51.765008 TX Vref=28, minBit 5, minWin=27, winSum=448
1600 10:01:51.768139 TX Vref=30, minBit 1, minWin=27, winSum=449
1601 10:01:51.774377 TX Vref=32, minBit 0, minWin=27, winSum=444
1602 10:01:51.777678 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 30
1603 10:01:51.777758
1604 10:01:51.781302 Final TX Range 1 Vref 30
1605 10:01:51.781384
1606 10:01:51.781449 ==
1607 10:01:51.784944 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 10:01:51.788535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 10:01:51.788612 ==
1610 10:01:51.788681
1611 10:01:51.788770
1612 10:01:51.791733 TX Vref Scan disable
1613 10:01:51.795346 == TX Byte 0 ==
1614 10:01:51.798712 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1615 10:01:51.801605 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1616 10:01:51.805216 == TX Byte 1 ==
1617 10:01:51.808292 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1618 10:01:51.811475 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1619 10:01:51.811557
1620 10:01:51.815097 [DATLAT]
1621 10:01:51.815177 Freq=800, CH1 RK0
1622 10:01:51.815244
1623 10:01:51.818152 DATLAT Default: 0xa
1624 10:01:51.818223 0, 0xFFFF, sum = 0
1625 10:01:51.821623 1, 0xFFFF, sum = 0
1626 10:01:51.821701 2, 0xFFFF, sum = 0
1627 10:01:51.824894 3, 0xFFFF, sum = 0
1628 10:01:51.824968 4, 0xFFFF, sum = 0
1629 10:01:51.828328 5, 0xFFFF, sum = 0
1630 10:01:51.828410 6, 0xFFFF, sum = 0
1631 10:01:51.831541 7, 0xFFFF, sum = 0
1632 10:01:51.831629 8, 0xFFFF, sum = 0
1633 10:01:51.834806 9, 0x0, sum = 1
1634 10:01:51.834912 10, 0x0, sum = 2
1635 10:01:51.838436 11, 0x0, sum = 3
1636 10:01:51.838521 12, 0x0, sum = 4
1637 10:01:51.841542 best_step = 10
1638 10:01:51.841626
1639 10:01:51.841693 ==
1640 10:01:51.845014 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 10:01:51.848290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 10:01:51.848375 ==
1643 10:01:51.851408 RX Vref Scan: 1
1644 10:01:51.851492
1645 10:01:51.851559 Set Vref Range= 32 -> 127
1646 10:01:51.851623
1647 10:01:51.854658 RX Vref 32 -> 127, step: 1
1648 10:01:51.854742
1649 10:01:51.858017 RX Delay -111 -> 252, step: 8
1650 10:01:51.858101
1651 10:01:51.861359 Set Vref, RX VrefLevel [Byte0]: 32
1652 10:01:51.864622 [Byte1]: 32
1653 10:01:51.864707
1654 10:01:51.868252 Set Vref, RX VrefLevel [Byte0]: 33
1655 10:01:51.871324 [Byte1]: 33
1656 10:01:51.874885
1657 10:01:51.874969 Set Vref, RX VrefLevel [Byte0]: 34
1658 10:01:51.878146 [Byte1]: 34
1659 10:01:51.882741
1660 10:01:51.882824 Set Vref, RX VrefLevel [Byte0]: 35
1661 10:01:51.885725 [Byte1]: 35
1662 10:01:51.890308
1663 10:01:51.890392 Set Vref, RX VrefLevel [Byte0]: 36
1664 10:01:51.893450 [Byte1]: 36
1665 10:01:51.898156
1666 10:01:51.898239 Set Vref, RX VrefLevel [Byte0]: 37
1667 10:01:51.901257 [Byte1]: 37
1668 10:01:51.905504
1669 10:01:51.905588 Set Vref, RX VrefLevel [Byte0]: 38
1670 10:01:51.909359 [Byte1]: 38
1671 10:01:51.913636
1672 10:01:51.913721 Set Vref, RX VrefLevel [Byte0]: 39
1673 10:01:51.916941 [Byte1]: 39
1674 10:01:51.920695
1675 10:01:51.920779 Set Vref, RX VrefLevel [Byte0]: 40
1676 10:01:51.924472 [Byte1]: 40
1677 10:01:51.928661
1678 10:01:51.928777 Set Vref, RX VrefLevel [Byte0]: 41
1679 10:01:51.932117 [Byte1]: 41
1680 10:01:51.936091
1681 10:01:51.936177 Set Vref, RX VrefLevel [Byte0]: 42
1682 10:01:51.939823 [Byte1]: 42
1683 10:01:51.943829
1684 10:01:51.943906 Set Vref, RX VrefLevel [Byte0]: 43
1685 10:01:51.946939 [Byte1]: 43
1686 10:01:51.951456
1687 10:01:51.951542 Set Vref, RX VrefLevel [Byte0]: 44
1688 10:01:51.955027 [Byte1]: 44
1689 10:01:51.959408
1690 10:01:51.959493 Set Vref, RX VrefLevel [Byte0]: 45
1691 10:01:51.962649 [Byte1]: 45
1692 10:01:51.967051
1693 10:01:51.967135 Set Vref, RX VrefLevel [Byte0]: 46
1694 10:01:51.969999 [Byte1]: 46
1695 10:01:51.974523
1696 10:01:51.974607 Set Vref, RX VrefLevel [Byte0]: 47
1697 10:01:51.977560 [Byte1]: 47
1698 10:01:51.982198
1699 10:01:51.982281 Set Vref, RX VrefLevel [Byte0]: 48
1700 10:01:51.985455 [Byte1]: 48
1701 10:01:51.989636
1702 10:01:51.989720 Set Vref, RX VrefLevel [Byte0]: 49
1703 10:01:51.992901 [Byte1]: 49
1704 10:01:51.997615
1705 10:01:51.997694 Set Vref, RX VrefLevel [Byte0]: 50
1706 10:01:52.000789 [Byte1]: 50
1707 10:01:52.005100
1708 10:01:52.005177 Set Vref, RX VrefLevel [Byte0]: 51
1709 10:01:52.008280 [Byte1]: 51
1710 10:01:52.012758
1711 10:01:52.012861 Set Vref, RX VrefLevel [Byte0]: 52
1712 10:01:52.015886 [Byte1]: 52
1713 10:01:52.020162
1714 10:01:52.020265 Set Vref, RX VrefLevel [Byte0]: 53
1715 10:01:52.023606 [Byte1]: 53
1716 10:01:52.028066
1717 10:01:52.028190 Set Vref, RX VrefLevel [Byte0]: 54
1718 10:01:52.031511 [Byte1]: 54
1719 10:01:52.035540
1720 10:01:52.035635 Set Vref, RX VrefLevel [Byte0]: 55
1721 10:01:52.039122 [Byte1]: 55
1722 10:01:52.043314
1723 10:01:52.043439 Set Vref, RX VrefLevel [Byte0]: 56
1724 10:01:52.046729 [Byte1]: 56
1725 10:01:52.051003
1726 10:01:52.051080 Set Vref, RX VrefLevel [Byte0]: 57
1727 10:01:52.053967 [Byte1]: 57
1728 10:01:52.058703
1729 10:01:52.058810 Set Vref, RX VrefLevel [Byte0]: 58
1730 10:01:52.061721 [Byte1]: 58
1731 10:01:52.066275
1732 10:01:52.066375 Set Vref, RX VrefLevel [Byte0]: 59
1733 10:01:52.069598 [Byte1]: 59
1734 10:01:52.073933
1735 10:01:52.074010 Set Vref, RX VrefLevel [Byte0]: 60
1736 10:01:52.077186 [Byte1]: 60
1737 10:01:52.081394
1738 10:01:52.081472 Set Vref, RX VrefLevel [Byte0]: 61
1739 10:01:52.085053 [Byte1]: 61
1740 10:01:52.089198
1741 10:01:52.089281 Set Vref, RX VrefLevel [Byte0]: 62
1742 10:01:52.092256 [Byte1]: 62
1743 10:01:52.096824
1744 10:01:52.096901 Set Vref, RX VrefLevel [Byte0]: 63
1745 10:01:52.099983 [Byte1]: 63
1746 10:01:52.104329
1747 10:01:52.104407 Set Vref, RX VrefLevel [Byte0]: 64
1748 10:01:52.107806 [Byte1]: 64
1749 10:01:52.111940
1750 10:01:52.112048 Set Vref, RX VrefLevel [Byte0]: 65
1751 10:01:52.115263 [Byte1]: 65
1752 10:01:52.119853
1753 10:01:52.119932 Set Vref, RX VrefLevel [Byte0]: 66
1754 10:01:52.122984 [Byte1]: 66
1755 10:01:52.127505
1756 10:01:52.127593 Set Vref, RX VrefLevel [Byte0]: 67
1757 10:01:52.130750 [Byte1]: 67
1758 10:01:52.135180
1759 10:01:52.135267 Set Vref, RX VrefLevel [Byte0]: 68
1760 10:01:52.138535 [Byte1]: 68
1761 10:01:52.142937
1762 10:01:52.143038 Set Vref, RX VrefLevel [Byte0]: 69
1763 10:01:52.145908 [Byte1]: 69
1764 10:01:52.150218
1765 10:01:52.150303 Set Vref, RX VrefLevel [Byte0]: 70
1766 10:01:52.153751 [Byte1]: 70
1767 10:01:52.158118
1768 10:01:52.158204 Set Vref, RX VrefLevel [Byte0]: 71
1769 10:01:52.161594 [Byte1]: 71
1770 10:01:52.165738
1771 10:01:52.165824 Set Vref, RX VrefLevel [Byte0]: 72
1772 10:01:52.168848 [Byte1]: 72
1773 10:01:52.173552
1774 10:01:52.173637 Set Vref, RX VrefLevel [Byte0]: 73
1775 10:01:52.176566 [Byte1]: 73
1776 10:01:52.180723
1777 10:01:52.180809 Set Vref, RX VrefLevel [Byte0]: 74
1778 10:01:52.184530 [Byte1]: 74
1779 10:01:52.188521
1780 10:01:52.188611 Final RX Vref Byte 0 = 60 to rank0
1781 10:01:52.192274 Final RX Vref Byte 1 = 55 to rank0
1782 10:01:52.195542 Final RX Vref Byte 0 = 60 to rank1
1783 10:01:52.198784 Final RX Vref Byte 1 = 55 to rank1==
1784 10:01:52.201834 Dram Type= 6, Freq= 0, CH_1, rank 0
1785 10:01:52.208209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1786 10:01:52.208299 ==
1787 10:01:52.208387 DQS Delay:
1788 10:01:52.208469 DQS0 = 0, DQS1 = 0
1789 10:01:52.211758 DQM Delay:
1790 10:01:52.211845 DQM0 = 81, DQM1 = 71
1791 10:01:52.214934 DQ Delay:
1792 10:01:52.218596 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1793 10:01:52.221733 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1794 10:01:52.224914 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1795 10:01:52.228445 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1796 10:01:52.228531
1797 10:01:52.228615
1798 10:01:52.234713 [DQSOSCAuto] RK0, (LSB)MR18= 0xe18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1799 10:01:52.238438 CH1 RK0: MR19=606, MR18=E18
1800 10:01:52.244765 CH1_RK0: MR19=0x606, MR18=0xE18, DQSOSC=403, MR23=63, INC=90, DEC=60
1801 10:01:52.244852
1802 10:01:52.248206 ----->DramcWriteLeveling(PI) begin...
1803 10:01:52.248293 ==
1804 10:01:52.251870 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 10:01:52.254939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 10:01:52.255026 ==
1807 10:01:52.258084 Write leveling (Byte 0): 28 => 28
1808 10:01:52.261510 Write leveling (Byte 1): 29 => 29
1809 10:01:52.264664 DramcWriteLeveling(PI) end<-----
1810 10:01:52.264749
1811 10:01:52.264835 ==
1812 10:01:52.268024 Dram Type= 6, Freq= 0, CH_1, rank 1
1813 10:01:52.271138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 10:01:52.271224 ==
1815 10:01:52.274694 [Gating] SW mode calibration
1816 10:01:52.281125 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1817 10:01:52.287809 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1818 10:01:52.291238 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1819 10:01:52.295038 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1820 10:01:52.301113 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1821 10:01:52.304747 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 10:01:52.307807 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 10:01:52.314506 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 10:01:52.318206 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 10:01:52.321344 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 10:01:52.328082 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 10:01:52.331220 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 10:01:52.334336 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 10:01:52.341388 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 10:01:52.344517 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 10:01:52.347672 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 10:01:52.354476 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 10:01:52.357968 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 10:01:52.360699 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1835 10:01:52.367453 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1836 10:01:52.370730 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1837 10:01:52.374237 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 10:01:52.380521 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 10:01:52.384155 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 10:01:52.387426 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 10:01:52.394201 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 10:01:52.397303 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 10:01:52.400605 0 9 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1844 10:01:52.407246 0 9 8 | B1->B0 | 2d2c 3434 | 1 1 | (1 1) (1 1)
1845 10:01:52.410768 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 10:01:52.413867 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 10:01:52.420411 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 10:01:52.424079 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 10:01:52.427070 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 10:01:52.434162 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1851 10:01:52.437121 0 10 4 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
1852 10:01:52.440297 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 1) (0 0)
1853 10:01:52.443881 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 10:01:52.450404 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 10:01:52.453938 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 10:01:52.457180 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 10:01:52.463516 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 10:01:52.466982 0 11 0 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1859 10:01:52.470468 0 11 4 | B1->B0 | 2b2b 3737 | 0 0 | (1 1) (1 1)
1860 10:01:52.476740 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1861 10:01:52.480011 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 10:01:52.483421 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 10:01:52.490242 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 10:01:52.493648 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 10:01:52.496698 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 10:01:52.503824 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 10:01:52.507008 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1868 10:01:52.509989 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 10:01:52.516460 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 10:01:52.520552 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 10:01:52.523181 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 10:01:52.529974 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 10:01:52.533177 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 10:01:52.536818 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 10:01:52.543333 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 10:01:52.546448 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 10:01:52.550405 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 10:01:52.556687 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 10:01:52.559658 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 10:01:52.563564 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 10:01:52.569638 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 10:01:52.573168 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 10:01:52.576477 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1884 10:01:52.579569 Total UI for P1: 0, mck2ui 16
1885 10:01:52.582731 best dqsien dly found for B1: ( 0, 14, 2)
1886 10:01:52.589841 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 10:01:52.589923 Total UI for P1: 0, mck2ui 16
1888 10:01:52.595990 best dqsien dly found for B0: ( 0, 14, 4)
1889 10:01:52.599514 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1890 10:01:52.602504 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1891 10:01:52.602583
1892 10:01:52.605929 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1893 10:01:52.609092 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1894 10:01:52.612538 [Gating] SW calibration Done
1895 10:01:52.612615 ==
1896 10:01:52.616096 Dram Type= 6, Freq= 0, CH_1, rank 1
1897 10:01:52.619526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1898 10:01:52.619607 ==
1899 10:01:52.622920 RX Vref Scan: 0
1900 10:01:52.622995
1901 10:01:52.623060 RX Vref 0 -> 0, step: 1
1902 10:01:52.623122
1903 10:01:52.626031 RX Delay -130 -> 252, step: 16
1904 10:01:52.629390 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1905 10:01:52.636299 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1906 10:01:52.639264 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1907 10:01:52.642969 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1908 10:01:52.645742 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1909 10:01:52.649365 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1910 10:01:52.655962 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1911 10:01:52.659376 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1912 10:01:52.662375 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1913 10:01:52.666014 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1914 10:01:52.669150 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1915 10:01:52.675794 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1916 10:01:52.678990 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1917 10:01:52.682347 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1918 10:01:52.685721 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1919 10:01:52.689213 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1920 10:01:52.692237 ==
1921 10:01:52.695836 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 10:01:52.698884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 10:01:52.698989 ==
1924 10:01:52.699072 DQS Delay:
1925 10:01:52.702253 DQS0 = 0, DQS1 = 0
1926 10:01:52.702357 DQM Delay:
1927 10:01:52.705777 DQM0 = 77, DQM1 = 73
1928 10:01:52.705890 DQ Delay:
1929 10:01:52.709402 DQ0 =77, DQ1 =69, DQ2 =69, DQ3 =77
1930 10:01:52.712281 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1931 10:01:52.716297 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1932 10:01:52.718962 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1933 10:01:52.719116
1934 10:01:52.719239
1935 10:01:52.719359 ==
1936 10:01:52.722416 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 10:01:52.725564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 10:01:52.725746 ==
1939 10:01:52.725928
1940 10:01:52.726099
1941 10:01:52.728787 TX Vref Scan disable
1942 10:01:52.732843 == TX Byte 0 ==
1943 10:01:52.735856 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1944 10:01:52.739107 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1945 10:01:52.742302 == TX Byte 1 ==
1946 10:01:52.745620 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1947 10:01:52.749270 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1948 10:01:52.749674 ==
1949 10:01:52.752450 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 10:01:52.758650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 10:01:52.759080 ==
1952 10:01:52.770299 TX Vref=22, minBit 1, minWin=27, winSum=446
1953 10:01:52.773553 TX Vref=24, minBit 1, minWin=27, winSum=449
1954 10:01:52.777142 TX Vref=26, minBit 0, minWin=28, winSum=455
1955 10:01:52.780117 TX Vref=28, minBit 5, minWin=27, winSum=460
1956 10:01:52.783801 TX Vref=30, minBit 0, minWin=28, winSum=460
1957 10:01:52.790419 TX Vref=32, minBit 1, minWin=28, winSum=460
1958 10:01:52.793445 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 30
1959 10:01:52.793880
1960 10:01:52.796845 Final TX Range 1 Vref 30
1961 10:01:52.797337
1962 10:01:52.797701 ==
1963 10:01:52.800242 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 10:01:52.803552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 10:01:52.804056 ==
1966 10:01:52.807173
1967 10:01:52.807603
1968 10:01:52.807950 TX Vref Scan disable
1969 10:01:52.810167 == TX Byte 0 ==
1970 10:01:52.813379 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1971 10:01:52.820074 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1972 10:01:52.820508 == TX Byte 1 ==
1973 10:01:52.823264 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1974 10:01:52.830341 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1975 10:01:52.830818
1976 10:01:52.831226 [DATLAT]
1977 10:01:52.831556 Freq=800, CH1 RK1
1978 10:01:52.831877
1979 10:01:52.833532 DATLAT Default: 0xa
1980 10:01:52.833964 0, 0xFFFF, sum = 0
1981 10:01:52.836996 1, 0xFFFF, sum = 0
1982 10:01:52.837437 2, 0xFFFF, sum = 0
1983 10:01:52.840494 3, 0xFFFF, sum = 0
1984 10:01:52.843388 4, 0xFFFF, sum = 0
1985 10:01:52.843827 5, 0xFFFF, sum = 0
1986 10:01:52.846708 6, 0xFFFF, sum = 0
1987 10:01:52.847165 7, 0xFFFF, sum = 0
1988 10:01:52.849843 8, 0xFFFF, sum = 0
1989 10:01:52.850280 9, 0x0, sum = 1
1990 10:01:52.853627 10, 0x0, sum = 2
1991 10:01:52.854062 11, 0x0, sum = 3
1992 10:01:52.854415 12, 0x0, sum = 4
1993 10:01:52.856713 best_step = 10
1994 10:01:52.857157
1995 10:01:52.857507 ==
1996 10:01:52.859866 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 10:01:52.863082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 10:01:52.863518 ==
1999 10:01:52.866695 RX Vref Scan: 0
2000 10:01:52.867168
2001 10:01:52.867518 RX Vref 0 -> 0, step: 1
2002 10:01:52.869809
2003 10:01:52.870239 RX Delay -111 -> 252, step: 8
2004 10:01:52.877290 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
2005 10:01:52.880582 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2006 10:01:52.883828 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2007 10:01:52.886796 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2008 10:01:52.890433 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2009 10:01:52.896872 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2010 10:01:52.900471 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2011 10:01:52.903291 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2012 10:01:52.906646 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2013 10:01:52.910117 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2014 10:01:52.916751 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2015 10:01:52.919875 iDelay=209, Bit 11, Center 72 (-47 ~ 192) 240
2016 10:01:52.923611 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2017 10:01:52.926631 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2018 10:01:52.933274 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2019 10:01:52.936690 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2020 10:01:52.937144 ==
2021 10:01:52.940158 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 10:01:52.943771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 10:01:52.944232 ==
2024 10:01:52.946461 DQS Delay:
2025 10:01:52.946957 DQS0 = 0, DQS1 = 0
2026 10:01:52.947312 DQM Delay:
2027 10:01:52.950184 DQM0 = 78, DQM1 = 75
2028 10:01:52.950617 DQ Delay:
2029 10:01:52.953275 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2030 10:01:52.956542 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2031 10:01:52.959741 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
2032 10:01:52.962988 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2033 10:01:52.963421
2034 10:01:52.963766
2035 10:01:52.973237 [DQSOSCAuto] RK1, (LSB)MR18= 0x2037, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2036 10:01:52.973673 CH1 RK1: MR19=606, MR18=2037
2037 10:01:52.979898 CH1_RK1: MR19=0x606, MR18=0x2037, DQSOSC=395, MR23=63, INC=94, DEC=63
2038 10:01:52.983189 [RxdqsGatingPostProcess] freq 800
2039 10:01:52.989954 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2040 10:01:52.993049 Pre-setting of DQS Precalculation
2041 10:01:52.996151 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2042 10:01:53.003039 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2043 10:01:53.012636 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2044 10:01:53.013183
2045 10:01:53.013682
2046 10:01:53.016259 [Calibration Summary] 1600 Mbps
2047 10:01:53.016692 CH 0, Rank 0
2048 10:01:53.019522 SW Impedance : PASS
2049 10:01:53.019955 DUTY Scan : NO K
2050 10:01:53.022673 ZQ Calibration : PASS
2051 10:01:53.026318 Jitter Meter : NO K
2052 10:01:53.026751 CBT Training : PASS
2053 10:01:53.029395 Write leveling : PASS
2054 10:01:53.032587 RX DQS gating : PASS
2055 10:01:53.033019 RX DQ/DQS(RDDQC) : PASS
2056 10:01:53.036197 TX DQ/DQS : PASS
2057 10:01:53.036651 RX DATLAT : PASS
2058 10:01:53.039645 RX DQ/DQS(Engine): PASS
2059 10:01:53.042522 TX OE : NO K
2060 10:01:53.042995 All Pass.
2061 10:01:53.043348
2062 10:01:53.043672 CH 0, Rank 1
2063 10:01:53.045784 SW Impedance : PASS
2064 10:01:53.049136 DUTY Scan : NO K
2065 10:01:53.049570 ZQ Calibration : PASS
2066 10:01:53.052880 Jitter Meter : NO K
2067 10:01:53.056074 CBT Training : PASS
2068 10:01:53.056507 Write leveling : PASS
2069 10:01:53.058994 RX DQS gating : PASS
2070 10:01:53.062696 RX DQ/DQS(RDDQC) : PASS
2071 10:01:53.063193 TX DQ/DQS : PASS
2072 10:01:53.065897 RX DATLAT : PASS
2073 10:01:53.069199 RX DQ/DQS(Engine): PASS
2074 10:01:53.069629 TX OE : NO K
2075 10:01:53.072791 All Pass.
2076 10:01:53.073223
2077 10:01:53.073569 CH 1, Rank 0
2078 10:01:53.075972 SW Impedance : PASS
2079 10:01:53.076405 DUTY Scan : NO K
2080 10:01:53.079142 ZQ Calibration : PASS
2081 10:01:53.082402 Jitter Meter : NO K
2082 10:01:53.082862 CBT Training : PASS
2083 10:01:53.085680 Write leveling : PASS
2084 10:01:53.086121 RX DQS gating : PASS
2085 10:01:53.088833 RX DQ/DQS(RDDQC) : PASS
2086 10:01:53.092899 TX DQ/DQS : PASS
2087 10:01:53.093379 RX DATLAT : PASS
2088 10:01:53.095646 RX DQ/DQS(Engine): PASS
2089 10:01:53.098895 TX OE : NO K
2090 10:01:53.099328 All Pass.
2091 10:01:53.099759
2092 10:01:53.100100 CH 1, Rank 1
2093 10:01:53.102144 SW Impedance : PASS
2094 10:01:53.105676 DUTY Scan : NO K
2095 10:01:53.106109 ZQ Calibration : PASS
2096 10:01:53.108913 Jitter Meter : NO K
2097 10:01:53.112538 CBT Training : PASS
2098 10:01:53.112972 Write leveling : PASS
2099 10:01:53.115461 RX DQS gating : PASS
2100 10:01:53.119085 RX DQ/DQS(RDDQC) : PASS
2101 10:01:53.119624 TX DQ/DQS : PASS
2102 10:01:53.122492 RX DATLAT : PASS
2103 10:01:53.125326 RX DQ/DQS(Engine): PASS
2104 10:01:53.125794 TX OE : NO K
2105 10:01:53.128705 All Pass.
2106 10:01:53.129222
2107 10:01:53.129767 DramC Write-DBI off
2108 10:01:53.132136 PER_BANK_REFRESH: Hybrid Mode
2109 10:01:53.132567 TX_TRACKING: ON
2110 10:01:53.135696 [GetDramInforAfterCalByMRR] Vendor 6.
2111 10:01:53.142269 [GetDramInforAfterCalByMRR] Revision 606.
2112 10:01:53.145383 [GetDramInforAfterCalByMRR] Revision 2 0.
2113 10:01:53.145835 MR0 0x3b3b
2114 10:01:53.146186 MR8 0x5151
2115 10:01:53.148514 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 10:01:53.148948
2117 10:01:53.152141 MR0 0x3b3b
2118 10:01:53.152574 MR8 0x5151
2119 10:01:53.155186 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 10:01:53.155618
2121 10:01:53.165276 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2122 10:01:53.168446 [FAST_K] Save calibration result to emmc
2123 10:01:53.171666 [FAST_K] Save calibration result to emmc
2124 10:01:53.175383 dram_init: config_dvfs: 1
2125 10:01:53.178414 dramc_set_vcore_voltage set vcore to 662500
2126 10:01:53.181615 Read voltage for 1200, 2
2127 10:01:53.182047 Vio18 = 0
2128 10:01:53.182397 Vcore = 662500
2129 10:01:53.184897 Vdram = 0
2130 10:01:53.185329 Vddq = 0
2131 10:01:53.185675 Vmddr = 0
2132 10:01:53.191947 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2133 10:01:53.194925 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2134 10:01:53.198075 MEM_TYPE=3, freq_sel=15
2135 10:01:53.201479 sv_algorithm_assistance_LP4_1600
2136 10:01:53.204781 ============ PULL DRAM RESETB DOWN ============
2137 10:01:53.208059 ========== PULL DRAM RESETB DOWN end =========
2138 10:01:53.214765 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2139 10:01:53.217912 ===================================
2140 10:01:53.221239 LPDDR4 DRAM CONFIGURATION
2141 10:01:53.224661 ===================================
2142 10:01:53.225096 EX_ROW_EN[0] = 0x0
2143 10:01:53.228067 EX_ROW_EN[1] = 0x0
2144 10:01:53.228499 LP4Y_EN = 0x0
2145 10:01:53.231436 WORK_FSP = 0x0
2146 10:01:53.231885 WL = 0x4
2147 10:01:53.234992 RL = 0x4
2148 10:01:53.235420 BL = 0x2
2149 10:01:53.237945 RPST = 0x0
2150 10:01:53.238381 RD_PRE = 0x0
2151 10:01:53.241348 WR_PRE = 0x1
2152 10:01:53.241782 WR_PST = 0x0
2153 10:01:53.244836 DBI_WR = 0x0
2154 10:01:53.245270 DBI_RD = 0x0
2155 10:01:53.247816 OTF = 0x1
2156 10:01:53.251256 ===================================
2157 10:01:53.254823 ===================================
2158 10:01:53.255353 ANA top config
2159 10:01:53.257879 ===================================
2160 10:01:53.261522 DLL_ASYNC_EN = 0
2161 10:01:53.264584 ALL_SLAVE_EN = 0
2162 10:01:53.267882 NEW_RANK_MODE = 1
2163 10:01:53.268392 DLL_IDLE_MODE = 1
2164 10:01:53.271279 LP45_APHY_COMB_EN = 1
2165 10:01:53.274381 TX_ODT_DIS = 1
2166 10:01:53.277717 NEW_8X_MODE = 1
2167 10:01:53.281481 ===================================
2168 10:01:53.284374 ===================================
2169 10:01:53.287542 data_rate = 2400
2170 10:01:53.291268 CKR = 1
2171 10:01:53.291699 DQ_P2S_RATIO = 8
2172 10:01:53.294463 ===================================
2173 10:01:53.297714 CA_P2S_RATIO = 8
2174 10:01:53.300811 DQ_CA_OPEN = 0
2175 10:01:53.304674 DQ_SEMI_OPEN = 0
2176 10:01:53.307871 CA_SEMI_OPEN = 0
2177 10:01:53.308304 CA_FULL_RATE = 0
2178 10:01:53.311363 DQ_CKDIV4_EN = 0
2179 10:01:53.314313 CA_CKDIV4_EN = 0
2180 10:01:53.317502 CA_PREDIV_EN = 0
2181 10:01:53.320763 PH8_DLY = 17
2182 10:01:53.324398 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2183 10:01:53.324895 DQ_AAMCK_DIV = 4
2184 10:01:53.327854 CA_AAMCK_DIV = 4
2185 10:01:53.330627 CA_ADMCK_DIV = 4
2186 10:01:53.334226 DQ_TRACK_CA_EN = 0
2187 10:01:53.337483 CA_PICK = 1200
2188 10:01:53.341054 CA_MCKIO = 1200
2189 10:01:53.344117 MCKIO_SEMI = 0
2190 10:01:53.347300 PLL_FREQ = 2366
2191 10:01:53.347733 DQ_UI_PI_RATIO = 32
2192 10:01:53.350807 CA_UI_PI_RATIO = 0
2193 10:01:53.354138 ===================================
2194 10:01:53.357131 ===================================
2195 10:01:53.360815 memory_type:LPDDR4
2196 10:01:53.363870 GP_NUM : 10
2197 10:01:53.364299 SRAM_EN : 1
2198 10:01:53.367460 MD32_EN : 0
2199 10:01:53.370890 ===================================
2200 10:01:53.374052 [ANA_INIT] >>>>>>>>>>>>>>
2201 10:01:53.374479 <<<<<< [CONFIGURE PHASE]: ANA_TX
2202 10:01:53.377274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2203 10:01:53.380574 ===================================
2204 10:01:53.383906 data_rate = 2400,PCW = 0X5b00
2205 10:01:53.387252 ===================================
2206 10:01:53.390543 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2207 10:01:53.396844 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 10:01:53.403842 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2209 10:01:53.406811 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2210 10:01:53.410471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2211 10:01:53.413623 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2212 10:01:53.416773 [ANA_INIT] flow start
2213 10:01:53.417205 [ANA_INIT] PLL >>>>>>>>
2214 10:01:53.420503 [ANA_INIT] PLL <<<<<<<<
2215 10:01:53.423694 [ANA_INIT] MIDPI >>>>>>>>
2216 10:01:53.424125 [ANA_INIT] MIDPI <<<<<<<<
2217 10:01:53.426915 [ANA_INIT] DLL >>>>>>>>
2218 10:01:53.430239 [ANA_INIT] DLL <<<<<<<<
2219 10:01:53.430683 [ANA_INIT] flow end
2220 10:01:53.437103 ============ LP4 DIFF to SE enter ============
2221 10:01:53.440151 ============ LP4 DIFF to SE exit ============
2222 10:01:53.443609 [ANA_INIT] <<<<<<<<<<<<<
2223 10:01:53.446821 [Flow] Enable top DCM control >>>>>
2224 10:01:53.450097 [Flow] Enable top DCM control <<<<<
2225 10:01:53.450528 Enable DLL master slave shuffle
2226 10:01:53.456887 ==============================================================
2227 10:01:53.460338 Gating Mode config
2228 10:01:53.463543 ==============================================================
2229 10:01:53.466782 Config description:
2230 10:01:53.476753 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2231 10:01:53.483470 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2232 10:01:53.486269 SELPH_MODE 0: By rank 1: By Phase
2233 10:01:53.493168 ==============================================================
2234 10:01:53.496291 GAT_TRACK_EN = 1
2235 10:01:53.500086 RX_GATING_MODE = 2
2236 10:01:53.503367 RX_GATING_TRACK_MODE = 2
2237 10:01:53.506493 SELPH_MODE = 1
2238 10:01:53.509945 PICG_EARLY_EN = 1
2239 10:01:53.510377 VALID_LAT_VALUE = 1
2240 10:01:53.516436 ==============================================================
2241 10:01:53.519748 Enter into Gating configuration >>>>
2242 10:01:53.522918 Exit from Gating configuration <<<<
2243 10:01:53.526140 Enter into DVFS_PRE_config >>>>>
2244 10:01:53.536368 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2245 10:01:53.539343 Exit from DVFS_PRE_config <<<<<
2246 10:01:53.542735 Enter into PICG configuration >>>>
2247 10:01:53.546262 Exit from PICG configuration <<<<
2248 10:01:53.549342 [RX_INPUT] configuration >>>>>
2249 10:01:53.552669 [RX_INPUT] configuration <<<<<
2250 10:01:53.559128 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2251 10:01:53.562523 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2252 10:01:53.568979 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 10:01:53.575696 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 10:01:53.582098 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2255 10:01:53.588996 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2256 10:01:53.592481 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2257 10:01:53.595932 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2258 10:01:53.599167 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2259 10:01:53.605450 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2260 10:01:53.609285 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2261 10:01:53.612374 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2262 10:01:53.615625 ===================================
2263 10:01:53.618770 LPDDR4 DRAM CONFIGURATION
2264 10:01:53.622040 ===================================
2265 10:01:53.622476 EX_ROW_EN[0] = 0x0
2266 10:01:53.625208 EX_ROW_EN[1] = 0x0
2267 10:01:53.628960 LP4Y_EN = 0x0
2268 10:01:53.629392 WORK_FSP = 0x0
2269 10:01:53.632105 WL = 0x4
2270 10:01:53.632593 RL = 0x4
2271 10:01:53.635290 BL = 0x2
2272 10:01:53.635741 RPST = 0x0
2273 10:01:53.638470 RD_PRE = 0x0
2274 10:01:53.638939 WR_PRE = 0x1
2275 10:01:53.641696 WR_PST = 0x0
2276 10:01:53.642173 DBI_WR = 0x0
2277 10:01:53.645121 DBI_RD = 0x0
2278 10:01:53.645607 OTF = 0x1
2279 10:01:53.648749 ===================================
2280 10:01:53.651974 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2281 10:01:53.658528 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2282 10:01:53.661498 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2283 10:01:53.665069 ===================================
2284 10:01:53.668522 LPDDR4 DRAM CONFIGURATION
2285 10:01:53.672450 ===================================
2286 10:01:53.672910 EX_ROW_EN[0] = 0x10
2287 10:01:53.674808 EX_ROW_EN[1] = 0x0
2288 10:01:53.678204 LP4Y_EN = 0x0
2289 10:01:53.678663 WORK_FSP = 0x0
2290 10:01:53.681630 WL = 0x4
2291 10:01:53.682079 RL = 0x4
2292 10:01:53.684841 BL = 0x2
2293 10:01:53.685309 RPST = 0x0
2294 10:01:53.688224 RD_PRE = 0x0
2295 10:01:53.688715 WR_PRE = 0x1
2296 10:01:53.691602 WR_PST = 0x0
2297 10:01:53.692102 DBI_WR = 0x0
2298 10:01:53.695078 DBI_RD = 0x0
2299 10:01:53.695528 OTF = 0x1
2300 10:01:53.698024 ===================================
2301 10:01:53.704831 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2302 10:01:53.705281 ==
2303 10:01:53.708118 Dram Type= 6, Freq= 0, CH_0, rank 0
2304 10:01:53.711342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2305 10:01:53.714870 ==
2306 10:01:53.715184 [Duty_Offset_Calibration]
2307 10:01:53.718176 B0:2 B1:0 CA:3
2308 10:01:53.718482
2309 10:01:53.721066 [DutyScan_Calibration_Flow] k_type=0
2310 10:01:53.729616
2311 10:01:53.729898 ==CLK 0==
2312 10:01:53.732777 Final CLK duty delay cell = 0
2313 10:01:53.736001 [0] MAX Duty = 5062%(X100), DQS PI = 20
2314 10:01:53.739808 [0] MIN Duty = 4875%(X100), DQS PI = 58
2315 10:01:53.740007 [0] AVG Duty = 4968%(X100)
2316 10:01:53.742851
2317 10:01:53.746362 CH0 CLK Duty spec in!! Max-Min= 187%
2318 10:01:53.749814 [DutyScan_Calibration_Flow] ====Done====
2319 10:01:53.750529
2320 10:01:53.752882 [DutyScan_Calibration_Flow] k_type=1
2321 10:01:53.768458
2322 10:01:53.768879 ==DQS 0 ==
2323 10:01:53.771696 Final DQS duty delay cell = 0
2324 10:01:53.775221 [0] MAX Duty = 5062%(X100), DQS PI = 20
2325 10:01:53.778180 [0] MIN Duty = 4907%(X100), DQS PI = 2
2326 10:01:53.778629 [0] AVG Duty = 4984%(X100)
2327 10:01:53.781569
2328 10:01:53.782013 ==DQS 1 ==
2329 10:01:53.784949 Final DQS duty delay cell = -4
2330 10:01:53.788351 [-4] MAX Duty = 4969%(X100), DQS PI = 24
2331 10:01:53.791334 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2332 10:01:53.794769 [-4] AVG Duty = 4922%(X100)
2333 10:01:53.795379
2334 10:01:53.797935 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2335 10:01:53.798351
2336 10:01:53.801320 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2337 10:01:53.805079 [DutyScan_Calibration_Flow] ====Done====
2338 10:01:53.805530
2339 10:01:53.807974 [DutyScan_Calibration_Flow] k_type=3
2340 10:01:53.825364
2341 10:01:53.825914 ==DQM 0 ==
2342 10:01:53.829369 Final DQM duty delay cell = 0
2343 10:01:53.832151 [0] MAX Duty = 5124%(X100), DQS PI = 28
2344 10:01:53.835440 [0] MIN Duty = 4876%(X100), DQS PI = 0
2345 10:01:53.838637 [0] AVG Duty = 5000%(X100)
2346 10:01:53.839097
2347 10:01:53.839431 ==DQM 1 ==
2348 10:01:53.841856 Final DQM duty delay cell = 4
2349 10:01:53.845629 [4] MAX Duty = 5124%(X100), DQS PI = 50
2350 10:01:53.848795 [4] MIN Duty = 5031%(X100), DQS PI = 10
2351 10:01:53.851874 [4] AVG Duty = 5077%(X100)
2352 10:01:53.852300
2353 10:01:53.855462 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2354 10:01:53.855897
2355 10:01:53.858854 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2356 10:01:53.861802 [DutyScan_Calibration_Flow] ====Done====
2357 10:01:53.862234
2358 10:01:53.865510 [DutyScan_Calibration_Flow] k_type=2
2359 10:01:53.880613
2360 10:01:53.881047 ==DQ 0 ==
2361 10:01:53.883897 Final DQ duty delay cell = -4
2362 10:01:53.886931 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2363 10:01:53.890762 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2364 10:01:53.893673 [-4] AVG Duty = 4969%(X100)
2365 10:01:53.894107
2366 10:01:53.894457 ==DQ 1 ==
2367 10:01:53.897189 Final DQ duty delay cell = -4
2368 10:01:53.900588 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2369 10:01:53.903620 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2370 10:01:53.907172 [-4] AVG Duty = 4938%(X100)
2371 10:01:53.907605
2372 10:01:53.910248 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2373 10:01:53.910681
2374 10:01:53.913669 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2375 10:01:53.916820 [DutyScan_Calibration_Flow] ====Done====
2376 10:01:53.917343 ==
2377 10:01:53.920149 Dram Type= 6, Freq= 0, CH_1, rank 0
2378 10:01:53.923450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2379 10:01:53.923886 ==
2380 10:01:53.926718 [Duty_Offset_Calibration]
2381 10:01:53.927175 B0:1 B1:-2 CA:0
2382 10:01:53.927524
2383 10:01:53.930198 [DutyScan_Calibration_Flow] k_type=0
2384 10:01:53.941254
2385 10:01:53.941804 ==CLK 0==
2386 10:01:53.944705 Final CLK duty delay cell = 0
2387 10:01:53.947422 [0] MAX Duty = 5031%(X100), DQS PI = 18
2388 10:01:53.950719 [0] MIN Duty = 4907%(X100), DQS PI = 0
2389 10:01:53.954519 [0] AVG Duty = 4969%(X100)
2390 10:01:53.955011
2391 10:01:53.957544 CH1 CLK Duty spec in!! Max-Min= 124%
2392 10:01:53.961170 [DutyScan_Calibration_Flow] ====Done====
2393 10:01:53.961647
2394 10:01:53.964352 [DutyScan_Calibration_Flow] k_type=1
2395 10:01:53.979550
2396 10:01:53.980003 ==DQS 0 ==
2397 10:01:53.982500 Final DQS duty delay cell = -4
2398 10:01:53.986135 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2399 10:01:53.989652 [-4] MIN Duty = 4907%(X100), DQS PI = 4
2400 10:01:53.992561 [-4] AVG Duty = 4969%(X100)
2401 10:01:53.992995
2402 10:01:53.993370 ==DQS 1 ==
2403 10:01:53.995931 Final DQS duty delay cell = 0
2404 10:01:53.999246 [0] MAX Duty = 5093%(X100), DQS PI = 0
2405 10:01:54.002396 [0] MIN Duty = 4875%(X100), DQS PI = 26
2406 10:01:54.006169 [0] AVG Duty = 4984%(X100)
2407 10:01:54.006600
2408 10:01:54.009161 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2409 10:01:54.009607
2410 10:01:54.012605 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2411 10:01:54.015768 [DutyScan_Calibration_Flow] ====Done====
2412 10:01:54.016213
2413 10:01:54.019318 [DutyScan_Calibration_Flow] k_type=3
2414 10:01:54.036406
2415 10:01:54.036838 ==DQM 0 ==
2416 10:01:54.039495 Final DQM duty delay cell = 0
2417 10:01:54.042789 [0] MAX Duty = 5031%(X100), DQS PI = 24
2418 10:01:54.045944 [0] MIN Duty = 4876%(X100), DQS PI = 52
2419 10:01:54.049243 [0] AVG Duty = 4953%(X100)
2420 10:01:54.049669
2421 10:01:54.050009 ==DQM 1 ==
2422 10:01:54.052356 Final DQM duty delay cell = 0
2423 10:01:54.055618 [0] MAX Duty = 5031%(X100), DQS PI = 34
2424 10:01:54.059284 [0] MIN Duty = 4907%(X100), DQS PI = 4
2425 10:01:54.062510 [0] AVG Duty = 4969%(X100)
2426 10:01:54.063007
2427 10:01:54.065462 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2428 10:01:54.065889
2429 10:01:54.068745 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2430 10:01:54.072565 [DutyScan_Calibration_Flow] ====Done====
2431 10:01:54.072995
2432 10:01:54.075467 [DutyScan_Calibration_Flow] k_type=2
2433 10:01:54.092709
2434 10:01:54.093189 ==DQ 0 ==
2435 10:01:54.095628 Final DQ duty delay cell = 0
2436 10:01:54.099126 [0] MAX Duty = 5093%(X100), DQS PI = 20
2437 10:01:54.102524 [0] MIN Duty = 4938%(X100), DQS PI = 54
2438 10:01:54.102980 [0] AVG Duty = 5015%(X100)
2439 10:01:54.106166
2440 10:01:54.106687 ==DQ 1 ==
2441 10:01:54.108857 Final DQ duty delay cell = 0
2442 10:01:54.112526 [0] MAX Duty = 5093%(X100), DQS PI = 18
2443 10:01:54.116012 [0] MIN Duty = 4969%(X100), DQS PI = 26
2444 10:01:54.116446 [0] AVG Duty = 5031%(X100)
2445 10:01:54.119017
2446 10:01:54.122238 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2447 10:01:54.122670
2448 10:01:54.125422 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2449 10:01:54.128998 [DutyScan_Calibration_Flow] ====Done====
2450 10:01:54.131838 nWR fixed to 30
2451 10:01:54.132272 [ModeRegInit_LP4] CH0 RK0
2452 10:01:54.135487 [ModeRegInit_LP4] CH0 RK1
2453 10:01:54.138642 [ModeRegInit_LP4] CH1 RK0
2454 10:01:54.142173 [ModeRegInit_LP4] CH1 RK1
2455 10:01:54.142602 match AC timing 7
2456 10:01:54.148602 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2457 10:01:54.151761 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2458 10:01:54.154967 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2459 10:01:54.161903 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2460 10:01:54.165097 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2461 10:01:54.165528 ==
2462 10:01:54.168160 Dram Type= 6, Freq= 0, CH_0, rank 0
2463 10:01:54.171761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2464 10:01:54.172195 ==
2465 10:01:54.178203 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2466 10:01:54.184938 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2467 10:01:54.192364 [CA 0] Center 40 (10~71) winsize 62
2468 10:01:54.195706 [CA 1] Center 39 (9~70) winsize 62
2469 10:01:54.199224 [CA 2] Center 36 (6~66) winsize 61
2470 10:01:54.202553 [CA 3] Center 35 (5~66) winsize 62
2471 10:01:54.205591 [CA 4] Center 34 (4~65) winsize 62
2472 10:01:54.209077 [CA 5] Center 33 (3~63) winsize 61
2473 10:01:54.209506
2474 10:01:54.212511 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2475 10:01:54.212940
2476 10:01:54.215595 [CATrainingPosCal] consider 1 rank data
2477 10:01:54.218727 u2DelayCellTimex100 = 270/100 ps
2478 10:01:54.222343 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2479 10:01:54.228706 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2480 10:01:54.232522 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2481 10:01:54.235734 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2482 10:01:54.239071 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2483 10:01:54.242329 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2484 10:01:54.242753
2485 10:01:54.245478 CA PerBit enable=1, Macro0, CA PI delay=33
2486 10:01:54.245908
2487 10:01:54.248815 [CBTSetCACLKResult] CA Dly = 33
2488 10:01:54.252341 CS Dly: 7 (0~38)
2489 10:01:54.252768 ==
2490 10:01:54.255591 Dram Type= 6, Freq= 0, CH_0, rank 1
2491 10:01:54.258893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2492 10:01:54.259326 ==
2493 10:01:54.265288 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2494 10:01:54.268491 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2495 10:01:54.278428 [CA 0] Center 40 (10~70) winsize 61
2496 10:01:54.282244 [CA 1] Center 40 (10~70) winsize 61
2497 10:01:54.285479 [CA 2] Center 35 (5~66) winsize 62
2498 10:01:54.288646 [CA 3] Center 35 (5~66) winsize 62
2499 10:01:54.291739 [CA 4] Center 34 (4~65) winsize 62
2500 10:01:54.295125 [CA 5] Center 33 (3~64) winsize 62
2501 10:01:54.295570
2502 10:01:54.298638 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2503 10:01:54.299113
2504 10:01:54.302000 [CATrainingPosCal] consider 2 rank data
2505 10:01:54.305049 u2DelayCellTimex100 = 270/100 ps
2506 10:01:54.308588 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2507 10:01:54.315117 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2508 10:01:54.318260 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2509 10:01:54.322104 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2510 10:01:54.324931 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2511 10:01:54.328558 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2512 10:01:54.329064
2513 10:01:54.331946 CA PerBit enable=1, Macro0, CA PI delay=33
2514 10:01:54.332419
2515 10:01:54.334792 [CBTSetCACLKResult] CA Dly = 33
2516 10:01:54.338475 CS Dly: 8 (0~40)
2517 10:01:54.339096
2518 10:01:54.341415 ----->DramcWriteLeveling(PI) begin...
2519 10:01:54.342007 ==
2520 10:01:54.344822 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 10:01:54.348333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 10:01:54.348795 ==
2523 10:01:54.351431 Write leveling (Byte 0): 31 => 31
2524 10:01:54.354670 Write leveling (Byte 1): 29 => 29
2525 10:01:54.357884 DramcWriteLeveling(PI) end<-----
2526 10:01:54.358445
2527 10:01:54.358888 ==
2528 10:01:54.361686 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 10:01:54.364779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 10:01:54.365247 ==
2531 10:01:54.367910 [Gating] SW mode calibration
2532 10:01:54.374791 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2533 10:01:54.381166 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2534 10:01:54.384726 0 15 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
2535 10:01:54.388055 0 15 4 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
2536 10:01:54.394324 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 10:01:54.397946 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 10:01:54.401082 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 10:01:54.407565 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 10:01:54.410952 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 10:01:54.414479 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2542 10:01:54.420986 1 0 0 | B1->B0 | 3030 2525 | 0 0 | (0 0) (0 0)
2543 10:01:54.424612 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2544 10:01:54.427369 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 10:01:54.433908 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 10:01:54.437784 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 10:01:54.440985 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 10:01:54.447888 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 10:01:54.450884 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 10:01:54.454082 1 1 0 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
2551 10:01:54.460743 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2552 10:01:54.463942 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 10:01:54.467236 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 10:01:54.473615 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 10:01:54.477250 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 10:01:54.480357 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 10:01:54.487237 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2558 10:01:54.490368 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2559 10:01:54.493588 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2560 10:01:54.500303 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 10:01:54.503596 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 10:01:54.506814 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 10:01:54.513693 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 10:01:54.516792 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 10:01:54.520160 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 10:01:54.527057 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 10:01:54.530070 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 10:01:54.533414 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 10:01:54.540036 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 10:01:54.543344 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 10:01:54.546740 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 10:01:54.553382 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 10:01:54.556939 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2574 10:01:54.559801 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2575 10:01:54.563524 Total UI for P1: 0, mck2ui 16
2576 10:01:54.566799 best dqsien dly found for B0: ( 1, 3, 28)
2577 10:01:54.569962 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2578 10:01:54.576718 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 10:01:54.580050 Total UI for P1: 0, mck2ui 16
2580 10:01:54.583160 best dqsien dly found for B1: ( 1, 4, 2)
2581 10:01:54.586625 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2582 10:01:54.589861 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2583 10:01:54.590303
2584 10:01:54.593096 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2585 10:01:54.596284 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2586 10:01:54.600152 [Gating] SW calibration Done
2587 10:01:54.600597 ==
2588 10:01:54.603304 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 10:01:54.606417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 10:01:54.606889 ==
2591 10:01:54.609830 RX Vref Scan: 0
2592 10:01:54.610277
2593 10:01:54.613319 RX Vref 0 -> 0, step: 1
2594 10:01:54.613764
2595 10:01:54.614214 RX Delay -40 -> 252, step: 8
2596 10:01:54.619482 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2597 10:01:54.622929 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2598 10:01:54.626525 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2599 10:01:54.629508 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2600 10:01:54.633103 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2601 10:01:54.639397 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2602 10:01:54.642991 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2603 10:01:54.646296 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2604 10:01:54.649436 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2605 10:01:54.652968 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2606 10:01:54.656276 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2607 10:01:54.662772 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2608 10:01:54.665852 iDelay=200, Bit 12, Center 107 (40 ~ 175) 136
2609 10:01:54.669223 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2610 10:01:54.672920 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2611 10:01:54.679438 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2612 10:01:54.679888 ==
2613 10:01:54.682673 Dram Type= 6, Freq= 0, CH_0, rank 0
2614 10:01:54.685749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2615 10:01:54.686194 ==
2616 10:01:54.686648 DQS Delay:
2617 10:01:54.689278 DQS0 = 0, DQS1 = 0
2618 10:01:54.689722 DQM Delay:
2619 10:01:54.692437 DQM0 = 112, DQM1 = 102
2620 10:01:54.692883 DQ Delay:
2621 10:01:54.695728 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2622 10:01:54.699498 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2623 10:01:54.702627 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2624 10:01:54.705725 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2625 10:01:54.706157
2626 10:01:54.706504
2627 10:01:54.706861 ==
2628 10:01:54.709367 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 10:01:54.715647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 10:01:54.716081 ==
2631 10:01:54.716424
2632 10:01:54.716747
2633 10:01:54.717055 TX Vref Scan disable
2634 10:01:54.719457 == TX Byte 0 ==
2635 10:01:54.722982 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2636 10:01:54.729310 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2637 10:01:54.729803 == TX Byte 1 ==
2638 10:01:54.732702 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2639 10:01:54.739852 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2640 10:01:54.740380 ==
2641 10:01:54.742826 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 10:01:54.745804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 10:01:54.746312 ==
2644 10:01:54.756973 TX Vref=22, minBit 5, minWin=25, winSum=417
2645 10:01:54.760392 TX Vref=24, minBit 1, minWin=26, winSum=422
2646 10:01:54.763748 TX Vref=26, minBit 4, minWin=26, winSum=435
2647 10:01:54.766964 TX Vref=28, minBit 10, minWin=26, winSum=438
2648 10:01:54.770054 TX Vref=30, minBit 8, minWin=26, winSum=436
2649 10:01:54.777197 TX Vref=32, minBit 10, minWin=25, winSum=429
2650 10:01:54.779750 [TxChooseVref] Worse bit 10, Min win 26, Win sum 438, Final Vref 28
2651 10:01:54.779853
2652 10:01:54.783476 Final TX Range 1 Vref 28
2653 10:01:54.783589
2654 10:01:54.783685 ==
2655 10:01:54.786702 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 10:01:54.792953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 10:01:54.793031 ==
2658 10:01:54.793113
2659 10:01:54.793177
2660 10:01:54.793238 TX Vref Scan disable
2661 10:01:54.797148 == TX Byte 0 ==
2662 10:01:54.800516 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2663 10:01:54.806846 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2664 10:01:54.806936 == TX Byte 1 ==
2665 10:01:54.810054 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2666 10:01:54.817005 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2667 10:01:54.817089
2668 10:01:54.817156 [DATLAT]
2669 10:01:54.817218 Freq=1200, CH0 RK0
2670 10:01:54.817278
2671 10:01:54.820060 DATLAT Default: 0xd
2672 10:01:54.823287 0, 0xFFFF, sum = 0
2673 10:01:54.823372 1, 0xFFFF, sum = 0
2674 10:01:54.826483 2, 0xFFFF, sum = 0
2675 10:01:54.826568 3, 0xFFFF, sum = 0
2676 10:01:54.830027 4, 0xFFFF, sum = 0
2677 10:01:54.830113 5, 0xFFFF, sum = 0
2678 10:01:54.833365 6, 0xFFFF, sum = 0
2679 10:01:54.833449 7, 0xFFFF, sum = 0
2680 10:01:54.836329 8, 0xFFFF, sum = 0
2681 10:01:54.836419 9, 0xFFFF, sum = 0
2682 10:01:54.840239 10, 0xFFFF, sum = 0
2683 10:01:54.840324 11, 0xFFFF, sum = 0
2684 10:01:54.843244 12, 0x0, sum = 1
2685 10:01:54.843328 13, 0x0, sum = 2
2686 10:01:54.846295 14, 0x0, sum = 3
2687 10:01:54.846379 15, 0x0, sum = 4
2688 10:01:54.849739 best_step = 13
2689 10:01:54.849841
2690 10:01:54.849931 ==
2691 10:01:54.853214 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 10:01:54.856225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 10:01:54.856338 ==
2694 10:01:54.859480 RX Vref Scan: 1
2695 10:01:54.859563
2696 10:01:54.859631 Set Vref Range= 32 -> 127
2697 10:01:54.859694
2698 10:01:54.863034 RX Vref 32 -> 127, step: 1
2699 10:01:54.863117
2700 10:01:54.866077 RX Delay -37 -> 252, step: 4
2701 10:01:54.866159
2702 10:01:54.869730 Set Vref, RX VrefLevel [Byte0]: 32
2703 10:01:54.872872 [Byte1]: 32
2704 10:01:54.872955
2705 10:01:54.876117 Set Vref, RX VrefLevel [Byte0]: 33
2706 10:01:54.879393 [Byte1]: 33
2707 10:01:54.884154
2708 10:01:54.884237 Set Vref, RX VrefLevel [Byte0]: 34
2709 10:01:54.886953 [Byte1]: 34
2710 10:01:54.891746
2711 10:01:54.891829 Set Vref, RX VrefLevel [Byte0]: 35
2712 10:01:54.894847 [Byte1]: 35
2713 10:01:54.899457
2714 10:01:54.899541 Set Vref, RX VrefLevel [Byte0]: 36
2715 10:01:54.903288 [Byte1]: 36
2716 10:01:54.907598
2717 10:01:54.907681 Set Vref, RX VrefLevel [Byte0]: 37
2718 10:01:54.910764 [Byte1]: 37
2719 10:01:54.915575
2720 10:01:54.915658 Set Vref, RX VrefLevel [Byte0]: 38
2721 10:01:54.918814 [Byte1]: 38
2722 10:01:54.923578
2723 10:01:54.923661 Set Vref, RX VrefLevel [Byte0]: 39
2724 10:01:54.927116 [Byte1]: 39
2725 10:01:54.931554
2726 10:01:54.931637 Set Vref, RX VrefLevel [Byte0]: 40
2727 10:01:54.935034 [Byte1]: 40
2728 10:01:54.939465
2729 10:01:54.939548 Set Vref, RX VrefLevel [Byte0]: 41
2730 10:01:54.943160 [Byte1]: 41
2731 10:01:54.947834
2732 10:01:54.947916 Set Vref, RX VrefLevel [Byte0]: 42
2733 10:01:54.950764 [Byte1]: 42
2734 10:01:54.955821
2735 10:01:54.955903 Set Vref, RX VrefLevel [Byte0]: 43
2736 10:01:54.959023 [Byte1]: 43
2737 10:01:54.964120
2738 10:01:54.964203 Set Vref, RX VrefLevel [Byte0]: 44
2739 10:01:54.967100 [Byte1]: 44
2740 10:01:54.971771
2741 10:01:54.971854 Set Vref, RX VrefLevel [Byte0]: 45
2742 10:01:54.978289 [Byte1]: 45
2743 10:01:54.978372
2744 10:01:54.981604 Set Vref, RX VrefLevel [Byte0]: 46
2745 10:01:54.984590 [Byte1]: 46
2746 10:01:54.984673
2747 10:01:54.988125 Set Vref, RX VrefLevel [Byte0]: 47
2748 10:01:54.991057 [Byte1]: 47
2749 10:01:54.995864
2750 10:01:54.995946 Set Vref, RX VrefLevel [Byte0]: 48
2751 10:01:54.999097 [Byte1]: 48
2752 10:01:55.003621
2753 10:01:55.003704 Set Vref, RX VrefLevel [Byte0]: 49
2754 10:01:55.006779 [Byte1]: 49
2755 10:01:55.011575
2756 10:01:55.011661 Set Vref, RX VrefLevel [Byte0]: 50
2757 10:01:55.015037 [Byte1]: 50
2758 10:01:55.019608
2759 10:01:55.019690 Set Vref, RX VrefLevel [Byte0]: 51
2760 10:01:55.022782 [Byte1]: 51
2761 10:01:55.027561
2762 10:01:55.027644 Set Vref, RX VrefLevel [Byte0]: 52
2763 10:01:55.031251 [Byte1]: 52
2764 10:01:55.035722
2765 10:01:55.035805 Set Vref, RX VrefLevel [Byte0]: 53
2766 10:01:55.039079 [Byte1]: 53
2767 10:01:55.043569
2768 10:01:55.043652 Set Vref, RX VrefLevel [Byte0]: 54
2769 10:01:55.047001 [Byte1]: 54
2770 10:01:55.051955
2771 10:01:55.052038 Set Vref, RX VrefLevel [Byte0]: 55
2772 10:01:55.054823 [Byte1]: 55
2773 10:01:55.059759
2774 10:01:55.059842 Set Vref, RX VrefLevel [Byte0]: 56
2775 10:01:55.063398 [Byte1]: 56
2776 10:01:55.067569
2777 10:01:55.067652 Set Vref, RX VrefLevel [Byte0]: 57
2778 10:01:55.071146 [Byte1]: 57
2779 10:01:55.075909
2780 10:01:55.075992 Set Vref, RX VrefLevel [Byte0]: 58
2781 10:01:55.078733 [Byte1]: 58
2782 10:01:55.083856
2783 10:01:55.083939 Set Vref, RX VrefLevel [Byte0]: 59
2784 10:01:55.090235 [Byte1]: 59
2785 10:01:55.090318
2786 10:01:55.093412 Set Vref, RX VrefLevel [Byte0]: 60
2787 10:01:55.097021 [Byte1]: 60
2788 10:01:55.097105
2789 10:01:55.099838 Set Vref, RX VrefLevel [Byte0]: 61
2790 10:01:55.103164 [Byte1]: 61
2791 10:01:55.107871
2792 10:01:55.107954 Set Vref, RX VrefLevel [Byte0]: 62
2793 10:01:55.111044 [Byte1]: 62
2794 10:01:55.115765
2795 10:01:55.115848 Set Vref, RX VrefLevel [Byte0]: 63
2796 10:01:55.118840 [Byte1]: 63
2797 10:01:55.123734
2798 10:01:55.123817 Set Vref, RX VrefLevel [Byte0]: 64
2799 10:01:55.127084 [Byte1]: 64
2800 10:01:55.131433
2801 10:01:55.131515 Set Vref, RX VrefLevel [Byte0]: 65
2802 10:01:55.135183 [Byte1]: 65
2803 10:01:55.139917
2804 10:01:55.139999 Set Vref, RX VrefLevel [Byte0]: 66
2805 10:01:55.142718 [Byte1]: 66
2806 10:01:55.147482
2807 10:01:55.147565 Set Vref, RX VrefLevel [Byte0]: 67
2808 10:01:55.151159 [Byte1]: 67
2809 10:01:55.155884
2810 10:01:55.155967 Set Vref, RX VrefLevel [Byte0]: 68
2811 10:01:55.158751 [Byte1]: 68
2812 10:01:55.163795
2813 10:01:55.163878 Set Vref, RX VrefLevel [Byte0]: 69
2814 10:01:55.166991 [Byte1]: 69
2815 10:01:55.171599
2816 10:01:55.171682 Set Vref, RX VrefLevel [Byte0]: 70
2817 10:01:55.174844 [Byte1]: 70
2818 10:01:55.179880
2819 10:01:55.179963 Set Vref, RX VrefLevel [Byte0]: 71
2820 10:01:55.182887 [Byte1]: 71
2821 10:01:55.187500
2822 10:01:55.187583 Set Vref, RX VrefLevel [Byte0]: 72
2823 10:01:55.191069 [Byte1]: 72
2824 10:01:55.195558
2825 10:01:55.195667 Set Vref, RX VrefLevel [Byte0]: 73
2826 10:01:55.198729 [Byte1]: 73
2827 10:01:55.203591
2828 10:01:55.203674 Set Vref, RX VrefLevel [Byte0]: 74
2829 10:01:55.206809 [Byte1]: 74
2830 10:01:55.211985
2831 10:01:55.212068 Final RX Vref Byte 0 = 62 to rank0
2832 10:01:55.215129 Final RX Vref Byte 1 = 55 to rank0
2833 10:01:55.218297 Final RX Vref Byte 0 = 62 to rank1
2834 10:01:55.221429 Final RX Vref Byte 1 = 55 to rank1==
2835 10:01:55.225145 Dram Type= 6, Freq= 0, CH_0, rank 0
2836 10:01:55.231574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 10:01:55.231658 ==
2838 10:01:55.231725 DQS Delay:
2839 10:01:55.231789 DQS0 = 0, DQS1 = 0
2840 10:01:55.234765 DQM Delay:
2841 10:01:55.234899 DQM0 = 112, DQM1 = 102
2842 10:01:55.237970 DQ Delay:
2843 10:01:55.241780 DQ0 =112, DQ1 =112, DQ2 =114, DQ3 =108
2844 10:01:55.245039 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2845 10:01:55.248230 DQ8 =94, DQ9 =86, DQ10 =102, DQ11 =94
2846 10:01:55.251828 DQ12 =108, DQ13 =106, DQ14 =116, DQ15 =110
2847 10:01:55.251911
2848 10:01:55.251977
2849 10:01:55.258450 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
2850 10:01:55.261625 CH0 RK0: MR19=303, MR18=FCFB
2851 10:01:55.268375 CH0_RK0: MR19=0x303, MR18=0xFCFB, DQSOSC=411, MR23=63, INC=38, DEC=25
2852 10:01:55.268459
2853 10:01:55.271389 ----->DramcWriteLeveling(PI) begin...
2854 10:01:55.271474 ==
2855 10:01:55.274818 Dram Type= 6, Freq= 0, CH_0, rank 1
2856 10:01:55.278202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2857 10:01:55.281543 ==
2858 10:01:55.281630 Write leveling (Byte 0): 33 => 33
2859 10:01:55.284649 Write leveling (Byte 1): 31 => 31
2860 10:01:55.287832 DramcWriteLeveling(PI) end<-----
2861 10:01:55.287915
2862 10:01:55.287981 ==
2863 10:01:55.291397 Dram Type= 6, Freq= 0, CH_0, rank 1
2864 10:01:55.297703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2865 10:01:55.297787 ==
2866 10:01:55.300859 [Gating] SW mode calibration
2867 10:01:55.307836 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2868 10:01:55.311393 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2869 10:01:55.318025 0 15 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
2870 10:01:55.321283 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2871 10:01:55.324479 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 10:01:55.330813 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2873 10:01:55.334580 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2874 10:01:55.337943 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2875 10:01:55.344117 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2876 10:01:55.347928 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
2877 10:01:55.351108 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2878 10:01:55.357437 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 10:01:55.361120 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 10:01:55.364038 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2881 10:01:55.370729 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2882 10:01:55.374119 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2883 10:01:55.377644 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2884 10:01:55.383907 1 0 28 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
2885 10:01:55.387416 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
2886 10:01:55.390684 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 10:01:55.394148 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 10:01:55.400650 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 10:01:55.403812 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 10:01:55.407303 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 10:01:55.414021 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 10:01:55.416992 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2893 10:01:55.420496 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2894 10:01:55.427140 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 10:01:55.430622 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 10:01:55.434083 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 10:01:55.440366 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 10:01:55.443429 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 10:01:55.447264 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 10:01:55.453547 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 10:01:55.456727 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 10:01:55.460251 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 10:01:55.466770 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 10:01:55.470200 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 10:01:55.473402 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 10:01:55.480257 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 10:01:55.483206 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2908 10:01:55.486623 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2909 10:01:55.490696 Total UI for P1: 0, mck2ui 16
2910 10:01:55.493744 best dqsien dly found for B0: ( 1, 3, 24)
2911 10:01:55.500094 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 10:01:55.500179 Total UI for P1: 0, mck2ui 16
2913 10:01:55.507169 best dqsien dly found for B1: ( 1, 3, 28)
2914 10:01:55.510131 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2915 10:01:55.513329 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2916 10:01:55.513413
2917 10:01:55.516727 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2918 10:01:55.519971 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2919 10:01:55.523183 [Gating] SW calibration Done
2920 10:01:55.523267 ==
2921 10:01:55.526699 Dram Type= 6, Freq= 0, CH_0, rank 1
2922 10:01:55.530004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2923 10:01:55.530089 ==
2924 10:01:55.533379 RX Vref Scan: 0
2925 10:01:55.533462
2926 10:01:55.533530 RX Vref 0 -> 0, step: 1
2927 10:01:55.533597
2928 10:01:55.536419 RX Delay -40 -> 252, step: 8
2929 10:01:55.539611 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2930 10:01:55.546470 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2931 10:01:55.549606 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2932 10:01:55.552846 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2933 10:01:55.556434 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2934 10:01:55.559626 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2935 10:01:55.566086 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2936 10:01:55.569528 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2937 10:01:55.572958 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2938 10:01:55.575979 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2939 10:01:55.579270 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2940 10:01:55.586171 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2941 10:01:55.589481 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2942 10:01:55.592705 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2943 10:01:55.595982 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2944 10:01:55.599802 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2945 10:01:55.602374 ==
2946 10:01:55.606091 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 10:01:55.609394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 10:01:55.609477 ==
2949 10:01:55.609544 DQS Delay:
2950 10:01:55.612766 DQS0 = 0, DQS1 = 0
2951 10:01:55.612848 DQM Delay:
2952 10:01:55.615865 DQM0 = 111, DQM1 = 101
2953 10:01:55.615949 DQ Delay:
2954 10:01:55.619302 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2955 10:01:55.622510 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2956 10:01:55.625941 DQ8 =91, DQ9 =83, DQ10 =107, DQ11 =95
2957 10:01:55.629500 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
2958 10:01:55.629576
2959 10:01:55.629648
2960 10:01:55.629709 ==
2961 10:01:55.632203 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 10:01:55.639382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 10:01:55.639459 ==
2964 10:01:55.639524
2965 10:01:55.639583
2966 10:01:55.639642 TX Vref Scan disable
2967 10:01:55.642393 == TX Byte 0 ==
2968 10:01:55.645594 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2969 10:01:55.652554 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2970 10:01:55.652654 == TX Byte 1 ==
2971 10:01:55.655823 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2972 10:01:55.662201 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2973 10:01:55.662314 ==
2974 10:01:55.665801 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 10:01:55.669102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 10:01:55.669240 ==
2977 10:01:55.680445 TX Vref=22, minBit 1, minWin=25, winSum=421
2978 10:01:55.683850 TX Vref=24, minBit 1, minWin=26, winSum=430
2979 10:01:55.687393 TX Vref=26, minBit 2, minWin=26, winSum=435
2980 10:01:55.690373 TX Vref=28, minBit 2, minWin=26, winSum=438
2981 10:01:55.693773 TX Vref=30, minBit 2, minWin=27, winSum=442
2982 10:01:55.697225 TX Vref=32, minBit 3, minWin=26, winSum=438
2983 10:01:55.704124 [TxChooseVref] Worse bit 2, Min win 27, Win sum 442, Final Vref 30
2984 10:01:55.704552
2985 10:01:55.707468 Final TX Range 1 Vref 30
2986 10:01:55.707895
2987 10:01:55.708240 ==
2988 10:01:55.710616 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 10:01:55.713852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 10:01:55.714281 ==
2991 10:01:55.714623
2992 10:01:55.717034
2993 10:01:55.717460 TX Vref Scan disable
2994 10:01:55.720630 == TX Byte 0 ==
2995 10:01:55.723938 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2996 10:01:55.727366 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2997 10:01:55.730431 == TX Byte 1 ==
2998 10:01:55.733599 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2999 10:01:55.737089 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3000 10:01:55.740779
3001 10:01:55.741204 [DATLAT]
3002 10:01:55.741542 Freq=1200, CH0 RK1
3003 10:01:55.741861
3004 10:01:55.743899 DATLAT Default: 0xd
3005 10:01:55.744330 0, 0xFFFF, sum = 0
3006 10:01:55.747101 1, 0xFFFF, sum = 0
3007 10:01:55.747538 2, 0xFFFF, sum = 0
3008 10:01:55.750553 3, 0xFFFF, sum = 0
3009 10:01:55.753674 4, 0xFFFF, sum = 0
3010 10:01:55.754112 5, 0xFFFF, sum = 0
3011 10:01:55.756853 6, 0xFFFF, sum = 0
3012 10:01:55.757293 7, 0xFFFF, sum = 0
3013 10:01:55.760106 8, 0xFFFF, sum = 0
3014 10:01:55.760544 9, 0xFFFF, sum = 0
3015 10:01:55.763788 10, 0xFFFF, sum = 0
3016 10:01:55.764228 11, 0xFFFF, sum = 0
3017 10:01:55.767250 12, 0x0, sum = 1
3018 10:01:55.767689 13, 0x0, sum = 2
3019 10:01:55.770229 14, 0x0, sum = 3
3020 10:01:55.770667 15, 0x0, sum = 4
3021 10:01:55.771043 best_step = 13
3022 10:01:55.773468
3023 10:01:55.773920 ==
3024 10:01:55.776641 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 10:01:55.780165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 10:01:55.780600 ==
3027 10:01:55.780944 RX Vref Scan: 0
3028 10:01:55.781267
3029 10:01:55.783496 RX Vref 0 -> 0, step: 1
3030 10:01:55.783946
3031 10:01:55.786612 RX Delay -37 -> 252, step: 4
3032 10:01:55.790093 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3033 10:01:55.796888 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3034 10:01:55.799840 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3035 10:01:55.803231 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3036 10:01:55.806622 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3037 10:01:55.810147 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3038 10:01:55.816602 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3039 10:01:55.819787 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3040 10:01:55.823618 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3041 10:01:55.827000 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3042 10:01:55.829540 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3043 10:01:55.836325 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3044 10:01:55.840010 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3045 10:01:55.843039 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3046 10:01:55.846523 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3047 10:01:55.853338 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3048 10:01:55.853803 ==
3049 10:01:55.856629 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 10:01:55.860008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 10:01:55.860434 ==
3052 10:01:55.860805 DQS Delay:
3053 10:01:55.863092 DQS0 = 0, DQS1 = 0
3054 10:01:55.863571 DQM Delay:
3055 10:01:55.866282 DQM0 = 111, DQM1 = 101
3056 10:01:55.866872 DQ Delay:
3057 10:01:55.870113 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3058 10:01:55.872780 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3059 10:01:55.876460 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3060 10:01:55.879762 DQ12 =110, DQ13 =108, DQ14 =114, DQ15 =110
3061 10:01:55.880243
3062 10:01:55.880628
3063 10:01:55.889568 [DQSOSCAuto] RK1, (LSB)MR18= 0x15fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 401 ps
3064 10:01:55.892793 CH0 RK1: MR19=403, MR18=15FC
3065 10:01:55.896504 CH0_RK1: MR19=0x403, MR18=0x15FC, DQSOSC=401, MR23=63, INC=40, DEC=27
3066 10:01:55.899631 [RxdqsGatingPostProcess] freq 1200
3067 10:01:55.906043 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3068 10:01:55.909591 best DQS0 dly(2T, 0.5T) = (0, 11)
3069 10:01:55.912827 best DQS1 dly(2T, 0.5T) = (0, 12)
3070 10:01:55.916147 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3071 10:01:55.919315 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3072 10:01:55.922763 best DQS0 dly(2T, 0.5T) = (0, 11)
3073 10:01:55.925907 best DQS1 dly(2T, 0.5T) = (0, 11)
3074 10:01:55.929195 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3075 10:01:55.932711 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3076 10:01:55.933220 Pre-setting of DQS Precalculation
3077 10:01:55.939102 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3078 10:01:55.939655 ==
3079 10:01:55.942719 Dram Type= 6, Freq= 0, CH_1, rank 0
3080 10:01:55.945667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 10:01:55.946151 ==
3082 10:01:55.952598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3083 10:01:55.959315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3084 10:01:55.966866 [CA 0] Center 37 (7~67) winsize 61
3085 10:01:55.970128 [CA 1] Center 37 (7~68) winsize 62
3086 10:01:55.973390 [CA 2] Center 34 (4~64) winsize 61
3087 10:01:55.976692 [CA 3] Center 33 (3~64) winsize 62
3088 10:01:55.979810 [CA 4] Center 34 (4~64) winsize 61
3089 10:01:55.983418 [CA 5] Center 33 (3~63) winsize 61
3090 10:01:55.983860
3091 10:01:55.986707 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3092 10:01:55.987210
3093 10:01:55.989905 [CATrainingPosCal] consider 1 rank data
3094 10:01:55.993622 u2DelayCellTimex100 = 270/100 ps
3095 10:01:55.996925 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3096 10:01:56.002934 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3097 10:01:56.006424 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3098 10:01:56.009420 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3099 10:01:56.012874 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3100 10:01:56.016273 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3101 10:01:56.016706
3102 10:01:56.019750 CA PerBit enable=1, Macro0, CA PI delay=33
3103 10:01:56.020316
3104 10:01:56.023213 [CBTSetCACLKResult] CA Dly = 33
3105 10:01:56.026125 CS Dly: 5 (0~36)
3106 10:01:56.026571 ==
3107 10:01:56.029596 Dram Type= 6, Freq= 0, CH_1, rank 1
3108 10:01:56.032746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 10:01:56.033182 ==
3110 10:01:56.036389 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3111 10:01:56.042731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3112 10:01:56.052376 [CA 0] Center 37 (7~67) winsize 61
3113 10:01:56.055483 [CA 1] Center 37 (7~68) winsize 62
3114 10:01:56.058784 [CA 2] Center 34 (4~65) winsize 62
3115 10:01:56.062080 [CA 3] Center 33 (3~64) winsize 62
3116 10:01:56.065736 [CA 4] Center 34 (4~64) winsize 61
3117 10:01:56.068834 [CA 5] Center 32 (2~63) winsize 62
3118 10:01:56.069267
3119 10:01:56.072166 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3120 10:01:56.072601
3121 10:01:56.075317 [CATrainingPosCal] consider 2 rank data
3122 10:01:56.078469 u2DelayCellTimex100 = 270/100 ps
3123 10:01:56.081883 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3124 10:01:56.088784 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3125 10:01:56.091950 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3126 10:01:56.095305 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3127 10:01:56.098675 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3128 10:01:56.101791 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3129 10:01:56.102300
3130 10:01:56.105423 CA PerBit enable=1, Macro0, CA PI delay=33
3131 10:01:56.105967
3132 10:01:56.108648 [CBTSetCACLKResult] CA Dly = 33
3133 10:01:56.109079 CS Dly: 6 (0~39)
3134 10:01:56.111706
3135 10:01:56.115236 ----->DramcWriteLeveling(PI) begin...
3136 10:01:56.115676 ==
3137 10:01:56.118567 Dram Type= 6, Freq= 0, CH_1, rank 0
3138 10:01:56.121955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3139 10:01:56.122415 ==
3140 10:01:56.125029 Write leveling (Byte 0): 26 => 26
3141 10:01:56.128865 Write leveling (Byte 1): 31 => 31
3142 10:01:56.131546 DramcWriteLeveling(PI) end<-----
3143 10:01:56.131978
3144 10:01:56.132355 ==
3145 10:01:56.135111 Dram Type= 6, Freq= 0, CH_1, rank 0
3146 10:01:56.138113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3147 10:01:56.138549 ==
3148 10:01:56.141666 [Gating] SW mode calibration
3149 10:01:56.148455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3150 10:01:56.154912 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3151 10:01:56.158073 0 15 0 | B1->B0 | 3232 2727 | 0 1 | (0 0) (0 0)
3152 10:01:56.161706 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 10:01:56.168135 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 10:01:56.171095 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3155 10:01:56.174725 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3156 10:01:56.181184 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3157 10:01:56.184528 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3158 10:01:56.187528 0 15 28 | B1->B0 | 2929 2a2a | 0 0 | (1 0) (0 0)
3159 10:01:56.194740 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 10:01:56.197895 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 10:01:56.200962 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 10:01:56.207850 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3163 10:01:56.210744 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3164 10:01:56.214493 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3165 10:01:56.220754 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3166 10:01:56.224115 1 0 28 | B1->B0 | 4242 3f3f | 0 0 | (0 0) (0 0)
3167 10:01:56.227617 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 10:01:56.234387 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 10:01:56.237671 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 10:01:56.240805 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 10:01:56.247119 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 10:01:56.250806 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 10:01:56.253952 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 10:01:56.260566 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3175 10:01:56.264183 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3176 10:01:56.267277 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 10:01:56.273983 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 10:01:56.277299 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 10:01:56.280577 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 10:01:56.287054 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 10:01:56.290186 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 10:01:56.293978 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 10:01:56.300191 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 10:01:56.303760 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 10:01:56.306907 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 10:01:56.313329 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 10:01:56.316650 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 10:01:56.320277 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 10:01:56.323555 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 10:01:56.330035 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3191 10:01:56.333576 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 10:01:56.336563 Total UI for P1: 0, mck2ui 16
3193 10:01:56.340191 best dqsien dly found for B0: ( 1, 3, 28)
3194 10:01:56.343612 Total UI for P1: 0, mck2ui 16
3195 10:01:56.346739 best dqsien dly found for B1: ( 1, 3, 28)
3196 10:01:56.350165 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3197 10:01:56.353684 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3198 10:01:56.354206
3199 10:01:56.356971 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3200 10:01:56.360475 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3201 10:01:56.363265 [Gating] SW calibration Done
3202 10:01:56.363753 ==
3203 10:01:56.366930 Dram Type= 6, Freq= 0, CH_1, rank 0
3204 10:01:56.373359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3205 10:01:56.373937 ==
3206 10:01:56.374352 RX Vref Scan: 0
3207 10:01:56.374756
3208 10:01:56.376960 RX Vref 0 -> 0, step: 1
3209 10:01:56.377419
3210 10:01:56.380268 RX Delay -40 -> 252, step: 8
3211 10:01:56.383106 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3212 10:01:56.387077 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3213 10:01:56.390057 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3214 10:01:56.393158 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3215 10:01:56.399557 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3216 10:01:56.403218 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3217 10:01:56.406486 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3218 10:01:56.409555 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3219 10:01:56.412909 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3220 10:01:56.419916 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3221 10:01:56.422736 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3222 10:01:56.426123 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3223 10:01:56.429566 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3224 10:01:56.436059 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3225 10:01:56.439557 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3226 10:01:56.442545 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3227 10:01:56.443113 ==
3228 10:01:56.445916 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 10:01:56.449398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 10:01:56.449849 ==
3231 10:01:56.452742 DQS Delay:
3232 10:01:56.453349 DQS0 = 0, DQS1 = 0
3233 10:01:56.455916 DQM Delay:
3234 10:01:56.456365 DQM0 = 114, DQM1 = 106
3235 10:01:56.456744 DQ Delay:
3236 10:01:56.459301 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3237 10:01:56.466424 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3238 10:01:56.469316 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3239 10:01:56.472458 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3240 10:01:56.472905
3241 10:01:56.473262
3242 10:01:56.473612 ==
3243 10:01:56.475927 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 10:01:56.479224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 10:01:56.479675 ==
3246 10:01:56.480049
3247 10:01:56.480393
3248 10:01:56.482861 TX Vref Scan disable
3249 10:01:56.485731 == TX Byte 0 ==
3250 10:01:56.489154 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3251 10:01:56.492220 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3252 10:01:56.496049 == TX Byte 1 ==
3253 10:01:56.499077 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3254 10:01:56.502261 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3255 10:01:56.502775 ==
3256 10:01:56.505681 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 10:01:56.508889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 10:01:56.512058 ==
3259 10:01:56.522501 TX Vref=22, minBit 2, minWin=25, winSum=415
3260 10:01:56.525735 TX Vref=24, minBit 8, minWin=25, winSum=422
3261 10:01:56.528951 TX Vref=26, minBit 0, minWin=26, winSum=425
3262 10:01:56.532505 TX Vref=28, minBit 1, minWin=26, winSum=432
3263 10:01:56.535468 TX Vref=30, minBit 1, minWin=26, winSum=430
3264 10:01:56.542604 TX Vref=32, minBit 1, minWin=26, winSum=427
3265 10:01:56.545680 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 28
3266 10:01:56.546262
3267 10:01:56.548619 Final TX Range 1 Vref 28
3268 10:01:56.549074
3269 10:01:56.549600 ==
3270 10:01:56.552191 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 10:01:56.555341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 10:01:56.558677 ==
3273 10:01:56.559207
3274 10:01:56.559786
3275 10:01:56.560338 TX Vref Scan disable
3276 10:01:56.562276 == TX Byte 0 ==
3277 10:01:56.565794 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3278 10:01:56.572158 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3279 10:01:56.572764 == TX Byte 1 ==
3280 10:01:56.575245 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3281 10:01:56.582200 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3282 10:01:56.582653
3283 10:01:56.583115 [DATLAT]
3284 10:01:56.583474 Freq=1200, CH1 RK0
3285 10:01:56.583831
3286 10:01:56.585501 DATLAT Default: 0xd
3287 10:01:56.588445 0, 0xFFFF, sum = 0
3288 10:01:56.588902 1, 0xFFFF, sum = 0
3289 10:01:56.591793 2, 0xFFFF, sum = 0
3290 10:01:56.592248 3, 0xFFFF, sum = 0
3291 10:01:56.595178 4, 0xFFFF, sum = 0
3292 10:01:56.595770 5, 0xFFFF, sum = 0
3293 10:01:56.598876 6, 0xFFFF, sum = 0
3294 10:01:56.599431 7, 0xFFFF, sum = 0
3295 10:01:56.601895 8, 0xFFFF, sum = 0
3296 10:01:56.602589 9, 0xFFFF, sum = 0
3297 10:01:56.605509 10, 0xFFFF, sum = 0
3298 10:01:56.606064 11, 0xFFFF, sum = 0
3299 10:01:56.608823 12, 0x0, sum = 1
3300 10:01:56.609307 13, 0x0, sum = 2
3301 10:01:56.612282 14, 0x0, sum = 3
3302 10:01:56.612737 15, 0x0, sum = 4
3303 10:01:56.615217 best_step = 13
3304 10:01:56.615669
3305 10:01:56.616032 ==
3306 10:01:56.618495 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 10:01:56.621603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 10:01:56.622041 ==
3309 10:01:56.622421 RX Vref Scan: 1
3310 10:01:56.625524
3311 10:01:56.625966 Set Vref Range= 32 -> 127
3312 10:01:56.626334
3313 10:01:56.628571 RX Vref 32 -> 127, step: 1
3314 10:01:56.628928
3315 10:01:56.631755 RX Delay -21 -> 252, step: 4
3316 10:01:56.632059
3317 10:01:56.634884 Set Vref, RX VrefLevel [Byte0]: 32
3318 10:01:56.637928 [Byte1]: 32
3319 10:01:56.638176
3320 10:01:56.641628 Set Vref, RX VrefLevel [Byte0]: 33
3321 10:01:56.644578 [Byte1]: 33
3322 10:01:56.648496
3323 10:01:56.648725 Set Vref, RX VrefLevel [Byte0]: 34
3324 10:01:56.651942 [Byte1]: 34
3325 10:01:56.656367
3326 10:01:56.656660 Set Vref, RX VrefLevel [Byte0]: 35
3327 10:01:56.659920 [Byte1]: 35
3328 10:01:56.664561
3329 10:01:56.664790 Set Vref, RX VrefLevel [Byte0]: 36
3330 10:01:56.668120 [Byte1]: 36
3331 10:01:56.672105
3332 10:01:56.672335 Set Vref, RX VrefLevel [Byte0]: 37
3333 10:01:56.675332 [Byte1]: 37
3334 10:01:56.680156
3335 10:01:56.680390 Set Vref, RX VrefLevel [Byte0]: 38
3336 10:01:56.683236 [Byte1]: 38
3337 10:01:56.688074
3338 10:01:56.688418 Set Vref, RX VrefLevel [Byte0]: 39
3339 10:01:56.691594 [Byte1]: 39
3340 10:01:56.696357
3341 10:01:56.696796 Set Vref, RX VrefLevel [Byte0]: 40
3342 10:01:56.699564 [Byte1]: 40
3343 10:01:56.704195
3344 10:01:56.704618 Set Vref, RX VrefLevel [Byte0]: 41
3345 10:01:56.707377 [Byte1]: 41
3346 10:01:56.712166
3347 10:01:56.712586 Set Vref, RX VrefLevel [Byte0]: 42
3348 10:01:56.715380 [Byte1]: 42
3349 10:01:56.720207
3350 10:01:56.720632 Set Vref, RX VrefLevel [Byte0]: 43
3351 10:01:56.723363 [Byte1]: 43
3352 10:01:56.727665
3353 10:01:56.730900 Set Vref, RX VrefLevel [Byte0]: 44
3354 10:01:56.734569 [Byte1]: 44
3355 10:01:56.735106
3356 10:01:56.737619 Set Vref, RX VrefLevel [Byte0]: 45
3357 10:01:56.741387 [Byte1]: 45
3358 10:01:56.741811
3359 10:01:56.744406 Set Vref, RX VrefLevel [Byte0]: 46
3360 10:01:56.747374 [Byte1]: 46
3361 10:01:56.751781
3362 10:01:56.752202 Set Vref, RX VrefLevel [Byte0]: 47
3363 10:01:56.754779 [Byte1]: 47
3364 10:01:56.759613
3365 10:01:56.760035 Set Vref, RX VrefLevel [Byte0]: 48
3366 10:01:56.762667 [Byte1]: 48
3367 10:01:56.767627
3368 10:01:56.768051 Set Vref, RX VrefLevel [Byte0]: 49
3369 10:01:56.771093 [Byte1]: 49
3370 10:01:56.775544
3371 10:01:56.775979 Set Vref, RX VrefLevel [Byte0]: 50
3372 10:01:56.778570 [Byte1]: 50
3373 10:01:56.783192
3374 10:01:56.783627 Set Vref, RX VrefLevel [Byte0]: 51
3375 10:01:56.786521 [Byte1]: 51
3376 10:01:56.791130
3377 10:01:56.791675 Set Vref, RX VrefLevel [Byte0]: 52
3378 10:01:56.795010 [Byte1]: 52
3379 10:01:56.799152
3380 10:01:56.799454 Set Vref, RX VrefLevel [Byte0]: 53
3381 10:01:56.802309 [Byte1]: 53
3382 10:01:56.807171
3383 10:01:56.807470 Set Vref, RX VrefLevel [Byte0]: 54
3384 10:01:56.810124 [Byte1]: 54
3385 10:01:56.814946
3386 10:01:56.815124 Set Vref, RX VrefLevel [Byte0]: 55
3387 10:01:56.818215 [Byte1]: 55
3388 10:01:56.822324
3389 10:01:56.822408 Set Vref, RX VrefLevel [Byte0]: 56
3390 10:01:56.826002 [Byte1]: 56
3391 10:01:56.830441
3392 10:01:56.830546 Set Vref, RX VrefLevel [Byte0]: 57
3393 10:01:56.833980 [Byte1]: 57
3394 10:01:56.838208
3395 10:01:56.838351 Set Vref, RX VrefLevel [Byte0]: 58
3396 10:01:56.841844 [Byte1]: 58
3397 10:01:56.846378
3398 10:01:56.846452 Set Vref, RX VrefLevel [Byte0]: 59
3399 10:01:56.849845 [Byte1]: 59
3400 10:01:56.854676
3401 10:01:56.854785 Set Vref, RX VrefLevel [Byte0]: 60
3402 10:01:56.857725 [Byte1]: 60
3403 10:01:56.862287
3404 10:01:56.862370 Set Vref, RX VrefLevel [Byte0]: 61
3405 10:01:56.865365 [Byte1]: 61
3406 10:01:56.870257
3407 10:01:56.870333 Set Vref, RX VrefLevel [Byte0]: 62
3408 10:01:56.873743 [Byte1]: 62
3409 10:01:56.877847
3410 10:01:56.877928 Set Vref, RX VrefLevel [Byte0]: 63
3411 10:01:56.881554 [Byte1]: 63
3412 10:01:56.886147
3413 10:01:56.886244 Set Vref, RX VrefLevel [Byte0]: 64
3414 10:01:56.889162 [Byte1]: 64
3415 10:01:56.893952
3416 10:01:56.894047 Set Vref, RX VrefLevel [Byte0]: 65
3417 10:01:56.896965 [Byte1]: 65
3418 10:01:56.901644
3419 10:01:56.901761 Final RX Vref Byte 0 = 55 to rank0
3420 10:01:56.905120 Final RX Vref Byte 1 = 51 to rank0
3421 10:01:56.908404 Final RX Vref Byte 0 = 55 to rank1
3422 10:01:56.912030 Final RX Vref Byte 1 = 51 to rank1==
3423 10:01:56.914933 Dram Type= 6, Freq= 0, CH_1, rank 0
3424 10:01:56.921611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 10:01:56.921697 ==
3426 10:01:56.921765 DQS Delay:
3427 10:01:56.921827 DQS0 = 0, DQS1 = 0
3428 10:01:56.925327 DQM Delay:
3429 10:01:56.925438 DQM0 = 114, DQM1 = 107
3430 10:01:56.928627 DQ Delay:
3431 10:01:56.931828 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =112
3432 10:01:56.935097 DQ4 =112, DQ5 =122, DQ6 =124, DQ7 =112
3433 10:01:56.938209 DQ8 =94, DQ9 =100, DQ10 =104, DQ11 =102
3434 10:01:56.941505 DQ12 =114, DQ13 =114, DQ14 =114, DQ15 =114
3435 10:01:56.941590
3436 10:01:56.941656
3437 10:01:56.951217 [DQSOSCAuto] RK0, (LSB)MR18= 0xf2f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
3438 10:01:56.951315 CH1 RK0: MR19=303, MR18=F2F9
3439 10:01:56.958103 CH1_RK0: MR19=0x303, MR18=0xF2F9, DQSOSC=412, MR23=63, INC=38, DEC=25
3440 10:01:56.958217
3441 10:01:56.961590 ----->DramcWriteLeveling(PI) begin...
3442 10:01:56.961743 ==
3443 10:01:56.964516 Dram Type= 6, Freq= 0, CH_1, rank 1
3444 10:01:56.971270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3445 10:01:56.971397 ==
3446 10:01:56.974861 Write leveling (Byte 0): 25 => 25
3447 10:01:56.977786 Write leveling (Byte 1): 30 => 30
3448 10:01:56.977945 DramcWriteLeveling(PI) end<-----
3449 10:01:56.978071
3450 10:01:56.981422 ==
3451 10:01:56.984813 Dram Type= 6, Freq= 0, CH_1, rank 1
3452 10:01:56.988017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3453 10:01:56.988226 ==
3454 10:01:56.991400 [Gating] SW mode calibration
3455 10:01:56.998296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3456 10:01:57.001105 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3457 10:01:57.007907 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3458 10:01:57.011017 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 10:01:57.014583 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 10:01:57.021154 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 10:01:57.024581 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 10:01:57.027748 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 10:01:57.034135 0 15 24 | B1->B0 | 3333 2929 | 0 0 | (0 0) (1 0)
3464 10:01:57.037851 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
3465 10:01:57.040918 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 10:01:57.047815 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 10:01:57.050996 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 10:01:57.054142 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 10:01:57.060854 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 10:01:57.064138 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3471 10:01:57.067197 1 0 24 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
3472 10:01:57.074101 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 10:01:57.076926 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 10:01:57.080345 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 10:01:57.087357 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 10:01:57.090297 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 10:01:57.093927 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 10:01:57.100126 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3479 10:01:57.103899 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3480 10:01:57.106763 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3481 10:01:57.113201 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 10:01:57.116855 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 10:01:57.120252 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 10:01:57.126599 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 10:01:57.130090 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 10:01:57.133364 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 10:01:57.139793 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 10:01:57.143482 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 10:01:57.146589 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 10:01:57.153120 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 10:01:57.156843 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 10:01:57.160132 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 10:01:57.166450 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 10:01:57.169751 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 10:01:57.173374 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3496 10:01:57.180038 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3497 10:01:57.180154 Total UI for P1: 0, mck2ui 16
3498 10:01:57.183157 best dqsien dly found for B0: ( 1, 3, 24)
3499 10:01:57.189716 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 10:01:57.192885 Total UI for P1: 0, mck2ui 16
3501 10:01:57.196705 best dqsien dly found for B1: ( 1, 3, 26)
3502 10:01:57.199659 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3503 10:01:57.202774 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3504 10:01:57.202940
3505 10:01:57.206106 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3506 10:01:57.209528 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3507 10:01:57.212578 [Gating] SW calibration Done
3508 10:01:57.212738 ==
3509 10:01:57.216595 Dram Type= 6, Freq= 0, CH_1, rank 1
3510 10:01:57.219333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3511 10:01:57.219493 ==
3512 10:01:57.222953 RX Vref Scan: 0
3513 10:01:57.223110
3514 10:01:57.225780 RX Vref 0 -> 0, step: 1
3515 10:01:57.225865
3516 10:01:57.225934 RX Delay -40 -> 252, step: 8
3517 10:01:57.232536 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3518 10:01:57.235855 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3519 10:01:57.239032 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3520 10:01:57.242620 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3521 10:01:57.245907 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3522 10:01:57.252572 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3523 10:01:57.255352 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3524 10:01:57.259136 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3525 10:01:57.262306 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3526 10:01:57.265501 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3527 10:01:57.271972 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3528 10:01:57.275398 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3529 10:01:57.278816 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3530 10:01:57.282186 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3531 10:01:57.288277 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3532 10:01:57.291700 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3533 10:01:57.291785 ==
3534 10:01:57.295255 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 10:01:57.298202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 10:01:57.298287 ==
3537 10:01:57.301595 DQS Delay:
3538 10:01:57.301679 DQS0 = 0, DQS1 = 0
3539 10:01:57.301747 DQM Delay:
3540 10:01:57.305072 DQM0 = 110, DQM1 = 108
3541 10:01:57.305155 DQ Delay:
3542 10:01:57.307990 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3543 10:01:57.311617 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3544 10:01:57.314763 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3545 10:01:57.321558 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =111
3546 10:01:57.321643
3547 10:01:57.321710
3548 10:01:57.321772 ==
3549 10:01:57.324818 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 10:01:57.327981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 10:01:57.328066 ==
3552 10:01:57.328133
3553 10:01:57.328196
3554 10:01:57.331054 TX Vref Scan disable
3555 10:01:57.331144 == TX Byte 0 ==
3556 10:01:57.337643 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3557 10:01:57.341292 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3558 10:01:57.344504 == TX Byte 1 ==
3559 10:01:57.347753 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3560 10:01:57.351019 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3561 10:01:57.351145 ==
3562 10:01:57.354087 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 10:01:57.357746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 10:01:57.357831 ==
3565 10:01:57.370967 TX Vref=22, minBit 1, minWin=26, winSum=428
3566 10:01:57.374563 TX Vref=24, minBit 1, minWin=26, winSum=429
3567 10:01:57.377750 TX Vref=26, minBit 8, minWin=26, winSum=436
3568 10:01:57.380802 TX Vref=28, minBit 1, minWin=26, winSum=437
3569 10:01:57.383895 TX Vref=30, minBit 0, minWin=26, winSum=438
3570 10:01:57.390646 TX Vref=32, minBit 8, minWin=26, winSum=434
3571 10:01:57.393739 [TxChooseVref] Worse bit 0, Min win 26, Win sum 438, Final Vref 30
3572 10:01:57.393823
3573 10:01:57.397233 Final TX Range 1 Vref 30
3574 10:01:57.397317
3575 10:01:57.397384 ==
3576 10:01:57.400594 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 10:01:57.403793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 10:01:57.406709 ==
3579 10:01:57.406793
3580 10:01:57.406897
3581 10:01:57.406959 TX Vref Scan disable
3582 10:01:57.411225 == TX Byte 0 ==
3583 10:01:57.413687 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3584 10:01:57.420580 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3585 10:01:57.420664 == TX Byte 1 ==
3586 10:01:57.423905 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3587 10:01:57.430406 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3588 10:01:57.430490
3589 10:01:57.430557 [DATLAT]
3590 10:01:57.430620 Freq=1200, CH1 RK1
3591 10:01:57.430681
3592 10:01:57.433473 DATLAT Default: 0xd
3593 10:01:57.436934 0, 0xFFFF, sum = 0
3594 10:01:57.437019 1, 0xFFFF, sum = 0
3595 10:01:57.440311 2, 0xFFFF, sum = 0
3596 10:01:57.440396 3, 0xFFFF, sum = 0
3597 10:01:57.443834 4, 0xFFFF, sum = 0
3598 10:01:57.443920 5, 0xFFFF, sum = 0
3599 10:01:57.446915 6, 0xFFFF, sum = 0
3600 10:01:57.447000 7, 0xFFFF, sum = 0
3601 10:01:57.450233 8, 0xFFFF, sum = 0
3602 10:01:57.450318 9, 0xFFFF, sum = 0
3603 10:01:57.453182 10, 0xFFFF, sum = 0
3604 10:01:57.453267 11, 0xFFFF, sum = 0
3605 10:01:57.456812 12, 0x0, sum = 1
3606 10:01:57.456897 13, 0x0, sum = 2
3607 10:01:57.460093 14, 0x0, sum = 3
3608 10:01:57.460178 15, 0x0, sum = 4
3609 10:01:57.463580 best_step = 13
3610 10:01:57.463664
3611 10:01:57.463731 ==
3612 10:01:57.466589 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 10:01:57.469786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 10:01:57.469871 ==
3615 10:01:57.472969 RX Vref Scan: 0
3616 10:01:57.473053
3617 10:01:57.473120 RX Vref 0 -> 0, step: 1
3618 10:01:57.473182
3619 10:01:57.476273 RX Delay -21 -> 252, step: 4
3620 10:01:57.482934 iDelay=195, Bit 0, Center 112 (39 ~ 186) 148
3621 10:01:57.486074 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3622 10:01:57.489623 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3623 10:01:57.492834 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3624 10:01:57.499652 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3625 10:01:57.502868 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3626 10:01:57.505956 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3627 10:01:57.509338 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3628 10:01:57.512892 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3629 10:01:57.519315 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3630 10:01:57.522364 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3631 10:01:57.525765 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3632 10:01:57.528833 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3633 10:01:57.532139 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3634 10:01:57.538986 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3635 10:01:57.542335 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3636 10:01:57.542408 ==
3637 10:01:57.545308 Dram Type= 6, Freq= 0, CH_1, rank 1
3638 10:01:57.549262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3639 10:01:57.549339 ==
3640 10:01:57.552218 DQS Delay:
3641 10:01:57.552303 DQS0 = 0, DQS1 = 0
3642 10:01:57.552368 DQM Delay:
3643 10:01:57.555427 DQM0 = 110, DQM1 = 109
3644 10:01:57.555496 DQ Delay:
3645 10:01:57.558639 DQ0 =112, DQ1 =108, DQ2 =100, DQ3 =108
3646 10:01:57.561836 DQ4 =110, DQ5 =120, DQ6 =120, DQ7 =108
3647 10:01:57.568719 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =104
3648 10:01:57.571894 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3649 10:01:57.571972
3650 10:01:57.572039
3651 10:01:57.578355 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb0b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3652 10:01:57.581566 CH1 RK1: MR19=304, MR18=FB0B
3653 10:01:57.588303 CH1_RK1: MR19=0x304, MR18=0xFB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3654 10:01:57.591510 [RxdqsGatingPostProcess] freq 1200
3655 10:01:57.598429 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3656 10:01:57.598507 best DQS0 dly(2T, 0.5T) = (0, 11)
3657 10:01:57.601532 best DQS1 dly(2T, 0.5T) = (0, 11)
3658 10:01:57.604876 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3659 10:01:57.608052 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3660 10:01:57.611585 best DQS0 dly(2T, 0.5T) = (0, 11)
3661 10:01:57.614815 best DQS1 dly(2T, 0.5T) = (0, 11)
3662 10:01:57.617911 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3663 10:01:57.621329 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3664 10:01:57.625041 Pre-setting of DQS Precalculation
3665 10:01:57.631073 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3666 10:01:57.637967 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3667 10:01:57.644207 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3668 10:01:57.644286
3669 10:01:57.644353
3670 10:01:57.647854 [Calibration Summary] 2400 Mbps
3671 10:01:57.647938 CH 0, Rank 0
3672 10:01:57.650845 SW Impedance : PASS
3673 10:01:57.654313 DUTY Scan : NO K
3674 10:01:57.654427 ZQ Calibration : PASS
3675 10:01:57.657368 Jitter Meter : NO K
3676 10:01:57.660905 CBT Training : PASS
3677 10:01:57.660988 Write leveling : PASS
3678 10:01:57.664057 RX DQS gating : PASS
3679 10:01:57.667508 RX DQ/DQS(RDDQC) : PASS
3680 10:01:57.667592 TX DQ/DQS : PASS
3681 10:01:57.670923 RX DATLAT : PASS
3682 10:01:57.674126 RX DQ/DQS(Engine): PASS
3683 10:01:57.674209 TX OE : NO K
3684 10:01:57.674277 All Pass.
3685 10:01:57.677377
3686 10:01:57.677460 CH 0, Rank 1
3687 10:01:57.680628 SW Impedance : PASS
3688 10:01:57.680712 DUTY Scan : NO K
3689 10:01:57.683879 ZQ Calibration : PASS
3690 10:01:57.687179 Jitter Meter : NO K
3691 10:01:57.687265 CBT Training : PASS
3692 10:01:57.690440 Write leveling : PASS
3693 10:01:57.690530 RX DQS gating : PASS
3694 10:01:57.693807 RX DQ/DQS(RDDQC) : PASS
3695 10:01:57.696767 TX DQ/DQS : PASS
3696 10:01:57.696853 RX DATLAT : PASS
3697 10:01:57.700378 RX DQ/DQS(Engine): PASS
3698 10:01:57.703463 TX OE : NO K
3699 10:01:57.703548 All Pass.
3700 10:01:57.703651
3701 10:01:57.703752 CH 1, Rank 0
3702 10:01:57.706523 SW Impedance : PASS
3703 10:01:57.710240 DUTY Scan : NO K
3704 10:01:57.710344 ZQ Calibration : PASS
3705 10:01:57.713583 Jitter Meter : NO K
3706 10:01:57.716997 CBT Training : PASS
3707 10:01:57.717076 Write leveling : PASS
3708 10:01:57.719865 RX DQS gating : PASS
3709 10:01:57.723258 RX DQ/DQS(RDDQC) : PASS
3710 10:01:57.723330 TX DQ/DQS : PASS
3711 10:01:57.726711 RX DATLAT : PASS
3712 10:01:57.730117 RX DQ/DQS(Engine): PASS
3713 10:01:57.730202 TX OE : NO K
3714 10:01:57.733038 All Pass.
3715 10:01:57.733122
3716 10:01:57.733189 CH 1, Rank 1
3717 10:01:57.736577 SW Impedance : PASS
3718 10:01:57.736660 DUTY Scan : NO K
3719 10:01:57.739777 ZQ Calibration : PASS
3720 10:01:57.743299 Jitter Meter : NO K
3721 10:01:57.743383 CBT Training : PASS
3722 10:01:57.746188 Write leveling : PASS
3723 10:01:57.749843 RX DQS gating : PASS
3724 10:01:57.749939 RX DQ/DQS(RDDQC) : PASS
3725 10:01:57.753225 TX DQ/DQS : PASS
3726 10:01:57.756296 RX DATLAT : PASS
3727 10:01:57.756404 RX DQ/DQS(Engine): PASS
3728 10:01:57.759442 TX OE : NO K
3729 10:01:57.759557 All Pass.
3730 10:01:57.759649
3731 10:01:57.762938 DramC Write-DBI off
3732 10:01:57.766212 PER_BANK_REFRESH: Hybrid Mode
3733 10:01:57.766294 TX_TRACKING: ON
3734 10:01:57.775946 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3735 10:01:57.779114 [FAST_K] Save calibration result to emmc
3736 10:01:57.782342 dramc_set_vcore_voltage set vcore to 650000
3737 10:01:57.786115 Read voltage for 600, 5
3738 10:01:57.786194 Vio18 = 0
3739 10:01:57.786284 Vcore = 650000
3740 10:01:57.789279 Vdram = 0
3741 10:01:57.789381 Vddq = 0
3742 10:01:57.789474 Vmddr = 0
3743 10:01:57.796010 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3744 10:01:57.799195 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3745 10:01:57.802534 MEM_TYPE=3, freq_sel=19
3746 10:01:57.805618 sv_algorithm_assistance_LP4_1600
3747 10:01:57.808885 ============ PULL DRAM RESETB DOWN ============
3748 10:01:57.812507 ========== PULL DRAM RESETB DOWN end =========
3749 10:01:57.818974 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3750 10:01:57.822177 ===================================
3751 10:01:57.825627 LPDDR4 DRAM CONFIGURATION
3752 10:01:57.828742 ===================================
3753 10:01:57.828848 EX_ROW_EN[0] = 0x0
3754 10:01:57.831971 EX_ROW_EN[1] = 0x0
3755 10:01:57.832081 LP4Y_EN = 0x0
3756 10:01:57.835595 WORK_FSP = 0x0
3757 10:01:57.835702 WL = 0x2
3758 10:01:57.838726 RL = 0x2
3759 10:01:57.838850 BL = 0x2
3760 10:01:57.841971 RPST = 0x0
3761 10:01:57.842083 RD_PRE = 0x0
3762 10:01:57.845285 WR_PRE = 0x1
3763 10:01:57.845394 WR_PST = 0x0
3764 10:01:57.848381 DBI_WR = 0x0
3765 10:01:57.851670 DBI_RD = 0x0
3766 10:01:57.851751 OTF = 0x1
3767 10:01:57.855285 ===================================
3768 10:01:57.858467 ===================================
3769 10:01:57.858575 ANA top config
3770 10:01:57.861523 ===================================
3771 10:01:57.865262 DLL_ASYNC_EN = 0
3772 10:01:57.868302 ALL_SLAVE_EN = 1
3773 10:01:57.871678 NEW_RANK_MODE = 1
3774 10:01:57.874918 DLL_IDLE_MODE = 1
3775 10:01:57.874998 LP45_APHY_COMB_EN = 1
3776 10:01:57.878170 TX_ODT_DIS = 1
3777 10:01:57.881337 NEW_8X_MODE = 1
3778 10:01:57.884443 ===================================
3779 10:01:57.888235 ===================================
3780 10:01:57.891543 data_rate = 1200
3781 10:01:57.894823 CKR = 1
3782 10:01:57.897805 DQ_P2S_RATIO = 8
3783 10:01:57.901238 ===================================
3784 10:01:57.901317 CA_P2S_RATIO = 8
3785 10:01:57.904405 DQ_CA_OPEN = 0
3786 10:01:57.907733 DQ_SEMI_OPEN = 0
3787 10:01:57.910952 CA_SEMI_OPEN = 0
3788 10:01:57.914696 CA_FULL_RATE = 0
3789 10:01:57.917930 DQ_CKDIV4_EN = 1
3790 10:01:57.918003 CA_CKDIV4_EN = 1
3791 10:01:57.921185 CA_PREDIV_EN = 0
3792 10:01:57.924557 PH8_DLY = 0
3793 10:01:57.927827 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3794 10:01:57.930675 DQ_AAMCK_DIV = 4
3795 10:01:57.934077 CA_AAMCK_DIV = 4
3796 10:01:57.934154 CA_ADMCK_DIV = 4
3797 10:01:57.937247 DQ_TRACK_CA_EN = 0
3798 10:01:57.941252 CA_PICK = 600
3799 10:01:57.944135 CA_MCKIO = 600
3800 10:01:57.947695 MCKIO_SEMI = 0
3801 10:01:57.950435 PLL_FREQ = 2288
3802 10:01:57.954044 DQ_UI_PI_RATIO = 32
3803 10:01:57.954128 CA_UI_PI_RATIO = 0
3804 10:01:57.956902 ===================================
3805 10:01:57.960330 ===================================
3806 10:01:57.963506 memory_type:LPDDR4
3807 10:01:57.967148 GP_NUM : 10
3808 10:01:57.967234 SRAM_EN : 1
3809 10:01:57.970214 MD32_EN : 0
3810 10:01:57.973694 ===================================
3811 10:01:57.977116 [ANA_INIT] >>>>>>>>>>>>>>
3812 10:01:57.980456 <<<<<< [CONFIGURE PHASE]: ANA_TX
3813 10:01:57.983553 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3814 10:01:57.986937 ===================================
3815 10:01:57.990029 data_rate = 1200,PCW = 0X5800
3816 10:01:57.993236 ===================================
3817 10:01:57.996482 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3818 10:01:57.999752 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3819 10:01:58.006451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3820 10:01:58.010200 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3821 10:01:58.013419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3822 10:01:58.016719 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3823 10:01:58.019674 [ANA_INIT] flow start
3824 10:01:58.022800 [ANA_INIT] PLL >>>>>>>>
3825 10:01:58.022910 [ANA_INIT] PLL <<<<<<<<
3826 10:01:58.026030 [ANA_INIT] MIDPI >>>>>>>>
3827 10:01:58.029252 [ANA_INIT] MIDPI <<<<<<<<
3828 10:01:58.032910 [ANA_INIT] DLL >>>>>>>>
3829 10:01:58.032995 [ANA_INIT] flow end
3830 10:01:58.036086 ============ LP4 DIFF to SE enter ============
3831 10:01:58.042810 ============ LP4 DIFF to SE exit ============
3832 10:01:58.042906 [ANA_INIT] <<<<<<<<<<<<<
3833 10:01:58.046138 [Flow] Enable top DCM control >>>>>
3834 10:01:58.049363 [Flow] Enable top DCM control <<<<<
3835 10:01:58.052483 Enable DLL master slave shuffle
3836 10:01:58.059370 ==============================================================
3837 10:01:58.059454 Gating Mode config
3838 10:01:58.065885 ==============================================================
3839 10:01:58.069095 Config description:
3840 10:01:58.079104 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3841 10:01:58.085713 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3842 10:01:58.088921 SELPH_MODE 0: By rank 1: By Phase
3843 10:01:58.095280 ==============================================================
3844 10:01:58.098519 GAT_TRACK_EN = 1
3845 10:01:58.101724 RX_GATING_MODE = 2
3846 10:01:58.105027 RX_GATING_TRACK_MODE = 2
3847 10:01:58.105111 SELPH_MODE = 1
3848 10:01:58.108526 PICG_EARLY_EN = 1
3849 10:01:58.112085 VALID_LAT_VALUE = 1
3850 10:01:58.118206 ==============================================================
3851 10:01:58.121728 Enter into Gating configuration >>>>
3852 10:01:58.124933 Exit from Gating configuration <<<<
3853 10:01:58.128316 Enter into DVFS_PRE_config >>>>>
3854 10:01:58.138461 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3855 10:01:58.141593 Exit from DVFS_PRE_config <<<<<
3856 10:01:58.144973 Enter into PICG configuration >>>>
3857 10:01:58.147935 Exit from PICG configuration <<<<
3858 10:01:58.151319 [RX_INPUT] configuration >>>>>
3859 10:01:58.154329 [RX_INPUT] configuration <<<<<
3860 10:01:58.158044 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3861 10:01:58.164536 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3862 10:01:58.171257 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3863 10:01:58.177613 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3864 10:01:58.183803 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3865 10:01:58.190767 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3866 10:01:58.194012 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3867 10:01:58.197215 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3868 10:01:58.200407 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3869 10:01:58.207376 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3870 10:01:58.210756 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3871 10:01:58.213523 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3872 10:01:58.217238 ===================================
3873 10:01:58.220442 LPDDR4 DRAM CONFIGURATION
3874 10:01:58.223477 ===================================
3875 10:01:58.223550 EX_ROW_EN[0] = 0x0
3876 10:01:58.226836 EX_ROW_EN[1] = 0x0
3877 10:01:58.230224 LP4Y_EN = 0x0
3878 10:01:58.230299 WORK_FSP = 0x0
3879 10:01:58.233371 WL = 0x2
3880 10:01:58.233444 RL = 0x2
3881 10:01:58.236866 BL = 0x2
3882 10:01:58.236938 RPST = 0x0
3883 10:01:58.240112 RD_PRE = 0x0
3884 10:01:58.240184 WR_PRE = 0x1
3885 10:01:58.243337 WR_PST = 0x0
3886 10:01:58.243408 DBI_WR = 0x0
3887 10:01:58.246802 DBI_RD = 0x0
3888 10:01:58.246928 OTF = 0x1
3889 10:01:58.250063 ===================================
3890 10:01:58.256443 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3891 10:01:58.259562 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3892 10:01:58.263200 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3893 10:01:58.266113 ===================================
3894 10:01:58.269671 LPDDR4 DRAM CONFIGURATION
3895 10:01:58.272648 ===================================
3896 10:01:58.276285 EX_ROW_EN[0] = 0x10
3897 10:01:58.276364 EX_ROW_EN[1] = 0x0
3898 10:01:58.279470 LP4Y_EN = 0x0
3899 10:01:58.279551 WORK_FSP = 0x0
3900 10:01:58.282919 WL = 0x2
3901 10:01:58.283004 RL = 0x2
3902 10:01:58.286052 BL = 0x2
3903 10:01:58.286128 RPST = 0x0
3904 10:01:58.289688 RD_PRE = 0x0
3905 10:01:58.289774 WR_PRE = 0x1
3906 10:01:58.292832 WR_PST = 0x0
3907 10:01:58.292908 DBI_WR = 0x0
3908 10:01:58.295884 DBI_RD = 0x0
3909 10:01:58.295963 OTF = 0x1
3910 10:01:58.299444 ===================================
3911 10:01:58.305943 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3912 10:01:58.310357 nWR fixed to 30
3913 10:01:58.314120 [ModeRegInit_LP4] CH0 RK0
3914 10:01:58.314198 [ModeRegInit_LP4] CH0 RK1
3915 10:01:58.317168 [ModeRegInit_LP4] CH1 RK0
3916 10:01:58.320278 [ModeRegInit_LP4] CH1 RK1
3917 10:01:58.320355 match AC timing 17
3918 10:01:58.327347 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3919 10:01:58.330612 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3920 10:01:58.333783 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3921 10:01:58.340178 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3922 10:01:58.343475 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3923 10:01:58.343579 ==
3924 10:01:58.347145 Dram Type= 6, Freq= 0, CH_0, rank 0
3925 10:01:58.350381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3926 10:01:58.350510 ==
3927 10:01:58.356990 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3928 10:01:58.363369 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3929 10:01:58.366564 [CA 0] Center 37 (7~67) winsize 61
3930 10:01:58.369930 [CA 1] Center 36 (6~67) winsize 62
3931 10:01:58.373000 [CA 2] Center 35 (5~65) winsize 61
3932 10:01:58.376678 [CA 3] Center 35 (5~65) winsize 61
3933 10:01:58.379793 [CA 4] Center 34 (4~65) winsize 62
3934 10:01:58.383199 [CA 5] Center 34 (4~64) winsize 61
3935 10:01:58.383284
3936 10:01:58.386443 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3937 10:01:58.386553
3938 10:01:58.389448 [CATrainingPosCal] consider 1 rank data
3939 10:01:58.393144 u2DelayCellTimex100 = 270/100 ps
3940 10:01:58.396614 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3941 10:01:58.399649 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3942 10:01:58.403188 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3943 10:01:58.409160 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3944 10:01:58.412911 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3945 10:01:58.416017 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3946 10:01:58.416121
3947 10:01:58.419138 CA PerBit enable=1, Macro0, CA PI delay=34
3948 10:01:58.419247
3949 10:01:58.422236 [CBTSetCACLKResult] CA Dly = 34
3950 10:01:58.422341 CS Dly: 6 (0~37)
3951 10:01:58.422438 ==
3952 10:01:58.426069 Dram Type= 6, Freq= 0, CH_0, rank 1
3953 10:01:58.432064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3954 10:01:58.432142 ==
3955 10:01:58.435658 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3956 10:01:58.442213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3957 10:01:58.445923 [CA 0] Center 37 (7~67) winsize 61
3958 10:01:58.449165 [CA 1] Center 37 (7~67) winsize 61
3959 10:01:58.452339 [CA 2] Center 35 (5~65) winsize 61
3960 10:01:58.455951 [CA 3] Center 35 (5~65) winsize 61
3961 10:01:58.459205 [CA 4] Center 34 (4~64) winsize 61
3962 10:01:58.462245 [CA 5] Center 34 (4~64) winsize 61
3963 10:01:58.462323
3964 10:01:58.465701 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3965 10:01:58.465795
3966 10:01:58.468653 [CATrainingPosCal] consider 2 rank data
3967 10:01:58.472190 u2DelayCellTimex100 = 270/100 ps
3968 10:01:58.475403 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3969 10:01:58.482209 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3970 10:01:58.485344 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3971 10:01:58.488748 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3972 10:01:58.491748 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3973 10:01:58.494894 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3974 10:01:58.494971
3975 10:01:58.498425 CA PerBit enable=1, Macro0, CA PI delay=34
3976 10:01:58.498498
3977 10:01:58.501710 [CBTSetCACLKResult] CA Dly = 34
3978 10:01:58.505267 CS Dly: 6 (0~37)
3979 10:01:58.505346
3980 10:01:58.508482 ----->DramcWriteLeveling(PI) begin...
3981 10:01:58.508554 ==
3982 10:01:58.511906 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 10:01:58.515130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 10:01:58.515199 ==
3985 10:01:58.518198 Write leveling (Byte 0): 33 => 33
3986 10:01:58.521514 Write leveling (Byte 1): 33 => 33
3987 10:01:58.525392 DramcWriteLeveling(PI) end<-----
3988 10:01:58.525462
3989 10:01:58.525525 ==
3990 10:01:58.528379 Dram Type= 6, Freq= 0, CH_0, rank 0
3991 10:01:58.531588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3992 10:01:58.531661 ==
3993 10:01:58.534773 [Gating] SW mode calibration
3994 10:01:58.541478 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3995 10:01:58.548198 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3996 10:01:58.551351 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3997 10:01:58.554545 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 10:01:58.561089 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 10:01:58.564129 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4000 10:01:58.567643 0 9 16 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
4001 10:01:58.574141 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 10:01:58.577649 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 10:01:58.584101 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 10:01:58.587335 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 10:01:58.590417 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 10:01:58.597441 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 10:01:58.600750 0 10 12 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
4008 10:01:58.603836 0 10 16 | B1->B0 | 3131 3a3a | 1 0 | (0 0) (0 0)
4009 10:01:58.607339 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 10:01:58.613777 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 10:01:58.617205 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 10:01:58.623629 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 10:01:58.626813 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 10:01:58.630396 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 10:01:58.636736 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 10:01:58.640389 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 10:01:58.643521 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 10:01:58.646990 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 10:01:58.653484 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 10:01:58.656475 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 10:01:58.659743 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 10:01:58.666377 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 10:01:58.670317 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 10:01:58.673283 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 10:01:58.679666 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 10:01:58.682718 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 10:01:58.689279 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 10:01:58.692697 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 10:01:58.696139 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 10:01:58.702519 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 10:01:58.705980 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4032 10:01:58.709275 Total UI for P1: 0, mck2ui 16
4033 10:01:58.712309 best dqsien dly found for B0: ( 0, 13, 10)
4034 10:01:58.715665 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4035 10:01:58.722343 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 10:01:58.722428 Total UI for P1: 0, mck2ui 16
4037 10:01:58.725771 best dqsien dly found for B1: ( 0, 13, 18)
4038 10:01:58.731940 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4039 10:01:58.735441 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4040 10:01:58.735526
4041 10:01:58.738591 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4042 10:01:58.741745 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4043 10:01:58.745545 [Gating] SW calibration Done
4044 10:01:58.745629 ==
4045 10:01:58.748711 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 10:01:58.752100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 10:01:58.752184 ==
4048 10:01:58.754976 RX Vref Scan: 0
4049 10:01:58.755060
4050 10:01:58.755127 RX Vref 0 -> 0, step: 1
4051 10:01:58.758648
4052 10:01:58.758731 RX Delay -230 -> 252, step: 16
4053 10:01:58.765039 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4054 10:01:58.768168 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4055 10:01:58.771905 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4056 10:01:58.775084 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4057 10:01:58.781631 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4058 10:01:58.784644 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4059 10:01:58.788102 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4060 10:01:58.791384 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4061 10:01:58.795104 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4062 10:01:58.801466 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4063 10:01:58.804469 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4064 10:01:58.808000 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4065 10:01:58.811307 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4066 10:01:58.817574 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4067 10:01:58.821057 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4068 10:01:58.824306 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4069 10:01:58.824390 ==
4070 10:01:58.827663 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 10:01:58.834444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 10:01:58.834530 ==
4073 10:01:58.834597 DQS Delay:
4074 10:01:58.834661 DQS0 = 0, DQS1 = 0
4075 10:01:58.837513 DQM Delay:
4076 10:01:58.837597 DQM0 = 38, DQM1 = 30
4077 10:01:58.840742 DQ Delay:
4078 10:01:58.843928 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4079 10:01:58.847257 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4080 10:01:58.850840 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4081 10:01:58.854055 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4082 10:01:58.854146
4083 10:01:58.854211
4084 10:01:58.854272 ==
4085 10:01:58.857109 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 10:01:58.861001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 10:01:58.861075 ==
4088 10:01:58.861139
4089 10:01:58.861199
4090 10:01:58.863964 TX Vref Scan disable
4091 10:01:58.864076 == TX Byte 0 ==
4092 10:01:58.870304 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4093 10:01:58.873665 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4094 10:01:58.877395 == TX Byte 1 ==
4095 10:01:58.880126 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4096 10:01:58.883444 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4097 10:01:58.883530 ==
4098 10:01:58.886837 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 10:01:58.890254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 10:01:58.893606 ==
4101 10:01:58.893678
4102 10:01:58.893741
4103 10:01:58.893800 TX Vref Scan disable
4104 10:01:58.897229 == TX Byte 0 ==
4105 10:01:58.900432 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4106 10:01:58.907011 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4107 10:01:58.907090 == TX Byte 1 ==
4108 10:01:58.910328 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4109 10:01:58.917553 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4110 10:01:58.917755
4111 10:01:58.917855 [DATLAT]
4112 10:01:58.917921 Freq=600, CH0 RK0
4113 10:01:58.918007
4114 10:01:58.920411 DATLAT Default: 0x9
4115 10:01:58.920544 0, 0xFFFF, sum = 0
4116 10:01:58.923617 1, 0xFFFF, sum = 0
4117 10:01:58.926990 2, 0xFFFF, sum = 0
4118 10:01:58.927135 3, 0xFFFF, sum = 0
4119 10:01:58.930108 4, 0xFFFF, sum = 0
4120 10:01:58.930189 5, 0xFFFF, sum = 0
4121 10:01:58.933456 6, 0xFFFF, sum = 0
4122 10:01:58.933535 7, 0xFFFF, sum = 0
4123 10:01:58.936955 8, 0x0, sum = 1
4124 10:01:58.937039 9, 0x0, sum = 2
4125 10:01:58.939814 10, 0x0, sum = 3
4126 10:01:58.939895 11, 0x0, sum = 4
4127 10:01:58.939980 best_step = 9
4128 10:01:58.940068
4129 10:01:58.943286 ==
4130 10:01:58.946489 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 10:01:58.949743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 10:01:58.949823 ==
4133 10:01:58.949906 RX Vref Scan: 1
4134 10:01:58.949993
4135 10:01:58.952999 RX Vref 0 -> 0, step: 1
4136 10:01:58.953076
4137 10:01:58.956728 RX Delay -195 -> 252, step: 8
4138 10:01:58.956809
4139 10:01:58.959834 Set Vref, RX VrefLevel [Byte0]: 62
4140 10:01:58.962995 [Byte1]: 55
4141 10:01:58.963074
4142 10:01:58.966316 Final RX Vref Byte 0 = 62 to rank0
4143 10:01:58.969367 Final RX Vref Byte 1 = 55 to rank0
4144 10:01:58.972753 Final RX Vref Byte 0 = 62 to rank1
4145 10:01:58.976409 Final RX Vref Byte 1 = 55 to rank1==
4146 10:01:58.979709 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 10:01:58.983105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 10:01:58.986129 ==
4149 10:01:58.986206 DQS Delay:
4150 10:01:58.986290 DQS0 = 0, DQS1 = 0
4151 10:01:58.989465 DQM Delay:
4152 10:01:58.989545 DQM0 = 36, DQM1 = 28
4153 10:01:58.992906 DQ Delay:
4154 10:01:58.996296 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4155 10:01:58.996377 DQ4 =36, DQ5 =24, DQ6 =40, DQ7 =48
4156 10:01:58.999348 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4157 10:01:59.002707 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4158 10:01:59.006380
4159 10:01:59.006462
4160 10:01:59.012476 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4161 10:01:59.015678 CH0 RK0: MR19=808, MR18=3F3E
4162 10:01:59.022532 CH0_RK0: MR19=0x808, MR18=0x3F3E, DQSOSC=397, MR23=63, INC=166, DEC=110
4163 10:01:59.022616
4164 10:01:59.025729 ----->DramcWriteLeveling(PI) begin...
4165 10:01:59.025810 ==
4166 10:01:59.028860 Dram Type= 6, Freq= 0, CH_0, rank 1
4167 10:01:59.032493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 10:01:59.032590 ==
4169 10:01:59.035364 Write leveling (Byte 0): 32 => 32
4170 10:01:59.039228 Write leveling (Byte 1): 32 => 32
4171 10:01:59.042074 DramcWriteLeveling(PI) end<-----
4172 10:01:59.042157
4173 10:01:59.042251 ==
4174 10:01:59.045731 Dram Type= 6, Freq= 0, CH_0, rank 1
4175 10:01:59.049071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 10:01:59.049150 ==
4177 10:01:59.052233 [Gating] SW mode calibration
4178 10:01:59.058746 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4179 10:01:59.065549 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4180 10:01:59.068465 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4181 10:01:59.075033 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4182 10:01:59.078298 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 10:01:59.081529 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4184 10:01:59.088192 0 9 16 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
4185 10:01:59.091852 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 10:01:59.094656 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 10:01:59.101682 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 10:01:59.104729 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 10:01:59.108125 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 10:01:59.114729 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 10:01:59.117968 0 10 12 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
4192 10:01:59.121206 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4193 10:01:59.127682 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 10:01:59.130970 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 10:01:59.134220 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 10:01:59.140853 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 10:01:59.143972 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 10:01:59.147322 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 10:01:59.154221 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4200 10:01:59.157555 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4201 10:01:59.160825 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 10:01:59.167057 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 10:01:59.170284 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 10:01:59.174206 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 10:01:59.180258 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 10:01:59.183662 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 10:01:59.186845 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 10:01:59.193576 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 10:01:59.196730 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 10:01:59.199965 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 10:01:59.206792 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 10:01:59.209797 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 10:01:59.213349 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 10:01:59.219660 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 10:01:59.223201 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4216 10:01:59.226404 Total UI for P1: 0, mck2ui 16
4217 10:01:59.229510 best dqsien dly found for B0: ( 0, 13, 10)
4218 10:01:59.232808 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 10:01:59.236398 Total UI for P1: 0, mck2ui 16
4220 10:01:59.239734 best dqsien dly found for B1: ( 0, 13, 12)
4221 10:01:59.243140 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4222 10:01:59.249723 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4223 10:01:59.249803
4224 10:01:59.252872 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4225 10:01:59.256469 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4226 10:01:59.259550 [Gating] SW calibration Done
4227 10:01:59.259628 ==
4228 10:01:59.262945 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 10:01:59.265971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 10:01:59.266053 ==
4231 10:01:59.269089 RX Vref Scan: 0
4232 10:01:59.269166
4233 10:01:59.269249 RX Vref 0 -> 0, step: 1
4234 10:01:59.269329
4235 10:01:59.272708 RX Delay -230 -> 252, step: 16
4236 10:01:59.275772 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4237 10:01:59.282460 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4238 10:01:59.285936 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4239 10:01:59.289100 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4240 10:01:59.292310 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4241 10:01:59.298762 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4242 10:01:59.302500 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4243 10:01:59.305752 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4244 10:01:59.308879 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4245 10:01:59.312153 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4246 10:01:59.318731 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4247 10:01:59.322274 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4248 10:01:59.325277 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4249 10:01:59.331760 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4250 10:01:59.335416 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4251 10:01:59.338246 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4252 10:01:59.338327 ==
4253 10:01:59.341879 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 10:01:59.344941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 10:01:59.345029 ==
4256 10:01:59.348261 DQS Delay:
4257 10:01:59.348340 DQS0 = 0, DQS1 = 0
4258 10:01:59.351773 DQM Delay:
4259 10:01:59.351846 DQM0 = 36, DQM1 = 30
4260 10:01:59.351910 DQ Delay:
4261 10:01:59.355295 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4262 10:01:59.358467 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4263 10:01:59.361671 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4264 10:01:59.364922 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4265 10:01:59.365001
4266 10:01:59.365067
4267 10:01:59.368039 ==
4268 10:01:59.371497 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 10:01:59.375100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 10:01:59.375176 ==
4271 10:01:59.375240
4272 10:01:59.375301
4273 10:01:59.378489 TX Vref Scan disable
4274 10:01:59.378558 == TX Byte 0 ==
4275 10:01:59.384526 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4276 10:01:59.388123 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4277 10:01:59.388199 == TX Byte 1 ==
4278 10:01:59.394614 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4279 10:01:59.397669 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4280 10:01:59.397753 ==
4281 10:01:59.401331 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 10:01:59.404519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 10:01:59.404604 ==
4284 10:01:59.404671
4285 10:01:59.404734
4286 10:01:59.407835 TX Vref Scan disable
4287 10:01:59.411007 == TX Byte 0 ==
4288 10:01:59.414145 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4289 10:01:59.417774 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4290 10:01:59.420750 == TX Byte 1 ==
4291 10:01:59.424201 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4292 10:01:59.427746 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4293 10:01:59.430999
4294 10:01:59.431084 [DATLAT]
4295 10:01:59.431151 Freq=600, CH0 RK1
4296 10:01:59.431215
4297 10:01:59.434112 DATLAT Default: 0x9
4298 10:01:59.434200 0, 0xFFFF, sum = 0
4299 10:01:59.437619 1, 0xFFFF, sum = 0
4300 10:01:59.437703 2, 0xFFFF, sum = 0
4301 10:01:59.440728 3, 0xFFFF, sum = 0
4302 10:01:59.440811 4, 0xFFFF, sum = 0
4303 10:01:59.443738 5, 0xFFFF, sum = 0
4304 10:01:59.447161 6, 0xFFFF, sum = 0
4305 10:01:59.447244 7, 0xFFFF, sum = 0
4306 10:01:59.450849 8, 0x0, sum = 1
4307 10:01:59.450946 9, 0x0, sum = 2
4308 10:01:59.451013 10, 0x0, sum = 3
4309 10:01:59.454069 11, 0x0, sum = 4
4310 10:01:59.454151 best_step = 9
4311 10:01:59.454216
4312 10:01:59.454276 ==
4313 10:01:59.457031 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 10:01:59.463588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 10:01:59.463670 ==
4316 10:01:59.463735 RX Vref Scan: 0
4317 10:01:59.463797
4318 10:01:59.467177 RX Vref 0 -> 0, step: 1
4319 10:01:59.467258
4320 10:01:59.470221 RX Delay -195 -> 252, step: 8
4321 10:01:59.473717 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4322 10:01:59.480344 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4323 10:01:59.483475 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4324 10:01:59.487210 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4325 10:01:59.490428 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4326 10:01:59.496918 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4327 10:01:59.500197 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4328 10:01:59.503130 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4329 10:01:59.506774 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4330 10:01:59.513567 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4331 10:01:59.516404 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4332 10:01:59.519900 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4333 10:01:59.523163 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4334 10:01:59.529682 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4335 10:01:59.533139 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4336 10:01:59.536436 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4337 10:01:59.536518 ==
4338 10:01:59.539253 Dram Type= 6, Freq= 0, CH_0, rank 1
4339 10:01:59.543061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 10:01:59.546094 ==
4341 10:01:59.546175 DQS Delay:
4342 10:01:59.546240 DQS0 = 0, DQS1 = 0
4343 10:01:59.549118 DQM Delay:
4344 10:01:59.549200 DQM0 = 33, DQM1 = 27
4345 10:01:59.552654 DQ Delay:
4346 10:01:59.552735 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4347 10:01:59.555946 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4348 10:01:59.559103 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4349 10:01:59.563176 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4350 10:01:59.563258
4351 10:01:59.565799
4352 10:01:59.572210 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c3b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4353 10:01:59.575870 CH0 RK1: MR19=808, MR18=6C3B
4354 10:01:59.582306 CH0_RK1: MR19=0x808, MR18=0x6C3B, DQSOSC=389, MR23=63, INC=173, DEC=115
4355 10:01:59.585606 [RxdqsGatingPostProcess] freq 600
4356 10:01:59.588861 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4357 10:01:59.592063 Pre-setting of DQS Precalculation
4358 10:01:59.598517 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4359 10:01:59.598633 ==
4360 10:01:59.601768 Dram Type= 6, Freq= 0, CH_1, rank 0
4361 10:01:59.605123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4362 10:01:59.605240 ==
4363 10:01:59.611620 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4364 10:01:59.614871 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4365 10:01:59.619677 [CA 0] Center 36 (6~66) winsize 61
4366 10:01:59.622689 [CA 1] Center 36 (6~66) winsize 61
4367 10:01:59.626364 [CA 2] Center 34 (4~65) winsize 62
4368 10:01:59.629510 [CA 3] Center 34 (3~65) winsize 63
4369 10:01:59.632627 [CA 4] Center 34 (4~65) winsize 62
4370 10:01:59.636497 [CA 5] Center 33 (3~64) winsize 62
4371 10:01:59.636604
4372 10:01:59.639088 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4373 10:01:59.639168
4374 10:01:59.643073 [CATrainingPosCal] consider 1 rank data
4375 10:01:59.646215 u2DelayCellTimex100 = 270/100 ps
4376 10:01:59.649408 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4377 10:01:59.655737 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4378 10:01:59.659084 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4379 10:01:59.662474 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4380 10:01:59.665770 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4381 10:01:59.669394 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4382 10:01:59.669513
4383 10:01:59.672761 CA PerBit enable=1, Macro0, CA PI delay=33
4384 10:01:59.672856
4385 10:01:59.675775 [CBTSetCACLKResult] CA Dly = 33
4386 10:01:59.678850 CS Dly: 4 (0~35)
4387 10:01:59.678941 ==
4388 10:01:59.682430 Dram Type= 6, Freq= 0, CH_1, rank 1
4389 10:01:59.685804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 10:01:59.685906 ==
4391 10:01:59.692112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4392 10:01:59.695505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4393 10:01:59.699891 [CA 0] Center 36 (6~66) winsize 61
4394 10:01:59.703572 [CA 1] Center 35 (5~66) winsize 62
4395 10:01:59.706597 [CA 2] Center 34 (4~65) winsize 62
4396 10:01:59.709743 [CA 3] Center 34 (3~65) winsize 63
4397 10:01:59.712990 [CA 4] Center 34 (4~65) winsize 62
4398 10:01:59.716282 [CA 5] Center 33 (3~64) winsize 62
4399 10:01:59.716357
4400 10:01:59.719495 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4401 10:01:59.719565
4402 10:01:59.722756 [CATrainingPosCal] consider 2 rank data
4403 10:01:59.725976 u2DelayCellTimex100 = 270/100 ps
4404 10:01:59.729353 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4405 10:01:59.735957 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4406 10:01:59.739202 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4407 10:01:59.742735 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4408 10:01:59.745656 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4409 10:01:59.749290 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4410 10:01:59.749396
4411 10:01:59.752741 CA PerBit enable=1, Macro0, CA PI delay=33
4412 10:01:59.752860
4413 10:01:59.756194 [CBTSetCACLKResult] CA Dly = 33
4414 10:01:59.759084 CS Dly: 4 (0~36)
4415 10:01:59.759162
4416 10:01:59.762151 ----->DramcWriteLeveling(PI) begin...
4417 10:01:59.762270 ==
4418 10:01:59.765630 Dram Type= 6, Freq= 0, CH_1, rank 0
4419 10:01:59.768779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 10:01:59.768883 ==
4421 10:01:59.772034 Write leveling (Byte 0): 31 => 31
4422 10:01:59.775331 Write leveling (Byte 1): 31 => 31
4423 10:01:59.778716 DramcWriteLeveling(PI) end<-----
4424 10:01:59.778849
4425 10:01:59.778959 ==
4426 10:01:59.782225 Dram Type= 6, Freq= 0, CH_1, rank 0
4427 10:01:59.785145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 10:01:59.785250 ==
4429 10:01:59.788810 [Gating] SW mode calibration
4430 10:01:59.795611 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4431 10:01:59.801850 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4432 10:01:59.805366 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4433 10:01:59.808218 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4434 10:01:59.814698 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4435 10:01:59.818474 0 9 12 | B1->B0 | 3232 3030 | 0 1 | (0 0) (1 1)
4436 10:01:59.821216 0 9 16 | B1->B0 | 2929 2b2b | 0 0 | (0 0) (0 0)
4437 10:01:59.827806 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 10:01:59.831469 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 10:01:59.837790 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 10:01:59.841362 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 10:01:59.844725 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 10:01:59.847780 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 10:01:59.854405 0 10 12 | B1->B0 | 2c2c 3030 | 0 0 | (0 0) (0 0)
4444 10:01:59.857772 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 10:01:59.861065 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 10:01:59.867679 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 10:01:59.870946 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 10:01:59.874151 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 10:01:59.880566 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 10:01:59.884062 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 10:01:59.887696 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 10:01:59.894162 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 10:01:59.897097 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 10:01:59.900788 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 10:01:59.907719 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 10:01:59.910711 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 10:01:59.913931 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 10:01:59.920484 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 10:01:59.923672 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 10:01:59.926795 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 10:01:59.933723 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 10:01:59.936767 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 10:01:59.940368 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 10:01:59.946625 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 10:01:59.949836 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 10:01:59.956813 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 10:01:59.959586 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4468 10:01:59.963268 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 10:01:59.966568 Total UI for P1: 0, mck2ui 16
4470 10:01:59.970079 best dqsien dly found for B0: ( 0, 13, 12)
4471 10:01:59.973117 Total UI for P1: 0, mck2ui 16
4472 10:01:59.975987 best dqsien dly found for B1: ( 0, 13, 12)
4473 10:01:59.979976 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4474 10:01:59.982824 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4475 10:01:59.982909
4476 10:01:59.986010 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4477 10:01:59.992903 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4478 10:01:59.993024 [Gating] SW calibration Done
4479 10:01:59.996314 ==
4480 10:01:59.996395 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 10:02:00.002474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 10:02:00.002563 ==
4483 10:02:00.002633 RX Vref Scan: 0
4484 10:02:00.002698
4485 10:02:00.006141 RX Vref 0 -> 0, step: 1
4486 10:02:00.006227
4487 10:02:00.009305 RX Delay -230 -> 252, step: 16
4488 10:02:00.012632 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4489 10:02:00.015807 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4490 10:02:00.022244 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4491 10:02:00.025980 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4492 10:02:00.029212 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4493 10:02:00.032425 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4494 10:02:00.038764 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4495 10:02:00.042739 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4496 10:02:00.045820 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4497 10:02:00.048785 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4498 10:02:00.052032 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4499 10:02:00.058822 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4500 10:02:00.061694 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4501 10:02:00.065491 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4502 10:02:00.071658 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4503 10:02:00.075091 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4504 10:02:00.075175 ==
4505 10:02:00.078204 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 10:02:00.081567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 10:02:00.081647 ==
4508 10:02:00.085202 DQS Delay:
4509 10:02:00.085280 DQS0 = 0, DQS1 = 0
4510 10:02:00.085345 DQM Delay:
4511 10:02:00.088380 DQM0 = 38, DQM1 = 31
4512 10:02:00.088459 DQ Delay:
4513 10:02:00.091707 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4514 10:02:00.094945 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4515 10:02:00.098546 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4516 10:02:00.101601 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4517 10:02:00.101676
4518 10:02:00.101741
4519 10:02:00.101808 ==
4520 10:02:00.105540 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 10:02:00.111224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 10:02:00.111305 ==
4523 10:02:00.111372
4524 10:02:00.111442
4525 10:02:00.111503 TX Vref Scan disable
4526 10:02:00.114924 == TX Byte 0 ==
4527 10:02:00.118354 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4528 10:02:00.124830 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4529 10:02:00.124907 == TX Byte 1 ==
4530 10:02:00.128229 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4531 10:02:00.134750 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4532 10:02:00.134834 ==
4533 10:02:00.137948 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 10:02:00.141216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 10:02:00.141298 ==
4536 10:02:00.141364
4537 10:02:00.141426
4538 10:02:00.144706 TX Vref Scan disable
4539 10:02:00.147845 == TX Byte 0 ==
4540 10:02:00.151019 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4541 10:02:00.154741 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4542 10:02:00.157869 == TX Byte 1 ==
4543 10:02:00.160893 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4544 10:02:00.164480 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4545 10:02:00.164560
4546 10:02:00.167619 [DATLAT]
4547 10:02:00.167701 Freq=600, CH1 RK0
4548 10:02:00.167769
4549 10:02:00.171153 DATLAT Default: 0x9
4550 10:02:00.171228 0, 0xFFFF, sum = 0
4551 10:02:00.174371 1, 0xFFFF, sum = 0
4552 10:02:00.174454 2, 0xFFFF, sum = 0
4553 10:02:00.177340 3, 0xFFFF, sum = 0
4554 10:02:00.177415 4, 0xFFFF, sum = 0
4555 10:02:00.180852 5, 0xFFFF, sum = 0
4556 10:02:00.180932 6, 0xFFFF, sum = 0
4557 10:02:00.184014 7, 0xFFFF, sum = 0
4558 10:02:00.184089 8, 0x0, sum = 1
4559 10:02:00.187364 9, 0x0, sum = 2
4560 10:02:00.187449 10, 0x0, sum = 3
4561 10:02:00.190993 11, 0x0, sum = 4
4562 10:02:00.191071 best_step = 9
4563 10:02:00.191136
4564 10:02:00.191204 ==
4565 10:02:00.194207 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 10:02:00.197288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 10:02:00.200512 ==
4568 10:02:00.200596 RX Vref Scan: 1
4569 10:02:00.200661
4570 10:02:00.203943 RX Vref 0 -> 0, step: 1
4571 10:02:00.204015
4572 10:02:00.204085 RX Delay -179 -> 252, step: 8
4573 10:02:00.207120
4574 10:02:00.207192 Set Vref, RX VrefLevel [Byte0]: 55
4575 10:02:00.210435 [Byte1]: 51
4576 10:02:00.215319
4577 10:02:00.215396 Final RX Vref Byte 0 = 55 to rank0
4578 10:02:00.218510 Final RX Vref Byte 1 = 51 to rank0
4579 10:02:00.222020 Final RX Vref Byte 0 = 55 to rank1
4580 10:02:00.225283 Final RX Vref Byte 1 = 51 to rank1==
4581 10:02:00.228777 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 10:02:00.234977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 10:02:00.235056 ==
4584 10:02:00.235123 DQS Delay:
4585 10:02:00.238708 DQS0 = 0, DQS1 = 0
4586 10:02:00.238782 DQM Delay:
4587 10:02:00.238878 DQM0 = 39, DQM1 = 29
4588 10:02:00.241926 DQ Delay:
4589 10:02:00.245129 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4590 10:02:00.248244 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4591 10:02:00.252138 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4592 10:02:00.255035 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4593 10:02:00.255107
4594 10:02:00.255171
4595 10:02:00.261385 [DQSOSCAuto] RK0, (LSB)MR18= 0x202d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
4596 10:02:00.264499 CH1 RK0: MR19=808, MR18=202D
4597 10:02:00.271068 CH1_RK0: MR19=0x808, MR18=0x202D, DQSOSC=401, MR23=63, INC=163, DEC=108
4598 10:02:00.271151
4599 10:02:00.274284 ----->DramcWriteLeveling(PI) begin...
4600 10:02:00.274369 ==
4601 10:02:00.277900 Dram Type= 6, Freq= 0, CH_1, rank 1
4602 10:02:00.281035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 10:02:00.281116 ==
4604 10:02:00.284530 Write leveling (Byte 0): 30 => 30
4605 10:02:00.287847 Write leveling (Byte 1): 30 => 30
4606 10:02:00.290953 DramcWriteLeveling(PI) end<-----
4607 10:02:00.291026
4608 10:02:00.291091 ==
4609 10:02:00.294323 Dram Type= 6, Freq= 0, CH_1, rank 1
4610 10:02:00.301311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 10:02:00.301392 ==
4612 10:02:00.301460 [Gating] SW mode calibration
4613 10:02:00.310971 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4614 10:02:00.314165 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4615 10:02:00.317570 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4616 10:02:00.324203 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4617 10:02:00.326990 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4618 10:02:00.334283 0 9 12 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 1)
4619 10:02:00.337051 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4620 10:02:00.340632 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 10:02:00.346991 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 10:02:00.350463 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 10:02:00.353915 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 10:02:00.357165 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 10:02:00.363312 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 10:02:00.366883 0 10 12 | B1->B0 | 3131 3c3c | 0 0 | (0 0) (0 0)
4627 10:02:00.373410 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4628 10:02:00.376392 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 10:02:00.380235 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 10:02:00.386215 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 10:02:00.389792 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 10:02:00.393003 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 10:02:00.396457 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 10:02:00.403162 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4635 10:02:00.406369 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 10:02:00.409395 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 10:02:00.416295 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 10:02:00.419715 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 10:02:00.422758 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 10:02:00.429912 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 10:02:00.432830 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 10:02:00.436244 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 10:02:00.442661 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 10:02:00.445783 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 10:02:00.449373 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 10:02:00.455679 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 10:02:00.459232 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 10:02:00.462372 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 10:02:00.469338 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 10:02:00.472279 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4651 10:02:00.475865 Total UI for P1: 0, mck2ui 16
4652 10:02:00.479316 best dqsien dly found for B1: ( 0, 13, 10)
4653 10:02:00.482314 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 10:02:00.485891 Total UI for P1: 0, mck2ui 16
4655 10:02:00.488875 best dqsien dly found for B0: ( 0, 13, 12)
4656 10:02:00.492385 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4657 10:02:00.495508 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4658 10:02:00.498706
4659 10:02:00.502300 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4660 10:02:00.505518 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4661 10:02:00.509148 [Gating] SW calibration Done
4662 10:02:00.509235 ==
4663 10:02:00.512191 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 10:02:00.515359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 10:02:00.515443 ==
4666 10:02:00.518483 RX Vref Scan: 0
4667 10:02:00.518566
4668 10:02:00.518632 RX Vref 0 -> 0, step: 1
4669 10:02:00.518693
4670 10:02:00.521942 RX Delay -230 -> 252, step: 16
4671 10:02:00.525330 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4672 10:02:00.531947 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4673 10:02:00.534927 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4674 10:02:00.538736 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4675 10:02:00.541604 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4676 10:02:00.548145 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4677 10:02:00.551600 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4678 10:02:00.554528 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4679 10:02:00.558299 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4680 10:02:00.564464 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4681 10:02:00.567976 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4682 10:02:00.571143 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4683 10:02:00.574681 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4684 10:02:00.581138 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4685 10:02:00.584259 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4686 10:02:00.587512 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4687 10:02:00.587597 ==
4688 10:02:00.591123 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 10:02:00.594326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 10:02:00.597474 ==
4691 10:02:00.597560 DQS Delay:
4692 10:02:00.597646 DQS0 = 0, DQS1 = 0
4693 10:02:00.600660 DQM Delay:
4694 10:02:00.600743 DQM0 = 36, DQM1 = 29
4695 10:02:00.604263 DQ Delay:
4696 10:02:00.604337 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4697 10:02:00.607226 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4698 10:02:00.610796 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4699 10:02:00.614063 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4700 10:02:00.616962
4701 10:02:00.617034
4702 10:02:00.617097 ==
4703 10:02:00.620729 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 10:02:00.623861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 10:02:00.623947 ==
4706 10:02:00.624013
4707 10:02:00.624076
4708 10:02:00.626952 TX Vref Scan disable
4709 10:02:00.627035 == TX Byte 0 ==
4710 10:02:00.633783 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4711 10:02:00.636861 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4712 10:02:00.636945 == TX Byte 1 ==
4713 10:02:00.643333 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4714 10:02:00.647115 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4715 10:02:00.647199 ==
4716 10:02:00.650046 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 10:02:00.653876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 10:02:00.653960 ==
4719 10:02:00.654026
4720 10:02:00.656663
4721 10:02:00.656746 TX Vref Scan disable
4722 10:02:00.660320 == TX Byte 0 ==
4723 10:02:00.663383 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4724 10:02:00.670119 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4725 10:02:00.670202 == TX Byte 1 ==
4726 10:02:00.673320 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4727 10:02:00.680063 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4728 10:02:00.680146
4729 10:02:00.680213 [DATLAT]
4730 10:02:00.680274 Freq=600, CH1 RK1
4731 10:02:00.680335
4732 10:02:00.683118 DATLAT Default: 0x9
4733 10:02:00.686242 0, 0xFFFF, sum = 0
4734 10:02:00.686326 1, 0xFFFF, sum = 0
4735 10:02:00.689891 2, 0xFFFF, sum = 0
4736 10:02:00.689977 3, 0xFFFF, sum = 0
4737 10:02:00.693029 4, 0xFFFF, sum = 0
4738 10:02:00.693114 5, 0xFFFF, sum = 0
4739 10:02:00.696391 6, 0xFFFF, sum = 0
4740 10:02:00.696475 7, 0xFFFF, sum = 0
4741 10:02:00.699450 8, 0x0, sum = 1
4742 10:02:00.699535 9, 0x0, sum = 2
4743 10:02:00.702546 10, 0x0, sum = 3
4744 10:02:00.702631 11, 0x0, sum = 4
4745 10:02:00.702698 best_step = 9
4746 10:02:00.702761
4747 10:02:00.706288 ==
4748 10:02:00.709334 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 10:02:00.712879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 10:02:00.712962 ==
4751 10:02:00.713028 RX Vref Scan: 0
4752 10:02:00.713091
4753 10:02:00.716038 RX Vref 0 -> 0, step: 1
4754 10:02:00.716121
4755 10:02:00.719170 RX Delay -195 -> 252, step: 8
4756 10:02:00.725904 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4757 10:02:00.729093 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4758 10:02:00.732332 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4759 10:02:00.735619 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4760 10:02:00.742256 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4761 10:02:00.745520 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4762 10:02:00.748991 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4763 10:02:00.752553 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4764 10:02:00.755625 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4765 10:02:00.762620 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4766 10:02:00.765324 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4767 10:02:00.768391 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4768 10:02:00.772317 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4769 10:02:00.778766 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4770 10:02:00.781605 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4771 10:02:00.785229 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4772 10:02:00.785312 ==
4773 10:02:00.788238 Dram Type= 6, Freq= 0, CH_1, rank 1
4774 10:02:00.795332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4775 10:02:00.795415 ==
4776 10:02:00.795483 DQS Delay:
4777 10:02:00.798340 DQS0 = 0, DQS1 = 0
4778 10:02:00.798423 DQM Delay:
4779 10:02:00.798490 DQM0 = 36, DQM1 = 29
4780 10:02:00.801660 DQ Delay:
4781 10:02:00.805122 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4782 10:02:00.808331 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4783 10:02:00.811455 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =20
4784 10:02:00.814955 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4785 10:02:00.815038
4786 10:02:00.815103
4787 10:02:00.821356 [DQSOSCAuto] RK1, (LSB)MR18= 0x395a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4788 10:02:00.824934 CH1 RK1: MR19=808, MR18=395A
4789 10:02:00.831824 CH1_RK1: MR19=0x808, MR18=0x395A, DQSOSC=392, MR23=63, INC=170, DEC=113
4790 10:02:00.834840 [RxdqsGatingPostProcess] freq 600
4791 10:02:00.838042 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4792 10:02:00.841264 Pre-setting of DQS Precalculation
4793 10:02:00.847941 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4794 10:02:00.854168 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4795 10:02:00.861469 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4796 10:02:00.861552
4797 10:02:00.861618
4798 10:02:00.864363 [Calibration Summary] 1200 Mbps
4799 10:02:00.864446 CH 0, Rank 0
4800 10:02:00.867716 SW Impedance : PASS
4801 10:02:00.870750 DUTY Scan : NO K
4802 10:02:00.870852 ZQ Calibration : PASS
4803 10:02:00.874363 Jitter Meter : NO K
4804 10:02:00.877481 CBT Training : PASS
4805 10:02:00.877564 Write leveling : PASS
4806 10:02:00.880702 RX DQS gating : PASS
4807 10:02:00.884338 RX DQ/DQS(RDDQC) : PASS
4808 10:02:00.884421 TX DQ/DQS : PASS
4809 10:02:00.887445 RX DATLAT : PASS
4810 10:02:00.890695 RX DQ/DQS(Engine): PASS
4811 10:02:00.890778 TX OE : NO K
4812 10:02:00.894250 All Pass.
4813 10:02:00.894333
4814 10:02:00.894400 CH 0, Rank 1
4815 10:02:00.897584 SW Impedance : PASS
4816 10:02:00.897667 DUTY Scan : NO K
4817 10:02:00.900872 ZQ Calibration : PASS
4818 10:02:00.903897 Jitter Meter : NO K
4819 10:02:00.903995 CBT Training : PASS
4820 10:02:00.907303 Write leveling : PASS
4821 10:02:00.910374 RX DQS gating : PASS
4822 10:02:00.910457 RX DQ/DQS(RDDQC) : PASS
4823 10:02:00.913573 TX DQ/DQS : PASS
4824 10:02:00.917356 RX DATLAT : PASS
4825 10:02:00.917439 RX DQ/DQS(Engine): PASS
4826 10:02:00.920267 TX OE : NO K
4827 10:02:00.920350 All Pass.
4828 10:02:00.920417
4829 10:02:00.923448 CH 1, Rank 0
4830 10:02:00.923530 SW Impedance : PASS
4831 10:02:00.926729 DUTY Scan : NO K
4832 10:02:00.926812 ZQ Calibration : PASS
4833 10:02:00.930242 Jitter Meter : NO K
4834 10:02:00.933453 CBT Training : PASS
4835 10:02:00.933536 Write leveling : PASS
4836 10:02:00.936663 RX DQS gating : PASS
4837 10:02:00.940380 RX DQ/DQS(RDDQC) : PASS
4838 10:02:00.940460 TX DQ/DQS : PASS
4839 10:02:00.943586 RX DATLAT : PASS
4840 10:02:00.946763 RX DQ/DQS(Engine): PASS
4841 10:02:00.946900 TX OE : NO K
4842 10:02:00.949673 All Pass.
4843 10:02:00.949753
4844 10:02:00.949818 CH 1, Rank 1
4845 10:02:00.953786 SW Impedance : PASS
4846 10:02:00.953890 DUTY Scan : NO K
4847 10:02:00.956501 ZQ Calibration : PASS
4848 10:02:00.960129 Jitter Meter : NO K
4849 10:02:00.960205 CBT Training : PASS
4850 10:02:00.962819 Write leveling : PASS
4851 10:02:00.966458 RX DQS gating : PASS
4852 10:02:00.966560 RX DQ/DQS(RDDQC) : PASS
4853 10:02:00.969525 TX DQ/DQS : PASS
4854 10:02:00.973237 RX DATLAT : PASS
4855 10:02:00.973316 RX DQ/DQS(Engine): PASS
4856 10:02:00.976539 TX OE : NO K
4857 10:02:00.976615 All Pass.
4858 10:02:00.976681
4859 10:02:00.979430 DramC Write-DBI off
4860 10:02:00.983002 PER_BANK_REFRESH: Hybrid Mode
4861 10:02:00.983078 TX_TRACKING: ON
4862 10:02:00.992809 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4863 10:02:00.995721 [FAST_K] Save calibration result to emmc
4864 10:02:00.999299 dramc_set_vcore_voltage set vcore to 662500
4865 10:02:01.002364 Read voltage for 933, 3
4866 10:02:01.002440 Vio18 = 0
4867 10:02:01.002506 Vcore = 662500
4868 10:02:01.005907 Vdram = 0
4869 10:02:01.006008 Vddq = 0
4870 10:02:01.006095 Vmddr = 0
4871 10:02:01.012432 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4872 10:02:01.015487 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4873 10:02:01.019180 MEM_TYPE=3, freq_sel=17
4874 10:02:01.022279 sv_algorithm_assistance_LP4_1600
4875 10:02:01.025829 ============ PULL DRAM RESETB DOWN ============
4876 10:02:01.032265 ========== PULL DRAM RESETB DOWN end =========
4877 10:02:01.035288 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4878 10:02:01.039036 ===================================
4879 10:02:01.042291 LPDDR4 DRAM CONFIGURATION
4880 10:02:01.045319 ===================================
4881 10:02:01.045423 EX_ROW_EN[0] = 0x0
4882 10:02:01.048551 EX_ROW_EN[1] = 0x0
4883 10:02:01.048628 LP4Y_EN = 0x0
4884 10:02:01.052295 WORK_FSP = 0x0
4885 10:02:01.052374 WL = 0x3
4886 10:02:01.055359 RL = 0x3
4887 10:02:01.055459 BL = 0x2
4888 10:02:01.059040 RPST = 0x0
4889 10:02:01.059133 RD_PRE = 0x0
4890 10:02:01.062024 WR_PRE = 0x1
4891 10:02:01.065121 WR_PST = 0x0
4892 10:02:01.065204 DBI_WR = 0x0
4893 10:02:01.068366 DBI_RD = 0x0
4894 10:02:01.068450 OTF = 0x1
4895 10:02:01.071534 ===================================
4896 10:02:01.075080 ===================================
4897 10:02:01.078201 ANA top config
4898 10:02:01.081274 ===================================
4899 10:02:01.081387 DLL_ASYNC_EN = 0
4900 10:02:01.084704 ALL_SLAVE_EN = 1
4901 10:02:01.087879 NEW_RANK_MODE = 1
4902 10:02:01.091187 DLL_IDLE_MODE = 1
4903 10:02:01.091271 LP45_APHY_COMB_EN = 1
4904 10:02:01.094692 TX_ODT_DIS = 1
4905 10:02:01.097998 NEW_8X_MODE = 1
4906 10:02:01.101056 ===================================
4907 10:02:01.104614 ===================================
4908 10:02:01.107969 data_rate = 1866
4909 10:02:01.111043 CKR = 1
4910 10:02:01.114702 DQ_P2S_RATIO = 8
4911 10:02:01.117467 ===================================
4912 10:02:01.117551 CA_P2S_RATIO = 8
4913 10:02:01.121264 DQ_CA_OPEN = 0
4914 10:02:01.124281 DQ_SEMI_OPEN = 0
4915 10:02:01.127821 CA_SEMI_OPEN = 0
4916 10:02:01.130967 CA_FULL_RATE = 0
4917 10:02:01.134140 DQ_CKDIV4_EN = 1
4918 10:02:01.134225 CA_CKDIV4_EN = 1
4919 10:02:01.137252 CA_PREDIV_EN = 0
4920 10:02:01.140777 PH8_DLY = 0
4921 10:02:01.144007 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4922 10:02:01.147830 DQ_AAMCK_DIV = 4
4923 10:02:01.150862 CA_AAMCK_DIV = 4
4924 10:02:01.153961 CA_ADMCK_DIV = 4
4925 10:02:01.154044 DQ_TRACK_CA_EN = 0
4926 10:02:01.157074 CA_PICK = 933
4927 10:02:01.160259 CA_MCKIO = 933
4928 10:02:01.164011 MCKIO_SEMI = 0
4929 10:02:01.167132 PLL_FREQ = 3732
4930 10:02:01.170486 DQ_UI_PI_RATIO = 32
4931 10:02:01.173728 CA_UI_PI_RATIO = 0
4932 10:02:01.177095 ===================================
4933 10:02:01.180294 ===================================
4934 10:02:01.180377 memory_type:LPDDR4
4935 10:02:01.183525 GP_NUM : 10
4936 10:02:01.186739 SRAM_EN : 1
4937 10:02:01.186822 MD32_EN : 0
4938 10:02:01.189883 ===================================
4939 10:02:01.193426 [ANA_INIT] >>>>>>>>>>>>>>
4940 10:02:01.196882 <<<<<< [CONFIGURE PHASE]: ANA_TX
4941 10:02:01.199873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4942 10:02:01.202991 ===================================
4943 10:02:01.206378 data_rate = 1866,PCW = 0X8f00
4944 10:02:01.209810 ===================================
4945 10:02:01.213143 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4946 10:02:01.216466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4947 10:02:01.223042 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4948 10:02:01.226181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4949 10:02:01.232749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4950 10:02:01.235973 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4951 10:02:01.236056 [ANA_INIT] flow start
4952 10:02:01.239124 [ANA_INIT] PLL >>>>>>>>
4953 10:02:01.242731 [ANA_INIT] PLL <<<<<<<<
4954 10:02:01.242842 [ANA_INIT] MIDPI >>>>>>>>
4955 10:02:01.245917 [ANA_INIT] MIDPI <<<<<<<<
4956 10:02:01.248989 [ANA_INIT] DLL >>>>>>>>
4957 10:02:01.249065 [ANA_INIT] flow end
4958 10:02:01.256034 ============ LP4 DIFF to SE enter ============
4959 10:02:01.259713 ============ LP4 DIFF to SE exit ============
4960 10:02:01.259868 [ANA_INIT] <<<<<<<<<<<<<
4961 10:02:01.262300 [Flow] Enable top DCM control >>>>>
4962 10:02:01.265602 [Flow] Enable top DCM control <<<<<
4963 10:02:01.268952 Enable DLL master slave shuffle
4964 10:02:01.276025 ==============================================================
4965 10:02:01.279077 Gating Mode config
4966 10:02:01.282256 ==============================================================
4967 10:02:01.285358 Config description:
4968 10:02:01.295384 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4969 10:02:01.302014 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4970 10:02:01.305590 SELPH_MODE 0: By rank 1: By Phase
4971 10:02:01.312112 ==============================================================
4972 10:02:01.314985 GAT_TRACK_EN = 1
4973 10:02:01.318458 RX_GATING_MODE = 2
4974 10:02:01.322223 RX_GATING_TRACK_MODE = 2
4975 10:02:01.325068 SELPH_MODE = 1
4976 10:02:01.325152 PICG_EARLY_EN = 1
4977 10:02:01.328295 VALID_LAT_VALUE = 1
4978 10:02:01.334817 ==============================================================
4979 10:02:01.338468 Enter into Gating configuration >>>>
4980 10:02:01.341931 Exit from Gating configuration <<<<
4981 10:02:01.344841 Enter into DVFS_PRE_config >>>>>
4982 10:02:01.354600 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4983 10:02:01.358391 Exit from DVFS_PRE_config <<<<<
4984 10:02:01.361549 Enter into PICG configuration >>>>
4985 10:02:01.364676 Exit from PICG configuration <<<<
4986 10:02:01.367865 [RX_INPUT] configuration >>>>>
4987 10:02:01.371060 [RX_INPUT] configuration <<<<<
4988 10:02:01.377554 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4989 10:02:01.380834 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4990 10:02:01.387763 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4991 10:02:01.394231 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4992 10:02:01.400616 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4993 10:02:01.407286 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4994 10:02:01.410461 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4995 10:02:01.414059 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4996 10:02:01.417300 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4997 10:02:01.424053 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4998 10:02:01.427294 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4999 10:02:01.430173 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5000 10:02:01.433693 ===================================
5001 10:02:01.436712 LPDDR4 DRAM CONFIGURATION
5002 10:02:01.440145 ===================================
5003 10:02:01.443478 EX_ROW_EN[0] = 0x0
5004 10:02:01.443562 EX_ROW_EN[1] = 0x0
5005 10:02:01.446723 LP4Y_EN = 0x0
5006 10:02:01.446854 WORK_FSP = 0x0
5007 10:02:01.449905 WL = 0x3
5008 10:02:01.449988 RL = 0x3
5009 10:02:01.453505 BL = 0x2
5010 10:02:01.453589 RPST = 0x0
5011 10:02:01.456913 RD_PRE = 0x0
5012 10:02:01.456997 WR_PRE = 0x1
5013 10:02:01.460352 WR_PST = 0x0
5014 10:02:01.460435 DBI_WR = 0x0
5015 10:02:01.463493 DBI_RD = 0x0
5016 10:02:01.463578 OTF = 0x1
5017 10:02:01.466754 ===================================
5018 10:02:01.473521 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5019 10:02:01.476750 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5020 10:02:01.480025 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5021 10:02:01.483405 ===================================
5022 10:02:01.486400 LPDDR4 DRAM CONFIGURATION
5023 10:02:01.489689 ===================================
5024 10:02:01.492899 EX_ROW_EN[0] = 0x10
5025 10:02:01.492983 EX_ROW_EN[1] = 0x0
5026 10:02:01.496366 LP4Y_EN = 0x0
5027 10:02:01.496449 WORK_FSP = 0x0
5028 10:02:01.499384 WL = 0x3
5029 10:02:01.499467 RL = 0x3
5030 10:02:01.502774 BL = 0x2
5031 10:02:01.502909 RPST = 0x0
5032 10:02:01.505919 RD_PRE = 0x0
5033 10:02:01.506003 WR_PRE = 0x1
5034 10:02:01.509528 WR_PST = 0x0
5035 10:02:01.509612 DBI_WR = 0x0
5036 10:02:01.512647 DBI_RD = 0x0
5037 10:02:01.515915 OTF = 0x1
5038 10:02:01.519087 ===================================
5039 10:02:01.522702 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5040 10:02:01.527775 nWR fixed to 30
5041 10:02:01.530757 [ModeRegInit_LP4] CH0 RK0
5042 10:02:01.530896 [ModeRegInit_LP4] CH0 RK1
5043 10:02:01.534253 [ModeRegInit_LP4] CH1 RK0
5044 10:02:01.537357 [ModeRegInit_LP4] CH1 RK1
5045 10:02:01.537440 match AC timing 9
5046 10:02:01.543920 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5047 10:02:01.547271 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5048 10:02:01.550757 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5049 10:02:01.557468 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5050 10:02:01.560606 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5051 10:02:01.560690 ==
5052 10:02:01.563828 Dram Type= 6, Freq= 0, CH_0, rank 0
5053 10:02:01.567090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5054 10:02:01.567175 ==
5055 10:02:01.573839 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5056 10:02:01.580076 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5057 10:02:01.583515 [CA 0] Center 38 (8~69) winsize 62
5058 10:02:01.586721 [CA 1] Center 38 (7~69) winsize 63
5059 10:02:01.590017 [CA 2] Center 35 (5~65) winsize 61
5060 10:02:01.593139 [CA 3] Center 35 (5~65) winsize 61
5061 10:02:01.597012 [CA 4] Center 34 (4~65) winsize 62
5062 10:02:01.600105 [CA 5] Center 33 (3~64) winsize 62
5063 10:02:01.600189
5064 10:02:01.603168 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5065 10:02:01.603252
5066 10:02:01.606646 [CATrainingPosCal] consider 1 rank data
5067 10:02:01.610072 u2DelayCellTimex100 = 270/100 ps
5068 10:02:01.613296 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5069 10:02:01.616793 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5070 10:02:01.619732 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5071 10:02:01.626554 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5072 10:02:01.629546 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5073 10:02:01.633001 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5074 10:02:01.633085
5075 10:02:01.636162 CA PerBit enable=1, Macro0, CA PI delay=33
5076 10:02:01.636246
5077 10:02:01.639622 [CBTSetCACLKResult] CA Dly = 33
5078 10:02:01.639706 CS Dly: 7 (0~38)
5079 10:02:01.639773 ==
5080 10:02:01.642787 Dram Type= 6, Freq= 0, CH_0, rank 1
5081 10:02:01.649416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5082 10:02:01.649526 ==
5083 10:02:01.653003 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5084 10:02:01.659362 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5085 10:02:01.662885 [CA 0] Center 38 (8~69) winsize 62
5086 10:02:01.666050 [CA 1] Center 38 (8~69) winsize 62
5087 10:02:01.669249 [CA 2] Center 35 (5~66) winsize 62
5088 10:02:01.673063 [CA 3] Center 35 (4~66) winsize 63
5089 10:02:01.676393 [CA 4] Center 34 (4~64) winsize 61
5090 10:02:01.679296 [CA 5] Center 33 (3~64) winsize 62
5091 10:02:01.679380
5092 10:02:01.682537 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5093 10:02:01.682622
5094 10:02:01.685942 [CATrainingPosCal] consider 2 rank data
5095 10:02:01.689661 u2DelayCellTimex100 = 270/100 ps
5096 10:02:01.692385 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5097 10:02:01.699114 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5098 10:02:01.702371 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5099 10:02:01.706101 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5100 10:02:01.709296 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5101 10:02:01.712157 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5102 10:02:01.712241
5103 10:02:01.715666 CA PerBit enable=1, Macro0, CA PI delay=33
5104 10:02:01.715750
5105 10:02:01.719073 [CBTSetCACLKResult] CA Dly = 33
5106 10:02:01.722438 CS Dly: 7 (0~39)
5107 10:02:01.722522
5108 10:02:01.725667 ----->DramcWriteLeveling(PI) begin...
5109 10:02:01.725752 ==
5110 10:02:01.728788 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 10:02:01.732025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 10:02:01.732113 ==
5113 10:02:01.735273 Write leveling (Byte 0): 31 => 31
5114 10:02:01.738732 Write leveling (Byte 1): 31 => 31
5115 10:02:01.742225 DramcWriteLeveling(PI) end<-----
5116 10:02:01.742309
5117 10:02:01.742375 ==
5118 10:02:01.745270 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 10:02:01.748889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5120 10:02:01.748980 ==
5121 10:02:01.751827 [Gating] SW mode calibration
5122 10:02:01.758547 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5123 10:02:01.764939 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5124 10:02:01.768221 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
5125 10:02:01.772047 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5126 10:02:01.778470 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 10:02:01.781449 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 10:02:01.785235 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 10:02:01.791533 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 10:02:01.794991 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 10:02:01.798230 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5132 10:02:01.805163 0 15 0 | B1->B0 | 3333 2b2b | 0 0 | (0 0) (0 0)
5133 10:02:01.808250 0 15 4 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
5134 10:02:01.811491 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 10:02:01.818122 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 10:02:01.821146 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 10:02:01.824389 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 10:02:01.831048 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 10:02:01.834709 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 10:02:01.837830 1 0 0 | B1->B0 | 2b2b 4040 | 0 0 | (0 0) (0 0)
5141 10:02:01.844413 1 0 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5142 10:02:01.847852 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 10:02:01.850804 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 10:02:01.857564 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 10:02:01.860939 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 10:02:01.864222 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 10:02:01.870355 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 10:02:01.873740 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5149 10:02:01.877526 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5150 10:02:01.883818 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 10:02:01.886936 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 10:02:01.890106 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 10:02:01.896924 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 10:02:01.900315 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 10:02:01.903409 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 10:02:01.909934 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 10:02:01.913237 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 10:02:01.916355 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 10:02:01.923285 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 10:02:01.926310 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 10:02:01.929602 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 10:02:01.936492 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 10:02:01.939966 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 10:02:01.942761 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5165 10:02:01.946327 Total UI for P1: 0, mck2ui 16
5166 10:02:01.949534 best dqsien dly found for B0: ( 1, 2, 30)
5167 10:02:01.956169 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5168 10:02:01.959187 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 10:02:01.962904 Total UI for P1: 0, mck2ui 16
5170 10:02:01.966034 best dqsien dly found for B1: ( 1, 3, 4)
5171 10:02:01.969313 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5172 10:02:01.972393 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5173 10:02:01.972476
5174 10:02:01.975770 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5175 10:02:01.982366 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5176 10:02:01.982449 [Gating] SW calibration Done
5177 10:02:01.982517 ==
5178 10:02:01.985487 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 10:02:01.992245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 10:02:01.992329 ==
5181 10:02:01.992396 RX Vref Scan: 0
5182 10:02:01.992459
5183 10:02:01.995368 RX Vref 0 -> 0, step: 1
5184 10:02:01.995483
5185 10:02:01.998625 RX Delay -80 -> 252, step: 8
5186 10:02:02.002018 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5187 10:02:02.005318 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5188 10:02:02.008485 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5189 10:02:02.014771 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5190 10:02:02.018499 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5191 10:02:02.021753 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5192 10:02:02.025049 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5193 10:02:02.028241 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5194 10:02:02.034760 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5195 10:02:02.038207 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5196 10:02:02.041364 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5197 10:02:02.044807 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5198 10:02:02.047801 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5199 10:02:02.054630 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5200 10:02:02.057799 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5201 10:02:02.061117 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5202 10:02:02.061200 ==
5203 10:02:02.064565 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 10:02:02.067642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 10:02:02.070684 ==
5206 10:02:02.070767 DQS Delay:
5207 10:02:02.070855 DQS0 = 0, DQS1 = 0
5208 10:02:02.074165 DQM Delay:
5209 10:02:02.074249 DQM0 = 94, DQM1 = 82
5210 10:02:02.077700 DQ Delay:
5211 10:02:02.077785 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5212 10:02:02.080936 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5213 10:02:02.083970 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5214 10:02:02.090708 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5215 10:02:02.090791
5216 10:02:02.090906
5217 10:02:02.090970 ==
5218 10:02:02.093852 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 10:02:02.097003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 10:02:02.097082 ==
5221 10:02:02.097152
5222 10:02:02.097213
5223 10:02:02.100576 TX Vref Scan disable
5224 10:02:02.100662 == TX Byte 0 ==
5225 10:02:02.107244 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5226 10:02:02.110410 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5227 10:02:02.110494 == TX Byte 1 ==
5228 10:02:02.116978 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5229 10:02:02.120335 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5230 10:02:02.120419 ==
5231 10:02:02.123551 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 10:02:02.126734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 10:02:02.126818 ==
5234 10:02:02.129965
5235 10:02:02.130048
5236 10:02:02.130115 TX Vref Scan disable
5237 10:02:02.133036 == TX Byte 0 ==
5238 10:02:02.136756 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5239 10:02:02.142994 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5240 10:02:02.143078 == TX Byte 1 ==
5241 10:02:02.146388 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5242 10:02:02.152937 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5243 10:02:02.153021
5244 10:02:02.153088 [DATLAT]
5245 10:02:02.153149 Freq=933, CH0 RK0
5246 10:02:02.153210
5247 10:02:02.156628 DATLAT Default: 0xd
5248 10:02:02.159774 0, 0xFFFF, sum = 0
5249 10:02:02.159860 1, 0xFFFF, sum = 0
5250 10:02:02.163245 2, 0xFFFF, sum = 0
5251 10:02:02.163331 3, 0xFFFF, sum = 0
5252 10:02:02.166432 4, 0xFFFF, sum = 0
5253 10:02:02.166517 5, 0xFFFF, sum = 0
5254 10:02:02.169395 6, 0xFFFF, sum = 0
5255 10:02:02.169479 7, 0xFFFF, sum = 0
5256 10:02:02.172844 8, 0xFFFF, sum = 0
5257 10:02:02.172929 9, 0xFFFF, sum = 0
5258 10:02:02.176227 10, 0x0, sum = 1
5259 10:02:02.176312 11, 0x0, sum = 2
5260 10:02:02.179536 12, 0x0, sum = 3
5261 10:02:02.179621 13, 0x0, sum = 4
5262 10:02:02.179691 best_step = 11
5263 10:02:02.182718
5264 10:02:02.182804 ==
5265 10:02:02.186239 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 10:02:02.189216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 10:02:02.189300 ==
5268 10:02:02.189368 RX Vref Scan: 1
5269 10:02:02.189431
5270 10:02:02.192991 RX Vref 0 -> 0, step: 1
5271 10:02:02.193075
5272 10:02:02.195830 RX Delay -69 -> 252, step: 4
5273 10:02:02.195914
5274 10:02:02.199294 Set Vref, RX VrefLevel [Byte0]: 62
5275 10:02:02.202504 [Byte1]: 55
5276 10:02:02.205815
5277 10:02:02.205899 Final RX Vref Byte 0 = 62 to rank0
5278 10:02:02.209357 Final RX Vref Byte 1 = 55 to rank0
5279 10:02:02.212439 Final RX Vref Byte 0 = 62 to rank1
5280 10:02:02.215670 Final RX Vref Byte 1 = 55 to rank1==
5281 10:02:02.219280 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 10:02:02.225754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 10:02:02.225839 ==
5284 10:02:02.225907 DQS Delay:
5285 10:02:02.228911 DQS0 = 0, DQS1 = 0
5286 10:02:02.228995 DQM Delay:
5287 10:02:02.229063 DQM0 = 95, DQM1 = 83
5288 10:02:02.232011 DQ Delay:
5289 10:02:02.235850 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5290 10:02:02.239006 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =108
5291 10:02:02.242161 DQ8 =78, DQ9 =72, DQ10 =82, DQ11 =80
5292 10:02:02.245502 DQ12 =88, DQ13 =86, DQ14 =92, DQ15 =90
5293 10:02:02.245586
5294 10:02:02.245653
5295 10:02:02.252072 [DQSOSCAuto] RK0, (LSB)MR18= 0x100f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5296 10:02:02.255711 CH0 RK0: MR19=505, MR18=100F
5297 10:02:02.261759 CH0_RK0: MR19=0x505, MR18=0x100F, DQSOSC=416, MR23=63, INC=62, DEC=41
5298 10:02:02.261844
5299 10:02:02.265362 ----->DramcWriteLeveling(PI) begin...
5300 10:02:02.265446 ==
5301 10:02:02.268449 Dram Type= 6, Freq= 0, CH_0, rank 1
5302 10:02:02.272082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 10:02:02.272164 ==
5304 10:02:02.274993 Write leveling (Byte 0): 33 => 33
5305 10:02:02.278427 Write leveling (Byte 1): 28 => 28
5306 10:02:02.281834 DramcWriteLeveling(PI) end<-----
5307 10:02:02.281915
5308 10:02:02.281981 ==
5309 10:02:02.284765 Dram Type= 6, Freq= 0, CH_0, rank 1
5310 10:02:02.288313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 10:02:02.291702 ==
5312 10:02:02.291784 [Gating] SW mode calibration
5313 10:02:02.301266 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5314 10:02:02.305211 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5315 10:02:02.307974 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5316 10:02:02.314762 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 10:02:02.317872 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 10:02:02.321557 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 10:02:02.327989 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 10:02:02.331173 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 10:02:02.334289 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 10:02:02.340912 0 14 28 | B1->B0 | 3030 2828 | 1 0 | (1 0) (0 0)
5323 10:02:02.344010 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5324 10:02:02.347778 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 10:02:02.354056 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 10:02:02.357539 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 10:02:02.361043 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 10:02:02.366987 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 10:02:02.370508 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 10:02:02.373717 0 15 28 | B1->B0 | 2929 3434 | 0 0 | (0 0) (0 0)
5331 10:02:02.380325 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
5332 10:02:02.383651 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 10:02:02.389965 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 10:02:02.393379 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 10:02:02.396544 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 10:02:02.403296 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 10:02:02.406803 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 10:02:02.409775 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5339 10:02:02.416602 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5340 10:02:02.419721 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 10:02:02.423136 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 10:02:02.429827 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 10:02:02.433188 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 10:02:02.435939 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 10:02:02.442850 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 10:02:02.446025 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 10:02:02.449191 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 10:02:02.455589 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 10:02:02.459355 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 10:02:02.462534 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 10:02:02.469205 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 10:02:02.472113 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 10:02:02.475722 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 10:02:02.481953 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5355 10:02:02.485450 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5356 10:02:02.488637 Total UI for P1: 0, mck2ui 16
5357 10:02:02.491827 best dqsien dly found for B0: ( 1, 2, 28)
5358 10:02:02.495220 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 10:02:02.498274 Total UI for P1: 0, mck2ui 16
5360 10:02:02.501807 best dqsien dly found for B1: ( 1, 3, 0)
5361 10:02:02.505183 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5362 10:02:02.508163 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5363 10:02:02.508247
5364 10:02:02.514665 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5365 10:02:02.518415 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5366 10:02:02.518499 [Gating] SW calibration Done
5367 10:02:02.521474 ==
5368 10:02:02.524903 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 10:02:02.528340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 10:02:02.528425 ==
5371 10:02:02.528492 RX Vref Scan: 0
5372 10:02:02.528556
5373 10:02:02.531529 RX Vref 0 -> 0, step: 1
5374 10:02:02.531613
5375 10:02:02.534722 RX Delay -80 -> 252, step: 8
5376 10:02:02.537868 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5377 10:02:02.541074 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5378 10:02:02.547318 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5379 10:02:02.550520 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5380 10:02:02.554144 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5381 10:02:02.557376 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5382 10:02:02.560552 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5383 10:02:02.567369 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5384 10:02:02.570378 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5385 10:02:02.573693 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5386 10:02:02.577030 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5387 10:02:02.580057 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5388 10:02:02.586801 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5389 10:02:02.590017 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5390 10:02:02.593454 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5391 10:02:02.596781 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5392 10:02:02.596857 ==
5393 10:02:02.600067 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 10:02:02.606682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 10:02:02.606785 ==
5396 10:02:02.606874 DQS Delay:
5397 10:02:02.609696 DQS0 = 0, DQS1 = 0
5398 10:02:02.609766 DQM Delay:
5399 10:02:02.609827 DQM0 = 91, DQM1 = 83
5400 10:02:02.613173 DQ Delay:
5401 10:02:02.616692 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5402 10:02:02.619740 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5403 10:02:02.622967 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5404 10:02:02.626121 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =91
5405 10:02:02.626204
5406 10:02:02.626270
5407 10:02:02.626333 ==
5408 10:02:02.630024 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 10:02:02.632751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 10:02:02.632836 ==
5411 10:02:02.632903
5412 10:02:02.632966
5413 10:02:02.636398 TX Vref Scan disable
5414 10:02:02.639647 == TX Byte 0 ==
5415 10:02:02.642932 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5416 10:02:02.646119 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5417 10:02:02.649378 == TX Byte 1 ==
5418 10:02:02.652777 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5419 10:02:02.655899 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5420 10:02:02.655983 ==
5421 10:02:02.659168 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 10:02:02.666136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 10:02:02.666220 ==
5424 10:02:02.666286
5425 10:02:02.666349
5426 10:02:02.666408 TX Vref Scan disable
5427 10:02:02.669801 == TX Byte 0 ==
5428 10:02:02.672962 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5429 10:02:02.679684 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5430 10:02:02.679768 == TX Byte 1 ==
5431 10:02:02.682711 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5432 10:02:02.689431 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5433 10:02:02.689515
5434 10:02:02.689582 [DATLAT]
5435 10:02:02.689645 Freq=933, CH0 RK1
5436 10:02:02.689706
5437 10:02:02.693050 DATLAT Default: 0xb
5438 10:02:02.695958 0, 0xFFFF, sum = 0
5439 10:02:02.696073 1, 0xFFFF, sum = 0
5440 10:02:02.699356 2, 0xFFFF, sum = 0
5441 10:02:02.699441 3, 0xFFFF, sum = 0
5442 10:02:02.702715 4, 0xFFFF, sum = 0
5443 10:02:02.702835 5, 0xFFFF, sum = 0
5444 10:02:02.706481 6, 0xFFFF, sum = 0
5445 10:02:02.706566 7, 0xFFFF, sum = 0
5446 10:02:02.709185 8, 0xFFFF, sum = 0
5447 10:02:02.709270 9, 0xFFFF, sum = 0
5448 10:02:02.712547 10, 0x0, sum = 1
5449 10:02:02.712631 11, 0x0, sum = 2
5450 10:02:02.715883 12, 0x0, sum = 3
5451 10:02:02.715975 13, 0x0, sum = 4
5452 10:02:02.719257 best_step = 11
5453 10:02:02.719340
5454 10:02:02.719406 ==
5455 10:02:02.722225 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 10:02:02.725685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 10:02:02.725769 ==
5458 10:02:02.725837 RX Vref Scan: 0
5459 10:02:02.728737
5460 10:02:02.728820 RX Vref 0 -> 0, step: 1
5461 10:02:02.728886
5462 10:02:02.732664 RX Delay -69 -> 252, step: 4
5463 10:02:02.738715 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5464 10:02:02.741981 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5465 10:02:02.745726 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5466 10:02:02.748482 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5467 10:02:02.751953 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5468 10:02:02.758424 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5469 10:02:02.762042 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5470 10:02:02.764919 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5471 10:02:02.768235 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5472 10:02:02.771965 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5473 10:02:02.778426 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5474 10:02:02.781610 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5475 10:02:02.784758 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5476 10:02:02.788149 iDelay=199, Bit 13, Center 88 (-5 ~ 182) 188
5477 10:02:02.791543 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5478 10:02:02.798163 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5479 10:02:02.798271 ==
5480 10:02:02.801221 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 10:02:02.804737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 10:02:02.804822 ==
5483 10:02:02.804889 DQS Delay:
5484 10:02:02.808155 DQS0 = 0, DQS1 = 0
5485 10:02:02.808239 DQM Delay:
5486 10:02:02.810991 DQM0 = 92, DQM1 = 85
5487 10:02:02.811076 DQ Delay:
5488 10:02:02.814710 DQ0 =88, DQ1 =94, DQ2 =88, DQ3 =88
5489 10:02:02.817774 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =104
5490 10:02:02.821167 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =78
5491 10:02:02.824612 DQ12 =92, DQ13 =88, DQ14 =96, DQ15 =92
5492 10:02:02.824696
5493 10:02:02.824762
5494 10:02:02.834532 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5495 10:02:02.834618 CH0 RK1: MR19=505, MR18=2D0E
5496 10:02:02.841849 CH0_RK1: MR19=0x505, MR18=0x2D0E, DQSOSC=407, MR23=63, INC=65, DEC=43
5497 10:02:02.843993 [RxdqsGatingPostProcess] freq 933
5498 10:02:02.851082 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5499 10:02:02.854275 best DQS0 dly(2T, 0.5T) = (0, 10)
5500 10:02:02.857521 best DQS1 dly(2T, 0.5T) = (0, 11)
5501 10:02:02.860681 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5502 10:02:02.864350 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5503 10:02:02.864428 best DQS0 dly(2T, 0.5T) = (0, 10)
5504 10:02:02.867893 best DQS1 dly(2T, 0.5T) = (0, 11)
5505 10:02:02.870736 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5506 10:02:02.873881 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5507 10:02:02.877743 Pre-setting of DQS Precalculation
5508 10:02:02.884237 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5509 10:02:02.884327 ==
5510 10:02:02.887363 Dram Type= 6, Freq= 0, CH_1, rank 0
5511 10:02:02.890419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 10:02:02.890495 ==
5513 10:02:02.897143 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5514 10:02:02.903747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5515 10:02:02.907274 [CA 0] Center 37 (7~67) winsize 61
5516 10:02:02.910769 [CA 1] Center 37 (7~68) winsize 62
5517 10:02:02.913742 [CA 2] Center 34 (5~64) winsize 60
5518 10:02:02.916936 [CA 3] Center 34 (4~64) winsize 61
5519 10:02:02.920344 [CA 4] Center 34 (5~64) winsize 60
5520 10:02:02.923516 [CA 5] Center 33 (4~63) winsize 60
5521 10:02:02.923600
5522 10:02:02.926656 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5523 10:02:02.926766
5524 10:02:02.930045 [CATrainingPosCal] consider 1 rank data
5525 10:02:02.933378 u2DelayCellTimex100 = 270/100 ps
5526 10:02:02.936718 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5527 10:02:02.939973 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5528 10:02:02.942986 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5529 10:02:02.946364 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5530 10:02:02.950019 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5531 10:02:02.952855 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5532 10:02:02.956529
5533 10:02:02.959928 CA PerBit enable=1, Macro0, CA PI delay=33
5534 10:02:02.960013
5535 10:02:02.962955 [CBTSetCACLKResult] CA Dly = 33
5536 10:02:02.963039 CS Dly: 5 (0~36)
5537 10:02:02.963105 ==
5538 10:02:02.966167 Dram Type= 6, Freq= 0, CH_1, rank 1
5539 10:02:02.969384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5540 10:02:02.972709 ==
5541 10:02:02.975963 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5542 10:02:02.983167 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5543 10:02:02.986122 [CA 0] Center 38 (8~68) winsize 61
5544 10:02:02.989360 [CA 1] Center 37 (7~68) winsize 62
5545 10:02:02.992436 [CA 2] Center 35 (5~65) winsize 61
5546 10:02:02.996036 [CA 3] Center 34 (4~64) winsize 61
5547 10:02:02.999312 [CA 4] Center 35 (5~65) winsize 61
5548 10:02:03.002460 [CA 5] Center 34 (4~64) winsize 61
5549 10:02:03.002537
5550 10:02:03.005660 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5551 10:02:03.005737
5552 10:02:03.009075 [CATrainingPosCal] consider 2 rank data
5553 10:02:03.012326 u2DelayCellTimex100 = 270/100 ps
5554 10:02:03.015934 CA0 delay=37 (8~67),Diff = 4 PI (24 cell)
5555 10:02:03.019231 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5556 10:02:03.022198 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5557 10:02:03.028812 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5558 10:02:03.032165 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5559 10:02:03.035220 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5560 10:02:03.035303
5561 10:02:03.038714 CA PerBit enable=1, Macro0, CA PI delay=33
5562 10:02:03.038810
5563 10:02:03.041832 [CBTSetCACLKResult] CA Dly = 33
5564 10:02:03.041915 CS Dly: 6 (0~38)
5565 10:02:03.041982
5566 10:02:03.045212 ----->DramcWriteLeveling(PI) begin...
5567 10:02:03.048514 ==
5568 10:02:03.051961 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 10:02:03.055308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 10:02:03.055392 ==
5571 10:02:03.058477 Write leveling (Byte 0): 24 => 24
5572 10:02:03.061805 Write leveling (Byte 1): 30 => 30
5573 10:02:03.065451 DramcWriteLeveling(PI) end<-----
5574 10:02:03.065534
5575 10:02:03.065600 ==
5576 10:02:03.068611 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 10:02:03.071756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 10:02:03.071840 ==
5579 10:02:03.074972 [Gating] SW mode calibration
5580 10:02:03.081525 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5581 10:02:03.088405 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5582 10:02:03.091747 0 14 0 | B1->B0 | 3232 3333 | 0 1 | (0 0) (1 1)
5583 10:02:03.094799 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 10:02:03.101629 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 10:02:03.104802 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 10:02:03.108122 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 10:02:03.115006 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 10:02:03.117622 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 10:02:03.121215 0 14 28 | B1->B0 | 3131 2f2f | 0 1 | (0 1) (1 0)
5590 10:02:03.127904 0 15 0 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
5591 10:02:03.130764 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 10:02:03.134498 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 10:02:03.141257 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 10:02:03.144380 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 10:02:03.147738 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 10:02:03.154060 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 10:02:03.157494 0 15 28 | B1->B0 | 2d2d 3333 | 1 0 | (0 0) (0 0)
5598 10:02:03.160795 1 0 0 | B1->B0 | 4444 4444 | 1 0 | (0 0) (0 0)
5599 10:02:03.167326 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 10:02:03.170425 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 10:02:03.173713 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 10:02:03.180497 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 10:02:03.183570 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 10:02:03.186977 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 10:02:03.193443 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 10:02:03.197075 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 10:02:03.200242 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 10:02:03.206960 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 10:02:03.209655 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 10:02:03.213425 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 10:02:03.220208 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 10:02:03.223166 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 10:02:03.226525 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 10:02:03.233322 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 10:02:03.236408 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 10:02:03.239708 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 10:02:03.246274 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 10:02:03.249399 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 10:02:03.252655 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 10:02:03.259515 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 10:02:03.262759 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5622 10:02:03.265858 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 10:02:03.269349 Total UI for P1: 0, mck2ui 16
5624 10:02:03.272257 best dqsien dly found for B0: ( 1, 2, 28)
5625 10:02:03.276007 Total UI for P1: 0, mck2ui 16
5626 10:02:03.279306 best dqsien dly found for B1: ( 1, 2, 28)
5627 10:02:03.282695 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5628 10:02:03.285767 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5629 10:02:03.285852
5630 10:02:03.292241 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5631 10:02:03.295817 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5632 10:02:03.295895 [Gating] SW calibration Done
5633 10:02:03.299030 ==
5634 10:02:03.302220 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 10:02:03.305391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 10:02:03.305504 ==
5637 10:02:03.305595 RX Vref Scan: 0
5638 10:02:03.305660
5639 10:02:03.308554 RX Vref 0 -> 0, step: 1
5640 10:02:03.308637
5641 10:02:03.312290 RX Delay -80 -> 252, step: 8
5642 10:02:03.315533 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5643 10:02:03.318714 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5644 10:02:03.325374 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5645 10:02:03.328436 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5646 10:02:03.331782 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5647 10:02:03.335108 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5648 10:02:03.338201 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5649 10:02:03.341773 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5650 10:02:03.348486 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5651 10:02:03.351915 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5652 10:02:03.355379 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5653 10:02:03.358288 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5654 10:02:03.361433 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5655 10:02:03.368208 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5656 10:02:03.371688 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5657 10:02:03.374667 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5658 10:02:03.374750 ==
5659 10:02:03.378154 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 10:02:03.381647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 10:02:03.381731 ==
5662 10:02:03.384853 DQS Delay:
5663 10:02:03.384938 DQS0 = 0, DQS1 = 0
5664 10:02:03.385024 DQM Delay:
5665 10:02:03.388056 DQM0 = 96, DQM1 = 87
5666 10:02:03.388140 DQ Delay:
5667 10:02:03.391719 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5668 10:02:03.394865 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =95
5669 10:02:03.398051 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5670 10:02:03.401299 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5671 10:02:03.401384
5672 10:02:03.401471
5673 10:02:03.404468 ==
5674 10:02:03.407611 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 10:02:03.411357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 10:02:03.411464 ==
5677 10:02:03.411551
5678 10:02:03.411633
5679 10:02:03.414089 TX Vref Scan disable
5680 10:02:03.414175 == TX Byte 0 ==
5681 10:02:03.421017 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5682 10:02:03.424021 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5683 10:02:03.424106 == TX Byte 1 ==
5684 10:02:03.430578 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5685 10:02:03.434305 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5686 10:02:03.434411 ==
5687 10:02:03.437091 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 10:02:03.440806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 10:02:03.440892 ==
5690 10:02:03.440978
5691 10:02:03.441059
5692 10:02:03.444010 TX Vref Scan disable
5693 10:02:03.447091 == TX Byte 0 ==
5694 10:02:03.450760 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5695 10:02:03.453844 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5696 10:02:03.457953 == TX Byte 1 ==
5697 10:02:03.460168 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5698 10:02:03.463704 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5699 10:02:03.463791
5700 10:02:03.466667 [DATLAT]
5701 10:02:03.466770 Freq=933, CH1 RK0
5702 10:02:03.466889
5703 10:02:03.470246 DATLAT Default: 0xd
5704 10:02:03.470332 0, 0xFFFF, sum = 0
5705 10:02:03.473691 1, 0xFFFF, sum = 0
5706 10:02:03.473779 2, 0xFFFF, sum = 0
5707 10:02:03.476685 3, 0xFFFF, sum = 0
5708 10:02:03.476773 4, 0xFFFF, sum = 0
5709 10:02:03.480116 5, 0xFFFF, sum = 0
5710 10:02:03.480204 6, 0xFFFF, sum = 0
5711 10:02:03.483632 7, 0xFFFF, sum = 0
5712 10:02:03.486482 8, 0xFFFF, sum = 0
5713 10:02:03.486598 9, 0xFFFF, sum = 0
5714 10:02:03.490264 10, 0x0, sum = 1
5715 10:02:03.490351 11, 0x0, sum = 2
5716 10:02:03.490439 12, 0x0, sum = 3
5717 10:02:03.493388 13, 0x0, sum = 4
5718 10:02:03.493476 best_step = 11
5719 10:02:03.493562
5720 10:02:03.493643 ==
5721 10:02:03.497026 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 10:02:03.503203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 10:02:03.503287 ==
5724 10:02:03.503355 RX Vref Scan: 1
5725 10:02:03.503437
5726 10:02:03.506382 RX Vref 0 -> 0, step: 1
5727 10:02:03.506465
5728 10:02:03.509509 RX Delay -69 -> 252, step: 4
5729 10:02:03.509592
5730 10:02:03.512832 Set Vref, RX VrefLevel [Byte0]: 55
5731 10:02:03.516384 [Byte1]: 51
5732 10:02:03.516468
5733 10:02:03.519547 Final RX Vref Byte 0 = 55 to rank0
5734 10:02:03.522748 Final RX Vref Byte 1 = 51 to rank0
5735 10:02:03.526379 Final RX Vref Byte 0 = 55 to rank1
5736 10:02:03.529450 Final RX Vref Byte 1 = 51 to rank1==
5737 10:02:03.533145 Dram Type= 6, Freq= 0, CH_1, rank 0
5738 10:02:03.536301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 10:02:03.539330 ==
5740 10:02:03.539443 DQS Delay:
5741 10:02:03.539525 DQS0 = 0, DQS1 = 0
5742 10:02:03.542776 DQM Delay:
5743 10:02:03.542895 DQM0 = 95, DQM1 = 87
5744 10:02:03.546185 DQ Delay:
5745 10:02:03.549359 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =92
5746 10:02:03.552447 DQ4 =92, DQ5 =104, DQ6 =108, DQ7 =92
5747 10:02:03.556065 DQ8 =76, DQ9 =80, DQ10 =86, DQ11 =80
5748 10:02:03.559066 DQ12 =96, DQ13 =92, DQ14 =96, DQ15 =94
5749 10:02:03.559150
5750 10:02:03.559234
5751 10:02:03.565803 [DQSOSCAuto] RK0, (LSB)MR18= 0x30b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5752 10:02:03.569320 CH1 RK0: MR19=505, MR18=30B
5753 10:02:03.575949 CH1_RK0: MR19=0x505, MR18=0x30B, DQSOSC=418, MR23=63, INC=62, DEC=41
5754 10:02:03.576035
5755 10:02:03.578793 ----->DramcWriteLeveling(PI) begin...
5756 10:02:03.578917 ==
5757 10:02:03.582239 Dram Type= 6, Freq= 0, CH_1, rank 1
5758 10:02:03.585637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 10:02:03.585721 ==
5760 10:02:03.589111 Write leveling (Byte 0): 27 => 27
5761 10:02:03.592463 Write leveling (Byte 1): 28 => 28
5762 10:02:03.595503 DramcWriteLeveling(PI) end<-----
5763 10:02:03.595587
5764 10:02:03.595654 ==
5765 10:02:03.598586 Dram Type= 6, Freq= 0, CH_1, rank 1
5766 10:02:03.602346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 10:02:03.602430 ==
5768 10:02:03.605446 [Gating] SW mode calibration
5769 10:02:03.612007 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5770 10:02:03.618652 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5771 10:02:03.621790 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
5772 10:02:03.628661 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 10:02:03.631811 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 10:02:03.634752 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 10:02:03.641766 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 10:02:03.644881 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5777 10:02:03.648318 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
5778 10:02:03.654964 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5779 10:02:03.658371 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 10:02:03.661498 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 10:02:03.668034 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 10:02:03.671487 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 10:02:03.674946 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 10:02:03.681461 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 10:02:03.684403 0 15 24 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
5786 10:02:03.687682 0 15 28 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (1 1)
5787 10:02:03.694581 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 10:02:03.697538 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 10:02:03.700940 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 10:02:03.707835 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 10:02:03.711194 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 10:02:03.714264 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 10:02:03.720674 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5794 10:02:03.723725 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5795 10:02:03.727394 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5796 10:02:03.733761 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 10:02:03.736916 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 10:02:03.740518 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 10:02:03.746824 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 10:02:03.749980 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 10:02:03.753450 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 10:02:03.760271 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 10:02:03.763343 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 10:02:03.766470 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 10:02:03.773245 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 10:02:03.776910 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 10:02:03.780295 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 10:02:03.786288 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 10:02:03.789759 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5810 10:02:03.793218 Total UI for P1: 0, mck2ui 16
5811 10:02:03.796259 best dqsien dly found for B0: ( 1, 2, 22)
5812 10:02:03.799731 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5813 10:02:03.806060 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5814 10:02:03.809348 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 10:02:03.812535 Total UI for P1: 0, mck2ui 16
5816 10:02:03.815746 best dqsien dly found for B1: ( 1, 2, 28)
5817 10:02:03.819404 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5818 10:02:03.822757 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5819 10:02:03.822872
5820 10:02:03.825762 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5821 10:02:03.829237 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5822 10:02:03.832431 [Gating] SW calibration Done
5823 10:02:03.832509 ==
5824 10:02:03.835680 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 10:02:03.842418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 10:02:03.842529 ==
5827 10:02:03.842635 RX Vref Scan: 0
5828 10:02:03.842727
5829 10:02:03.845907 RX Vref 0 -> 0, step: 1
5830 10:02:03.846014
5831 10:02:03.848742 RX Delay -80 -> 252, step: 8
5832 10:02:03.851984 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5833 10:02:03.855222 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5834 10:02:03.859199 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5835 10:02:03.861890 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5836 10:02:03.868405 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5837 10:02:03.872275 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5838 10:02:03.875267 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5839 10:02:03.878340 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5840 10:02:03.881610 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5841 10:02:03.888346 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5842 10:02:03.891503 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5843 10:02:03.894837 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5844 10:02:03.898204 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5845 10:02:03.901094 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5846 10:02:03.907604 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5847 10:02:03.911212 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5848 10:02:03.911314 ==
5849 10:02:03.914430 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 10:02:03.917730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 10:02:03.917842 ==
5852 10:02:03.920926 DQS Delay:
5853 10:02:03.921004 DQS0 = 0, DQS1 = 0
5854 10:02:03.921109 DQM Delay:
5855 10:02:03.924304 DQM0 = 94, DQM1 = 88
5856 10:02:03.924386 DQ Delay:
5857 10:02:03.927405 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5858 10:02:03.931053 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5859 10:02:03.934182 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5860 10:02:03.937356 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5861 10:02:03.937456
5862 10:02:03.937561
5863 10:02:03.937653 ==
5864 10:02:03.940707 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 10:02:03.947245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 10:02:03.947327 ==
5867 10:02:03.947392
5868 10:02:03.947453
5869 10:02:03.947526 TX Vref Scan disable
5870 10:02:03.951036 == TX Byte 0 ==
5871 10:02:03.954192 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5872 10:02:03.960668 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5873 10:02:03.960753 == TX Byte 1 ==
5874 10:02:03.964409 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5875 10:02:03.970534 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5876 10:02:03.970620 ==
5877 10:02:03.973915 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 10:02:03.977142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 10:02:03.977227 ==
5880 10:02:03.977296
5881 10:02:03.977358
5882 10:02:03.980317 TX Vref Scan disable
5883 10:02:03.983987 == TX Byte 0 ==
5884 10:02:03.987061 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5885 10:02:03.990350 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5886 10:02:03.993617 == TX Byte 1 ==
5887 10:02:03.996979 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5888 10:02:04.000408 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5889 10:02:04.000492
5890 10:02:04.000560 [DATLAT]
5891 10:02:04.003925 Freq=933, CH1 RK1
5892 10:02:04.004009
5893 10:02:04.006750 DATLAT Default: 0xb
5894 10:02:04.006844 0, 0xFFFF, sum = 0
5895 10:02:04.010145 1, 0xFFFF, sum = 0
5896 10:02:04.010231 2, 0xFFFF, sum = 0
5897 10:02:04.013737 3, 0xFFFF, sum = 0
5898 10:02:04.013822 4, 0xFFFF, sum = 0
5899 10:02:04.016702 5, 0xFFFF, sum = 0
5900 10:02:04.016788 6, 0xFFFF, sum = 0
5901 10:02:04.020163 7, 0xFFFF, sum = 0
5902 10:02:04.020249 8, 0xFFFF, sum = 0
5903 10:02:04.023371 9, 0xFFFF, sum = 0
5904 10:02:04.023457 10, 0x0, sum = 1
5905 10:02:04.026543 11, 0x0, sum = 2
5906 10:02:04.026628 12, 0x0, sum = 3
5907 10:02:04.029847 13, 0x0, sum = 4
5908 10:02:04.029932 best_step = 11
5909 10:02:04.030000
5910 10:02:04.030063 ==
5911 10:02:04.033425 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 10:02:04.036493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 10:02:04.036578 ==
5914 10:02:04.039770 RX Vref Scan: 0
5915 10:02:04.039854
5916 10:02:04.043457 RX Vref 0 -> 0, step: 1
5917 10:02:04.043544
5918 10:02:04.043611 RX Delay -69 -> 252, step: 4
5919 10:02:04.051277 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5920 10:02:04.054451 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5921 10:02:04.058118 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5922 10:02:04.061370 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5923 10:02:04.064611 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5924 10:02:04.071030 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5925 10:02:04.074349 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5926 10:02:04.077278 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5927 10:02:04.080753 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5928 10:02:04.083968 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5929 10:02:04.090870 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5930 10:02:04.093867 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5931 10:02:04.097900 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5932 10:02:04.100648 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5933 10:02:04.104167 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5934 10:02:04.107264 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5935 10:02:04.110561 ==
5936 10:02:04.114129 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 10:02:04.117085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 10:02:04.117160 ==
5939 10:02:04.117224 DQS Delay:
5940 10:02:04.120424 DQS0 = 0, DQS1 = 0
5941 10:02:04.120522 DQM Delay:
5942 10:02:04.124011 DQM0 = 91, DQM1 = 90
5943 10:02:04.124126 DQ Delay:
5944 10:02:04.127531 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5945 10:02:04.130629 DQ4 =90, DQ5 =102, DQ6 =102, DQ7 =88
5946 10:02:04.133800 DQ8 =78, DQ9 =82, DQ10 =94, DQ11 =84
5947 10:02:04.136987 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5948 10:02:04.137060
5949 10:02:04.137135
5950 10:02:04.143347 [DQSOSCAuto] RK1, (LSB)MR18= 0xb1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
5951 10:02:04.147006 CH1 RK1: MR19=505, MR18=B1F
5952 10:02:04.153237 CH1_RK1: MR19=0x505, MR18=0xB1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5953 10:02:04.156850 [RxdqsGatingPostProcess] freq 933
5954 10:02:04.163178 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5955 10:02:04.166354 best DQS0 dly(2T, 0.5T) = (0, 10)
5956 10:02:04.166454 best DQS1 dly(2T, 0.5T) = (0, 10)
5957 10:02:04.169504 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5958 10:02:04.172782 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5959 10:02:04.176444 best DQS0 dly(2T, 0.5T) = (0, 10)
5960 10:02:04.179619 best DQS1 dly(2T, 0.5T) = (0, 10)
5961 10:02:04.182887 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5962 10:02:04.186083 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5963 10:02:04.189358 Pre-setting of DQS Precalculation
5964 10:02:04.196026 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5965 10:02:04.202373 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5966 10:02:04.209205 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5967 10:02:04.209292
5968 10:02:04.209358
5969 10:02:04.212218 [Calibration Summary] 1866 Mbps
5970 10:02:04.212299 CH 0, Rank 0
5971 10:02:04.215750 SW Impedance : PASS
5972 10:02:04.218871 DUTY Scan : NO K
5973 10:02:04.218945 ZQ Calibration : PASS
5974 10:02:04.222162 Jitter Meter : NO K
5975 10:02:04.225698 CBT Training : PASS
5976 10:02:04.225772 Write leveling : PASS
5977 10:02:04.228734 RX DQS gating : PASS
5978 10:02:04.232157 RX DQ/DQS(RDDQC) : PASS
5979 10:02:04.232241 TX DQ/DQS : PASS
5980 10:02:04.235408 RX DATLAT : PASS
5981 10:02:04.238680 RX DQ/DQS(Engine): PASS
5982 10:02:04.238764 TX OE : NO K
5983 10:02:04.241662 All Pass.
5984 10:02:04.241747
5985 10:02:04.241813 CH 0, Rank 1
5986 10:02:04.245322 SW Impedance : PASS
5987 10:02:04.245406 DUTY Scan : NO K
5988 10:02:04.248551 ZQ Calibration : PASS
5989 10:02:04.251824 Jitter Meter : NO K
5990 10:02:04.251908 CBT Training : PASS
5991 10:02:04.255022 Write leveling : PASS
5992 10:02:04.258606 RX DQS gating : PASS
5993 10:02:04.258697 RX DQ/DQS(RDDQC) : PASS
5994 10:02:04.261816 TX DQ/DQS : PASS
5995 10:02:04.264950 RX DATLAT : PASS
5996 10:02:04.265034 RX DQ/DQS(Engine): PASS
5997 10:02:04.268120 TX OE : NO K
5998 10:02:04.268204 All Pass.
5999 10:02:04.268272
6000 10:02:04.271413 CH 1, Rank 0
6001 10:02:04.271496 SW Impedance : PASS
6002 10:02:04.275229 DUTY Scan : NO K
6003 10:02:04.278295 ZQ Calibration : PASS
6004 10:02:04.278379 Jitter Meter : NO K
6005 10:02:04.281374 CBT Training : PASS
6006 10:02:04.284728 Write leveling : PASS
6007 10:02:04.284811 RX DQS gating : PASS
6008 10:02:04.287931 RX DQ/DQS(RDDQC) : PASS
6009 10:02:04.288016 TX DQ/DQS : PASS
6010 10:02:04.291297 RX DATLAT : PASS
6011 10:02:04.294519 RX DQ/DQS(Engine): PASS
6012 10:02:04.294603 TX OE : NO K
6013 10:02:04.298074 All Pass.
6014 10:02:04.298158
6015 10:02:04.298226 CH 1, Rank 1
6016 10:02:04.301261 SW Impedance : PASS
6017 10:02:04.301345 DUTY Scan : NO K
6018 10:02:04.304938 ZQ Calibration : PASS
6019 10:02:04.308211 Jitter Meter : NO K
6020 10:02:04.308296 CBT Training : PASS
6021 10:02:04.311781 Write leveling : PASS
6022 10:02:04.314501 RX DQS gating : PASS
6023 10:02:04.314585 RX DQ/DQS(RDDQC) : PASS
6024 10:02:04.317877 TX DQ/DQS : PASS
6025 10:02:04.321398 RX DATLAT : PASS
6026 10:02:04.321482 RX DQ/DQS(Engine): PASS
6027 10:02:04.324420 TX OE : NO K
6028 10:02:04.324504 All Pass.
6029 10:02:04.324572
6030 10:02:04.327408 DramC Write-DBI off
6031 10:02:04.330610 PER_BANK_REFRESH: Hybrid Mode
6032 10:02:04.330693 TX_TRACKING: ON
6033 10:02:04.340909 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6034 10:02:04.344356 [FAST_K] Save calibration result to emmc
6035 10:02:04.347378 dramc_set_vcore_voltage set vcore to 650000
6036 10:02:04.350468 Read voltage for 400, 6
6037 10:02:04.350551 Vio18 = 0
6038 10:02:04.350619 Vcore = 650000
6039 10:02:04.354265 Vdram = 0
6040 10:02:04.354348 Vddq = 0
6041 10:02:04.354415 Vmddr = 0
6042 10:02:04.360645 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6043 10:02:04.363740 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6044 10:02:04.367039 MEM_TYPE=3, freq_sel=20
6045 10:02:04.370206 sv_algorithm_assistance_LP4_800
6046 10:02:04.373926 ============ PULL DRAM RESETB DOWN ============
6047 10:02:04.380237 ========== PULL DRAM RESETB DOWN end =========
6048 10:02:04.383856 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6049 10:02:04.387077 ===================================
6050 10:02:04.390302 LPDDR4 DRAM CONFIGURATION
6051 10:02:04.393311 ===================================
6052 10:02:04.393437 EX_ROW_EN[0] = 0x0
6053 10:02:04.396932 EX_ROW_EN[1] = 0x0
6054 10:02:04.397016 LP4Y_EN = 0x0
6055 10:02:04.399816 WORK_FSP = 0x0
6056 10:02:04.399900 WL = 0x2
6057 10:02:04.403311 RL = 0x2
6058 10:02:04.406728 BL = 0x2
6059 10:02:04.406868 RPST = 0x0
6060 10:02:04.409971 RD_PRE = 0x0
6061 10:02:04.410057 WR_PRE = 0x1
6062 10:02:04.413517 WR_PST = 0x0
6063 10:02:04.413596 DBI_WR = 0x0
6064 10:02:04.416379 DBI_RD = 0x0
6065 10:02:04.416465 OTF = 0x1
6066 10:02:04.419870 ===================================
6067 10:02:04.422821 ===================================
6068 10:02:04.426221 ANA top config
6069 10:02:04.429751 ===================================
6070 10:02:04.429834 DLL_ASYNC_EN = 0
6071 10:02:04.432782 ALL_SLAVE_EN = 1
6072 10:02:04.436251 NEW_RANK_MODE = 1
6073 10:02:04.439475 DLL_IDLE_MODE = 1
6074 10:02:04.442531 LP45_APHY_COMB_EN = 1
6075 10:02:04.442619 TX_ODT_DIS = 1
6076 10:02:04.445986 NEW_8X_MODE = 1
6077 10:02:04.449044 ===================================
6078 10:02:04.452574 ===================================
6079 10:02:04.455841 data_rate = 800
6080 10:02:04.458971 CKR = 1
6081 10:02:04.462639 DQ_P2S_RATIO = 4
6082 10:02:04.465731 ===================================
6083 10:02:04.468815 CA_P2S_RATIO = 4
6084 10:02:04.468909 DQ_CA_OPEN = 0
6085 10:02:04.472055 DQ_SEMI_OPEN = 1
6086 10:02:04.475421 CA_SEMI_OPEN = 1
6087 10:02:04.478558 CA_FULL_RATE = 0
6088 10:02:04.482303 DQ_CKDIV4_EN = 0
6089 10:02:04.485485 CA_CKDIV4_EN = 1
6090 10:02:04.485565 CA_PREDIV_EN = 0
6091 10:02:04.488756 PH8_DLY = 0
6092 10:02:04.492003 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6093 10:02:04.495239 DQ_AAMCK_DIV = 0
6094 10:02:04.498356 CA_AAMCK_DIV = 0
6095 10:02:04.502088 CA_ADMCK_DIV = 4
6096 10:02:04.502173 DQ_TRACK_CA_EN = 0
6097 10:02:04.505099 CA_PICK = 800
6098 10:02:04.508632 CA_MCKIO = 400
6099 10:02:04.511645 MCKIO_SEMI = 400
6100 10:02:04.514709 PLL_FREQ = 3016
6101 10:02:04.518377 DQ_UI_PI_RATIO = 32
6102 10:02:04.521560 CA_UI_PI_RATIO = 32
6103 10:02:04.524908 ===================================
6104 10:02:04.528045 ===================================
6105 10:02:04.531351 memory_type:LPDDR4
6106 10:02:04.531435 GP_NUM : 10
6107 10:02:04.534405 SRAM_EN : 1
6108 10:02:04.534489 MD32_EN : 0
6109 10:02:04.538010 ===================================
6110 10:02:04.541307 [ANA_INIT] >>>>>>>>>>>>>>
6111 10:02:04.544302 <<<<<< [CONFIGURE PHASE]: ANA_TX
6112 10:02:04.547803 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6113 10:02:04.550706 ===================================
6114 10:02:04.554699 data_rate = 800,PCW = 0X7400
6115 10:02:04.557447 ===================================
6116 10:02:04.561449 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6117 10:02:04.567550 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6118 10:02:04.577354 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6119 10:02:04.580675 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6120 10:02:04.583769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6121 10:02:04.590887 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6122 10:02:04.590971 [ANA_INIT] flow start
6123 10:02:04.594109 [ANA_INIT] PLL >>>>>>>>
6124 10:02:04.594193 [ANA_INIT] PLL <<<<<<<<
6125 10:02:04.597074 [ANA_INIT] MIDPI >>>>>>>>
6126 10:02:04.600310 [ANA_INIT] MIDPI <<<<<<<<
6127 10:02:04.603792 [ANA_INIT] DLL >>>>>>>>
6128 10:02:04.603877 [ANA_INIT] flow end
6129 10:02:04.606953 ============ LP4 DIFF to SE enter ============
6130 10:02:04.613801 ============ LP4 DIFF to SE exit ============
6131 10:02:04.613886 [ANA_INIT] <<<<<<<<<<<<<
6132 10:02:04.616927 [Flow] Enable top DCM control >>>>>
6133 10:02:04.620514 [Flow] Enable top DCM control <<<<<
6134 10:02:04.623832 Enable DLL master slave shuffle
6135 10:02:04.630198 ==============================================================
6136 10:02:04.633431 Gating Mode config
6137 10:02:04.636951 ==============================================================
6138 10:02:04.639834 Config description:
6139 10:02:04.649711 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6140 10:02:04.656655 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6141 10:02:04.659850 SELPH_MODE 0: By rank 1: By Phase
6142 10:02:04.666266 ==============================================================
6143 10:02:04.669525 GAT_TRACK_EN = 0
6144 10:02:04.673228 RX_GATING_MODE = 2
6145 10:02:04.676259 RX_GATING_TRACK_MODE = 2
6146 10:02:04.679434 SELPH_MODE = 1
6147 10:02:04.679518 PICG_EARLY_EN = 1
6148 10:02:04.682702 VALID_LAT_VALUE = 1
6149 10:02:04.689568 ==============================================================
6150 10:02:04.692798 Enter into Gating configuration >>>>
6151 10:02:04.696018 Exit from Gating configuration <<<<
6152 10:02:04.699291 Enter into DVFS_PRE_config >>>>>
6153 10:02:04.709067 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6154 10:02:04.712390 Exit from DVFS_PRE_config <<<<<
6155 10:02:04.716068 Enter into PICG configuration >>>>
6156 10:02:04.719921 Exit from PICG configuration <<<<
6157 10:02:04.722287 [RX_INPUT] configuration >>>>>
6158 10:02:04.725937 [RX_INPUT] configuration <<<<<
6159 10:02:04.728981 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6160 10:02:04.735912 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6161 10:02:04.742235 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6162 10:02:04.749139 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6163 10:02:04.755713 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6164 10:02:04.762227 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6165 10:02:04.765183 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6166 10:02:04.768529 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6167 10:02:04.772025 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6168 10:02:04.778317 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6169 10:02:04.781912 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6170 10:02:04.785253 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6171 10:02:04.788263 ===================================
6172 10:02:04.792050 LPDDR4 DRAM CONFIGURATION
6173 10:02:04.795184 ===================================
6174 10:02:04.795269 EX_ROW_EN[0] = 0x0
6175 10:02:04.798347 EX_ROW_EN[1] = 0x0
6176 10:02:04.801735 LP4Y_EN = 0x0
6177 10:02:04.801845 WORK_FSP = 0x0
6178 10:02:04.804893 WL = 0x2
6179 10:02:04.804977 RL = 0x2
6180 10:02:04.808239 BL = 0x2
6181 10:02:04.808324 RPST = 0x0
6182 10:02:04.811802 RD_PRE = 0x0
6183 10:02:04.811886 WR_PRE = 0x1
6184 10:02:04.814905 WR_PST = 0x0
6185 10:02:04.814989 DBI_WR = 0x0
6186 10:02:04.818392 DBI_RD = 0x0
6187 10:02:04.818476 OTF = 0x1
6188 10:02:04.821339 ===================================
6189 10:02:04.824796 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6190 10:02:04.831131 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6191 10:02:04.834757 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6192 10:02:04.838062 ===================================
6193 10:02:04.841504 LPDDR4 DRAM CONFIGURATION
6194 10:02:04.844516 ===================================
6195 10:02:04.844600 EX_ROW_EN[0] = 0x10
6196 10:02:04.847743 EX_ROW_EN[1] = 0x0
6197 10:02:04.851105 LP4Y_EN = 0x0
6198 10:02:04.851189 WORK_FSP = 0x0
6199 10:02:04.854149 WL = 0x2
6200 10:02:04.854261 RL = 0x2
6201 10:02:04.857674 BL = 0x2
6202 10:02:04.857757 RPST = 0x0
6203 10:02:04.860725 RD_PRE = 0x0
6204 10:02:04.860809 WR_PRE = 0x1
6205 10:02:04.864044 WR_PST = 0x0
6206 10:02:04.864130 DBI_WR = 0x0
6207 10:02:04.867450 DBI_RD = 0x0
6208 10:02:04.867535 OTF = 0x1
6209 10:02:04.870985 ===================================
6210 10:02:04.877351 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6211 10:02:04.881731 nWR fixed to 30
6212 10:02:04.885188 [ModeRegInit_LP4] CH0 RK0
6213 10:02:04.885272 [ModeRegInit_LP4] CH0 RK1
6214 10:02:04.888384 [ModeRegInit_LP4] CH1 RK0
6215 10:02:04.891619 [ModeRegInit_LP4] CH1 RK1
6216 10:02:04.891704 match AC timing 19
6217 10:02:04.898353 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6218 10:02:04.901743 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6219 10:02:04.904885 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6220 10:02:04.911255 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6221 10:02:04.914734 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6222 10:02:04.914818 ==
6223 10:02:04.918397 Dram Type= 6, Freq= 0, CH_0, rank 0
6224 10:02:04.921158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 10:02:04.921243 ==
6226 10:02:04.927837 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 10:02:04.934291 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6228 10:02:04.937938 [CA 0] Center 36 (8~64) winsize 57
6229 10:02:04.941074 [CA 1] Center 36 (8~64) winsize 57
6230 10:02:04.944247 [CA 2] Center 36 (8~64) winsize 57
6231 10:02:04.947916 [CA 3] Center 36 (8~64) winsize 57
6232 10:02:04.951005 [CA 4] Center 36 (8~64) winsize 57
6233 10:02:04.954533 [CA 5] Center 36 (8~64) winsize 57
6234 10:02:04.954616
6235 10:02:04.957370 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6236 10:02:04.957479
6237 10:02:04.961000 [CATrainingPosCal] consider 1 rank data
6238 10:02:04.964230 u2DelayCellTimex100 = 270/100 ps
6239 10:02:04.967236 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 10:02:04.970963 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 10:02:04.974078 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 10:02:04.977191 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 10:02:04.980439 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 10:02:04.983927 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 10:02:04.984011
6246 10:02:04.990535 CA PerBit enable=1, Macro0, CA PI delay=36
6247 10:02:04.990619
6248 10:02:04.990686 [CBTSetCACLKResult] CA Dly = 36
6249 10:02:04.993694 CS Dly: 1 (0~32)
6250 10:02:04.993777 ==
6251 10:02:04.997500 Dram Type= 6, Freq= 0, CH_0, rank 1
6252 10:02:05.000424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 10:02:05.000509 ==
6254 10:02:05.006822 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6255 10:02:05.013280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6256 10:02:05.016841 [CA 0] Center 36 (8~64) winsize 57
6257 10:02:05.019920 [CA 1] Center 36 (8~64) winsize 57
6258 10:02:05.023583 [CA 2] Center 36 (8~64) winsize 57
6259 10:02:05.026770 [CA 3] Center 36 (8~64) winsize 57
6260 10:02:05.029994 [CA 4] Center 36 (8~64) winsize 57
6261 10:02:05.030077 [CA 5] Center 36 (8~64) winsize 57
6262 10:02:05.033206
6263 10:02:05.036248 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6264 10:02:05.036357
6265 10:02:05.039768 [CATrainingPosCal] consider 2 rank data
6266 10:02:05.043236 u2DelayCellTimex100 = 270/100 ps
6267 10:02:05.046349 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 10:02:05.049660 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 10:02:05.052851 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 10:02:05.056006 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 10:02:05.059325 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 10:02:05.062866 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 10:02:05.062988
6274 10:02:05.069578 CA PerBit enable=1, Macro0, CA PI delay=36
6275 10:02:05.069662
6276 10:02:05.069729 [CBTSetCACLKResult] CA Dly = 36
6277 10:02:05.072624 CS Dly: 1 (0~32)
6278 10:02:05.072708
6279 10:02:05.076180 ----->DramcWriteLeveling(PI) begin...
6280 10:02:05.076264 ==
6281 10:02:05.079360 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 10:02:05.082584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 10:02:05.082668 ==
6284 10:02:05.085576 Write leveling (Byte 0): 40 => 8
6285 10:02:05.089597 Write leveling (Byte 1): 40 => 8
6286 10:02:05.092752 DramcWriteLeveling(PI) end<-----
6287 10:02:05.092835
6288 10:02:05.092903 ==
6289 10:02:05.095725 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 10:02:05.098950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 10:02:05.102169 ==
6292 10:02:05.102252 [Gating] SW mode calibration
6293 10:02:05.112366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6294 10:02:05.115600 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6295 10:02:05.118758 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6296 10:02:05.125385 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6297 10:02:05.128583 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6298 10:02:05.131830 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6299 10:02:05.138286 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 10:02:05.141902 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 10:02:05.144876 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 10:02:05.151461 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 10:02:05.154598 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6304 10:02:05.158452 Total UI for P1: 0, mck2ui 16
6305 10:02:05.161089 best dqsien dly found for B0: ( 0, 14, 24)
6306 10:02:05.164992 Total UI for P1: 0, mck2ui 16
6307 10:02:05.168050 best dqsien dly found for B1: ( 0, 14, 24)
6308 10:02:05.171135 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6309 10:02:05.174439 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6310 10:02:05.174521
6311 10:02:05.177866 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6312 10:02:05.184345 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6313 10:02:05.184427 [Gating] SW calibration Done
6314 10:02:05.187748 ==
6315 10:02:05.187830 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 10:02:05.194098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 10:02:05.194181 ==
6318 10:02:05.194246 RX Vref Scan: 0
6319 10:02:05.194307
6320 10:02:05.197713 RX Vref 0 -> 0, step: 1
6321 10:02:05.197795
6322 10:02:05.200719 RX Delay -410 -> 252, step: 16
6323 10:02:05.204393 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6324 10:02:05.207679 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6325 10:02:05.214005 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6326 10:02:05.217213 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6327 10:02:05.220451 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6328 10:02:05.224173 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6329 10:02:05.230328 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6330 10:02:05.234090 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6331 10:02:05.236910 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6332 10:02:05.243820 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6333 10:02:05.246951 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6334 10:02:05.250154 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6335 10:02:05.253692 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6336 10:02:05.260337 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6337 10:02:05.263814 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6338 10:02:05.266882 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6339 10:02:05.266965 ==
6340 10:02:05.270007 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 10:02:05.277033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 10:02:05.277118 ==
6343 10:02:05.277186 DQS Delay:
6344 10:02:05.280134 DQS0 = 59, DQS1 = 59
6345 10:02:05.280218 DQM Delay:
6346 10:02:05.280285 DQM0 = 18, DQM1 = 10
6347 10:02:05.283187 DQ Delay:
6348 10:02:05.286661 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6349 10:02:05.289701 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6350 10:02:05.289785 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6351 10:02:05.296139 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6352 10:02:05.296223
6353 10:02:05.296290
6354 10:02:05.296352 ==
6355 10:02:05.299747 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 10:02:05.303232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 10:02:05.303348 ==
6358 10:02:05.303431
6359 10:02:05.303507
6360 10:02:05.306200 TX Vref Scan disable
6361 10:02:05.306283 == TX Byte 0 ==
6362 10:02:05.312658 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 10:02:05.315854 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 10:02:05.315938 == TX Byte 1 ==
6365 10:02:05.319517 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6366 10:02:05.326048 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6367 10:02:05.326132 ==
6368 10:02:05.329150 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 10:02:05.332633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 10:02:05.332743 ==
6371 10:02:05.332839
6372 10:02:05.332931
6373 10:02:05.335855 TX Vref Scan disable
6374 10:02:05.335941 == TX Byte 0 ==
6375 10:02:05.342361 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 10:02:05.346168 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 10:02:05.346251 == TX Byte 1 ==
6378 10:02:05.352577 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6379 10:02:05.356067 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6380 10:02:05.356152
6381 10:02:05.356218 [DATLAT]
6382 10:02:05.359060 Freq=400, CH0 RK0
6383 10:02:05.359143
6384 10:02:05.359211 DATLAT Default: 0xf
6385 10:02:05.362519 0, 0xFFFF, sum = 0
6386 10:02:05.362604 1, 0xFFFF, sum = 0
6387 10:02:05.365768 2, 0xFFFF, sum = 0
6388 10:02:05.365852 3, 0xFFFF, sum = 0
6389 10:02:05.369025 4, 0xFFFF, sum = 0
6390 10:02:05.369111 5, 0xFFFF, sum = 0
6391 10:02:05.372414 6, 0xFFFF, sum = 0
6392 10:02:05.372500 7, 0xFFFF, sum = 0
6393 10:02:05.375952 8, 0xFFFF, sum = 0
6394 10:02:05.376037 9, 0xFFFF, sum = 0
6395 10:02:05.378832 10, 0xFFFF, sum = 0
6396 10:02:05.382565 11, 0xFFFF, sum = 0
6397 10:02:05.382650 12, 0xFFFF, sum = 0
6398 10:02:05.385758 13, 0x0, sum = 1
6399 10:02:05.385844 14, 0x0, sum = 2
6400 10:02:05.388763 15, 0x0, sum = 3
6401 10:02:05.388848 16, 0x0, sum = 4
6402 10:02:05.388918 best_step = 14
6403 10:02:05.388981
6404 10:02:05.392102 ==
6405 10:02:05.395315 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 10:02:05.398745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 10:02:05.398854 ==
6408 10:02:05.398937 RX Vref Scan: 1
6409 10:02:05.399001
6410 10:02:05.401777 RX Vref 0 -> 0, step: 1
6411 10:02:05.401862
6412 10:02:05.405237 RX Delay -359 -> 252, step: 8
6413 10:02:05.405320
6414 10:02:05.408830 Set Vref, RX VrefLevel [Byte0]: 62
6415 10:02:05.411832 [Byte1]: 55
6416 10:02:05.415898
6417 10:02:05.415981 Final RX Vref Byte 0 = 62 to rank0
6418 10:02:05.418870 Final RX Vref Byte 1 = 55 to rank0
6419 10:02:05.422117 Final RX Vref Byte 0 = 62 to rank1
6420 10:02:05.425707 Final RX Vref Byte 1 = 55 to rank1==
6421 10:02:05.428890 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 10:02:05.435210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 10:02:05.435294 ==
6424 10:02:05.435362 DQS Delay:
6425 10:02:05.438960 DQS0 = 60, DQS1 = 68
6426 10:02:05.439044 DQM Delay:
6427 10:02:05.439111 DQM0 = 15, DQM1 = 13
6428 10:02:05.442168 DQ Delay:
6429 10:02:05.445380 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6430 10:02:05.448596 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6431 10:02:05.451813 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6432 10:02:05.455028 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6433 10:02:05.455112
6434 10:02:05.455180
6435 10:02:05.462226 [DQSOSCAuto] RK0, (LSB)MR18= 0x8786, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6436 10:02:05.465121 CH0 RK0: MR19=C0C, MR18=8786
6437 10:02:05.471839 CH0_RK0: MR19=0xC0C, MR18=0x8786, DQSOSC=392, MR23=63, INC=384, DEC=256
6438 10:02:05.471957 ==
6439 10:02:05.474695 Dram Type= 6, Freq= 0, CH_0, rank 1
6440 10:02:05.478736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 10:02:05.478821 ==
6442 10:02:05.481429 [Gating] SW mode calibration
6443 10:02:05.487967 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6444 10:02:05.494748 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6445 10:02:05.498118 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6446 10:02:05.501135 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6447 10:02:05.507696 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 10:02:05.511528 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6449 10:02:05.514983 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 10:02:05.521282 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 10:02:05.524193 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 10:02:05.527893 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 10:02:05.534314 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6454 10:02:05.537367 Total UI for P1: 0, mck2ui 16
6455 10:02:05.540863 best dqsien dly found for B0: ( 0, 14, 24)
6456 10:02:05.544095 Total UI for P1: 0, mck2ui 16
6457 10:02:05.547377 best dqsien dly found for B1: ( 0, 14, 24)
6458 10:02:05.550520 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6459 10:02:05.554389 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6460 10:02:05.554495
6461 10:02:05.557683 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6462 10:02:05.560820 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6463 10:02:05.563855 [Gating] SW calibration Done
6464 10:02:05.563934 ==
6465 10:02:05.567425 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 10:02:05.570350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 10:02:05.570455 ==
6468 10:02:05.574040 RX Vref Scan: 0
6469 10:02:05.574144
6470 10:02:05.577043 RX Vref 0 -> 0, step: 1
6471 10:02:05.577145
6472 10:02:05.577243 RX Delay -410 -> 252, step: 16
6473 10:02:05.584171 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6474 10:02:05.587356 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6475 10:02:05.590550 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6476 10:02:05.593929 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6477 10:02:05.600705 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6478 10:02:05.603639 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6479 10:02:05.607266 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6480 10:02:05.613701 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6481 10:02:05.617194 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6482 10:02:05.620374 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6483 10:02:05.623352 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6484 10:02:05.630378 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6485 10:02:05.633735 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6486 10:02:05.636930 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6487 10:02:05.640057 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6488 10:02:05.646749 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6489 10:02:05.646894 ==
6490 10:02:05.649994 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 10:02:05.653123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 10:02:05.653228 ==
6493 10:02:05.653327 DQS Delay:
6494 10:02:05.656383 DQS0 = 59, DQS1 = 59
6495 10:02:05.656459 DQM Delay:
6496 10:02:05.659937 DQM0 = 16, DQM1 = 10
6497 10:02:05.660025 DQ Delay:
6498 10:02:05.663199 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6499 10:02:05.666380 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6500 10:02:05.669489 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6501 10:02:05.673176 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6502 10:02:05.673282
6503 10:02:05.673376
6504 10:02:05.673468 ==
6505 10:02:05.676321 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 10:02:05.679477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 10:02:05.683077 ==
6508 10:02:05.683152
6509 10:02:05.683219
6510 10:02:05.683287 TX Vref Scan disable
6511 10:02:05.686378 == TX Byte 0 ==
6512 10:02:05.689427 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6513 10:02:05.693162 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6514 10:02:05.696342 == TX Byte 1 ==
6515 10:02:05.699291 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6516 10:02:05.702603 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6517 10:02:05.702704 ==
6518 10:02:05.706097 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 10:02:05.712557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 10:02:05.712660 ==
6521 10:02:05.712759
6522 10:02:05.712852
6523 10:02:05.712940 TX Vref Scan disable
6524 10:02:05.715981 == TX Byte 0 ==
6525 10:02:05.719433 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6526 10:02:05.722457 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6527 10:02:05.726054 == TX Byte 1 ==
6528 10:02:05.729541 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6529 10:02:05.732591 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6530 10:02:05.732691
6531 10:02:05.735706 [DATLAT]
6532 10:02:05.735796 Freq=400, CH0 RK1
6533 10:02:05.735866
6534 10:02:05.738896 DATLAT Default: 0xe
6535 10:02:05.738978 0, 0xFFFF, sum = 0
6536 10:02:05.742732 1, 0xFFFF, sum = 0
6537 10:02:05.742883 2, 0xFFFF, sum = 0
6538 10:02:05.745644 3, 0xFFFF, sum = 0
6539 10:02:05.745733 4, 0xFFFF, sum = 0
6540 10:02:05.749077 5, 0xFFFF, sum = 0
6541 10:02:05.749180 6, 0xFFFF, sum = 0
6542 10:02:05.752506 7, 0xFFFF, sum = 0
6543 10:02:05.752614 8, 0xFFFF, sum = 0
6544 10:02:05.755724 9, 0xFFFF, sum = 0
6545 10:02:05.758930 10, 0xFFFF, sum = 0
6546 10:02:05.759031 11, 0xFFFF, sum = 0
6547 10:02:05.761998 12, 0xFFFF, sum = 0
6548 10:02:05.762107 13, 0x0, sum = 1
6549 10:02:05.765351 14, 0x0, sum = 2
6550 10:02:05.765453 15, 0x0, sum = 3
6551 10:02:05.765567 16, 0x0, sum = 4
6552 10:02:05.768482 best_step = 14
6553 10:02:05.768569
6554 10:02:05.768633 ==
6555 10:02:05.772129 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 10:02:05.775353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 10:02:05.775454 ==
6558 10:02:05.778312 RX Vref Scan: 0
6559 10:02:05.778414
6560 10:02:05.782034 RX Vref 0 -> 0, step: 1
6561 10:02:05.782138
6562 10:02:05.782234 RX Delay -359 -> 252, step: 8
6563 10:02:05.790977 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6564 10:02:05.793648 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6565 10:02:05.797311 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6566 10:02:05.803679 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6567 10:02:05.807255 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6568 10:02:05.810454 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6569 10:02:05.813676 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6570 10:02:05.820048 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6571 10:02:05.823379 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6572 10:02:05.826669 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6573 10:02:05.830236 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6574 10:02:05.836815 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6575 10:02:05.840005 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6576 10:02:05.843383 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6577 10:02:05.846612 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6578 10:02:05.853275 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6579 10:02:05.853379 ==
6580 10:02:05.856560 Dram Type= 6, Freq= 0, CH_0, rank 1
6581 10:02:05.859778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 10:02:05.859853 ==
6583 10:02:05.859918 DQS Delay:
6584 10:02:05.862934 DQS0 = 60, DQS1 = 72
6585 10:02:05.863037 DQM Delay:
6586 10:02:05.866251 DQM0 = 11, DQM1 = 18
6587 10:02:05.866350 DQ Delay:
6588 10:02:05.869421 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6589 10:02:05.873131 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6590 10:02:05.876356 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6591 10:02:05.879482 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6592 10:02:05.879588
6593 10:02:05.879682
6594 10:02:05.889316 [DQSOSCAuto] RK1, (LSB)MR18= 0xc87f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 385 ps
6595 10:02:05.889422 CH0 RK1: MR19=C0C, MR18=C87F
6596 10:02:05.895925 CH0_RK1: MR19=0xC0C, MR18=0xC87F, DQSOSC=385, MR23=63, INC=398, DEC=265
6597 10:02:05.899126 [RxdqsGatingPostProcess] freq 400
6598 10:02:05.905663 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6599 10:02:05.908824 best DQS0 dly(2T, 0.5T) = (0, 10)
6600 10:02:05.912007 best DQS1 dly(2T, 0.5T) = (0, 10)
6601 10:02:05.915167 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6602 10:02:05.918988 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6603 10:02:05.922029 best DQS0 dly(2T, 0.5T) = (0, 10)
6604 10:02:05.925317 best DQS1 dly(2T, 0.5T) = (0, 10)
6605 10:02:05.928646 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6606 10:02:05.932080 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6607 10:02:05.932156 Pre-setting of DQS Precalculation
6608 10:02:05.938494 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6609 10:02:05.938601 ==
6610 10:02:05.941670 Dram Type= 6, Freq= 0, CH_1, rank 0
6611 10:02:05.945229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 10:02:05.945341 ==
6613 10:02:05.951710 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 10:02:05.958553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6615 10:02:05.961722 [CA 0] Center 36 (8~64) winsize 57
6616 10:02:05.964971 [CA 1] Center 36 (8~64) winsize 57
6617 10:02:05.968227 [CA 2] Center 36 (8~64) winsize 57
6618 10:02:05.971446 [CA 3] Center 36 (8~64) winsize 57
6619 10:02:05.975216 [CA 4] Center 36 (8~64) winsize 57
6620 10:02:05.975325 [CA 5] Center 36 (8~64) winsize 57
6621 10:02:05.978401
6622 10:02:05.981679 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6623 10:02:05.981784
6624 10:02:05.984750 [CATrainingPosCal] consider 1 rank data
6625 10:02:05.988347 u2DelayCellTimex100 = 270/100 ps
6626 10:02:05.991440 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 10:02:05.994656 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 10:02:05.997938 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 10:02:06.001127 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 10:02:06.005017 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 10:02:06.008108 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 10:02:06.008213
6633 10:02:06.011604 CA PerBit enable=1, Macro0, CA PI delay=36
6634 10:02:06.011677
6635 10:02:06.014474 [CBTSetCACLKResult] CA Dly = 36
6636 10:02:06.017737 CS Dly: 1 (0~32)
6637 10:02:06.017837 ==
6638 10:02:06.021384 Dram Type= 6, Freq= 0, CH_1, rank 1
6639 10:02:06.024459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 10:02:06.024560 ==
6641 10:02:06.030919 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6642 10:02:06.037715 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6643 10:02:06.041201 [CA 0] Center 36 (8~64) winsize 57
6644 10:02:06.044212 [CA 1] Center 36 (8~64) winsize 57
6645 10:02:06.047702 [CA 2] Center 36 (8~64) winsize 57
6646 10:02:06.047809 [CA 3] Center 36 (8~64) winsize 57
6647 10:02:06.050521 [CA 4] Center 36 (8~64) winsize 57
6648 10:02:06.054169 [CA 5] Center 36 (8~64) winsize 57
6649 10:02:06.054259
6650 10:02:06.060783 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6651 10:02:06.060888
6652 10:02:06.064514 [CATrainingPosCal] consider 2 rank data
6653 10:02:06.067797 u2DelayCellTimex100 = 270/100 ps
6654 10:02:06.070767 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 10:02:06.074026 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 10:02:06.077097 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 10:02:06.080303 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 10:02:06.084075 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 10:02:06.087220 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 10:02:06.087309
6661 10:02:06.090241 CA PerBit enable=1, Macro0, CA PI delay=36
6662 10:02:06.090349
6663 10:02:06.093907 [CBTSetCACLKResult] CA Dly = 36
6664 10:02:06.097187 CS Dly: 1 (0~32)
6665 10:02:06.097300
6666 10:02:06.100381 ----->DramcWriteLeveling(PI) begin...
6667 10:02:06.100459 ==
6668 10:02:06.103674 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 10:02:06.106806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 10:02:06.106907 ==
6671 10:02:06.109964 Write leveling (Byte 0): 40 => 8
6672 10:02:06.113413 Write leveling (Byte 1): 40 => 8
6673 10:02:06.116638 DramcWriteLeveling(PI) end<-----
6674 10:02:06.116716
6675 10:02:06.116789 ==
6676 10:02:06.119777 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 10:02:06.122980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 10:02:06.123057 ==
6679 10:02:06.126699 [Gating] SW mode calibration
6680 10:02:06.133406 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6681 10:02:06.139768 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6682 10:02:06.143163 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6683 10:02:06.149663 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6684 10:02:06.152703 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6685 10:02:06.156139 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6686 10:02:06.162671 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 10:02:06.166446 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 10:02:06.169319 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 10:02:06.176047 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 10:02:06.178959 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6691 10:02:06.182612 Total UI for P1: 0, mck2ui 16
6692 10:02:06.186033 best dqsien dly found for B0: ( 0, 14, 24)
6693 10:02:06.189143 Total UI for P1: 0, mck2ui 16
6694 10:02:06.192374 best dqsien dly found for B1: ( 0, 14, 24)
6695 10:02:06.195699 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6696 10:02:06.199009 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6697 10:02:06.199110
6698 10:02:06.202206 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6699 10:02:06.205397 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6700 10:02:06.208972 [Gating] SW calibration Done
6701 10:02:06.209078 ==
6702 10:02:06.212345 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 10:02:06.218520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 10:02:06.218596 ==
6705 10:02:06.218659 RX Vref Scan: 0
6706 10:02:06.218746
6707 10:02:06.221685 RX Vref 0 -> 0, step: 1
6708 10:02:06.221770
6709 10:02:06.225343 RX Delay -410 -> 252, step: 16
6710 10:02:06.228348 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6711 10:02:06.232069 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6712 10:02:06.238250 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6713 10:02:06.241722 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6714 10:02:06.244686 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6715 10:02:06.248179 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6716 10:02:06.254818 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6717 10:02:06.257746 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6718 10:02:06.261113 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6719 10:02:06.264590 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6720 10:02:06.271343 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6721 10:02:06.274337 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6722 10:02:06.277963 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6723 10:02:06.281101 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6724 10:02:06.287505 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6725 10:02:06.290768 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6726 10:02:06.290887 ==
6727 10:02:06.294396 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 10:02:06.297570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 10:02:06.297655 ==
6730 10:02:06.301149 DQS Delay:
6731 10:02:06.301248 DQS0 = 51, DQS1 = 67
6732 10:02:06.304406 DQM Delay:
6733 10:02:06.304521 DQM0 = 12, DQM1 = 18
6734 10:02:06.307676 DQ Delay:
6735 10:02:06.307760 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6736 10:02:06.310969 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6737 10:02:06.313959 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6738 10:02:06.317654 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6739 10:02:06.317738
6740 10:02:06.317804
6741 10:02:06.320529 ==
6742 10:02:06.320613 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 10:02:06.327276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 10:02:06.327363 ==
6745 10:02:06.327469
6746 10:02:06.327562
6747 10:02:06.330756 TX Vref Scan disable
6748 10:02:06.330849 == TX Byte 0 ==
6749 10:02:06.333742 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 10:02:06.340143 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 10:02:06.340226 == TX Byte 1 ==
6752 10:02:06.343875 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 10:02:06.350346 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 10:02:06.350446 ==
6755 10:02:06.353750 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 10:02:06.356744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 10:02:06.356829 ==
6758 10:02:06.356896
6759 10:02:06.356958
6760 10:02:06.360157 TX Vref Scan disable
6761 10:02:06.360241 == TX Byte 0 ==
6762 10:02:06.363810 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 10:02:06.370181 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 10:02:06.370264 == TX Byte 1 ==
6765 10:02:06.373239 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 10:02:06.379953 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 10:02:06.380037
6768 10:02:06.380104 [DATLAT]
6769 10:02:06.380168 Freq=400, CH1 RK0
6770 10:02:06.380229
6771 10:02:06.383483 DATLAT Default: 0xf
6772 10:02:06.386700 0, 0xFFFF, sum = 0
6773 10:02:06.386785 1, 0xFFFF, sum = 0
6774 10:02:06.390132 2, 0xFFFF, sum = 0
6775 10:02:06.390217 3, 0xFFFF, sum = 0
6776 10:02:06.392989 4, 0xFFFF, sum = 0
6777 10:02:06.393075 5, 0xFFFF, sum = 0
6778 10:02:06.396326 6, 0xFFFF, sum = 0
6779 10:02:06.396411 7, 0xFFFF, sum = 0
6780 10:02:06.399890 8, 0xFFFF, sum = 0
6781 10:02:06.399975 9, 0xFFFF, sum = 0
6782 10:02:06.402894 10, 0xFFFF, sum = 0
6783 10:02:06.402979 11, 0xFFFF, sum = 0
6784 10:02:06.406619 12, 0xFFFF, sum = 0
6785 10:02:06.406718 13, 0x0, sum = 1
6786 10:02:06.409805 14, 0x0, sum = 2
6787 10:02:06.409891 15, 0x0, sum = 3
6788 10:02:06.412935 16, 0x0, sum = 4
6789 10:02:06.413020 best_step = 14
6790 10:02:06.413088
6791 10:02:06.413149 ==
6792 10:02:06.416213 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 10:02:06.422789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 10:02:06.422897 ==
6795 10:02:06.422966 RX Vref Scan: 1
6796 10:02:06.423028
6797 10:02:06.425854 RX Vref 0 -> 0, step: 1
6798 10:02:06.425952
6799 10:02:06.429143 RX Delay -375 -> 252, step: 8
6800 10:02:06.429227
6801 10:02:06.433200 Set Vref, RX VrefLevel [Byte0]: 55
6802 10:02:06.435746 [Byte1]: 51
6803 10:02:06.439148
6804 10:02:06.439231 Final RX Vref Byte 0 = 55 to rank0
6805 10:02:06.442300 Final RX Vref Byte 1 = 51 to rank0
6806 10:02:06.445744 Final RX Vref Byte 0 = 55 to rank1
6807 10:02:06.448885 Final RX Vref Byte 1 = 51 to rank1==
6808 10:02:06.452906 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 10:02:06.459160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 10:02:06.459244 ==
6811 10:02:06.459312 DQS Delay:
6812 10:02:06.462298 DQS0 = 52, DQS1 = 64
6813 10:02:06.462382 DQM Delay:
6814 10:02:06.462449 DQM0 = 9, DQM1 = 11
6815 10:02:06.465822 DQ Delay:
6816 10:02:06.468793 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6817 10:02:06.468877 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6818 10:02:06.472446 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6819 10:02:06.475188 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6820 10:02:06.478550
6821 10:02:06.478633
6822 10:02:06.485210 [DQSOSCAuto] RK0, (LSB)MR18= 0x5265, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 399 ps
6823 10:02:06.488505 CH1 RK0: MR19=C0C, MR18=5265
6824 10:02:06.495540 CH1_RK0: MR19=0xC0C, MR18=0x5265, DQSOSC=397, MR23=63, INC=374, DEC=249
6825 10:02:06.495625 ==
6826 10:02:06.498422 Dram Type= 6, Freq= 0, CH_1, rank 1
6827 10:02:06.501651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 10:02:06.501736 ==
6829 10:02:06.504922 [Gating] SW mode calibration
6830 10:02:06.511522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6831 10:02:06.518063 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6832 10:02:06.521244 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6833 10:02:06.524447 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6834 10:02:06.531249 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6835 10:02:06.534409 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6836 10:02:06.537750 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 10:02:06.544114 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 10:02:06.547562 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 10:02:06.550700 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 10:02:06.557260 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6841 10:02:06.560859 Total UI for P1: 0, mck2ui 16
6842 10:02:06.563861 best dqsien dly found for B0: ( 0, 14, 24)
6843 10:02:06.567330 Total UI for P1: 0, mck2ui 16
6844 10:02:06.570375 best dqsien dly found for B1: ( 0, 14, 24)
6845 10:02:06.573772 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6846 10:02:06.577058 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6847 10:02:06.577142
6848 10:02:06.580606 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6849 10:02:06.583669 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6850 10:02:06.587015 [Gating] SW calibration Done
6851 10:02:06.587099 ==
6852 10:02:06.590262 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 10:02:06.593566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 10:02:06.593651 ==
6855 10:02:06.597245 RX Vref Scan: 0
6856 10:02:06.597330
6857 10:02:06.600429 RX Vref 0 -> 0, step: 1
6858 10:02:06.600514
6859 10:02:06.603690 RX Delay -410 -> 252, step: 16
6860 10:02:06.606872 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6861 10:02:06.610001 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6862 10:02:06.613556 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6863 10:02:06.620131 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6864 10:02:06.623355 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6865 10:02:06.626699 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6866 10:02:06.629913 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6867 10:02:06.636798 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6868 10:02:06.639733 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6869 10:02:06.643010 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6870 10:02:06.649318 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6871 10:02:06.652699 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6872 10:02:06.656230 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6873 10:02:06.659409 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6874 10:02:06.666313 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6875 10:02:06.669441 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6876 10:02:06.669519 ==
6877 10:02:06.672550 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 10:02:06.675981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 10:02:06.676064 ==
6880 10:02:06.679161 DQS Delay:
6881 10:02:06.679292 DQS0 = 59, DQS1 = 59
6882 10:02:06.682128 DQM Delay:
6883 10:02:06.682213 DQM0 = 19, DQM1 = 14
6884 10:02:06.682282 DQ Delay:
6885 10:02:06.685929 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6886 10:02:06.688795 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6887 10:02:06.692234 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6888 10:02:06.695728 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6889 10:02:06.695813
6890 10:02:06.695880
6891 10:02:06.695942 ==
6892 10:02:06.698729 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 10:02:06.706036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 10:02:06.706122 ==
6895 10:02:06.706190
6896 10:02:06.706275
6897 10:02:06.706349 TX Vref Scan disable
6898 10:02:06.708890 == TX Byte 0 ==
6899 10:02:06.711924 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6900 10:02:06.715497 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6901 10:02:06.718615 == TX Byte 1 ==
6902 10:02:06.721948 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6903 10:02:06.725268 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6904 10:02:06.728476 ==
6905 10:02:06.731772 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 10:02:06.735462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 10:02:06.735547 ==
6908 10:02:06.735615
6909 10:02:06.735676
6910 10:02:06.738351 TX Vref Scan disable
6911 10:02:06.738461 == TX Byte 0 ==
6912 10:02:06.741500 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6913 10:02:06.748323 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6914 10:02:06.748407 == TX Byte 1 ==
6915 10:02:06.751536 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6916 10:02:06.758094 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6917 10:02:06.758178
6918 10:02:06.758245 [DATLAT]
6919 10:02:06.758307 Freq=400, CH1 RK1
6920 10:02:06.758367
6921 10:02:06.761492 DATLAT Default: 0xe
6922 10:02:06.761603 0, 0xFFFF, sum = 0
6923 10:02:06.764493 1, 0xFFFF, sum = 0
6924 10:02:06.767805 2, 0xFFFF, sum = 0
6925 10:02:06.767890 3, 0xFFFF, sum = 0
6926 10:02:06.771321 4, 0xFFFF, sum = 0
6927 10:02:06.771406 5, 0xFFFF, sum = 0
6928 10:02:06.775019 6, 0xFFFF, sum = 0
6929 10:02:06.775104 7, 0xFFFF, sum = 0
6930 10:02:06.778102 8, 0xFFFF, sum = 0
6931 10:02:06.778217 9, 0xFFFF, sum = 0
6932 10:02:06.781526 10, 0xFFFF, sum = 0
6933 10:02:06.781611 11, 0xFFFF, sum = 0
6934 10:02:06.784836 12, 0xFFFF, sum = 0
6935 10:02:06.784922 13, 0x0, sum = 1
6936 10:02:06.788156 14, 0x0, sum = 2
6937 10:02:06.788241 15, 0x0, sum = 3
6938 10:02:06.791119 16, 0x0, sum = 4
6939 10:02:06.791204 best_step = 14
6940 10:02:06.791272
6941 10:02:06.791334 ==
6942 10:02:06.794665 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 10:02:06.797662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 10:02:06.801156 ==
6945 10:02:06.801240 RX Vref Scan: 0
6946 10:02:06.801346
6947 10:02:06.805008 RX Vref 0 -> 0, step: 1
6948 10:02:06.805092
6949 10:02:06.807842 RX Delay -359 -> 252, step: 8
6950 10:02:06.814069 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6951 10:02:06.817751 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6952 10:02:06.820851 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6953 10:02:06.824189 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6954 10:02:06.830708 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6955 10:02:06.833871 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6956 10:02:06.837401 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6957 10:02:06.840717 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6958 10:02:06.847114 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6959 10:02:06.850784 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6960 10:02:06.853633 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6961 10:02:06.857027 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6962 10:02:06.864033 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6963 10:02:06.867348 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6964 10:02:06.870955 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6965 10:02:06.876873 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6966 10:02:06.876957 ==
6967 10:02:06.880104 Dram Type= 6, Freq= 0, CH_1, rank 1
6968 10:02:06.883368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6969 10:02:06.883456 ==
6970 10:02:06.883523 DQS Delay:
6971 10:02:06.886886 DQS0 = 60, DQS1 = 64
6972 10:02:06.886970 DQM Delay:
6973 10:02:06.890084 DQM0 = 12, DQM1 = 10
6974 10:02:06.890200 DQ Delay:
6975 10:02:06.893159 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6976 10:02:06.897183 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6977 10:02:06.899929 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6978 10:02:06.903215 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6979 10:02:06.903299
6980 10:02:06.903385
6981 10:02:06.909620 [DQSOSCAuto] RK1, (LSB)MR18= 0x74a4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
6982 10:02:06.913125 CH1 RK1: MR19=C0C, MR18=74A4
6983 10:02:06.919324 CH1_RK1: MR19=0xC0C, MR18=0x74A4, DQSOSC=389, MR23=63, INC=390, DEC=260
6984 10:02:06.922903 [RxdqsGatingPostProcess] freq 400
6985 10:02:06.929302 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6986 10:02:06.933007 best DQS0 dly(2T, 0.5T) = (0, 10)
6987 10:02:06.936534 best DQS1 dly(2T, 0.5T) = (0, 10)
6988 10:02:06.939334 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6989 10:02:06.942487 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6990 10:02:06.942598 best DQS0 dly(2T, 0.5T) = (0, 10)
6991 10:02:06.946040 best DQS1 dly(2T, 0.5T) = (0, 10)
6992 10:02:06.949211 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6993 10:02:06.952387 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6994 10:02:06.955465 Pre-setting of DQS Precalculation
6995 10:02:06.962650 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6996 10:02:06.969223 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6997 10:02:06.975700 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6998 10:02:06.975784
6999 10:02:06.975851
7000 10:02:06.978824 [Calibration Summary] 800 Mbps
7001 10:02:06.978948 CH 0, Rank 0
7002 10:02:06.981889 SW Impedance : PASS
7003 10:02:06.985213 DUTY Scan : NO K
7004 10:02:06.985297 ZQ Calibration : PASS
7005 10:02:06.988514 Jitter Meter : NO K
7006 10:02:06.991645 CBT Training : PASS
7007 10:02:06.991728 Write leveling : PASS
7008 10:02:06.995075 RX DQS gating : PASS
7009 10:02:06.998831 RX DQ/DQS(RDDQC) : PASS
7010 10:02:06.998916 TX DQ/DQS : PASS
7011 10:02:07.001488 RX DATLAT : PASS
7012 10:02:07.004837 RX DQ/DQS(Engine): PASS
7013 10:02:07.004920 TX OE : NO K
7014 10:02:07.008142 All Pass.
7015 10:02:07.008235
7016 10:02:07.008332 CH 0, Rank 1
7017 10:02:07.011571 SW Impedance : PASS
7018 10:02:07.011654 DUTY Scan : NO K
7019 10:02:07.015032 ZQ Calibration : PASS
7020 10:02:07.018423 Jitter Meter : NO K
7021 10:02:07.018506 CBT Training : PASS
7022 10:02:07.021320 Write leveling : NO K
7023 10:02:07.024912 RX DQS gating : PASS
7024 10:02:07.024995 RX DQ/DQS(RDDQC) : PASS
7025 10:02:07.028189 TX DQ/DQS : PASS
7026 10:02:07.031665 RX DATLAT : PASS
7027 10:02:07.031757 RX DQ/DQS(Engine): PASS
7028 10:02:07.034799 TX OE : NO K
7029 10:02:07.034929 All Pass.
7030 10:02:07.034997
7031 10:02:07.037890 CH 1, Rank 0
7032 10:02:07.037974 SW Impedance : PASS
7033 10:02:07.041114 DUTY Scan : NO K
7034 10:02:07.044965 ZQ Calibration : PASS
7035 10:02:07.045048 Jitter Meter : NO K
7036 10:02:07.048311 CBT Training : PASS
7037 10:02:07.051180 Write leveling : PASS
7038 10:02:07.051263 RX DQS gating : PASS
7039 10:02:07.054559 RX DQ/DQS(RDDQC) : PASS
7040 10:02:07.054643 TX DQ/DQS : PASS
7041 10:02:07.057633 RX DATLAT : PASS
7042 10:02:07.061341 RX DQ/DQS(Engine): PASS
7043 10:02:07.061424 TX OE : NO K
7044 10:02:07.064497 All Pass.
7045 10:02:07.064580
7046 10:02:07.064647 CH 1, Rank 1
7047 10:02:07.067673 SW Impedance : PASS
7048 10:02:07.067758 DUTY Scan : NO K
7049 10:02:07.071283 ZQ Calibration : PASS
7050 10:02:07.074957 Jitter Meter : NO K
7051 10:02:07.075040 CBT Training : PASS
7052 10:02:07.077685 Write leveling : NO K
7053 10:02:07.081089 RX DQS gating : PASS
7054 10:02:07.081172 RX DQ/DQS(RDDQC) : PASS
7055 10:02:07.084398 TX DQ/DQS : PASS
7056 10:02:07.087574 RX DATLAT : PASS
7057 10:02:07.087658 RX DQ/DQS(Engine): PASS
7058 10:02:07.090886 TX OE : NO K
7059 10:02:07.090970 All Pass.
7060 10:02:07.091038
7061 10:02:07.094558 DramC Write-DBI off
7062 10:02:07.098146 PER_BANK_REFRESH: Hybrid Mode
7063 10:02:07.098237 TX_TRACKING: ON
7064 10:02:07.107617 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7065 10:02:07.110904 [FAST_K] Save calibration result to emmc
7066 10:02:07.113949 dramc_set_vcore_voltage set vcore to 725000
7067 10:02:07.117363 Read voltage for 1600, 0
7068 10:02:07.117440 Vio18 = 0
7069 10:02:07.117506 Vcore = 725000
7070 10:02:07.120782 Vdram = 0
7071 10:02:07.120897 Vddq = 0
7072 10:02:07.120980 Vmddr = 0
7073 10:02:07.127244 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7074 10:02:07.130679 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7075 10:02:07.133835 MEM_TYPE=3, freq_sel=13
7076 10:02:07.137138 sv_algorithm_assistance_LP4_3733
7077 10:02:07.140391 ============ PULL DRAM RESETB DOWN ============
7078 10:02:07.147254 ========== PULL DRAM RESETB DOWN end =========
7079 10:02:07.150390 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7080 10:02:07.153426 ===================================
7081 10:02:07.156794 LPDDR4 DRAM CONFIGURATION
7082 10:02:07.160312 ===================================
7083 10:02:07.160396 EX_ROW_EN[0] = 0x0
7084 10:02:07.163458 EX_ROW_EN[1] = 0x0
7085 10:02:07.163541 LP4Y_EN = 0x0
7086 10:02:07.166767 WORK_FSP = 0x1
7087 10:02:07.166886 WL = 0x5
7088 10:02:07.170321 RL = 0x5
7089 10:02:07.170405 BL = 0x2
7090 10:02:07.173273 RPST = 0x0
7091 10:02:07.173364 RD_PRE = 0x0
7092 10:02:07.177029 WR_PRE = 0x1
7093 10:02:07.180282 WR_PST = 0x1
7094 10:02:07.180366 DBI_WR = 0x0
7095 10:02:07.183183 DBI_RD = 0x0
7096 10:02:07.183268 OTF = 0x1
7097 10:02:07.186611 ===================================
7098 10:02:07.190059 ===================================
7099 10:02:07.193011 ANA top config
7100 10:02:07.193095 ===================================
7101 10:02:07.196831 DLL_ASYNC_EN = 0
7102 10:02:07.199985 ALL_SLAVE_EN = 0
7103 10:02:07.203214 NEW_RANK_MODE = 1
7104 10:02:07.206357 DLL_IDLE_MODE = 1
7105 10:02:07.206441 LP45_APHY_COMB_EN = 1
7106 10:02:07.209838 TX_ODT_DIS = 0
7107 10:02:07.213003 NEW_8X_MODE = 1
7108 10:02:07.216471 ===================================
7109 10:02:07.219550 ===================================
7110 10:02:07.222983 data_rate = 3200
7111 10:02:07.225887 CKR = 1
7112 10:02:07.229318 DQ_P2S_RATIO = 8
7113 10:02:07.232761 ===================================
7114 10:02:07.232845 CA_P2S_RATIO = 8
7115 10:02:07.235734 DQ_CA_OPEN = 0
7116 10:02:07.239176 DQ_SEMI_OPEN = 0
7117 10:02:07.242345 CA_SEMI_OPEN = 0
7118 10:02:07.245770 CA_FULL_RATE = 0
7119 10:02:07.249071 DQ_CKDIV4_EN = 0
7120 10:02:07.249155 CA_CKDIV4_EN = 0
7121 10:02:07.252202 CA_PREDIV_EN = 0
7122 10:02:07.256104 PH8_DLY = 12
7123 10:02:07.258775 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7124 10:02:07.262613 DQ_AAMCK_DIV = 4
7125 10:02:07.265343 CA_AAMCK_DIV = 4
7126 10:02:07.265427 CA_ADMCK_DIV = 4
7127 10:02:07.268927 DQ_TRACK_CA_EN = 0
7128 10:02:07.272331 CA_PICK = 1600
7129 10:02:07.275332 CA_MCKIO = 1600
7130 10:02:07.278900 MCKIO_SEMI = 0
7131 10:02:07.282257 PLL_FREQ = 3068
7132 10:02:07.285534 DQ_UI_PI_RATIO = 32
7133 10:02:07.288553 CA_UI_PI_RATIO = 0
7134 10:02:07.292137 ===================================
7135 10:02:07.295051 ===================================
7136 10:02:07.295135 memory_type:LPDDR4
7137 10:02:07.298594 GP_NUM : 10
7138 10:02:07.301906 SRAM_EN : 1
7139 10:02:07.301989 MD32_EN : 0
7140 10:02:07.304987 ===================================
7141 10:02:07.308254 [ANA_INIT] >>>>>>>>>>>>>>
7142 10:02:07.311920 <<<<<< [CONFIGURE PHASE]: ANA_TX
7143 10:02:07.314892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7144 10:02:07.318112 ===================================
7145 10:02:07.321534 data_rate = 3200,PCW = 0X7600
7146 10:02:07.324964 ===================================
7147 10:02:07.328249 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7148 10:02:07.331708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7149 10:02:07.338291 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7150 10:02:07.341226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7151 10:02:07.344728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7152 10:02:07.351354 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7153 10:02:07.351438 [ANA_INIT] flow start
7154 10:02:07.354737 [ANA_INIT] PLL >>>>>>>>
7155 10:02:07.357850 [ANA_INIT] PLL <<<<<<<<
7156 10:02:07.357960 [ANA_INIT] MIDPI >>>>>>>>
7157 10:02:07.361269 [ANA_INIT] MIDPI <<<<<<<<
7158 10:02:07.364448 [ANA_INIT] DLL >>>>>>>>
7159 10:02:07.364531 [ANA_INIT] DLL <<<<<<<<
7160 10:02:07.367872 [ANA_INIT] flow end
7161 10:02:07.370998 ============ LP4 DIFF to SE enter ============
7162 10:02:07.374033 ============ LP4 DIFF to SE exit ============
7163 10:02:07.377838 [ANA_INIT] <<<<<<<<<<<<<
7164 10:02:07.380991 [Flow] Enable top DCM control >>>>>
7165 10:02:07.384079 [Flow] Enable top DCM control <<<<<
7166 10:02:07.387328 Enable DLL master slave shuffle
7167 10:02:07.394480 ==============================================================
7168 10:02:07.394592 Gating Mode config
7169 10:02:07.400733 ==============================================================
7170 10:02:07.404071 Config description:
7171 10:02:07.410340 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7172 10:02:07.417237 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7173 10:02:07.423590 SELPH_MODE 0: By rank 1: By Phase
7174 10:02:07.430143 ==============================================================
7175 10:02:07.433210 GAT_TRACK_EN = 1
7176 10:02:07.433323 RX_GATING_MODE = 2
7177 10:02:07.436588 RX_GATING_TRACK_MODE = 2
7178 10:02:07.440097 SELPH_MODE = 1
7179 10:02:07.443115 PICG_EARLY_EN = 1
7180 10:02:07.446755 VALID_LAT_VALUE = 1
7181 10:02:07.453143 ==============================================================
7182 10:02:07.456734 Enter into Gating configuration >>>>
7183 10:02:07.459868 Exit from Gating configuration <<<<
7184 10:02:07.463620 Enter into DVFS_PRE_config >>>>>
7185 10:02:07.473208 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7186 10:02:07.476342 Exit from DVFS_PRE_config <<<<<
7187 10:02:07.479572 Enter into PICG configuration >>>>
7188 10:02:07.482713 Exit from PICG configuration <<<<
7189 10:02:07.486272 [RX_INPUT] configuration >>>>>
7190 10:02:07.489402 [RX_INPUT] configuration <<<<<
7191 10:02:07.492561 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7192 10:02:07.499000 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7193 10:02:07.505633 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7194 10:02:07.512244 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7195 10:02:07.519183 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7196 10:02:07.522287 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7197 10:02:07.528679 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7198 10:02:07.532182 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7199 10:02:07.535248 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7200 10:02:07.538664 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7201 10:02:07.545129 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7202 10:02:07.548190 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7203 10:02:07.551702 ===================================
7204 10:02:07.554702 LPDDR4 DRAM CONFIGURATION
7205 10:02:07.558105 ===================================
7206 10:02:07.558202 EX_ROW_EN[0] = 0x0
7207 10:02:07.561715 EX_ROW_EN[1] = 0x0
7208 10:02:07.561801 LP4Y_EN = 0x0
7209 10:02:07.564804 WORK_FSP = 0x1
7210 10:02:07.568059 WL = 0x5
7211 10:02:07.568137 RL = 0x5
7212 10:02:07.571305 BL = 0x2
7213 10:02:07.571390 RPST = 0x0
7214 10:02:07.574729 RD_PRE = 0x0
7215 10:02:07.574814 WR_PRE = 0x1
7216 10:02:07.578058 WR_PST = 0x1
7217 10:02:07.578133 DBI_WR = 0x0
7218 10:02:07.581486 DBI_RD = 0x0
7219 10:02:07.581566 OTF = 0x1
7220 10:02:07.584471 ===================================
7221 10:02:07.588060 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7222 10:02:07.594478 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7223 10:02:07.597890 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7224 10:02:07.601167 ===================================
7225 10:02:07.604668 LPDDR4 DRAM CONFIGURATION
7226 10:02:07.607450 ===================================
7227 10:02:07.607528 EX_ROW_EN[0] = 0x10
7228 10:02:07.611115 EX_ROW_EN[1] = 0x0
7229 10:02:07.611232 LP4Y_EN = 0x0
7230 10:02:07.614297 WORK_FSP = 0x1
7231 10:02:07.617795 WL = 0x5
7232 10:02:07.617880 RL = 0x5
7233 10:02:07.620796 BL = 0x2
7234 10:02:07.620881 RPST = 0x0
7235 10:02:07.624347 RD_PRE = 0x0
7236 10:02:07.624495 WR_PRE = 0x1
7237 10:02:07.627379 WR_PST = 0x1
7238 10:02:07.627462 DBI_WR = 0x0
7239 10:02:07.630548 DBI_RD = 0x0
7240 10:02:07.630712 OTF = 0x1
7241 10:02:07.634333 ===================================
7242 10:02:07.640826 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7243 10:02:07.640911 ==
7244 10:02:07.644019 Dram Type= 6, Freq= 0, CH_0, rank 0
7245 10:02:07.647525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7246 10:02:07.647611 ==
7247 10:02:07.650761 [Duty_Offset_Calibration]
7248 10:02:07.653857 B0:2 B1:0 CA:3
7249 10:02:07.653947
7250 10:02:07.657307 [DutyScan_Calibration_Flow] k_type=0
7251 10:02:07.665666
7252 10:02:07.665750 ==CLK 0==
7253 10:02:07.668863 Final CLK duty delay cell = 0
7254 10:02:07.672315 [0] MAX Duty = 5031%(X100), DQS PI = 12
7255 10:02:07.676176 [0] MIN Duty = 4907%(X100), DQS PI = 4
7256 10:02:07.676278 [0] AVG Duty = 4969%(X100)
7257 10:02:07.678979
7258 10:02:07.682256 CH0 CLK Duty spec in!! Max-Min= 124%
7259 10:02:07.685939 [DutyScan_Calibration_Flow] ====Done====
7260 10:02:07.686023
7261 10:02:07.688667 [DutyScan_Calibration_Flow] k_type=1
7262 10:02:07.705681
7263 10:02:07.705764 ==DQS 0 ==
7264 10:02:07.708814 Final DQS duty delay cell = 0
7265 10:02:07.711973 [0] MAX Duty = 5094%(X100), DQS PI = 30
7266 10:02:07.715603 [0] MIN Duty = 4875%(X100), DQS PI = 48
7267 10:02:07.718702 [0] AVG Duty = 4984%(X100)
7268 10:02:07.718812
7269 10:02:07.718900 ==DQS 1 ==
7270 10:02:07.722113 Final DQS duty delay cell = 0
7271 10:02:07.725161 [0] MAX Duty = 5156%(X100), DQS PI = 32
7272 10:02:07.728410 [0] MIN Duty = 5031%(X100), DQS PI = 14
7273 10:02:07.731922 [0] AVG Duty = 5093%(X100)
7274 10:02:07.732006
7275 10:02:07.735084 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7276 10:02:07.735167
7277 10:02:07.738254 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7278 10:02:07.741945 [DutyScan_Calibration_Flow] ====Done====
7279 10:02:07.742028
7280 10:02:07.745335 [DutyScan_Calibration_Flow] k_type=3
7281 10:02:07.763253
7282 10:02:07.763338 ==DQM 0 ==
7283 10:02:07.766700 Final DQM duty delay cell = 0
7284 10:02:07.769775 [0] MAX Duty = 5156%(X100), DQS PI = 14
7285 10:02:07.773241 [0] MIN Duty = 4875%(X100), DQS PI = 0
7286 10:02:07.776454 [0] AVG Duty = 5015%(X100)
7287 10:02:07.776538
7288 10:02:07.776605 ==DQM 1 ==
7289 10:02:07.780200 Final DQM duty delay cell = 4
7290 10:02:07.782979 [4] MAX Duty = 5187%(X100), DQS PI = 60
7291 10:02:07.786391 [4] MIN Duty = 5031%(X100), DQS PI = 12
7292 10:02:07.789613 [4] AVG Duty = 5109%(X100)
7293 10:02:07.789723
7294 10:02:07.792930 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7295 10:02:07.793013
7296 10:02:07.796144 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7297 10:02:07.799669 [DutyScan_Calibration_Flow] ====Done====
7298 10:02:07.799754
7299 10:02:07.802982 [DutyScan_Calibration_Flow] k_type=2
7300 10:02:07.819355
7301 10:02:07.819439 ==DQ 0 ==
7302 10:02:07.823074 Final DQ duty delay cell = -4
7303 10:02:07.826117 [-4] MAX Duty = 5000%(X100), DQS PI = 16
7304 10:02:07.829164 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7305 10:02:07.832318 [-4] AVG Duty = 4938%(X100)
7306 10:02:07.832431
7307 10:02:07.832497 ==DQ 1 ==
7308 10:02:07.835870 Final DQ duty delay cell = 0
7309 10:02:07.838964 [0] MAX Duty = 5156%(X100), DQS PI = 58
7310 10:02:07.842198 [0] MIN Duty = 5000%(X100), DQS PI = 14
7311 10:02:07.845883 [0] AVG Duty = 5078%(X100)
7312 10:02:07.845965
7313 10:02:07.849539 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7314 10:02:07.849621
7315 10:02:07.852334 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7316 10:02:07.855628 [DutyScan_Calibration_Flow] ====Done====
7317 10:02:07.855710 ==
7318 10:02:07.858670 Dram Type= 6, Freq= 0, CH_1, rank 0
7319 10:02:07.861676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7320 10:02:07.861759 ==
7321 10:02:07.865077 [Duty_Offset_Calibration]
7322 10:02:07.868953 B0:1 B1:-2 CA:1
7323 10:02:07.869035
7324 10:02:07.871666 [DutyScan_Calibration_Flow] k_type=0
7325 10:02:07.880193
7326 10:02:07.880275 ==CLK 0==
7327 10:02:07.883358 Final CLK duty delay cell = 0
7328 10:02:07.887092 [0] MAX Duty = 5062%(X100), DQS PI = 20
7329 10:02:07.890212 [0] MIN Duty = 4844%(X100), DQS PI = 4
7330 10:02:07.890294 [0] AVG Duty = 4953%(X100)
7331 10:02:07.893313
7332 10:02:07.896398 CH1 CLK Duty spec in!! Max-Min= 218%
7333 10:02:07.899938 [DutyScan_Calibration_Flow] ====Done====
7334 10:02:07.900020
7335 10:02:07.902910 [DutyScan_Calibration_Flow] k_type=1
7336 10:02:07.918931
7337 10:02:07.919013 ==DQS 0 ==
7338 10:02:07.921992 Final DQS duty delay cell = -4
7339 10:02:07.925266 [-4] MAX Duty = 5000%(X100), DQS PI = 26
7340 10:02:07.928396 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7341 10:02:07.931949 [-4] AVG Duty = 4922%(X100)
7342 10:02:07.932032
7343 10:02:07.932097 ==DQS 1 ==
7344 10:02:07.935027 Final DQS duty delay cell = 0
7345 10:02:07.938496 [0] MAX Duty = 5093%(X100), DQS PI = 60
7346 10:02:07.941539 [0] MIN Duty = 4844%(X100), DQS PI = 24
7347 10:02:07.944826 [0] AVG Duty = 4968%(X100)
7348 10:02:07.944908
7349 10:02:07.948010 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7350 10:02:07.948092
7351 10:02:07.951186 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7352 10:02:07.955296 [DutyScan_Calibration_Flow] ====Done====
7353 10:02:07.955378
7354 10:02:07.957952 [DutyScan_Calibration_Flow] k_type=3
7355 10:02:07.975796
7356 10:02:07.975878 ==DQM 0 ==
7357 10:02:07.979236 Final DQM duty delay cell = 0
7358 10:02:07.982740 [0] MAX Duty = 5031%(X100), DQS PI = 24
7359 10:02:07.985671 [0] MIN Duty = 4813%(X100), DQS PI = 54
7360 10:02:07.989321 [0] AVG Duty = 4922%(X100)
7361 10:02:07.989405
7362 10:02:07.989472 ==DQM 1 ==
7363 10:02:07.992489 Final DQM duty delay cell = 0
7364 10:02:07.995608 [0] MAX Duty = 5062%(X100), DQS PI = 34
7365 10:02:07.999148 [0] MIN Duty = 4875%(X100), DQS PI = 24
7366 10:02:08.002638 [0] AVG Duty = 4968%(X100)
7367 10:02:08.002720
7368 10:02:08.005905 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7369 10:02:08.005987
7370 10:02:08.008731 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7371 10:02:08.012446 [DutyScan_Calibration_Flow] ====Done====
7372 10:02:08.012528
7373 10:02:08.015478 [DutyScan_Calibration_Flow] k_type=2
7374 10:02:08.032727
7375 10:02:08.032808 ==DQ 0 ==
7376 10:02:08.035859 Final DQ duty delay cell = 0
7377 10:02:08.039475 [0] MAX Duty = 5093%(X100), DQS PI = 20
7378 10:02:08.042538 [0] MIN Duty = 4907%(X100), DQS PI = 62
7379 10:02:08.042620 [0] AVG Duty = 5000%(X100)
7380 10:02:08.045946
7381 10:02:08.046028 ==DQ 1 ==
7382 10:02:08.049004 Final DQ duty delay cell = 0
7383 10:02:08.052282 [0] MAX Duty = 5156%(X100), DQS PI = 36
7384 10:02:08.056009 [0] MIN Duty = 4969%(X100), DQS PI = 24
7385 10:02:08.056093 [0] AVG Duty = 5062%(X100)
7386 10:02:08.059063
7387 10:02:08.062384 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7388 10:02:08.062492
7389 10:02:08.065986 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7390 10:02:08.068813 [DutyScan_Calibration_Flow] ====Done====
7391 10:02:08.072359 nWR fixed to 30
7392 10:02:08.076026 [ModeRegInit_LP4] CH0 RK0
7393 10:02:08.076109 [ModeRegInit_LP4] CH0 RK1
7394 10:02:08.078834 [ModeRegInit_LP4] CH1 RK0
7395 10:02:08.082245 [ModeRegInit_LP4] CH1 RK1
7396 10:02:08.082328 match AC timing 5
7397 10:02:08.088772 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7398 10:02:08.092189 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7399 10:02:08.095407 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7400 10:02:08.101869 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7401 10:02:08.105395 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7402 10:02:08.105480 [MiockJmeterHQA]
7403 10:02:08.105547
7404 10:02:08.108706 [DramcMiockJmeter] u1RxGatingPI = 0
7405 10:02:08.111943 0 : 4365, 4138
7406 10:02:08.112030 4 : 4257, 4032
7407 10:02:08.114960 8 : 4257, 4029
7408 10:02:08.115046 12 : 4366, 4140
7409 10:02:08.118392 16 : 4255, 4030
7410 10:02:08.118478 20 : 4252, 4027
7411 10:02:08.118546 24 : 4255, 4029
7412 10:02:08.121483 28 : 4260, 4032
7413 10:02:08.121568 32 : 4257, 4029
7414 10:02:08.125238 36 : 4254, 4030
7415 10:02:08.125323 40 : 4252, 4030
7416 10:02:08.128393 44 : 4254, 4029
7417 10:02:08.128478 48 : 4257, 4032
7418 10:02:08.131448 52 : 4255, 4030
7419 10:02:08.131533 56 : 4255, 4029
7420 10:02:08.131601 60 : 4255, 4029
7421 10:02:08.134807 64 : 4252, 4029
7422 10:02:08.134898 68 : 4257, 4032
7423 10:02:08.137952 72 : 4255, 4029
7424 10:02:08.138037 76 : 4252, 4030
7425 10:02:08.141224 80 : 4368, 4142
7426 10:02:08.141310 84 : 4255, 4029
7427 10:02:08.144913 88 : 4363, 4140
7428 10:02:08.144999 92 : 4255, 4029
7429 10:02:08.145068 96 : 4252, 4029
7430 10:02:08.147831 100 : 4254, 4030
7431 10:02:08.147916 104 : 4360, 3728
7432 10:02:08.151649 108 : 4250, 2
7433 10:02:08.151734 112 : 4252, 0
7434 10:02:08.154543 116 : 4250, 0
7435 10:02:08.154629 120 : 4253, 0
7436 10:02:08.154697 124 : 4252, 0
7437 10:02:08.157809 128 : 4257, 0
7438 10:02:08.157895 132 : 4253, 0
7439 10:02:08.161000 136 : 4255, 0
7440 10:02:08.161085 140 : 4257, 0
7441 10:02:08.161154 144 : 4252, 0
7442 10:02:08.164224 148 : 4363, 0
7443 10:02:08.164309 152 : 4252, 0
7444 10:02:08.168055 156 : 4252, 0
7445 10:02:08.168140 160 : 4364, 0
7446 10:02:08.168208 164 : 4255, 0
7447 10:02:08.171145 168 : 4252, 0
7448 10:02:08.171230 172 : 4253, 0
7449 10:02:08.171298 176 : 4255, 0
7450 10:02:08.174202 180 : 4252, 0
7451 10:02:08.174287 184 : 4252, 0
7452 10:02:08.177885 188 : 4255, 0
7453 10:02:08.177969 192 : 4257, 0
7454 10:02:08.178038 196 : 4252, 0
7455 10:02:08.180715 200 : 4255, 0
7456 10:02:08.180801 204 : 4258, 0
7457 10:02:08.184265 208 : 4253, 0
7458 10:02:08.184350 212 : 4365, 0
7459 10:02:08.184418 216 : 4250, 0
7460 10:02:08.187158 220 : 4250, 0
7461 10:02:08.187271 224 : 4366, 0
7462 10:02:08.190576 228 : 4250, 0
7463 10:02:08.190689 232 : 4250, 0
7464 10:02:08.190797 236 : 4363, 1193
7465 10:02:08.194045 240 : 4255, 4030
7466 10:02:08.194123 244 : 4253, 4029
7467 10:02:08.197634 248 : 4360, 4138
7468 10:02:08.197734 252 : 4360, 4137
7469 10:02:08.200822 256 : 4250, 4027
7470 10:02:08.200899 260 : 4250, 4026
7471 10:02:08.203937 264 : 4365, 4140
7472 10:02:08.204030 268 : 4250, 4027
7473 10:02:08.207140 272 : 4255, 4029
7474 10:02:08.207242 276 : 4255, 4032
7475 10:02:08.210775 280 : 4250, 4027
7476 10:02:08.210876 284 : 4255, 4030
7477 10:02:08.213965 288 : 4363, 4140
7478 10:02:08.214078 292 : 4250, 4026
7479 10:02:08.214176 296 : 4250, 4027
7480 10:02:08.217023 300 : 4252, 4030
7481 10:02:08.217100 304 : 4360, 4137
7482 10:02:08.220608 308 : 4254, 4029
7483 10:02:08.220696 312 : 4250, 4027
7484 10:02:08.223615 316 : 4253, 4029
7485 10:02:08.223703 320 : 4255, 4029
7486 10:02:08.227264 324 : 4252, 4030
7487 10:02:08.227340 328 : 4252, 4030
7488 10:02:08.230446 332 : 4250, 4027
7489 10:02:08.230559 336 : 4250, 4027
7490 10:02:08.233595 340 : 4250, 4027
7491 10:02:08.233708 344 : 4363, 4140
7492 10:02:08.237232 348 : 4255, 4029
7493 10:02:08.237311 352 : 4250, 4007
7494 10:02:08.240403 356 : 4250, 2930
7495 10:02:08.240513 360 : 4252, 2
7496 10:02:08.240608
7497 10:02:08.243684 MIOCK jitter meter ch=0
7498 10:02:08.243792
7499 10:02:08.246777 1T = (360-108) = 252 dly cells
7500 10:02:08.250539 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7501 10:02:08.250649 ==
7502 10:02:08.254054 Dram Type= 6, Freq= 0, CH_0, rank 0
7503 10:02:08.260235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7504 10:02:08.260316 ==
7505 10:02:08.263291 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7506 10:02:08.269762 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7507 10:02:08.273437 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7508 10:02:08.279762 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7509 10:02:08.287721 [CA 0] Center 44 (14~75) winsize 62
7510 10:02:08.291300 [CA 1] Center 43 (13~74) winsize 62
7511 10:02:08.294062 [CA 2] Center 40 (11~69) winsize 59
7512 10:02:08.297513 [CA 3] Center 39 (10~68) winsize 59
7513 10:02:08.300881 [CA 4] Center 37 (8~67) winsize 60
7514 10:02:08.304319 [CA 5] Center 37 (7~67) winsize 61
7515 10:02:08.304409
7516 10:02:08.307446 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7517 10:02:08.310777
7518 10:02:08.314167 [CATrainingPosCal] consider 1 rank data
7519 10:02:08.314287 u2DelayCellTimex100 = 258/100 ps
7520 10:02:08.320718 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7521 10:02:08.323709 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7522 10:02:08.327156 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7523 10:02:08.330461 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7524 10:02:08.333759 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7525 10:02:08.336999 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7526 10:02:08.337118
7527 10:02:08.340516 CA PerBit enable=1, Macro0, CA PI delay=37
7528 10:02:08.343788
7529 10:02:08.343907 [CBTSetCACLKResult] CA Dly = 37
7530 10:02:08.346940 CS Dly: 11 (0~42)
7531 10:02:08.350118 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7532 10:02:08.353404 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7533 10:02:08.356667 ==
7534 10:02:08.359727 Dram Type= 6, Freq= 0, CH_0, rank 1
7535 10:02:08.363122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 10:02:08.363221 ==
7537 10:02:08.366452 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7538 10:02:08.373149 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7539 10:02:08.376230 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7540 10:02:08.382945 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7541 10:02:08.391685 [CA 0] Center 44 (13~75) winsize 63
7542 10:02:08.394712 [CA 1] Center 43 (13~74) winsize 62
7543 10:02:08.398300 [CA 2] Center 39 (10~69) winsize 60
7544 10:02:08.401156 [CA 3] Center 39 (10~68) winsize 59
7545 10:02:08.404637 [CA 4] Center 37 (8~67) winsize 60
7546 10:02:08.408086 [CA 5] Center 36 (7~66) winsize 60
7547 10:02:08.408169
7548 10:02:08.411245 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7549 10:02:08.414372
7550 10:02:08.417827 [CATrainingPosCal] consider 2 rank data
7551 10:02:08.417905 u2DelayCellTimex100 = 258/100 ps
7552 10:02:08.424326 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7553 10:02:08.427901 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7554 10:02:08.430971 CA2 delay=40 (11~69),Diff = 4 PI (15 cell)
7555 10:02:08.434440 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7556 10:02:08.437533 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7557 10:02:08.440669 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7558 10:02:08.440785
7559 10:02:08.444204 CA PerBit enable=1, Macro0, CA PI delay=36
7560 10:02:08.447401
7561 10:02:08.447510 [CBTSetCACLKResult] CA Dly = 36
7562 10:02:08.450720 CS Dly: 11 (0~42)
7563 10:02:08.453901 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7564 10:02:08.457187 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7565 10:02:08.460325
7566 10:02:08.464015 ----->DramcWriteLeveling(PI) begin...
7567 10:02:08.464120 ==
7568 10:02:08.467550 Dram Type= 6, Freq= 0, CH_0, rank 0
7569 10:02:08.470254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 10:02:08.470357 ==
7571 10:02:08.473958 Write leveling (Byte 0): 35 => 35
7572 10:02:08.477111 Write leveling (Byte 1): 29 => 29
7573 10:02:08.480261 DramcWriteLeveling(PI) end<-----
7574 10:02:08.480365
7575 10:02:08.480461 ==
7576 10:02:08.483781 Dram Type= 6, Freq= 0, CH_0, rank 0
7577 10:02:08.486705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7578 10:02:08.486808 ==
7579 10:02:08.490178 [Gating] SW mode calibration
7580 10:02:08.496639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7581 10:02:08.503209 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7582 10:02:08.506751 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 10:02:08.510168 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 10:02:08.516490 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 10:02:08.519840 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 10:02:08.523550 1 4 16 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
7587 10:02:08.529742 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7588 10:02:08.532829 1 4 24 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
7589 10:02:08.536511 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 10:02:08.543018 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 10:02:08.546072 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 10:02:08.549790 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 10:02:08.556214 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7594 10:02:08.559505 1 5 16 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7595 10:02:08.562684 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7596 10:02:08.568888 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7597 10:02:08.572233 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7598 10:02:08.575652 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 10:02:08.582296 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 10:02:08.585777 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 10:02:08.588992 1 6 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7602 10:02:08.595477 1 6 16 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7603 10:02:08.599076 1 6 20 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
7604 10:02:08.601762 1 6 24 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
7605 10:02:08.608831 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 10:02:08.611873 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 10:02:08.615141 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 10:02:08.621666 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 10:02:08.624971 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 10:02:08.631722 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7611 10:02:08.635029 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7612 10:02:08.638149 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7613 10:02:08.644494 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 10:02:08.648053 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 10:02:08.651249 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 10:02:08.657813 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 10:02:08.661294 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 10:02:08.664639 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 10:02:08.671207 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 10:02:08.674431 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 10:02:08.677640 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 10:02:08.683872 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 10:02:08.687557 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 10:02:08.690797 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 10:02:08.697166 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7626 10:02:08.700465 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7627 10:02:08.703688 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7628 10:02:08.707452 Total UI for P1: 0, mck2ui 16
7629 10:02:08.710705 best dqsien dly found for B0: ( 1, 9, 14)
7630 10:02:08.716845 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7631 10:02:08.720211 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 10:02:08.723534 Total UI for P1: 0, mck2ui 16
7633 10:02:08.726765 best dqsien dly found for B1: ( 1, 9, 22)
7634 10:02:08.730093 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7635 10:02:08.733614 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7636 10:02:08.733693
7637 10:02:08.737009 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7638 10:02:08.740559 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7639 10:02:08.743241 [Gating] SW calibration Done
7640 10:02:08.743322 ==
7641 10:02:08.746499 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 10:02:08.750090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 10:02:08.753320 ==
7644 10:02:08.753418 RX Vref Scan: 0
7645 10:02:08.753511
7646 10:02:08.756661 RX Vref 0 -> 0, step: 1
7647 10:02:08.756745
7648 10:02:08.756812 RX Delay 0 -> 252, step: 8
7649 10:02:08.763390 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7650 10:02:08.766770 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7651 10:02:08.769987 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7652 10:02:08.773110 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7653 10:02:08.777087 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7654 10:02:08.783333 iDelay=200, Bit 5, Center 115 (64 ~ 167) 104
7655 10:02:08.786464 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7656 10:02:08.789816 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7657 10:02:08.793242 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7658 10:02:08.796312 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7659 10:02:08.803228 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7660 10:02:08.806573 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7661 10:02:08.809593 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7662 10:02:08.813161 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7663 10:02:08.819448 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7664 10:02:08.822804 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7665 10:02:08.822897 ==
7666 10:02:08.826249 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 10:02:08.829573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 10:02:08.829683 ==
7669 10:02:08.832527 DQS Delay:
7670 10:02:08.832610 DQS0 = 0, DQS1 = 0
7671 10:02:08.832677 DQM Delay:
7672 10:02:08.835970 DQM0 = 128, DQM1 = 124
7673 10:02:08.836054 DQ Delay:
7674 10:02:08.839186 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7675 10:02:08.842610 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =143
7676 10:02:08.849087 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7677 10:02:08.852331 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7678 10:02:08.852414
7679 10:02:08.852480
7680 10:02:08.852542 ==
7681 10:02:08.855543 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 10:02:08.859245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 10:02:08.859329 ==
7684 10:02:08.859396
7685 10:02:08.859458
7686 10:02:08.862487 TX Vref Scan disable
7687 10:02:08.865572 == TX Byte 0 ==
7688 10:02:08.869108 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7689 10:02:08.872352 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7690 10:02:08.875581 == TX Byte 1 ==
7691 10:02:08.878755 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7692 10:02:08.882099 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7693 10:02:08.882183 ==
7694 10:02:08.885292 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 10:02:08.888688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 10:02:08.891973 ==
7697 10:02:08.903651
7698 10:02:08.906777 TX Vref early break, caculate TX vref
7699 10:02:08.910664 TX Vref=16, minBit 8, minWin=21, winSum=356
7700 10:02:08.913875 TX Vref=18, minBit 8, minWin=22, winSum=369
7701 10:02:08.916772 TX Vref=20, minBit 8, minWin=22, winSum=376
7702 10:02:08.919988 TX Vref=22, minBit 13, minWin=23, winSum=391
7703 10:02:08.923597 TX Vref=24, minBit 4, minWin=24, winSum=400
7704 10:02:08.929981 TX Vref=26, minBit 13, minWin=24, winSum=408
7705 10:02:08.933505 TX Vref=28, minBit 4, minWin=24, winSum=405
7706 10:02:08.936825 TX Vref=30, minBit 8, minWin=24, winSum=406
7707 10:02:08.940230 TX Vref=32, minBit 3, minWin=24, winSum=393
7708 10:02:08.943187 TX Vref=34, minBit 8, minWin=21, winSum=382
7709 10:02:08.949871 [TxChooseVref] Worse bit 13, Min win 24, Win sum 408, Final Vref 26
7710 10:02:08.949960
7711 10:02:08.952870 Final TX Range 0 Vref 26
7712 10:02:08.952954
7713 10:02:08.953020 ==
7714 10:02:08.956598 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 10:02:08.960215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 10:02:08.960325 ==
7717 10:02:08.960414
7718 10:02:08.963150
7719 10:02:08.963233 TX Vref Scan disable
7720 10:02:08.969334 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7721 10:02:08.969416 == TX Byte 0 ==
7722 10:02:08.973236 u2DelayCellOfst[0]=15 cells (4 PI)
7723 10:02:08.976068 u2DelayCellOfst[1]=18 cells (5 PI)
7724 10:02:08.979316 u2DelayCellOfst[2]=11 cells (3 PI)
7725 10:02:08.983213 u2DelayCellOfst[3]=15 cells (4 PI)
7726 10:02:08.986220 u2DelayCellOfst[4]=11 cells (3 PI)
7727 10:02:08.989353 u2DelayCellOfst[5]=0 cells (0 PI)
7728 10:02:08.992401 u2DelayCellOfst[6]=22 cells (6 PI)
7729 10:02:08.995613 u2DelayCellOfst[7]=22 cells (6 PI)
7730 10:02:08.999330 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7731 10:02:09.002580 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7732 10:02:09.005700 == TX Byte 1 ==
7733 10:02:09.009057 u2DelayCellOfst[8]=0 cells (0 PI)
7734 10:02:09.012250 u2DelayCellOfst[9]=3 cells (1 PI)
7735 10:02:09.015394 u2DelayCellOfst[10]=11 cells (3 PI)
7736 10:02:09.018801 u2DelayCellOfst[11]=7 cells (2 PI)
7737 10:02:09.022054 u2DelayCellOfst[12]=11 cells (3 PI)
7738 10:02:09.025259 u2DelayCellOfst[13]=11 cells (3 PI)
7739 10:02:09.028822 u2DelayCellOfst[14]=15 cells (4 PI)
7740 10:02:09.031984 u2DelayCellOfst[15]=11 cells (3 PI)
7741 10:02:09.035476 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7742 10:02:09.038776 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7743 10:02:09.041971 DramC Write-DBI on
7744 10:02:09.042055 ==
7745 10:02:09.044948 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 10:02:09.048243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 10:02:09.048327 ==
7748 10:02:09.048394
7749 10:02:09.048456
7750 10:02:09.051745 TX Vref Scan disable
7751 10:02:09.055134 == TX Byte 0 ==
7752 10:02:09.058273 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7753 10:02:09.058356 == TX Byte 1 ==
7754 10:02:09.065109 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7755 10:02:09.065193 DramC Write-DBI off
7756 10:02:09.065259
7757 10:02:09.065321 [DATLAT]
7758 10:02:09.068296 Freq=1600, CH0 RK0
7759 10:02:09.068379
7760 10:02:09.071404 DATLAT Default: 0xf
7761 10:02:09.071488 0, 0xFFFF, sum = 0
7762 10:02:09.075043 1, 0xFFFF, sum = 0
7763 10:02:09.075127 2, 0xFFFF, sum = 0
7764 10:02:09.077851 3, 0xFFFF, sum = 0
7765 10:02:09.077964 4, 0xFFFF, sum = 0
7766 10:02:09.081146 5, 0xFFFF, sum = 0
7767 10:02:09.081230 6, 0xFFFF, sum = 0
7768 10:02:09.084824 7, 0xFFFF, sum = 0
7769 10:02:09.084909 8, 0xFFFF, sum = 0
7770 10:02:09.087942 9, 0xFFFF, sum = 0
7771 10:02:09.088027 10, 0xFFFF, sum = 0
7772 10:02:09.091071 11, 0xFFFF, sum = 0
7773 10:02:09.094660 12, 0xFFFF, sum = 0
7774 10:02:09.094771 13, 0xEFFF, sum = 0
7775 10:02:09.097971 14, 0x0, sum = 1
7776 10:02:09.098055 15, 0x0, sum = 2
7777 10:02:09.098124 16, 0x0, sum = 3
7778 10:02:09.100946 17, 0x0, sum = 4
7779 10:02:09.101031 best_step = 15
7780 10:02:09.101097
7781 10:02:09.104197 ==
7782 10:02:09.104280 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 10:02:09.110970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 10:02:09.111054 ==
7785 10:02:09.111121 RX Vref Scan: 1
7786 10:02:09.111184
7787 10:02:09.114231 Set Vref Range= 24 -> 127
7788 10:02:09.114317
7789 10:02:09.117471 RX Vref 24 -> 127, step: 1
7790 10:02:09.117554
7791 10:02:09.120509 RX Delay 11 -> 252, step: 4
7792 10:02:09.120595
7793 10:02:09.123979 Set Vref, RX VrefLevel [Byte0]: 24
7794 10:02:09.127234 [Byte1]: 24
7795 10:02:09.127318
7796 10:02:09.130394 Set Vref, RX VrefLevel [Byte0]: 25
7797 10:02:09.133946 [Byte1]: 25
7798 10:02:09.134030
7799 10:02:09.137124 Set Vref, RX VrefLevel [Byte0]: 26
7800 10:02:09.140338 [Byte1]: 26
7801 10:02:09.144081
7802 10:02:09.144165 Set Vref, RX VrefLevel [Byte0]: 27
7803 10:02:09.150769 [Byte1]: 27
7804 10:02:09.150906
7805 10:02:09.153962 Set Vref, RX VrefLevel [Byte0]: 28
7806 10:02:09.156900 [Byte1]: 28
7807 10:02:09.156983
7808 10:02:09.160293 Set Vref, RX VrefLevel [Byte0]: 29
7809 10:02:09.163455 [Byte1]: 29
7810 10:02:09.166740
7811 10:02:09.166886 Set Vref, RX VrefLevel [Byte0]: 30
7812 10:02:09.170478 [Byte1]: 30
7813 10:02:09.174429
7814 10:02:09.174536 Set Vref, RX VrefLevel [Byte0]: 31
7815 10:02:09.178063 [Byte1]: 31
7816 10:02:09.182265
7817 10:02:09.182346 Set Vref, RX VrefLevel [Byte0]: 32
7818 10:02:09.185534 [Byte1]: 32
7819 10:02:09.189952
7820 10:02:09.190031 Set Vref, RX VrefLevel [Byte0]: 33
7821 10:02:09.193284 [Byte1]: 33
7822 10:02:09.197501
7823 10:02:09.197578 Set Vref, RX VrefLevel [Byte0]: 34
7824 10:02:09.200493 [Byte1]: 34
7825 10:02:09.204852
7826 10:02:09.204962 Set Vref, RX VrefLevel [Byte0]: 35
7827 10:02:09.208096 [Byte1]: 35
7828 10:02:09.212816
7829 10:02:09.212897 Set Vref, RX VrefLevel [Byte0]: 36
7830 10:02:09.216320 [Byte1]: 36
7831 10:02:09.220338
7832 10:02:09.220414 Set Vref, RX VrefLevel [Byte0]: 37
7833 10:02:09.223569 [Byte1]: 37
7834 10:02:09.227790
7835 10:02:09.227871 Set Vref, RX VrefLevel [Byte0]: 38
7836 10:02:09.231032 [Byte1]: 38
7837 10:02:09.235226
7838 10:02:09.235303 Set Vref, RX VrefLevel [Byte0]: 39
7839 10:02:09.238948 [Byte1]: 39
7840 10:02:09.243085
7841 10:02:09.243163 Set Vref, RX VrefLevel [Byte0]: 40
7842 10:02:09.246392 [Byte1]: 40
7843 10:02:09.250624
7844 10:02:09.250706 Set Vref, RX VrefLevel [Byte0]: 41
7845 10:02:09.254393 [Byte1]: 41
7846 10:02:09.258371
7847 10:02:09.258450 Set Vref, RX VrefLevel [Byte0]: 42
7848 10:02:09.261705 [Byte1]: 42
7849 10:02:09.265782
7850 10:02:09.265889 Set Vref, RX VrefLevel [Byte0]: 43
7851 10:02:09.269096 [Byte1]: 43
7852 10:02:09.273710
7853 10:02:09.273820 Set Vref, RX VrefLevel [Byte0]: 44
7854 10:02:09.276928 [Byte1]: 44
7855 10:02:09.281213
7856 10:02:09.281294 Set Vref, RX VrefLevel [Byte0]: 45
7857 10:02:09.284429 [Byte1]: 45
7858 10:02:09.288613
7859 10:02:09.288698 Set Vref, RX VrefLevel [Byte0]: 46
7860 10:02:09.291817 [Byte1]: 46
7861 10:02:09.296330
7862 10:02:09.296414 Set Vref, RX VrefLevel [Byte0]: 47
7863 10:02:09.299505 [Byte1]: 47
7864 10:02:09.303723
7865 10:02:09.303806 Set Vref, RX VrefLevel [Byte0]: 48
7866 10:02:09.307327 [Byte1]: 48
7867 10:02:09.311554
7868 10:02:09.311637 Set Vref, RX VrefLevel [Byte0]: 49
7869 10:02:09.314714 [Byte1]: 49
7870 10:02:09.318987
7871 10:02:09.319071 Set Vref, RX VrefLevel [Byte0]: 50
7872 10:02:09.322776 [Byte1]: 50
7873 10:02:09.326698
7874 10:02:09.326808 Set Vref, RX VrefLevel [Byte0]: 51
7875 10:02:09.330182 [Byte1]: 51
7876 10:02:09.334434
7877 10:02:09.334517 Set Vref, RX VrefLevel [Byte0]: 52
7878 10:02:09.337937 [Byte1]: 52
7879 10:02:09.342380
7880 10:02:09.342465 Set Vref, RX VrefLevel [Byte0]: 53
7881 10:02:09.345504 [Byte1]: 53
7882 10:02:09.349848
7883 10:02:09.349932 Set Vref, RX VrefLevel [Byte0]: 54
7884 10:02:09.352936 [Byte1]: 54
7885 10:02:09.357336
7886 10:02:09.357421 Set Vref, RX VrefLevel [Byte0]: 55
7887 10:02:09.360470 [Byte1]: 55
7888 10:02:09.364921
7889 10:02:09.365004 Set Vref, RX VrefLevel [Byte0]: 56
7890 10:02:09.368420 [Byte1]: 56
7891 10:02:09.372402
7892 10:02:09.372486 Set Vref, RX VrefLevel [Byte0]: 57
7893 10:02:09.375862 [Byte1]: 57
7894 10:02:09.380050
7895 10:02:09.380133 Set Vref, RX VrefLevel [Byte0]: 58
7896 10:02:09.383500 [Byte1]: 58
7897 10:02:09.387732
7898 10:02:09.387816 Set Vref, RX VrefLevel [Byte0]: 59
7899 10:02:09.391101 [Byte1]: 59
7900 10:02:09.395418
7901 10:02:09.395502 Set Vref, RX VrefLevel [Byte0]: 60
7902 10:02:09.398552 [Byte1]: 60
7903 10:02:09.402820
7904 10:02:09.402943 Set Vref, RX VrefLevel [Byte0]: 61
7905 10:02:09.406501 [Byte1]: 61
7906 10:02:09.410971
7907 10:02:09.411054 Set Vref, RX VrefLevel [Byte0]: 62
7908 10:02:09.413881 [Byte1]: 62
7909 10:02:09.417952
7910 10:02:09.418036 Set Vref, RX VrefLevel [Byte0]: 63
7911 10:02:09.421193 [Byte1]: 63
7912 10:02:09.426039
7913 10:02:09.426122 Set Vref, RX VrefLevel [Byte0]: 64
7914 10:02:09.428984 [Byte1]: 64
7915 10:02:09.433224
7916 10:02:09.433307 Set Vref, RX VrefLevel [Byte0]: 65
7917 10:02:09.436686 [Byte1]: 65
7918 10:02:09.440779
7919 10:02:09.440863 Set Vref, RX VrefLevel [Byte0]: 66
7920 10:02:09.444325 [Byte1]: 66
7921 10:02:09.448543
7922 10:02:09.448626 Set Vref, RX VrefLevel [Byte0]: 67
7923 10:02:09.451780 [Byte1]: 67
7924 10:02:09.456111
7925 10:02:09.456194 Set Vref, RX VrefLevel [Byte0]: 68
7926 10:02:09.459335 [Byte1]: 68
7927 10:02:09.464252
7928 10:02:09.464335 Set Vref, RX VrefLevel [Byte0]: 69
7929 10:02:09.467291 [Byte1]: 69
7930 10:02:09.471211
7931 10:02:09.471294 Set Vref, RX VrefLevel [Byte0]: 70
7932 10:02:09.475065 [Byte1]: 70
7933 10:02:09.478787
7934 10:02:09.478901 Set Vref, RX VrefLevel [Byte0]: 71
7935 10:02:09.482433 [Byte1]: 71
7936 10:02:09.486684
7937 10:02:09.486766 Set Vref, RX VrefLevel [Byte0]: 72
7938 10:02:09.489869 [Byte1]: 72
7939 10:02:09.494540
7940 10:02:09.494623 Set Vref, RX VrefLevel [Byte0]: 73
7941 10:02:09.497321 [Byte1]: 73
7942 10:02:09.501925
7943 10:02:09.502008 Set Vref, RX VrefLevel [Byte0]: 74
7944 10:02:09.505371 [Byte1]: 74
7945 10:02:09.509362
7946 10:02:09.509444 Set Vref, RX VrefLevel [Byte0]: 75
7947 10:02:09.512842 [Byte1]: 75
7948 10:02:09.516957
7949 10:02:09.517040 Set Vref, RX VrefLevel [Byte0]: 76
7950 10:02:09.520669 [Byte1]: 76
7951 10:02:09.524887
7952 10:02:09.524969 Set Vref, RX VrefLevel [Byte0]: 77
7953 10:02:09.528050 [Byte1]: 77
7954 10:02:09.532352
7955 10:02:09.532435 Final RX Vref Byte 0 = 64 to rank0
7956 10:02:09.535944 Final RX Vref Byte 1 = 60 to rank0
7957 10:02:09.538841 Final RX Vref Byte 0 = 64 to rank1
7958 10:02:09.542371 Final RX Vref Byte 1 = 60 to rank1==
7959 10:02:09.545433 Dram Type= 6, Freq= 0, CH_0, rank 0
7960 10:02:09.552410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 10:02:09.552494 ==
7962 10:02:09.552561 DQS Delay:
7963 10:02:09.552622 DQS0 = 0, DQS1 = 0
7964 10:02:09.555909 DQM Delay:
7965 10:02:09.555992 DQM0 = 126, DQM1 = 120
7966 10:02:09.558801 DQ Delay:
7967 10:02:09.561967 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7968 10:02:09.565216 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7969 10:02:09.568377 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
7970 10:02:09.571965 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7971 10:02:09.572047
7972 10:02:09.572113
7973 10:02:09.572175
7974 10:02:09.574897 [DramC_TX_OE_Calibration] TA2
7975 10:02:09.578628 Original DQ_B0 (3 6) =30, OEN = 27
7976 10:02:09.581827 Original DQ_B1 (3 6) =30, OEN = 27
7977 10:02:09.584785 24, 0x0, End_B0=24 End_B1=24
7978 10:02:09.588349 25, 0x0, End_B0=25 End_B1=25
7979 10:02:09.588433 26, 0x0, End_B0=26 End_B1=26
7980 10:02:09.591803 27, 0x0, End_B0=27 End_B1=27
7981 10:02:09.595244 28, 0x0, End_B0=28 End_B1=28
7982 10:02:09.598497 29, 0x0, End_B0=29 End_B1=29
7983 10:02:09.598582 30, 0x0, End_B0=30 End_B1=30
7984 10:02:09.602056 31, 0x5151, End_B0=30 End_B1=30
7985 10:02:09.604690 Byte0 end_step=30 best_step=27
7986 10:02:09.608289 Byte1 end_step=30 best_step=27
7987 10:02:09.611592 Byte0 TX OE(2T, 0.5T) = (3, 3)
7988 10:02:09.614734 Byte1 TX OE(2T, 0.5T) = (3, 3)
7989 10:02:09.614836
7990 10:02:09.614908
7991 10:02:09.621451 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
7992 10:02:09.624564 CH0 RK0: MR19=303, MR18=1313
7993 10:02:09.630974 CH0_RK0: MR19=0x303, MR18=0x1313, DQSOSC=400, MR23=63, INC=23, DEC=15
7994 10:02:09.631058
7995 10:02:09.634762 ----->DramcWriteLeveling(PI) begin...
7996 10:02:09.634881 ==
7997 10:02:09.637920 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 10:02:09.641109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 10:02:09.641193 ==
8000 10:02:09.644818 Write leveling (Byte 0): 34 => 34
8001 10:02:09.647678 Write leveling (Byte 1): 29 => 29
8002 10:02:09.651272 DramcWriteLeveling(PI) end<-----
8003 10:02:09.651355
8004 10:02:09.651421 ==
8005 10:02:09.654223 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 10:02:09.657481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 10:02:09.661266 ==
8008 10:02:09.661362 [Gating] SW mode calibration
8009 10:02:09.671078 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8010 10:02:09.674165 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8011 10:02:09.677606 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 10:02:09.683947 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 10:02:09.687369 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 10:02:09.690450 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8015 10:02:09.697457 1 4 16 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8016 10:02:09.700446 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 10:02:09.703667 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 10:02:09.710205 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 10:02:09.713801 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 10:02:09.717551 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 10:02:09.723573 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8022 10:02:09.726781 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8023 10:02:09.730017 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8024 10:02:09.736475 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8025 10:02:09.740298 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 10:02:09.743487 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 10:02:09.749873 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 10:02:09.752977 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 10:02:09.756528 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8030 10:02:09.763060 1 6 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8031 10:02:09.766599 1 6 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
8032 10:02:09.769386 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 10:02:09.776316 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 10:02:09.779443 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 10:02:09.786278 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 10:02:09.789383 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 10:02:09.792466 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8038 10:02:09.795764 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8039 10:02:09.802753 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8040 10:02:09.805728 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8041 10:02:09.809310 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 10:02:09.815802 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 10:02:09.818817 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 10:02:09.826008 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 10:02:09.828631 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 10:02:09.832206 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 10:02:09.838957 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 10:02:09.842068 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 10:02:09.845305 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 10:02:09.851748 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 10:02:09.854958 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 10:02:09.858354 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 10:02:09.864738 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8054 10:02:09.868615 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8055 10:02:09.871377 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8056 10:02:09.874749 Total UI for P1: 0, mck2ui 16
8057 10:02:09.877998 best dqsien dly found for B0: ( 1, 9, 10)
8058 10:02:09.884829 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8059 10:02:09.887836 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 10:02:09.891463 Total UI for P1: 0, mck2ui 16
8061 10:02:09.894585 best dqsien dly found for B1: ( 1, 9, 18)
8062 10:02:09.897944 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8063 10:02:09.901324 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8064 10:02:09.901408
8065 10:02:09.904311 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8066 10:02:09.907883 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8067 10:02:09.910739 [Gating] SW calibration Done
8068 10:02:09.910866 ==
8069 10:02:09.913979 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 10:02:09.920900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 10:02:09.920984 ==
8072 10:02:09.921052 RX Vref Scan: 0
8073 10:02:09.921116
8074 10:02:09.924454 RX Vref 0 -> 0, step: 1
8075 10:02:09.924537
8076 10:02:09.927616 RX Delay 0 -> 252, step: 8
8077 10:02:09.930727 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8078 10:02:09.934388 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8079 10:02:09.937327 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8080 10:02:09.940792 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8081 10:02:09.947305 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8082 10:02:09.950452 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8083 10:02:09.953955 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8084 10:02:09.957235 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8085 10:02:09.960289 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8086 10:02:09.966569 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8087 10:02:09.970271 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8088 10:02:09.973180 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8089 10:02:09.976645 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8090 10:02:09.982817 iDelay=200, Bit 13, Center 123 (64 ~ 183) 120
8091 10:02:09.986214 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8092 10:02:09.989756 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8093 10:02:09.989839 ==
8094 10:02:09.992961 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 10:02:09.996144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 10:02:09.999298 ==
8097 10:02:09.999381 DQS Delay:
8098 10:02:09.999448 DQS0 = 0, DQS1 = 0
8099 10:02:10.002942 DQM Delay:
8100 10:02:10.003025 DQM0 = 128, DQM1 = 121
8101 10:02:10.006374 DQ Delay:
8102 10:02:10.009864 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8103 10:02:10.012643 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8104 10:02:10.015705 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8105 10:02:10.019032 DQ12 =127, DQ13 =123, DQ14 =131, DQ15 =127
8106 10:02:10.019124
8107 10:02:10.019191
8108 10:02:10.019253 ==
8109 10:02:10.022737 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 10:02:10.026121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 10:02:10.026226 ==
8112 10:02:10.029212
8113 10:02:10.029293
8114 10:02:10.029376 TX Vref Scan disable
8115 10:02:10.032185 == TX Byte 0 ==
8116 10:02:10.035776 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8117 10:02:10.038887 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8118 10:02:10.042615 == TX Byte 1 ==
8119 10:02:10.045636 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8120 10:02:10.048971 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8121 10:02:10.052157 ==
8122 10:02:10.055323 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 10:02:10.058463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 10:02:10.058580 ==
8125 10:02:10.072187
8126 10:02:10.075738 TX Vref early break, caculate TX vref
8127 10:02:10.078720 TX Vref=16, minBit 0, minWin=22, winSum=367
8128 10:02:10.082280 TX Vref=18, minBit 8, minWin=22, winSum=374
8129 10:02:10.085308 TX Vref=20, minBit 8, minWin=22, winSum=382
8130 10:02:10.088924 TX Vref=22, minBit 8, minWin=23, winSum=392
8131 10:02:10.092008 TX Vref=24, minBit 0, minWin=24, winSum=401
8132 10:02:10.098778 TX Vref=26, minBit 1, minWin=25, winSum=404
8133 10:02:10.102021 TX Vref=28, minBit 2, minWin=25, winSum=405
8134 10:02:10.105177 TX Vref=30, minBit 8, minWin=23, winSum=407
8135 10:02:10.108386 TX Vref=32, minBit 8, minWin=24, winSum=402
8136 10:02:10.112124 TX Vref=34, minBit 8, minWin=23, winSum=394
8137 10:02:10.118605 TX Vref=36, minBit 8, minWin=22, winSum=382
8138 10:02:10.121738 [TxChooseVref] Worse bit 2, Min win 25, Win sum 405, Final Vref 28
8139 10:02:10.121848
8140 10:02:10.124857 Final TX Range 0 Vref 28
8141 10:02:10.124956
8142 10:02:10.125051 ==
8143 10:02:10.128317 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 10:02:10.131697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 10:02:10.134835 ==
8146 10:02:10.134930
8147 10:02:10.134996
8148 10:02:10.135060 TX Vref Scan disable
8149 10:02:10.141658 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8150 10:02:10.141743 == TX Byte 0 ==
8151 10:02:10.144879 u2DelayCellOfst[0]=11 cells (3 PI)
8152 10:02:10.148318 u2DelayCellOfst[1]=18 cells (5 PI)
8153 10:02:10.151519 u2DelayCellOfst[2]=11 cells (3 PI)
8154 10:02:10.154789 u2DelayCellOfst[3]=11 cells (3 PI)
8155 10:02:10.158439 u2DelayCellOfst[4]=7 cells (2 PI)
8156 10:02:10.161315 u2DelayCellOfst[5]=0 cells (0 PI)
8157 10:02:10.164561 u2DelayCellOfst[6]=18 cells (5 PI)
8158 10:02:10.168161 u2DelayCellOfst[7]=18 cells (5 PI)
8159 10:02:10.171239 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8160 10:02:10.174535 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8161 10:02:10.177654 == TX Byte 1 ==
8162 10:02:10.181249 u2DelayCellOfst[8]=0 cells (0 PI)
8163 10:02:10.184415 u2DelayCellOfst[9]=0 cells (0 PI)
8164 10:02:10.187653 u2DelayCellOfst[10]=7 cells (2 PI)
8165 10:02:10.190956 u2DelayCellOfst[11]=3 cells (1 PI)
8166 10:02:10.194205 u2DelayCellOfst[12]=11 cells (3 PI)
8167 10:02:10.197736 u2DelayCellOfst[13]=11 cells (3 PI)
8168 10:02:10.200895 u2DelayCellOfst[14]=15 cells (4 PI)
8169 10:02:10.200999 u2DelayCellOfst[15]=7 cells (2 PI)
8170 10:02:10.207756 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8171 10:02:10.211031 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8172 10:02:10.214053 DramC Write-DBI on
8173 10:02:10.214164 ==
8174 10:02:10.217298 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 10:02:10.220885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 10:02:10.220999 ==
8177 10:02:10.221093
8178 10:02:10.221195
8179 10:02:10.223927 TX Vref Scan disable
8180 10:02:10.224029 == TX Byte 0 ==
8181 10:02:10.230688 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8182 10:02:10.230794 == TX Byte 1 ==
8183 10:02:10.234002 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8184 10:02:10.237049 DramC Write-DBI off
8185 10:02:10.237159
8186 10:02:10.237264 [DATLAT]
8187 10:02:10.240659 Freq=1600, CH0 RK1
8188 10:02:10.240769
8189 10:02:10.240862 DATLAT Default: 0xf
8190 10:02:10.243739 0, 0xFFFF, sum = 0
8191 10:02:10.247334 1, 0xFFFF, sum = 0
8192 10:02:10.247442 2, 0xFFFF, sum = 0
8193 10:02:10.250164 3, 0xFFFF, sum = 0
8194 10:02:10.250278 4, 0xFFFF, sum = 0
8195 10:02:10.253878 5, 0xFFFF, sum = 0
8196 10:02:10.253988 6, 0xFFFF, sum = 0
8197 10:02:10.256921 7, 0xFFFF, sum = 0
8198 10:02:10.257034 8, 0xFFFF, sum = 0
8199 10:02:10.260222 9, 0xFFFF, sum = 0
8200 10:02:10.260328 10, 0xFFFF, sum = 0
8201 10:02:10.263482 11, 0xFFFF, sum = 0
8202 10:02:10.263585 12, 0xFFFF, sum = 0
8203 10:02:10.266733 13, 0xCFFF, sum = 0
8204 10:02:10.266887 14, 0x0, sum = 1
8205 10:02:10.269979 15, 0x0, sum = 2
8206 10:02:10.270083 16, 0x0, sum = 3
8207 10:02:10.273392 17, 0x0, sum = 4
8208 10:02:10.273496 best_step = 15
8209 10:02:10.273609
8210 10:02:10.273701 ==
8211 10:02:10.276985 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 10:02:10.283391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 10:02:10.283497 ==
8214 10:02:10.283613 RX Vref Scan: 0
8215 10:02:10.283706
8216 10:02:10.286438 RX Vref 0 -> 0, step: 1
8217 10:02:10.286545
8218 10:02:10.289638 RX Delay 3 -> 252, step: 4
8219 10:02:10.293184 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8220 10:02:10.296608 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8221 10:02:10.299583 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8222 10:02:10.306287 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8223 10:02:10.309560 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8224 10:02:10.312865 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8225 10:02:10.316080 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8226 10:02:10.319266 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8227 10:02:10.326019 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8228 10:02:10.329201 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8229 10:02:10.332766 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8230 10:02:10.336026 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8231 10:02:10.342698 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8232 10:02:10.345658 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8233 10:02:10.349158 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8234 10:02:10.352608 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8235 10:02:10.352732 ==
8236 10:02:10.355983 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 10:02:10.362454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 10:02:10.362576 ==
8239 10:02:10.362673 DQS Delay:
8240 10:02:10.365992 DQS0 = 0, DQS1 = 0
8241 10:02:10.366113 DQM Delay:
8242 10:02:10.366209 DQM0 = 124, DQM1 = 118
8243 10:02:10.368662 DQ Delay:
8244 10:02:10.372677 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8245 10:02:10.375434 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8246 10:02:10.378977 DQ8 =112, DQ9 =104, DQ10 =118, DQ11 =112
8247 10:02:10.382118 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8248 10:02:10.382222
8249 10:02:10.382334
8250 10:02:10.382427
8251 10:02:10.385606 [DramC_TX_OE_Calibration] TA2
8252 10:02:10.388534 Original DQ_B0 (3 6) =30, OEN = 27
8253 10:02:10.392229 Original DQ_B1 (3 6) =30, OEN = 27
8254 10:02:10.395392 24, 0x0, End_B0=24 End_B1=24
8255 10:02:10.398661 25, 0x0, End_B0=25 End_B1=25
8256 10:02:10.398740 26, 0x0, End_B0=26 End_B1=26
8257 10:02:10.401685 27, 0x0, End_B0=27 End_B1=27
8258 10:02:10.405393 28, 0x0, End_B0=28 End_B1=28
8259 10:02:10.408648 29, 0x0, End_B0=29 End_B1=29
8260 10:02:10.408741 30, 0x0, End_B0=30 End_B1=30
8261 10:02:10.411823 31, 0x4545, End_B0=30 End_B1=30
8262 10:02:10.414921 Byte0 end_step=30 best_step=27
8263 10:02:10.418125 Byte1 end_step=30 best_step=27
8264 10:02:10.421825 Byte0 TX OE(2T, 0.5T) = (3, 3)
8265 10:02:10.425023 Byte1 TX OE(2T, 0.5T) = (3, 3)
8266 10:02:10.425124
8267 10:02:10.425229
8268 10:02:10.431237 [DQSOSCAuto] RK1, (LSB)MR18= 0x2210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8269 10:02:10.434969 CH0 RK1: MR19=303, MR18=2210
8270 10:02:10.441341 CH0_RK1: MR19=0x303, MR18=0x2210, DQSOSC=392, MR23=63, INC=24, DEC=16
8271 10:02:10.444641 [RxdqsGatingPostProcess] freq 1600
8272 10:02:10.450986 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8273 10:02:10.454325 best DQS0 dly(2T, 0.5T) = (1, 1)
8274 10:02:10.454431 best DQS1 dly(2T, 0.5T) = (1, 1)
8275 10:02:10.457578 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8276 10:02:10.460906 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8277 10:02:10.464227 best DQS0 dly(2T, 0.5T) = (1, 1)
8278 10:02:10.467675 best DQS1 dly(2T, 0.5T) = (1, 1)
8279 10:02:10.470913 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8280 10:02:10.474349 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8281 10:02:10.477656 Pre-setting of DQS Precalculation
8282 10:02:10.480773 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8283 10:02:10.484271 ==
8284 10:02:10.484372 Dram Type= 6, Freq= 0, CH_1, rank 0
8285 10:02:10.490545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 10:02:10.490646 ==
8287 10:02:10.494174 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8288 10:02:10.500440 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8289 10:02:10.503628 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8290 10:02:10.510517 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8291 10:02:10.518765 [CA 0] Center 41 (12~70) winsize 59
8292 10:02:10.521911 [CA 1] Center 42 (12~72) winsize 61
8293 10:02:10.525068 [CA 2] Center 37 (8~66) winsize 59
8294 10:02:10.528302 [CA 3] Center 36 (7~66) winsize 60
8295 10:02:10.531829 [CA 4] Center 37 (8~67) winsize 60
8296 10:02:10.535069 [CA 5] Center 36 (7~66) winsize 60
8297 10:02:10.535170
8298 10:02:10.538648 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8299 10:02:10.538745
8300 10:02:10.542051 [CATrainingPosCal] consider 1 rank data
8301 10:02:10.545197 u2DelayCellTimex100 = 258/100 ps
8302 10:02:10.551940 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8303 10:02:10.554602 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8304 10:02:10.557959 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8305 10:02:10.561525 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8306 10:02:10.565006 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8307 10:02:10.568023 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8308 10:02:10.568130
8309 10:02:10.571505 CA PerBit enable=1, Macro0, CA PI delay=36
8310 10:02:10.571607
8311 10:02:10.574438 [CBTSetCACLKResult] CA Dly = 36
8312 10:02:10.577819 CS Dly: 9 (0~40)
8313 10:02:10.581308 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8314 10:02:10.584343 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8315 10:02:10.584447 ==
8316 10:02:10.588015 Dram Type= 6, Freq= 0, CH_1, rank 1
8317 10:02:10.594426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 10:02:10.594535 ==
8319 10:02:10.597602 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8320 10:02:10.604718 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8321 10:02:10.607641 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8322 10:02:10.614405 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8323 10:02:10.622008 [CA 0] Center 41 (12~71) winsize 60
8324 10:02:10.625240 [CA 1] Center 42 (12~72) winsize 61
8325 10:02:10.628325 [CA 2] Center 37 (8~67) winsize 60
8326 10:02:10.631428 [CA 3] Center 36 (7~66) winsize 60
8327 10:02:10.634654 [CA 4] Center 37 (8~67) winsize 60
8328 10:02:10.638031 [CA 5] Center 36 (7~66) winsize 60
8329 10:02:10.638135
8330 10:02:10.641756 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8331 10:02:10.641827
8332 10:02:10.648288 [CATrainingPosCal] consider 2 rank data
8333 10:02:10.648395 u2DelayCellTimex100 = 258/100 ps
8334 10:02:10.654591 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8335 10:02:10.658123 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8336 10:02:10.661060 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8337 10:02:10.664644 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8338 10:02:10.667714 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8339 10:02:10.671520 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8340 10:02:10.671596
8341 10:02:10.674687 CA PerBit enable=1, Macro0, CA PI delay=36
8342 10:02:10.674795
8343 10:02:10.677665 [CBTSetCACLKResult] CA Dly = 36
8344 10:02:10.681155 CS Dly: 10 (0~43)
8345 10:02:10.684652 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8346 10:02:10.687514 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8347 10:02:10.687596
8348 10:02:10.691117 ----->DramcWriteLeveling(PI) begin...
8349 10:02:10.691199 ==
8350 10:02:10.694167 Dram Type= 6, Freq= 0, CH_1, rank 0
8351 10:02:10.701086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 10:02:10.701178 ==
8353 10:02:10.704214 Write leveling (Byte 0): 25 => 25
8354 10:02:10.707386 Write leveling (Byte 1): 30 => 30
8355 10:02:10.707479 DramcWriteLeveling(PI) end<-----
8356 10:02:10.710520
8357 10:02:10.710601 ==
8358 10:02:10.713739 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 10:02:10.717488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 10:02:10.717571 ==
8361 10:02:10.720722 [Gating] SW mode calibration
8362 10:02:10.727170 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8363 10:02:10.733815 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8364 10:02:10.737151 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 10:02:10.740224 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 10:02:10.746729 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 10:02:10.750445 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 10:02:10.753683 1 4 16 | B1->B0 | 3333 3232 | 0 1 | (0 0) (1 1)
8369 10:02:10.760020 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 10:02:10.763630 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 10:02:10.766821 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 10:02:10.773263 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 10:02:10.776970 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 10:02:10.779702 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 10:02:10.786701 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8376 10:02:10.790133 1 5 16 | B1->B0 | 2d2d 2a2a | 0 0 | (1 0) (1 0)
8377 10:02:10.793748 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8378 10:02:10.796339 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 10:02:10.803066 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 10:02:10.806193 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 10:02:10.809858 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 10:02:10.816320 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 10:02:10.819526 1 6 12 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
8384 10:02:10.822764 1 6 16 | B1->B0 | 4242 4545 | 0 1 | (0 0) (0 0)
8385 10:02:10.829674 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 10:02:10.832688 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 10:02:10.836130 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 10:02:10.842535 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 10:02:10.846123 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 10:02:10.849299 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 10:02:10.855837 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 10:02:10.858935 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8393 10:02:10.862283 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8394 10:02:10.869529 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 10:02:10.872838 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 10:02:10.875588 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 10:02:10.882504 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 10:02:10.885657 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 10:02:10.888846 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 10:02:10.895109 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 10:02:10.898394 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 10:02:10.901757 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 10:02:10.908672 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 10:02:10.911757 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 10:02:10.914925 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 10:02:10.921898 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 10:02:10.924978 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8408 10:02:10.928298 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8409 10:02:10.934806 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 10:02:10.938331 Total UI for P1: 0, mck2ui 16
8411 10:02:10.941361 best dqsien dly found for B0: ( 1, 9, 14)
8412 10:02:10.944480 Total UI for P1: 0, mck2ui 16
8413 10:02:10.948201 best dqsien dly found for B1: ( 1, 9, 14)
8414 10:02:10.951239 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8415 10:02:10.954945 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8416 10:02:10.955052
8417 10:02:10.958279 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8418 10:02:10.961416 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8419 10:02:10.964567 [Gating] SW calibration Done
8420 10:02:10.964671 ==
8421 10:02:10.967667 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 10:02:10.971397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 10:02:10.971502 ==
8424 10:02:10.974537 RX Vref Scan: 0
8425 10:02:10.974638
8426 10:02:10.977655 RX Vref 0 -> 0, step: 1
8427 10:02:10.977754
8428 10:02:10.977849 RX Delay 0 -> 252, step: 8
8429 10:02:10.984518 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8430 10:02:10.987843 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8431 10:02:10.991217 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8432 10:02:10.994147 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8433 10:02:10.997375 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8434 10:02:11.004169 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8435 10:02:11.007121 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8436 10:02:11.010645 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8437 10:02:11.014285 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8438 10:02:11.017423 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8439 10:02:11.024060 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8440 10:02:11.026987 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8441 10:02:11.030757 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8442 10:02:11.034164 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8443 10:02:11.040440 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8444 10:02:11.043956 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8445 10:02:11.044062 ==
8446 10:02:11.047381 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 10:02:11.050501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 10:02:11.050609 ==
8449 10:02:11.053638 DQS Delay:
8450 10:02:11.053743 DQS0 = 0, DQS1 = 0
8451 10:02:11.053842 DQM Delay:
8452 10:02:11.057207 DQM0 = 132, DQM1 = 126
8453 10:02:11.057308 DQ Delay:
8454 10:02:11.060422 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8455 10:02:11.063254 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8456 10:02:11.070014 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8457 10:02:11.073269 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8458 10:02:11.073382
8459 10:02:11.073477
8460 10:02:11.073584 ==
8461 10:02:11.076543 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 10:02:11.079809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 10:02:11.079915 ==
8464 10:02:11.080014
8465 10:02:11.080117
8466 10:02:11.083070 TX Vref Scan disable
8467 10:02:11.086358 == TX Byte 0 ==
8468 10:02:11.090237 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8469 10:02:11.092745 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8470 10:02:11.096315 == TX Byte 1 ==
8471 10:02:11.099859 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8472 10:02:11.102719 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8473 10:02:11.102839 ==
8474 10:02:11.106203 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 10:02:11.112653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 10:02:11.112764 ==
8477 10:02:11.125103
8478 10:02:11.128483 TX Vref early break, caculate TX vref
8479 10:02:11.131711 TX Vref=16, minBit 9, minWin=21, winSum=358
8480 10:02:11.134794 TX Vref=18, minBit 11, minWin=21, winSum=363
8481 10:02:11.138891 TX Vref=20, minBit 11, minWin=21, winSum=372
8482 10:02:11.141663 TX Vref=22, minBit 8, minWin=22, winSum=383
8483 10:02:11.148388 TX Vref=24, minBit 0, minWin=24, winSum=395
8484 10:02:11.151417 TX Vref=26, minBit 0, minWin=24, winSum=406
8485 10:02:11.154976 TX Vref=28, minBit 1, minWin=24, winSum=410
8486 10:02:11.158161 TX Vref=30, minBit 0, minWin=25, winSum=409
8487 10:02:11.161229 TX Vref=32, minBit 1, minWin=24, winSum=399
8488 10:02:11.164865 TX Vref=34, minBit 0, minWin=23, winSum=389
8489 10:02:11.171275 TX Vref=36, minBit 6, minWin=22, winSum=378
8490 10:02:11.174400 [TxChooseVref] Worse bit 0, Min win 25, Win sum 409, Final Vref 30
8491 10:02:11.174504
8492 10:02:11.177703 Final TX Range 0 Vref 30
8493 10:02:11.177811
8494 10:02:11.177909 ==
8495 10:02:11.181418 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 10:02:11.187660 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 10:02:11.187765 ==
8498 10:02:11.187863
8499 10:02:11.187956
8500 10:02:11.188047 TX Vref Scan disable
8501 10:02:11.194762 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8502 10:02:11.194887 == TX Byte 0 ==
8503 10:02:11.198150 u2DelayCellOfst[0]=22 cells (6 PI)
8504 10:02:11.201129 u2DelayCellOfst[1]=15 cells (4 PI)
8505 10:02:11.204727 u2DelayCellOfst[2]=0 cells (0 PI)
8506 10:02:11.208033 u2DelayCellOfst[3]=11 cells (3 PI)
8507 10:02:11.211137 u2DelayCellOfst[4]=11 cells (3 PI)
8508 10:02:11.214193 u2DelayCellOfst[5]=26 cells (7 PI)
8509 10:02:11.217633 u2DelayCellOfst[6]=22 cells (6 PI)
8510 10:02:11.221348 u2DelayCellOfst[7]=11 cells (3 PI)
8511 10:02:11.224536 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8512 10:02:11.227312 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8513 10:02:11.230891 == TX Byte 1 ==
8514 10:02:11.234309 u2DelayCellOfst[8]=0 cells (0 PI)
8515 10:02:11.237526 u2DelayCellOfst[9]=7 cells (2 PI)
8516 10:02:11.240728 u2DelayCellOfst[10]=11 cells (3 PI)
8517 10:02:11.243958 u2DelayCellOfst[11]=7 cells (2 PI)
8518 10:02:11.247480 u2DelayCellOfst[12]=15 cells (4 PI)
8519 10:02:11.250684 u2DelayCellOfst[13]=18 cells (5 PI)
8520 10:02:11.253952 u2DelayCellOfst[14]=18 cells (5 PI)
8521 10:02:11.257042 u2DelayCellOfst[15]=18 cells (5 PI)
8522 10:02:11.260565 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8523 10:02:11.264068 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8524 10:02:11.266916 DramC Write-DBI on
8525 10:02:11.267024 ==
8526 10:02:11.270504 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 10:02:11.273783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 10:02:11.273893 ==
8529 10:02:11.273987
8530 10:02:11.274095
8531 10:02:11.276934 TX Vref Scan disable
8532 10:02:11.280097 == TX Byte 0 ==
8533 10:02:11.283347 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8534 10:02:11.283453 == TX Byte 1 ==
8535 10:02:11.290171 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8536 10:02:11.290282 DramC Write-DBI off
8537 10:02:11.290387
8538 10:02:11.290479 [DATLAT]
8539 10:02:11.293184 Freq=1600, CH1 RK0
8540 10:02:11.293293
8541 10:02:11.296473 DATLAT Default: 0xf
8542 10:02:11.296577 0, 0xFFFF, sum = 0
8543 10:02:11.299624 1, 0xFFFF, sum = 0
8544 10:02:11.299738 2, 0xFFFF, sum = 0
8545 10:02:11.303239 3, 0xFFFF, sum = 0
8546 10:02:11.303342 4, 0xFFFF, sum = 0
8547 10:02:11.306346 5, 0xFFFF, sum = 0
8548 10:02:11.306461 6, 0xFFFF, sum = 0
8549 10:02:11.309667 7, 0xFFFF, sum = 0
8550 10:02:11.309773 8, 0xFFFF, sum = 0
8551 10:02:11.313225 9, 0xFFFF, sum = 0
8552 10:02:11.313332 10, 0xFFFF, sum = 0
8553 10:02:11.316726 11, 0xFFFF, sum = 0
8554 10:02:11.316829 12, 0xFFFF, sum = 0
8555 10:02:11.320111 13, 0x8FFF, sum = 0
8556 10:02:11.320212 14, 0x0, sum = 1
8557 10:02:11.322729 15, 0x0, sum = 2
8558 10:02:11.322857 16, 0x0, sum = 3
8559 10:02:11.326077 17, 0x0, sum = 4
8560 10:02:11.326206 best_step = 15
8561 10:02:11.326299
8562 10:02:11.326390 ==
8563 10:02:11.329529 Dram Type= 6, Freq= 0, CH_1, rank 0
8564 10:02:11.336188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8565 10:02:11.336296 ==
8566 10:02:11.336393 RX Vref Scan: 1
8567 10:02:11.336513
8568 10:02:11.339617 Set Vref Range= 24 -> 127
8569 10:02:11.339717
8570 10:02:11.342631 RX Vref 24 -> 127, step: 1
8571 10:02:11.342728
8572 10:02:11.345770 RX Delay 11 -> 252, step: 4
8573 10:02:11.345870
8574 10:02:11.349342 Set Vref, RX VrefLevel [Byte0]: 24
8575 10:02:11.352561 [Byte1]: 24
8576 10:02:11.352646
8577 10:02:11.355718 Set Vref, RX VrefLevel [Byte0]: 25
8578 10:02:11.359111 [Byte1]: 25
8579 10:02:11.359195
8580 10:02:11.362380 Set Vref, RX VrefLevel [Byte0]: 26
8581 10:02:11.365493 [Byte1]: 26
8582 10:02:11.369220
8583 10:02:11.369369 Set Vref, RX VrefLevel [Byte0]: 27
8584 10:02:11.372587 [Byte1]: 27
8585 10:02:11.376733
8586 10:02:11.376843 Set Vref, RX VrefLevel [Byte0]: 28
8587 10:02:11.379924 [Byte1]: 28
8588 10:02:11.384207
8589 10:02:11.384286 Set Vref, RX VrefLevel [Byte0]: 29
8590 10:02:11.387967 [Byte1]: 29
8591 10:02:11.392236
8592 10:02:11.392320 Set Vref, RX VrefLevel [Byte0]: 30
8593 10:02:11.395194 [Byte1]: 30
8594 10:02:11.400260
8595 10:02:11.400349 Set Vref, RX VrefLevel [Byte0]: 31
8596 10:02:11.403068 [Byte1]: 31
8597 10:02:11.407230
8598 10:02:11.407314 Set Vref, RX VrefLevel [Byte0]: 32
8599 10:02:11.410495 [Byte1]: 32
8600 10:02:11.414784
8601 10:02:11.414905 Set Vref, RX VrefLevel [Byte0]: 33
8602 10:02:11.418252 [Byte1]: 33
8603 10:02:11.422438
8604 10:02:11.422521 Set Vref, RX VrefLevel [Byte0]: 34
8605 10:02:11.425919 [Byte1]: 34
8606 10:02:11.430269
8607 10:02:11.430353 Set Vref, RX VrefLevel [Byte0]: 35
8608 10:02:11.433618 [Byte1]: 35
8609 10:02:11.437713
8610 10:02:11.437796 Set Vref, RX VrefLevel [Byte0]: 36
8611 10:02:11.441383 [Byte1]: 36
8612 10:02:11.445329
8613 10:02:11.445413 Set Vref, RX VrefLevel [Byte0]: 37
8614 10:02:11.448721 [Byte1]: 37
8615 10:02:11.452886
8616 10:02:11.452970 Set Vref, RX VrefLevel [Byte0]: 38
8617 10:02:11.456510 [Byte1]: 38
8618 10:02:11.461024
8619 10:02:11.461118 Set Vref, RX VrefLevel [Byte0]: 39
8620 10:02:11.463871 [Byte1]: 39
8621 10:02:11.468188
8622 10:02:11.468305 Set Vref, RX VrefLevel [Byte0]: 40
8623 10:02:11.471323 [Byte1]: 40
8624 10:02:11.475909
8625 10:02:11.475984 Set Vref, RX VrefLevel [Byte0]: 41
8626 10:02:11.479392 [Byte1]: 41
8627 10:02:11.483348
8628 10:02:11.483421 Set Vref, RX VrefLevel [Byte0]: 42
8629 10:02:11.486653 [Byte1]: 42
8630 10:02:11.490763
8631 10:02:11.490880 Set Vref, RX VrefLevel [Byte0]: 43
8632 10:02:11.494764 [Byte1]: 43
8633 10:02:11.498720
8634 10:02:11.498821 Set Vref, RX VrefLevel [Byte0]: 44
8635 10:02:11.501818 [Byte1]: 44
8636 10:02:11.506414
8637 10:02:11.506501 Set Vref, RX VrefLevel [Byte0]: 45
8638 10:02:11.509711 [Byte1]: 45
8639 10:02:11.514109
8640 10:02:11.514215 Set Vref, RX VrefLevel [Byte0]: 46
8641 10:02:11.517222 [Byte1]: 46
8642 10:02:11.521605
8643 10:02:11.521709 Set Vref, RX VrefLevel [Byte0]: 47
8644 10:02:11.524865 [Byte1]: 47
8645 10:02:11.528899
8646 10:02:11.528973 Set Vref, RX VrefLevel [Byte0]: 48
8647 10:02:11.532437 [Byte1]: 48
8648 10:02:11.536834
8649 10:02:11.536918 Set Vref, RX VrefLevel [Byte0]: 49
8650 10:02:11.539833 [Byte1]: 49
8651 10:02:11.544162
8652 10:02:11.544245 Set Vref, RX VrefLevel [Byte0]: 50
8653 10:02:11.547648 [Byte1]: 50
8654 10:02:11.552202
8655 10:02:11.552285 Set Vref, RX VrefLevel [Byte0]: 51
8656 10:02:11.555313 [Byte1]: 51
8657 10:02:11.559435
8658 10:02:11.559518 Set Vref, RX VrefLevel [Byte0]: 52
8659 10:02:11.562680 [Byte1]: 52
8660 10:02:11.567443
8661 10:02:11.567526 Set Vref, RX VrefLevel [Byte0]: 53
8662 10:02:11.570514 [Byte1]: 53
8663 10:02:11.574729
8664 10:02:11.574813 Set Vref, RX VrefLevel [Byte0]: 54
8665 10:02:11.577888 [Byte1]: 54
8666 10:02:11.582582
8667 10:02:11.582666 Set Vref, RX VrefLevel [Byte0]: 55
8668 10:02:11.585684 [Byte1]: 55
8669 10:02:11.590403
8670 10:02:11.590487 Set Vref, RX VrefLevel [Byte0]: 56
8671 10:02:11.593354 [Byte1]: 56
8672 10:02:11.597690
8673 10:02:11.597774 Set Vref, RX VrefLevel [Byte0]: 57
8674 10:02:11.600874 [Byte1]: 57
8675 10:02:11.604983
8676 10:02:11.605067 Set Vref, RX VrefLevel [Byte0]: 58
8677 10:02:11.608748 [Byte1]: 58
8678 10:02:11.613160
8679 10:02:11.613244 Set Vref, RX VrefLevel [Byte0]: 59
8680 10:02:11.616004 [Byte1]: 59
8681 10:02:11.620350
8682 10:02:11.620434 Set Vref, RX VrefLevel [Byte0]: 60
8683 10:02:11.623499 [Byte1]: 60
8684 10:02:11.628278
8685 10:02:11.628361 Set Vref, RX VrefLevel [Byte0]: 61
8686 10:02:11.631347 [Byte1]: 61
8687 10:02:11.635847
8688 10:02:11.635930 Set Vref, RX VrefLevel [Byte0]: 62
8689 10:02:11.638853 [Byte1]: 62
8690 10:02:11.643217
8691 10:02:11.643301 Set Vref, RX VrefLevel [Byte0]: 63
8692 10:02:11.646350 [Byte1]: 63
8693 10:02:11.650772
8694 10:02:11.650878 Set Vref, RX VrefLevel [Byte0]: 64
8695 10:02:11.654443 [Byte1]: 64
8696 10:02:11.658718
8697 10:02:11.658801 Set Vref, RX VrefLevel [Byte0]: 65
8698 10:02:11.661651 [Byte1]: 65
8699 10:02:11.666227
8700 10:02:11.666311 Set Vref, RX VrefLevel [Byte0]: 66
8701 10:02:11.669363 [Byte1]: 66
8702 10:02:11.673708
8703 10:02:11.673791 Set Vref, RX VrefLevel [Byte0]: 67
8704 10:02:11.676876 [Byte1]: 67
8705 10:02:11.681514
8706 10:02:11.681597 Set Vref, RX VrefLevel [Byte0]: 68
8707 10:02:11.684770 [Byte1]: 68
8708 10:02:11.688909
8709 10:02:11.688992 Set Vref, RX VrefLevel [Byte0]: 69
8710 10:02:11.692349 [Byte1]: 69
8711 10:02:11.696550
8712 10:02:11.696634 Set Vref, RX VrefLevel [Byte0]: 70
8713 10:02:11.699739 [Byte1]: 70
8714 10:02:11.703985
8715 10:02:11.704070 Final RX Vref Byte 0 = 58 to rank0
8716 10:02:11.707902 Final RX Vref Byte 1 = 54 to rank0
8717 10:02:11.710978 Final RX Vref Byte 0 = 58 to rank1
8718 10:02:11.714117 Final RX Vref Byte 1 = 54 to rank1==
8719 10:02:11.717164 Dram Type= 6, Freq= 0, CH_1, rank 0
8720 10:02:11.724136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8721 10:02:11.724221 ==
8722 10:02:11.724289 DQS Delay:
8723 10:02:11.727315 DQS0 = 0, DQS1 = 0
8724 10:02:11.727435 DQM Delay:
8725 10:02:11.727501 DQM0 = 130, DQM1 = 122
8726 10:02:11.730755 DQ Delay:
8727 10:02:11.733870 DQ0 =136, DQ1 =126, DQ2 =118, DQ3 =126
8728 10:02:11.737265 DQ4 =130, DQ5 =140, DQ6 =142, DQ7 =128
8729 10:02:11.740543 DQ8 =106, DQ9 =112, DQ10 =122, DQ11 =114
8730 10:02:11.743290 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =130
8731 10:02:11.743374
8732 10:02:11.743455
8733 10:02:11.743530
8734 10:02:11.746762 [DramC_TX_OE_Calibration] TA2
8735 10:02:11.750316 Original DQ_B0 (3 6) =30, OEN = 27
8736 10:02:11.753318 Original DQ_B1 (3 6) =30, OEN = 27
8737 10:02:11.757122 24, 0x0, End_B0=24 End_B1=24
8738 10:02:11.760246 25, 0x0, End_B0=25 End_B1=25
8739 10:02:11.760332 26, 0x0, End_B0=26 End_B1=26
8740 10:02:11.763481 27, 0x0, End_B0=27 End_B1=27
8741 10:02:11.766694 28, 0x0, End_B0=28 End_B1=28
8742 10:02:11.769814 29, 0x0, End_B0=29 End_B1=29
8743 10:02:11.769899 30, 0x0, End_B0=30 End_B1=30
8744 10:02:11.773113 31, 0x4141, End_B0=30 End_B1=30
8745 10:02:11.776834 Byte0 end_step=30 best_step=27
8746 10:02:11.779964 Byte1 end_step=30 best_step=27
8747 10:02:11.783170 Byte0 TX OE(2T, 0.5T) = (3, 3)
8748 10:02:11.786726 Byte1 TX OE(2T, 0.5T) = (3, 3)
8749 10:02:11.786855
8750 10:02:11.786940
8751 10:02:11.793096 [DQSOSCAuto] RK0, (LSB)MR18= 0x70c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
8752 10:02:11.796773 CH1 RK0: MR19=303, MR18=70C
8753 10:02:11.803336 CH1_RK0: MR19=0x303, MR18=0x70C, DQSOSC=403, MR23=63, INC=22, DEC=15
8754 10:02:11.803420
8755 10:02:11.806473 ----->DramcWriteLeveling(PI) begin...
8756 10:02:11.806557 ==
8757 10:02:11.809567 Dram Type= 6, Freq= 0, CH_1, rank 1
8758 10:02:11.812697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8759 10:02:11.812781 ==
8760 10:02:11.816567 Write leveling (Byte 0): 23 => 23
8761 10:02:11.819710 Write leveling (Byte 1): 28 => 28
8762 10:02:11.823044 DramcWriteLeveling(PI) end<-----
8763 10:02:11.823127
8764 10:02:11.823192 ==
8765 10:02:11.826006 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 10:02:11.829299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 10:02:11.832570 ==
8768 10:02:11.832654 [Gating] SW mode calibration
8769 10:02:11.842625 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8770 10:02:11.845901 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8771 10:02:11.848957 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 10:02:11.855431 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 10:02:11.859132 1 4 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8774 10:02:11.862091 1 4 12 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8775 10:02:11.871576 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 10:02:11.871989 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 10:02:11.875394 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 10:02:11.881759 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 10:02:11.885057 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 10:02:11.888208 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 10:02:11.894905 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
8782 10:02:11.898139 1 5 12 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (1 0)
8783 10:02:11.901722 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 10:02:11.908386 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 10:02:11.911469 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 10:02:11.914662 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 10:02:11.921319 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 10:02:11.924363 1 6 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
8789 10:02:11.931002 1 6 8 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8790 10:02:11.934254 1 6 12 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
8791 10:02:11.937744 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 10:02:11.944497 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 10:02:11.947542 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 10:02:11.951001 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 10:02:11.957761 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 10:02:11.960862 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 10:02:11.964070 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8798 10:02:11.970685 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8799 10:02:11.974142 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 10:02:11.977295 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 10:02:11.984052 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 10:02:11.987079 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 10:02:11.990287 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 10:02:11.996933 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 10:02:12.000046 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 10:02:12.003826 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 10:02:12.009881 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 10:02:12.013433 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 10:02:12.016679 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 10:02:12.023353 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 10:02:12.026800 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 10:02:12.029913 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8813 10:02:12.036300 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8814 10:02:12.039843 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8815 10:02:12.043087 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 10:02:12.046347 Total UI for P1: 0, mck2ui 16
8817 10:02:12.049483 best dqsien dly found for B0: ( 1, 9, 8)
8818 10:02:12.053238 Total UI for P1: 0, mck2ui 16
8819 10:02:12.056247 best dqsien dly found for B1: ( 1, 9, 12)
8820 10:02:12.059398 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8821 10:02:12.062810 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8822 10:02:12.062931
8823 10:02:12.066300 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8824 10:02:12.072550 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8825 10:02:12.072632 [Gating] SW calibration Done
8826 10:02:12.075975 ==
8827 10:02:12.079444 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 10:02:12.082328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 10:02:12.082431 ==
8830 10:02:12.082543 RX Vref Scan: 0
8831 10:02:12.082637
8832 10:02:12.086246 RX Vref 0 -> 0, step: 1
8833 10:02:12.086354
8834 10:02:12.089049 RX Delay 0 -> 252, step: 8
8835 10:02:12.092724 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8836 10:02:12.095974 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8837 10:02:12.099144 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8838 10:02:12.105441 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8839 10:02:12.108648 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8840 10:02:12.111947 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8841 10:02:12.115500 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8842 10:02:12.118799 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8843 10:02:12.125401 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8844 10:02:12.128633 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8845 10:02:12.131752 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8846 10:02:12.135252 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8847 10:02:12.141734 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8848 10:02:12.144882 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8849 10:02:12.148254 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8850 10:02:12.151829 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8851 10:02:12.151905 ==
8852 10:02:12.155303 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 10:02:12.161785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 10:02:12.161899 ==
8855 10:02:12.161997 DQS Delay:
8856 10:02:12.164857 DQS0 = 0, DQS1 = 0
8857 10:02:12.164960 DQM Delay:
8858 10:02:12.165063 DQM0 = 129, DQM1 = 128
8859 10:02:12.168230 DQ Delay:
8860 10:02:12.171516 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8861 10:02:12.174804 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8862 10:02:12.177619 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8863 10:02:12.181098 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8864 10:02:12.181205
8865 10:02:12.181302
8866 10:02:12.181396 ==
8867 10:02:12.184428 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 10:02:12.190919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 10:02:12.191036 ==
8870 10:02:12.191136
8871 10:02:12.191226
8872 10:02:12.191336 TX Vref Scan disable
8873 10:02:12.194693 == TX Byte 0 ==
8874 10:02:12.197770 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8875 10:02:12.204340 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8876 10:02:12.204417 == TX Byte 1 ==
8877 10:02:12.207534 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8878 10:02:12.213982 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8879 10:02:12.214072 ==
8880 10:02:12.217091 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 10:02:12.220513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 10:02:12.220617 ==
8883 10:02:12.234800
8884 10:02:12.238257 TX Vref early break, caculate TX vref
8885 10:02:12.241448 TX Vref=16, minBit 0, minWin=22, winSum=376
8886 10:02:12.244988 TX Vref=18, minBit 0, minWin=21, winSum=382
8887 10:02:12.248040 TX Vref=20, minBit 0, minWin=21, winSum=395
8888 10:02:12.251185 TX Vref=22, minBit 0, minWin=23, winSum=399
8889 10:02:12.254446 TX Vref=24, minBit 0, minWin=24, winSum=411
8890 10:02:12.261597 TX Vref=26, minBit 0, minWin=23, winSum=411
8891 10:02:12.264331 TX Vref=28, minBit 0, minWin=24, winSum=421
8892 10:02:12.267625 TX Vref=30, minBit 5, minWin=24, winSum=413
8893 10:02:12.271330 TX Vref=32, minBit 1, minWin=24, winSum=405
8894 10:02:12.274581 TX Vref=34, minBit 0, minWin=23, winSum=400
8895 10:02:12.281171 TX Vref=36, minBit 0, minWin=23, winSum=386
8896 10:02:12.284667 [TxChooseVref] Worse bit 0, Min win 24, Win sum 421, Final Vref 28
8897 10:02:12.284787
8898 10:02:12.287566 Final TX Range 0 Vref 28
8899 10:02:12.287671
8900 10:02:12.287770 ==
8901 10:02:12.290542 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 10:02:12.294188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 10:02:12.297183 ==
8904 10:02:12.297267
8905 10:02:12.297371
8906 10:02:12.297462 TX Vref Scan disable
8907 10:02:12.304306 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8908 10:02:12.304386 == TX Byte 0 ==
8909 10:02:12.307571 u2DelayCellOfst[0]=22 cells (6 PI)
8910 10:02:12.310929 u2DelayCellOfst[1]=15 cells (4 PI)
8911 10:02:12.314106 u2DelayCellOfst[2]=0 cells (0 PI)
8912 10:02:12.317328 u2DelayCellOfst[3]=7 cells (2 PI)
8913 10:02:12.320509 u2DelayCellOfst[4]=7 cells (2 PI)
8914 10:02:12.323818 u2DelayCellOfst[5]=22 cells (6 PI)
8915 10:02:12.327559 u2DelayCellOfst[6]=22 cells (6 PI)
8916 10:02:12.330589 u2DelayCellOfst[7]=7 cells (2 PI)
8917 10:02:12.333758 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8918 10:02:12.337073 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8919 10:02:12.340638 == TX Byte 1 ==
8920 10:02:12.343769 u2DelayCellOfst[8]=0 cells (0 PI)
8921 10:02:12.347000 u2DelayCellOfst[9]=7 cells (2 PI)
8922 10:02:12.350230 u2DelayCellOfst[10]=15 cells (4 PI)
8923 10:02:12.353419 u2DelayCellOfst[11]=7 cells (2 PI)
8924 10:02:12.356718 u2DelayCellOfst[12]=18 cells (5 PI)
8925 10:02:12.359850 u2DelayCellOfst[13]=18 cells (5 PI)
8926 10:02:12.359926 u2DelayCellOfst[14]=22 cells (6 PI)
8927 10:02:12.363541 u2DelayCellOfst[15]=22 cells (6 PI)
8928 10:02:12.370323 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8929 10:02:12.373525 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8930 10:02:12.376759 DramC Write-DBI on
8931 10:02:12.376848 ==
8932 10:02:12.379689 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 10:02:12.383436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 10:02:12.383552 ==
8935 10:02:12.383647
8936 10:02:12.383743
8937 10:02:12.386749 TX Vref Scan disable
8938 10:02:12.386898 == TX Byte 0 ==
8939 10:02:12.392865 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8940 10:02:12.392972 == TX Byte 1 ==
8941 10:02:12.399640 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8942 10:02:12.399751 DramC Write-DBI off
8943 10:02:12.399856
8944 10:02:12.399948 [DATLAT]
8945 10:02:12.402656 Freq=1600, CH1 RK1
8946 10:02:12.402738
8947 10:02:12.402867 DATLAT Default: 0xf
8948 10:02:12.406202 0, 0xFFFF, sum = 0
8949 10:02:12.409702 1, 0xFFFF, sum = 0
8950 10:02:12.409807 2, 0xFFFF, sum = 0
8951 10:02:12.412624 3, 0xFFFF, sum = 0
8952 10:02:12.412699 4, 0xFFFF, sum = 0
8953 10:02:12.415962 5, 0xFFFF, sum = 0
8954 10:02:12.416059 6, 0xFFFF, sum = 0
8955 10:02:12.419161 7, 0xFFFF, sum = 0
8956 10:02:12.419238 8, 0xFFFF, sum = 0
8957 10:02:12.422442 9, 0xFFFF, sum = 0
8958 10:02:12.422554 10, 0xFFFF, sum = 0
8959 10:02:12.425637 11, 0xFFFF, sum = 0
8960 10:02:12.425716 12, 0xFFFF, sum = 0
8961 10:02:12.429369 13, 0x8FFF, sum = 0
8962 10:02:12.429473 14, 0x0, sum = 1
8963 10:02:12.432498 15, 0x0, sum = 2
8964 10:02:12.432604 16, 0x0, sum = 3
8965 10:02:12.435742 17, 0x0, sum = 4
8966 10:02:12.435824 best_step = 15
8967 10:02:12.435888
8968 10:02:12.435948 ==
8969 10:02:12.439059 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 10:02:12.445389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 10:02:12.445470 ==
8972 10:02:12.445574 RX Vref Scan: 0
8973 10:02:12.445666
8974 10:02:12.449001 RX Vref 0 -> 0, step: 1
8975 10:02:12.449090
8976 10:02:12.452175 RX Delay 11 -> 252, step: 4
8977 10:02:12.455512 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8978 10:02:12.458730 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8979 10:02:12.465041 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8980 10:02:12.468305 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8981 10:02:12.471811 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8982 10:02:12.475042 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8983 10:02:12.478256 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8984 10:02:12.484997 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
8985 10:02:12.488228 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
8986 10:02:12.491537 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8987 10:02:12.495256 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8988 10:02:12.498510 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
8989 10:02:12.504683 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8990 10:02:12.508063 iDelay=195, Bit 13, Center 130 (75 ~ 186) 112
8991 10:02:12.511537 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8992 10:02:12.515055 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8993 10:02:12.515130 ==
8994 10:02:12.518252 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 10:02:12.524536 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 10:02:12.524613 ==
8997 10:02:12.524678 DQS Delay:
8998 10:02:12.528026 DQS0 = 0, DQS1 = 0
8999 10:02:12.528097 DQM Delay:
9000 10:02:12.531300 DQM0 = 127, DQM1 = 123
9001 10:02:12.531370 DQ Delay:
9002 10:02:12.534474 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =122
9003 10:02:12.537742 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9004 10:02:12.541040 DQ8 =108, DQ9 =112, DQ10 =128, DQ11 =118
9005 10:02:12.544530 DQ12 =132, DQ13 =130, DQ14 =130, DQ15 =132
9006 10:02:12.544604
9007 10:02:12.544667
9008 10:02:12.544726
9009 10:02:12.547963 [DramC_TX_OE_Calibration] TA2
9010 10:02:12.551176 Original DQ_B0 (3 6) =30, OEN = 27
9011 10:02:12.554454 Original DQ_B1 (3 6) =30, OEN = 27
9012 10:02:12.557493 24, 0x0, End_B0=24 End_B1=24
9013 10:02:12.561321 25, 0x0, End_B0=25 End_B1=25
9014 10:02:12.561412 26, 0x0, End_B0=26 End_B1=26
9015 10:02:12.564567 27, 0x0, End_B0=27 End_B1=27
9016 10:02:12.567881 28, 0x0, End_B0=28 End_B1=28
9017 10:02:12.571202 29, 0x0, End_B0=29 End_B1=29
9018 10:02:12.571319 30, 0x0, End_B0=30 End_B1=30
9019 10:02:12.574055 31, 0x4141, End_B0=30 End_B1=30
9020 10:02:12.577755 Byte0 end_step=30 best_step=27
9021 10:02:12.580847 Byte1 end_step=30 best_step=27
9022 10:02:12.584099 Byte0 TX OE(2T, 0.5T) = (3, 3)
9023 10:02:12.587172 Byte1 TX OE(2T, 0.5T) = (3, 3)
9024 10:02:12.587271
9025 10:02:12.587371
9026 10:02:12.593946 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9027 10:02:12.597231 CH1 RK1: MR19=303, MR18=F1B
9028 10:02:12.603707 CH1_RK1: MR19=0x303, MR18=0xF1B, DQSOSC=396, MR23=63, INC=23, DEC=15
9029 10:02:12.607612 [RxdqsGatingPostProcess] freq 1600
9030 10:02:12.613956 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9031 10:02:12.614037 best DQS0 dly(2T, 0.5T) = (1, 1)
9032 10:02:12.616860 best DQS1 dly(2T, 0.5T) = (1, 1)
9033 10:02:12.620286 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9034 10:02:12.623673 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9035 10:02:12.626706 best DQS0 dly(2T, 0.5T) = (1, 1)
9036 10:02:12.630119 best DQS1 dly(2T, 0.5T) = (1, 1)
9037 10:02:12.633545 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9038 10:02:12.636638 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9039 10:02:12.640368 Pre-setting of DQS Precalculation
9040 10:02:12.643642 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9041 10:02:12.653072 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9042 10:02:12.660025 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9043 10:02:12.660113
9044 10:02:12.660180
9045 10:02:12.663030 [Calibration Summary] 3200 Mbps
9046 10:02:12.663114 CH 0, Rank 0
9047 10:02:12.666324 SW Impedance : PASS
9048 10:02:12.666408 DUTY Scan : NO K
9049 10:02:12.670035 ZQ Calibration : PASS
9050 10:02:12.673258 Jitter Meter : NO K
9051 10:02:12.673369 CBT Training : PASS
9052 10:02:12.676529 Write leveling : PASS
9053 10:02:12.679439 RX DQS gating : PASS
9054 10:02:12.679533 RX DQ/DQS(RDDQC) : PASS
9055 10:02:12.683148 TX DQ/DQS : PASS
9056 10:02:12.686214 RX DATLAT : PASS
9057 10:02:12.686331 RX DQ/DQS(Engine): PASS
9058 10:02:12.689436 TX OE : PASS
9059 10:02:12.689554 All Pass.
9060 10:02:12.689650
9061 10:02:12.692870 CH 0, Rank 1
9062 10:02:12.692979 SW Impedance : PASS
9063 10:02:12.696250 DUTY Scan : NO K
9064 10:02:12.699770 ZQ Calibration : PASS
9065 10:02:12.699877 Jitter Meter : NO K
9066 10:02:12.702680 CBT Training : PASS
9067 10:02:12.705757 Write leveling : PASS
9068 10:02:12.705847 RX DQS gating : PASS
9069 10:02:12.709375 RX DQ/DQS(RDDQC) : PASS
9070 10:02:12.712742 TX DQ/DQS : PASS
9071 10:02:12.712836 RX DATLAT : PASS
9072 10:02:12.715867 RX DQ/DQS(Engine): PASS
9073 10:02:12.718919 TX OE : PASS
9074 10:02:12.719004 All Pass.
9075 10:02:12.719110
9076 10:02:12.719202 CH 1, Rank 0
9077 10:02:12.722266 SW Impedance : PASS
9078 10:02:12.725820 DUTY Scan : NO K
9079 10:02:12.725924 ZQ Calibration : PASS
9080 10:02:12.728963 Jitter Meter : NO K
9081 10:02:12.729074 CBT Training : PASS
9082 10:02:12.732329 Write leveling : PASS
9083 10:02:12.735843 RX DQS gating : PASS
9084 10:02:12.735953 RX DQ/DQS(RDDQC) : PASS
9085 10:02:12.739118 TX DQ/DQS : PASS
9086 10:02:12.742215 RX DATLAT : PASS
9087 10:02:12.742317 RX DQ/DQS(Engine): PASS
9088 10:02:12.745422 TX OE : PASS
9089 10:02:12.745523 All Pass.
9090 10:02:12.745618
9091 10:02:12.748621 CH 1, Rank 1
9092 10:02:12.748729 SW Impedance : PASS
9093 10:02:12.751805 DUTY Scan : NO K
9094 10:02:12.755441 ZQ Calibration : PASS
9095 10:02:12.755521 Jitter Meter : NO K
9096 10:02:12.758578 CBT Training : PASS
9097 10:02:12.761691 Write leveling : PASS
9098 10:02:12.761768 RX DQS gating : PASS
9099 10:02:12.765193 RX DQ/DQS(RDDQC) : PASS
9100 10:02:12.768607 TX DQ/DQS : PASS
9101 10:02:12.768684 RX DATLAT : PASS
9102 10:02:12.771529 RX DQ/DQS(Engine): PASS
9103 10:02:12.774783 TX OE : PASS
9104 10:02:12.774915 All Pass.
9105 10:02:12.774996
9106 10:02:12.778361 DramC Write-DBI on
9107 10:02:12.778472 PER_BANK_REFRESH: Hybrid Mode
9108 10:02:12.781658 TX_TRACKING: ON
9109 10:02:12.791643 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9110 10:02:12.798363 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9111 10:02:12.804823 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9112 10:02:12.807886 [FAST_K] Save calibration result to emmc
9113 10:02:12.811391 sync common calibartion params.
9114 10:02:12.814600 sync cbt_mode0:1, 1:1
9115 10:02:12.814704 dram_init: ddr_geometry: 2
9116 10:02:12.817691 dram_init: ddr_geometry: 2
9117 10:02:12.821054 dram_init: ddr_geometry: 2
9118 10:02:12.824423 0:dram_rank_size:100000000
9119 10:02:12.824510 1:dram_rank_size:100000000
9120 10:02:12.830934 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9121 10:02:12.834419 DFS_SHUFFLE_HW_MODE: ON
9122 10:02:12.837408 dramc_set_vcore_voltage set vcore to 725000
9123 10:02:12.840762 Read voltage for 1600, 0
9124 10:02:12.840874 Vio18 = 0
9125 10:02:12.840973 Vcore = 725000
9126 10:02:12.844097 Vdram = 0
9127 10:02:12.844200 Vddq = 0
9128 10:02:12.844306 Vmddr = 0
9129 10:02:12.847345 switch to 3200 Mbps bootup
9130 10:02:12.847420 [DramcRunTimeConfig]
9131 10:02:12.850723 PHYPLL
9132 10:02:12.850836 DPM_CONTROL_AFTERK: ON
9133 10:02:12.854318 PER_BANK_REFRESH: ON
9134 10:02:12.857615 REFRESH_OVERHEAD_REDUCTION: ON
9135 10:02:12.857719 CMD_PICG_NEW_MODE: OFF
9136 10:02:12.860979 XRTWTW_NEW_MODE: ON
9137 10:02:12.861082 XRTRTR_NEW_MODE: ON
9138 10:02:12.864125 TX_TRACKING: ON
9139 10:02:12.864201 RDSEL_TRACKING: OFF
9140 10:02:12.867464 DQS Precalculation for DVFS: ON
9141 10:02:12.870703 RX_TRACKING: OFF
9142 10:02:12.870806 HW_GATING DBG: ON
9143 10:02:12.874231 ZQCS_ENABLE_LP4: ON
9144 10:02:12.874335 RX_PICG_NEW_MODE: ON
9145 10:02:12.877074 TX_PICG_NEW_MODE: ON
9146 10:02:12.877174 ENABLE_RX_DCM_DPHY: ON
9147 10:02:12.880399 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9148 10:02:12.883738 DUMMY_READ_FOR_TRACKING: OFF
9149 10:02:12.887289 !!! SPM_CONTROL_AFTERK: OFF
9150 10:02:12.890729 !!! SPM could not control APHY
9151 10:02:12.890841 IMPEDANCE_TRACKING: ON
9152 10:02:12.893881 TEMP_SENSOR: ON
9153 10:02:12.893981 HW_SAVE_FOR_SR: OFF
9154 10:02:12.897129 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9155 10:02:12.900524 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9156 10:02:12.903886 Read ODT Tracking: ON
9157 10:02:12.907073 Refresh Rate DeBounce: ON
9158 10:02:12.907173 DFS_NO_QUEUE_FLUSH: ON
9159 10:02:12.910279 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9160 10:02:12.913409 ENABLE_DFS_RUNTIME_MRW: OFF
9161 10:02:12.917201 DDR_RESERVE_NEW_MODE: ON
9162 10:02:12.917306 MR_CBT_SWITCH_FREQ: ON
9163 10:02:12.920405 =========================
9164 10:02:12.939352 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9165 10:02:12.942346 dram_init: ddr_geometry: 2
9166 10:02:12.960756 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9167 10:02:12.964348 dram_init: dram init end (result: 0)
9168 10:02:12.970728 DRAM-K: Full calibration passed in 24569 msecs
9169 10:02:12.974246 MRC: failed to locate region type 0.
9170 10:02:12.974328 DRAM rank0 size:0x100000000,
9171 10:02:12.977602 DRAM rank1 size=0x100000000
9172 10:02:12.987061 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9173 10:02:12.993840 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9174 10:02:13.000285 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9175 10:02:13.006881 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9176 10:02:13.010193 DRAM rank0 size:0x100000000,
9177 10:02:13.013892 DRAM rank1 size=0x100000000
9178 10:02:13.014003 CBMEM:
9179 10:02:13.017206 IMD: root @ 0xfffff000 254 entries.
9180 10:02:13.020286 IMD: root @ 0xffffec00 62 entries.
9181 10:02:13.024002 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9182 10:02:13.030309 WARNING: RO_VPD is uninitialized or empty.
9183 10:02:13.033590 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9184 10:02:13.041167 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9185 10:02:13.053479 read SPI 0x42894 0xe01e: 6229 us, 9210 KB/s, 73.680 Mbps
9186 10:02:13.064803 BS: romstage times (exec / console): total (unknown) / 24033 ms
9187 10:02:13.064913
9188 10:02:13.065010
9189 10:02:13.074699 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9190 10:02:13.078191 ARM64: Exception handlers installed.
9191 10:02:13.081462 ARM64: Testing exception
9192 10:02:13.084490 ARM64: Done test exception
9193 10:02:13.084598 Enumerating buses...
9194 10:02:13.088085 Show all devs... Before device enumeration.
9195 10:02:13.091388 Root Device: enabled 1
9196 10:02:13.094959 CPU_CLUSTER: 0: enabled 1
9197 10:02:13.095032 CPU: 00: enabled 1
9198 10:02:13.097754 Compare with tree...
9199 10:02:13.097850 Root Device: enabled 1
9200 10:02:13.100999 CPU_CLUSTER: 0: enabled 1
9201 10:02:13.104239 CPU: 00: enabled 1
9202 10:02:13.104337 Root Device scanning...
9203 10:02:13.107821 scan_static_bus for Root Device
9204 10:02:13.110876 CPU_CLUSTER: 0 enabled
9205 10:02:13.113982 scan_static_bus for Root Device done
9206 10:02:13.117761 scan_bus: bus Root Device finished in 8 msecs
9207 10:02:13.117863 done
9208 10:02:13.124025 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9209 10:02:13.127672 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9210 10:02:13.134149 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9211 10:02:13.140900 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9212 10:02:13.141015 Allocating resources...
9213 10:02:13.143894 Reading resources...
9214 10:02:13.147113 Root Device read_resources bus 0 link: 0
9215 10:02:13.150881 DRAM rank0 size:0x100000000,
9216 10:02:13.150985 DRAM rank1 size=0x100000000
9217 10:02:13.157141 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9218 10:02:13.157249 CPU: 00 missing read_resources
9219 10:02:13.163627 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9220 10:02:13.167027 Root Device read_resources bus 0 link: 0 done
9221 10:02:13.170227 Done reading resources.
9222 10:02:13.173822 Show resources in subtree (Root Device)...After reading.
9223 10:02:13.177050 Root Device child on link 0 CPU_CLUSTER: 0
9224 10:02:13.180689 CPU_CLUSTER: 0 child on link 0 CPU: 00
9225 10:02:13.190222 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9226 10:02:13.190331 CPU: 00
9227 10:02:13.196621 Root Device assign_resources, bus 0 link: 0
9228 10:02:13.199911 CPU_CLUSTER: 0 missing set_resources
9229 10:02:13.203133 Root Device assign_resources, bus 0 link: 0 done
9230 10:02:13.206809 Done setting resources.
9231 10:02:13.209983 Show resources in subtree (Root Device)...After assigning values.
9232 10:02:13.213521 Root Device child on link 0 CPU_CLUSTER: 0
9233 10:02:13.219984 CPU_CLUSTER: 0 child on link 0 CPU: 00
9234 10:02:13.226757 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9235 10:02:13.226902 CPU: 00
9236 10:02:13.229879 Done allocating resources.
9237 10:02:13.236713 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9238 10:02:13.236822 Enabling resources...
9239 10:02:13.239825 done.
9240 10:02:13.242960 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9241 10:02:13.246359 Initializing devices...
9242 10:02:13.246459 Root Device init
9243 10:02:13.249828 init hardware done!
9244 10:02:13.249930 0x00000018: ctrlr->caps
9245 10:02:13.252685 52.000 MHz: ctrlr->f_max
9246 10:02:13.256541 0.400 MHz: ctrlr->f_min
9247 10:02:13.256651 0x40ff8080: ctrlr->voltages
9248 10:02:13.259776 sclk: 390625
9249 10:02:13.259878 Bus Width = 1
9250 10:02:13.262661 sclk: 390625
9251 10:02:13.262759 Bus Width = 1
9252 10:02:13.266086 Early init status = 3
9253 10:02:13.269681 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9254 10:02:13.272687 in-header: 03 fc 00 00 01 00 00 00
9255 10:02:13.275676 in-data: 00
9256 10:02:13.279387 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9257 10:02:13.283610 in-header: 03 fd 00 00 00 00 00 00
9258 10:02:13.287233 in-data:
9259 10:02:13.290714 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9260 10:02:13.293662 in-header: 03 fc 00 00 01 00 00 00
9261 10:02:13.296987 in-data: 00
9262 10:02:13.300492 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9263 10:02:13.305552 in-header: 03 fd 00 00 00 00 00 00
9264 10:02:13.309095 in-data:
9265 10:02:13.312065 [SSUSB] Setting up USB HOST controller...
9266 10:02:13.315277 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9267 10:02:13.318715 [SSUSB] phy power-on done.
9268 10:02:13.322039 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9269 10:02:13.328429 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9270 10:02:13.331648 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9271 10:02:13.338121 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9272 10:02:13.344548 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9273 10:02:13.351184 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9274 10:02:13.358082 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9275 10:02:13.364586 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9276 10:02:13.367572 SPM: binary array size = 0x9dc
9277 10:02:13.374149 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9278 10:02:13.377347 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9279 10:02:13.387373 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9280 10:02:13.390962 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9281 10:02:13.394244 configure_display: Starting display init
9282 10:02:13.428656 anx7625_power_on_init: Init interface.
9283 10:02:13.432327 anx7625_disable_pd_protocol: Disabled PD feature.
9284 10:02:13.435477 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9285 10:02:13.463381 anx7625_start_dp_work: Secure OCM version=00
9286 10:02:13.466722 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9287 10:02:13.481349 sp_tx_get_edid_block: EDID Block = 1
9288 10:02:13.583632 Extracted contents:
9289 10:02:13.587227 header: 00 ff ff ff ff ff ff 00
9290 10:02:13.590281 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9291 10:02:13.593796 version: 01 04
9292 10:02:13.596972 basic params: 95 1f 11 78 0a
9293 10:02:13.600140 chroma info: 76 90 94 55 54 90 27 21 50 54
9294 10:02:13.603619 established: 00 00 00
9295 10:02:13.610091 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9296 10:02:13.617222 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9297 10:02:13.620276 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9298 10:02:13.626672 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9299 10:02:13.633251 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9300 10:02:13.636440 extensions: 00
9301 10:02:13.636549 checksum: fb
9302 10:02:13.636625
9303 10:02:13.643555 Manufacturer: IVO Model 57d Serial Number 0
9304 10:02:13.643639 Made week 0 of 2020
9305 10:02:13.646367 EDID version: 1.4
9306 10:02:13.646448 Digital display
9307 10:02:13.649595 6 bits per primary color channel
9308 10:02:13.649677 DisplayPort interface
9309 10:02:13.652770 Maximum image size: 31 cm x 17 cm
9310 10:02:13.656476 Gamma: 220%
9311 10:02:13.656583 Check DPMS levels
9312 10:02:13.662745 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9313 10:02:13.666022 First detailed timing is preferred timing
9314 10:02:13.669152 Established timings supported:
9315 10:02:13.669234 Standard timings supported:
9316 10:02:13.672668 Detailed timings
9317 10:02:13.676157 Hex of detail: 383680a07038204018303c0035ae10000019
9318 10:02:13.682558 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9319 10:02:13.686203 0780 0798 07c8 0820 hborder 0
9320 10:02:13.689079 0438 043b 0447 0458 vborder 0
9321 10:02:13.692783 -hsync -vsync
9322 10:02:13.692865 Did detailed timing
9323 10:02:13.699451 Hex of detail: 000000000000000000000000000000000000
9324 10:02:13.702567 Manufacturer-specified data, tag 0
9325 10:02:13.705926 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9326 10:02:13.709017 ASCII string: InfoVision
9327 10:02:13.712650 Hex of detail: 000000fe00523134304e574635205248200a
9328 10:02:13.715911 ASCII string: R140NWF5 RH
9329 10:02:13.715992 Checksum
9330 10:02:13.719031 Checksum: 0xfb (valid)
9331 10:02:13.722574 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9332 10:02:13.725878 DSI data_rate: 832800000 bps
9333 10:02:13.732210 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9334 10:02:13.735838 anx7625_parse_edid: pixelclock(138800).
9335 10:02:13.738917 hactive(1920), hsync(48), hfp(24), hbp(88)
9336 10:02:13.741969 vactive(1080), vsync(12), vfp(3), vbp(17)
9337 10:02:13.745232 anx7625_dsi_config: config dsi.
9338 10:02:13.751818 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9339 10:02:13.765730 anx7625_dsi_config: success to config DSI
9340 10:02:13.768930 anx7625_dp_start: MIPI phy setup OK.
9341 10:02:13.772595 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9342 10:02:13.775673 mtk_ddp_mode_set invalid vrefresh 60
9343 10:02:13.778707 main_disp_path_setup
9344 10:02:13.778789 ovl_layer_smi_id_en
9345 10:02:13.782128 ovl_layer_smi_id_en
9346 10:02:13.782211 ccorr_config
9347 10:02:13.782285 aal_config
9348 10:02:13.785572 gamma_config
9349 10:02:13.785648 postmask_config
9350 10:02:13.788710 dither_config
9351 10:02:13.792197 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9352 10:02:13.798860 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9353 10:02:13.801712 Root Device init finished in 551 msecs
9354 10:02:13.805410 CPU_CLUSTER: 0 init
9355 10:02:13.811977 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9356 10:02:13.818324 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9357 10:02:13.818404 APU_MBOX 0x190000b0 = 0x10001
9358 10:02:13.821659 APU_MBOX 0x190001b0 = 0x10001
9359 10:02:13.824958 APU_MBOX 0x190005b0 = 0x10001
9360 10:02:13.828474 APU_MBOX 0x190006b0 = 0x10001
9361 10:02:13.834635 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9362 10:02:13.844853 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9363 10:02:13.857090 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9364 10:02:13.863969 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9365 10:02:13.875379 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9366 10:02:13.884439 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9367 10:02:13.887803 CPU_CLUSTER: 0 init finished in 81 msecs
9368 10:02:13.891291 Devices initialized
9369 10:02:13.894207 Show all devs... After init.
9370 10:02:13.894290 Root Device: enabled 1
9371 10:02:13.897653 CPU_CLUSTER: 0: enabled 1
9372 10:02:13.901153 CPU: 00: enabled 1
9373 10:02:13.904623 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9374 10:02:13.907718 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9375 10:02:13.910753 ELOG: NV offset 0x57f000 size 0x1000
9376 10:02:13.917696 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9377 10:02:13.924551 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9378 10:02:13.927693 ELOG: Event(17) added with size 13 at 2023-06-10 10:02:16 UTC
9379 10:02:13.934390 out: cmd=0x121: 03 db 21 01 00 00 00 00
9380 10:02:13.937522 in-header: 03 5e 00 00 2c 00 00 00
9381 10:02:13.948034 in-data: 00 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9382 10:02:13.954046 ELOG: Event(A1) added with size 10 at 2023-06-10 10:02:16 UTC
9383 10:02:13.960571 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9384 10:02:13.967409 ELOG: Event(A0) added with size 9 at 2023-06-10 10:02:16 UTC
9385 10:02:13.970684 elog_add_boot_reason: Logged dev mode boot
9386 10:02:13.976981 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9387 10:02:13.977105 Finalize devices...
9388 10:02:13.980275 Devices finalized
9389 10:02:13.984355 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9390 10:02:13.987287 Writing coreboot table at 0xffe64000
9391 10:02:13.990264 0. 000000000010a000-0000000000113fff: RAMSTAGE
9392 10:02:13.996971 1. 0000000040000000-00000000400fffff: RAM
9393 10:02:14.000434 2. 0000000040100000-000000004032afff: RAMSTAGE
9394 10:02:14.003465 3. 000000004032b000-00000000545fffff: RAM
9395 10:02:14.007056 4. 0000000054600000-000000005465ffff: BL31
9396 10:02:14.010143 5. 0000000054660000-00000000ffe63fff: RAM
9397 10:02:14.016553 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9398 10:02:14.019792 7. 0000000100000000-000000023fffffff: RAM
9399 10:02:14.023616 Passing 5 GPIOs to payload:
9400 10:02:14.026743 NAME | PORT | POLARITY | VALUE
9401 10:02:14.033098 EC in RW | 0x000000aa | low | undefined
9402 10:02:14.036440 EC interrupt | 0x00000005 | low | undefined
9403 10:02:14.039910 TPM interrupt | 0x000000ab | high | undefined
9404 10:02:14.046301 SD card detect | 0x00000011 | high | undefined
9405 10:02:14.049748 speaker enable | 0x00000093 | high | undefined
9406 10:02:14.052915 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9407 10:02:14.055959 in-header: 03 f9 00 00 02 00 00 00
9408 10:02:14.059624 in-data: 02 00
9409 10:02:14.062791 ADC[4]: Raw value=897410 ID=7
9410 10:02:14.062914 ADC[3]: Raw value=213440 ID=1
9411 10:02:14.066001 RAM Code: 0x71
9412 10:02:14.069312 ADC[6]: Raw value=74722 ID=0
9413 10:02:14.072642 ADC[5]: Raw value=212330 ID=1
9414 10:02:14.072725 SKU Code: 0x1
9415 10:02:14.079584 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9416 10:02:14.079668 coreboot table: 964 bytes.
9417 10:02:14.082736 IMD ROOT 0. 0xfffff000 0x00001000
9418 10:02:14.085761 IMD SMALL 1. 0xffffe000 0x00001000
9419 10:02:14.089004 RO MCACHE 2. 0xffffc000 0x00001104
9420 10:02:14.092642 CONSOLE 3. 0xfff7c000 0x00080000
9421 10:02:14.095940 FMAP 4. 0xfff7b000 0x00000452
9422 10:02:14.098786 TIME STAMP 5. 0xfff7a000 0x00000910
9423 10:02:14.102386 VBOOT WORK 6. 0xfff66000 0x00014000
9424 10:02:14.105841 RAMOOPS 7. 0xffe66000 0x00100000
9425 10:02:14.109135 COREBOOT 8. 0xffe64000 0x00002000
9426 10:02:14.112290 IMD small region:
9427 10:02:14.115767 IMD ROOT 0. 0xffffec00 0x00000400
9428 10:02:14.118641 VPD 1. 0xffffeba0 0x0000004c
9429 10:02:14.121964 MMC STATUS 2. 0xffffeb80 0x00000004
9430 10:02:14.128913 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9431 10:02:14.128997 Probing TPM: done!
9432 10:02:14.135310 Connected to device vid:did:rid of 1ae0:0028:00
9433 10:02:14.142158 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9434 10:02:14.145236 Initialized TPM device CR50 revision 0
9435 10:02:14.148663 Checking cr50 for pending updates
9436 10:02:14.154421 Reading cr50 TPM mode
9437 10:02:14.162733 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9438 10:02:14.169540 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9439 10:02:14.209758 read SPI 0x3990ec 0x4f1b0: 34861 us, 9294 KB/s, 74.352 Mbps
9440 10:02:14.212801 Checking segment from ROM address 0x40100000
9441 10:02:14.216380 Checking segment from ROM address 0x4010001c
9442 10:02:14.222596 Loading segment from ROM address 0x40100000
9443 10:02:14.222681 code (compression=0)
9444 10:02:14.232642 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9445 10:02:14.239718 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9446 10:02:14.239803 it's not compressed!
9447 10:02:14.245969 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9448 10:02:14.252684 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9449 10:02:14.270219 Loading segment from ROM address 0x4010001c
9450 10:02:14.270304 Entry Point 0x80000000
9451 10:02:14.273268 Loaded segments
9452 10:02:14.276398 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9453 10:02:14.283135 Jumping to boot code at 0x80000000(0xffe64000)
9454 10:02:14.290032 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9455 10:02:14.296875 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9456 10:02:14.304763 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9457 10:02:14.307714 Checking segment from ROM address 0x40100000
9458 10:02:14.310873 Checking segment from ROM address 0x4010001c
9459 10:02:14.317843 Loading segment from ROM address 0x40100000
9460 10:02:14.317927 code (compression=1)
9461 10:02:14.324169 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9462 10:02:14.334043 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9463 10:02:14.334128 using LZMA
9464 10:02:14.342891 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9465 10:02:14.349405 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9466 10:02:14.352425 Loading segment from ROM address 0x4010001c
9467 10:02:14.356097 Entry Point 0x54601000
9468 10:02:14.356180 Loaded segments
9469 10:02:14.359213 NOTICE: MT8192 bl31_setup
9470 10:02:14.366150 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9471 10:02:14.369826 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9472 10:02:14.373038 WARNING: region 0:
9473 10:02:14.376209 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 10:02:14.376293 WARNING: region 1:
9475 10:02:14.383060 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9476 10:02:14.386092 WARNING: region 2:
9477 10:02:14.389660 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9478 10:02:14.392794 WARNING: region 3:
9479 10:02:14.396015 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9480 10:02:14.399650 WARNING: region 4:
9481 10:02:14.406064 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9482 10:02:14.406148 WARNING: region 5:
9483 10:02:14.409183 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 10:02:14.412646 WARNING: region 6:
9485 10:02:14.416490 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 10:02:14.419104 WARNING: region 7:
9487 10:02:14.422659 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9488 10:02:14.429132 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9489 10:02:14.432675 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9490 10:02:14.438890 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9491 10:02:14.442474 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9492 10:02:14.445728 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9493 10:02:14.452460 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9494 10:02:14.456012 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9495 10:02:14.459146 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9496 10:02:14.465712 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9497 10:02:14.468754 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9498 10:02:14.475773 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9499 10:02:14.478626 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9500 10:02:14.482279 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9501 10:02:14.489312 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9502 10:02:14.491923 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9503 10:02:14.495557 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9504 10:02:14.501930 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9505 10:02:14.505124 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9506 10:02:14.512107 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9507 10:02:14.515172 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9508 10:02:14.518958 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9509 10:02:14.525329 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9510 10:02:14.528702 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9511 10:02:14.535088 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9512 10:02:14.538586 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9513 10:02:14.541614 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9514 10:02:14.548220 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9515 10:02:14.551486 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9516 10:02:14.558140 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9517 10:02:14.561391 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9518 10:02:14.564985 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9519 10:02:14.571286 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9520 10:02:14.574779 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9521 10:02:14.577790 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9522 10:02:14.584808 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9523 10:02:14.588284 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9524 10:02:14.591381 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9525 10:02:14.594534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9526 10:02:14.601006 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9527 10:02:14.604665 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9528 10:02:14.607952 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9529 10:02:14.611367 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9530 10:02:14.617721 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9531 10:02:14.620837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9532 10:02:14.624157 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9533 10:02:14.627747 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9534 10:02:14.634088 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9535 10:02:14.637620 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9536 10:02:14.640913 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9537 10:02:14.648000 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9538 10:02:14.650649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9539 10:02:14.657531 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9540 10:02:14.660697 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9541 10:02:14.667078 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9542 10:02:14.670529 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9543 10:02:14.673769 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9544 10:02:14.680570 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9545 10:02:14.683723 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9546 10:02:14.690576 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9547 10:02:14.693739 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9548 10:02:14.700593 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9549 10:02:14.703973 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9550 10:02:14.710187 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9551 10:02:14.713939 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9552 10:02:14.717441 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9553 10:02:14.723572 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9554 10:02:14.726979 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9555 10:02:14.733460 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9556 10:02:14.737044 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9557 10:02:14.743943 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9558 10:02:14.747402 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9559 10:02:14.749965 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9560 10:02:14.756674 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9561 10:02:14.760241 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9562 10:02:14.766719 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9563 10:02:14.770263 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9564 10:02:14.776490 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9565 10:02:14.780287 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9566 10:02:14.786780 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9567 10:02:14.789987 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9568 10:02:14.796314 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9569 10:02:14.799898 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9570 10:02:14.803217 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9571 10:02:14.809581 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9572 10:02:14.812824 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9573 10:02:14.819815 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9574 10:02:14.822925 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9575 10:02:14.829420 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9576 10:02:14.833077 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9577 10:02:14.836654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9578 10:02:14.842709 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9579 10:02:14.846286 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9580 10:02:14.852655 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9581 10:02:14.856204 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9582 10:02:14.862515 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9583 10:02:14.865824 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9584 10:02:14.869577 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9585 10:02:14.876050 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9586 10:02:14.879239 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9587 10:02:14.882790 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9588 10:02:14.886256 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9589 10:02:14.892404 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9590 10:02:14.895699 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9591 10:02:14.902436 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9592 10:02:14.905752 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9593 10:02:14.909083 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9594 10:02:14.916282 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9595 10:02:14.919085 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9596 10:02:14.926007 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9597 10:02:14.929183 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9598 10:02:14.932356 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9599 10:02:14.939445 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9600 10:02:14.942244 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9601 10:02:14.949207 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9602 10:02:14.952250 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9603 10:02:14.955706 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9604 10:02:14.962080 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9605 10:02:14.965284 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9606 10:02:14.968697 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9607 10:02:14.975387 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9608 10:02:14.978674 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9609 10:02:14.982041 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9610 10:02:14.985429 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9611 10:02:14.992132 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9612 10:02:14.995210 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9613 10:02:14.998760 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9614 10:02:15.005168 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9615 10:02:15.008285 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9616 10:02:15.015642 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9617 10:02:15.018499 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9618 10:02:15.021656 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9619 10:02:15.028161 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9620 10:02:15.031299 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9621 10:02:15.038169 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9622 10:02:15.041390 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9623 10:02:15.044550 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9624 10:02:15.051380 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9625 10:02:15.054440 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9626 10:02:15.061297 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9627 10:02:15.064817 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9628 10:02:15.067604 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9629 10:02:15.074392 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9630 10:02:15.077806 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9631 10:02:15.084443 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9632 10:02:15.087686 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9633 10:02:15.091281 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9634 10:02:15.097696 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9635 10:02:15.101121 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9636 10:02:15.107912 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9637 10:02:15.111062 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9638 10:02:15.114203 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9639 10:02:15.120683 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9640 10:02:15.124291 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9641 10:02:15.130743 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9642 10:02:15.134365 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9643 10:02:15.137554 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9644 10:02:15.143922 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9645 10:02:15.147747 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9646 10:02:15.150821 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9647 10:02:15.157242 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9648 10:02:15.160772 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9649 10:02:15.167222 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9650 10:02:15.170713 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9651 10:02:15.173719 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9652 10:02:15.180459 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9653 10:02:15.183936 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9654 10:02:15.190478 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9655 10:02:15.193984 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9656 10:02:15.196992 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9657 10:02:15.203864 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9658 10:02:15.207036 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9659 10:02:15.213421 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9660 10:02:15.216624 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9661 10:02:15.219929 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9662 10:02:15.226587 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9663 10:02:15.230228 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9664 10:02:15.236753 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9665 10:02:15.239782 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9666 10:02:15.242946 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9667 10:02:15.249848 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9668 10:02:15.253068 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9669 10:02:15.259363 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9670 10:02:15.263055 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9671 10:02:15.266164 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9672 10:02:15.272598 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9673 10:02:15.275814 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9674 10:02:15.282568 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9675 10:02:15.285971 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9676 10:02:15.292412 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9677 10:02:15.295791 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9678 10:02:15.299237 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9679 10:02:15.305999 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9680 10:02:15.309082 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9681 10:02:15.315855 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9682 10:02:15.319012 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9683 10:02:15.322289 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9684 10:02:15.328748 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9685 10:02:15.331882 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9686 10:02:15.338625 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9687 10:02:15.342134 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9688 10:02:15.348612 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9689 10:02:15.352105 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9690 10:02:15.358499 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9691 10:02:15.361700 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9692 10:02:15.364729 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9693 10:02:15.371605 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9694 10:02:15.374680 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9695 10:02:15.381655 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9696 10:02:15.384609 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9697 10:02:15.387924 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9698 10:02:15.394497 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9699 10:02:15.397795 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9700 10:02:15.404181 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9701 10:02:15.407698 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9702 10:02:15.414301 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9703 10:02:15.417402 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9704 10:02:15.424143 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9705 10:02:15.427216 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9706 10:02:15.430641 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9707 10:02:15.437126 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9708 10:02:15.440831 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9709 10:02:15.447285 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9710 10:02:15.450604 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9711 10:02:15.456935 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9712 10:02:15.460117 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9713 10:02:15.463449 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9714 10:02:15.470305 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9715 10:02:15.473578 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9716 10:02:15.479814 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9717 10:02:15.483073 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9718 10:02:15.486314 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9719 10:02:15.489684 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9720 10:02:15.496402 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9721 10:02:15.499693 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9722 10:02:15.502663 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9723 10:02:15.509541 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9724 10:02:15.512935 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9725 10:02:15.519407 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9726 10:02:15.522325 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9727 10:02:15.526128 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9728 10:02:15.532785 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9729 10:02:15.535849 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9730 10:02:15.539192 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9731 10:02:15.545555 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9732 10:02:15.548827 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9733 10:02:15.552399 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9734 10:02:15.559192 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9735 10:02:15.562403 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9736 10:02:15.568931 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9737 10:02:15.571934 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9738 10:02:15.575659 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9739 10:02:15.581936 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9740 10:02:15.585710 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9741 10:02:15.588739 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9742 10:02:15.595280 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9743 10:02:15.598795 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9744 10:02:15.605482 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9745 10:02:15.608483 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9746 10:02:15.611841 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9747 10:02:15.618124 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9748 10:02:15.621367 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9749 10:02:15.628084 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9750 10:02:15.631261 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9751 10:02:15.634376 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9752 10:02:15.640940 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9753 10:02:15.644329 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9754 10:02:15.647587 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9755 10:02:15.654439 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9756 10:02:15.657705 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9757 10:02:15.661086 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9758 10:02:15.667477 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9759 10:02:15.670712 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9760 10:02:15.673883 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9761 10:02:15.677563 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9762 10:02:15.680667 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9763 10:02:15.687098 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9764 10:02:15.690732 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9765 10:02:15.693920 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9766 10:02:15.700314 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9767 10:02:15.703900 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9768 10:02:15.707092 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9769 10:02:15.710008 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9770 10:02:15.716588 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9771 10:02:15.720393 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9772 10:02:15.726784 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9773 10:02:15.730248 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9774 10:02:15.736515 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9775 10:02:15.740506 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9776 10:02:15.746472 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9777 10:02:15.749564 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9778 10:02:15.752964 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9779 10:02:15.759690 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9780 10:02:15.762744 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9781 10:02:15.769710 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9782 10:02:15.772856 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9783 10:02:15.776052 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9784 10:02:15.782720 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9785 10:02:15.786487 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9786 10:02:15.792724 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9787 10:02:15.795994 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9788 10:02:15.799174 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9789 10:02:15.805780 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9790 10:02:15.809403 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9791 10:02:15.815729 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9792 10:02:15.819103 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9793 10:02:15.822237 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9794 10:02:15.829160 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9795 10:02:15.832084 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9796 10:02:15.838991 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9797 10:02:15.842202 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9798 10:02:15.848849 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9799 10:02:15.852033 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9800 10:02:15.858575 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9801 10:02:15.861837 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9802 10:02:15.865476 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9803 10:02:15.872155 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9804 10:02:15.875056 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9805 10:02:15.881520 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9806 10:02:15.884785 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9807 10:02:15.888324 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9808 10:02:15.894685 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9809 10:02:15.898327 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9810 10:02:15.904864 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9811 10:02:15.908160 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9812 10:02:15.914802 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9813 10:02:15.917853 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9814 10:02:15.920929 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9815 10:02:15.927717 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9816 10:02:15.931317 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9817 10:02:15.938097 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9818 10:02:15.940616 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9819 10:02:15.944444 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9820 10:02:15.950746 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9821 10:02:15.954250 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9822 10:02:15.961002 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9823 10:02:15.964199 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9824 10:02:15.970496 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9825 10:02:15.973691 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9826 10:02:15.976962 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9827 10:02:15.983724 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9828 10:02:15.986930 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9829 10:02:15.993603 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9830 10:02:15.996831 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9831 10:02:16.003777 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9832 10:02:16.006739 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9833 10:02:16.009906 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9834 10:02:16.016977 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9835 10:02:16.019875 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9836 10:02:16.026671 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9837 10:02:16.029934 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9838 10:02:16.033162 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9839 10:02:16.039886 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9840 10:02:16.043147 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9841 10:02:16.049749 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9842 10:02:16.052740 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9843 10:02:16.059653 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9844 10:02:16.062607 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9845 10:02:16.065882 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9846 10:02:16.072950 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9847 10:02:16.076194 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9848 10:02:16.082585 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9849 10:02:16.085674 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9850 10:02:16.092334 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9851 10:02:16.095826 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9852 10:02:16.102342 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9853 10:02:16.105951 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9854 10:02:16.109257 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9855 10:02:16.115441 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9856 10:02:16.118665 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9857 10:02:16.125479 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9858 10:02:16.128584 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9859 10:02:16.135363 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9860 10:02:16.138763 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9861 10:02:16.145233 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9862 10:02:16.148223 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9863 10:02:16.154805 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9864 10:02:16.158487 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9865 10:02:16.161413 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9866 10:02:16.167711 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9867 10:02:16.171138 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9868 10:02:16.178176 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9869 10:02:16.181312 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9870 10:02:16.187541 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9871 10:02:16.191113 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9872 10:02:16.198008 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9873 10:02:16.200812 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9874 10:02:16.204576 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9875 10:02:16.210794 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9876 10:02:16.214138 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9877 10:02:16.221139 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9878 10:02:16.224147 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9879 10:02:16.230538 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9880 10:02:16.234222 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9881 10:02:16.237291 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9882 10:02:16.244126 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9883 10:02:16.247396 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9884 10:02:16.253889 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9885 10:02:16.257492 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9886 10:02:16.263894 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9887 10:02:16.267073 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9888 10:02:16.273443 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9889 10:02:16.277058 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9890 10:02:16.280620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9891 10:02:16.286541 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9892 10:02:16.290284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9893 10:02:16.297021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9894 10:02:16.299766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9895 10:02:16.306540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9896 10:02:16.309708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9897 10:02:16.316425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9898 10:02:16.319678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9899 10:02:16.326067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9900 10:02:16.329684 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9901 10:02:16.336173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9902 10:02:16.339287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9903 10:02:16.346262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9904 10:02:16.349447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9905 10:02:16.356092 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9906 10:02:16.359459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9907 10:02:16.365872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9908 10:02:16.368871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9909 10:02:16.375542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9910 10:02:16.378800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9911 10:02:16.385249 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9912 10:02:16.388789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9913 10:02:16.395556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9914 10:02:16.398763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9915 10:02:16.405697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9916 10:02:16.408593 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9917 10:02:16.415445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9918 10:02:16.418643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9919 10:02:16.425069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9920 10:02:16.428388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9921 10:02:16.434621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9922 10:02:16.438007 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9923 10:02:16.441733 INFO: [APUAPC] vio 0
9924 10:02:16.444772 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9925 10:02:16.451654 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9926 10:02:16.454683 INFO: [APUAPC] D0_APC_0: 0x400510
9927 10:02:16.458114 INFO: [APUAPC] D0_APC_1: 0x0
9928 10:02:16.458242 INFO: [APUAPC] D0_APC_2: 0x1540
9929 10:02:16.461727 INFO: [APUAPC] D0_APC_3: 0x0
9930 10:02:16.464873 INFO: [APUAPC] D1_APC_0: 0xffffffff
9931 10:02:16.467774 INFO: [APUAPC] D1_APC_1: 0xffffffff
9932 10:02:16.471149 INFO: [APUAPC] D1_APC_2: 0x3fffff
9933 10:02:16.474210 INFO: [APUAPC] D1_APC_3: 0x0
9934 10:02:16.478000 INFO: [APUAPC] D2_APC_0: 0xffffffff
9935 10:02:16.481293 INFO: [APUAPC] D2_APC_1: 0xffffffff
9936 10:02:16.484212 INFO: [APUAPC] D2_APC_2: 0x3fffff
9937 10:02:16.487649 INFO: [APUAPC] D2_APC_3: 0x0
9938 10:02:16.490594 INFO: [APUAPC] D3_APC_0: 0xffffffff
9939 10:02:16.494174 INFO: [APUAPC] D3_APC_1: 0xffffffff
9940 10:02:16.497520 INFO: [APUAPC] D3_APC_2: 0x3fffff
9941 10:02:16.500758 INFO: [APUAPC] D3_APC_3: 0x0
9942 10:02:16.504642 INFO: [APUAPC] D4_APC_0: 0xffffffff
9943 10:02:16.507816 INFO: [APUAPC] D4_APC_1: 0xffffffff
9944 10:02:16.510969 INFO: [APUAPC] D4_APC_2: 0x3fffff
9945 10:02:16.513973 INFO: [APUAPC] D4_APC_3: 0x0
9946 10:02:16.517531 INFO: [APUAPC] D5_APC_0: 0xffffffff
9947 10:02:16.520568 INFO: [APUAPC] D5_APC_1: 0xffffffff
9948 10:02:16.523910 INFO: [APUAPC] D5_APC_2: 0x3fffff
9949 10:02:16.527132 INFO: [APUAPC] D5_APC_3: 0x0
9950 10:02:16.531026 INFO: [APUAPC] D6_APC_0: 0xffffffff
9951 10:02:16.534161 INFO: [APUAPC] D6_APC_1: 0xffffffff
9952 10:02:16.537694 INFO: [APUAPC] D6_APC_2: 0x3fffff
9953 10:02:16.540801 INFO: [APUAPC] D6_APC_3: 0x0
9954 10:02:16.543953 INFO: [APUAPC] D7_APC_0: 0xffffffff
9955 10:02:16.547378 INFO: [APUAPC] D7_APC_1: 0xffffffff
9956 10:02:16.550743 INFO: [APUAPC] D7_APC_2: 0x3fffff
9957 10:02:16.553867 INFO: [APUAPC] D7_APC_3: 0x0
9958 10:02:16.557448 INFO: [APUAPC] D8_APC_0: 0xffffffff
9959 10:02:16.560598 INFO: [APUAPC] D8_APC_1: 0xffffffff
9960 10:02:16.563814 INFO: [APUAPC] D8_APC_2: 0x3fffff
9961 10:02:16.567001 INFO: [APUAPC] D8_APC_3: 0x0
9962 10:02:16.570945 INFO: [APUAPC] D9_APC_0: 0xffffffff
9963 10:02:16.574261 INFO: [APUAPC] D9_APC_1: 0xffffffff
9964 10:02:16.577476 INFO: [APUAPC] D9_APC_2: 0x3fffff
9965 10:02:16.580640 INFO: [APUAPC] D9_APC_3: 0x0
9966 10:02:16.583855 INFO: [APUAPC] D10_APC_0: 0xffffffff
9967 10:02:16.587232 INFO: [APUAPC] D10_APC_1: 0xffffffff
9968 10:02:16.590274 INFO: [APUAPC] D10_APC_2: 0x3fffff
9969 10:02:16.593753 INFO: [APUAPC] D10_APC_3: 0x0
9970 10:02:16.597214 INFO: [APUAPC] D11_APC_0: 0xffffffff
9971 10:02:16.600637 INFO: [APUAPC] D11_APC_1: 0xffffffff
9972 10:02:16.603922 INFO: [APUAPC] D11_APC_2: 0x3fffff
9973 10:02:16.606932 INFO: [APUAPC] D11_APC_3: 0x0
9974 10:02:16.610443 INFO: [APUAPC] D12_APC_0: 0xffffffff
9975 10:02:16.613412 INFO: [APUAPC] D12_APC_1: 0xffffffff
9976 10:02:16.616665 INFO: [APUAPC] D12_APC_2: 0x3fffff
9977 10:02:16.620172 INFO: [APUAPC] D12_APC_3: 0x0
9978 10:02:16.623386 INFO: [APUAPC] D13_APC_0: 0xffffffff
9979 10:02:16.626534 INFO: [APUAPC] D13_APC_1: 0xffffffff
9980 10:02:16.629985 INFO: [APUAPC] D13_APC_2: 0x3fffff
9981 10:02:16.633591 INFO: [APUAPC] D13_APC_3: 0x0
9982 10:02:16.636699 INFO: [APUAPC] D14_APC_0: 0xffffffff
9983 10:02:16.639950 INFO: [APUAPC] D14_APC_1: 0xffffffff
9984 10:02:16.643288 INFO: [APUAPC] D14_APC_2: 0x3fffff
9985 10:02:16.646442 INFO: [APUAPC] D14_APC_3: 0x0
9986 10:02:16.649854 INFO: [APUAPC] D15_APC_0: 0xffffffff
9987 10:02:16.652781 INFO: [APUAPC] D15_APC_1: 0xffffffff
9988 10:02:16.656886 INFO: [APUAPC] D15_APC_2: 0x3fffff
9989 10:02:16.659411 INFO: [APUAPC] D15_APC_3: 0x0
9990 10:02:16.662664 INFO: [APUAPC] APC_CON: 0x4
9991 10:02:16.666083 INFO: [NOCDAPC] D0_APC_0: 0x0
9992 10:02:16.669147 INFO: [NOCDAPC] D0_APC_1: 0x0
9993 10:02:16.672890 INFO: [NOCDAPC] D1_APC_0: 0x0
9994 10:02:16.675935 INFO: [NOCDAPC] D1_APC_1: 0xfff
9995 10:02:16.679402 INFO: [NOCDAPC] D2_APC_0: 0x0
9996 10:02:16.680027 INFO: [NOCDAPC] D2_APC_1: 0xfff
9997 10:02:16.682791 INFO: [NOCDAPC] D3_APC_0: 0x0
9998 10:02:16.685535 INFO: [NOCDAPC] D3_APC_1: 0xfff
9999 10:02:16.689028 INFO: [NOCDAPC] D4_APC_0: 0x0
10000 10:02:16.692738 INFO: [NOCDAPC] D4_APC_1: 0xfff
10001 10:02:16.695935 INFO: [NOCDAPC] D5_APC_0: 0x0
10002 10:02:16.699391 INFO: [NOCDAPC] D5_APC_1: 0xfff
10003 10:02:16.702436 INFO: [NOCDAPC] D6_APC_0: 0x0
10004 10:02:16.705309 INFO: [NOCDAPC] D6_APC_1: 0xfff
10005 10:02:16.709210 INFO: [NOCDAPC] D7_APC_0: 0x0
10006 10:02:16.712409 INFO: [NOCDAPC] D7_APC_1: 0xfff
10007 10:02:16.712896 INFO: [NOCDAPC] D8_APC_0: 0x0
10008 10:02:16.715661 INFO: [NOCDAPC] D8_APC_1: 0xfff
10009 10:02:16.718943 INFO: [NOCDAPC] D9_APC_0: 0x0
10010 10:02:16.722561 INFO: [NOCDAPC] D9_APC_1: 0xfff
10011 10:02:16.725709 INFO: [NOCDAPC] D10_APC_0: 0x0
10012 10:02:16.728661 INFO: [NOCDAPC] D10_APC_1: 0xfff
10013 10:02:16.732414 INFO: [NOCDAPC] D11_APC_0: 0x0
10014 10:02:16.735505 INFO: [NOCDAPC] D11_APC_1: 0xfff
10015 10:02:16.738529 INFO: [NOCDAPC] D12_APC_0: 0x0
10016 10:02:16.741795 INFO: [NOCDAPC] D12_APC_1: 0xfff
10017 10:02:16.745180 INFO: [NOCDAPC] D13_APC_0: 0x0
10018 10:02:16.748646 INFO: [NOCDAPC] D13_APC_1: 0xfff
10019 10:02:16.751769 INFO: [NOCDAPC] D14_APC_0: 0x0
10020 10:02:16.755461 INFO: [NOCDAPC] D14_APC_1: 0xfff
10021 10:02:16.758178 INFO: [NOCDAPC] D15_APC_0: 0x0
10022 10:02:16.761345 INFO: [NOCDAPC] D15_APC_1: 0xfff
10023 10:02:16.761857 INFO: [NOCDAPC] APC_CON: 0x4
10024 10:02:16.765396 INFO: [APUAPC] set_apusys_apc done
10025 10:02:16.768396 INFO: [DEVAPC] devapc_init done
10026 10:02:16.774858 INFO: GICv3 without legacy support detected.
10027 10:02:16.778553 INFO: ARM GICv3 driver initialized in EL3
10028 10:02:16.781579 INFO: Maximum SPI INTID supported: 639
10029 10:02:16.784836 INFO: BL31: Initializing runtime services
10030 10:02:16.791414 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10031 10:02:16.794750 INFO: SPM: enable CPC mode
10032 10:02:16.798338 INFO: mcdi ready for mcusys-off-idle and system suspend
10033 10:02:16.804892 INFO: BL31: Preparing for EL3 exit to normal world
10034 10:02:16.807498 INFO: Entry point address = 0x80000000
10035 10:02:16.808128 INFO: SPSR = 0x8
10036 10:02:16.815290
10037 10:02:16.815877
10038 10:02:16.816283
10039 10:02:16.818333 Starting depthcharge on Spherion...
10040 10:02:16.818809
10041 10:02:16.819228 Wipe memory regions:
10042 10:02:16.819584
10043 10:02:16.821965 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10044 10:02:16.822506 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10045 10:02:16.822998 Setting prompt string to ['asurada:']
10046 10:02:16.823446 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10047 10:02:16.824209 [0x00000040000000, 0x00000054600000)
10048 10:02:16.944330
10049 10:02:16.944918 [0x00000054660000, 0x00000080000000)
10050 10:02:17.204965
10051 10:02:17.205548 [0x000000821a7280, 0x000000ffe64000)
10052 10:02:17.949256
10053 10:02:17.949784 [0x00000100000000, 0x00000240000000)
10054 10:02:19.839841
10055 10:02:19.842777 Initializing XHCI USB controller at 0x11200000.
10056 10:02:20.882248
10057 10:02:20.885538 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10058 10:02:20.886121
10059 10:02:20.886503
10060 10:02:20.886888
10061 10:02:20.887713 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 10:02:20.989081 asurada: tftpboot 192.168.201.1 10670675/tftp-deploy-2_f07u3u/kernel/image.itb 10670675/tftp-deploy-2_f07u3u/kernel/cmdline
10064 10:02:20.989916 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10065 10:02:20.990427 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10066 10:02:20.995207 tftpboot 192.168.201.1 10670675/tftp-deploy-2_f07u3u/kernel/image.itp-deploy-2_f07u3u/kernel/cmdline
10067 10:02:20.995694
10068 10:02:20.996069 Waiting for link
10069 10:02:21.153408
10070 10:02:21.153991 R8152: Initializing
10071 10:02:21.154378
10072 10:02:21.156869 Version 6 (ocp_data = 5c30)
10073 10:02:21.157455
10074 10:02:21.159998 R8152: Done initializing
10075 10:02:21.160580
10076 10:02:21.160965 Adding net device
10077 10:02:23.061779
10078 10:02:23.062354 done.
10079 10:02:23.062732
10080 10:02:23.063142 MAC: 00:24:32:30:78:ff
10081 10:02:23.063486
10082 10:02:23.065276 Sending DHCP discover... done.
10083 10:02:23.065885
10084 10:02:27.245018 Waiting for reply... done.
10085 10:02:27.245594
10086 10:02:27.245973 Sending DHCP request... done.
10087 10:02:27.248226
10088 10:02:27.248692 Waiting for reply... done.
10089 10:02:27.249062
10090 10:02:27.251137 My ip is 192.168.201.21
10091 10:02:27.251604
10092 10:02:27.254469 The DHCP server ip is 192.168.201.1
10093 10:02:27.254966
10094 10:02:27.258224 TFTP server IP predefined by user: 192.168.201.1
10095 10:02:27.258790
10096 10:02:27.264819 Bootfile predefined by user: 10670675/tftp-deploy-2_f07u3u/kernel/image.itb
10097 10:02:27.265578
10098 10:02:27.268230 Sending tftp read request... done.
10099 10:02:27.268695
10100 10:02:27.275870 Waiting for the transfer...
10101 10:02:27.276355
10102 10:02:27.981228 00000000 ################################################################
10103 10:02:27.981840
10104 10:02:28.704162 00080000 ################################################################
10105 10:02:28.704725
10106 10:02:29.421345 00100000 ################################################################
10107 10:02:29.422012
10108 10:02:30.151787 00180000 ################################################################
10109 10:02:30.152418
10110 10:02:30.872682 00200000 ################################################################
10111 10:02:30.873267
10112 10:02:31.595455 00280000 ################################################################
10113 10:02:31.595988
10114 10:02:32.319947 00300000 ################################################################
10115 10:02:32.320545
10116 10:02:33.031194 00380000 ################################################################
10117 10:02:33.031755
10118 10:02:33.748635 00400000 ################################################################
10119 10:02:33.749233
10120 10:02:34.479219 00480000 ################################################################
10121 10:02:34.479785
10122 10:02:35.132668 00500000 ################################################################
10123 10:02:35.133189
10124 10:02:35.843491 00580000 ################################################################
10125 10:02:35.844091
10126 10:02:36.573714 00600000 ################################################################
10127 10:02:36.574356
10128 10:02:37.252901 00680000 ################################################################
10129 10:02:37.253459
10130 10:02:37.951606 00700000 ################################################################
10131 10:02:37.952290
10132 10:02:38.622501 00780000 ################################################################
10133 10:02:38.623118
10134 10:02:39.305806 00800000 ################################################################
10135 10:02:39.305959
10136 10:02:39.983913 00880000 ################################################################
10137 10:02:39.984417
10138 10:02:40.631212 00900000 ################################################################
10139 10:02:40.631732
10140 10:02:41.219791 00980000 ################################################################
10141 10:02:41.219945
10142 10:02:41.743296 00a00000 ################################################################
10143 10:02:41.743454
10144 10:02:42.317060 00a80000 ################################################################
10145 10:02:42.317210
10146 10:02:42.943040 00b00000 ################################################################
10147 10:02:42.943180
10148 10:02:43.491957 00b80000 ################################################################
10149 10:02:43.492103
10150 10:02:44.093811 00c00000 ################################################################
10151 10:02:44.093975
10152 10:02:44.716128 00c80000 ################################################################
10153 10:02:44.716777
10154 10:02:45.381386 00d00000 ################################################################
10155 10:02:45.381526
10156 10:02:46.060744 00d80000 ################################################################
10157 10:02:46.061323
10158 10:02:46.626980 00e00000 ################################################################
10159 10:02:46.627115
10160 10:02:47.179973 00e80000 ################################################################
10161 10:02:47.180575
10162 10:02:47.741558 00f00000 ################################################################
10163 10:02:47.741698
10164 10:02:48.277667 00f80000 ################################################################
10165 10:02:48.277824
10166 10:02:48.876565 01000000 ################################################################
10167 10:02:48.877206
10168 10:02:49.570976 01080000 ################################################################
10169 10:02:49.571523
10170 10:02:50.212068 01100000 ################################################################
10171 10:02:50.212220
10172 10:02:50.824527 01180000 ################################################################
10173 10:02:50.824691
10174 10:02:51.386888 01200000 ################################################################
10175 10:02:51.387442
10176 10:02:52.086233 01280000 ################################################################
10177 10:02:52.086819
10178 10:02:52.769754 01300000 ################################################################
10179 10:02:52.769923
10180 10:02:53.486859 01380000 ################################################################
10181 10:02:53.487458
10182 10:02:54.215809 01400000 ################################################################
10183 10:02:54.216462
10184 10:02:54.943395 01480000 ################################################################
10185 10:02:54.943971
10186 10:02:55.657889 01500000 ################################################################
10187 10:02:55.658542
10188 10:02:56.394455 01580000 ################################################################
10189 10:02:56.395025
10190 10:02:57.099423 01600000 ################################################################
10191 10:02:57.100092
10192 10:02:57.800952 01680000 ################################################################
10193 10:02:57.801499
10194 10:02:58.505533 01700000 ################################################################
10195 10:02:58.506385
10196 10:02:59.206051 01780000 ################################################################
10197 10:02:59.206657
10198 10:02:59.930705 01800000 ################################################################
10199 10:02:59.931363
10200 10:03:00.650350 01880000 ################################################################
10201 10:03:00.651040
10202 10:03:01.387473 01900000 ################################################################
10203 10:03:01.388064
10204 10:03:02.119818 01980000 ################################################################
10205 10:03:02.120436
10206 10:03:02.850991 01a00000 ################################################################
10207 10:03:02.851584
10208 10:03:03.581919 01a80000 ################################################################
10209 10:03:03.582665
10210 10:03:04.318563 01b00000 ################################################################
10211 10:03:04.319130
10212 10:03:05.046676 01b80000 ################################################################
10213 10:03:05.047301
10214 10:03:05.784760 01c00000 ################################################################
10215 10:03:05.785353
10216 10:03:06.528761 01c80000 ################################################################
10217 10:03:06.529353
10218 10:03:07.274161 01d00000 ################################################################
10219 10:03:07.274751
10220 10:03:08.005756 01d80000 ################################################################
10221 10:03:08.006344
10222 10:03:08.741709 01e00000 ################################################################
10223 10:03:08.742315
10224 10:03:09.464699 01e80000 ################################################################
10225 10:03:09.465291
10226 10:03:10.196707 01f00000 ################################################################
10227 10:03:10.197300
10228 10:03:10.910352 01f80000 ################################################################
10229 10:03:10.911128
10230 10:03:11.658383 02000000 ################################################################
10231 10:03:11.658965
10232 10:03:12.376066 02080000 ################################################################
10233 10:03:12.376644
10234 10:03:13.106287 02100000 ################################################################
10235 10:03:13.106877
10236 10:03:13.829949 02180000 ################################################################
10237 10:03:13.830545
10238 10:03:14.559583 02200000 ################################################################
10239 10:03:14.560199
10240 10:03:15.271305 02280000 ################################################################
10241 10:03:15.271458
10242 10:03:15.917803 02300000 ################################################################
10243 10:03:15.918410
10244 10:03:16.626277 02380000 ################################################################
10245 10:03:16.626420
10246 10:03:17.184136 02400000 ################################################################
10247 10:03:17.184280
10248 10:03:17.751906 02480000 ################################################################
10249 10:03:17.752085
10250 10:03:18.322641 02500000 ################################################################
10251 10:03:18.322802
10252 10:03:18.892354 02580000 ################################################################
10253 10:03:18.892508
10254 10:03:19.468839 02600000 ################################################################
10255 10:03:19.469037
10256 10:03:20.041840 02680000 ################################################################
10257 10:03:20.042035
10258 10:03:20.620138 02700000 ################################################################
10259 10:03:20.620331
10260 10:03:21.200590 02780000 ################################################################
10261 10:03:21.200783
10262 10:03:21.768158 02800000 ################################################################
10263 10:03:21.768356
10264 10:03:22.329564 02880000 ################################################################
10265 10:03:22.329763
10266 10:03:22.904923 02900000 ################################################################
10267 10:03:22.905114
10268 10:03:23.489265 02980000 ################################################################
10269 10:03:23.489447
10270 10:03:24.067211 02a00000 ################################################################
10271 10:03:24.067363
10272 10:03:24.636138 02a80000 ################################################################
10273 10:03:24.636290
10274 10:03:25.215070 02b00000 ################################################################
10275 10:03:25.215211
10276 10:03:25.795203 02b80000 ################################################################
10277 10:03:25.795364
10278 10:03:26.369227 02c00000 ################################################################
10279 10:03:26.369379
10280 10:03:26.898528 02c80000 ################################################################
10281 10:03:26.898679
10282 10:03:27.448326 02d00000 ################################################################
10283 10:03:27.448499
10284 10:03:28.027396 02d80000 ################################################################
10285 10:03:28.027556
10286 10:03:28.569425 02e00000 ################################################################
10287 10:03:28.569578
10288 10:03:29.124382 02e80000 ################################################################
10289 10:03:29.124534
10290 10:03:29.696728 02f00000 ################################################################
10291 10:03:29.696883
10292 10:03:30.257571 02f80000 ################################################################
10293 10:03:30.257725
10294 10:03:30.815545 03000000 ################################################################
10295 10:03:30.815723
10296 10:03:31.362746 03080000 ################################################################
10297 10:03:31.362934
10298 10:03:31.907655 03100000 ################################################################
10299 10:03:31.907813
10300 10:03:32.462350 03180000 ################################################################
10301 10:03:32.462500
10302 10:03:33.031991 03200000 ################################################################
10303 10:03:33.032152
10304 10:03:33.612525 03280000 ################################################################
10305 10:03:33.612681
10306 10:03:34.188704 03300000 ################################################################
10307 10:03:34.188865
10308 10:03:34.776530 03380000 ################################################################
10309 10:03:34.776688
10310 10:03:35.350559 03400000 ################################################################
10311 10:03:35.350723
10312 10:03:35.951686 03480000 ################################################################
10313 10:03:35.951848
10314 10:03:36.516379 03500000 ################################################################
10315 10:03:36.516535
10316 10:03:37.071148 03580000 ################################################################
10317 10:03:37.071304
10318 10:03:37.629827 03600000 ################################################################
10319 10:03:37.629989
10320 10:03:38.219083 03680000 ################################################################
10321 10:03:38.219246
10322 10:03:38.813722 03700000 ################################################################
10323 10:03:38.813884
10324 10:03:39.415489 03780000 ################################################################
10325 10:03:39.415638
10326 10:03:40.003273 03800000 ################################################################
10327 10:03:40.003434
10328 10:03:40.597211 03880000 ################################################################
10329 10:03:40.597372
10330 10:03:41.183169 03900000 ################################################################
10331 10:03:41.183329
10332 10:03:41.771598 03980000 ################################################################
10333 10:03:41.771749
10334 10:03:42.370128 03a00000 ################################################################
10335 10:03:42.370291
10336 10:03:42.958454 03a80000 ################################################################
10337 10:03:42.958613
10338 10:03:43.562545 03b00000 ################################################################
10339 10:03:43.562716
10340 10:03:44.155018 03b80000 ################################################################
10341 10:03:44.155177
10342 10:03:44.739809 03c00000 ################################################################
10343 10:03:44.739973
10344 10:03:45.324481 03c80000 ################################################################
10345 10:03:45.324703
10346 10:03:45.924390 03d00000 ################################################################
10347 10:03:45.924554
10348 10:03:46.524192 03d80000 ################################################################
10349 10:03:46.524354
10350 10:03:47.124955 03e00000 ################################################################
10351 10:03:47.125115
10352 10:03:47.727530 03e80000 ################################################################
10353 10:03:47.727698
10354 10:03:48.331128 03f00000 ################################################################
10355 10:03:48.331290
10356 10:03:48.875986 03f80000 ################################################################
10357 10:03:48.876144
10358 10:03:49.475184 04000000 ################################################################
10359 10:03:49.475339
10360 10:03:50.084820 04080000 ################################################################
10361 10:03:50.084976
10362 10:03:50.675971 04100000 ################################################################
10363 10:03:50.676130
10364 10:03:51.247848 04180000 ################################################################
10365 10:03:51.247998
10366 10:03:51.824230 04200000 ################################################################
10367 10:03:51.824372
10368 10:03:52.372355 04280000 ################################################################
10369 10:03:52.372498
10370 10:03:52.919341 04300000 ################################################################
10371 10:03:52.919497
10372 10:03:53.520366 04380000 ################################################################
10373 10:03:53.520519
10374 10:03:54.118174 04400000 ################################################################
10375 10:03:54.118425
10376 10:03:54.663905 04480000 ################################################################
10377 10:03:54.664050
10378 10:03:55.244301 04500000 ################################################################
10379 10:03:55.244450
10380 10:03:55.826397 04580000 ################################################################
10381 10:03:55.826547
10382 10:03:56.402156 04600000 ################################################################
10383 10:03:56.402301
10384 10:03:56.979138 04680000 ################################################################
10385 10:03:56.979284
10386 10:03:57.559058 04700000 ################################################################
10387 10:03:57.559197
10388 10:03:58.145727 04780000 ################################################################
10389 10:03:58.145871
10390 10:03:58.731859 04800000 ################################################################
10391 10:03:58.732007
10392 10:03:59.309660 04880000 ################################################################
10393 10:03:59.309811
10394 10:03:59.838571 04900000 ################################################################
10395 10:03:59.838729
10396 10:04:00.382619 04980000 ################################################################
10397 10:04:00.382765
10398 10:04:00.927511 04a00000 ################################################################
10399 10:04:00.927675
10400 10:04:01.481466 04a80000 ################################################################
10401 10:04:01.481612
10402 10:04:02.031214 04b00000 ################################################################
10403 10:04:02.031356
10404 10:04:02.587980 04b80000 ################################################################
10405 10:04:02.588119
10406 10:04:03.166648 04c00000 ################################################################
10407 10:04:03.166787
10408 10:04:03.747324 04c80000 ################################################################
10409 10:04:03.747465
10410 10:04:04.332640 04d00000 ################################################################
10411 10:04:04.332789
10412 10:04:04.905770 04d80000 ################################################################
10413 10:04:04.905946
10414 10:04:05.462396 04e00000 ################################################################
10415 10:04:05.462540
10416 10:04:06.033677 04e80000 ################################################################
10417 10:04:06.033827
10418 10:04:06.615256 04f00000 ################################################################
10419 10:04:06.615406
10420 10:04:07.197128 04f80000 ################################################################
10421 10:04:07.197273
10422 10:04:07.756364 05000000 ################################################################
10423 10:04:07.756501
10424 10:04:08.324763 05080000 ################################################################
10425 10:04:08.324898
10426 10:04:08.853477 05100000 ################################################################
10427 10:04:08.853616
10428 10:04:09.375525 05180000 ################################################################
10429 10:04:09.375679
10430 10:04:09.906901 05200000 ################################################################
10431 10:04:09.907064
10432 10:04:10.437824 05280000 ################################################################
10433 10:04:10.437978
10434 10:04:10.985667 05300000 ################################################################
10435 10:04:10.985822
10436 10:04:11.524601 05380000 ################################################################
10437 10:04:11.524740
10438 10:04:12.048927 05400000 ################################################################
10439 10:04:12.049065
10440 10:04:12.607758 05480000 ################################################################
10441 10:04:12.607914
10442 10:04:13.156840 05500000 ################################################################
10443 10:04:13.157018
10444 10:04:13.701039 05580000 ################################################################
10445 10:04:13.701189
10446 10:04:14.244134 05600000 ################################################################
10447 10:04:14.244283
10448 10:04:14.788194 05680000 ################################################################
10449 10:04:14.788333
10450 10:04:15.340399 05700000 ################################################################
10451 10:04:15.340588
10452 10:04:15.871355 05780000 ################################################################
10453 10:04:15.871535
10454 10:04:16.407140 05800000 ################################################################
10455 10:04:16.407315
10456 10:04:16.940025 05880000 ################################################################
10457 10:04:16.940232
10458 10:04:17.479027 05900000 ################################################################
10459 10:04:17.479165
10460 10:04:18.031034 05980000 ################################################################
10461 10:04:18.031181
10462 10:04:18.574084 05a00000 ################################################################
10463 10:04:18.574265
10464 10:04:19.113584 05a80000 ################################################################
10465 10:04:19.113756
10466 10:04:19.638604 05b00000 ################################################################
10467 10:04:19.638754
10468 10:04:20.165687 05b80000 ################################################################
10469 10:04:20.165872
10470 10:04:20.701060 05c00000 ################################################################
10471 10:04:20.701212
10472 10:04:21.218508 05c80000 ################################################################
10473 10:04:21.218656
10474 10:04:21.738472 05d00000 ################################################################
10475 10:04:21.738654
10476 10:04:22.277551 05d80000 ################################################################
10477 10:04:22.277699
10478 10:04:22.852906 05e00000 ################################################################
10479 10:04:22.853042
10480 10:04:23.441110 05e80000 ################################################################
10481 10:04:23.441275
10482 10:04:24.019698 05f00000 ################################################################
10483 10:04:24.019833
10484 10:04:24.547375 05f80000 ################################################################
10485 10:04:24.547564
10486 10:04:25.073275 06000000 ################################################################
10487 10:04:25.073451
10488 10:04:25.624560 06080000 ################################################################
10489 10:04:25.624699
10490 10:04:26.171084 06100000 ################################################################
10491 10:04:26.171245
10492 10:04:26.736317 06180000 ################################################################
10493 10:04:26.736456
10494 10:04:27.280169 06200000 ################################################################
10495 10:04:27.280336
10496 10:04:27.847522 06280000 ################################################################
10497 10:04:27.847709
10498 10:04:28.413872 06300000 ################################################################
10499 10:04:28.414007
10500 10:04:28.996345 06380000 ################################################################
10501 10:04:28.996518
10502 10:04:29.580863 06400000 ################################################################
10503 10:04:29.581030
10504 10:04:30.167066 06480000 ################################################################
10505 10:04:30.167207
10506 10:04:30.754925 06500000 ################################################################
10507 10:04:30.755074
10508 10:04:31.329783 06580000 ################################################################
10509 10:04:31.329960
10510 10:04:31.907628 06600000 ################################################################
10511 10:04:31.907782
10512 10:04:32.490103 06680000 ################################################################
10513 10:04:32.490278
10514 10:04:32.776345 06700000 ################################ done.
10515 10:04:32.776487
10516 10:04:32.779894 The bootfile was 108260742 bytes long.
10517 10:04:32.779979
10518 10:04:32.783057 Sending tftp read request... done.
10519 10:04:32.783137
10520 10:04:32.783201 Waiting for the transfer...
10521 10:04:32.786312
10522 10:04:32.786397 00000000 # done.
10523 10:04:32.786466
10524 10:04:32.792772 Command line loaded dynamically from TFTP file: 10670675/tftp-deploy-2_f07u3u/kernel/cmdline
10525 10:04:32.792871
10526 10:04:32.806344 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10527 10:04:32.806462
10528 10:04:32.806554 Loading FIT.
10529 10:04:32.806640
10530 10:04:32.809285 Image ramdisk-1 has 98124468 bytes.
10531 10:04:32.809430
10532 10:04:32.812684 Image fdt-1 has 46924 bytes.
10533 10:04:32.812823
10534 10:04:32.816163 Image kernel-1 has 10087317 bytes.
10535 10:04:32.816303
10536 10:04:32.825986 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10537 10:04:32.826166
10538 10:04:32.842375 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10539 10:04:32.842795
10540 10:04:32.845728 Choosing best match conf-1 for compat google,spherion-rev2.
10541 10:04:32.849586
10542 10:04:32.852752 Connected to device vid:did:rid of 1ae0:0028:00
10543 10:04:32.863344
10544 10:04:32.866290 tpm_get_response: command 0x17b, return code 0x0
10545 10:04:32.866932
10546 10:04:32.869647 ec_init: CrosEC protocol v3 supported (256, 248)
10547 10:04:32.873558
10548 10:04:32.876840 tpm_cleanup: add release locality here.
10549 10:04:32.877392
10550 10:04:32.877819 Shutting down all USB controllers.
10551 10:04:32.880400
10552 10:04:32.880816 Removing current net device
10553 10:04:32.881178
10554 10:04:32.886988 Exiting depthcharge with code 4 at timestamp: 165375752
10555 10:04:32.887536
10556 10:04:32.890157 LZMA decompressing kernel-1 to 0x821a6718
10557 10:04:32.890670
10558 10:04:32.893425 LZMA decompressing kernel-1 to 0x40000000
10559 10:04:34.161341
10560 10:04:34.161492 jumping to kernel
10561 10:04:34.161974 end: 2.2.4 bootloader-commands (duration 00:02:17) [common]
10562 10:04:34.162078 start: 2.2.5 auto-login-action (timeout 00:02:08) [common]
10563 10:04:34.162163 Setting prompt string to ['Linux version [0-9]']
10564 10:04:34.162235 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10565 10:04:34.162321 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10566 10:04:34.243101
10567 10:04:34.246484 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10568 10:04:34.249771 start: 2.2.5.1 login-action (timeout 00:02:08) [common]
10569 10:04:34.249863 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10570 10:04:34.249953 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10571 10:04:34.250037 Using line separator: #'\n'#
10572 10:04:34.250101 No login prompt set.
10573 10:04:34.250166 Parsing kernel messages
10574 10:04:34.250224 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10575 10:04:34.250329 [login-action] Waiting for messages, (timeout 00:02:08)
10576 10:04:34.269601 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j19381-arm64-gcc-10-defconfig-arm64-chromebook-d6qsg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023
10577 10:04:34.272574 [ 0.000000] random: crng init done
10578 10:04:34.278987 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10579 10:04:34.279072 [ 0.000000] efi: UEFI not found.
10580 10:04:34.289039 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10581 10:04:34.295877 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10582 10:04:34.305823 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10583 10:04:34.315659 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10584 10:04:34.322084 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10585 10:04:34.328873 [ 0.000000] printk: bootconsole [mtk8250] enabled
10586 10:04:34.335333 [ 0.000000] NUMA: No NUMA configuration found
10587 10:04:34.341744 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10588 10:04:34.344927 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10589 10:04:34.348645 [ 0.000000] Zone ranges:
10590 10:04:34.355088 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10591 10:04:34.358416 [ 0.000000] DMA32 empty
10592 10:04:34.364686 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10593 10:04:34.368057 [ 0.000000] Movable zone start for each node
10594 10:04:34.371016 [ 0.000000] Early memory node ranges
10595 10:04:34.377635 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10596 10:04:34.384547 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10597 10:04:34.391349 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10598 10:04:34.397777 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10599 10:04:34.404175 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10600 10:04:34.411179 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10601 10:04:34.467102 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10602 10:04:34.473504 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10603 10:04:34.480078 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10604 10:04:34.483602 [ 0.000000] psci: probing for conduit method from DT.
10605 10:04:34.489904 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10606 10:04:34.493125 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10607 10:04:34.500230 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10608 10:04:34.502909 [ 0.000000] psci: SMC Calling Convention v1.2
10609 10:04:34.509846 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10610 10:04:34.512904 [ 0.000000] Detected VIPT I-cache on CPU0
10611 10:04:34.519601 [ 0.000000] CPU features: detected: GIC system register CPU interface
10612 10:04:34.526638 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10613 10:04:34.532626 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10614 10:04:34.539218 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10615 10:04:34.549187 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10616 10:04:34.555654 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10617 10:04:34.558775 [ 0.000000] alternatives: applying boot alternatives
10618 10:04:34.565842 [ 0.000000] Fallback order for Node 0: 0
10619 10:04:34.572525 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10620 10:04:34.575524 [ 0.000000] Policy zone: Normal
10621 10:04:34.585461 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10622 10:04:34.598788 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10623 10:04:34.608761 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10624 10:04:34.619064 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10625 10:04:34.625250 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10626 10:04:34.628278 <6>[ 0.000000] software IO TLB: area num 8.
10627 10:04:34.685329 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10628 10:04:34.834562 <6>[ 0.000000] Memory: 7877116K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 475652K reserved, 32768K cma-reserved)
10629 10:04:34.841253 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10630 10:04:34.847751 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10631 10:04:34.851596 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10632 10:04:34.857821 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10633 10:04:34.864383 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10634 10:04:34.867604 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10635 10:04:34.877431 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10636 10:04:34.884036 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10637 10:04:34.890938 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10638 10:04:34.897387 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10639 10:04:34.900822 <6>[ 0.000000] GICv3: 608 SPIs implemented
10640 10:04:34.903945 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10641 10:04:34.910550 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10642 10:04:34.914013 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10643 10:04:34.920862 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10644 10:04:34.933718 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10645 10:04:34.946942 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10646 10:04:34.953531 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10647 10:04:34.961437 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10648 10:04:34.974510 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10649 10:04:34.980992 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10650 10:04:34.987907 <6>[ 0.009175] Console: colour dummy device 80x25
10651 10:04:34.997516 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10652 10:04:35.004370 <6>[ 0.024343] pid_max: default: 32768 minimum: 301
10653 10:04:35.007241 <6>[ 0.029248] LSM: Security Framework initializing
10654 10:04:35.013472 <6>[ 0.034216] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10655 10:04:35.023600 <6>[ 0.042029] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10656 10:04:35.033845 <6>[ 0.051461] cblist_init_generic: Setting adjustable number of callback queues.
10657 10:04:35.040241 <6>[ 0.058914] cblist_init_generic: Setting shift to 3 and lim to 1.
10658 10:04:35.043292 <6>[ 0.065292] cblist_init_generic: Setting shift to 3 and lim to 1.
10659 10:04:35.049634 <6>[ 0.071699] rcu: Hierarchical SRCU implementation.
10660 10:04:35.056533 <6>[ 0.076713] rcu: Max phase no-delay instances is 1000.
10661 10:04:35.063281 <6>[ 0.083734] EFI services will not be available.
10662 10:04:35.066078 <6>[ 0.088705] smp: Bringing up secondary CPUs ...
10663 10:04:35.074389 <6>[ 0.093787] Detected VIPT I-cache on CPU1
10664 10:04:35.080772 <6>[ 0.093858] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10665 10:04:35.087603 <6>[ 0.093888] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10666 10:04:35.090816 <6>[ 0.094219] Detected VIPT I-cache on CPU2
10667 10:04:35.100602 <6>[ 0.094267] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10668 10:04:35.107089 <6>[ 0.094282] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10669 10:04:35.110544 <6>[ 0.094538] Detected VIPT I-cache on CPU3
10670 10:04:35.117051 <6>[ 0.094584] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10671 10:04:35.123512 <6>[ 0.094597] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10672 10:04:35.129847 <6>[ 0.094901] CPU features: detected: Spectre-v4
10673 10:04:35.133325 <6>[ 0.094907] CPU features: detected: Spectre-BHB
10674 10:04:35.136408 <6>[ 0.094914] Detected PIPT I-cache on CPU4
10675 10:04:35.146579 <6>[ 0.094972] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10676 10:04:35.152973 <6>[ 0.094988] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10677 10:04:35.156308 <6>[ 0.095282] Detected PIPT I-cache on CPU5
10678 10:04:35.162812 <6>[ 0.095345] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10679 10:04:35.169707 <6>[ 0.095362] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10680 10:04:35.173358 <6>[ 0.095644] Detected PIPT I-cache on CPU6
10681 10:04:35.182769 <6>[ 0.095709] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10682 10:04:35.189328 <6>[ 0.095726] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10683 10:04:35.192360 <6>[ 0.096024] Detected PIPT I-cache on CPU7
10684 10:04:35.198768 <6>[ 0.096089] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10685 10:04:35.205862 <6>[ 0.096105] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10686 10:04:35.212191 <6>[ 0.096153] smp: Brought up 1 node, 8 CPUs
10687 10:04:35.215207 <6>[ 0.237520] SMP: Total of 8 processors activated.
10688 10:04:35.222073 <6>[ 0.242471] CPU features: detected: 32-bit EL0 Support
10689 10:04:35.228437 <6>[ 0.247833] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10690 10:04:35.235026 <6>[ 0.256688] CPU features: detected: Common not Private translations
10691 10:04:35.241902 <6>[ 0.263204] CPU features: detected: CRC32 instructions
10692 10:04:35.248404 <6>[ 0.268555] CPU features: detected: RCpc load-acquire (LDAPR)
10693 10:04:35.254655 <6>[ 0.274515] CPU features: detected: LSE atomic instructions
10694 10:04:35.258447 <6>[ 0.280296] CPU features: detected: Privileged Access Never
10695 10:04:35.264948 <6>[ 0.286076] CPU features: detected: RAS Extension Support
10696 10:04:35.271328 <6>[ 0.291719] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10697 10:04:35.277846 <6>[ 0.298939] CPU: All CPU(s) started at EL2
10698 10:04:35.281323 <6>[ 0.303255] alternatives: applying system-wide alternatives
10699 10:04:35.292004 <6>[ 0.313970] devtmpfs: initialized
10700 10:04:35.307604 <6>[ 0.322918] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10701 10:04:35.314124 <6>[ 0.332882] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10702 10:04:35.320583 <6>[ 0.341115] pinctrl core: initialized pinctrl subsystem
10703 10:04:35.324087 <6>[ 0.347777] DMI not present or invalid.
10704 10:04:35.330791 <6>[ 0.352190] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10705 10:04:35.340523 <6>[ 0.359068] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10706 10:04:35.346825 <6>[ 0.366651] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10707 10:04:35.356803 <6>[ 0.374878] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10708 10:04:35.363692 <6>[ 0.383125] audit: initializing netlink subsys (disabled)
10709 10:04:35.370374 <5>[ 0.388820] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10710 10:04:35.376757 <6>[ 0.389528] thermal_sys: Registered thermal governor 'step_wise'
10711 10:04:35.383257 <6>[ 0.396782] thermal_sys: Registered thermal governor 'power_allocator'
10712 10:04:35.386990 <6>[ 0.403038] cpuidle: using governor menu
10713 10:04:35.393281 <6>[ 0.413995] NET: Registered PF_QIPCRTR protocol family
10714 10:04:35.399732 <6>[ 0.419470] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10715 10:04:35.406149 <6>[ 0.426574] ASID allocator initialised with 32768 entries
10716 10:04:35.409312 <6>[ 0.433139] Serial: AMBA PL011 UART driver
10717 10:04:35.420011 <4>[ 0.441799] Trying to register duplicate clock ID: 134
10718 10:04:35.474050 <6>[ 0.498972] KASLR enabled
10719 10:04:35.488325 <6>[ 0.506773] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10720 10:04:35.494936 <6>[ 0.513786] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10721 10:04:35.501528 <6>[ 0.520276] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10722 10:04:35.508359 <6>[ 0.527281] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10723 10:04:35.514560 <6>[ 0.533770] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10724 10:04:35.521182 <6>[ 0.540774] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10725 10:04:35.527525 <6>[ 0.547261] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10726 10:04:35.534115 <6>[ 0.554267] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10727 10:04:35.537646 <6>[ 0.561791] ACPI: Interpreter disabled.
10728 10:04:35.546554 <6>[ 0.568185] iommu: Default domain type: Translated
10729 10:04:35.552851 <6>[ 0.573298] iommu: DMA domain TLB invalidation policy: strict mode
10730 10:04:35.556107 <5>[ 0.579953] SCSI subsystem initialized
10731 10:04:35.562848 <6>[ 0.584120] usbcore: registered new interface driver usbfs
10732 10:04:35.569981 <6>[ 0.589852] usbcore: registered new interface driver hub
10733 10:04:35.572936 <6>[ 0.595403] usbcore: registered new device driver usb
10734 10:04:35.579870 <6>[ 0.601485] pps_core: LinuxPPS API ver. 1 registered
10735 10:04:35.589638 <6>[ 0.606678] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10736 10:04:35.592658 <6>[ 0.616023] PTP clock support registered
10737 10:04:35.596125 <6>[ 0.620266] EDAC MC: Ver: 3.0.0
10738 10:04:35.603784 <6>[ 0.625408] FPGA manager framework
10739 10:04:35.610006 <6>[ 0.629089] Advanced Linux Sound Architecture Driver Initialized.
10740 10:04:35.613152 <6>[ 0.635856] vgaarb: loaded
10741 10:04:35.620098 <6>[ 0.639019] clocksource: Switched to clocksource arch_sys_counter
10742 10:04:35.623387 <5>[ 0.645463] VFS: Disk quotas dquot_6.6.0
10743 10:04:35.629725 <6>[ 0.649647] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10744 10:04:35.633062 <6>[ 0.656841] pnp: PnP ACPI: disabled
10745 10:04:35.641661 <6>[ 0.663603] NET: Registered PF_INET protocol family
10746 10:04:35.651493 <6>[ 0.669202] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10747 10:04:35.662926 <6>[ 0.681543] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10748 10:04:35.673051 <6>[ 0.690361] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10749 10:04:35.679606 <6>[ 0.698331] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10750 10:04:35.689258 <6>[ 0.707028] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10751 10:04:35.696100 <6>[ 0.716776] TCP: Hash tables configured (established 65536 bind 65536)
10752 10:04:35.702723 <6>[ 0.723634] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10753 10:04:35.712224 <6>[ 0.730829] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10754 10:04:35.719030 <6>[ 0.738528] NET: Registered PF_UNIX/PF_LOCAL protocol family
10755 10:04:35.725450 <6>[ 0.744680] RPC: Registered named UNIX socket transport module.
10756 10:04:35.729062 <6>[ 0.750837] RPC: Registered udp transport module.
10757 10:04:35.735863 <6>[ 0.755769] RPC: Registered tcp transport module.
10758 10:04:35.742004 <6>[ 0.760702] RPC: Registered tcp NFSv4.1 backchannel transport module.
10759 10:04:35.745410 <6>[ 0.767363] PCI: CLS 0 bytes, default 64
10760 10:04:35.748767 <6>[ 0.771691] Unpacking initramfs...
10761 10:04:35.773341 <6>[ 0.791156] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10762 10:04:35.783043 <6>[ 0.799827] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10763 10:04:35.786172 <6>[ 0.808666] kvm [1]: IPA Size Limit: 40 bits
10764 10:04:35.792841 <6>[ 0.813193] kvm [1]: GICv3: no GICV resource entry
10765 10:04:35.796230 <6>[ 0.818213] kvm [1]: disabling GICv2 emulation
10766 10:04:35.802641 <6>[ 0.822900] kvm [1]: GIC system register CPU interface enabled
10767 10:04:35.805892 <6>[ 0.829072] kvm [1]: vgic interrupt IRQ18
10768 10:04:35.812068 <6>[ 0.833428] kvm [1]: VHE mode initialized successfully
10769 10:04:35.818497 <5>[ 0.839834] Initialise system trusted keyrings
10770 10:04:35.825402 <6>[ 0.844631] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10771 10:04:35.832978 <6>[ 0.854860] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10772 10:04:35.839805 <5>[ 0.861261] NFS: Registering the id_resolver key type
10773 10:04:35.842799 <5>[ 0.866569] Key type id_resolver registered
10774 10:04:35.849448 <5>[ 0.870984] Key type id_legacy registered
10775 10:04:35.856014 <6>[ 0.875269] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10776 10:04:35.862418 <6>[ 0.882190] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10777 10:04:35.868921 <6>[ 0.889916] 9p: Installing v9fs 9p2000 file system support
10778 10:04:35.906022 <5>[ 0.927812] Key type asymmetric registered
10779 10:04:35.909256 <5>[ 0.932145] Asymmetric key parser 'x509' registered
10780 10:04:35.919177 <6>[ 0.937307] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10781 10:04:35.922338 <6>[ 0.944918] io scheduler mq-deadline registered
10782 10:04:35.925460 <6>[ 0.949698] io scheduler kyber registered
10783 10:04:35.945213 <6>[ 0.966676] EINJ: ACPI disabled.
10784 10:04:35.977419 <4>[ 0.992299] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10785 10:04:35.987044 <4>[ 1.002924] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10786 10:04:36.001943 <6>[ 1.023478] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10787 10:04:36.009763 <6>[ 1.031550] printk: console [ttyS0] disabled
10788 10:04:36.037825 <6>[ 1.056205] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10789 10:04:36.044754 <6>[ 1.065690] printk: console [ttyS0] enabled
10790 10:04:36.048065 <6>[ 1.065690] printk: console [ttyS0] enabled
10791 10:04:36.054393 <6>[ 1.074592] printk: bootconsole [mtk8250] disabled
10792 10:04:36.057505 <6>[ 1.074592] printk: bootconsole [mtk8250] disabled
10793 10:04:36.064259 <6>[ 1.085939] SuperH (H)SCI(F) driver initialized
10794 10:04:36.067569 <6>[ 1.091244] msm_serial: driver initialized
10795 10:04:36.081924 <6>[ 1.100166] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10796 10:04:36.091768 <6>[ 1.108713] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10797 10:04:36.098352 <6>[ 1.117256] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10798 10:04:36.108389 <6>[ 1.125884] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10799 10:04:36.118641 <6>[ 1.134597] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10800 10:04:36.124826 <6>[ 1.143310] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10801 10:04:36.134807 <6>[ 1.151850] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10802 10:04:36.141664 <6>[ 1.160651] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10803 10:04:36.151396 <6>[ 1.169193] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10804 10:04:36.162992 <6>[ 1.184738] loop: module loaded
10805 10:04:36.169967 <6>[ 1.190776] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10806 10:04:36.192243 <4>[ 1.213998] mtk-pmic-keys: Failed to locate of_node [id: -1]
10807 10:04:36.198921 <6>[ 1.220677] megasas: 07.719.03.00-rc1
10808 10:04:36.208720 <6>[ 1.230179] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10809 10:04:36.217214 <6>[ 1.238394] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10810 10:04:36.233508 <6>[ 1.254968] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10811 10:04:36.293971 <6>[ 1.308978] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10812 10:04:39.755663 <6>[ 4.777775] Freeing initrd memory: 95820K
10813 10:04:39.765726 <6>[ 4.788212] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10814 10:04:39.776791 <6>[ 4.799155] tun: Universal TUN/TAP device driver, 1.6
10815 10:04:39.780226 <6>[ 4.805203] thunder_xcv, ver 1.0
10816 10:04:39.783243 <6>[ 4.808709] thunder_bgx, ver 1.0
10817 10:04:39.786697 <6>[ 4.812205] nicpf, ver 1.0
10818 10:04:39.797114 <6>[ 4.816204] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10819 10:04:39.800277 <6>[ 4.823679] hns3: Copyright (c) 2017 Huawei Corporation.
10820 10:04:39.807280 <6>[ 4.829265] hclge is initializing
10821 10:04:39.810407 <6>[ 4.832845] e1000: Intel(R) PRO/1000 Network Driver
10822 10:04:39.816875 <6>[ 4.837974] e1000: Copyright (c) 1999-2006 Intel Corporation.
10823 10:04:39.820228 <6>[ 4.843989] e1000e: Intel(R) PRO/1000 Network Driver
10824 10:04:39.827104 <6>[ 4.849205] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10825 10:04:39.833870 <6>[ 4.855390] igb: Intel(R) Gigabit Ethernet Network Driver
10826 10:04:39.840237 <6>[ 4.861039] igb: Copyright (c) 2007-2014 Intel Corporation.
10827 10:04:39.846794 <6>[ 4.866875] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10828 10:04:39.853718 <6>[ 4.873393] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10829 10:04:39.856864 <6>[ 4.879853] sky2: driver version 1.30
10830 10:04:39.863048 <6>[ 4.884817] VFIO - User Level meta-driver version: 0.3
10831 10:04:39.871110 <6>[ 4.893023] usbcore: registered new interface driver usb-storage
10832 10:04:39.877379 <6>[ 4.899465] usbcore: registered new device driver onboard-usb-hub
10833 10:04:39.886293 <6>[ 4.908537] mt6397-rtc mt6359-rtc: registered as rtc0
10834 10:04:39.895972 <6>[ 4.914019] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-10T10:04:42 UTC (1686391482)
10835 10:04:39.899472 <6>[ 4.923608] i2c_dev: i2c /dev entries driver
10836 10:04:39.916568 <6>[ 4.935361] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10837 10:04:39.923272 <6>[ 4.945585] sdhci: Secure Digital Host Controller Interface driver
10838 10:04:39.929665 <6>[ 4.952022] sdhci: Copyright(c) Pierre Ossman
10839 10:04:39.936565 <6>[ 4.957409] Synopsys Designware Multimedia Card Interface Driver
10840 10:04:39.939713 <6>[ 4.964037] mmc0: CQHCI version 5.10
10841 10:04:39.946212 <6>[ 4.964586] sdhci-pltfm: SDHCI platform and OF driver helper
10842 10:04:39.953858 <6>[ 4.975902] ledtrig-cpu: registered to indicate activity on CPUs
10843 10:04:39.964534 <6>[ 4.983218] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10844 10:04:39.968095 <6>[ 4.990597] usbcore: registered new interface driver usbhid
10845 10:04:39.974465 <6>[ 4.996429] usbhid: USB HID core driver
10846 10:04:39.981160 <6>[ 5.000671] spi_master spi0: will run message pump with realtime priority
10847 10:04:40.029924 <6>[ 5.045635] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10848 10:04:40.050305 <6>[ 5.061732] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10849 10:04:40.053390 <6>[ 5.075315] mmc0: Command Queue Engine enabled
10850 10:04:40.060330 <6>[ 5.078522] cros-ec-spi spi0.0: Chrome EC device registered
10851 10:04:40.066698 <6>[ 5.080062] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10852 10:04:40.070179 <6>[ 5.093188] mmcblk0: mmc0:0001 DA4128 116 GiB
10853 10:04:40.085689 <6>[ 5.104180] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10854 10:04:40.091989 <6>[ 5.107801] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10855 10:04:40.099079 <6>[ 5.115687] NET: Registered PF_PACKET protocol family
10856 10:04:40.101924 <6>[ 5.120836] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10857 10:04:40.108850 <6>[ 5.124826] 9pnet: Installing 9P2000 support
10858 10:04:40.111826 <6>[ 5.130649] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10859 10:04:40.118314 <5>[ 5.134519] Key type dns_resolver registered
10860 10:04:40.125094 <6>[ 5.140306] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10861 10:04:40.128399 <6>[ 5.144831] registered taskstats version 1
10862 10:04:40.131419 <5>[ 5.155119] Loading compiled-in X.509 certificates
10863 10:04:40.167125 <4>[ 5.182962] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10864 10:04:40.177142 <4>[ 5.193648] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10865 10:04:40.187583 <3>[ 5.206396] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10866 10:04:40.199826 <6>[ 5.221868] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10867 10:04:40.206809 <6>[ 5.228612] xhci-mtk 11200000.usb: xHCI Host Controller
10868 10:04:40.213407 <6>[ 5.234113] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10869 10:04:40.223350 <6>[ 5.241957] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10870 10:04:40.230008 <6>[ 5.251400] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10871 10:04:40.236419 <6>[ 5.257598] xhci-mtk 11200000.usb: xHCI Host Controller
10872 10:04:40.243175 <6>[ 5.263104] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10873 10:04:40.249418 <6>[ 5.270764] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10874 10:04:40.256830 <6>[ 5.278656] hub 1-0:1.0: USB hub found
10875 10:04:40.260107 <6>[ 5.282712] hub 1-0:1.0: 1 port detected
10876 10:04:40.269741 <6>[ 5.287076] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10877 10:04:40.273019 <6>[ 5.295921] hub 2-0:1.0: USB hub found
10878 10:04:40.276297 <6>[ 5.299955] hub 2-0:1.0: 1 port detected
10879 10:04:40.285083 <6>[ 5.307202] mtk-msdc 11f70000.mmc: Got CD GPIO
10880 10:04:40.302540 <6>[ 5.321088] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10881 10:04:40.309232 <6>[ 5.329116] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10882 10:04:40.318807 <4>[ 5.337086] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10883 10:04:40.328991 <6>[ 5.346755] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10884 10:04:40.335495 <6>[ 5.354836] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10885 10:04:40.345471 <6>[ 5.362871] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10886 10:04:40.352169 <6>[ 5.370788] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10887 10:04:40.358229 <6>[ 5.378610] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10888 10:04:40.368404 <6>[ 5.386438] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10889 10:04:40.378624 <6>[ 5.397168] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10890 10:04:40.388797 <6>[ 5.405536] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10891 10:04:40.395140 <6>[ 5.413888] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10892 10:04:40.405057 <6>[ 5.422231] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10893 10:04:40.411608 <6>[ 5.430575] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10894 10:04:40.421404 <6>[ 5.438918] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10895 10:04:40.427980 <6>[ 5.447262] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10896 10:04:40.438062 <6>[ 5.455605] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10897 10:04:40.444362 <6>[ 5.463949] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10898 10:04:40.454649 <6>[ 5.472302] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10899 10:04:40.460985 <6>[ 5.480646] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10900 10:04:40.470822 <6>[ 5.488990] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10901 10:04:40.477543 <6>[ 5.497334] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10902 10:04:40.487573 <6>[ 5.505677] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10903 10:04:40.493780 <6>[ 5.514022] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10904 10:04:40.500684 <6>[ 5.522922] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10905 10:04:40.508101 <6>[ 5.530342] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10906 10:04:40.515436 <6>[ 5.537388] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10907 10:04:40.525953 <6>[ 5.544496] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10908 10:04:40.532433 <6>[ 5.551809] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10909 10:04:40.542200 <6>[ 5.558715] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10910 10:04:40.549074 <6>[ 5.567858] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10911 10:04:40.558594 <6>[ 5.576986] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10912 10:04:40.568825 <6>[ 5.586288] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10913 10:04:40.578798 <6>[ 5.595763] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10914 10:04:40.588765 <6>[ 5.605238] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10915 10:04:40.598134 <6>[ 5.614365] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10916 10:04:40.605024 <6>[ 5.623841] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10917 10:04:40.615107 <6>[ 5.632968] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10918 10:04:40.624797 <6>[ 5.642282] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10919 10:04:40.634558 <6>[ 5.652449] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10920 10:04:40.645372 <6>[ 5.664281] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10921 10:04:40.688560 <6>[ 5.707327] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10922 10:04:40.842518 <6>[ 5.864771] hub 1-1:1.0: USB hub found
10923 10:04:40.846367 <6>[ 5.869245] hub 1-1:1.0: 4 ports detected
10924 10:04:40.968431 <6>[ 5.987491] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10925 10:04:40.993844 <6>[ 6.015791] hub 2-1:1.0: USB hub found
10926 10:04:40.996933 <6>[ 6.020185] hub 2-1:1.0: 3 ports detected
10927 10:04:41.168330 <6>[ 6.187292] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10928 10:04:41.301056 <6>[ 6.323550] hub 1-1.4:1.0: USB hub found
10929 10:04:41.304298 <6>[ 6.328227] hub 1-1.4:1.0: 2 ports detected
10930 10:04:41.380414 <6>[ 6.399522] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10931 10:04:41.600045 <6>[ 6.619293] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10932 10:04:41.792630 <6>[ 6.811293] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10933 10:04:52.936811 <6>[ 17.963708] ALSA device list:
10934 10:04:52.943078 <6>[ 17.966943] No soundcards found.
10935 10:04:52.955591 <6>[ 17.979365] Freeing unused kernel memory: 8384K
10936 10:04:52.959042 <6>[ 17.984280] Run /init as init process
10937 10:04:52.989305 <6>[ 18.013050] NET: Registered PF_INET6 protocol family
10938 10:04:52.995655 <6>[ 18.019561] Segment Routing with IPv6
10939 10:04:52.999207 <6>[ 18.023533] In-situ OAM (IOAM) with IPv6
10940 10:04:53.033903 <30>[ 18.038010] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10941 10:04:53.037186 <30>[ 18.061836] systemd[1]: Detected architecture arm64.
10942 10:04:53.037270
10943 10:04:53.044006 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10944 10:04:53.044090
10945 10:04:53.059735 <30>[ 18.083439] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10946 10:04:53.186640 <30>[ 18.207171] systemd[1]: Queued start job for default target Graphical Interface.
10947 10:04:53.233048 <30>[ 18.256696] systemd[1]: Created slice system-getty.slice.
10948 10:04:53.239428 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10949 10:04:53.256192 <30>[ 18.279898] systemd[1]: Created slice system-modprobe.slice.
10950 10:04:53.262400 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10951 10:04:53.279753 <30>[ 18.303783] systemd[1]: Created slice system-serial\x2dgetty.slice.
10952 10:04:53.290123 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10953 10:04:53.304491 <30>[ 18.328335] systemd[1]: Created slice User and Session Slice.
10954 10:04:53.311422 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10955 10:04:53.331297 <30>[ 18.351825] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10956 10:04:53.341158 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10957 10:04:53.358737 <30>[ 18.379450] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10958 10:04:53.365727 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10959 10:04:53.386231 <30>[ 18.403369] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10960 10:04:53.392609 <30>[ 18.415406] systemd[1]: Reached target Local Encrypted Volumes.
10961 10:04:53.399723 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10962 10:04:53.415839 <30>[ 18.439648] systemd[1]: Reached target Paths.
10963 10:04:53.419035 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10964 10:04:53.435511 <30>[ 18.459281] systemd[1]: Reached target Remote File Systems.
10965 10:04:53.441805 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10966 10:04:53.455601 <30>[ 18.479279] systemd[1]: Reached target Slices.
10967 10:04:53.462080 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10968 10:04:53.475737 <30>[ 18.499348] systemd[1]: Reached target Swap.
10969 10:04:53.479018 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10970 10:04:53.498993 <30>[ 18.519550] systemd[1]: Listening on initctl Compatibility Named Pipe.
10971 10:04:53.505623 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10972 10:04:53.512287 <30>[ 18.534253] systemd[1]: Listening on Journal Audit Socket.
10973 10:04:53.518735 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10974 10:04:53.531489 <30>[ 18.555545] systemd[1]: Listening on Journal Socket (/dev/log).
10975 10:04:53.538129 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10976 10:04:53.555976 <30>[ 18.580079] systemd[1]: Listening on Journal Socket.
10977 10:04:53.562854 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10978 10:04:53.575806 <30>[ 18.599592] systemd[1]: Listening on udev Control Socket.
10979 10:04:53.582187 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10980 10:04:53.600026 <30>[ 18.623970] systemd[1]: Listening on udev Kernel Socket.
10981 10:04:53.606424 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10982 10:04:53.643779 <30>[ 18.667650] systemd[1]: Mounting Huge Pages File System...
10983 10:04:53.650108 Mounting [0;1;39mHuge Pages File System[0m...
10984 10:04:53.665610 <30>[ 18.689408] systemd[1]: Mounting POSIX Message Queue File System...
10985 10:04:53.672553 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10986 10:04:53.689416 <30>[ 18.713337] systemd[1]: Mounting Kernel Debug File System...
10987 10:04:53.695699 Mounting [0;1;39mKernel Debug File System[0m...
10988 10:04:53.715042 <30>[ 18.735604] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10989 10:04:53.725739 <30>[ 18.746635] systemd[1]: Starting Create list of static device nodes for the current kernel...
10990 10:04:53.732698 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10991 10:04:53.749407 <30>[ 18.773512] systemd[1]: Starting Load Kernel Module configfs...
10992 10:04:53.755860 Starting [0;1;39mLoad Kernel Module configfs[0m...
10993 10:04:53.773860 <30>[ 18.797548] systemd[1]: Starting Load Kernel Module drm...
10994 10:04:53.780143 Starting [0;1;39mLoad Kernel Module drm[0m...
10995 10:04:53.799000 <30>[ 18.819570] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10996 10:04:53.839987 <30>[ 18.863938] systemd[1]: Starting Journal Service...
10997 10:04:53.843396 Starting [0;1;39mJournal Service[0m...
10998 10:04:53.861762 <30>[ 18.885870] systemd[1]: Starting Load Kernel Modules...
10999 10:04:53.868145 Starting [0;1;39mLoad Kernel Modules[0m...
11000 10:04:53.889551 <30>[ 18.910099] systemd[1]: Starting Remount Root and Kernel File Systems...
11001 10:04:53.895845 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11002 10:04:53.913995 <30>[ 18.937947] systemd[1]: Starting Coldplug All udev Devices...
11003 10:04:53.920738 Starting [0;1;39mColdplug All udev Devices[0m...
11004 10:04:53.938459 <30>[ 18.962073] systemd[1]: Mounted Huge Pages File System.
11005 10:04:53.945085 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11006 10:04:53.960103 <30>[ 18.983839] systemd[1]: Started Journal Service.
11007 10:04:53.967334 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11008 10:04:53.981400 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11009 10:04:53.996714 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11010 10:04:54.016095 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11011 10:04:54.033361 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11012 10:04:54.049223 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11013 10:04:54.069305 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11014 10:04:54.089093 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11015 10:04:54.104160 See 'systemctl status systemd-remount-fs.service' for details.
11016 10:04:54.148177 Mounting [0;1;39mKernel Configuration File System[0m...
11017 10:04:54.166304 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11018 10:04:54.184435 <46>[ 19.204627] systemd-journald[177]: Received client request to flush runtime journal.
11019 10:04:54.192727 Starting [0;1;39mLoad/Save Random Seed[0m...
11020 10:04:54.210729 Starting [0;1;39mApply Kernel Variables[0m...
11021 10:04:54.230396 Starting [0;1;39mCreate System Users[0m...
11022 10:04:54.245694 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11023 10:04:54.268447 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11024 10:04:54.280648 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11025 10:04:54.296734 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11026 10:04:54.312990 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11027 10:04:54.332617 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11028 10:04:54.372531 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11029 10:04:54.395663 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11030 10:04:54.412391 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11031 10:04:54.427661 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11032 10:04:54.472317 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11033 10:04:54.495114 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11034 10:04:54.516392 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11035 10:04:54.540663 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11036 10:04:54.600838 Starting [0;1;39mNetwork Time Synchronization[0m...
11037 10:04:54.619895 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11038 10:04:54.659475 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11039 10:04:54.691342 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11040 10:04:54.697843 <6>[ 19.718909] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11041 10:04:54.709485 [[0;32m OK [<6>[ 19.734157] remoteproc remoteproc0: scp is available
11042 10:04:54.725887 0m] Created slice [0;1;39msystem-systemd\x2dbac<4>[ 19.742999] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11043 10:04:54.732363 klight.slice[0m<6>[ 19.753601] remoteproc remoteproc0: powering up scp
11044 10:04:54.732867 .
11045 10:04:54.742242 <4>[ 19.761008] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11046 10:04:54.748882 <3>[ 19.770867] remoteproc remoteproc0: request_firmware failed: -2
11047 10:04:54.764893 <3>[ 19.785490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11048 10:04:54.772206 <3>[ 19.793632] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11049 10:04:54.781975 <3>[ 19.801727] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11050 10:04:54.798074 <3>[ 19.818214] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11051 10:04:54.804391 <3>[ 19.826522] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11052 10:04:54.814547 <3>[ 19.834717] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11053 10:04:54.820908 <3>[ 19.842875] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11054 10:04:54.830657 Startin<6>[ 19.844711] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11055 10:04:54.840533 g [0;1;39mLoad/<3>[ 19.851095] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11056 10:04:54.850693 Save Screen …o<6>[ 19.860001] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11057 10:04:54.860364 f leds:white:kbd<3>[ 19.877191] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11058 10:04:54.870316 _backlight[0m..<6>[ 19.879512] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11059 10:04:54.870799 .
11060 10:04:54.891367 <3>[ 19.911814] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11061 10:04:54.898404 <3>[ 19.919997] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11062 10:04:54.908226 <3>[ 19.928117] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11063 10:04:54.914558 <6>[ 19.935811] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11064 10:04:54.921171 <4>[ 19.936887] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11065 10:04:54.930743 <3>[ 19.947909] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11066 10:04:54.937747 <3>[ 19.959293] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11067 10:04:54.947596 <3>[ 19.959304] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11068 10:04:54.954421 <3>[ 19.975496] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11069 10:04:54.960475 <6>[ 19.975979] mc: Linux media interface: v0.10
11070 10:04:54.967348 <3>[ 19.983584] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11071 10:04:54.977452 [[0;32m OK [<4>[ 19.983609] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11072 10:04:54.983919 <4>[ 19.983609] Fallback method does not support PEC.
11073 10:04:54.990508 0m] Started [0;<4>[ 19.988609] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11074 10:04:54.999994 <3>[ 19.991517] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11075 10:04:55.006804 1;39mNetwork Tim<6>[ 20.013300] videodev: Linux video capture interface: v2.00
11076 10:04:55.013345 e Synchronizatio<6>[ 20.025638] usbcore: registered new interface driver r8152
11077 10:04:55.020222 <6>[ 20.029955] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11078 10:04:55.020659 n[0m.
11079 10:04:55.026732 <6>[ 20.049362] pci_bus 0000:00: root bus resource [bus 00-ff]
11080 10:04:55.036389 <6>[ 20.051719] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11081 10:04:55.043691 <6>[ 20.057105] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11082 10:04:55.056899 [[0;32m OK [0m] Finished [0<6>[ 20.074009] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11083 10:04:55.066341 ;1;39mLoad/Save <6>[ 20.075099] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11084 10:04:55.076392 Screen …s of l<3>[ 20.082544] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11085 10:04:55.086145 eds:white:kbd_ba<6>[ 20.087495] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11086 10:04:55.086231 cklight[0m.
11087 10:04:55.092685 <6>[ 20.114847] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11088 10:04:55.102651 <6>[ 20.114963] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11089 10:04:55.106193 <6>[ 20.130598] pci 0000:00:00.0: supports D1 D2
11090 10:04:55.115706 <6>[ 20.134657] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11091 10:04:55.122524 <6>[ 20.135133] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11092 10:04:55.129653 <6>[ 20.137301] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11093 10:04:55.140006 <4>[ 20.142742] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11094 10:04:55.146787 <4>[ 20.142753] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11095 10:04:55.157710 <3>[ 20.164953] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11096 10:04:55.163986 <6>[ 20.168992] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11097 10:04:55.170640 <3>[ 20.175119] power_supply sbs-5-000b: driver failed to report `status' property: -6
11098 10:04:55.180496 <3>[ 20.185509] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11099 10:04:55.188028 <6>[ 20.185709] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11100 10:04:55.191544 <6>[ 20.193263] Bluetooth: Core ver 2.22
11101 10:04:55.198120 <6>[ 20.193423] usbcore: registered new interface driver cdc_ether
11102 10:04:55.204284 <6>[ 20.199781] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11103 10:04:55.211060 <6>[ 20.199992] usbcore: registered new interface driver r8153_ecm
11104 10:04:55.217745 <6>[ 20.208644] NET: Registered PF_BLUETOOTH protocol family
11105 10:04:55.221589 <6>[ 20.208652] r8152 2-1.3:1.0 eth0: v1.12.13
11106 10:04:55.227977 <3>[ 20.212450] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11107 10:04:55.238294 <6>[ 20.216055] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11108 10:04:55.244631 <6>[ 20.217705] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11109 10:04:55.255454 <6>[ 20.218978] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11110 10:04:55.261890 <6>[ 20.219189] usbcore: registered new interface driver uvcvideo
11111 10:04:55.268116 <6>[ 20.219878] Bluetooth: HCI device and connection manager initialized
11112 10:04:55.275273 <6>[ 20.223134] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
11113 10:04:55.278328 <6>[ 20.226092] pci 0000:01:00.0: supports D1 D2
11114 10:04:55.288348 <3>[ 20.229852] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11115 10:04:55.292250 <6>[ 20.233455] Bluetooth: HCI socket layer initialized
11116 10:04:55.298629 <6>[ 20.239534] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11117 10:04:55.305493 <6>[ 20.240316] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11118 10:04:55.312239 <6>[ 20.244122] remoteproc remoteproc0: powering up scp
11119 10:04:55.322260 <4>[ 20.244166] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11120 10:04:55.329016 <3>[ 20.244174] remoteproc remoteproc0: request_firmware failed: -2
11121 10:04:55.335229 <3>[ 20.244177] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11122 10:04:55.342018 <6>[ 20.245099] Bluetooth: L2CAP socket layer initialized
11123 10:04:55.349664 <3>[ 20.251539] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11124 10:04:55.355991 <6>[ 20.258234] Bluetooth: SCO socket layer initialized
11125 10:04:55.362525 <6>[ 20.267220] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11126 10:04:55.369388 <3>[ 20.286703] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11127 10:04:55.379854 <6>[ 20.291213] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11128 10:04:55.383002 <6>[ 20.309115] usbcore: registered new interface driver btusb
11129 10:04:55.393290 <4>[ 20.309750] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11130 10:04:55.399857 <3>[ 20.309759] Bluetooth: hci0: Failed to load firmware file (-2)
11131 10:04:55.406741 <3>[ 20.309763] Bluetooth: hci0: Failed to set up firmware (-2)
11132 10:04:55.416746 <4>[ 20.309766] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11133 10:04:55.423723 <6>[ 20.317198] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11134 10:04:55.433497 <6>[ 20.317213] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11135 10:04:55.440435 <3>[ 20.318825] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11136 10:04:55.449911 <3>[ 20.342034] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11137 10:04:55.456786 <6>[ 20.350668] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11138 10:04:55.467170 <6>[ 20.487406] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11139 10:04:55.470064 <6>[ 20.487421] pci 0000:00:00.0: PCI bridge to [bus 01]
11140 10:04:55.480058 <6>[ 20.487428] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11141 10:04:55.486695 <6>[ 20.487617] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11142 10:04:55.492936 [[0;32m OK [<6>[ 20.516121] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11143 10:04:55.499550 0m] Reached targ<6>[ 20.523037] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11144 10:04:55.503084 et [0;1;39mSystem Initialization[0m.
11145 10:04:55.520326 <5>[ 20.541282] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11146 10:04:55.531761 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11147 10:04:55.541760 <5>[ 20.562341] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11148 10:04:55.548129 <4>[ 20.569329] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11149 10:04:55.554436 <6>[ 20.578318] cfg80211: failed to load regulatory.db
11150 10:04:55.561277 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11151 10:04:55.583124 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11152 10:04:55.606601 [[0;32m OK [0m] Started [0;1;39mDiscard unu<6>[ 20.627569] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11153 10:04:55.613244 sed blocks once <6>[ 20.636027] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11154 10:04:55.616735 a week[0m.
11155 10:04:55.631567 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11156 10:04:55.640305 <6>[ 20.664488] mt7921e 0000:01:00.0: ASIC revision: 79610010
11157 10:04:55.651085 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11158 10:04:55.663271 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11159 10:04:55.679415 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11160 10:04:55.698504 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11161 10:04:55.745606 <4>[ 20.763105] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11162 10:04:55.751931 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11163 10:04:55.778667 Starting [0;1;39mUser Login Management[0m...
11164 10:04:55.793346 Starting [0;1;39mPermit User Sessions[0m...
11165 10:04:55.815522 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11166 10:04:55.837765 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11167 10:04:55.875426 <4>[ 20.891846] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11168 10:04:55.907850 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11169 10:04:55.925848 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11170 10:04:55.943417 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11171 10:04:55.972285 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11172 10:04:55.985635 <4>[ 21.003172] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11173 10:04:55.997084 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11174 10:04:56.012268 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11175 10:04:56.028220 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11176 10:04:56.043558 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11177 10:04:56.079242 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11178 10:04:56.105668 <4>[ 21.123249] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11179 10:04:56.112268 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11180 10:04:56.155917
11181 10:04:56.156012
11182 10:04:56.159187 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11183 10:04:56.159272
11184 10:04:56.162446 debian-bullseye-arm64 login: root (automatic login)
11185 10:04:56.162536
11186 10:04:56.162607
11187 10:04:56.179608 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023 aarch64
11188 10:04:56.179722
11189 10:04:56.185855 The programs included with the Debian GNU/Linux system are free software;
11190 10:04:56.192397 the exact distribution terms for each program are described in the
11191 10:04:56.195998 individual files in /usr/share/doc/*/copyright.
11192 10:04:56.196153
11193 10:04:56.202718 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11194 10:04:56.205995 permitted by applicable law.
11195 10:04:56.206596 Matched prompt #10: / #
11197 10:04:56.207121 Setting prompt string to ['/ #']
11198 10:04:56.207356 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11200 10:04:56.207939 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11201 10:04:56.208194 start: 2.2.6 expect-shell-connection (timeout 00:01:46) [common]
11202 10:04:56.208403 Setting prompt string to ['/ #']
11203 10:04:56.208586 Forcing a shell prompt, looking for ['/ #']
11205 10:04:56.259063 / #
11206 10:04:56.259613 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11207 10:04:56.260131 Waiting using forced prompt support (timeout 00:02:30)
11208 10:04:56.260654 <4>[ 21.242157] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11209 10:04:56.265455
11210 10:04:56.266342 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11211 10:04:56.267034 start: 2.2.7 export-device-env (timeout 00:01:46) [common]
11212 10:04:56.267735 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11213 10:04:56.268335 end: 2.2 depthcharge-retry (duration 00:03:14) [common]
11214 10:04:56.268911 end: 2 depthcharge-action (duration 00:03:14) [common]
11215 10:04:56.269418 start: 3 lava-test-retry (timeout 00:05:00) [common]
11216 10:04:56.270000 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11217 10:04:56.270412 Using namespace: common
11219 10:04:56.371765 / # #
11220 10:04:56.372445 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11221 10:04:56.373076 #<4>[ 21.361652] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11222 10:04:56.378002
11223 10:04:56.378730 Using /lava-10670675
11225 10:04:56.479922 / # export SHELL=/bin/sh
11226 10:04:56.480796 export SHELL=/bin/sh<4>[ 21.481564] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11227 10:04:56.486211
11229 10:04:56.587651 / # . /lava-10670675/environment
11230 10:04:56.588353 . /lava-10670675/environment<4>[ 21.601414] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11231 10:04:56.593468
11233 10:04:56.694757 / # /lava-10670675/bin/lava-test-runner /lava-10670675/0
11234 10:04:56.694958 Test shell timeout: 10s (minimum of the action and connection timeout)
11235 10:04:56.738962 /lava-10670675/bin/lava-test-runner /lava-10670675/0<4>[ 21.721270] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11236 10:04:56.739066
11237 10:04:56.739134 + export TESTRUN_ID=0_sleep
11238 10:04:56.739200 + cd /lava-10670675/0/tests/0_sleep
11239 10:04:56.740834 + cat uuid
11240 10:04:56.740919 + UUID=10670675_1.5.2.3.1
11241 10:04:56.744541 + set +x
11242 10:04:56.747638 <LAVA_SIGNAL_STARTRUN 0_sleep 10670675_1.5.2.3.1>
11243 10:04:56.747900 Received signal: <STARTRUN> 0_sleep 10670675_1.5.2.3.1
11244 10:04:56.747978 Starting test lava.0_sleep (10670675_1.5.2.3.1)
11245 10:04:56.748065 Skipping test definition patterns.
11246 10:04:56.750798 + ./config/lava/sleep/sleep.sh mem freeze
11247 10:04:56.754622 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11249 10:04:56.757527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11250 10:04:56.760702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11251 10:04:56.760954 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11253 10:04:56.764338 rtcwake: assuming RTC uses UTC ...
11254 10:04:56.774144 rtcwake: wakeup from "mem" using rtc0 at Sat<6>[ 21.796718] PM: suspend entry (deep)
11255 10:04:56.777155 Jun 10 10:05:05<6>[ 21.801963] Filesystems sync: 0.000 seconds
11256 10:04:56.780649 2023
11257 10:04:56.783926 <6>[ 21.809997] Freezing user space processes
11258 10:04:56.794872 <6>[ 21.815861] Freezing user space processes completed (elapsed 0.001 seconds)
11259 10:04:56.797907 <6>[ 21.823088] OOM killer disabled.
11260 10:04:56.801282 <6>[ 21.826567] Freezing remaining freezable tasks
11261 10:04:56.812438 <6>[ 21.833564] Freezing remaining freezable tasks completed (elapsed 0.002 seconds)
11262 10:04:56.819184 <6>[ 21.841290] printk: Suspending console(s) (use no_console_suspend to debug)
11263 10:04:56.828941 <4>[ 21.841754] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11264 10:05:00.107878 <3>[ 21.967217] mt7921e 0000:01:00.0: hardware init failed
11265 10:05:00.114426 <3>[ 24.907364] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11266 10:05:00.124238 <3>[ 24.907405] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11267 10:05:00.134396 <3>[ 24.907448] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11268 10:05:00.140930 <3>[ 24.907468] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11269 10:05:00.147897 <3>[ 24.907819] PM: Some devices failed to suspend, or early wake event detected
11270 10:05:00.154015 <4>[ 24.922208] typec port0-partner: PM: parent port0 should not be sleeping
11271 10:05:00.157502 <6>[ 25.184741] OOM killer enabled.
11272 10:05:00.165110 <6>[ 25.188143] Restarting tasks ... done.
11273 10:05:00.168584 <5>[ 25.193700] random: crng reseeded on system resumption
11274 10:05:00.173071 <6>[ 25.201109] PM: suspend exit
11275 10:05:00.176251 rtcwake: write error
11276 10:05:00.184699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11277 10:05:00.184953 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11279 10:05:00.187932 rtcwake: assuming RTC uses UTC ...
11280 10:05:00.194505 rtcwake: wakeup from "mem" using rtc0 at Sat Jun 10 10:05:08 2023
11281 10:05:00.207418 <6>[ 25.231854] PM: suspend entry (deep)
11282 10:05:00.211063 <6>[ 25.235755] Filesystems sync: 0.000 seconds
11283 10:05:00.217499 <6>[ 25.240853] Freezing user space processes
11284 10:05:00.224042 <6>[ 25.246759] Freezing user space processes completed (elapsed 0.001 seconds)
11285 10:05:00.227429 <6>[ 25.254042] OOM killer disabled.
11286 10:05:00.233904 <6>[ 25.257531] Freezing remaining freezable tasks
11287 10:05:00.240701 <6>[ 25.263061] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11288 10:05:00.247064 <6>[ 25.270718] printk: Suspending console(s) (use no_console_suspend to debug)
11289 10:05:03.700740 <3>[ 28.491300] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11290 10:05:03.710371 <3>[ 28.491324] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11291 10:05:03.720198 <3>[ 28.491350] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11292 10:05:03.726968 <3>[ 28.491372] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11293 10:05:03.736725 <3>[ 28.491736] PM: Some devices failed to suspend, or early wake event detected
11294 10:05:03.739963 <6>[ 28.764912] OOM killer enabled.
11295 10:05:03.743317 <6>[ 28.768311] Restarting tasks ... done.
11296 10:05:03.749954 <5>[ 28.773792] random: crng reseeded on system resumption
11297 10:05:03.753589 <6>[ 28.780314] PM: suspend exit
11298 10:05:03.756735 rtcwake: write error
11299 10:05:03.763905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11300 10:05:03.764690 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11302 10:05:03.767726 rtcwake: assuming RTC uses UTC ...
11303 10:05:03.774185 rtcwake: wakeup from "mem" using rtc0 at Sat Jun 10 10:05:12 2023
11304 10:05:03.786986 <6>[ 28.811388] PM: suspend entry (deep)
11305 10:05:03.790006 <6>[ 28.815308] Filesystems sync: 0.000 seconds
11306 10:05:03.796725 <6>[ 28.820505] Freezing user space processes
11307 10:05:03.803113 <6>[ 28.826582] Freezing user space processes completed (elapsed 0.001 seconds)
11308 10:05:03.806824 <6>[ 28.833819] OOM killer disabled.
11309 10:05:03.813447 <6>[ 28.837301] Freezing remaining freezable tasks
11310 10:05:03.819680 <6>[ 28.843109] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11311 10:05:03.829498 <6>[ 28.850764] printk: Suspending console(s) (use no_console_suspend to debug)
11312 10:05:07.284043 <3>[ 32.075325] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11313 10:05:07.293890 <3>[ 32.075351] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11314 10:05:07.303579 <3>[ 32.075384] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11315 10:05:07.310592 <3>[ 32.075405] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11316 10:05:07.320500 <3>[ 32.075820] PM: Some devices failed to suspend, or early wake event detected
11317 10:05:07.323647 <6>[ 32.348909] OOM killer enabled.
11318 10:05:07.326563 <6>[ 32.352310] Restarting tasks ... done.
11319 10:05:07.333343 <5>[ 32.358256] random: crng reseeded on system resumption
11320 10:05:07.336705 <6>[ 32.364800] PM: suspend exit
11321 10:05:07.340564 rtcwake: write error
11322 10:05:07.347730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11323 10:05:07.348428 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11325 10:05:07.351842 rtcwake: assuming RTC uses UTC ...
11326 10:05:07.357649 rtcwake: wakeup from "mem" using rtc0 at Sat Jun 10 10:05:15 2023
11327 10:05:07.370874 <6>[ 32.396042] PM: suspend entry (deep)
11328 10:05:07.374222 <6>[ 32.399932] Filesystems sync: 0.000 seconds
11329 10:05:07.381165 <6>[ 32.405071] Freezing user space processes
11330 10:05:07.387277 <6>[ 32.411232] Freezing user space processes completed (elapsed 0.001 seconds)
11331 10:05:07.390447 <6>[ 32.418479] OOM killer disabled.
11332 10:05:07.397339 <6>[ 32.421963] Freezing remaining freezable tasks
11333 10:05:07.403875 <6>[ 32.427910] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11334 10:05:07.413738 <6>[ 32.435567] printk: Suspending console(s) (use no_console_suspend to debug)
11335 10:05:10.863734 <3>[ 35.659295] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11336 10:05:10.873669 <3>[ 35.659320] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11337 10:05:10.883743 <3>[ 35.659353] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11338 10:05:10.889925 <3>[ 35.659375] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11339 10:05:10.897013 <3>[ 35.659817] PM: Some devices failed to suspend, or early wake event detected
11340 10:05:10.903478 <6>[ 35.928901] OOM killer enabled.
11341 10:05:10.906716 <6>[ 35.932300] Restarting tasks ... done.
11342 10:05:10.913347 <5>[ 35.937961] random: crng reseeded on system resumption
11343 10:05:10.916654 <6>[ 35.944499] PM: suspend exit
11344 10:05:10.919555 rtcwake: write error
11345 10:05:10.927727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11346 10:05:10.928594 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11348 10:05:10.930870 rtcwake: assuming RTC uses UTC ...
11349 10:05:10.937568 rtcwake: wakeup from "mem" using rtc0 at Sat Jun 10 10:05:19 2023
11350 10:05:10.950587 <6>[ 35.975821] PM: suspend entry (deep)
11351 10:05:10.953428 <6>[ 35.979728] Filesystems sync: 0.000 seconds
11352 10:05:10.960538 <6>[ 35.984870] Freezing user space processes
11353 10:05:10.967517 <6>[ 35.990855] Freezing user space processes completed (elapsed 0.001 seconds)
11354 10:05:10.970482 <6>[ 35.998136] OOM killer disabled.
11355 10:05:10.977574 <6>[ 36.001629] Freezing remaining freezable tasks
11356 10:05:10.984031 <6>[ 36.007599] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11357 10:05:10.993728 <6>[ 36.015255] printk: Suspending console(s) (use no_console_suspend to debug)
11358 10:05:14.450740 <3>[ 39.243315] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11359 10:05:14.461337 <3>[ 39.243344] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11360 10:05:14.470951 <3>[ 39.243379] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11361 10:05:14.477533 <3>[ 39.243402] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11362 10:05:14.487206 <3>[ 39.243877] PM: Some devices failed to suspend, or early wake event detected
11363 10:05:14.490198 <6>[ 39.516346] OOM killer enabled.
11364 10:05:14.494006 <6>[ 39.519745] Restarting tasks ... done.
11365 10:05:14.500734 <5>[ 39.525392] random: crng reseeded on system resumption
11366 10:05:14.503507 <6>[ 39.532191] PM: suspend exit
11367 10:05:14.506776 rtcwake: write error
11368 10:05:14.515244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11369 10:05:14.516184 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11371 10:05:14.518164 rtcwake: assuming RTC uses UTC ...
11372 10:05:14.524479 rtcwake: wakeup from "mem" using rtc0 at Sat Jun 10 10:05:23 2023
11373 10:05:14.537550 <6>[ 39.563226] PM: suspend entry (deep)
11374 10:05:14.540661 <6>[ 39.567139] Filesystems sync: 0.000 seconds
11375 10:05:14.547371 <6>[ 39.572303] Freezing user space processes
11376 10:05:14.554117 <6>[ 39.578403] Freezing user space processes completed (elapsed 0.001 seconds)
11377 10:05:14.557424 <6>[ 39.585654] OOM killer disabled.
11378 10:05:14.563883 <6>[ 39.589145] Freezing remaining freezable tasks
11379 10:05:14.573289 <6>[ 39.595201] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11380 10:05:14.580009 <6>[ 39.602877] printk: Suspending console(s) (use no_console_suspend to debug)
11381 10:05:18.026397 <3>[ 42.827380] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11382 10:05:18.039342 <3>[ 42.827473] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11383 10:05:18.046012 <3>[ 42.827526] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11384 10:05:18.052547 <3>[ 42.827547] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11385 10:05:18.062751 <3>[ 42.827755] PM: Some devices failed to suspend, or early wake event detected
11386 10:05:18.066294 <6>[ 43.092295] OOM killer enabled.
11387 10:05:18.068997 <6>[ 43.095694] Restarting tasks ... done.
11388 10:05:18.076229 <5>[ 43.101381] random: crng reseeded on system resumption
11389 10:05:18.079531 <6>[ 43.108539] PM: suspend exit
11390 10:05:18.082200 rtcwake: write error
11391 10:05:18.090596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11392 10:05:18.091513 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11394 10:05:18.093581 rtcwake: assuming RTC uses UTC ...
11395 10:05:18.100500 rtcwake: wakeup from "mem" using rtc0 at Sat Jun 10 10:05:26 2023
11396 10:05:18.113457 <6>[ 43.139480] PM: suspend entry (deep)
11397 10:05:18.116582 <6>[ 43.143409] Filesystems sync: 0.000 seconds
11398 10:05:18.123352 <6>[ 43.148584] Freezing user space processes
11399 10:05:18.129506 <6>[ 43.154723] Freezing user space processes completed (elapsed 0.001 seconds)
11400 10:05:18.133147 <6>[ 43.161979] OOM killer disabled.
11401 10:05:18.140097 <6>[ 43.165463] Freezing remaining freezable tasks
11402 10:05:18.146288 <6>[ 43.171092] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11403 10:05:18.156164 <6>[ 43.178758] printk: Suspending console(s) (use no_console_suspend to debug)
11404 10:05:21.618000 <3>[ 46.411340] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11405 10:05:21.631390 <3>[ 46.411377] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11406 10:05:21.637869 <3>[ 46.411410] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11407 10:05:21.644746 <3>[ 46.411436] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11408 10:05:21.653880 <3>[ 46.411737] PM: Some devices failed to suspend, or early wake event detected
11409 10:05:21.657558 <6>[ 46.684427] OOM killer enabled.
11410 10:05:21.660585 <6>[ 46.687826] Restarting tasks ... done.
11411 10:05:21.667514 <5>[ 46.693496] random: crng reseeded on system resumption
11412 10:05:21.670633 <6>[ 46.700395] PM: suspend exit
11413 10:05:21.673797 rtcwake: write error
11414 10:05:21.682466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11415 10:05:21.683351 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11417 10:05:21.685862 rtcwake: assuming RTC uses UTC ...
11418 10:05:21.692285 rtcwake: wakeup from "mem" using rtc0 at Sat Jun 10 10:05:30 2023
11419 10:05:21.705083 <6>[ 46.731612] PM: suspend entry (deep)
11420 10:05:21.708284 <6>[ 46.735536] Filesystems sync: 0.000 seconds
11421 10:05:21.714745 <6>[ 46.740713] Freezing user space processes
11422 10:05:21.721354 <6>[ 46.746760] Freezing user space processes completed (elapsed 0.001 seconds)
11423 10:05:21.725307 <6>[ 46.753996] OOM killer disabled.
11424 10:05:21.731707 <6>[ 46.757479] Freezing remaining freezable tasks
11425 10:05:21.738457 <6>[ 46.763156] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11426 10:05:21.748548 <6>[ 46.770817] printk: Suspending console(s) (use no_console_suspend to debug)
11427 10:05:25.194154 <6>[ 48.203585] vpu: disabling
11428 10:05:25.197378 <6>[ 48.203684] vproc2: disabling
11429 10:05:25.200641 <6>[ 48.203723] vproc1: disabling
11430 10:05:25.204071 <6>[ 48.203761] vaud18: disabling
11431 10:05:25.207648 <6>[ 48.203944] vsram_others: disabling
11432 10:05:25.210977 <6>[ 48.204089] va09: disabling
11433 10:05:25.214017 <6>[ 48.204144] vsram_md: disabling
11434 10:05:25.217267 <6>[ 48.204239] Vgpu: disabling
11435 10:05:25.223868 <3>[ 49.995317] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11436 10:05:25.234150 <3>[ 49.995345] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11437 10:05:25.244351 <3>[ 49.995381] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11438 10:05:25.250237 <3>[ 49.995404] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11439 10:05:25.256771 <3>[ 49.995882] PM: Some devices failed to suspend, or early wake event detected
11440 10:05:25.260588 <6>[ 50.290277] OOM killer enabled.
11441 10:05:25.268697 <6>[ 50.293676] Restarting tasks ... done.
11442 10:05:25.271550 <5>[ 50.299682] random: crng reseeded on system resumption
11443 10:05:25.275461 <6>[ 50.306081] PM: suspend exit
11444 10:05:25.278517 rtcwake: write error
11445 10:05:25.287639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11446 10:05:25.288510 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11448 10:05:25.290696 rtcwake: assuming RTC uses UTC ...
11449 10:05:25.297294 rtcwake: wakeup from "mem" using rtc0 at Sat Jun 10 10:05:33 2023
11450 10:05:25.310680 <6>[ 50.337478] PM: suspend entry (deep)
11451 10:05:25.313969 <6>[ 50.341374] Filesystems sync: 0.000 seconds
11452 10:05:25.320455 <6>[ 50.346545] Freezing user space processes
11453 10:05:25.327134 <6>[ 50.352758] Freezing user space processes completed (elapsed 0.001 seconds)
11454 10:05:25.330345 <6>[ 50.360051] OOM killer disabled.
11455 10:05:25.337020 <6>[ 50.363534] Freezing remaining freezable tasks
11456 10:05:25.346781 <6>[ 50.369524] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11457 10:05:25.353502 <6>[ 50.377197] printk: Suspending console(s) (use no_console_suspend to debug)
11458 10:05:28.781704 <3>[ 53.579270] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11459 10:05:28.794773 <3>[ 53.579295] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11460 10:05:28.801483 <3>[ 53.579320] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11461 10:05:28.807702 <3>[ 53.579341] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11462 10:05:28.817776 <3>[ 53.579757] PM: Some devices failed to suspend, or early wake event detected
11463 10:05:28.821978 <6>[ 53.849003] OOM killer enabled.
11464 10:05:28.825288 <6>[ 53.852403] Restarting tasks ... done.
11465 10:05:28.831011 <5>[ 53.858141] random: crng reseeded on system resumption
11466 10:05:28.834210 <6>[ 53.864641] PM: suspend exit
11467 10:05:28.837752 rtcwake: write error
11468 10:05:28.846067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11469 10:05:28.846914 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11471 10:05:28.849049 rtcwake: assuming RTC uses UTC ...
11472 10:05:28.855565 rtcwake: wakeup from "mem" using rtc0 at Sat Jun 10 10:05:37 2023
11473 10:05:28.868914 <6>[ 53.895748] PM: suspend entry (deep)
11474 10:05:28.871810 <6>[ 53.899642] Filesystems sync: 0.000 seconds
11475 10:05:28.878086 <6>[ 53.904775] Freezing user space processes
11476 10:05:28.884862 <6>[ 53.910830] Freezing user space processes completed (elapsed 0.001 seconds)
11477 10:05:28.888351 <6>[ 53.918179] OOM killer disabled.
11478 10:05:28.894530 <6>[ 53.921666] Freezing remaining freezable tasks
11479 10:05:28.901275 <6>[ 53.927596] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11480 10:05:28.911765 <6>[ 53.935258] printk: Suspending console(s) (use no_console_suspend to debug)
11481 10:05:32.365037 <3>[ 57.163337] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11482 10:05:32.378335 <3>[ 57.163365] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11483 10:05:32.385288 <3>[ 57.163403] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11484 10:05:32.391634 <3>[ 57.163423] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11485 10:05:32.401389 <3>[ 57.163681] PM: Some devices failed to suspend, or early wake event detected
11486 10:05:32.404430 <6>[ 57.432987] OOM killer enabled.
11487 10:05:32.407883 <6>[ 57.436386] Restarting tasks ... done.
11488 10:05:32.414536 <5>[ 57.442092] random: crng reseeded on system resumption
11489 10:05:32.417898 <6>[ 57.448617] PM: suspend exit
11490 10:05:32.421190 rtcwake: write error
11491 10:05:32.429145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11492 10:05:32.430033 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11494 10:05:32.432135 rtcwake: assuming RTC uses UTC ...
11495 10:05:32.439200 rtcwake: wakeup from "freeze" using rtc0 at Sat Jun 10 10:05:40 2023
11496 10:05:32.453437 <6>[ 57.481290] PM: suspend entry (s2idle)
11497 10:05:32.457058 <6>[ 57.485401] Filesystems sync: 0.000 seconds
11498 10:05:32.463362 <6>[ 57.490643] Freezing user space processes
11499 10:05:32.470117 <6>[ 57.496607] Freezing user space processes completed (elapsed 0.001 seconds)
11500 10:05:32.473236 <6>[ 57.503835] OOM killer disabled.
11501 10:05:32.479668 <6>[ 57.507316] Freezing remaining freezable tasks
11502 10:05:32.489907 <6>[ 57.513399] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11503 10:05:32.496419 <6>[ 57.521080] printk: Suspending console(s) (use no_console_suspend to debug)
11504 10:05:35.952972 <3>[ 60.747264] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11505 10:05:35.963029 <3>[ 60.747287] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11506 10:05:35.972530 <3>[ 60.747313] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11507 10:05:35.979612 <3>[ 60.747335] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11508 10:05:35.989209 <3>[ 60.747586] PM: Some devices failed to suspend, or early wake event detected
11509 10:05:35.992479 <6>[ 61.020907] OOM killer enabled.
11510 10:05:35.995874 <6>[ 61.024308] Restarting tasks ... done.
11511 10:05:36.002339 <5>[ 61.029940] random: crng reseeded on system resumption
11512 10:05:36.005899 <6>[ 61.036602] PM: suspend exit
11513 10:05:36.009057 rtcwake: write error
11514 10:05:36.016540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11515 10:05:36.017304 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11517 10:05:36.019726 rtcwake: assuming RTC uses UTC ...
11518 10:05:36.026077 rtcwake: wakeup from "freeze" using rtc0 at Sat Jun 10 10:05:44 2023
11519 10:05:36.039219 <6>[ 61.067279] PM: suspend entry (s2idle)
11520 10:05:36.042533 <6>[ 61.071347] Filesystems sync: 0.000 seconds
11521 10:05:36.048986 <6>[ 61.076454] Freezing user space processes
11522 10:05:36.055641 <6>[ 61.082410] Freezing user space processes completed (elapsed 0.001 seconds)
11523 10:05:36.059010 <6>[ 61.089704] OOM killer disabled.
11524 10:05:36.065496 <6>[ 61.093195] Freezing remaining freezable tasks
11525 10:05:36.072280 <6>[ 61.099062] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11526 10:05:36.082175 <6>[ 61.106715] printk: Suspending console(s) (use no_console_suspend to debug)
11527 10:05:39.531938 <3>[ 64.331289] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11528 10:05:39.541929 <3>[ 64.331314] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11529 10:05:39.551942 <3>[ 64.331347] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11530 10:05:39.558887 <3>[ 64.331368] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11531 10:05:39.565289 <3>[ 64.331934] PM: Some devices failed to suspend, or early wake event detected
11532 10:05:39.571872 <6>[ 64.600915] OOM killer enabled.
11533 10:05:39.575217 <6>[ 64.604314] Restarting tasks ... done.
11534 10:05:39.581577 <5>[ 64.609998] random: crng reseeded on system resumption
11535 10:05:39.584764 <6>[ 64.616726] PM: suspend exit
11536 10:05:39.588148 rtcwake: write error
11537 10:05:39.595788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11538 10:05:39.596049 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11540 10:05:39.599200 rtcwake: assuming RTC uses UTC ...
11541 10:05:39.605897 rtcwake: wakeup from "freeze" using rtc0 at Sat Jun 10 10:05:48 2023
11542 10:05:39.618404 <6>[ 64.647649] PM: suspend entry (s2idle)
11543 10:05:39.622102 <6>[ 64.651808] Filesystems sync: 0.000 seconds
11544 10:05:39.628668 <6>[ 64.656966] Freezing user space processes
11545 10:05:39.634808 <6>[ 64.662920] Freezing user space processes completed (elapsed 0.001 seconds)
11546 10:05:39.638456 <6>[ 64.670204] OOM killer disabled.
11547 10:05:39.644745 <6>[ 64.673688] Freezing remaining freezable tasks
11548 10:05:39.651610 <6>[ 64.679638] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11549 10:05:39.661472 <6>[ 64.687296] printk: Suspending console(s) (use no_console_suspend to debug)
11550 10:05:43.118824 <3>[ 67.915316] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11551 10:05:43.129097 <3>[ 67.915341] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11552 10:05:43.139029 <3>[ 67.915374] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11553 10:05:43.145192 <3>[ 67.915396] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11554 10:05:43.155363 <3>[ 67.915682] PM: Some devices failed to suspend, or early wake event detected
11555 10:05:43.158501 <6>[ 68.188273] OOM killer enabled.
11556 10:05:43.161678 <6>[ 68.191672] Restarting tasks ... done.
11557 10:05:43.168430 <5>[ 68.197237] random: crng reseeded on system resumption
11558 10:05:43.172001 <6>[ 68.203809] PM: suspend exit
11559 10:05:43.175033 rtcwake: write error
11560 10:05:43.182543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11561 10:05:43.182811 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11563 10:05:43.185941 rtcwake: assuming RTC uses UTC ...
11564 10:05:43.192284 rtcwake: wakeup from "freeze" using rtc0 at Sat Jun 10 10:05:51 2023
11565 10:05:43.205360 <6>[ 68.234762] PM: suspend entry (s2idle)
11566 10:05:43.208732 <6>[ 68.238846] Filesystems sync: 0.000 seconds
11567 10:05:43.215296 <6>[ 68.244032] Freezing user space processes
11568 10:05:43.221480 <6>[ 68.250061] Freezing user space processes completed (elapsed 0.001 seconds)
11569 10:05:43.225074 <6>[ 68.257293] OOM killer disabled.
11570 10:05:43.231401 <6>[ 68.260776] Freezing remaining freezable tasks
11571 10:05:43.238334 <6>[ 68.266687] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11572 10:05:43.247818 <6>[ 68.274361] printk: Suspending console(s) (use no_console_suspend to debug)
11573 10:05:46.702718 <3>[ 71.499350] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11574 10:05:46.712897 <3>[ 71.499389] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11575 10:05:46.722821 <3>[ 71.499427] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11576 10:05:46.729692 <3>[ 71.499453] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11577 10:05:46.739472 <3>[ 71.499884] PM: Some devices failed to suspend, or early wake event detected
11578 10:05:46.742776 <6>[ 71.772420] OOM killer enabled.
11579 10:05:46.745964 <6>[ 71.775819] Restarting tasks ... done.
11580 10:05:46.752992 <5>[ 71.781524] random: crng reseeded on system resumption
11581 10:05:46.756555 <6>[ 71.788325] PM: suspend exit
11582 10:05:46.759334 rtcwake: write error
11583 10:05:46.766932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11584 10:05:46.767607 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11586 10:05:46.770362 rtcwake: assuming RTC uses UTC ...
11587 10:05:46.777432 rtcwake: wakeup from "freeze" using rtc0 at Sat Jun 10 10:05:55 2023
11588 10:05:46.790051 <6>[ 71.819476] PM: suspend entry (s2idle)
11589 10:05:46.793339 <6>[ 71.823539] Filesystems sync: 0.000 seconds
11590 10:05:46.799873 <6>[ 71.828743] Freezing user space processes
11591 10:05:46.806804 <6>[ 71.834769] Freezing user space processes completed (elapsed 0.001 seconds)
11592 10:05:46.809683 <6>[ 71.841999] OOM killer disabled.
11593 10:05:46.816568 <6>[ 71.845481] Freezing remaining freezable tasks
11594 10:05:46.822979 <6>[ 71.851062] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11595 10:05:46.833343 <6>[ 71.858717] printk: Suspending console(s) (use no_console_suspend to debug)
11596 10:05:50.283125 <3>[ 75.083328] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11597 10:05:50.292814 <3>[ 75.083380] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11598 10:05:50.302629 <3>[ 75.083451] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11599 10:05:50.309360 <3>[ 75.083519] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11600 10:05:50.319140 <3>[ 75.083815] PM: Some devices failed to suspend, or early wake event detected
11601 10:05:50.322416 <6>[ 75.352906] OOM killer enabled.
11602 10:05:50.325739 <6>[ 75.356306] Restarting tasks ... done.
11603 10:05:50.332626 <5>[ 75.362158] random: crng reseeded on system resumption
11604 10:05:50.335952 <6>[ 75.368675] PM: suspend exit
11605 10:05:50.339500 rtcwake: write error
11606 10:05:50.347250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11607 10:05:50.347957 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11609 10:05:50.350227 rtcwake: assuming RTC uses UTC ...
11610 10:05:50.357046 rtcwake: wakeup from "freeze" using rtc0 at Sat Jun 10 10:05:58 2023
11611 10:05:50.369658 <6>[ 75.400006] PM: suspend entry (s2idle)
11612 10:05:50.373130 <6>[ 75.404150] Filesystems sync: 0.000 seconds
11613 10:05:50.379823 <6>[ 75.409269] Freezing user space processes
11614 10:05:50.386542 <6>[ 75.415189] Freezing user space processes completed (elapsed 0.001 seconds)
11615 10:05:50.389737 <6>[ 75.422436] OOM killer disabled.
11616 10:05:50.397139 <6>[ 75.425921] Freezing remaining freezable tasks
11617 10:05:50.402971 <6>[ 75.431818] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11618 10:05:50.412769 <6>[ 75.439475] printk: Suspending console(s) (use no_console_suspend to debug)
11619 10:05:53.870624 <3>[ 78.667311] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11620 10:05:53.880153 <3>[ 78.667336] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11621 10:05:53.890256 <3>[ 78.667368] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11622 10:05:53.896835 <3>[ 78.667390] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11623 10:05:53.907097 <3>[ 78.667674] PM: Some devices failed to suspend, or early wake event detected
11624 10:05:53.909860 <6>[ 78.940889] OOM killer enabled.
11625 10:05:53.913328 <6>[ 78.944289] Restarting tasks ... done.
11626 10:05:53.919987 <5>[ 78.949911] random: crng reseeded on system resumption
11627 10:05:53.923486 <6>[ 78.956631] PM: suspend exit
11628 10:05:53.927088 rtcwake: write error
11629 10:05:53.934963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11630 10:05:53.935223 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11632 10:05:53.937556 rtcwake: assuming RTC uses UTC ...
11633 10:05:53.944164 rtcwake: wakeup from "freeze" using rtc0 at Sat Jun 10 10:06:02 2023
11634 10:05:53.957443 <6>[ 78.988103] PM: suspend entry (s2idle)
11635 10:05:53.960564 <6>[ 78.992181] Filesystems sync: 0.000 seconds
11636 10:05:53.967128 <6>[ 78.997331] Freezing user space processes
11637 10:05:53.973793 <6>[ 79.003173] Freezing user space processes completed (elapsed 0.001 seconds)
11638 10:05:53.977341 <6>[ 79.010395] OOM killer disabled.
11639 10:05:53.983526 <6>[ 79.013888] Freezing remaining freezable tasks
11640 10:05:53.990388 <6>[ 79.019827] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11641 10:05:54.000063 <6>[ 79.027482] printk: Suspending console(s) (use no_console_suspend to debug)
11642 10:05:57.449843 <3>[ 82.251290] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11643 10:05:57.460114 <3>[ 82.251316] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11644 10:05:57.470148 <3>[ 82.251349] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11645 10:05:57.476317 <3>[ 82.251370] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11646 10:05:57.486312 <3>[ 82.251666] PM: Some devices failed to suspend, or early wake event detected
11647 10:05:57.489375 <6>[ 82.520907] OOM killer enabled.
11648 10:05:57.493102 <6>[ 82.524307] Restarting tasks ... done.
11649 10:05:57.499364 <5>[ 82.530087] random: crng reseeded on system resumption
11650 10:05:57.502943 <6>[ 82.536463] PM: suspend exit
11651 10:05:57.505984 rtcwake: write error
11652 10:05:57.513331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11653 10:05:57.513592 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11655 10:05:57.516444 rtcwake: assuming RTC uses UTC ...
11656 10:05:57.522966 rtcwake: wakeup from "freeze" using rtc0 at Sat Jun 10 10:06:06 2023
11657 10:05:57.536133 <6>[ 82.567286] PM: suspend entry (s2idle)
11658 10:05:57.539579 <6>[ 82.571371] Filesystems sync: 0.000 seconds
11659 10:05:57.545790 <6>[ 82.576554] Freezing user space processes
11660 10:05:57.552615 <6>[ 82.582528] Freezing user space processes completed (elapsed 0.001 seconds)
11661 10:05:57.555801 <6>[ 82.589823] OOM killer disabled.
11662 10:05:57.562410 <6>[ 82.593307] Freezing remaining freezable tasks
11663 10:05:57.569164 <6>[ 82.599094] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11664 10:05:57.579309 <6>[ 82.606751] printk: Suspending console(s) (use no_console_suspend to debug)
11665 10:06:01.037144 <3>[ 85.835320] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11666 10:06:01.047048 <3>[ 85.835346] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11667 10:06:01.056796 <3>[ 85.835379] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11668 10:06:01.063286 <3>[ 85.835402] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11669 10:06:01.070205 <3>[ 85.835692] PM: Some devices failed to suspend, or early wake event detected
11670 10:06:01.076384 <6>[ 86.108248] OOM killer enabled.
11671 10:06:01.080181 <6>[ 86.111646] Restarting tasks ... done.
11672 10:06:01.086354 <5>[ 86.117357] random: crng reseeded on system resumption
11673 10:06:01.090060 <6>[ 86.124543] PM: suspend exit
11674 10:06:01.093432 rtcwake: write error
11675 10:06:01.101260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11676 10:06:01.101548 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11678 10:06:01.104471 rtcwake: assuming RTC uses UTC ...
11679 10:06:01.111217 rtcwake: wakeup from "freeze" using rtc0 at Sat Jun 10 10:06:09 2023
11680 10:06:01.123405 <6>[ 86.155204] PM: suspend entry (s2idle)
11681 10:06:01.127225 <6>[ 86.159287] Filesystems sync: 0.000 seconds
11682 10:06:01.133385 <6>[ 86.164499] Freezing user space processes
11683 10:06:01.139995 <6>[ 86.170570] Freezing user space processes completed (elapsed 0.001 seconds)
11684 10:06:01.143587 <6>[ 86.177799] OOM killer disabled.
11685 10:06:01.150166 <6>[ 86.181281] Freezing remaining freezable tasks
11686 10:06:01.159623 <6>[ 86.187149] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11687 10:06:01.166664 <6>[ 86.194807] printk: Suspending console(s) (use no_console_suspend to debug)
11688 10:06:04.617302 <3>[ 89.419301] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11689 10:06:04.627139 <3>[ 89.419324] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11690 10:06:04.636916 <3>[ 89.419350] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11691 10:06:04.643483 <3>[ 89.419375] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11692 10:06:04.653587 <3>[ 89.419733] PM: Some devices failed to suspend, or early wake event detected
11693 10:06:04.656757 <6>[ 89.689116] OOM killer enabled.
11694 10:06:04.660653 <6>[ 89.692517] Restarting tasks ... done.
11695 10:06:04.666796 <5>[ 89.698720] random: crng reseeded on system resumption
11696 10:06:04.671176 <6>[ 89.705968] PM: suspend exit
11697 10:06:04.673887 rtcwake: write error
11698 10:06:04.682355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11699 10:06:04.682661 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11701 10:06:04.685076 rtcwake: assuming RTC uses UTC ...
11702 10:06:04.691696 rtcwake: wakeup from "freeze" using rtc0 at Sat Jun 10 10:06:13 2023
11703 10:06:04.705085 <6>[ 89.736836] PM: suspend entry (s2idle)
11704 10:06:04.708382 <6>[ 89.740921] Filesystems sync: 0.000 seconds
11705 10:06:04.714494 <6>[ 89.746105] Freezing user space processes
11706 10:06:04.721393 <6>[ 89.751984] Freezing user space processes completed (elapsed 0.001 seconds)
11707 10:06:04.724484 <6>[ 89.759208] OOM killer disabled.
11708 10:06:04.731300 <6>[ 89.762688] Freezing remaining freezable tasks
11709 10:06:04.737952 <6>[ 89.768596] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11710 10:06:04.747729 <6>[ 89.776255] printk: Suspending console(s) (use no_console_suspend to debug)
11711 10:06:08.204473 <3>[ 93.003292] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11712 10:06:08.214235 <3>[ 93.003319] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11713 10:06:08.224230 <3>[ 93.003351] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11714 10:06:08.230834 <3>[ 93.003371] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11715 10:06:08.237993 <3>[ 93.003791] PM: Some devices failed to suspend, or early wake event detected
11716 10:06:08.244581 <6>[ 93.276485] OOM killer enabled.
11717 10:06:08.247166 <6>[ 93.279883] Restarting tasks ... done.
11718 10:06:08.253898 <5>[ 93.285584] random: crng reseeded on system resumption
11719 10:06:08.257542 <6>[ 93.292307] PM: suspend exit
11720 10:06:08.260577 rtcwake: write error
11721 10:06:08.267746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11722 10:06:08.268041 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11724 10:06:08.271362 + set +x
11725 10:06:08.274877 <LAVA_SIGNAL_ENDRUN 0_sleep 10670675_1.5.2.3.1>
11726 10:06:08.274966 <LAVA_TEST_RUNNER EXIT>
11727 10:06:08.275223 Received signal: <ENDRUN> 0_sleep 10670675_1.5.2.3.1
11728 10:06:08.275316 Ending use of test pattern.
11729 10:06:08.275388 Ending test lava.0_sleep (10670675_1.5.2.3.1), duration 71.53
11731 10:06:08.275834 ok: lava_test_shell seems to have completed
11732 10:06:08.276043 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11733 10:06:08.276152 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11734 10:06:08.276250 end: 3 lava-test-retry (duration 00:01:12) [common]
11735 10:06:08.276351 start: 4 finalize (timeout 00:05:05) [common]
11736 10:06:08.276450 start: 4.1 power-off (timeout 00:00:30) [common]
11737 10:06:08.276732 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11738 10:06:08.351885 >> Command sent successfully.
11739 10:06:08.354337 Returned 0 in 0 seconds
11740 10:06:08.454782 end: 4.1 power-off (duration 00:00:00) [common]
11742 10:06:08.455198 start: 4.2 read-feedback (timeout 00:05:04) [common]
11743 10:06:08.455483 Listened to connection for namespace 'common' for up to 1s
11744 10:06:08.455779 Listened to connection for namespace 'common' for up to 1s
11745 10:06:09.456423 Finalising connection for namespace 'common'
11746 10:06:09.456621 Disconnecting from shell: Finalise
11747 10:06:09.456725 / #
11748 10:06:09.557094 end: 4.2 read-feedback (duration 00:00:01) [common]
11749 10:06:09.557297 end: 4 finalize (duration 00:00:01) [common]
11750 10:06:09.557434 Cleaning after the job
11751 10:06:09.557547 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670675/tftp-deploy-2_f07u3u/ramdisk
11752 10:06:09.567866 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670675/tftp-deploy-2_f07u3u/kernel
11753 10:06:09.585164 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670675/tftp-deploy-2_f07u3u/dtb
11754 10:06:09.585414 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670675/tftp-deploy-2_f07u3u/modules
11755 10:06:09.590839 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10670675
11756 10:06:09.729265 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10670675
11757 10:06:09.729450 Job finished correctly