Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 31
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 65
- Errors: 1
1 10:06:35.293124 lava-dispatcher, installed at version: 2023.05.1
2 10:06:35.293328 start: 0 validate
3 10:06:35.293479 Start time: 2023-06-10 10:06:35.293472+00:00 (UTC)
4 10:06:35.293601 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:06:35.293730 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 10:06:35.557210 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:06:35.557401 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:06:35.822907 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:06:35.823081 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:06:36.089527 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:06:36.089694 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:06:36.348370 validate duration: 1.05
14 10:06:36.348627 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:06:36.348725 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:06:36.348809 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:06:36.348932 Not decompressing ramdisk as can be used compressed.
18 10:06:36.349016 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
19 10:06:36.349080 saving as /var/lib/lava/dispatcher/tmp/10670703/tftp-deploy-huopdwre/ramdisk/rootfs.cpio.gz
20 10:06:36.349140 total size: 27151647 (25MB)
21 10:06:36.350139 progress 0% (0MB)
22 10:06:36.357126 progress 5% (1MB)
23 10:06:36.363932 progress 10% (2MB)
24 10:06:36.370901 progress 15% (3MB)
25 10:06:36.377622 progress 20% (5MB)
26 10:06:36.384544 progress 25% (6MB)
27 10:06:36.391329 progress 30% (7MB)
28 10:06:36.398275 progress 35% (9MB)
29 10:06:36.405065 progress 40% (10MB)
30 10:06:36.411824 progress 45% (11MB)
31 10:06:36.418692 progress 50% (12MB)
32 10:06:36.425407 progress 55% (14MB)
33 10:06:36.432264 progress 60% (15MB)
34 10:06:36.439001 progress 65% (16MB)
35 10:06:36.445971 progress 70% (18MB)
36 10:06:36.452757 progress 75% (19MB)
37 10:06:36.459519 progress 80% (20MB)
38 10:06:36.466412 progress 85% (22MB)
39 10:06:36.473174 progress 90% (23MB)
40 10:06:36.480011 progress 95% (24MB)
41 10:06:36.486670 progress 100% (25MB)
42 10:06:36.486899 25MB downloaded in 0.14s (187.97MB/s)
43 10:06:36.487054 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:06:36.487292 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:06:36.487380 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:06:36.487463 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:06:36.487627 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:06:36.487700 saving as /var/lib/lava/dispatcher/tmp/10670703/tftp-deploy-huopdwre/kernel/Image
50 10:06:36.487761 total size: 45746688 (43MB)
51 10:06:36.487821 No compression specified
52 10:06:36.488878 progress 0% (0MB)
53 10:06:36.500342 progress 5% (2MB)
54 10:06:36.511906 progress 10% (4MB)
55 10:06:36.523416 progress 15% (6MB)
56 10:06:36.534847 progress 20% (8MB)
57 10:06:36.546366 progress 25% (10MB)
58 10:06:36.557707 progress 30% (13MB)
59 10:06:36.569182 progress 35% (15MB)
60 10:06:36.580753 progress 40% (17MB)
61 10:06:36.592250 progress 45% (19MB)
62 10:06:36.603760 progress 50% (21MB)
63 10:06:36.615087 progress 55% (24MB)
64 10:06:36.626580 progress 60% (26MB)
65 10:06:36.638032 progress 65% (28MB)
66 10:06:36.649528 progress 70% (30MB)
67 10:06:36.661015 progress 75% (32MB)
68 10:06:36.672373 progress 80% (34MB)
69 10:06:36.683867 progress 85% (37MB)
70 10:06:36.695377 progress 90% (39MB)
71 10:06:36.706712 progress 95% (41MB)
72 10:06:36.717991 progress 100% (43MB)
73 10:06:36.718110 43MB downloaded in 0.23s (189.40MB/s)
74 10:06:36.718255 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:06:36.718483 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:06:36.718569 start: 1.3 download-retry (timeout 00:10:00) [common]
78 10:06:36.718655 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 10:06:36.718792 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:06:36.718897 saving as /var/lib/lava/dispatcher/tmp/10670703/tftp-deploy-huopdwre/dtb/mt8192-asurada-spherion-r0.dtb
81 10:06:36.718959 total size: 46924 (0MB)
82 10:06:36.719019 No compression specified
83 10:06:36.720094 progress 69% (0MB)
84 10:06:36.720361 progress 100% (0MB)
85 10:06:36.720512 0MB downloaded in 0.00s (28.87MB/s)
86 10:06:36.720631 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:06:36.720850 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:06:36.720934 start: 1.4 download-retry (timeout 00:10:00) [common]
90 10:06:36.721015 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 10:06:36.721122 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:06:36.721190 saving as /var/lib/lava/dispatcher/tmp/10670703/tftp-deploy-huopdwre/modules/modules.tar
93 10:06:36.721251 total size: 8540248 (8MB)
94 10:06:36.721312 Using unxz to decompress xz
95 10:06:36.724937 progress 0% (0MB)
96 10:06:36.747291 progress 5% (0MB)
97 10:06:36.772080 progress 10% (0MB)
98 10:06:36.796066 progress 15% (1MB)
99 10:06:36.821184 progress 20% (1MB)
100 10:06:36.845786 progress 25% (2MB)
101 10:06:36.868750 progress 30% (2MB)
102 10:06:36.894267 progress 35% (2MB)
103 10:06:36.918609 progress 40% (3MB)
104 10:06:36.942154 progress 45% (3MB)
105 10:06:36.969472 progress 50% (4MB)
106 10:06:36.994231 progress 55% (4MB)
107 10:06:37.019665 progress 60% (4MB)
108 10:06:37.045092 progress 65% (5MB)
109 10:06:37.070127 progress 70% (5MB)
110 10:06:37.094149 progress 75% (6MB)
111 10:06:37.117289 progress 80% (6MB)
112 10:06:37.141144 progress 85% (6MB)
113 10:06:37.170252 progress 90% (7MB)
114 10:06:37.195689 progress 95% (7MB)
115 10:06:37.220543 progress 100% (8MB)
116 10:06:37.225840 8MB downloaded in 0.50s (16.14MB/s)
117 10:06:37.226143 end: 1.4.1 http-download (duration 00:00:01) [common]
119 10:06:37.226407 end: 1.4 download-retry (duration 00:00:01) [common]
120 10:06:37.226500 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 10:06:37.226595 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 10:06:37.226675 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:06:37.226759 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 10:06:37.227018 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43
125 10:06:37.227144 makedir: /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin
126 10:06:37.227247 makedir: /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/tests
127 10:06:37.227340 makedir: /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/results
128 10:06:37.227452 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-add-keys
129 10:06:37.227594 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-add-sources
130 10:06:37.227722 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-background-process-start
131 10:06:37.227850 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-background-process-stop
132 10:06:37.227971 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-common-functions
133 10:06:37.228090 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-echo-ipv4
134 10:06:37.228211 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-install-packages
135 10:06:37.228330 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-installed-packages
136 10:06:37.228448 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-os-build
137 10:06:37.228568 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-probe-channel
138 10:06:37.228687 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-probe-ip
139 10:06:37.228807 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-target-ip
140 10:06:37.228925 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-target-mac
141 10:06:37.229042 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-target-storage
142 10:06:37.229164 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-test-case
143 10:06:37.229283 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-test-event
144 10:06:37.229400 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-test-feedback
145 10:06:37.229518 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-test-raise
146 10:06:37.229638 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-test-reference
147 10:06:37.229758 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-test-runner
148 10:06:37.229876 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-test-set
149 10:06:37.229998 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-test-shell
150 10:06:37.230119 Updating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-install-packages (oe)
151 10:06:37.230267 Updating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/bin/lava-installed-packages (oe)
152 10:06:37.230386 Creating /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/environment
153 10:06:37.230526 LAVA metadata
154 10:06:37.230599 - LAVA_JOB_ID=10670703
155 10:06:37.230665 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:06:37.230783 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 10:06:37.230877 skipped lava-vland-overlay
158 10:06:37.230952 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:06:37.231035 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 10:06:37.231095 skipped lava-multinode-overlay
161 10:06:37.231169 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:06:37.231254 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 10:06:37.231326 Loading test definitions
164 10:06:37.231416 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 10:06:37.231489 Using /lava-10670703 at stage 0
166 10:06:37.231775 uuid=10670703_1.5.2.3.1 testdef=None
167 10:06:37.231864 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 10:06:37.231950 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 10:06:37.232447 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 10:06:37.232665 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 10:06:37.233252 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 10:06:37.233484 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 10:06:37.234093 runner path: /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/0/tests/0_v4l2-compliance-uvc test_uuid 10670703_1.5.2.3.1
176 10:06:37.234246 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 10:06:37.234452 Creating lava-test-runner.conf files
179 10:06:37.234516 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10670703/lava-overlay-cnvcgy43/lava-10670703/0 for stage 0
180 10:06:37.234602 - 0_v4l2-compliance-uvc
181 10:06:37.234697 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 10:06:37.234784 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 10:06:37.241252 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 10:06:37.241355 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 10:06:37.241439 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 10:06:37.241523 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 10:06:37.241612 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 10:06:37.968404 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 10:06:37.968771 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 10:06:37.968909 extracting modules file /var/lib/lava/dispatcher/tmp/10670703/tftp-deploy-huopdwre/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670703/extract-overlay-ramdisk-2ssusc_e/ramdisk
191 10:06:38.204370 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 10:06:38.204536 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 10:06:38.204630 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670703/compress-overlay-ualt03w0/overlay-1.5.2.4.tar.gz to ramdisk
194 10:06:38.204702 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670703/compress-overlay-ualt03w0/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10670703/extract-overlay-ramdisk-2ssusc_e/ramdisk
195 10:06:38.212644 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 10:06:38.212762 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 10:06:38.212854 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 10:06:38.212941 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 10:06:38.213036 Building ramdisk /var/lib/lava/dispatcher/tmp/10670703/extract-overlay-ramdisk-2ssusc_e/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10670703/extract-overlay-ramdisk-2ssusc_e/ramdisk
200 10:06:38.873856 >> 230341 blocks
201 10:06:42.800443 rename /var/lib/lava/dispatcher/tmp/10670703/extract-overlay-ramdisk-2ssusc_e/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10670703/tftp-deploy-huopdwre/ramdisk/ramdisk.cpio.gz
202 10:06:42.800870 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 10:06:42.800990 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 10:06:42.801090 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 10:06:42.801199 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10670703/tftp-deploy-huopdwre/kernel/Image'
206 10:06:54.108807 Returned 0 in 11 seconds
207 10:06:54.209735 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10670703/tftp-deploy-huopdwre/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10670703/tftp-deploy-huopdwre/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10670703/tftp-deploy-huopdwre/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10670703/tftp-deploy-huopdwre/kernel/image.itb
208 10:06:55.022647 output: FIT description: Kernel Image image with one or more FDT blobs
209 10:06:55.023037 output: Created: Sat Jun 10 11:06:54 2023
210 10:06:55.023114 output: Image 0 (kernel-1)
211 10:06:55.023218 output: Description:
212 10:06:55.023339 output: Created: Sat Jun 10 11:06:54 2023
213 10:06:55.023398 output: Type: Kernel Image
214 10:06:55.023456 output: Compression: lzma compressed
215 10:06:55.023511 output: Data Size: 10087317 Bytes = 9850.90 KiB = 9.62 MiB
216 10:06:55.023566 output: Architecture: AArch64
217 10:06:55.023620 output: OS: Linux
218 10:06:55.023676 output: Load Address: 0x00000000
219 10:06:55.023731 output: Entry Point: 0x00000000
220 10:06:55.023785 output: Hash algo: crc32
221 10:06:55.023839 output: Hash value: c9e456fd
222 10:06:55.023892 output: Image 1 (fdt-1)
223 10:06:55.023944 output: Description: mt8192-asurada-spherion-r0
224 10:06:55.023995 output: Created: Sat Jun 10 11:06:54 2023
225 10:06:55.024047 output: Type: Flat Device Tree
226 10:06:55.024099 output: Compression: uncompressed
227 10:06:55.024150 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 10:06:55.024201 output: Architecture: AArch64
229 10:06:55.024252 output: Hash algo: crc32
230 10:06:55.024304 output: Hash value: 1df858fa
231 10:06:55.024354 output: Image 2 (ramdisk-1)
232 10:06:55.024405 output: Description: unavailable
233 10:06:55.024455 output: Created: Sat Jun 10 11:06:54 2023
234 10:06:55.024506 output: Type: RAMDisk Image
235 10:06:55.024557 output: Compression: Unknown Compression
236 10:06:55.024608 output: Data Size: 40129633 Bytes = 39189.09 KiB = 38.27 MiB
237 10:06:55.024660 output: Architecture: AArch64
238 10:06:55.024711 output: OS: Linux
239 10:06:55.024762 output: Load Address: unavailable
240 10:06:55.024812 output: Entry Point: unavailable
241 10:06:55.024863 output: Hash algo: crc32
242 10:06:55.024913 output: Hash value: 555b3179
243 10:06:55.024963 output: Default Configuration: 'conf-1'
244 10:06:55.025014 output: Configuration 0 (conf-1)
245 10:06:55.025065 output: Description: mt8192-asurada-spherion-r0
246 10:06:55.025115 output: Kernel: kernel-1
247 10:06:55.025166 output: Init Ramdisk: ramdisk-1
248 10:06:55.025221 output: FDT: fdt-1
249 10:06:55.025302 output: Loadables: kernel-1
250 10:06:55.025354 output:
251 10:06:55.025550 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
252 10:06:55.025645 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
253 10:06:55.025746 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 10:06:55.025834 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 10:06:55.025906 No LXC device requested
256 10:06:55.025982 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 10:06:55.026063 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 10:06:55.026136 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 10:06:55.026204 Checking files for TFTP limit of 4294967296 bytes.
260 10:06:55.026684 end: 1 tftp-deploy (duration 00:00:19) [common]
261 10:06:55.026785 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 10:06:55.026916 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 10:06:55.027034 substitutions:
264 10:06:55.027100 - {DTB}: 10670703/tftp-deploy-huopdwre/dtb/mt8192-asurada-spherion-r0.dtb
265 10:06:55.027161 - {INITRD}: 10670703/tftp-deploy-huopdwre/ramdisk/ramdisk.cpio.gz
266 10:06:55.027225 - {KERNEL}: 10670703/tftp-deploy-huopdwre/kernel/Image
267 10:06:55.027372 - {LAVA_MAC}: None
268 10:06:55.027447 - {PRESEED_CONFIG}: None
269 10:06:55.027570 - {PRESEED_LOCAL}: None
270 10:06:55.027626 - {RAMDISK}: 10670703/tftp-deploy-huopdwre/ramdisk/ramdisk.cpio.gz
271 10:06:55.027681 - {ROOT_PART}: None
272 10:06:55.027736 - {ROOT}: None
273 10:06:55.027790 - {SERVER_IP}: 192.168.201.1
274 10:06:55.027844 - {TEE}: None
275 10:06:55.027897 Parsed boot commands:
276 10:06:55.027951 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 10:06:55.028123 Parsed boot commands: tftpboot 192.168.201.1 10670703/tftp-deploy-huopdwre/kernel/image.itb 10670703/tftp-deploy-huopdwre/kernel/cmdline
278 10:06:55.028210 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 10:06:55.028294 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 10:06:55.028382 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 10:06:55.028462 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 10:06:55.028531 Not connected, no need to disconnect.
283 10:06:55.028602 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 10:06:55.028681 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 10:06:55.028744 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
286 10:06:55.032056 Setting prompt string to ['lava-test: # ']
287 10:06:55.032385 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 10:06:55.032491 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 10:06:55.032583 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 10:06:55.032673 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 10:06:55.032855 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 10:07:00.173254 >> Command sent successfully.
293 10:07:00.182381 Returned 0 in 5 seconds
294 10:07:00.283747 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 10:07:00.286703 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 10:07:00.287373 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 10:07:00.287884 Setting prompt string to 'Starting depthcharge on Spherion...'
299 10:07:00.288302 Changing prompt to 'Starting depthcharge on Spherion...'
300 10:07:00.288746 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 10:07:00.290022 [Enter `^Ec?' for help]
302 10:07:00.448285
303 10:07:00.448819
304 10:07:00.449174 F0: 102B 0000
305 10:07:00.449492
306 10:07:00.449845 F3: 1001 0000 [0200]
307 10:07:00.451494
308 10:07:00.451974 F3: 1001 0000
309 10:07:00.452345
310 10:07:00.452662 F7: 102D 0000
311 10:07:00.452967
312 10:07:00.454959 F1: 0000 0000
313 10:07:00.455440
314 10:07:00.455780 V0: 0000 0000 [0001]
315 10:07:00.456110
316 10:07:00.458198 00: 0007 8000
317 10:07:00.458638
318 10:07:00.459035 01: 0000 0000
319 10:07:00.459370
320 10:07:00.461433 BP: 0C00 0209 [0000]
321 10:07:00.461880
322 10:07:00.462236 G0: 1182 0000
323 10:07:00.462552
324 10:07:00.464752 EC: 0000 0021 [4000]
325 10:07:00.465170
326 10:07:00.465507 S7: 0000 0000 [0000]
327 10:07:00.465854
328 10:07:00.468943 CC: 0000 0000 [0001]
329 10:07:00.469363
330 10:07:00.469731 T0: 0000 0040 [010F]
331 10:07:00.470071
332 10:07:00.470375 Jump to BL
333 10:07:00.470671
334 10:07:00.495767
335 10:07:00.496242
336 10:07:00.496622
337 10:07:00.502787 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 10:07:00.506426 ARM64: Exception handlers installed.
339 10:07:00.510331 ARM64: Testing exception
340 10:07:00.513230 ARM64: Done test exception
341 10:07:00.520322 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 10:07:00.531177 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 10:07:00.537100 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 10:07:00.546898 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 10:07:00.553813 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 10:07:00.560573 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 10:07:00.572219 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 10:07:00.578802 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 10:07:00.598182 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 10:07:00.601142 WDT: Last reset was cold boot
351 10:07:00.604552 SPI1(PAD0) initialized at 2873684 Hz
352 10:07:00.607911 SPI5(PAD0) initialized at 992727 Hz
353 10:07:00.611511 VBOOT: Loading verstage.
354 10:07:00.618135 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 10:07:00.621104 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 10:07:00.624600 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 10:07:00.628075 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 10:07:00.635237 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 10:07:00.642114 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 10:07:00.652749 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 10:07:00.653189
362 10:07:00.653526
363 10:07:00.663121 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 10:07:00.666288 ARM64: Exception handlers installed.
365 10:07:00.669452 ARM64: Testing exception
366 10:07:00.669876 ARM64: Done test exception
367 10:07:00.676882 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 10:07:00.680072 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 10:07:00.694032 Probing TPM: . done!
370 10:07:00.694453 TPM ready after 0 ms
371 10:07:00.700676 Connected to device vid:did:rid of 1ae0:0028:00
372 10:07:00.711261 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 10:07:00.711828 Initialized TPM device CR50 revision 0
374 10:07:00.761720 tlcl_send_startup: Startup return code is 0
375 10:07:00.762161 TPM: setup succeeded
376 10:07:00.773192 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 10:07:00.782068 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 10:07:00.793526 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 10:07:00.804321 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 10:07:00.807633 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 10:07:00.811526 in-header: 03 07 00 00 08 00 00 00
382 10:07:00.814991 in-data: aa e4 47 04 13 02 00 00
383 10:07:00.815532 Chrome EC: UHEPI supported
384 10:07:00.821746 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 10:07:00.825950 in-header: 03 9d 00 00 08 00 00 00
386 10:07:00.829444 in-data: 10 20 20 08 00 00 00 00
387 10:07:00.829866 Phase 1
388 10:07:00.833019 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 10:07:00.840149 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 10:07:00.847883 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 10:07:00.848310 Recovery requested (1009000e)
392 10:07:00.857006 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 10:07:00.861839 tlcl_extend: response is 0
394 10:07:00.870325 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 10:07:00.875558 tlcl_extend: response is 0
396 10:07:00.881961 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 10:07:00.903375 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 10:07:00.910707 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 10:07:00.911178
400 10:07:00.911682
401 10:07:00.921354 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 10:07:00.924625 ARM64: Exception handlers installed.
403 10:07:00.925099 ARM64: Testing exception
404 10:07:00.928178 ARM64: Done test exception
405 10:07:00.948771 pmic_efuse_setting: Set efuses in 11 msecs
406 10:07:00.951557 pmwrap_interface_init: Select PMIF_VLD_RDY
407 10:07:00.958987 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 10:07:00.962637 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 10:07:00.966440 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 10:07:00.973816 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 10:07:00.977504 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 10:07:00.981148 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 10:07:00.988064 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 10:07:00.991741 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 10:07:00.994935 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 10:07:01.001404 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 10:07:01.005062 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 10:07:01.008196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 10:07:01.015205 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 10:07:01.021205 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 10:07:01.024524 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 10:07:01.031172 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 10:07:01.037953 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 10:07:01.044675 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 10:07:01.048347 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 10:07:01.055325 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 10:07:01.059515 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 10:07:01.066325 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 10:07:01.069311 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 10:07:01.076790 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 10:07:01.080380 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 10:07:01.086724 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 10:07:01.094673 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 10:07:01.097971 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 10:07:01.101166 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 10:07:01.108030 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 10:07:01.111230 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 10:07:01.118994 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 10:07:01.122748 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 10:07:01.126484 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 10:07:01.130452 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 10:07:01.137460 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 10:07:01.140875 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 10:07:01.147887 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 10:07:01.150885 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 10:07:01.154401 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 10:07:01.160879 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 10:07:01.164364 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 10:07:01.167476 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 10:07:01.174115 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 10:07:01.177060 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 10:07:01.184326 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 10:07:01.187193 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 10:07:01.190705 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 10:07:01.193710 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 10:07:01.200323 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 10:07:01.203529 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 10:07:01.209957 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 10:07:01.220068 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 10:07:01.223356 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 10:07:01.233390 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 10:07:01.240233 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 10:07:01.247071 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 10:07:01.250170 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 10:07:01.253451 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 10:07:01.260652 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0xd
467 10:07:01.267276 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 10:07:01.270632 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 10:07:01.274239 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 10:07:01.285589 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 10:07:01.289050 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 10:07:01.295361 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 10:07:01.298592 [RTC]rtc_boot_common,220: irqsta=1, bbpu=81, con=486
474 10:07:01.301870 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 10:07:01.305136 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 10:07:01.308829 ADC[4]: Raw value=896300 ID=7
477 10:07:01.312032 ADC[3]: Raw value=213070 ID=1
478 10:07:01.315249 RAM Code: 0x71
479 10:07:01.318488 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 10:07:01.322227 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 10:07:01.332480 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 10:07:01.339248 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 10:07:01.342355 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 10:07:01.345795 in-header: 03 07 00 00 08 00 00 00
485 10:07:01.349617 in-data: aa e4 47 04 13 02 00 00
486 10:07:01.352540 Chrome EC: UHEPI supported
487 10:07:01.356031 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 10:07:01.360452 in-header: 03 d5 00 00 08 00 00 00
489 10:07:01.364194 in-data: 98 20 60 08 00 00 00 00
490 10:07:01.367309 MRC: failed to locate region type 0.
491 10:07:01.375068 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 10:07:01.378273 DRAM-K: Running full calibration
493 10:07:01.385132 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 10:07:01.385748 header.status = 0x0
495 10:07:01.388663 header.version = 0x6 (expected: 0x6)
496 10:07:01.391379 header.size = 0xd00 (expected: 0xd00)
497 10:07:01.395386 header.flags = 0x0
498 10:07:01.399029 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 10:07:01.417675 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
500 10:07:01.424149 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 10:07:01.427253 dram_init: ddr_geometry: 2
502 10:07:01.430914 [EMI] MDL number = 2
503 10:07:01.431339 [EMI] Get MDL freq = 0
504 10:07:01.434033 dram_init: ddr_type: 0
505 10:07:01.434499 is_discrete_lpddr4: 1
506 10:07:01.437717 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 10:07:01.438301
508 10:07:01.440722
509 10:07:01.441137 [Bian_co] ETT version 0.0.0.1
510 10:07:01.447064 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 10:07:01.447507
512 10:07:01.450439 dramc_set_vcore_voltage set vcore to 650000
513 10:07:01.453982 Read voltage for 800, 4
514 10:07:01.454422 Vio18 = 0
515 10:07:01.454892 Vcore = 650000
516 10:07:01.457332 Vdram = 0
517 10:07:01.457770 Vddq = 0
518 10:07:01.458212 Vmddr = 0
519 10:07:01.460369 dram_init: config_dvfs: 1
520 10:07:01.463870 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 10:07:01.470704 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 10:07:01.473829 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 10:07:01.477342 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 10:07:01.480943 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 10:07:01.483691 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 10:07:01.487335 MEM_TYPE=3, freq_sel=18
527 10:07:01.490290 sv_algorithm_assistance_LP4_1600
528 10:07:01.493596 ============ PULL DRAM RESETB DOWN ============
529 10:07:01.500261 ========== PULL DRAM RESETB DOWN end =========
530 10:07:01.503590 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 10:07:01.507394 ===================================
532 10:07:01.510760 LPDDR4 DRAM CONFIGURATION
533 10:07:01.513813 ===================================
534 10:07:01.514239 EX_ROW_EN[0] = 0x0
535 10:07:01.516924 EX_ROW_EN[1] = 0x0
536 10:07:01.517349 LP4Y_EN = 0x0
537 10:07:01.520085 WORK_FSP = 0x0
538 10:07:01.520511 WL = 0x2
539 10:07:01.523806 RL = 0x2
540 10:07:01.524229 BL = 0x2
541 10:07:01.526961 RPST = 0x0
542 10:07:01.530129 RD_PRE = 0x0
543 10:07:01.530551 WR_PRE = 0x1
544 10:07:01.533360 WR_PST = 0x0
545 10:07:01.533798 DBI_WR = 0x0
546 10:07:01.536875 DBI_RD = 0x0
547 10:07:01.537494 OTF = 0x1
548 10:07:01.539871 ===================================
549 10:07:01.544299 ===================================
550 10:07:01.544718 ANA top config
551 10:07:01.547387 ===================================
552 10:07:01.550986 DLL_ASYNC_EN = 0
553 10:07:01.554595 ALL_SLAVE_EN = 1
554 10:07:01.555061 NEW_RANK_MODE = 1
555 10:07:01.558421 DLL_IDLE_MODE = 1
556 10:07:01.561911 LP45_APHY_COMB_EN = 1
557 10:07:01.565983 TX_ODT_DIS = 1
558 10:07:01.566563 NEW_8X_MODE = 1
559 10:07:01.569326 ===================================
560 10:07:01.572978 ===================================
561 10:07:01.576855 data_rate = 1600
562 10:07:01.580605 CKR = 1
563 10:07:01.581174 DQ_P2S_RATIO = 8
564 10:07:01.583968 ===================================
565 10:07:01.587727 CA_P2S_RATIO = 8
566 10:07:01.591579 DQ_CA_OPEN = 0
567 10:07:01.592113 DQ_SEMI_OPEN = 0
568 10:07:01.595287 CA_SEMI_OPEN = 0
569 10:07:01.598571 CA_FULL_RATE = 0
570 10:07:01.602424 DQ_CKDIV4_EN = 1
571 10:07:01.605983 CA_CKDIV4_EN = 1
572 10:07:01.606547 CA_PREDIV_EN = 0
573 10:07:01.609627 PH8_DLY = 0
574 10:07:01.613173 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 10:07:01.616828 DQ_AAMCK_DIV = 4
576 10:07:01.617268 CA_AAMCK_DIV = 4
577 10:07:01.620717 CA_ADMCK_DIV = 4
578 10:07:01.624498 DQ_TRACK_CA_EN = 0
579 10:07:01.628052 CA_PICK = 800
580 10:07:01.628502 CA_MCKIO = 800
581 10:07:01.631747 MCKIO_SEMI = 0
582 10:07:01.635005 PLL_FREQ = 3068
583 10:07:01.638458 DQ_UI_PI_RATIO = 32
584 10:07:01.641824 CA_UI_PI_RATIO = 0
585 10:07:01.645004 ===================================
586 10:07:01.648651 ===================================
587 10:07:01.649176 memory_type:LPDDR4
588 10:07:01.651618 GP_NUM : 10
589 10:07:01.654988 SRAM_EN : 1
590 10:07:01.655544 MD32_EN : 0
591 10:07:01.658531 ===================================
592 10:07:01.661508 [ANA_INIT] >>>>>>>>>>>>>>
593 10:07:01.664840 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 10:07:01.668438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 10:07:01.671385 ===================================
596 10:07:01.674806 data_rate = 1600,PCW = 0X7600
597 10:07:01.677972 ===================================
598 10:07:01.681617 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 10:07:01.684824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 10:07:01.691548 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 10:07:01.694880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 10:07:01.698172 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 10:07:01.705213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 10:07:01.705797 [ANA_INIT] flow start
605 10:07:01.708240 [ANA_INIT] PLL >>>>>>>>
606 10:07:01.708708 [ANA_INIT] PLL <<<<<<<<
607 10:07:01.712353 [ANA_INIT] MIDPI >>>>>>>>
608 10:07:01.715678 [ANA_INIT] MIDPI <<<<<<<<
609 10:07:01.716143 [ANA_INIT] DLL >>>>>>>>
610 10:07:01.719318 [ANA_INIT] flow end
611 10:07:01.722954 ============ LP4 DIFF to SE enter ============
612 10:07:01.726955 ============ LP4 DIFF to SE exit ============
613 10:07:01.730099 [ANA_INIT] <<<<<<<<<<<<<
614 10:07:01.733829 [Flow] Enable top DCM control >>>>>
615 10:07:01.734297 [Flow] Enable top DCM control <<<<<
616 10:07:01.738012 Enable DLL master slave shuffle
617 10:07:01.745087 ==============================================================
618 10:07:01.745672 Gating Mode config
619 10:07:01.751776 ==============================================================
620 10:07:01.754798 Config description:
621 10:07:01.761782 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 10:07:01.768469 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 10:07:01.774482 SELPH_MODE 0: By rank 1: By Phase
624 10:07:01.781209 ==============================================================
625 10:07:01.781887 GAT_TRACK_EN = 1
626 10:07:01.784823 RX_GATING_MODE = 2
627 10:07:01.787848 RX_GATING_TRACK_MODE = 2
628 10:07:01.791257 SELPH_MODE = 1
629 10:07:01.794574 PICG_EARLY_EN = 1
630 10:07:01.797739 VALID_LAT_VALUE = 1
631 10:07:01.804687 ==============================================================
632 10:07:01.807782 Enter into Gating configuration >>>>
633 10:07:01.811261 Exit from Gating configuration <<<<
634 10:07:01.814678 Enter into DVFS_PRE_config >>>>>
635 10:07:01.824759 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 10:07:01.827945 Exit from DVFS_PRE_config <<<<<
637 10:07:01.831295 Enter into PICG configuration >>>>
638 10:07:01.834431 Exit from PICG configuration <<<<
639 10:07:01.837649 [RX_INPUT] configuration >>>>>
640 10:07:01.838072 [RX_INPUT] configuration <<<<<
641 10:07:01.844477 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 10:07:01.851436 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 10:07:01.857519 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 10:07:01.861282 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 10:07:01.867574 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 10:07:01.873876 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 10:07:01.877603 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 10:07:01.880616 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 10:07:01.887577 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 10:07:01.891117 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 10:07:01.894228 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 10:07:01.901069 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 10:07:01.904148 ===================================
654 10:07:01.904541 LPDDR4 DRAM CONFIGURATION
655 10:07:01.907175 ===================================
656 10:07:01.910737 EX_ROW_EN[0] = 0x0
657 10:07:01.911201 EX_ROW_EN[1] = 0x0
658 10:07:01.914337 LP4Y_EN = 0x0
659 10:07:01.917855 WORK_FSP = 0x0
660 10:07:01.918588 WL = 0x2
661 10:07:01.920688 RL = 0x2
662 10:07:01.921188 BL = 0x2
663 10:07:01.924077 RPST = 0x0
664 10:07:01.924565 RD_PRE = 0x0
665 10:07:01.927465 WR_PRE = 0x1
666 10:07:01.927973 WR_PST = 0x0
667 10:07:01.931361 DBI_WR = 0x0
668 10:07:01.931789 DBI_RD = 0x0
669 10:07:01.933894 OTF = 0x1
670 10:07:01.937455 ===================================
671 10:07:01.940922 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 10:07:01.943926 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 10:07:01.947198 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 10:07:01.950886 ===================================
675 10:07:01.953915 LPDDR4 DRAM CONFIGURATION
676 10:07:01.957172 ===================================
677 10:07:01.960833 EX_ROW_EN[0] = 0x10
678 10:07:01.961332 EX_ROW_EN[1] = 0x0
679 10:07:01.963972 LP4Y_EN = 0x0
680 10:07:01.964442 WORK_FSP = 0x0
681 10:07:01.967191 WL = 0x2
682 10:07:01.967615 RL = 0x2
683 10:07:01.970885 BL = 0x2
684 10:07:01.971374 RPST = 0x0
685 10:07:01.974090 RD_PRE = 0x0
686 10:07:01.974561 WR_PRE = 0x1
687 10:07:01.977355 WR_PST = 0x0
688 10:07:01.980922 DBI_WR = 0x0
689 10:07:01.981380 DBI_RD = 0x0
690 10:07:01.984028 OTF = 0x1
691 10:07:01.987891 ===================================
692 10:07:01.991379 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 10:07:01.995950 nWR fixed to 40
694 10:07:01.999562 [ModeRegInit_LP4] CH0 RK0
695 10:07:02.000017 [ModeRegInit_LP4] CH0 RK1
696 10:07:02.003269 [ModeRegInit_LP4] CH1 RK0
697 10:07:02.006623 [ModeRegInit_LP4] CH1 RK1
698 10:07:02.007083 match AC timing 13
699 10:07:02.010002 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 10:07:02.017124 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 10:07:02.020661 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 10:07:02.024449 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 10:07:02.027913 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 10:07:02.031745 [EMI DOE] emi_dcm 0
705 10:07:02.034955 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 10:07:02.035432 ==
707 10:07:02.039143 Dram Type= 6, Freq= 0, CH_0, rank 0
708 10:07:02.042488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 10:07:02.042938 ==
710 10:07:02.049842 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 10:07:02.053013 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 10:07:02.063739 [CA 0] Center 38 (7~69) winsize 63
713 10:07:02.067380 [CA 1] Center 37 (7~68) winsize 62
714 10:07:02.071720 [CA 2] Center 35 (5~66) winsize 62
715 10:07:02.075443 [CA 3] Center 35 (5~66) winsize 62
716 10:07:02.078665 [CA 4] Center 34 (4~65) winsize 62
717 10:07:02.079312 [CA 5] Center 34 (4~64) winsize 61
718 10:07:02.082718
719 10:07:02.086135 [CmdBusTrainingLP45] Vref(ca) range 1: 32
720 10:07:02.086641
721 10:07:02.089788 [CATrainingPosCal] consider 1 rank data
722 10:07:02.090408 u2DelayCellTimex100 = 270/100 ps
723 10:07:02.093476 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 10:07:02.097201 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 10:07:02.100792 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 10:07:02.104225 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 10:07:02.107757 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 10:07:02.111506 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
729 10:07:02.112032
730 10:07:02.115410 CA PerBit enable=1, Macro0, CA PI delay=34
731 10:07:02.115883
732 10:07:02.119309 [CBTSetCACLKResult] CA Dly = 34
733 10:07:02.122772 CS Dly: 5 (0~36)
734 10:07:02.123298 ==
735 10:07:02.126253 Dram Type= 6, Freq= 0, CH_0, rank 1
736 10:07:02.130412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 10:07:02.130934 ==
738 10:07:02.134213 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 10:07:02.141340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 10:07:02.149874 [CA 0] Center 38 (7~69) winsize 63
741 10:07:02.153115 [CA 1] Center 38 (7~69) winsize 63
742 10:07:02.156651 [CA 2] Center 35 (5~66) winsize 62
743 10:07:02.160371 [CA 3] Center 35 (5~66) winsize 62
744 10:07:02.164342 [CA 4] Center 34 (4~65) winsize 62
745 10:07:02.167622 [CA 5] Center 34 (3~65) winsize 63
746 10:07:02.168117
747 10:07:02.170941 [CmdBusTrainingLP45] Vref(ca) range 1: 34
748 10:07:02.171365
749 10:07:02.174815 [CATrainingPosCal] consider 2 rank data
750 10:07:02.178517 u2DelayCellTimex100 = 270/100 ps
751 10:07:02.182281 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 10:07:02.185944 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 10:07:02.189640 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 10:07:02.193599 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 10:07:02.196910 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 10:07:02.200841 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
757 10:07:02.201260
758 10:07:02.204537 CA PerBit enable=1, Macro0, CA PI delay=34
759 10:07:02.204977
760 10:07:02.207828 [CBTSetCACLKResult] CA Dly = 34
761 10:07:02.208253 CS Dly: 5 (0~37)
762 10:07:02.208589
763 10:07:02.211572 ----->DramcWriteLeveling(PI) begin...
764 10:07:02.212000 ==
765 10:07:02.214930 Dram Type= 6, Freq= 0, CH_0, rank 0
766 10:07:02.218637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 10:07:02.219233 ==
768 10:07:02.222352 Write leveling (Byte 0): 32 => 32
769 10:07:02.225753 Write leveling (Byte 1): 28 => 28
770 10:07:02.229542 DramcWriteLeveling(PI) end<-----
771 10:07:02.229966
772 10:07:02.230301 ==
773 10:07:02.233485 Dram Type= 6, Freq= 0, CH_0, rank 0
774 10:07:02.236878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 10:07:02.237305 ==
776 10:07:02.240682 [Gating] SW mode calibration
777 10:07:02.248020 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 10:07:02.251585 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 10:07:02.255891 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 10:07:02.259445 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 10:07:02.262962 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
782 10:07:02.270505 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 10:07:02.274178 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 10:07:02.277808 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 10:07:02.281133 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 10:07:02.285285 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 10:07:02.291992 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 10:07:02.295636 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 10:07:02.299202 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 10:07:02.302923 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 10:07:02.309947 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 10:07:02.313341 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 10:07:02.316994 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 10:07:02.320235 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 10:07:02.326997 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 10:07:02.330325 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 10:07:02.333681 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
798 10:07:02.340313 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
799 10:07:02.343711 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 10:07:02.347168 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 10:07:02.353804 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 10:07:02.357176 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 10:07:02.360399 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 10:07:02.366951 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 10:07:02.370467 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
806 10:07:02.373721 0 9 12 | B1->B0 | 2626 3030 | 0 0 | (0 0) (0 0)
807 10:07:02.376964 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 10:07:02.383526 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 10:07:02.387022 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 10:07:02.390595 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 10:07:02.396724 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 10:07:02.399996 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 10:07:02.403444 0 10 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
814 10:07:02.409862 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
815 10:07:02.413589 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 10:07:02.417043 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 10:07:02.423233 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 10:07:02.426518 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 10:07:02.429717 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 10:07:02.436404 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 10:07:02.439886 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
822 10:07:02.443389 0 11 12 | B1->B0 | 3434 4242 | 0 0 | (1 1) (0 0)
823 10:07:02.450055 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 10:07:02.453256 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 10:07:02.456329 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 10:07:02.462792 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 10:07:02.466392 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 10:07:02.469909 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 10:07:02.476006 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 10:07:02.480008 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 10:07:02.483121 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 10:07:02.489648 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 10:07:02.492828 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 10:07:02.496207 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 10:07:02.502716 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 10:07:02.506351 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 10:07:02.509583 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 10:07:02.516152 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 10:07:02.519356 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 10:07:02.523332 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 10:07:02.529361 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 10:07:02.533240 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 10:07:02.536263 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 10:07:02.542394 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 10:07:02.545712 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 10:07:02.549292 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 10:07:02.552689 Total UI for P1: 0, mck2ui 16
848 10:07:02.556230 best dqsien dly found for B0: ( 0, 14, 10)
849 10:07:02.559290 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 10:07:02.562747 Total UI for P1: 0, mck2ui 16
851 10:07:02.566184 best dqsien dly found for B1: ( 0, 14, 12)
852 10:07:02.569059 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
853 10:07:02.576271 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 10:07:02.576735
855 10:07:02.579303 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
856 10:07:02.582518 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 10:07:02.586029 [Gating] SW calibration Done
858 10:07:02.586519 ==
859 10:07:02.589262 Dram Type= 6, Freq= 0, CH_0, rank 0
860 10:07:02.592428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 10:07:02.592897 ==
862 10:07:02.595631 RX Vref Scan: 0
863 10:07:02.596096
864 10:07:02.596464 RX Vref 0 -> 0, step: 1
865 10:07:02.596838
866 10:07:02.599371 RX Delay -130 -> 252, step: 16
867 10:07:02.602599 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
868 10:07:02.609024 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 10:07:02.612775 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 10:07:02.615687 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 10:07:02.618915 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 10:07:02.622908 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 10:07:02.628858 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 10:07:02.632663 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 10:07:02.636056 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 10:07:02.639309 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 10:07:02.642303 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 10:07:02.648984 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 10:07:02.652086 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 10:07:02.655288 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 10:07:02.658904 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
882 10:07:02.662484 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 10:07:02.665665 ==
884 10:07:02.666128 Dram Type= 6, Freq= 0, CH_0, rank 0
885 10:07:02.672258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 10:07:02.672751 ==
887 10:07:02.673116 DQS Delay:
888 10:07:02.675687 DQS0 = 0, DQS1 = 0
889 10:07:02.676150 DQM Delay:
890 10:07:02.679075 DQM0 = 82, DQM1 = 70
891 10:07:02.679593 DQ Delay:
892 10:07:02.682202 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
893 10:07:02.685577 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
894 10:07:02.689420 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
895 10:07:02.692146 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
896 10:07:02.692716
897 10:07:02.693085
898 10:07:02.693424 ==
899 10:07:02.695827 Dram Type= 6, Freq= 0, CH_0, rank 0
900 10:07:02.699080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 10:07:02.699549 ==
902 10:07:02.699919
903 10:07:02.700261
904 10:07:02.702757 TX Vref Scan disable
905 10:07:02.703402 == TX Byte 0 ==
906 10:07:02.708973 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
907 10:07:02.712718 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
908 10:07:02.713209 == TX Byte 1 ==
909 10:07:02.719026 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
910 10:07:02.722506 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
911 10:07:02.723035 ==
912 10:07:02.725574 Dram Type= 6, Freq= 0, CH_0, rank 0
913 10:07:02.728886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 10:07:02.729375 ==
915 10:07:02.743245 TX Vref=22, minBit 3, minWin=26, winSum=435
916 10:07:02.746515 TX Vref=24, minBit 3, minWin=26, winSum=440
917 10:07:02.750086 TX Vref=26, minBit 2, minWin=27, winSum=445
918 10:07:02.753367 TX Vref=28, minBit 12, minWin=27, winSum=447
919 10:07:02.756781 TX Vref=30, minBit 5, minWin=27, winSum=444
920 10:07:02.763198 TX Vref=32, minBit 2, minWin=27, winSum=443
921 10:07:02.766563 [TxChooseVref] Worse bit 12, Min win 27, Win sum 447, Final Vref 28
922 10:07:02.767070
923 10:07:02.769817 Final TX Range 1 Vref 28
924 10:07:02.770286
925 10:07:02.770657 ==
926 10:07:02.773219 Dram Type= 6, Freq= 0, CH_0, rank 0
927 10:07:02.776815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 10:07:02.779514 ==
929 10:07:02.779992
930 10:07:02.780357
931 10:07:02.780700 TX Vref Scan disable
932 10:07:02.783959 == TX Byte 0 ==
933 10:07:02.786772 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
934 10:07:02.790182 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
935 10:07:02.793737 == TX Byte 1 ==
936 10:07:02.797273 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
937 10:07:02.800513 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
938 10:07:02.803651
939 10:07:02.804118 [DATLAT]
940 10:07:02.804490 Freq=800, CH0 RK0
941 10:07:02.804841
942 10:07:02.806974 DATLAT Default: 0xa
943 10:07:02.807463 0, 0xFFFF, sum = 0
944 10:07:02.810369 1, 0xFFFF, sum = 0
945 10:07:02.810880 2, 0xFFFF, sum = 0
946 10:07:02.813901 3, 0xFFFF, sum = 0
947 10:07:02.814371 4, 0xFFFF, sum = 0
948 10:07:02.816951 5, 0xFFFF, sum = 0
949 10:07:02.820262 6, 0xFFFF, sum = 0
950 10:07:02.820851 7, 0xFFFF, sum = 0
951 10:07:02.823533 8, 0xFFFF, sum = 0
952 10:07:02.824005 9, 0x0, sum = 1
953 10:07:02.824384 10, 0x0, sum = 2
954 10:07:02.827430 11, 0x0, sum = 3
955 10:07:02.828084 12, 0x0, sum = 4
956 10:07:02.830665 best_step = 10
957 10:07:02.831176
958 10:07:02.831546 ==
959 10:07:02.833775 Dram Type= 6, Freq= 0, CH_0, rank 0
960 10:07:02.836973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 10:07:02.837443 ==
962 10:07:02.840178 RX Vref Scan: 1
963 10:07:02.840643
964 10:07:02.841006 Set Vref Range= 32 -> 127
965 10:07:02.843394
966 10:07:02.843859 RX Vref 32 -> 127, step: 1
967 10:07:02.844228
968 10:07:02.846582 RX Delay -111 -> 252, step: 8
969 10:07:02.847095
970 10:07:02.850595 Set Vref, RX VrefLevel [Byte0]: 32
971 10:07:02.853677 [Byte1]: 32
972 10:07:02.854245
973 10:07:02.857018 Set Vref, RX VrefLevel [Byte0]: 33
974 10:07:02.859931 [Byte1]: 33
975 10:07:02.864109
976 10:07:02.864576 Set Vref, RX VrefLevel [Byte0]: 34
977 10:07:02.867734 [Byte1]: 34
978 10:07:02.871792
979 10:07:02.872274 Set Vref, RX VrefLevel [Byte0]: 35
980 10:07:02.878129 [Byte1]: 35
981 10:07:02.878598
982 10:07:02.881450 Set Vref, RX VrefLevel [Byte0]: 36
983 10:07:02.884973 [Byte1]: 36
984 10:07:02.885536
985 10:07:02.888281 Set Vref, RX VrefLevel [Byte0]: 37
986 10:07:02.891741 [Byte1]: 37
987 10:07:02.892231
988 10:07:02.894694 Set Vref, RX VrefLevel [Byte0]: 38
989 10:07:02.898141 [Byte1]: 38
990 10:07:02.902494
991 10:07:02.902994 Set Vref, RX VrefLevel [Byte0]: 39
992 10:07:02.905833 [Byte1]: 39
993 10:07:02.909806
994 10:07:02.910274 Set Vref, RX VrefLevel [Byte0]: 40
995 10:07:02.913959 [Byte1]: 40
996 10:07:02.917435
997 10:07:02.917902 Set Vref, RX VrefLevel [Byte0]: 41
998 10:07:02.921138 [Byte1]: 41
999 10:07:02.925294
1000 10:07:02.925751 Set Vref, RX VrefLevel [Byte0]: 42
1001 10:07:02.928553 [Byte1]: 42
1002 10:07:02.933123
1003 10:07:02.933769 Set Vref, RX VrefLevel [Byte0]: 43
1004 10:07:02.936020 [Byte1]: 43
1005 10:07:02.940802
1006 10:07:02.941260 Set Vref, RX VrefLevel [Byte0]: 44
1007 10:07:02.943981 [Byte1]: 44
1008 10:07:02.948364
1009 10:07:02.948927 Set Vref, RX VrefLevel [Byte0]: 45
1010 10:07:02.951444 [Byte1]: 45
1011 10:07:02.956028
1012 10:07:02.956491 Set Vref, RX VrefLevel [Byte0]: 46
1013 10:07:02.959498 [Byte1]: 46
1014 10:07:02.963521
1015 10:07:02.964101 Set Vref, RX VrefLevel [Byte0]: 47
1016 10:07:02.966711 [Byte1]: 47
1017 10:07:02.971551
1018 10:07:02.972008 Set Vref, RX VrefLevel [Byte0]: 48
1019 10:07:02.974807 [Byte1]: 48
1020 10:07:02.979023
1021 10:07:02.979717 Set Vref, RX VrefLevel [Byte0]: 49
1022 10:07:02.982385 [Byte1]: 49
1023 10:07:02.986534
1024 10:07:02.987251 Set Vref, RX VrefLevel [Byte0]: 50
1025 10:07:02.989687 [Byte1]: 50
1026 10:07:02.994270
1027 10:07:02.994902 Set Vref, RX VrefLevel [Byte0]: 51
1028 10:07:02.997379 [Byte1]: 51
1029 10:07:03.001826
1030 10:07:03.002339 Set Vref, RX VrefLevel [Byte0]: 52
1031 10:07:03.004804 [Byte1]: 52
1032 10:07:03.009243
1033 10:07:03.009706 Set Vref, RX VrefLevel [Byte0]: 53
1034 10:07:03.013050 [Byte1]: 53
1035 10:07:03.017523
1036 10:07:03.017980 Set Vref, RX VrefLevel [Byte0]: 54
1037 10:07:03.020181 [Byte1]: 54
1038 10:07:03.024634
1039 10:07:03.025085 Set Vref, RX VrefLevel [Byte0]: 55
1040 10:07:03.028080 [Byte1]: 55
1041 10:07:03.032473
1042 10:07:03.032946 Set Vref, RX VrefLevel [Byte0]: 56
1043 10:07:03.035748 [Byte1]: 56
1044 10:07:03.040258
1045 10:07:03.040811 Set Vref, RX VrefLevel [Byte0]: 57
1046 10:07:03.043249 [Byte1]: 57
1047 10:07:03.047376
1048 10:07:03.048028 Set Vref, RX VrefLevel [Byte0]: 58
1049 10:07:03.050681 [Byte1]: 58
1050 10:07:03.054964
1051 10:07:03.055417 Set Vref, RX VrefLevel [Byte0]: 59
1052 10:07:03.058733 [Byte1]: 59
1053 10:07:03.063232
1054 10:07:03.063827 Set Vref, RX VrefLevel [Byte0]: 60
1055 10:07:03.066179 [Byte1]: 60
1056 10:07:03.070697
1057 10:07:03.071198 Set Vref, RX VrefLevel [Byte0]: 61
1058 10:07:03.073927 [Byte1]: 61
1059 10:07:03.078041
1060 10:07:03.078502 Set Vref, RX VrefLevel [Byte0]: 62
1061 10:07:03.081461 [Byte1]: 62
1062 10:07:03.086045
1063 10:07:03.086623 Set Vref, RX VrefLevel [Byte0]: 63
1064 10:07:03.089269 [Byte1]: 63
1065 10:07:03.093805
1066 10:07:03.094266 Set Vref, RX VrefLevel [Byte0]: 64
1067 10:07:03.096813 [Byte1]: 64
1068 10:07:03.101090
1069 10:07:03.101552 Set Vref, RX VrefLevel [Byte0]: 65
1070 10:07:03.104265 [Byte1]: 65
1071 10:07:03.108689
1072 10:07:03.109151 Set Vref, RX VrefLevel [Byte0]: 66
1073 10:07:03.111854 [Byte1]: 66
1074 10:07:03.116648
1075 10:07:03.117197 Set Vref, RX VrefLevel [Byte0]: 67
1076 10:07:03.119796 [Byte1]: 67
1077 10:07:03.124220
1078 10:07:03.124685 Set Vref, RX VrefLevel [Byte0]: 68
1079 10:07:03.127549 [Byte1]: 68
1080 10:07:03.131344
1081 10:07:03.131867 Set Vref, RX VrefLevel [Byte0]: 69
1082 10:07:03.135008 [Byte1]: 69
1083 10:07:03.139420
1084 10:07:03.139884 Set Vref, RX VrefLevel [Byte0]: 70
1085 10:07:03.142863 [Byte1]: 70
1086 10:07:03.146906
1087 10:07:03.147512 Set Vref, RX VrefLevel [Byte0]: 71
1088 10:07:03.150550 [Byte1]: 71
1089 10:07:03.154396
1090 10:07:03.155032 Set Vref, RX VrefLevel [Byte0]: 72
1091 10:07:03.157603 [Byte1]: 72
1092 10:07:03.162366
1093 10:07:03.162875 Set Vref, RX VrefLevel [Byte0]: 73
1094 10:07:03.165880 [Byte1]: 73
1095 10:07:03.169991
1096 10:07:03.170455 Set Vref, RX VrefLevel [Byte0]: 74
1097 10:07:03.173420 [Byte1]: 74
1098 10:07:03.177660
1099 10:07:03.178208 Set Vref, RX VrefLevel [Byte0]: 75
1100 10:07:03.180828 [Byte1]: 75
1101 10:07:03.185210
1102 10:07:03.185668 Set Vref, RX VrefLevel [Byte0]: 76
1103 10:07:03.188434 [Byte1]: 76
1104 10:07:03.192763
1105 10:07:03.193246 Set Vref, RX VrefLevel [Byte0]: 77
1106 10:07:03.195945 [Byte1]: 77
1107 10:07:03.200861
1108 10:07:03.201317 Set Vref, RX VrefLevel [Byte0]: 78
1109 10:07:03.203865 [Byte1]: 78
1110 10:07:03.208134
1111 10:07:03.208774 Set Vref, RX VrefLevel [Byte0]: 79
1112 10:07:03.211185 [Byte1]: 79
1113 10:07:03.215533
1114 10:07:03.216173 Final RX Vref Byte 0 = 63 to rank0
1115 10:07:03.218932 Final RX Vref Byte 1 = 63 to rank0
1116 10:07:03.222340 Final RX Vref Byte 0 = 63 to rank1
1117 10:07:03.225656 Final RX Vref Byte 1 = 63 to rank1==
1118 10:07:03.229376 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 10:07:03.235825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 10:07:03.236294 ==
1121 10:07:03.236663 DQS Delay:
1122 10:07:03.237004 DQS0 = 0, DQS1 = 0
1123 10:07:03.238883 DQM Delay:
1124 10:07:03.239351 DQM0 = 81, DQM1 = 68
1125 10:07:03.242184 DQ Delay:
1126 10:07:03.245198 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1127 10:07:03.249058 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1128 10:07:03.252360 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1129 10:07:03.255635 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1130 10:07:03.256098
1131 10:07:03.256466
1132 10:07:03.262194 [DQSOSCAuto] RK0, (LSB)MR18= 0x2726, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1133 10:07:03.265563 CH0 RK0: MR19=606, MR18=2726
1134 10:07:03.272073 CH0_RK0: MR19=0x606, MR18=0x2726, DQSOSC=400, MR23=63, INC=92, DEC=61
1135 10:07:03.272499
1136 10:07:03.275327 ----->DramcWriteLeveling(PI) begin...
1137 10:07:03.275755 ==
1138 10:07:03.278565 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 10:07:03.282026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 10:07:03.282561 ==
1141 10:07:03.285814 Write leveling (Byte 0): 32 => 32
1142 10:07:03.288589 Write leveling (Byte 1): 31 => 31
1143 10:07:03.291918 DramcWriteLeveling(PI) end<-----
1144 10:07:03.292340
1145 10:07:03.292674 ==
1146 10:07:03.295190 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 10:07:03.298669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 10:07:03.299171 ==
1149 10:07:03.302027 [Gating] SW mode calibration
1150 10:07:03.308113 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 10:07:03.314730 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 10:07:03.318372 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 10:07:03.325143 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1154 10:07:03.328712 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1155 10:07:03.331478 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1156 10:07:03.338535 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 10:07:03.341237 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 10:07:03.345106 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 10:07:03.351621 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 10:07:03.354637 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 10:07:03.357977 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 10:07:03.362002 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 10:07:03.368122 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 10:07:03.371244 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 10:07:03.415502 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 10:07:03.416439 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 10:07:03.416838 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 10:07:03.417186 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 10:07:03.417625 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 10:07:03.418168 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1171 10:07:03.418595 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 10:07:03.418991 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 10:07:03.419329 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 10:07:03.419647 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 10:07:03.431758 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 10:07:03.432335 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 10:07:03.435142 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 10:07:03.435611 0 9 8 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
1179 10:07:03.438323 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (1 1) (1 1)
1180 10:07:03.441488 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 10:07:03.445120 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 10:07:03.451407 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 10:07:03.454974 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 10:07:03.458355 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1185 10:07:03.465047 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1186 10:07:03.468099 0 10 8 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
1187 10:07:03.471361 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1188 10:07:03.478325 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 10:07:03.481596 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 10:07:03.484699 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 10:07:03.491643 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 10:07:03.494921 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 10:07:03.498164 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1194 10:07:03.504771 0 11 8 | B1->B0 | 3434 4040 | 1 0 | (0 0) (0 0)
1195 10:07:03.507856 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1196 10:07:03.511597 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 10:07:03.518144 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 10:07:03.521367 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 10:07:03.524897 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 10:07:03.531543 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 10:07:03.535086 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 10:07:03.539152 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1203 10:07:03.542414 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 10:07:03.549046 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 10:07:03.552282 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 10:07:03.556137 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 10:07:03.560015 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 10:07:03.566614 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 10:07:03.569670 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 10:07:03.573173 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 10:07:03.579942 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 10:07:03.583202 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 10:07:03.586379 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 10:07:03.593262 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 10:07:03.596642 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 10:07:03.599710 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 10:07:03.606274 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 10:07:03.609438 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 10:07:03.613170 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1220 10:07:03.616157 Total UI for P1: 0, mck2ui 16
1221 10:07:03.619272 best dqsien dly found for B0: ( 0, 14, 8)
1222 10:07:03.622652 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 10:07:03.626405 Total UI for P1: 0, mck2ui 16
1224 10:07:03.629558 best dqsien dly found for B1: ( 0, 14, 10)
1225 10:07:03.632952 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1226 10:07:03.639589 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1227 10:07:03.640052
1228 10:07:03.642790 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 10:07:03.646040 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1230 10:07:03.649718 [Gating] SW calibration Done
1231 10:07:03.650275 ==
1232 10:07:03.652870 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 10:07:03.655900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 10:07:03.656362 ==
1235 10:07:03.656909 RX Vref Scan: 0
1236 10:07:03.659548
1237 10:07:03.660005 RX Vref 0 -> 0, step: 1
1238 10:07:03.660370
1239 10:07:03.662808 RX Delay -130 -> 252, step: 16
1240 10:07:03.666232 iDelay=222, Bit 0, Center 69 (-50 ~ 189) 240
1241 10:07:03.669159 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1242 10:07:03.676117 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1243 10:07:03.679331 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1244 10:07:03.682642 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1245 10:07:03.686229 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1246 10:07:03.689105 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1247 10:07:03.696037 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1248 10:07:03.699276 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1249 10:07:03.702690 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1250 10:07:03.705480 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1251 10:07:03.712351 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1252 10:07:03.715331 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1253 10:07:03.718954 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1254 10:07:03.722450 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1255 10:07:03.725904 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1256 10:07:03.728873 ==
1257 10:07:03.731972 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 10:07:03.735337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 10:07:03.735798 ==
1260 10:07:03.736166 DQS Delay:
1261 10:07:03.738945 DQS0 = 0, DQS1 = 0
1262 10:07:03.739405 DQM Delay:
1263 10:07:03.742401 DQM0 = 76, DQM1 = 69
1264 10:07:03.742998 DQ Delay:
1265 10:07:03.745550 DQ0 =69, DQ1 =77, DQ2 =69, DQ3 =69
1266 10:07:03.749150 DQ4 =77, DQ5 =61, DQ6 =93, DQ7 =93
1267 10:07:03.751892 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1268 10:07:03.755219 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1269 10:07:03.755823
1270 10:07:03.756345
1271 10:07:03.756844 ==
1272 10:07:03.758631 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 10:07:03.761930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 10:07:03.762541 ==
1275 10:07:03.763123
1276 10:07:03.763561
1277 10:07:03.765417 TX Vref Scan disable
1278 10:07:03.768836 == TX Byte 0 ==
1279 10:07:03.771741 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1280 10:07:03.775074 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1281 10:07:03.778397 == TX Byte 1 ==
1282 10:07:03.781802 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1283 10:07:03.785162 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1284 10:07:03.785622 ==
1285 10:07:03.788239 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 10:07:03.794734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 10:07:03.795239 ==
1288 10:07:03.806611 TX Vref=22, minBit 15, minWin=26, winSum=433
1289 10:07:03.810176 TX Vref=24, minBit 0, minWin=27, winSum=436
1290 10:07:03.813382 TX Vref=26, minBit 1, minWin=27, winSum=441
1291 10:07:03.816564 TX Vref=28, minBit 9, minWin=27, winSum=446
1292 10:07:03.819715 TX Vref=30, minBit 1, minWin=27, winSum=442
1293 10:07:03.826243 TX Vref=32, minBit 1, minWin=27, winSum=442
1294 10:07:03.829538 [TxChooseVref] Worse bit 9, Min win 27, Win sum 446, Final Vref 28
1295 10:07:03.830065
1296 10:07:03.832626 Final TX Range 1 Vref 28
1297 10:07:03.833200
1298 10:07:03.833694 ==
1299 10:07:03.835904 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 10:07:03.839706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 10:07:03.842735 ==
1302 10:07:03.843314
1303 10:07:03.843657
1304 10:07:03.844006 TX Vref Scan disable
1305 10:07:03.846314 == TX Byte 0 ==
1306 10:07:03.849848 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1307 10:07:03.856003 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1308 10:07:03.856420 == TX Byte 1 ==
1309 10:07:03.859559 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1310 10:07:03.866220 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1311 10:07:03.866821
1312 10:07:03.867381 [DATLAT]
1313 10:07:03.867891 Freq=800, CH0 RK1
1314 10:07:03.868340
1315 10:07:03.869272 DATLAT Default: 0xa
1316 10:07:03.872721 0, 0xFFFF, sum = 0
1317 10:07:03.873162 1, 0xFFFF, sum = 0
1318 10:07:03.876126 2, 0xFFFF, sum = 0
1319 10:07:03.876541 3, 0xFFFF, sum = 0
1320 10:07:03.879349 4, 0xFFFF, sum = 0
1321 10:07:03.879847 5, 0xFFFF, sum = 0
1322 10:07:03.882649 6, 0xFFFF, sum = 0
1323 10:07:03.883253 7, 0xFFFF, sum = 0
1324 10:07:03.886040 8, 0xFFFF, sum = 0
1325 10:07:03.886560 9, 0x0, sum = 1
1326 10:07:03.889356 10, 0x0, sum = 2
1327 10:07:03.889895 11, 0x0, sum = 3
1328 10:07:03.892452 12, 0x0, sum = 4
1329 10:07:03.893020 best_step = 10
1330 10:07:03.893503
1331 10:07:03.893949 ==
1332 10:07:03.896015 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 10:07:03.899063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 10:07:03.899474 ==
1335 10:07:03.902363 RX Vref Scan: 0
1336 10:07:03.902769
1337 10:07:03.905543 RX Vref 0 -> 0, step: 1
1338 10:07:03.905952
1339 10:07:03.906334 RX Delay -111 -> 252, step: 8
1340 10:07:03.913049 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1341 10:07:03.916664 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1342 10:07:03.919455 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1343 10:07:03.923378 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1344 10:07:03.926398 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1345 10:07:03.932961 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1346 10:07:03.936383 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1347 10:07:03.939666 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1348 10:07:03.942874 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1349 10:07:03.946957 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1350 10:07:03.952980 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1351 10:07:03.956115 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1352 10:07:03.959663 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1353 10:07:03.962818 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1354 10:07:03.969725 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1355 10:07:03.972682 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1356 10:07:03.973273 ==
1357 10:07:03.975924 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 10:07:03.979304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 10:07:03.979763 ==
1360 10:07:03.982484 DQS Delay:
1361 10:07:03.983050 DQS0 = 0, DQS1 = 0
1362 10:07:03.983434 DQM Delay:
1363 10:07:03.985948 DQM0 = 79, DQM1 = 70
1364 10:07:03.986393 DQ Delay:
1365 10:07:03.989367 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1366 10:07:03.992748 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =92
1367 10:07:03.995863 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1368 10:07:03.999088 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =80
1369 10:07:03.999492
1370 10:07:03.999812
1371 10:07:04.009246 [DQSOSCAuto] RK1, (LSB)MR18= 0x4925, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1372 10:07:04.009659 CH0 RK1: MR19=606, MR18=4925
1373 10:07:04.016440 CH0_RK1: MR19=0x606, MR18=0x4925, DQSOSC=391, MR23=63, INC=96, DEC=64
1374 10:07:04.019804 [RxdqsGatingPostProcess] freq 800
1375 10:07:04.025673 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1376 10:07:04.028880 Pre-setting of DQS Precalculation
1377 10:07:04.032542 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1378 10:07:04.032998 ==
1379 10:07:04.036128 Dram Type= 6, Freq= 0, CH_1, rank 0
1380 10:07:04.042343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 10:07:04.042994 ==
1382 10:07:04.045959 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1383 10:07:04.052812 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1384 10:07:04.061795 [CA 0] Center 36 (6~66) winsize 61
1385 10:07:04.064711 [CA 1] Center 36 (6~67) winsize 62
1386 10:07:04.068232 [CA 2] Center 34 (5~64) winsize 60
1387 10:07:04.071563 [CA 3] Center 34 (4~64) winsize 61
1388 10:07:04.074692 [CA 4] Center 35 (5~65) winsize 61
1389 10:07:04.077845 [CA 5] Center 33 (3~64) winsize 62
1390 10:07:04.078290
1391 10:07:04.081209 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1392 10:07:04.081696
1393 10:07:04.084653 [CATrainingPosCal] consider 1 rank data
1394 10:07:04.087996 u2DelayCellTimex100 = 270/100 ps
1395 10:07:04.091390 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1396 10:07:04.098022 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1397 10:07:04.101239 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1398 10:07:04.104143 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1399 10:07:04.107771 CA4 delay=35 (5~65),Diff = 2 PI (14 cell)
1400 10:07:04.111456 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1401 10:07:04.112022
1402 10:07:04.114964 CA PerBit enable=1, Macro0, CA PI delay=33
1403 10:07:04.115519
1404 10:07:04.117821 [CBTSetCACLKResult] CA Dly = 33
1405 10:07:04.121532 CS Dly: 5 (0~36)
1406 10:07:04.122090 ==
1407 10:07:04.124397 Dram Type= 6, Freq= 0, CH_1, rank 1
1408 10:07:04.127642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 10:07:04.128109 ==
1410 10:07:04.134101 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1411 10:07:04.137646 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1412 10:07:04.147795 [CA 0] Center 36 (6~67) winsize 62
1413 10:07:04.151008 [CA 1] Center 36 (6~67) winsize 62
1414 10:07:04.154515 [CA 2] Center 35 (5~65) winsize 61
1415 10:07:04.157494 [CA 3] Center 33 (3~64) winsize 62
1416 10:07:04.160654 [CA 4] Center 34 (4~65) winsize 62
1417 10:07:04.164381 [CA 5] Center 33 (3~64) winsize 62
1418 10:07:04.164839
1419 10:07:04.167637 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1420 10:07:04.168113
1421 10:07:04.170779 [CATrainingPosCal] consider 2 rank data
1422 10:07:04.174004 u2DelayCellTimex100 = 270/100 ps
1423 10:07:04.177412 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1424 10:07:04.184159 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1425 10:07:04.187310 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1426 10:07:04.190716 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1427 10:07:04.194134 CA4 delay=35 (5~65),Diff = 2 PI (14 cell)
1428 10:07:04.197461 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1429 10:07:04.198072
1430 10:07:04.201430 CA PerBit enable=1, Macro0, CA PI delay=33
1431 10:07:04.201849
1432 10:07:04.204974 [CBTSetCACLKResult] CA Dly = 33
1433 10:07:04.205503 CS Dly: 6 (0~38)
1434 10:07:04.206086
1435 10:07:04.208730 ----->DramcWriteLeveling(PI) begin...
1436 10:07:04.209164 ==
1437 10:07:04.211900 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 10:07:04.215918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 10:07:04.216451 ==
1440 10:07:04.219377 Write leveling (Byte 0): 29 => 29
1441 10:07:04.222941 Write leveling (Byte 1): 30 => 30
1442 10:07:04.226814 DramcWriteLeveling(PI) end<-----
1443 10:07:04.227326
1444 10:07:04.227888 ==
1445 10:07:04.229718 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 10:07:04.233062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 10:07:04.233516 ==
1448 10:07:04.236290 [Gating] SW mode calibration
1449 10:07:04.242961 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1450 10:07:04.249447 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1451 10:07:04.253111 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 10:07:04.256342 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1453 10:07:04.262794 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1454 10:07:04.266068 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 10:07:04.269345 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 10:07:04.276075 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 10:07:04.279140 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 10:07:04.282947 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 10:07:04.289771 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 10:07:04.292768 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 10:07:04.296202 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 10:07:04.302295 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 10:07:04.305761 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 10:07:04.309264 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 10:07:04.315796 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 10:07:04.319174 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 10:07:04.322443 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 10:07:04.328708 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 10:07:04.332572 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1470 10:07:04.335407 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 10:07:04.341986 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 10:07:04.345239 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 10:07:04.348964 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 10:07:04.355398 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 10:07:04.358531 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 10:07:04.361998 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 10:07:04.368507 0 9 8 | B1->B0 | 2727 2a2a | 0 0 | (0 0) (0 0)
1478 10:07:04.371430 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 10:07:04.374652 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 10:07:04.381560 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 10:07:04.384617 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 10:07:04.387919 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 10:07:04.394680 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 10:07:04.398118 0 10 4 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 0)
1485 10:07:04.401761 0 10 8 | B1->B0 | 2f2f 2e2e | 0 0 | (1 1) (1 1)
1486 10:07:04.408123 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 10:07:04.411123 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 10:07:04.414784 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 10:07:04.421213 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 10:07:04.424531 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 10:07:04.427762 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 10:07:04.434553 0 11 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
1493 10:07:04.438181 0 11 8 | B1->B0 | 3434 3838 | 0 0 | (0 0) (1 1)
1494 10:07:04.441441 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 10:07:04.447666 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 10:07:04.451257 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 10:07:04.454448 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 10:07:04.460935 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 10:07:04.464027 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 10:07:04.467379 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 10:07:04.474374 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 10:07:04.477554 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 10:07:04.480683 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 10:07:04.487735 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 10:07:04.490600 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 10:07:04.494338 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 10:07:04.500696 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 10:07:04.503808 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 10:07:04.507377 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 10:07:04.513778 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 10:07:04.516758 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 10:07:04.520139 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 10:07:04.526796 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 10:07:04.530207 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 10:07:04.533982 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 10:07:04.540139 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 10:07:04.543393 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1518 10:07:04.546530 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 10:07:04.549938 Total UI for P1: 0, mck2ui 16
1520 10:07:04.553532 best dqsien dly found for B0: ( 0, 14, 8)
1521 10:07:04.556608 Total UI for P1: 0, mck2ui 16
1522 10:07:04.559783 best dqsien dly found for B1: ( 0, 14, 8)
1523 10:07:04.563664 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1524 10:07:04.566678 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1525 10:07:04.566784
1526 10:07:04.569994 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1527 10:07:04.576351 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1528 10:07:04.576434 [Gating] SW calibration Done
1529 10:07:04.576499 ==
1530 10:07:04.579580 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 10:07:04.586484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 10:07:04.586566 ==
1533 10:07:04.586630 RX Vref Scan: 0
1534 10:07:04.586689
1535 10:07:04.589572 RX Vref 0 -> 0, step: 1
1536 10:07:04.589652
1537 10:07:04.593255 RX Delay -130 -> 252, step: 16
1538 10:07:04.596430 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1539 10:07:04.599574 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1540 10:07:04.602717 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1541 10:07:04.609478 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1542 10:07:04.613418 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1543 10:07:04.616075 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1544 10:07:04.619351 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1545 10:07:04.622678 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1546 10:07:04.629410 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1547 10:07:04.632740 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1548 10:07:04.636267 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1549 10:07:04.639179 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1550 10:07:04.642541 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1551 10:07:04.649232 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1552 10:07:04.652804 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1553 10:07:04.656239 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1554 10:07:04.656326 ==
1555 10:07:04.659231 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 10:07:04.662292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 10:07:04.665949 ==
1558 10:07:04.666021 DQS Delay:
1559 10:07:04.666083 DQS0 = 0, DQS1 = 0
1560 10:07:04.669097 DQM Delay:
1561 10:07:04.669172 DQM0 = 81, DQM1 = 72
1562 10:07:04.672290 DQ Delay:
1563 10:07:04.676070 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1564 10:07:04.676146 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1565 10:07:04.679222 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1566 10:07:04.682535 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1567 10:07:04.685749
1568 10:07:04.685818
1569 10:07:04.685885 ==
1570 10:07:04.689242 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 10:07:04.691995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 10:07:04.692072 ==
1573 10:07:04.692133
1574 10:07:04.692191
1575 10:07:04.695556 TX Vref Scan disable
1576 10:07:04.695623 == TX Byte 0 ==
1577 10:07:04.702410 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1578 10:07:04.705595 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1579 10:07:04.705678 == TX Byte 1 ==
1580 10:07:04.712421 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1581 10:07:04.715593 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1582 10:07:04.715671 ==
1583 10:07:04.718807 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 10:07:04.721919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 10:07:04.721996 ==
1586 10:07:04.735710 TX Vref=22, minBit 1, minWin=26, winSum=438
1587 10:07:04.739059 TX Vref=24, minBit 1, minWin=26, winSum=439
1588 10:07:04.742464 TX Vref=26, minBit 0, minWin=27, winSum=442
1589 10:07:04.745823 TX Vref=28, minBit 4, minWin=27, winSum=446
1590 10:07:04.748890 TX Vref=30, minBit 4, minWin=27, winSum=446
1591 10:07:04.755394 TX Vref=32, minBit 0, minWin=27, winSum=446
1592 10:07:04.758823 [TxChooseVref] Worse bit 4, Min win 27, Win sum 446, Final Vref 28
1593 10:07:04.758946
1594 10:07:04.762128 Final TX Range 1 Vref 28
1595 10:07:04.762206
1596 10:07:04.762270 ==
1597 10:07:04.765862 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 10:07:04.769183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 10:07:04.769306 ==
1600 10:07:04.769369
1601 10:07:04.772591
1602 10:07:04.772665 TX Vref Scan disable
1603 10:07:04.775812 == TX Byte 0 ==
1604 10:07:04.778980 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1605 10:07:04.782285 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1606 10:07:04.785894 == TX Byte 1 ==
1607 10:07:04.789289 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1608 10:07:04.795347 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1609 10:07:04.795419
1610 10:07:04.795481 [DATLAT]
1611 10:07:04.795553 Freq=800, CH1 RK0
1612 10:07:04.795611
1613 10:07:04.798945 DATLAT Default: 0xa
1614 10:07:04.799022 0, 0xFFFF, sum = 0
1615 10:07:04.802044 1, 0xFFFF, sum = 0
1616 10:07:04.805286 2, 0xFFFF, sum = 0
1617 10:07:04.805365 3, 0xFFFF, sum = 0
1618 10:07:04.808937 4, 0xFFFF, sum = 0
1619 10:07:04.809018 5, 0xFFFF, sum = 0
1620 10:07:04.812243 6, 0xFFFF, sum = 0
1621 10:07:04.812313 7, 0xFFFF, sum = 0
1622 10:07:04.815289 8, 0xFFFF, sum = 0
1623 10:07:04.815359 9, 0x0, sum = 1
1624 10:07:04.819191 10, 0x0, sum = 2
1625 10:07:04.819260 11, 0x0, sum = 3
1626 10:07:04.819329 12, 0x0, sum = 4
1627 10:07:04.822171 best_step = 10
1628 10:07:04.822244
1629 10:07:04.822303 ==
1630 10:07:04.825630 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 10:07:04.828516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 10:07:04.828592 ==
1633 10:07:04.831597 RX Vref Scan: 1
1634 10:07:04.831672
1635 10:07:04.835162 Set Vref Range= 32 -> 127
1636 10:07:04.835234
1637 10:07:04.835346 RX Vref 32 -> 127, step: 1
1638 10:07:04.835406
1639 10:07:04.838582 RX Delay -111 -> 252, step: 8
1640 10:07:04.838664
1641 10:07:04.841614 Set Vref, RX VrefLevel [Byte0]: 32
1642 10:07:04.845093 [Byte1]: 32
1643 10:07:04.848588
1644 10:07:04.848670 Set Vref, RX VrefLevel [Byte0]: 33
1645 10:07:04.851962 [Byte1]: 33
1646 10:07:04.856044
1647 10:07:04.856125 Set Vref, RX VrefLevel [Byte0]: 34
1648 10:07:04.859718 [Byte1]: 34
1649 10:07:04.863900
1650 10:07:04.863986 Set Vref, RX VrefLevel [Byte0]: 35
1651 10:07:04.867026 [Byte1]: 35
1652 10:07:04.871453
1653 10:07:04.871568 Set Vref, RX VrefLevel [Byte0]: 36
1654 10:07:04.874731 [Byte1]: 36
1655 10:07:04.879034
1656 10:07:04.879141 Set Vref, RX VrefLevel [Byte0]: 37
1657 10:07:04.882319 [Byte1]: 37
1658 10:07:04.886556
1659 10:07:04.886628 Set Vref, RX VrefLevel [Byte0]: 38
1660 10:07:04.890278 [Byte1]: 38
1661 10:07:04.894543
1662 10:07:04.894644 Set Vref, RX VrefLevel [Byte0]: 39
1663 10:07:04.897603 [Byte1]: 39
1664 10:07:04.901894
1665 10:07:04.901997 Set Vref, RX VrefLevel [Byte0]: 40
1666 10:07:04.905407 [Byte1]: 40
1667 10:07:04.909728
1668 10:07:04.909809 Set Vref, RX VrefLevel [Byte0]: 41
1669 10:07:04.912976 [Byte1]: 41
1670 10:07:04.917155
1671 10:07:04.917236 Set Vref, RX VrefLevel [Byte0]: 42
1672 10:07:04.920828 [Byte1]: 42
1673 10:07:04.925035
1674 10:07:04.925117 Set Vref, RX VrefLevel [Byte0]: 43
1675 10:07:04.928148 [Byte1]: 43
1676 10:07:04.932848
1677 10:07:04.932930 Set Vref, RX VrefLevel [Byte0]: 44
1678 10:07:04.935975 [Byte1]: 44
1679 10:07:04.940369
1680 10:07:04.940450 Set Vref, RX VrefLevel [Byte0]: 45
1681 10:07:04.943750 [Byte1]: 45
1682 10:07:04.947798
1683 10:07:04.947880 Set Vref, RX VrefLevel [Byte0]: 46
1684 10:07:04.951540 [Byte1]: 46
1685 10:07:04.955413
1686 10:07:04.955526 Set Vref, RX VrefLevel [Byte0]: 47
1687 10:07:04.958889 [Byte1]: 47
1688 10:07:04.963397
1689 10:07:04.963478 Set Vref, RX VrefLevel [Byte0]: 48
1690 10:07:04.966602 [Byte1]: 48
1691 10:07:04.970725
1692 10:07:04.970806 Set Vref, RX VrefLevel [Byte0]: 49
1693 10:07:04.974202 [Byte1]: 49
1694 10:07:04.978412
1695 10:07:04.978493 Set Vref, RX VrefLevel [Byte0]: 50
1696 10:07:04.981997 [Byte1]: 50
1697 10:07:04.986381
1698 10:07:04.986463 Set Vref, RX VrefLevel [Byte0]: 51
1699 10:07:04.989499 [Byte1]: 51
1700 10:07:04.993899
1701 10:07:04.993981 Set Vref, RX VrefLevel [Byte0]: 52
1702 10:07:04.997013 [Byte1]: 52
1703 10:07:05.001338
1704 10:07:05.001425 Set Vref, RX VrefLevel [Byte0]: 53
1705 10:07:05.004542 [Byte1]: 53
1706 10:07:05.009247
1707 10:07:05.009329 Set Vref, RX VrefLevel [Byte0]: 54
1708 10:07:05.012469 [Byte1]: 54
1709 10:07:05.016850
1710 10:07:05.016937 Set Vref, RX VrefLevel [Byte0]: 55
1711 10:07:05.023521 [Byte1]: 55
1712 10:07:05.023683
1713 10:07:05.026700 Set Vref, RX VrefLevel [Byte0]: 56
1714 10:07:05.030022 [Byte1]: 56
1715 10:07:05.030124
1716 10:07:05.033602 Set Vref, RX VrefLevel [Byte0]: 57
1717 10:07:05.036551 [Byte1]: 57
1718 10:07:05.039801
1719 10:07:05.039924 Set Vref, RX VrefLevel [Byte0]: 58
1720 10:07:05.043221 [Byte1]: 58
1721 10:07:05.047807
1722 10:07:05.047995 Set Vref, RX VrefLevel [Byte0]: 59
1723 10:07:05.050654 [Byte1]: 59
1724 10:07:05.054974
1725 10:07:05.055148 Set Vref, RX VrefLevel [Byte0]: 60
1726 10:07:05.058554 [Byte1]: 60
1727 10:07:05.063055
1728 10:07:05.063296 Set Vref, RX VrefLevel [Byte0]: 61
1729 10:07:05.066007 [Byte1]: 61
1730 10:07:05.070683
1731 10:07:05.071011 Set Vref, RX VrefLevel [Byte0]: 62
1732 10:07:05.073901 [Byte1]: 62
1733 10:07:05.078344
1734 10:07:05.078765 Set Vref, RX VrefLevel [Byte0]: 63
1735 10:07:05.081832 [Byte1]: 63
1736 10:07:05.085969
1737 10:07:05.086390 Set Vref, RX VrefLevel [Byte0]: 64
1738 10:07:05.089457 [Byte1]: 64
1739 10:07:05.093457
1740 10:07:05.093877 Set Vref, RX VrefLevel [Byte0]: 65
1741 10:07:05.096765 [Byte1]: 65
1742 10:07:05.101478
1743 10:07:05.101902 Set Vref, RX VrefLevel [Byte0]: 66
1744 10:07:05.104528 [Byte1]: 66
1745 10:07:05.108689
1746 10:07:05.108964 Set Vref, RX VrefLevel [Byte0]: 67
1747 10:07:05.112136 [Byte1]: 67
1748 10:07:05.116336
1749 10:07:05.116490 Set Vref, RX VrefLevel [Byte0]: 68
1750 10:07:05.119547 [Byte1]: 68
1751 10:07:05.124033
1752 10:07:05.124190 Set Vref, RX VrefLevel [Byte0]: 69
1753 10:07:05.127326 [Byte1]: 69
1754 10:07:05.131552
1755 10:07:05.131712 Set Vref, RX VrefLevel [Byte0]: 70
1756 10:07:05.134738 [Byte1]: 70
1757 10:07:05.139378
1758 10:07:05.139533 Set Vref, RX VrefLevel [Byte0]: 71
1759 10:07:05.142549 [Byte1]: 71
1760 10:07:05.146768
1761 10:07:05.147003 Set Vref, RX VrefLevel [Byte0]: 72
1762 10:07:05.150323 [Byte1]: 72
1763 10:07:05.154646
1764 10:07:05.154802 Set Vref, RX VrefLevel [Byte0]: 73
1765 10:07:05.157799 [Byte1]: 73
1766 10:07:05.162122
1767 10:07:05.162284 Set Vref, RX VrefLevel [Byte0]: 74
1768 10:07:05.165517 [Byte1]: 74
1769 10:07:05.169919
1770 10:07:05.170115 Final RX Vref Byte 0 = 59 to rank0
1771 10:07:05.172955 Final RX Vref Byte 1 = 55 to rank0
1772 10:07:05.176612 Final RX Vref Byte 0 = 59 to rank1
1773 10:07:05.179807 Final RX Vref Byte 1 = 55 to rank1==
1774 10:07:05.183014 Dram Type= 6, Freq= 0, CH_1, rank 0
1775 10:07:05.189476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1776 10:07:05.189657 ==
1777 10:07:05.189801 DQS Delay:
1778 10:07:05.189936 DQS0 = 0, DQS1 = 0
1779 10:07:05.193202 DQM Delay:
1780 10:07:05.193382 DQM0 = 81, DQM1 = 71
1781 10:07:05.196259 DQ Delay:
1782 10:07:05.199942 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1783 10:07:05.202948 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1784 10:07:05.206483 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1785 10:07:05.209612 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1786 10:07:05.209793
1787 10:07:05.209934
1788 10:07:05.216132 [DQSOSCAuto] RK0, (LSB)MR18= 0xc16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
1789 10:07:05.219406 CH1 RK0: MR19=606, MR18=C16
1790 10:07:05.226245 CH1_RK0: MR19=0x606, MR18=0xC16, DQSOSC=404, MR23=63, INC=90, DEC=60
1791 10:07:05.226427
1792 10:07:05.229598 ----->DramcWriteLeveling(PI) begin...
1793 10:07:05.229783 ==
1794 10:07:05.232964 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 10:07:05.235965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 10:07:05.236154 ==
1797 10:07:05.239071 Write leveling (Byte 0): 29 => 29
1798 10:07:05.242701 Write leveling (Byte 1): 29 => 29
1799 10:07:05.245635 DramcWriteLeveling(PI) end<-----
1800 10:07:05.245818
1801 10:07:05.245964 ==
1802 10:07:05.249020 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 10:07:05.252741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 10:07:05.253004 ==
1805 10:07:05.256255 [Gating] SW mode calibration
1806 10:07:05.262497 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1807 10:07:05.269094 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1808 10:07:05.272591 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1809 10:07:05.275507 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1810 10:07:05.282708 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1811 10:07:05.285896 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 10:07:05.289123 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 10:07:05.295852 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 10:07:05.299454 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 10:07:05.302320 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 10:07:05.308775 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 10:07:05.312036 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 10:07:05.315310 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 10:07:05.321953 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 10:07:05.325295 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 10:07:05.328525 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 10:07:05.335586 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 10:07:05.338408 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 10:07:05.342141 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1825 10:07:05.348832 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1826 10:07:05.352086 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1827 10:07:05.355342 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 10:07:05.361742 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 10:07:05.365447 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 10:07:05.368921 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 10:07:05.374859 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 10:07:05.378426 0 9 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1833 10:07:05.381832 0 9 4 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
1834 10:07:05.388077 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1835 10:07:05.391390 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 10:07:05.395067 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 10:07:05.401343 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 10:07:05.405268 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 10:07:05.407917 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 10:07:05.414484 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 10:07:05.417889 0 10 4 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (0 1)
1842 10:07:05.421643 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1843 10:07:05.428189 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 10:07:05.431417 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 10:07:05.434665 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 10:07:05.441155 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 10:07:05.444303 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 10:07:05.447494 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 10:07:05.454584 0 11 4 | B1->B0 | 2727 3535 | 0 0 | (0 0) (0 0)
1850 10:07:05.457767 0 11 8 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
1851 10:07:05.460958 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 10:07:05.467370 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 10:07:05.470734 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 10:07:05.474269 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 10:07:05.480894 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 10:07:05.484156 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 10:07:05.487149 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1858 10:07:05.494253 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 10:07:05.497502 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 10:07:05.500647 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 10:07:05.507391 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 10:07:05.510602 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 10:07:05.513802 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 10:07:05.520732 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 10:07:05.524061 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 10:07:05.527358 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 10:07:05.530391 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 10:07:05.537007 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 10:07:05.540165 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 10:07:05.543353 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 10:07:05.550129 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 10:07:05.553408 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 10:07:05.560208 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 10:07:05.563458 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1875 10:07:05.566668 Total UI for P1: 0, mck2ui 16
1876 10:07:05.570002 best dqsien dly found for B0: ( 0, 14, 6)
1877 10:07:05.573401 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 10:07:05.576356 Total UI for P1: 0, mck2ui 16
1879 10:07:05.579664 best dqsien dly found for B1: ( 0, 14, 8)
1880 10:07:05.583315 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1881 10:07:05.586595 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1882 10:07:05.586677
1883 10:07:05.589942 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1884 10:07:05.596808 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1885 10:07:05.596890 [Gating] SW calibration Done
1886 10:07:05.596955 ==
1887 10:07:05.599478 Dram Type= 6, Freq= 0, CH_1, rank 1
1888 10:07:05.605892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1889 10:07:05.605974 ==
1890 10:07:05.606039 RX Vref Scan: 0
1891 10:07:05.606100
1892 10:07:05.609619 RX Vref 0 -> 0, step: 1
1893 10:07:05.609700
1894 10:07:05.612928 RX Delay -130 -> 252, step: 16
1895 10:07:05.616175 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1896 10:07:05.619321 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1897 10:07:05.622973 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1898 10:07:05.629188 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1899 10:07:05.633159 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1900 10:07:05.636038 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1901 10:07:05.639294 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1902 10:07:05.642497 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1903 10:07:05.649359 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1904 10:07:05.652555 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1905 10:07:05.655776 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1906 10:07:05.659095 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1907 10:07:05.662740 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1908 10:07:05.669167 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1909 10:07:05.672445 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1910 10:07:05.675711 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1911 10:07:05.675792 ==
1912 10:07:05.679008 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 10:07:05.682310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1914 10:07:05.685603 ==
1915 10:07:05.685687 DQS Delay:
1916 10:07:05.685753 DQS0 = 0, DQS1 = 0
1917 10:07:05.689126 DQM Delay:
1918 10:07:05.689199 DQM0 = 79, DQM1 = 71
1919 10:07:05.689261 DQ Delay:
1920 10:07:05.692563 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1921 10:07:05.695902 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1922 10:07:05.699449 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1923 10:07:05.702347 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1924 10:07:05.702427
1925 10:07:05.702491
1926 10:07:05.705671 ==
1927 10:07:05.709347 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 10:07:05.712418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 10:07:05.712500 ==
1930 10:07:05.712565
1931 10:07:05.712625
1932 10:07:05.715578 TX Vref Scan disable
1933 10:07:05.715660 == TX Byte 0 ==
1934 10:07:05.722634 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1935 10:07:05.725484 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1936 10:07:05.725565 == TX Byte 1 ==
1937 10:07:05.732687 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1938 10:07:05.735523 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1939 10:07:05.735606 ==
1940 10:07:05.739289 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 10:07:05.742444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 10:07:05.742526 ==
1943 10:07:05.755656 TX Vref=22, minBit 1, minWin=27, winSum=450
1944 10:07:05.758983 TX Vref=24, minBit 1, minWin=27, winSum=450
1945 10:07:05.762351 TX Vref=26, minBit 1, minWin=27, winSum=455
1946 10:07:05.766164 TX Vref=28, minBit 1, minWin=27, winSum=455
1947 10:07:05.769120 TX Vref=30, minBit 1, minWin=27, winSum=453
1948 10:07:05.775405 TX Vref=32, minBit 1, minWin=27, winSum=453
1949 10:07:05.778868 [TxChooseVref] Worse bit 1, Min win 27, Win sum 455, Final Vref 26
1950 10:07:05.779083
1951 10:07:05.782488 Final TX Range 1 Vref 26
1952 10:07:05.782729
1953 10:07:05.782888 ==
1954 10:07:05.785768 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 10:07:05.788844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 10:07:05.791899 ==
1957 10:07:05.792217
1958 10:07:05.792412
1959 10:07:05.792567 TX Vref Scan disable
1960 10:07:05.795600 == TX Byte 0 ==
1961 10:07:05.798541 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1962 10:07:05.805399 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1963 10:07:05.805507 == TX Byte 1 ==
1964 10:07:05.808897 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1965 10:07:05.815069 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1966 10:07:05.815243
1967 10:07:05.815350 [DATLAT]
1968 10:07:05.815446 Freq=800, CH1 RK1
1969 10:07:05.815526
1970 10:07:05.818799 DATLAT Default: 0xa
1971 10:07:05.818928 0, 0xFFFF, sum = 0
1972 10:07:05.822256 1, 0xFFFF, sum = 0
1973 10:07:05.825411 2, 0xFFFF, sum = 0
1974 10:07:05.825882 3, 0xFFFF, sum = 0
1975 10:07:05.829108 4, 0xFFFF, sum = 0
1976 10:07:05.829581 5, 0xFFFF, sum = 0
1977 10:07:05.832368 6, 0xFFFF, sum = 0
1978 10:07:05.832837 7, 0xFFFF, sum = 0
1979 10:07:05.835389 8, 0xFFFF, sum = 0
1980 10:07:05.835861 9, 0x0, sum = 1
1981 10:07:05.838489 10, 0x0, sum = 2
1982 10:07:05.838998 11, 0x0, sum = 3
1983 10:07:05.839384 12, 0x0, sum = 4
1984 10:07:05.842318 best_step = 10
1985 10:07:05.842955
1986 10:07:05.843440 ==
1987 10:07:05.845241 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 10:07:05.848954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 10:07:05.849574 ==
1990 10:07:05.851776 RX Vref Scan: 0
1991 10:07:05.852365
1992 10:07:05.855409 RX Vref 0 -> 0, step: 1
1993 10:07:05.855954
1994 10:07:05.856408 RX Delay -111 -> 252, step: 8
1995 10:07:05.862616 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1996 10:07:05.865763 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1997 10:07:05.868906 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
1998 10:07:05.872431 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1999 10:07:05.875607 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2000 10:07:05.882139 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2001 10:07:05.885817 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2002 10:07:05.889222 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2003 10:07:05.892446 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2004 10:07:05.895453 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2005 10:07:05.902283 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2006 10:07:05.905885 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2007 10:07:05.908974 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2008 10:07:05.912043 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2009 10:07:05.918982 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2010 10:07:05.922100 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2011 10:07:05.922656 ==
2012 10:07:05.925352 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 10:07:05.928593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 10:07:05.929082 ==
2015 10:07:05.931925 DQS Delay:
2016 10:07:05.932337 DQS0 = 0, DQS1 = 0
2017 10:07:05.932716 DQM Delay:
2018 10:07:05.935479 DQM0 = 77, DQM1 = 73
2019 10:07:05.935893 DQ Delay:
2020 10:07:05.938697 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2021 10:07:05.941915 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2022 10:07:05.945337 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2023 10:07:05.948594 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2024 10:07:05.949019
2025 10:07:05.949394
2026 10:07:05.958806 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b34, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
2027 10:07:05.959480 CH1 RK1: MR19=606, MR18=1B34
2028 10:07:05.965220 CH1_RK1: MR19=0x606, MR18=0x1B34, DQSOSC=396, MR23=63, INC=94, DEC=62
2029 10:07:05.968442 [RxdqsGatingPostProcess] freq 800
2030 10:07:05.974866 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2031 10:07:05.978422 Pre-setting of DQS Precalculation
2032 10:07:05.981825 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2033 10:07:05.991621 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2034 10:07:05.998075 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2035 10:07:05.998499
2036 10:07:05.998873
2037 10:07:06.001742 [Calibration Summary] 1600 Mbps
2038 10:07:06.002162 CH 0, Rank 0
2039 10:07:06.004759 SW Impedance : PASS
2040 10:07:06.005181 DUTY Scan : NO K
2041 10:07:06.008287 ZQ Calibration : PASS
2042 10:07:06.011678 Jitter Meter : NO K
2043 10:07:06.012210 CBT Training : PASS
2044 10:07:06.014618 Write leveling : PASS
2045 10:07:06.018474 RX DQS gating : PASS
2046 10:07:06.018993 RX DQ/DQS(RDDQC) : PASS
2047 10:07:06.021610 TX DQ/DQS : PASS
2048 10:07:06.022089 RX DATLAT : PASS
2049 10:07:06.024724 RX DQ/DQS(Engine): PASS
2050 10:07:06.027969 TX OE : NO K
2051 10:07:06.028391 All Pass.
2052 10:07:06.028724
2053 10:07:06.029087 CH 0, Rank 1
2054 10:07:06.031595 SW Impedance : PASS
2055 10:07:06.034744 DUTY Scan : NO K
2056 10:07:06.035335 ZQ Calibration : PASS
2057 10:07:06.038188 Jitter Meter : NO K
2058 10:07:06.041531 CBT Training : PASS
2059 10:07:06.042120 Write leveling : PASS
2060 10:07:06.044778 RX DQS gating : PASS
2061 10:07:06.047767 RX DQ/DQS(RDDQC) : PASS
2062 10:07:06.048188 TX DQ/DQS : PASS
2063 10:07:06.051324 RX DATLAT : PASS
2064 10:07:06.054450 RX DQ/DQS(Engine): PASS
2065 10:07:06.054900 TX OE : NO K
2066 10:07:06.058225 All Pass.
2067 10:07:06.058647
2068 10:07:06.059119 CH 1, Rank 0
2069 10:07:06.060990 SW Impedance : PASS
2070 10:07:06.061415 DUTY Scan : NO K
2071 10:07:06.064812 ZQ Calibration : PASS
2072 10:07:06.067708 Jitter Meter : NO K
2073 10:07:06.068130 CBT Training : PASS
2074 10:07:06.071317 Write leveling : PASS
2075 10:07:06.074465 RX DQS gating : PASS
2076 10:07:06.074953 RX DQ/DQS(RDDQC) : PASS
2077 10:07:06.077528 TX DQ/DQS : PASS
2078 10:07:06.077950 RX DATLAT : PASS
2079 10:07:06.081044 RX DQ/DQS(Engine): PASS
2080 10:07:06.084611 TX OE : NO K
2081 10:07:06.085034 All Pass.
2082 10:07:06.085369
2083 10:07:06.085682 CH 1, Rank 1
2084 10:07:06.087860 SW Impedance : PASS
2085 10:07:06.090952 DUTY Scan : NO K
2086 10:07:06.091375 ZQ Calibration : PASS
2087 10:07:06.094255 Jitter Meter : NO K
2088 10:07:06.097408 CBT Training : PASS
2089 10:07:06.097831 Write leveling : PASS
2090 10:07:06.101075 RX DQS gating : PASS
2091 10:07:06.104017 RX DQ/DQS(RDDQC) : PASS
2092 10:07:06.104099 TX DQ/DQS : PASS
2093 10:07:06.107176 RX DATLAT : PASS
2094 10:07:06.110563 RX DQ/DQS(Engine): PASS
2095 10:07:06.110644 TX OE : NO K
2096 10:07:06.113714 All Pass.
2097 10:07:06.113795
2098 10:07:06.113860 DramC Write-DBI off
2099 10:07:06.116949 PER_BANK_REFRESH: Hybrid Mode
2100 10:07:06.117030 TX_TRACKING: ON
2101 10:07:06.120416 [GetDramInforAfterCalByMRR] Vendor 6.
2102 10:07:06.126888 [GetDramInforAfterCalByMRR] Revision 606.
2103 10:07:06.130405 [GetDramInforAfterCalByMRR] Revision 2 0.
2104 10:07:06.130487 MR0 0x3b3b
2105 10:07:06.130552 MR8 0x5151
2106 10:07:06.133418 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2107 10:07:06.136854
2108 10:07:06.136928 MR0 0x3b3b
2109 10:07:06.136997 MR8 0x5151
2110 10:07:06.140041 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 10:07:06.140111
2112 10:07:06.150238 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2113 10:07:06.153694 [FAST_K] Save calibration result to emmc
2114 10:07:06.157070 [FAST_K] Save calibration result to emmc
2115 10:07:06.160124 dram_init: config_dvfs: 1
2116 10:07:06.163161 dramc_set_vcore_voltage set vcore to 662500
2117 10:07:06.166537 Read voltage for 1200, 2
2118 10:07:06.166610 Vio18 = 0
2119 10:07:06.166672 Vcore = 662500
2120 10:07:06.170524 Vdram = 0
2121 10:07:06.170619 Vddq = 0
2122 10:07:06.170706 Vmddr = 0
2123 10:07:06.176587 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2124 10:07:06.179824 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2125 10:07:06.182922 MEM_TYPE=3, freq_sel=15
2126 10:07:06.186659 sv_algorithm_assistance_LP4_1600
2127 10:07:06.189892 ============ PULL DRAM RESETB DOWN ============
2128 10:07:06.196728 ========== PULL DRAM RESETB DOWN end =========
2129 10:07:06.199811 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2130 10:07:06.203293 ===================================
2131 10:07:06.206596 LPDDR4 DRAM CONFIGURATION
2132 10:07:06.210345 ===================================
2133 10:07:06.210813 EX_ROW_EN[0] = 0x0
2134 10:07:06.213716 EX_ROW_EN[1] = 0x0
2135 10:07:06.214135 LP4Y_EN = 0x0
2136 10:07:06.216825 WORK_FSP = 0x0
2137 10:07:06.217241 WL = 0x4
2138 10:07:06.219917 RL = 0x4
2139 10:07:06.220336 BL = 0x2
2140 10:07:06.223373 RPST = 0x0
2141 10:07:06.223792 RD_PRE = 0x0
2142 10:07:06.226766 WR_PRE = 0x1
2143 10:07:06.227206 WR_PST = 0x0
2144 10:07:06.230268 DBI_WR = 0x0
2145 10:07:06.230682 DBI_RD = 0x0
2146 10:07:06.233356 OTF = 0x1
2147 10:07:06.236838 ===================================
2148 10:07:06.239769 ===================================
2149 10:07:06.240188 ANA top config
2150 10:07:06.243210 ===================================
2151 10:07:06.246759 DLL_ASYNC_EN = 0
2152 10:07:06.249843 ALL_SLAVE_EN = 0
2153 10:07:06.252982 NEW_RANK_MODE = 1
2154 10:07:06.256221 DLL_IDLE_MODE = 1
2155 10:07:06.256640 LP45_APHY_COMB_EN = 1
2156 10:07:06.259814 TX_ODT_DIS = 1
2157 10:07:06.262787 NEW_8X_MODE = 1
2158 10:07:06.266392 ===================================
2159 10:07:06.269844 ===================================
2160 10:07:06.272833 data_rate = 2400
2161 10:07:06.275925 CKR = 1
2162 10:07:06.276357 DQ_P2S_RATIO = 8
2163 10:07:06.280032 ===================================
2164 10:07:06.282765 CA_P2S_RATIO = 8
2165 10:07:06.286094 DQ_CA_OPEN = 0
2166 10:07:06.289244 DQ_SEMI_OPEN = 0
2167 10:07:06.292950 CA_SEMI_OPEN = 0
2168 10:07:06.296114 CA_FULL_RATE = 0
2169 10:07:06.296530 DQ_CKDIV4_EN = 0
2170 10:07:06.299298 CA_CKDIV4_EN = 0
2171 10:07:06.302388 CA_PREDIV_EN = 0
2172 10:07:06.306218 PH8_DLY = 17
2173 10:07:06.309404 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2174 10:07:06.312663 DQ_AAMCK_DIV = 4
2175 10:07:06.313077 CA_AAMCK_DIV = 4
2176 10:07:06.315914 CA_ADMCK_DIV = 4
2177 10:07:06.319024 DQ_TRACK_CA_EN = 0
2178 10:07:06.322650 CA_PICK = 1200
2179 10:07:06.326011 CA_MCKIO = 1200
2180 10:07:06.329088 MCKIO_SEMI = 0
2181 10:07:06.332407 PLL_FREQ = 2366
2182 10:07:06.335900 DQ_UI_PI_RATIO = 32
2183 10:07:06.336374 CA_UI_PI_RATIO = 0
2184 10:07:06.338953 ===================================
2185 10:07:06.342333 ===================================
2186 10:07:06.345912 memory_type:LPDDR4
2187 10:07:06.349136 GP_NUM : 10
2188 10:07:06.349238 SRAM_EN : 1
2189 10:07:06.351743 MD32_EN : 0
2190 10:07:06.355325 ===================================
2191 10:07:06.358786 [ANA_INIT] >>>>>>>>>>>>>>
2192 10:07:06.361981 <<<<<< [CONFIGURE PHASE]: ANA_TX
2193 10:07:06.365242 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2194 10:07:06.368386 ===================================
2195 10:07:06.368468 data_rate = 2400,PCW = 0X5b00
2196 10:07:06.371994 ===================================
2197 10:07:06.375169 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2198 10:07:06.381840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2199 10:07:06.388711 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 10:07:06.391943 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2201 10:07:06.395073 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2202 10:07:06.398505 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2203 10:07:06.401721 [ANA_INIT] flow start
2204 10:07:06.401842 [ANA_INIT] PLL >>>>>>>>
2205 10:07:06.405504 [ANA_INIT] PLL <<<<<<<<
2206 10:07:06.408711 [ANA_INIT] MIDPI >>>>>>>>
2207 10:07:06.411887 [ANA_INIT] MIDPI <<<<<<<<
2208 10:07:06.412037 [ANA_INIT] DLL >>>>>>>>
2209 10:07:06.415144 [ANA_INIT] DLL <<<<<<<<
2210 10:07:06.418335 [ANA_INIT] flow end
2211 10:07:06.421542 ============ LP4 DIFF to SE enter ============
2212 10:07:06.425571 ============ LP4 DIFF to SE exit ============
2213 10:07:06.428647 [ANA_INIT] <<<<<<<<<<<<<
2214 10:07:06.431478 [Flow] Enable top DCM control >>>>>
2215 10:07:06.435006 [Flow] Enable top DCM control <<<<<
2216 10:07:06.438558 Enable DLL master slave shuffle
2217 10:07:06.441678 ==============================================================
2218 10:07:06.444983 Gating Mode config
2219 10:07:06.448373 ==============================================================
2220 10:07:06.451795 Config description:
2221 10:07:06.461933 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2222 10:07:06.468356 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2223 10:07:06.471395 SELPH_MODE 0: By rank 1: By Phase
2224 10:07:06.477981 ==============================================================
2225 10:07:06.481336 GAT_TRACK_EN = 1
2226 10:07:06.484506 RX_GATING_MODE = 2
2227 10:07:06.488242 RX_GATING_TRACK_MODE = 2
2228 10:07:06.491547 SELPH_MODE = 1
2229 10:07:06.494438 PICG_EARLY_EN = 1
2230 10:07:06.498015 VALID_LAT_VALUE = 1
2231 10:07:06.501310 ==============================================================
2232 10:07:06.505140 Enter into Gating configuration >>>>
2233 10:07:06.507989 Exit from Gating configuration <<<<
2234 10:07:06.511190 Enter into DVFS_PRE_config >>>>>
2235 10:07:06.524503 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2236 10:07:06.524927 Exit from DVFS_PRE_config <<<<<
2237 10:07:06.527698 Enter into PICG configuration >>>>
2238 10:07:06.530903 Exit from PICG configuration <<<<
2239 10:07:06.534595 [RX_INPUT] configuration >>>>>
2240 10:07:06.537638 [RX_INPUT] configuration <<<<<
2241 10:07:06.544177 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2242 10:07:06.547636 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2243 10:07:06.553905 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 10:07:06.560819 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 10:07:06.567140 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 10:07:06.574118 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 10:07:06.577341 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2248 10:07:06.580273 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2249 10:07:06.583530 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2250 10:07:06.590461 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2251 10:07:06.593501 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2252 10:07:06.596999 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2253 10:07:06.600239 ===================================
2254 10:07:06.603643 LPDDR4 DRAM CONFIGURATION
2255 10:07:06.606734 ===================================
2256 10:07:06.610892 EX_ROW_EN[0] = 0x0
2257 10:07:06.611313 EX_ROW_EN[1] = 0x0
2258 10:07:06.613454 LP4Y_EN = 0x0
2259 10:07:06.613870 WORK_FSP = 0x0
2260 10:07:06.617043 WL = 0x4
2261 10:07:06.617459 RL = 0x4
2262 10:07:06.620714 BL = 0x2
2263 10:07:06.621132 RPST = 0x0
2264 10:07:06.623407 RD_PRE = 0x0
2265 10:07:06.623826 WR_PRE = 0x1
2266 10:07:06.626774 WR_PST = 0x0
2267 10:07:06.627227 DBI_WR = 0x0
2268 10:07:06.629899 DBI_RD = 0x0
2269 10:07:06.633078 OTF = 0x1
2270 10:07:06.633496 ===================================
2271 10:07:06.640057 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2272 10:07:06.643188 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2273 10:07:06.646653 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2274 10:07:06.649975 ===================================
2275 10:07:06.653508 LPDDR4 DRAM CONFIGURATION
2276 10:07:06.656442 ===================================
2277 10:07:06.659766 EX_ROW_EN[0] = 0x10
2278 10:07:06.660191 EX_ROW_EN[1] = 0x0
2279 10:07:06.663264 LP4Y_EN = 0x0
2280 10:07:06.663682 WORK_FSP = 0x0
2281 10:07:06.666256 WL = 0x4
2282 10:07:06.666674 RL = 0x4
2283 10:07:06.669921 BL = 0x2
2284 10:07:06.670337 RPST = 0x0
2285 10:07:06.673240 RD_PRE = 0x0
2286 10:07:06.673654 WR_PRE = 0x1
2287 10:07:06.676404 WR_PST = 0x0
2288 10:07:06.676900 DBI_WR = 0x0
2289 10:07:06.679459 DBI_RD = 0x0
2290 10:07:06.679877 OTF = 0x1
2291 10:07:06.683108 ===================================
2292 10:07:06.689847 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2293 10:07:06.690259 ==
2294 10:07:06.693028 Dram Type= 6, Freq= 0, CH_0, rank 0
2295 10:07:06.699251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2296 10:07:06.699662 ==
2297 10:07:06.699987 [Duty_Offset_Calibration]
2298 10:07:06.702939 B0:2 B1:0 CA:4
2299 10:07:06.703366
2300 10:07:06.706141 [DutyScan_Calibration_Flow] k_type=0
2301 10:07:06.715052
2302 10:07:06.715342 ==CLK 0==
2303 10:07:06.718539 Final CLK duty delay cell = 0
2304 10:07:06.721465 [0] MAX Duty = 5031%(X100), DQS PI = 12
2305 10:07:06.724762 [0] MIN Duty = 4907%(X100), DQS PI = 40
2306 10:07:06.728418 [0] AVG Duty = 4969%(X100)
2307 10:07:06.728708
2308 10:07:06.731680 CH0 CLK Duty spec in!! Max-Min= 124%
2309 10:07:06.734813 [DutyScan_Calibration_Flow] ====Done====
2310 10:07:06.735214
2311 10:07:06.738196 [DutyScan_Calibration_Flow] k_type=1
2312 10:07:06.753685
2313 10:07:06.754060 ==DQS 0 ==
2314 10:07:06.756692 Final DQS duty delay cell = 0
2315 10:07:06.760028 [0] MAX Duty = 5062%(X100), DQS PI = 12
2316 10:07:06.763668 [0] MIN Duty = 4876%(X100), DQS PI = 50
2317 10:07:06.766780 [0] AVG Duty = 4969%(X100)
2318 10:07:06.767194
2319 10:07:06.767491 ==DQS 1 ==
2320 10:07:06.770147 Final DQS duty delay cell = -4
2321 10:07:06.773175 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2322 10:07:06.776560 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2323 10:07:06.779987 [-4] AVG Duty = 4922%(X100)
2324 10:07:06.780356
2325 10:07:06.783055 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2326 10:07:06.783423
2327 10:07:06.786324 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2328 10:07:06.790063 [DutyScan_Calibration_Flow] ====Done====
2329 10:07:06.790643
2330 10:07:06.793142 [DutyScan_Calibration_Flow] k_type=3
2331 10:07:06.811224
2332 10:07:06.811592 ==DQM 0 ==
2333 10:07:06.814425 Final DQM duty delay cell = 0
2334 10:07:06.817488 [0] MAX Duty = 5124%(X100), DQS PI = 28
2335 10:07:06.821049 [0] MIN Duty = 4876%(X100), DQS PI = 0
2336 10:07:06.821521 [0] AVG Duty = 5000%(X100)
2337 10:07:06.824194
2338 10:07:06.824689 ==DQM 1 ==
2339 10:07:06.827733 Final DQM duty delay cell = 4
2340 10:07:06.831317 [4] MAX Duty = 5124%(X100), DQS PI = 50
2341 10:07:06.834517 [4] MIN Duty = 5031%(X100), DQS PI = 12
2342 10:07:06.834957 [4] AVG Duty = 5077%(X100)
2343 10:07:06.837686
2344 10:07:06.840934 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2345 10:07:06.841441
2346 10:07:06.844118 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2347 10:07:06.848153 [DutyScan_Calibration_Flow] ====Done====
2348 10:07:06.848601
2349 10:07:06.851049 [DutyScan_Calibration_Flow] k_type=2
2350 10:07:06.865965
2351 10:07:06.866453 ==DQ 0 ==
2352 10:07:06.869403 Final DQ duty delay cell = -4
2353 10:07:06.872765 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2354 10:07:06.875698 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2355 10:07:06.879393 [-4] AVG Duty = 4969%(X100)
2356 10:07:06.879880
2357 10:07:06.880243 ==DQ 1 ==
2358 10:07:06.882146 Final DQ duty delay cell = -4
2359 10:07:06.885720 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2360 10:07:06.888996 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2361 10:07:06.892297 [-4] AVG Duty = 4922%(X100)
2362 10:07:06.892753
2363 10:07:06.895824 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2364 10:07:06.896281
2365 10:07:06.898964 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2366 10:07:06.902129 [DutyScan_Calibration_Flow] ====Done====
2367 10:07:06.902540 ==
2368 10:07:06.905589 Dram Type= 6, Freq= 0, CH_1, rank 0
2369 10:07:06.908948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2370 10:07:06.909402 ==
2371 10:07:06.912270 [Duty_Offset_Calibration]
2372 10:07:06.912685 B0:1 B1:-2 CA:0
2373 10:07:06.915354
2374 10:07:06.918617 [DutyScan_Calibration_Flow] k_type=0
2375 10:07:06.926641
2376 10:07:06.927159 ==CLK 0==
2377 10:07:06.929460 Final CLK duty delay cell = 0
2378 10:07:06.933126 [0] MAX Duty = 5062%(X100), DQS PI = 30
2379 10:07:06.936386 [0] MIN Duty = 4876%(X100), DQS PI = 2
2380 10:07:06.936960 [0] AVG Duty = 4969%(X100)
2381 10:07:06.939555
2382 10:07:06.942760 CH1 CLK Duty spec in!! Max-Min= 186%
2383 10:07:06.946046 [DutyScan_Calibration_Flow] ====Done====
2384 10:07:06.946516
2385 10:07:06.949325 [DutyScan_Calibration_Flow] k_type=1
2386 10:07:06.964860
2387 10:07:06.965311 ==DQS 0 ==
2388 10:07:06.968067 Final DQS duty delay cell = -4
2389 10:07:06.971477 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2390 10:07:06.975007 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2391 10:07:06.978006 [-4] AVG Duty = 4969%(X100)
2392 10:07:06.978465
2393 10:07:06.978858 ==DQS 1 ==
2394 10:07:06.981412 Final DQS duty delay cell = 0
2395 10:07:06.984801 [0] MAX Duty = 5062%(X100), DQS PI = 0
2396 10:07:06.988190 [0] MIN Duty = 4875%(X100), DQS PI = 26
2397 10:07:06.991799 [0] AVG Duty = 4968%(X100)
2398 10:07:06.992262
2399 10:07:06.994959 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2400 10:07:06.995442
2401 10:07:06.998334 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2402 10:07:07.001775 [DutyScan_Calibration_Flow] ====Done====
2403 10:07:07.002237
2404 10:07:07.004948 [DutyScan_Calibration_Flow] k_type=3
2405 10:07:07.021572
2406 10:07:07.022186 ==DQM 0 ==
2407 10:07:07.025022 Final DQM duty delay cell = 0
2408 10:07:07.028479 [0] MAX Duty = 5031%(X100), DQS PI = 24
2409 10:07:07.031824 [0] MIN Duty = 4876%(X100), DQS PI = 2
2410 10:07:07.034740 [0] AVG Duty = 4953%(X100)
2411 10:07:07.035262
2412 10:07:07.035600 ==DQM 1 ==
2413 10:07:07.037791 Final DQM duty delay cell = 0
2414 10:07:07.041625 [0] MAX Duty = 5031%(X100), DQS PI = 36
2415 10:07:07.044683 [0] MIN Duty = 4907%(X100), DQS PI = 0
2416 10:07:07.047906 [0] AVG Duty = 4969%(X100)
2417 10:07:07.048328
2418 10:07:07.051018 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2419 10:07:07.051529
2420 10:07:07.054778 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2421 10:07:07.058006 [DutyScan_Calibration_Flow] ====Done====
2422 10:07:07.058426
2423 10:07:07.061120 [DutyScan_Calibration_Flow] k_type=2
2424 10:07:07.078017
2425 10:07:07.078727 ==DQ 0 ==
2426 10:07:07.081643 Final DQ duty delay cell = 0
2427 10:07:07.084340 [0] MAX Duty = 5093%(X100), DQS PI = 20
2428 10:07:07.087513 [0] MIN Duty = 4938%(X100), DQS PI = 54
2429 10:07:07.088152 [0] AVG Duty = 5015%(X100)
2430 10:07:07.090953
2431 10:07:07.091624 ==DQ 1 ==
2432 10:07:07.094227 Final DQ duty delay cell = 0
2433 10:07:07.097809 [0] MAX Duty = 5125%(X100), DQS PI = 36
2434 10:07:07.101405 [0] MIN Duty = 4969%(X100), DQS PI = 26
2435 10:07:07.101869 [0] AVG Duty = 5047%(X100)
2436 10:07:07.104252
2437 10:07:07.107710 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2438 10:07:07.108435
2439 10:07:07.110785 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2440 10:07:07.114124 [DutyScan_Calibration_Flow] ====Done====
2441 10:07:07.117739 nWR fixed to 30
2442 10:07:07.118255 [ModeRegInit_LP4] CH0 RK0
2443 10:07:07.120867 [ModeRegInit_LP4] CH0 RK1
2444 10:07:07.123945 [ModeRegInit_LP4] CH1 RK0
2445 10:07:07.127733 [ModeRegInit_LP4] CH1 RK1
2446 10:07:07.128239 match AC timing 7
2447 10:07:07.134257 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2448 10:07:07.137540 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2449 10:07:07.140723 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2450 10:07:07.147415 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2451 10:07:07.150667 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2452 10:07:07.151410 ==
2453 10:07:07.154391 Dram Type= 6, Freq= 0, CH_0, rank 0
2454 10:07:07.157864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2455 10:07:07.158398 ==
2456 10:07:07.164365 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2457 10:07:07.170425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2458 10:07:07.177767 [CA 0] Center 40 (10~71) winsize 62
2459 10:07:07.181253 [CA 1] Center 39 (9~70) winsize 62
2460 10:07:07.184247 [CA 2] Center 36 (6~66) winsize 61
2461 10:07:07.187764 [CA 3] Center 35 (5~66) winsize 62
2462 10:07:07.191178 [CA 4] Center 34 (4~65) winsize 62
2463 10:07:07.194596 [CA 5] Center 33 (3~63) winsize 61
2464 10:07:07.195239
2465 10:07:07.197743 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2466 10:07:07.198194
2467 10:07:07.201063 [CATrainingPosCal] consider 1 rank data
2468 10:07:07.204566 u2DelayCellTimex100 = 270/100 ps
2469 10:07:07.207730 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2470 10:07:07.214287 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2471 10:07:07.217407 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2472 10:07:07.220823 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2473 10:07:07.224546 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2474 10:07:07.227643 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2475 10:07:07.228082
2476 10:07:07.230937 CA PerBit enable=1, Macro0, CA PI delay=33
2477 10:07:07.231373
2478 10:07:07.234483 [CBTSetCACLKResult] CA Dly = 33
2479 10:07:07.237571 CS Dly: 7 (0~38)
2480 10:07:07.237986 ==
2481 10:07:07.241139 Dram Type= 6, Freq= 0, CH_0, rank 1
2482 10:07:07.243949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2483 10:07:07.244390 ==
2484 10:07:07.251127 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2485 10:07:07.254338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2486 10:07:07.263890 [CA 0] Center 40 (10~71) winsize 62
2487 10:07:07.267410 [CA 1] Center 40 (10~70) winsize 61
2488 10:07:07.270865 [CA 2] Center 35 (5~66) winsize 62
2489 10:07:07.273985 [CA 3] Center 35 (5~66) winsize 62
2490 10:07:07.277291 [CA 4] Center 34 (4~65) winsize 62
2491 10:07:07.280906 [CA 5] Center 33 (3~63) winsize 61
2492 10:07:07.281366
2493 10:07:07.283689 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2494 10:07:07.284130
2495 10:07:07.287308 [CATrainingPosCal] consider 2 rank data
2496 10:07:07.290591 u2DelayCellTimex100 = 270/100 ps
2497 10:07:07.293871 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2498 10:07:07.300511 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2499 10:07:07.303503 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2500 10:07:07.306768 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2501 10:07:07.310539 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2502 10:07:07.313622 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2503 10:07:07.314042
2504 10:07:07.316764 CA PerBit enable=1, Macro0, CA PI delay=33
2505 10:07:07.317258
2506 10:07:07.320300 [CBTSetCACLKResult] CA Dly = 33
2507 10:07:07.323737 CS Dly: 8 (0~40)
2508 10:07:07.324198
2509 10:07:07.326895 ----->DramcWriteLeveling(PI) begin...
2510 10:07:07.327318 ==
2511 10:07:07.330421 Dram Type= 6, Freq= 0, CH_0, rank 0
2512 10:07:07.333562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 10:07:07.333983 ==
2514 10:07:07.336708 Write leveling (Byte 0): 31 => 31
2515 10:07:07.340398 Write leveling (Byte 1): 29 => 29
2516 10:07:07.343669 DramcWriteLeveling(PI) end<-----
2517 10:07:07.344086
2518 10:07:07.344414 ==
2519 10:07:07.346742 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 10:07:07.350560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 10:07:07.351032 ==
2522 10:07:07.353306 [Gating] SW mode calibration
2523 10:07:07.359934 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2524 10:07:07.367013 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2525 10:07:07.370212 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 10:07:07.373626 0 15 4 | B1->B0 | 2525 3232 | 1 1 | (0 0) (1 1)
2527 10:07:07.380071 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 10:07:07.383240 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 10:07:07.386776 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 10:07:07.393411 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 10:07:07.396382 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 10:07:07.399827 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2533 10:07:07.406211 1 0 0 | B1->B0 | 3232 2929 | 0 0 | (0 1) (0 0)
2534 10:07:07.409516 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2535 10:07:07.413174 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 10:07:07.419855 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 10:07:07.423165 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 10:07:07.426388 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 10:07:07.433013 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 10:07:07.436146 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2541 10:07:07.439310 1 1 0 | B1->B0 | 2827 3434 | 1 0 | (0 0) (0 0)
2542 10:07:07.446147 1 1 4 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
2543 10:07:07.449450 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 10:07:07.452653 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 10:07:07.459818 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 10:07:07.462601 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 10:07:07.466331 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 10:07:07.472357 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 10:07:07.476052 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2550 10:07:07.479387 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2551 10:07:07.485796 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 10:07:07.489057 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 10:07:07.492137 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 10:07:07.498821 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 10:07:07.502317 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 10:07:07.505675 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 10:07:07.512244 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 10:07:07.515585 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 10:07:07.519046 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 10:07:07.525765 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 10:07:07.529016 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 10:07:07.532146 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 10:07:07.538766 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 10:07:07.541962 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 10:07:07.545181 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2566 10:07:07.548385 Total UI for P1: 0, mck2ui 16
2567 10:07:07.552110 best dqsien dly found for B0: ( 1, 3, 30)
2568 10:07:07.558310 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2569 10:07:07.561981 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 10:07:07.565198 Total UI for P1: 0, mck2ui 16
2571 10:07:07.568699 best dqsien dly found for B1: ( 1, 4, 2)
2572 10:07:07.571839 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2573 10:07:07.575243 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2574 10:07:07.575699
2575 10:07:07.578477 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2576 10:07:07.581586 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2577 10:07:07.584708 [Gating] SW calibration Done
2578 10:07:07.585118 ==
2579 10:07:07.588429 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 10:07:07.591559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 10:07:07.591989 ==
2582 10:07:07.594774 RX Vref Scan: 0
2583 10:07:07.595224
2584 10:07:07.597906 RX Vref 0 -> 0, step: 1
2585 10:07:07.598320
2586 10:07:07.598646 RX Delay -40 -> 252, step: 8
2587 10:07:07.604735 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2588 10:07:07.607755 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2589 10:07:07.611175 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2590 10:07:07.614761 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2591 10:07:07.618188 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2592 10:07:07.624701 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2593 10:07:07.628026 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2594 10:07:07.631339 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2595 10:07:07.635032 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2596 10:07:07.637717 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2597 10:07:07.644786 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2598 10:07:07.647825 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2599 10:07:07.651305 iDelay=200, Bit 12, Center 107 (40 ~ 175) 136
2600 10:07:07.654364 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2601 10:07:07.658237 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2602 10:07:07.664607 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2603 10:07:07.665023 ==
2604 10:07:07.667902 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 10:07:07.671125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 10:07:07.671540 ==
2607 10:07:07.671870 DQS Delay:
2608 10:07:07.674364 DQS0 = 0, DQS1 = 0
2609 10:07:07.674776 DQM Delay:
2610 10:07:07.678088 DQM0 = 112, DQM1 = 102
2611 10:07:07.678497 DQ Delay:
2612 10:07:07.680939 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2613 10:07:07.684566 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2614 10:07:07.687916 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2615 10:07:07.691134 DQ12 =107, DQ13 =111, DQ14 =115, DQ15 =111
2616 10:07:07.691541
2617 10:07:07.691864
2618 10:07:07.694372 ==
2619 10:07:07.694785 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 10:07:07.701226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 10:07:07.701642 ==
2622 10:07:07.701970
2623 10:07:07.702274
2624 10:07:07.703948 TX Vref Scan disable
2625 10:07:07.704360 == TX Byte 0 ==
2626 10:07:07.707585 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2627 10:07:07.713927 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2628 10:07:07.714339 == TX Byte 1 ==
2629 10:07:07.717268 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2630 10:07:07.724159 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2631 10:07:07.724698 ==
2632 10:07:07.727170 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 10:07:07.730764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 10:07:07.731237 ==
2635 10:07:07.742921 TX Vref=22, minBit 5, minWin=25, winSum=416
2636 10:07:07.746240 TX Vref=24, minBit 5, minWin=25, winSum=422
2637 10:07:07.749714 TX Vref=26, minBit 10, minWin=26, winSum=433
2638 10:07:07.752710 TX Vref=28, minBit 8, minWin=26, winSum=435
2639 10:07:07.756359 TX Vref=30, minBit 14, minWin=26, winSum=435
2640 10:07:07.762564 TX Vref=32, minBit 10, minWin=26, winSum=433
2641 10:07:07.765807 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 28
2642 10:07:07.766262
2643 10:07:07.769467 Final TX Range 1 Vref 28
2644 10:07:07.769922
2645 10:07:07.770279 ==
2646 10:07:07.772664 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 10:07:07.775989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 10:07:07.779237 ==
2649 10:07:07.779694
2650 10:07:07.780049
2651 10:07:07.780384 TX Vref Scan disable
2652 10:07:07.783043 == TX Byte 0 ==
2653 10:07:07.786312 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2654 10:07:07.792413 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2655 10:07:07.792903 == TX Byte 1 ==
2656 10:07:07.796468 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2657 10:07:07.802638 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2658 10:07:07.803128
2659 10:07:07.803495 [DATLAT]
2660 10:07:07.803835 Freq=1200, CH0 RK0
2661 10:07:07.804164
2662 10:07:07.806124 DATLAT Default: 0xd
2663 10:07:07.806577 0, 0xFFFF, sum = 0
2664 10:07:07.809417 1, 0xFFFF, sum = 0
2665 10:07:07.812400 2, 0xFFFF, sum = 0
2666 10:07:07.812883 3, 0xFFFF, sum = 0
2667 10:07:07.816020 4, 0xFFFF, sum = 0
2668 10:07:07.816487 5, 0xFFFF, sum = 0
2669 10:07:07.819084 6, 0xFFFF, sum = 0
2670 10:07:07.819542 7, 0xFFFF, sum = 0
2671 10:07:07.822513 8, 0xFFFF, sum = 0
2672 10:07:07.823030 9, 0xFFFF, sum = 0
2673 10:07:07.825798 10, 0xFFFF, sum = 0
2674 10:07:07.826260 11, 0xFFFF, sum = 0
2675 10:07:07.829293 12, 0x0, sum = 1
2676 10:07:07.829773 13, 0x0, sum = 2
2677 10:07:07.832213 14, 0x0, sum = 3
2678 10:07:07.832808 15, 0x0, sum = 4
2679 10:07:07.835688 best_step = 13
2680 10:07:07.836151
2681 10:07:07.836516 ==
2682 10:07:07.839427 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 10:07:07.842825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 10:07:07.843301 ==
2685 10:07:07.843705 RX Vref Scan: 1
2686 10:07:07.845766
2687 10:07:07.846280 Set Vref Range= 32 -> 127
2688 10:07:07.846640
2689 10:07:07.848976 RX Vref 32 -> 127, step: 1
2690 10:07:07.849396
2691 10:07:07.852546 RX Delay -37 -> 252, step: 4
2692 10:07:07.852987
2693 10:07:07.855463 Set Vref, RX VrefLevel [Byte0]: 32
2694 10:07:07.859084 [Byte1]: 32
2695 10:07:07.859506
2696 10:07:07.862414 Set Vref, RX VrefLevel [Byte0]: 33
2697 10:07:07.865489 [Byte1]: 33
2698 10:07:07.869193
2699 10:07:07.869613 Set Vref, RX VrefLevel [Byte0]: 34
2700 10:07:07.872922 [Byte1]: 34
2701 10:07:07.877234
2702 10:07:07.877720 Set Vref, RX VrefLevel [Byte0]: 35
2703 10:07:07.880717 [Byte1]: 35
2704 10:07:07.885604
2705 10:07:07.886020 Set Vref, RX VrefLevel [Byte0]: 36
2706 10:07:07.888747 [Byte1]: 36
2707 10:07:07.893337
2708 10:07:07.893756 Set Vref, RX VrefLevel [Byte0]: 37
2709 10:07:07.896449 [Byte1]: 37
2710 10:07:07.901228
2711 10:07:07.901779 Set Vref, RX VrefLevel [Byte0]: 38
2712 10:07:07.904507 [Byte1]: 38
2713 10:07:07.909222
2714 10:07:07.909794 Set Vref, RX VrefLevel [Byte0]: 39
2715 10:07:07.912929 [Byte1]: 39
2716 10:07:07.917696
2717 10:07:07.918145 Set Vref, RX VrefLevel [Byte0]: 40
2718 10:07:07.920484 [Byte1]: 40
2719 10:07:07.925547
2720 10:07:07.926092 Set Vref, RX VrefLevel [Byte0]: 41
2721 10:07:07.928976 [Byte1]: 41
2722 10:07:07.933302
2723 10:07:07.933736 Set Vref, RX VrefLevel [Byte0]: 42
2724 10:07:07.936682 [Byte1]: 42
2725 10:07:07.941439
2726 10:07:07.941844 Set Vref, RX VrefLevel [Byte0]: 43
2727 10:07:07.944696 [Byte1]: 43
2728 10:07:07.949467
2729 10:07:07.950050 Set Vref, RX VrefLevel [Byte0]: 44
2730 10:07:07.952954 [Byte1]: 44
2731 10:07:07.957860
2732 10:07:07.958318 Set Vref, RX VrefLevel [Byte0]: 45
2733 10:07:07.960697 [Byte1]: 45
2734 10:07:07.965199
2735 10:07:07.965787 Set Vref, RX VrefLevel [Byte0]: 46
2736 10:07:07.968758 [Byte1]: 46
2737 10:07:07.973261
2738 10:07:07.973894 Set Vref, RX VrefLevel [Byte0]: 47
2739 10:07:07.976455 [Byte1]: 47
2740 10:07:07.981363
2741 10:07:07.981814 Set Vref, RX VrefLevel [Byte0]: 48
2742 10:07:07.984523 [Byte1]: 48
2743 10:07:07.989204
2744 10:07:07.989835 Set Vref, RX VrefLevel [Byte0]: 49
2745 10:07:07.992447 [Byte1]: 49
2746 10:07:07.997508
2747 10:07:07.998056 Set Vref, RX VrefLevel [Byte0]: 50
2748 10:07:08.000688 [Byte1]: 50
2749 10:07:08.005160
2750 10:07:08.005712 Set Vref, RX VrefLevel [Byte0]: 51
2751 10:07:08.008331 [Byte1]: 51
2752 10:07:08.013178
2753 10:07:08.013661 Set Vref, RX VrefLevel [Byte0]: 52
2754 10:07:08.016849 [Byte1]: 52
2755 10:07:08.021555
2756 10:07:08.022003 Set Vref, RX VrefLevel [Byte0]: 53
2757 10:07:08.024766 [Byte1]: 53
2758 10:07:08.029140
2759 10:07:08.029550 Set Vref, RX VrefLevel [Byte0]: 54
2760 10:07:08.032565 [Byte1]: 54
2761 10:07:08.037270
2762 10:07:08.037703 Set Vref, RX VrefLevel [Byte0]: 55
2763 10:07:08.040855 [Byte1]: 55
2764 10:07:08.045644
2765 10:07:08.046122 Set Vref, RX VrefLevel [Byte0]: 56
2766 10:07:08.048652 [Byte1]: 56
2767 10:07:08.053285
2768 10:07:08.053796 Set Vref, RX VrefLevel [Byte0]: 57
2769 10:07:08.057050 [Byte1]: 57
2770 10:07:08.061077
2771 10:07:08.064597 Set Vref, RX VrefLevel [Byte0]: 58
2772 10:07:08.067632 [Byte1]: 58
2773 10:07:08.068222
2774 10:07:08.071327 Set Vref, RX VrefLevel [Byte0]: 59
2775 10:07:08.074289 [Byte1]: 59
2776 10:07:08.074951
2777 10:07:08.077661 Set Vref, RX VrefLevel [Byte0]: 60
2778 10:07:08.080904 [Byte1]: 60
2779 10:07:08.085322
2780 10:07:08.085866 Set Vref, RX VrefLevel [Byte0]: 61
2781 10:07:08.088470 [Byte1]: 61
2782 10:07:08.093208
2783 10:07:08.093792 Set Vref, RX VrefLevel [Byte0]: 62
2784 10:07:08.096461 [Byte1]: 62
2785 10:07:08.101460
2786 10:07:08.102020 Set Vref, RX VrefLevel [Byte0]: 63
2787 10:07:08.104699 [Byte1]: 63
2788 10:07:08.109466
2789 10:07:08.109886 Set Vref, RX VrefLevel [Byte0]: 64
2790 10:07:08.112639 [Byte1]: 64
2791 10:07:08.117398
2792 10:07:08.117834 Set Vref, RX VrefLevel [Byte0]: 65
2793 10:07:08.120429 [Byte1]: 65
2794 10:07:08.125453
2795 10:07:08.125896 Set Vref, RX VrefLevel [Byte0]: 66
2796 10:07:08.128462 [Byte1]: 66
2797 10:07:08.133460
2798 10:07:08.133880 Set Vref, RX VrefLevel [Byte0]: 67
2799 10:07:08.136795 [Byte1]: 67
2800 10:07:08.141172
2801 10:07:08.141588 Set Vref, RX VrefLevel [Byte0]: 68
2802 10:07:08.144764 [Byte1]: 68
2803 10:07:08.149575
2804 10:07:08.150034 Set Vref, RX VrefLevel [Byte0]: 69
2805 10:07:08.152540 [Byte1]: 69
2806 10:07:08.157440
2807 10:07:08.157902 Set Vref, RX VrefLevel [Byte0]: 70
2808 10:07:08.161001 [Byte1]: 70
2809 10:07:08.165594
2810 10:07:08.166149 Set Vref, RX VrefLevel [Byte0]: 71
2811 10:07:08.168872 [Byte1]: 71
2812 10:07:08.173444
2813 10:07:08.173922 Set Vref, RX VrefLevel [Byte0]: 72
2814 10:07:08.176929 [Byte1]: 72
2815 10:07:08.181554
2816 10:07:08.182020 Set Vref, RX VrefLevel [Byte0]: 73
2817 10:07:08.185055 [Byte1]: 73
2818 10:07:08.189609
2819 10:07:08.190164 Set Vref, RX VrefLevel [Byte0]: 74
2820 10:07:08.192633 [Byte1]: 74
2821 10:07:08.197712
2822 10:07:08.198263 Final RX Vref Byte 0 = 61 to rank0
2823 10:07:08.201319 Final RX Vref Byte 1 = 57 to rank0
2824 10:07:08.204228 Final RX Vref Byte 0 = 61 to rank1
2825 10:07:08.207789 Final RX Vref Byte 1 = 57 to rank1==
2826 10:07:08.210774 Dram Type= 6, Freq= 0, CH_0, rank 0
2827 10:07:08.217529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2828 10:07:08.218028 ==
2829 10:07:08.218498 DQS Delay:
2830 10:07:08.220823 DQS0 = 0, DQS1 = 0
2831 10:07:08.221328 DQM Delay:
2832 10:07:08.221723 DQM0 = 112, DQM1 = 102
2833 10:07:08.224032 DQ Delay:
2834 10:07:08.227451 DQ0 =112, DQ1 =110, DQ2 =112, DQ3 =108
2835 10:07:08.230339 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2836 10:07:08.233631 DQ8 =94, DQ9 =86, DQ10 =104, DQ11 =94
2837 10:07:08.237511 DQ12 =108, DQ13 =108, DQ14 =116, DQ15 =108
2838 10:07:08.237965
2839 10:07:08.238325
2840 10:07:08.247274 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcfc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2841 10:07:08.247764 CH0 RK0: MR19=303, MR18=FCFC
2842 10:07:08.253617 CH0_RK0: MR19=0x303, MR18=0xFCFC, DQSOSC=411, MR23=63, INC=38, DEC=25
2843 10:07:08.254076
2844 10:07:08.257035 ----->DramcWriteLeveling(PI) begin...
2845 10:07:08.257503 ==
2846 10:07:08.260484 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 10:07:08.266914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 10:07:08.267403 ==
2849 10:07:08.270718 Write leveling (Byte 0): 32 => 32
2850 10:07:08.271356 Write leveling (Byte 1): 28 => 28
2851 10:07:08.273593 DramcWriteLeveling(PI) end<-----
2852 10:07:08.274051
2853 10:07:08.277513 ==
2854 10:07:08.277978 Dram Type= 6, Freq= 0, CH_0, rank 1
2855 10:07:08.283504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2856 10:07:08.283967 ==
2857 10:07:08.286940 [Gating] SW mode calibration
2858 10:07:08.293399 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2859 10:07:08.296571 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2860 10:07:08.303163 0 15 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
2861 10:07:08.306279 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 10:07:08.309541 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 10:07:08.315995 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 10:07:08.319457 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 10:07:08.322667 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 10:07:08.329657 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2867 10:07:08.332943 0 15 28 | B1->B0 | 3434 2424 | 1 1 | (1 1) (1 0)
2868 10:07:08.336000 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
2869 10:07:08.342525 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 10:07:08.345700 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 10:07:08.349239 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 10:07:08.356211 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 10:07:08.359232 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 10:07:08.362446 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2875 10:07:08.368931 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2876 10:07:08.372229 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2877 10:07:08.376197 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 10:07:08.382437 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 10:07:08.385553 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 10:07:08.388970 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 10:07:08.395471 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 10:07:08.399063 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 10:07:08.402308 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2884 10:07:08.408788 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2885 10:07:08.412521 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 10:07:08.415581 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 10:07:08.422297 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 10:07:08.425766 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 10:07:08.429112 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 10:07:08.435415 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 10:07:08.438761 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 10:07:08.442077 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 10:07:08.445579 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 10:07:08.452351 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 10:07:08.455330 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 10:07:08.459386 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 10:07:08.465709 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 10:07:08.468802 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2899 10:07:08.472145 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2900 10:07:08.478788 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2901 10:07:08.481821 Total UI for P1: 0, mck2ui 16
2902 10:07:08.485344 best dqsien dly found for B0: ( 1, 3, 26)
2903 10:07:08.489078 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 10:07:08.491864 Total UI for P1: 0, mck2ui 16
2905 10:07:08.495526 best dqsien dly found for B1: ( 1, 4, 0)
2906 10:07:08.498501 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2907 10:07:08.502169 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2908 10:07:08.502634
2909 10:07:08.505009 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2910 10:07:08.508381 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2911 10:07:08.512035 [Gating] SW calibration Done
2912 10:07:08.512496 ==
2913 10:07:08.515192 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 10:07:08.518332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 10:07:08.521491 ==
2916 10:07:08.521910 RX Vref Scan: 0
2917 10:07:08.522246
2918 10:07:08.525113 RX Vref 0 -> 0, step: 1
2919 10:07:08.525553
2920 10:07:08.528190 RX Delay -40 -> 252, step: 8
2921 10:07:08.531796 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2922 10:07:08.534908 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2923 10:07:08.538914 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2924 10:07:08.541830 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2925 10:07:08.548171 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2926 10:07:08.551382 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2927 10:07:08.555106 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2928 10:07:08.558121 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2929 10:07:08.561911 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2930 10:07:08.568267 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2931 10:07:08.571269 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2932 10:07:08.574721 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2933 10:07:08.578356 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2934 10:07:08.581269 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2935 10:07:08.588553 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2936 10:07:08.591382 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2937 10:07:08.591802 ==
2938 10:07:08.594927 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 10:07:08.598271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 10:07:08.598689 ==
2941 10:07:08.601488 DQS Delay:
2942 10:07:08.601901 DQS0 = 0, DQS1 = 0
2943 10:07:08.602230 DQM Delay:
2944 10:07:08.604457 DQM0 = 112, DQM1 = 102
2945 10:07:08.604872 DQ Delay:
2946 10:07:08.607896 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2947 10:07:08.611405 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2948 10:07:08.614475 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2949 10:07:08.620549 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =111
2950 10:07:08.620636
2951 10:07:08.620704
2952 10:07:08.620767 ==
2953 10:07:08.624251 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 10:07:08.627435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 10:07:08.627537 ==
2956 10:07:08.627617
2957 10:07:08.627691
2958 10:07:08.630729 TX Vref Scan disable
2959 10:07:08.630839 == TX Byte 0 ==
2960 10:07:08.637256 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2961 10:07:08.640927 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2962 10:07:08.641149 == TX Byte 1 ==
2963 10:07:08.647208 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2964 10:07:08.650471 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2965 10:07:08.650655 ==
2966 10:07:08.653686 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 10:07:08.657403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 10:07:08.657602 ==
2969 10:07:08.670308 TX Vref=22, minBit 8, minWin=25, winSum=421
2970 10:07:08.673731 TX Vref=24, minBit 5, minWin=26, winSum=427
2971 10:07:08.676859 TX Vref=26, minBit 1, minWin=26, winSum=432
2972 10:07:08.680281 TX Vref=28, minBit 8, minWin=26, winSum=433
2973 10:07:08.683694 TX Vref=30, minBit 8, minWin=26, winSum=436
2974 10:07:08.690453 TX Vref=32, minBit 8, minWin=26, winSum=438
2975 10:07:08.693893 [TxChooseVref] Worse bit 8, Min win 26, Win sum 438, Final Vref 32
2976 10:07:08.694349
2977 10:07:08.696796 Final TX Range 1 Vref 32
2978 10:07:08.697255
2979 10:07:08.697616 ==
2980 10:07:08.700342 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 10:07:08.703712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 10:07:08.704172 ==
2983 10:07:08.707128
2984 10:07:08.707627
2985 10:07:08.708024 TX Vref Scan disable
2986 10:07:08.710129 == TX Byte 0 ==
2987 10:07:08.713582 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2988 10:07:08.720244 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2989 10:07:08.720704 == TX Byte 1 ==
2990 10:07:08.723459 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2991 10:07:08.730477 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2992 10:07:08.730966
2993 10:07:08.731330 [DATLAT]
2994 10:07:08.731664 Freq=1200, CH0 RK1
2995 10:07:08.731995
2996 10:07:08.733675 DATLAT Default: 0xd
2997 10:07:08.734133 0, 0xFFFF, sum = 0
2998 10:07:08.736819 1, 0xFFFF, sum = 0
2999 10:07:08.740125 2, 0xFFFF, sum = 0
3000 10:07:08.740591 3, 0xFFFF, sum = 0
3001 10:07:08.743212 4, 0xFFFF, sum = 0
3002 10:07:08.743679 5, 0xFFFF, sum = 0
3003 10:07:08.746690 6, 0xFFFF, sum = 0
3004 10:07:08.747176 7, 0xFFFF, sum = 0
3005 10:07:08.750289 8, 0xFFFF, sum = 0
3006 10:07:08.750756 9, 0xFFFF, sum = 0
3007 10:07:08.753877 10, 0xFFFF, sum = 0
3008 10:07:08.754343 11, 0xFFFF, sum = 0
3009 10:07:08.756688 12, 0x0, sum = 1
3010 10:07:08.757224 13, 0x0, sum = 2
3011 10:07:08.760173 14, 0x0, sum = 3
3012 10:07:08.760639 15, 0x0, sum = 4
3013 10:07:08.761103 best_step = 13
3014 10:07:08.763244
3015 10:07:08.763785 ==
3016 10:07:08.766464 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 10:07:08.770087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 10:07:08.770622 ==
3019 10:07:08.771102 RX Vref Scan: 0
3020 10:07:08.771548
3021 10:07:08.773508 RX Vref 0 -> 0, step: 1
3022 10:07:08.774163
3023 10:07:08.776452 RX Delay -37 -> 252, step: 4
3024 10:07:08.780102 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3025 10:07:08.786358 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3026 10:07:08.789786 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3027 10:07:08.793285 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3028 10:07:08.796857 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3029 10:07:08.800200 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3030 10:07:08.806788 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3031 10:07:08.810248 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3032 10:07:08.813620 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3033 10:07:08.816272 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3034 10:07:08.819835 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3035 10:07:08.826305 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3036 10:07:08.829589 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3037 10:07:08.833239 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3038 10:07:08.836246 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3039 10:07:08.839346 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3040 10:07:08.842739 ==
3041 10:07:08.845881 Dram Type= 6, Freq= 0, CH_0, rank 1
3042 10:07:08.849469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 10:07:08.849601 ==
3044 10:07:08.849730 DQS Delay:
3045 10:07:08.852446 DQS0 = 0, DQS1 = 0
3046 10:07:08.852589 DQM Delay:
3047 10:07:08.856462 DQM0 = 111, DQM1 = 102
3048 10:07:08.856619 DQ Delay:
3049 10:07:08.859438 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3050 10:07:08.862747 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3051 10:07:08.865885 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3052 10:07:08.869183 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =110
3053 10:07:08.869339
3054 10:07:08.869460
3055 10:07:08.879130 [DQSOSCAuto] RK1, (LSB)MR18= 0xff6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3056 10:07:08.882357 CH0 RK1: MR19=403, MR18=FF6
3057 10:07:08.885919 CH0_RK1: MR19=0x403, MR18=0xFF6, DQSOSC=404, MR23=63, INC=40, DEC=26
3058 10:07:08.889493 [RxdqsGatingPostProcess] freq 1200
3059 10:07:08.895702 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3060 10:07:08.899521 best DQS0 dly(2T, 0.5T) = (0, 11)
3061 10:07:08.902426 best DQS1 dly(2T, 0.5T) = (0, 12)
3062 10:07:08.905836 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3063 10:07:08.909037 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3064 10:07:08.912638 best DQS0 dly(2T, 0.5T) = (0, 11)
3065 10:07:08.915922 best DQS1 dly(2T, 0.5T) = (0, 12)
3066 10:07:08.919099 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3067 10:07:08.922384 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3068 10:07:08.922996 Pre-setting of DQS Precalculation
3069 10:07:08.929174 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3070 10:07:08.929731 ==
3071 10:07:08.932252 Dram Type= 6, Freq= 0, CH_1, rank 0
3072 10:07:08.935902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 10:07:08.936462 ==
3074 10:07:08.942207 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3075 10:07:08.948736 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3076 10:07:08.956279 [CA 0] Center 37 (8~67) winsize 60
3077 10:07:08.959963 [CA 1] Center 38 (8~68) winsize 61
3078 10:07:08.963007 [CA 2] Center 34 (4~64) winsize 61
3079 10:07:08.966489 [CA 3] Center 33 (3~64) winsize 62
3080 10:07:08.969684 [CA 4] Center 34 (4~64) winsize 61
3081 10:07:08.973517 [CA 5] Center 33 (3~63) winsize 61
3082 10:07:08.974078
3083 10:07:08.976284 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3084 10:07:08.976746
3085 10:07:08.979607 [CATrainingPosCal] consider 1 rank data
3086 10:07:08.983069 u2DelayCellTimex100 = 270/100 ps
3087 10:07:08.985960 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3088 10:07:08.992741 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3089 10:07:08.995794 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3090 10:07:08.999263 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3091 10:07:09.002573 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 10:07:09.006015 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3093 10:07:09.006489
3094 10:07:09.009278 CA PerBit enable=1, Macro0, CA PI delay=33
3095 10:07:09.009751
3096 10:07:09.012704 [CBTSetCACLKResult] CA Dly = 33
3097 10:07:09.013176 CS Dly: 6 (0~37)
3098 10:07:09.016181 ==
3099 10:07:09.018922 Dram Type= 6, Freq= 0, CH_1, rank 1
3100 10:07:09.022375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 10:07:09.022886 ==
3102 10:07:09.026161 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3103 10:07:09.032437 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3104 10:07:09.041850 [CA 0] Center 37 (7~67) winsize 61
3105 10:07:09.045190 [CA 1] Center 37 (7~68) winsize 62
3106 10:07:09.048337 [CA 2] Center 34 (4~65) winsize 62
3107 10:07:09.052031 [CA 3] Center 33 (3~64) winsize 62
3108 10:07:09.055232 [CA 4] Center 34 (4~65) winsize 62
3109 10:07:09.058725 [CA 5] Center 33 (3~63) winsize 61
3110 10:07:09.059338
3111 10:07:09.061616 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3112 10:07:09.062181
3113 10:07:09.065125 [CATrainingPosCal] consider 2 rank data
3114 10:07:09.068510 u2DelayCellTimex100 = 270/100 ps
3115 10:07:09.071739 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3116 10:07:09.078493 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3117 10:07:09.081496 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3118 10:07:09.084638 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3119 10:07:09.088585 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3120 10:07:09.091624 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3121 10:07:09.092194
3122 10:07:09.094691 CA PerBit enable=1, Macro0, CA PI delay=33
3123 10:07:09.095293
3124 10:07:09.098243 [CBTSetCACLKResult] CA Dly = 33
3125 10:07:09.098809 CS Dly: 7 (0~40)
3126 10:07:09.101153
3127 10:07:09.105052 ----->DramcWriteLeveling(PI) begin...
3128 10:07:09.105753 ==
3129 10:07:09.108321 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 10:07:09.111088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 10:07:09.111568 ==
3132 10:07:09.114654 Write leveling (Byte 0): 26 => 26
3133 10:07:09.118000 Write leveling (Byte 1): 29 => 29
3134 10:07:09.121002 DramcWriteLeveling(PI) end<-----
3135 10:07:09.121603
3136 10:07:09.122124 ==
3137 10:07:09.124911 Dram Type= 6, Freq= 0, CH_1, rank 0
3138 10:07:09.128367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3139 10:07:09.128923 ==
3140 10:07:09.131346 [Gating] SW mode calibration
3141 10:07:09.138191 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3142 10:07:09.144409 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3143 10:07:09.147871 0 15 0 | B1->B0 | 2b2b 2424 | 1 0 | (0 0) (0 0)
3144 10:07:09.151411 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 10:07:09.157791 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 10:07:09.160893 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 10:07:09.164778 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 10:07:09.171335 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 10:07:09.174334 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 10:07:09.177507 0 15 28 | B1->B0 | 2b2b 3131 | 0 0 | (0 0) (0 1)
3151 10:07:09.184334 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 10:07:09.188134 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 10:07:09.190819 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 10:07:09.197880 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 10:07:09.201086 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 10:07:09.204043 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 10:07:09.210752 1 0 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
3158 10:07:09.214385 1 0 28 | B1->B0 | 3a3a 3030 | 1 1 | (0 0) (0 0)
3159 10:07:09.217351 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 10:07:09.224031 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 10:07:09.227249 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 10:07:09.230533 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 10:07:09.234574 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 10:07:09.240853 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 10:07:09.244132 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 10:07:09.247287 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3167 10:07:09.254045 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3168 10:07:09.257294 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 10:07:09.261062 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 10:07:09.267315 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 10:07:09.270797 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 10:07:09.273740 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 10:07:09.280300 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 10:07:09.284110 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 10:07:09.287140 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 10:07:09.293877 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 10:07:09.296733 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 10:07:09.300711 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 10:07:09.307179 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 10:07:09.310294 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 10:07:09.313425 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 10:07:09.320454 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3183 10:07:09.323140 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 10:07:09.326624 Total UI for P1: 0, mck2ui 16
3185 10:07:09.330197 best dqsien dly found for B0: ( 1, 3, 28)
3186 10:07:09.333408 Total UI for P1: 0, mck2ui 16
3187 10:07:09.336963 best dqsien dly found for B1: ( 1, 3, 28)
3188 10:07:09.340000 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3189 10:07:09.343451 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3190 10:07:09.343916
3191 10:07:09.346795 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3192 10:07:09.349941 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3193 10:07:09.353251 [Gating] SW calibration Done
3194 10:07:09.353712 ==
3195 10:07:09.356539 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 10:07:09.360047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 10:07:09.363381 ==
3198 10:07:09.363839 RX Vref Scan: 0
3199 10:07:09.364205
3200 10:07:09.366576 RX Vref 0 -> 0, step: 1
3201 10:07:09.367055
3202 10:07:09.369843 RX Delay -40 -> 252, step: 8
3203 10:07:09.373054 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3204 10:07:09.376605 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3205 10:07:09.379531 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3206 10:07:09.383546 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3207 10:07:09.390060 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3208 10:07:09.393205 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3209 10:07:09.396447 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3210 10:07:09.399749 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3211 10:07:09.403185 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3212 10:07:09.409636 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3213 10:07:09.413247 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3214 10:07:09.416721 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3215 10:07:09.419560 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3216 10:07:09.423167 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3217 10:07:09.429554 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3218 10:07:09.433033 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3219 10:07:09.433590 ==
3220 10:07:09.436304 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 10:07:09.439344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 10:07:09.439801 ==
3223 10:07:09.442778 DQS Delay:
3224 10:07:09.443291 DQS0 = 0, DQS1 = 0
3225 10:07:09.443653 DQM Delay:
3226 10:07:09.445700 DQM0 = 113, DQM1 = 106
3227 10:07:09.446152 DQ Delay:
3228 10:07:09.449467 DQ0 =115, DQ1 =107, DQ2 =103, DQ3 =111
3229 10:07:09.452840 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3230 10:07:09.456089 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =103
3231 10:07:09.462748 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3232 10:07:09.463267
3233 10:07:09.463633
3234 10:07:09.463975 ==
3235 10:07:09.465912 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 10:07:09.469176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 10:07:09.469648 ==
3238 10:07:09.470020
3239 10:07:09.470358
3240 10:07:09.472231 TX Vref Scan disable
3241 10:07:09.472692 == TX Byte 0 ==
3242 10:07:09.479046 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3243 10:07:09.482334 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3244 10:07:09.482798 == TX Byte 1 ==
3245 10:07:09.489184 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3246 10:07:09.492706 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3247 10:07:09.493266 ==
3248 10:07:09.495820 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 10:07:09.499020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 10:07:09.499484 ==
3251 10:07:09.511902 TX Vref=22, minBit 8, minWin=24, winSum=408
3252 10:07:09.515733 TX Vref=24, minBit 8, minWin=25, winSum=416
3253 10:07:09.518585 TX Vref=26, minBit 9, minWin=25, winSum=422
3254 10:07:09.522066 TX Vref=28, minBit 11, minWin=25, winSum=424
3255 10:07:09.525061 TX Vref=30, minBit 9, minWin=25, winSum=424
3256 10:07:09.532354 TX Vref=32, minBit 9, minWin=25, winSum=424
3257 10:07:09.534922 [TxChooseVref] Worse bit 11, Min win 25, Win sum 424, Final Vref 28
3258 10:07:09.535481
3259 10:07:09.538267 Final TX Range 1 Vref 28
3260 10:07:09.538726
3261 10:07:09.539122 ==
3262 10:07:09.541975 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 10:07:09.545160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 10:07:09.548059 ==
3265 10:07:09.548518
3266 10:07:09.548880
3267 10:07:09.549220 TX Vref Scan disable
3268 10:07:09.551827 == TX Byte 0 ==
3269 10:07:09.554790 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3270 10:07:09.561769 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3271 10:07:09.562371 == TX Byte 1 ==
3272 10:07:09.565336 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3273 10:07:09.571635 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3274 10:07:09.572178
3275 10:07:09.572545 [DATLAT]
3276 10:07:09.572880 Freq=1200, CH1 RK0
3277 10:07:09.573208
3278 10:07:09.575021 DATLAT Default: 0xd
3279 10:07:09.578584 0, 0xFFFF, sum = 0
3280 10:07:09.579179 1, 0xFFFF, sum = 0
3281 10:07:09.581630 2, 0xFFFF, sum = 0
3282 10:07:09.582116 3, 0xFFFF, sum = 0
3283 10:07:09.585190 4, 0xFFFF, sum = 0
3284 10:07:09.585751 5, 0xFFFF, sum = 0
3285 10:07:09.588049 6, 0xFFFF, sum = 0
3286 10:07:09.588567 7, 0xFFFF, sum = 0
3287 10:07:09.591767 8, 0xFFFF, sum = 0
3288 10:07:09.592235 9, 0xFFFF, sum = 0
3289 10:07:09.594932 10, 0xFFFF, sum = 0
3290 10:07:09.595398 11, 0xFFFF, sum = 0
3291 10:07:09.598008 12, 0x0, sum = 1
3292 10:07:09.598476 13, 0x0, sum = 2
3293 10:07:09.601682 14, 0x0, sum = 3
3294 10:07:09.602140 15, 0x0, sum = 4
3295 10:07:09.604640 best_step = 13
3296 10:07:09.605087
3297 10:07:09.605441 ==
3298 10:07:09.607812 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 10:07:09.611056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 10:07:09.611506 ==
3301 10:07:09.611862 RX Vref Scan: 1
3302 10:07:09.614269
3303 10:07:09.614713 Set Vref Range= 32 -> 127
3304 10:07:09.615089
3305 10:07:09.618009 RX Vref 32 -> 127, step: 1
3306 10:07:09.618454
3307 10:07:09.621030 RX Delay -21 -> 252, step: 4
3308 10:07:09.621478
3309 10:07:09.624819 Set Vref, RX VrefLevel [Byte0]: 32
3310 10:07:09.627922 [Byte1]: 32
3311 10:07:09.628368
3312 10:07:09.631214 Set Vref, RX VrefLevel [Byte0]: 33
3313 10:07:09.634430 [Byte1]: 33
3314 10:07:09.638480
3315 10:07:09.639037 Set Vref, RX VrefLevel [Byte0]: 34
3316 10:07:09.641625 [Byte1]: 34
3317 10:07:09.646148
3318 10:07:09.646593 Set Vref, RX VrefLevel [Byte0]: 35
3319 10:07:09.649338 [Byte1]: 35
3320 10:07:09.654193
3321 10:07:09.655029 Set Vref, RX VrefLevel [Byte0]: 36
3322 10:07:09.657417 [Byte1]: 36
3323 10:07:09.662075
3324 10:07:09.662521 Set Vref, RX VrefLevel [Byte0]: 37
3325 10:07:09.665407 [Byte1]: 37
3326 10:07:09.669858
3327 10:07:09.670303 Set Vref, RX VrefLevel [Byte0]: 38
3328 10:07:09.673274 [Byte1]: 38
3329 10:07:09.678161
3330 10:07:09.678605 Set Vref, RX VrefLevel [Byte0]: 39
3331 10:07:09.680845 [Byte1]: 39
3332 10:07:09.685733
3333 10:07:09.686178 Set Vref, RX VrefLevel [Byte0]: 40
3334 10:07:09.689315 [Byte1]: 40
3335 10:07:09.693802
3336 10:07:09.694248 Set Vref, RX VrefLevel [Byte0]: 41
3337 10:07:09.697016 [Byte1]: 41
3338 10:07:09.701783
3339 10:07:09.702229 Set Vref, RX VrefLevel [Byte0]: 42
3340 10:07:09.704801 [Byte1]: 42
3341 10:07:09.709368
3342 10:07:09.709813 Set Vref, RX VrefLevel [Byte0]: 43
3343 10:07:09.712603 [Byte1]: 43
3344 10:07:09.717224
3345 10:07:09.717669 Set Vref, RX VrefLevel [Byte0]: 44
3346 10:07:09.720403 [Byte1]: 44
3347 10:07:09.725445
3348 10:07:09.725851 Set Vref, RX VrefLevel [Byte0]: 45
3349 10:07:09.728449 [Byte1]: 45
3350 10:07:09.733259
3351 10:07:09.733702 Set Vref, RX VrefLevel [Byte0]: 46
3352 10:07:09.736493 [Byte1]: 46
3353 10:07:09.741269
3354 10:07:09.741713 Set Vref, RX VrefLevel [Byte0]: 47
3355 10:07:09.744465 [Byte1]: 47
3356 10:07:09.749065
3357 10:07:09.749509 Set Vref, RX VrefLevel [Byte0]: 48
3358 10:07:09.752407 [Byte1]: 48
3359 10:07:09.757070
3360 10:07:09.757515 Set Vref, RX VrefLevel [Byte0]: 49
3361 10:07:09.760449 [Byte1]: 49
3362 10:07:09.764814
3363 10:07:09.765261 Set Vref, RX VrefLevel [Byte0]: 50
3364 10:07:09.768260 [Byte1]: 50
3365 10:07:09.773082
3366 10:07:09.773537 Set Vref, RX VrefLevel [Byte0]: 51
3367 10:07:09.776401 [Byte1]: 51
3368 10:07:09.780648
3369 10:07:09.781096 Set Vref, RX VrefLevel [Byte0]: 52
3370 10:07:09.784108 [Byte1]: 52
3371 10:07:09.788949
3372 10:07:09.789393 Set Vref, RX VrefLevel [Byte0]: 53
3373 10:07:09.791877 [Byte1]: 53
3374 10:07:09.796675
3375 10:07:09.797120 Set Vref, RX VrefLevel [Byte0]: 54
3376 10:07:09.799871 [Byte1]: 54
3377 10:07:09.804735
3378 10:07:09.805236 Set Vref, RX VrefLevel [Byte0]: 55
3379 10:07:09.807860 [Byte1]: 55
3380 10:07:09.812319
3381 10:07:09.812735 Set Vref, RX VrefLevel [Byte0]: 56
3382 10:07:09.816301 [Byte1]: 56
3383 10:07:09.820393
3384 10:07:09.820835 Set Vref, RX VrefLevel [Byte0]: 57
3385 10:07:09.823585 [Byte1]: 57
3386 10:07:09.828368
3387 10:07:09.828815 Set Vref, RX VrefLevel [Byte0]: 58
3388 10:07:09.831791 [Byte1]: 58
3389 10:07:09.836016
3390 10:07:09.836480 Set Vref, RX VrefLevel [Byte0]: 59
3391 10:07:09.839825 [Byte1]: 59
3392 10:07:09.844218
3393 10:07:09.844717 Set Vref, RX VrefLevel [Byte0]: 60
3394 10:07:09.847370 [Byte1]: 60
3395 10:07:09.852193
3396 10:07:09.852641 Set Vref, RX VrefLevel [Byte0]: 61
3397 10:07:09.855156 [Byte1]: 61
3398 10:07:09.860095
3399 10:07:09.860557 Set Vref, RX VrefLevel [Byte0]: 62
3400 10:07:09.862975 [Byte1]: 62
3401 10:07:09.868082
3402 10:07:09.868542 Set Vref, RX VrefLevel [Byte0]: 63
3403 10:07:09.870824 [Byte1]: 63
3404 10:07:09.875719
3405 10:07:09.879318 Set Vref, RX VrefLevel [Byte0]: 64
3406 10:07:09.882142 [Byte1]: 64
3407 10:07:09.882893
3408 10:07:09.885210 Set Vref, RX VrefLevel [Byte0]: 65
3409 10:07:09.888340 [Byte1]: 65
3410 10:07:09.888821
3411 10:07:09.892014 Set Vref, RX VrefLevel [Byte0]: 66
3412 10:07:09.895052 [Byte1]: 66
3413 10:07:09.899978
3414 10:07:09.900609 Set Vref, RX VrefLevel [Byte0]: 67
3415 10:07:09.902530 [Byte1]: 67
3416 10:07:09.907530
3417 10:07:09.907985 Final RX Vref Byte 0 = 58 to rank0
3418 10:07:09.910725 Final RX Vref Byte 1 = 48 to rank0
3419 10:07:09.913952 Final RX Vref Byte 0 = 58 to rank1
3420 10:07:09.917407 Final RX Vref Byte 1 = 48 to rank1==
3421 10:07:09.920815 Dram Type= 6, Freq= 0, CH_1, rank 0
3422 10:07:09.927296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3423 10:07:09.927722 ==
3424 10:07:09.928053 DQS Delay:
3425 10:07:09.930192 DQS0 = 0, DQS1 = 0
3426 10:07:09.930272 DQM Delay:
3427 10:07:09.930337 DQM0 = 114, DQM1 = 105
3428 10:07:09.933665 DQ Delay:
3429 10:07:09.937020 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =112
3430 10:07:09.940143 DQ4 =112, DQ5 =124, DQ6 =124, DQ7 =112
3431 10:07:09.943580 DQ8 =92, DQ9 =100, DQ10 =104, DQ11 =100
3432 10:07:09.946631 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3433 10:07:09.946747
3434 10:07:09.946857
3435 10:07:09.956858 [DQSOSCAuto] RK0, (LSB)MR18= 0xeef5, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3436 10:07:09.956971 CH1 RK0: MR19=303, MR18=EEF5
3437 10:07:09.963144 CH1_RK0: MR19=0x303, MR18=0xEEF5, DQSOSC=414, MR23=63, INC=38, DEC=25
3438 10:07:09.963233
3439 10:07:09.966558 ----->DramcWriteLeveling(PI) begin...
3440 10:07:09.966658 ==
3441 10:07:09.969907 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 10:07:09.976347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 10:07:09.976449 ==
3444 10:07:09.980017 Write leveling (Byte 0): 25 => 25
3445 10:07:09.983296 Write leveling (Byte 1): 27 => 27
3446 10:07:09.983372 DramcWriteLeveling(PI) end<-----
3447 10:07:09.983436
3448 10:07:09.986987 ==
3449 10:07:09.989504 Dram Type= 6, Freq= 0, CH_1, rank 1
3450 10:07:09.993430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3451 10:07:09.993512 ==
3452 10:07:09.996600 [Gating] SW mode calibration
3453 10:07:10.003284 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3454 10:07:10.006117 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3455 10:07:10.012878 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 10:07:10.016064 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 10:07:10.019407 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 10:07:10.025966 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 10:07:10.029403 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 10:07:10.032496 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3461 10:07:10.039411 0 15 24 | B1->B0 | 3333 2828 | 1 0 | (1 0) (0 0)
3462 10:07:10.042766 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3463 10:07:10.046456 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 10:07:10.052828 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 10:07:10.056077 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 10:07:10.059292 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 10:07:10.066012 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 10:07:10.069344 1 0 20 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
3469 10:07:10.072562 1 0 24 | B1->B0 | 3030 4646 | 0 0 | (1 1) (0 0)
3470 10:07:10.078893 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3471 10:07:10.082364 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 10:07:10.085398 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 10:07:10.091886 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 10:07:10.095547 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 10:07:10.098999 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 10:07:10.105323 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 10:07:10.108327 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3478 10:07:10.111890 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3479 10:07:10.118566 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 10:07:10.121663 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 10:07:10.124867 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 10:07:10.132104 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 10:07:10.135159 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 10:07:10.138444 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 10:07:10.144725 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 10:07:10.148069 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 10:07:10.151683 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 10:07:10.158063 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 10:07:10.161328 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 10:07:10.164455 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 10:07:10.170931 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 10:07:10.174435 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3493 10:07:10.177876 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3494 10:07:10.184689 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3495 10:07:10.187614 Total UI for P1: 0, mck2ui 16
3496 10:07:10.191383 best dqsien dly found for B0: ( 1, 3, 22)
3497 10:07:10.194127 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 10:07:10.197468 Total UI for P1: 0, mck2ui 16
3499 10:07:10.200686 best dqsien dly found for B1: ( 1, 3, 26)
3500 10:07:10.204584 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3501 10:07:10.207743 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3502 10:07:10.207916
3503 10:07:10.210867 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3504 10:07:10.213880 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3505 10:07:10.217453 [Gating] SW calibration Done
3506 10:07:10.217729 ==
3507 10:07:10.220669 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 10:07:10.227349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 10:07:10.227753 ==
3510 10:07:10.228101 RX Vref Scan: 0
3511 10:07:10.228417
3512 10:07:10.230501 RX Vref 0 -> 0, step: 1
3513 10:07:10.231018
3514 10:07:10.234007 RX Delay -40 -> 252, step: 8
3515 10:07:10.236958 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3516 10:07:10.240760 iDelay=200, Bit 1, Center 103 (32 ~ 175) 144
3517 10:07:10.243702 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3518 10:07:10.247428 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3519 10:07:10.253737 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3520 10:07:10.256998 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3521 10:07:10.260225 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3522 10:07:10.263542 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3523 10:07:10.266817 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3524 10:07:10.273307 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3525 10:07:10.276490 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3526 10:07:10.280484 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3527 10:07:10.283112 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3528 10:07:10.289515 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3529 10:07:10.293035 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3530 10:07:10.296513 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3531 10:07:10.296625 ==
3532 10:07:10.299457 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 10:07:10.303107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 10:07:10.303181 ==
3535 10:07:10.306339 DQS Delay:
3536 10:07:10.306411 DQS0 = 0, DQS1 = 0
3537 10:07:10.309482 DQM Delay:
3538 10:07:10.309563 DQM0 = 109, DQM1 = 107
3539 10:07:10.312531 DQ Delay:
3540 10:07:10.315917 DQ0 =115, DQ1 =103, DQ2 =99, DQ3 =107
3541 10:07:10.319323 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3542 10:07:10.322422 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3543 10:07:10.325855 DQ12 =115, DQ13 =111, DQ14 =115, DQ15 =115
3544 10:07:10.325961
3545 10:07:10.326031
3546 10:07:10.326092 ==
3547 10:07:10.329123 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 10:07:10.332446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 10:07:10.332528 ==
3550 10:07:10.332593
3551 10:07:10.332651
3552 10:07:10.335588 TX Vref Scan disable
3553 10:07:10.339033 == TX Byte 0 ==
3554 10:07:10.342640 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3555 10:07:10.345514 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3556 10:07:10.349060 == TX Byte 1 ==
3557 10:07:10.352143 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3558 10:07:10.355500 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3559 10:07:10.355609 ==
3560 10:07:10.358792 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 10:07:10.365181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 10:07:10.365263 ==
3563 10:07:10.376099 TX Vref=22, minBit 1, minWin=26, winSum=424
3564 10:07:10.379372 TX Vref=24, minBit 0, minWin=26, winSum=426
3565 10:07:10.382539 TX Vref=26, minBit 8, minWin=25, winSum=427
3566 10:07:10.385460 TX Vref=28, minBit 8, minWin=26, winSum=433
3567 10:07:10.388803 TX Vref=30, minBit 1, minWin=27, winSum=438
3568 10:07:10.395494 TX Vref=32, minBit 1, minWin=26, winSum=429
3569 10:07:10.399089 [TxChooseVref] Worse bit 1, Min win 27, Win sum 438, Final Vref 30
3570 10:07:10.399181
3571 10:07:10.402542 Final TX Range 1 Vref 30
3572 10:07:10.402630
3573 10:07:10.402700 ==
3574 10:07:10.405372 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 10:07:10.409061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 10:07:10.412141 ==
3577 10:07:10.412229
3578 10:07:10.412299
3579 10:07:10.412362 TX Vref Scan disable
3580 10:07:10.415331 == TX Byte 0 ==
3581 10:07:10.418814 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3582 10:07:10.425560 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3583 10:07:10.425659 == TX Byte 1 ==
3584 10:07:10.428594 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3585 10:07:10.435543 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3586 10:07:10.435659
3587 10:07:10.435753 [DATLAT]
3588 10:07:10.435842 Freq=1200, CH1 RK1
3589 10:07:10.435929
3590 10:07:10.438715 DATLAT Default: 0xd
3591 10:07:10.442062 0, 0xFFFF, sum = 0
3592 10:07:10.442274 1, 0xFFFF, sum = 0
3593 10:07:10.445460 2, 0xFFFF, sum = 0
3594 10:07:10.445661 3, 0xFFFF, sum = 0
3595 10:07:10.448637 4, 0xFFFF, sum = 0
3596 10:07:10.448811 5, 0xFFFF, sum = 0
3597 10:07:10.452119 6, 0xFFFF, sum = 0
3598 10:07:10.452320 7, 0xFFFF, sum = 0
3599 10:07:10.455172 8, 0xFFFF, sum = 0
3600 10:07:10.455374 9, 0xFFFF, sum = 0
3601 10:07:10.458635 10, 0xFFFF, sum = 0
3602 10:07:10.458900 11, 0xFFFF, sum = 0
3603 10:07:10.461920 12, 0x0, sum = 1
3604 10:07:10.462354 13, 0x0, sum = 2
3605 10:07:10.465378 14, 0x0, sum = 3
3606 10:07:10.465750 15, 0x0, sum = 4
3607 10:07:10.468390 best_step = 13
3608 10:07:10.468801
3609 10:07:10.469143 ==
3610 10:07:10.471607 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 10:07:10.474809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 10:07:10.475227 ==
3613 10:07:10.478219 RX Vref Scan: 0
3614 10:07:10.478537
3615 10:07:10.478797 RX Vref 0 -> 0, step: 1
3616 10:07:10.479061
3617 10:07:10.481872 RX Delay -21 -> 252, step: 4
3618 10:07:10.488305 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3619 10:07:10.491440 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3620 10:07:10.494714 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3621 10:07:10.498170 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3622 10:07:10.501629 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3623 10:07:10.507916 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3624 10:07:10.510820 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3625 10:07:10.514453 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3626 10:07:10.517791 iDelay=195, Bit 8, Center 96 (35 ~ 158) 124
3627 10:07:10.520956 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3628 10:07:10.527502 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3629 10:07:10.530798 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3630 10:07:10.534038 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3631 10:07:10.537163 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3632 10:07:10.543751 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
3633 10:07:10.547376 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3634 10:07:10.547459 ==
3635 10:07:10.550616 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 10:07:10.553773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 10:07:10.553871 ==
3638 10:07:10.557046 DQS Delay:
3639 10:07:10.557126 DQS0 = 0, DQS1 = 0
3640 10:07:10.557191 DQM Delay:
3641 10:07:10.560141 DQM0 = 111, DQM1 = 108
3642 10:07:10.560222 DQ Delay:
3643 10:07:10.563817 DQ0 =114, DQ1 =108, DQ2 =102, DQ3 =108
3644 10:07:10.566670 DQ4 =108, DQ5 =120, DQ6 =122, DQ7 =110
3645 10:07:10.573342 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3646 10:07:10.576678 DQ12 =114, DQ13 =114, DQ14 =114, DQ15 =116
3647 10:07:10.576793
3648 10:07:10.576873
3649 10:07:10.583048 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa0a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3650 10:07:10.586786 CH1 RK1: MR19=304, MR18=FA0A
3651 10:07:10.593344 CH1_RK1: MR19=0x304, MR18=0xFA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3652 10:07:10.596446 [RxdqsGatingPostProcess] freq 1200
3653 10:07:10.603551 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3654 10:07:10.606502 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 10:07:10.606698 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 10:07:10.609535 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 10:07:10.613242 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 10:07:10.615985 best DQS0 dly(2T, 0.5T) = (0, 11)
3659 10:07:10.619620 best DQS1 dly(2T, 0.5T) = (0, 11)
3660 10:07:10.623376 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3661 10:07:10.626628 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3662 10:07:10.629560 Pre-setting of DQS Precalculation
3663 10:07:10.636901 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3664 10:07:10.642663 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3665 10:07:10.649596 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3666 10:07:10.650063
3667 10:07:10.650435
3668 10:07:10.652419 [Calibration Summary] 2400 Mbps
3669 10:07:10.652884 CH 0, Rank 0
3670 10:07:10.656088 SW Impedance : PASS
3671 10:07:10.659401 DUTY Scan : NO K
3672 10:07:10.659865 ZQ Calibration : PASS
3673 10:07:10.663110 Jitter Meter : NO K
3674 10:07:10.665968 CBT Training : PASS
3675 10:07:10.666431 Write leveling : PASS
3676 10:07:10.669295 RX DQS gating : PASS
3677 10:07:10.672459 RX DQ/DQS(RDDQC) : PASS
3678 10:07:10.672932 TX DQ/DQS : PASS
3679 10:07:10.675733 RX DATLAT : PASS
3680 10:07:10.678896 RX DQ/DQS(Engine): PASS
3681 10:07:10.679406 TX OE : NO K
3682 10:07:10.682590 All Pass.
3683 10:07:10.683321
3684 10:07:10.683739 CH 0, Rank 1
3685 10:07:10.685860 SW Impedance : PASS
3686 10:07:10.686334 DUTY Scan : NO K
3687 10:07:10.688759 ZQ Calibration : PASS
3688 10:07:10.692028 Jitter Meter : NO K
3689 10:07:10.692505 CBT Training : PASS
3690 10:07:10.695245 Write leveling : PASS
3691 10:07:10.698952 RX DQS gating : PASS
3692 10:07:10.699425 RX DQ/DQS(RDDQC) : PASS
3693 10:07:10.702127 TX DQ/DQS : PASS
3694 10:07:10.702618 RX DATLAT : PASS
3695 10:07:10.705673 RX DQ/DQS(Engine): PASS
3696 10:07:10.708593 TX OE : NO K
3697 10:07:10.709057 All Pass.
3698 10:07:10.709490
3699 10:07:10.709902 CH 1, Rank 0
3700 10:07:10.711923 SW Impedance : PASS
3701 10:07:10.715098 DUTY Scan : NO K
3702 10:07:10.715669 ZQ Calibration : PASS
3703 10:07:10.718468 Jitter Meter : NO K
3704 10:07:10.721782 CBT Training : PASS
3705 10:07:10.722316 Write leveling : PASS
3706 10:07:10.725206 RX DQS gating : PASS
3707 10:07:10.728245 RX DQ/DQS(RDDQC) : PASS
3708 10:07:10.728896 TX DQ/DQS : PASS
3709 10:07:10.731581 RX DATLAT : PASS
3710 10:07:10.734994 RX DQ/DQS(Engine): PASS
3711 10:07:10.735456 TX OE : NO K
3712 10:07:10.738789 All Pass.
3713 10:07:10.739363
3714 10:07:10.739904 CH 1, Rank 1
3715 10:07:10.741863 SW Impedance : PASS
3716 10:07:10.742417 DUTY Scan : NO K
3717 10:07:10.745164 ZQ Calibration : PASS
3718 10:07:10.748146 Jitter Meter : NO K
3719 10:07:10.748701 CBT Training : PASS
3720 10:07:10.751616 Write leveling : PASS
3721 10:07:10.754652 RX DQS gating : PASS
3722 10:07:10.755163 RX DQ/DQS(RDDQC) : PASS
3723 10:07:10.758266 TX DQ/DQS : PASS
3724 10:07:10.761509 RX DATLAT : PASS
3725 10:07:10.761942 RX DQ/DQS(Engine): PASS
3726 10:07:10.765123 TX OE : NO K
3727 10:07:10.765738 All Pass.
3728 10:07:10.766266
3729 10:07:10.767996 DramC Write-DBI off
3730 10:07:10.771611 PER_BANK_REFRESH: Hybrid Mode
3731 10:07:10.772186 TX_TRACKING: ON
3732 10:07:10.781463 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3733 10:07:10.784726 [FAST_K] Save calibration result to emmc
3734 10:07:10.787763 dramc_set_vcore_voltage set vcore to 650000
3735 10:07:10.791081 Read voltage for 600, 5
3736 10:07:10.791300 Vio18 = 0
3737 10:07:10.791473 Vcore = 650000
3738 10:07:10.794229 Vdram = 0
3739 10:07:10.794518 Vddq = 0
3740 10:07:10.794768 Vmddr = 0
3741 10:07:10.801042 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3742 10:07:10.804116 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3743 10:07:10.807441 MEM_TYPE=3, freq_sel=19
3744 10:07:10.810622 sv_algorithm_assistance_LP4_1600
3745 10:07:10.813840 ============ PULL DRAM RESETB DOWN ============
3746 10:07:10.817178 ========== PULL DRAM RESETB DOWN end =========
3747 10:07:10.823617 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3748 10:07:10.827503 ===================================
3749 10:07:10.830076 LPDDR4 DRAM CONFIGURATION
3750 10:07:10.833470 ===================================
3751 10:07:10.833765 EX_ROW_EN[0] = 0x0
3752 10:07:10.836865 EX_ROW_EN[1] = 0x0
3753 10:07:10.837108 LP4Y_EN = 0x0
3754 10:07:10.840325 WORK_FSP = 0x0
3755 10:07:10.840544 WL = 0x2
3756 10:07:10.843488 RL = 0x2
3757 10:07:10.843708 BL = 0x2
3758 10:07:10.846699 RPST = 0x0
3759 10:07:10.846982 RD_PRE = 0x0
3760 10:07:10.850006 WR_PRE = 0x1
3761 10:07:10.853093 WR_PST = 0x0
3762 10:07:10.853342 DBI_WR = 0x0
3763 10:07:10.856554 DBI_RD = 0x0
3764 10:07:10.856779 OTF = 0x1
3765 10:07:10.859883 ===================================
3766 10:07:10.863225 ===================================
3767 10:07:10.866164 ANA top config
3768 10:07:10.869868 ===================================
3769 10:07:10.869945 DLL_ASYNC_EN = 0
3770 10:07:10.873110 ALL_SLAVE_EN = 1
3771 10:07:10.876354 NEW_RANK_MODE = 1
3772 10:07:10.879234 DLL_IDLE_MODE = 1
3773 10:07:10.879307 LP45_APHY_COMB_EN = 1
3774 10:07:10.882563 TX_ODT_DIS = 1
3775 10:07:10.885893 NEW_8X_MODE = 1
3776 10:07:10.889076 ===================================
3777 10:07:10.892445 ===================================
3778 10:07:10.895722 data_rate = 1200
3779 10:07:10.899147 CKR = 1
3780 10:07:10.902649 DQ_P2S_RATIO = 8
3781 10:07:10.905799 ===================================
3782 10:07:10.905881 CA_P2S_RATIO = 8
3783 10:07:10.908898 DQ_CA_OPEN = 0
3784 10:07:10.912186 DQ_SEMI_OPEN = 0
3785 10:07:10.915503 CA_SEMI_OPEN = 0
3786 10:07:10.919171 CA_FULL_RATE = 0
3787 10:07:10.922431 DQ_CKDIV4_EN = 1
3788 10:07:10.922512 CA_CKDIV4_EN = 1
3789 10:07:10.925967 CA_PREDIV_EN = 0
3790 10:07:10.929195 PH8_DLY = 0
3791 10:07:10.932227 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3792 10:07:10.935657 DQ_AAMCK_DIV = 4
3793 10:07:10.939193 CA_AAMCK_DIV = 4
3794 10:07:10.939274 CA_ADMCK_DIV = 4
3795 10:07:10.941827 DQ_TRACK_CA_EN = 0
3796 10:07:10.945422 CA_PICK = 600
3797 10:07:10.949095 CA_MCKIO = 600
3798 10:07:10.951631 MCKIO_SEMI = 0
3799 10:07:10.955172 PLL_FREQ = 2288
3800 10:07:10.958651 DQ_UI_PI_RATIO = 32
3801 10:07:10.961595 CA_UI_PI_RATIO = 0
3802 10:07:10.965259 ===================================
3803 10:07:10.968437 ===================================
3804 10:07:10.968560 memory_type:LPDDR4
3805 10:07:10.971663 GP_NUM : 10
3806 10:07:10.975192 SRAM_EN : 1
3807 10:07:10.975293 MD32_EN : 0
3808 10:07:10.978095 ===================================
3809 10:07:10.981658 [ANA_INIT] >>>>>>>>>>>>>>
3810 10:07:10.984905 <<<<<< [CONFIGURE PHASE]: ANA_TX
3811 10:07:10.987760 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3812 10:07:10.991235 ===================================
3813 10:07:10.994679 data_rate = 1200,PCW = 0X5800
3814 10:07:10.997941 ===================================
3815 10:07:11.001091 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3816 10:07:11.004351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3817 10:07:11.011247 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3818 10:07:11.014525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3819 10:07:11.017948 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3820 10:07:11.023925 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3821 10:07:11.024004 [ANA_INIT] flow start
3822 10:07:11.027755 [ANA_INIT] PLL >>>>>>>>
3823 10:07:11.030714 [ANA_INIT] PLL <<<<<<<<
3824 10:07:11.030780 [ANA_INIT] MIDPI >>>>>>>>
3825 10:07:11.034183 [ANA_INIT] MIDPI <<<<<<<<
3826 10:07:11.037390 [ANA_INIT] DLL >>>>>>>>
3827 10:07:11.037458 [ANA_INIT] flow end
3828 10:07:11.041092 ============ LP4 DIFF to SE enter ============
3829 10:07:11.047221 ============ LP4 DIFF to SE exit ============
3830 10:07:11.047294 [ANA_INIT] <<<<<<<<<<<<<
3831 10:07:11.050501 [Flow] Enable top DCM control >>>>>
3832 10:07:11.053917 [Flow] Enable top DCM control <<<<<
3833 10:07:11.057183 Enable DLL master slave shuffle
3834 10:07:11.063581 ==============================================================
3835 10:07:11.066882 Gating Mode config
3836 10:07:11.070336 ==============================================================
3837 10:07:11.073804 Config description:
3838 10:07:11.083709 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3839 10:07:11.090393 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3840 10:07:11.093510 SELPH_MODE 0: By rank 1: By Phase
3841 10:07:11.100243 ==============================================================
3842 10:07:11.103373 GAT_TRACK_EN = 1
3843 10:07:11.106600 RX_GATING_MODE = 2
3844 10:07:11.109769 RX_GATING_TRACK_MODE = 2
3845 10:07:11.109841 SELPH_MODE = 1
3846 10:07:11.112977 PICG_EARLY_EN = 1
3847 10:07:11.116604 VALID_LAT_VALUE = 1
3848 10:07:11.123069 ==============================================================
3849 10:07:11.126573 Enter into Gating configuration >>>>
3850 10:07:11.129877 Exit from Gating configuration <<<<
3851 10:07:11.132907 Enter into DVFS_PRE_config >>>>>
3852 10:07:11.143039 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3853 10:07:11.145946 Exit from DVFS_PRE_config <<<<<
3854 10:07:11.149846 Enter into PICG configuration >>>>
3855 10:07:11.152798 Exit from PICG configuration <<<<
3856 10:07:11.155854 [RX_INPUT] configuration >>>>>
3857 10:07:11.159275 [RX_INPUT] configuration <<<<<
3858 10:07:11.162720 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3859 10:07:11.169205 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3860 10:07:11.176060 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3861 10:07:11.182573 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3862 10:07:11.189233 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3863 10:07:11.195683 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3864 10:07:11.198957 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3865 10:07:11.202670 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3866 10:07:11.205626 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3867 10:07:11.212100 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3868 10:07:11.215155 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3869 10:07:11.218977 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 10:07:11.222133 ===================================
3871 10:07:11.225407 LPDDR4 DRAM CONFIGURATION
3872 10:07:11.228456 ===================================
3873 10:07:11.228538 EX_ROW_EN[0] = 0x0
3874 10:07:11.231719 EX_ROW_EN[1] = 0x0
3875 10:07:11.234940 LP4Y_EN = 0x0
3876 10:07:11.235021 WORK_FSP = 0x0
3877 10:07:11.238650 WL = 0x2
3878 10:07:11.238736 RL = 0x2
3879 10:07:11.241613 BL = 0x2
3880 10:07:11.241699 RPST = 0x0
3881 10:07:11.244998 RD_PRE = 0x0
3882 10:07:11.245079 WR_PRE = 0x1
3883 10:07:11.248428 WR_PST = 0x0
3884 10:07:11.248509 DBI_WR = 0x0
3885 10:07:11.251578 DBI_RD = 0x0
3886 10:07:11.251660 OTF = 0x1
3887 10:07:11.254792 ===================================
3888 10:07:11.258666 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3889 10:07:11.264515 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3890 10:07:11.267981 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3891 10:07:11.271493 ===================================
3892 10:07:11.274469 LPDDR4 DRAM CONFIGURATION
3893 10:07:11.277934 ===================================
3894 10:07:11.278016 EX_ROW_EN[0] = 0x10
3895 10:07:11.281303 EX_ROW_EN[1] = 0x0
3896 10:07:11.284483 LP4Y_EN = 0x0
3897 10:07:11.284563 WORK_FSP = 0x0
3898 10:07:11.287595 WL = 0x2
3899 10:07:11.287676 RL = 0x2
3900 10:07:11.290817 BL = 0x2
3901 10:07:11.290933 RPST = 0x0
3902 10:07:11.294399 RD_PRE = 0x0
3903 10:07:11.294480 WR_PRE = 0x1
3904 10:07:11.297566 WR_PST = 0x0
3905 10:07:11.297646 DBI_WR = 0x0
3906 10:07:11.301178 DBI_RD = 0x0
3907 10:07:11.301259 OTF = 0x1
3908 10:07:11.304497 ===================================
3909 10:07:11.310946 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3910 10:07:11.315860 nWR fixed to 30
3911 10:07:11.318811 [ModeRegInit_LP4] CH0 RK0
3912 10:07:11.318896 [ModeRegInit_LP4] CH0 RK1
3913 10:07:11.322075 [ModeRegInit_LP4] CH1 RK0
3914 10:07:11.325232 [ModeRegInit_LP4] CH1 RK1
3915 10:07:11.325313 match AC timing 17
3916 10:07:11.332099 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3917 10:07:11.335077 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3918 10:07:11.339104 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3919 10:07:11.345053 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3920 10:07:11.348531 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3921 10:07:11.348612 ==
3922 10:07:11.351800 Dram Type= 6, Freq= 0, CH_0, rank 0
3923 10:07:11.354869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3924 10:07:11.354964 ==
3925 10:07:11.361659 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3926 10:07:11.367997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3927 10:07:11.371375 [CA 0] Center 37 (7~67) winsize 61
3928 10:07:11.375096 [CA 1] Center 36 (6~67) winsize 62
3929 10:07:11.378064 [CA 2] Center 35 (5~65) winsize 61
3930 10:07:11.381283 [CA 3] Center 35 (5~65) winsize 61
3931 10:07:11.384934 [CA 4] Center 34 (4~65) winsize 62
3932 10:07:11.388101 [CA 5] Center 34 (4~64) winsize 61
3933 10:07:11.388183
3934 10:07:11.391241 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3935 10:07:11.391322
3936 10:07:11.394729 [CATrainingPosCal] consider 1 rank data
3937 10:07:11.398073 u2DelayCellTimex100 = 270/100 ps
3938 10:07:11.401350 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3939 10:07:11.404504 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3940 10:07:11.407954 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3941 10:07:11.414390 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3942 10:07:11.417689 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3943 10:07:11.420851 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3944 10:07:11.420932
3945 10:07:11.424169 CA PerBit enable=1, Macro0, CA PI delay=34
3946 10:07:11.424250
3947 10:07:11.427358 [CBTSetCACLKResult] CA Dly = 34
3948 10:07:11.427439 CS Dly: 7 (0~38)
3949 10:07:11.427503 ==
3950 10:07:11.430932 Dram Type= 6, Freq= 0, CH_0, rank 1
3951 10:07:11.437415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 10:07:11.437497 ==
3953 10:07:11.440558 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3954 10:07:11.447414 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3955 10:07:11.450904 [CA 0] Center 37 (7~67) winsize 61
3956 10:07:11.454106 [CA 1] Center 36 (6~67) winsize 62
3957 10:07:11.457391 [CA 2] Center 35 (5~65) winsize 61
3958 10:07:11.460709 [CA 3] Center 35 (5~65) winsize 61
3959 10:07:11.464577 [CA 4] Center 34 (4~65) winsize 62
3960 10:07:11.467432 [CA 5] Center 33 (3~64) winsize 62
3961 10:07:11.467533
3962 10:07:11.470814 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3963 10:07:11.470928
3964 10:07:11.473926 [CATrainingPosCal] consider 2 rank data
3965 10:07:11.477368 u2DelayCellTimex100 = 270/100 ps
3966 10:07:11.480934 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3967 10:07:11.487045 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3968 10:07:11.490506 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3969 10:07:11.493607 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3970 10:07:11.497197 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3971 10:07:11.500459 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3972 10:07:11.500533
3973 10:07:11.503554 CA PerBit enable=1, Macro0, CA PI delay=34
3974 10:07:11.503620
3975 10:07:11.507325 [CBTSetCACLKResult] CA Dly = 34
3976 10:07:11.510744 CS Dly: 6 (0~37)
3977 10:07:11.511391
3978 10:07:11.514130 ----->DramcWriteLeveling(PI) begin...
3979 10:07:11.514624 ==
3980 10:07:11.517348 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 10:07:11.520408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 10:07:11.521014 ==
3983 10:07:11.523800 Write leveling (Byte 0): 32 => 32
3984 10:07:11.527402 Write leveling (Byte 1): 32 => 32
3985 10:07:11.530514 DramcWriteLeveling(PI) end<-----
3986 10:07:11.531014
3987 10:07:11.531488 ==
3988 10:07:11.533782 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 10:07:11.536821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 10:07:11.537441 ==
3991 10:07:11.540551 [Gating] SW mode calibration
3992 10:07:11.546819 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3993 10:07:11.553679 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3994 10:07:11.556862 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 10:07:11.559922 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3996 10:07:11.567124 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3997 10:07:11.570250 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
3998 10:07:11.573007 0 9 16 | B1->B0 | 3131 2929 | 0 0 | (0 0) (0 0)
3999 10:07:11.579841 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4000 10:07:11.583126 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 10:07:11.586318 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 10:07:11.593258 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 10:07:11.596535 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 10:07:11.599614 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 10:07:11.606268 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 10:07:11.609334 0 10 16 | B1->B0 | 3939 3c3c | 0 0 | (0 0) (0 0)
4007 10:07:11.612991 0 10 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4008 10:07:11.619278 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 10:07:11.622424 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 10:07:11.626086 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 10:07:11.632396 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 10:07:11.635934 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 10:07:11.639167 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4014 10:07:11.645562 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4015 10:07:11.649003 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 10:07:11.652038 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 10:07:11.658865 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 10:07:11.661897 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 10:07:11.665606 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 10:07:11.671955 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 10:07:11.675092 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 10:07:11.678660 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 10:07:11.684872 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 10:07:11.688293 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 10:07:11.691769 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 10:07:11.698400 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 10:07:11.701865 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 10:07:11.704828 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 10:07:11.711422 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 10:07:11.714649 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4031 10:07:11.717749 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 10:07:11.721356 Total UI for P1: 0, mck2ui 16
4033 10:07:11.724689 best dqsien dly found for B0: ( 0, 13, 16)
4034 10:07:11.727716 Total UI for P1: 0, mck2ui 16
4035 10:07:11.730906 best dqsien dly found for B1: ( 0, 13, 18)
4036 10:07:11.737839 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4037 10:07:11.740855 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4038 10:07:11.741276
4039 10:07:11.744576 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4040 10:07:11.747857 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4041 10:07:11.750874 [Gating] SW calibration Done
4042 10:07:11.751356 ==
4043 10:07:11.754260 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 10:07:11.757444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 10:07:11.757867 ==
4046 10:07:11.760779 RX Vref Scan: 0
4047 10:07:11.761215
4048 10:07:11.761553 RX Vref 0 -> 0, step: 1
4049 10:07:11.761869
4050 10:07:11.764211 RX Delay -230 -> 252, step: 16
4051 10:07:11.767344 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4052 10:07:11.773890 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4053 10:07:11.777294 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4054 10:07:11.780472 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4055 10:07:11.784157 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4056 10:07:11.790606 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4057 10:07:11.794059 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4058 10:07:11.797228 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4059 10:07:11.800179 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4060 10:07:11.807378 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4061 10:07:11.810075 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4062 10:07:11.813647 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4063 10:07:11.816707 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4064 10:07:11.823465 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4065 10:07:11.826721 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4066 10:07:11.829730 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4067 10:07:11.830279 ==
4068 10:07:11.832973 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 10:07:11.836651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 10:07:11.839811 ==
4071 10:07:11.840253 DQS Delay:
4072 10:07:11.840634 DQS0 = 0, DQS1 = 0
4073 10:07:11.843241 DQM Delay:
4074 10:07:11.843353 DQM0 = 40, DQM1 = 30
4075 10:07:11.845971 DQ Delay:
4076 10:07:11.846052 DQ0 =33, DQ1 =41, DQ2 =41, DQ3 =41
4077 10:07:11.849111 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4078 10:07:11.852580 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4079 10:07:11.856021 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4080 10:07:11.858990
4081 10:07:11.859071
4082 10:07:11.859134 ==
4083 10:07:11.862656 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 10:07:11.865883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 10:07:11.865961 ==
4086 10:07:11.866026
4087 10:07:11.866085
4088 10:07:11.869012 TX Vref Scan disable
4089 10:07:11.869084 == TX Byte 0 ==
4090 10:07:11.875876 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4091 10:07:11.879155 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4092 10:07:11.879232 == TX Byte 1 ==
4093 10:07:11.885515 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4094 10:07:11.888785 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4095 10:07:11.888876 ==
4096 10:07:11.892168 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 10:07:11.895083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 10:07:11.895172 ==
4099 10:07:11.895238
4100 10:07:11.898791
4101 10:07:11.898893 TX Vref Scan disable
4102 10:07:11.902575 == TX Byte 0 ==
4103 10:07:11.905670 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4104 10:07:11.912473 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4105 10:07:11.912895 == TX Byte 1 ==
4106 10:07:11.915754 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4107 10:07:11.922104 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4108 10:07:11.922657
4109 10:07:11.923096 [DATLAT]
4110 10:07:11.923564 Freq=600, CH0 RK0
4111 10:07:11.923916
4112 10:07:11.925500 DATLAT Default: 0x9
4113 10:07:11.928966 0, 0xFFFF, sum = 0
4114 10:07:11.929434 1, 0xFFFF, sum = 0
4115 10:07:11.932052 2, 0xFFFF, sum = 0
4116 10:07:11.932516 3, 0xFFFF, sum = 0
4117 10:07:11.935363 4, 0xFFFF, sum = 0
4118 10:07:11.935943 5, 0xFFFF, sum = 0
4119 10:07:11.938566 6, 0xFFFF, sum = 0
4120 10:07:11.939203 7, 0xFFFF, sum = 0
4121 10:07:11.941809 8, 0x0, sum = 1
4122 10:07:11.942324 9, 0x0, sum = 2
4123 10:07:11.945106 10, 0x0, sum = 3
4124 10:07:11.945188 11, 0x0, sum = 4
4125 10:07:11.945254 best_step = 9
4126 10:07:11.945314
4127 10:07:11.948142 ==
4128 10:07:11.951669 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 10:07:11.954862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 10:07:11.954957 ==
4131 10:07:11.955022 RX Vref Scan: 1
4132 10:07:11.955082
4133 10:07:11.958126 RX Vref 0 -> 0, step: 1
4134 10:07:11.958207
4135 10:07:11.961160 RX Delay -195 -> 252, step: 8
4136 10:07:11.961241
4137 10:07:11.964879 Set Vref, RX VrefLevel [Byte0]: 61
4138 10:07:11.968067 [Byte1]: 57
4139 10:07:11.968148
4140 10:07:11.971111 Final RX Vref Byte 0 = 61 to rank0
4141 10:07:11.974794 Final RX Vref Byte 1 = 57 to rank0
4142 10:07:11.977991 Final RX Vref Byte 0 = 61 to rank1
4143 10:07:11.981333 Final RX Vref Byte 1 = 57 to rank1==
4144 10:07:11.984495 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 10:07:11.987780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 10:07:11.991037 ==
4147 10:07:11.991117 DQS Delay:
4148 10:07:11.991181 DQS0 = 0, DQS1 = 0
4149 10:07:11.994246 DQM Delay:
4150 10:07:11.994326 DQM0 = 35, DQM1 = 29
4151 10:07:11.997966 DQ Delay:
4152 10:07:12.001222 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =32
4153 10:07:12.001317 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4154 10:07:12.004525 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4155 10:07:12.007761 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4156 10:07:12.010914
4157 10:07:12.011011
4158 10:07:12.017599 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4159 10:07:12.021120 CH0 RK0: MR19=808, MR18=3C3B
4160 10:07:12.027810 CH0_RK0: MR19=0x808, MR18=0x3C3B, DQSOSC=398, MR23=63, INC=165, DEC=110
4161 10:07:12.028276
4162 10:07:12.031239 ----->DramcWriteLeveling(PI) begin...
4163 10:07:12.031807 ==
4164 10:07:12.034111 Dram Type= 6, Freq= 0, CH_0, rank 1
4165 10:07:12.037655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 10:07:12.038119 ==
4167 10:07:12.041117 Write leveling (Byte 0): 33 => 33
4168 10:07:12.044085 Write leveling (Byte 1): 30 => 30
4169 10:07:12.047340 DramcWriteLeveling(PI) end<-----
4170 10:07:12.047896
4171 10:07:12.048263 ==
4172 10:07:12.050908 Dram Type= 6, Freq= 0, CH_0, rank 1
4173 10:07:12.054274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 10:07:12.054692 ==
4175 10:07:12.057423 [Gating] SW mode calibration
4176 10:07:12.063571 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4177 10:07:12.070422 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4178 10:07:12.073766 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4179 10:07:12.080527 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 10:07:12.083723 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4181 10:07:12.086813 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4182 10:07:12.093551 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (0 0) (0 0)
4183 10:07:12.096713 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 10:07:12.099835 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 10:07:12.106504 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 10:07:12.109862 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 10:07:12.112886 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 10:07:12.119652 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 10:07:12.123232 0 10 12 | B1->B0 | 2626 3131 | 0 0 | (0 0) (1 1)
4190 10:07:12.126430 0 10 16 | B1->B0 | 3535 4343 | 0 0 | (0 0) (0 0)
4191 10:07:12.132892 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 10:07:12.136653 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 10:07:12.139820 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 10:07:12.146294 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 10:07:12.149373 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 10:07:12.152552 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 10:07:12.159498 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 10:07:12.162698 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4199 10:07:12.166078 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 10:07:12.172784 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 10:07:12.175908 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 10:07:12.179110 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 10:07:12.185968 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 10:07:12.189148 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 10:07:12.192334 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 10:07:12.198957 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 10:07:12.202126 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 10:07:12.205821 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 10:07:12.212299 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 10:07:12.215365 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 10:07:12.218623 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 10:07:12.225024 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 10:07:12.228403 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4214 10:07:12.231950 Total UI for P1: 0, mck2ui 16
4215 10:07:12.235197 best dqsien dly found for B0: ( 0, 13, 10)
4216 10:07:12.238054 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 10:07:12.241734 Total UI for P1: 0, mck2ui 16
4218 10:07:12.245063 best dqsien dly found for B1: ( 0, 13, 12)
4219 10:07:12.248697 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4220 10:07:12.251845 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4221 10:07:12.254657
4222 10:07:12.258094 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4223 10:07:12.261049 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4224 10:07:12.264309 [Gating] SW calibration Done
4225 10:07:12.264834 ==
4226 10:07:12.267722 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 10:07:12.271178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 10:07:12.271626 ==
4229 10:07:12.274257 RX Vref Scan: 0
4230 10:07:12.274765
4231 10:07:12.275170 RX Vref 0 -> 0, step: 1
4232 10:07:12.275533
4233 10:07:12.277856 RX Delay -230 -> 252, step: 16
4234 10:07:12.281221 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4235 10:07:12.287798 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4236 10:07:12.290949 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4237 10:07:12.294241 iDelay=218, Bit 3, Center 25 (-150 ~ 201) 352
4238 10:07:12.297408 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4239 10:07:12.304261 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4240 10:07:12.307356 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4241 10:07:12.310739 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4242 10:07:12.313904 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4243 10:07:12.320361 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4244 10:07:12.323332 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4245 10:07:12.326911 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4246 10:07:12.330397 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4247 10:07:12.336575 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4248 10:07:12.340217 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4249 10:07:12.343613 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4250 10:07:12.344113 ==
4251 10:07:12.346908 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 10:07:12.349721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 10:07:12.353171 ==
4254 10:07:12.353791 DQS Delay:
4255 10:07:12.354284 DQS0 = 0, DQS1 = 0
4256 10:07:12.356413 DQM Delay:
4257 10:07:12.356925 DQM0 = 34, DQM1 = 28
4258 10:07:12.360218 DQ Delay:
4259 10:07:12.360769 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =25
4260 10:07:12.363272 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4261 10:07:12.366416 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4262 10:07:12.369673 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4263 10:07:12.373237
4264 10:07:12.373845
4265 10:07:12.374195 ==
4266 10:07:12.376368 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 10:07:12.379487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 10:07:12.380030 ==
4269 10:07:12.380442
4270 10:07:12.380911
4271 10:07:12.383258 TX Vref Scan disable
4272 10:07:12.383838 == TX Byte 0 ==
4273 10:07:12.389681 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4274 10:07:12.392671 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4275 10:07:12.393219 == TX Byte 1 ==
4276 10:07:12.399747 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4277 10:07:12.402947 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4278 10:07:12.403373 ==
4279 10:07:12.406211 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 10:07:12.409328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 10:07:12.409768 ==
4282 10:07:12.410277
4283 10:07:12.410685
4284 10:07:12.412543 TX Vref Scan disable
4285 10:07:12.416199 == TX Byte 0 ==
4286 10:07:12.419515 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4287 10:07:12.422692 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4288 10:07:12.426163 == TX Byte 1 ==
4289 10:07:12.429044 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4290 10:07:12.432475 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4291 10:07:12.435968
4292 10:07:12.436049 [DATLAT]
4293 10:07:12.436112 Freq=600, CH0 RK1
4294 10:07:12.436171
4295 10:07:12.439491 DATLAT Default: 0x9
4296 10:07:12.439570 0, 0xFFFF, sum = 0
4297 10:07:12.442376 1, 0xFFFF, sum = 0
4298 10:07:12.442457 2, 0xFFFF, sum = 0
4299 10:07:12.445895 3, 0xFFFF, sum = 0
4300 10:07:12.449380 4, 0xFFFF, sum = 0
4301 10:07:12.449461 5, 0xFFFF, sum = 0
4302 10:07:12.452514 6, 0xFFFF, sum = 0
4303 10:07:12.452622 7, 0xFFFF, sum = 0
4304 10:07:12.455546 8, 0x0, sum = 1
4305 10:07:12.455643 9, 0x0, sum = 2
4306 10:07:12.455731 10, 0x0, sum = 3
4307 10:07:12.458707 11, 0x0, sum = 4
4308 10:07:12.458800 best_step = 9
4309 10:07:12.458922
4310 10:07:12.459005 ==
4311 10:07:12.462438 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 10:07:12.468689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 10:07:12.468769 ==
4314 10:07:12.468832 RX Vref Scan: 0
4315 10:07:12.468890
4316 10:07:12.472131 RX Vref 0 -> 0, step: 1
4317 10:07:12.472211
4318 10:07:12.475139 RX Delay -195 -> 252, step: 8
4319 10:07:12.478362 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4320 10:07:12.485476 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4321 10:07:12.488559 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4322 10:07:12.491803 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4323 10:07:12.495609 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4324 10:07:12.501650 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4325 10:07:12.505309 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4326 10:07:12.508842 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4327 10:07:12.511814 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4328 10:07:12.518322 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4329 10:07:12.521707 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4330 10:07:12.524883 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4331 10:07:12.528443 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4332 10:07:12.534666 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4333 10:07:12.538025 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4334 10:07:12.541691 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4335 10:07:12.542145 ==
4336 10:07:12.544629 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 10:07:12.548062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 10:07:12.548518 ==
4339 10:07:12.551539 DQS Delay:
4340 10:07:12.551989 DQS0 = 0, DQS1 = 0
4341 10:07:12.554675 DQM Delay:
4342 10:07:12.555203 DQM0 = 34, DQM1 = 27
4343 10:07:12.555566 DQ Delay:
4344 10:07:12.558359 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4345 10:07:12.561488 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4346 10:07:12.565015 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4347 10:07:12.568258 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4348 10:07:12.568734
4349 10:07:12.571366
4350 10:07:12.577918 [DQSOSCAuto] RK1, (LSB)MR18= 0x6533, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4351 10:07:12.581317 CH0 RK1: MR19=808, MR18=6533
4352 10:07:12.588085 CH0_RK1: MR19=0x808, MR18=0x6533, DQSOSC=390, MR23=63, INC=172, DEC=114
4353 10:07:12.590870 [RxdqsGatingPostProcess] freq 600
4354 10:07:12.594411 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4355 10:07:12.597515 Pre-setting of DQS Precalculation
4356 10:07:12.604090 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4357 10:07:12.604544 ==
4358 10:07:12.607291 Dram Type= 6, Freq= 0, CH_1, rank 0
4359 10:07:12.610561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 10:07:12.611009 ==
4361 10:07:12.617516 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4362 10:07:12.620750 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4363 10:07:12.624947 [CA 0] Center 36 (6~66) winsize 61
4364 10:07:12.628194 [CA 1] Center 36 (6~66) winsize 61
4365 10:07:12.631341 [CA 2] Center 34 (4~65) winsize 62
4366 10:07:12.635072 [CA 3] Center 34 (3~65) winsize 63
4367 10:07:12.638341 [CA 4] Center 34 (4~65) winsize 62
4368 10:07:12.641588 [CA 5] Center 33 (3~64) winsize 62
4369 10:07:12.642041
4370 10:07:12.644772 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4371 10:07:12.645180
4372 10:07:12.647910 [CATrainingPosCal] consider 1 rank data
4373 10:07:12.651317 u2DelayCellTimex100 = 270/100 ps
4374 10:07:12.654688 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4375 10:07:12.661518 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4376 10:07:12.664714 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4377 10:07:12.668363 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4378 10:07:12.671023 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4379 10:07:12.674711 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4380 10:07:12.675265
4381 10:07:12.677998 CA PerBit enable=1, Macro0, CA PI delay=33
4382 10:07:12.678452
4383 10:07:12.681189 [CBTSetCACLKResult] CA Dly = 33
4384 10:07:12.684432 CS Dly: 5 (0~36)
4385 10:07:12.684971 ==
4386 10:07:12.687748 Dram Type= 6, Freq= 0, CH_1, rank 1
4387 10:07:12.691024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 10:07:12.691549 ==
4389 10:07:12.697369 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4390 10:07:12.700844 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4391 10:07:12.705275 [CA 0] Center 36 (6~66) winsize 61
4392 10:07:12.708579 [CA 1] Center 36 (6~66) winsize 61
4393 10:07:12.711655 [CA 2] Center 34 (4~65) winsize 62
4394 10:07:12.714927 [CA 3] Center 33 (3~64) winsize 62
4395 10:07:12.718007 [CA 4] Center 34 (4~65) winsize 62
4396 10:07:12.721243 [CA 5] Center 33 (3~64) winsize 62
4397 10:07:12.721663
4398 10:07:12.725110 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4399 10:07:12.725531
4400 10:07:12.728306 [CATrainingPosCal] consider 2 rank data
4401 10:07:12.731418 u2DelayCellTimex100 = 270/100 ps
4402 10:07:12.734528 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4403 10:07:12.741373 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4404 10:07:12.744676 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4405 10:07:12.747926 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4406 10:07:12.751196 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4407 10:07:12.754290 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4408 10:07:12.754712
4409 10:07:12.757668 CA PerBit enable=1, Macro0, CA PI delay=33
4410 10:07:12.758092
4411 10:07:12.760969 [CBTSetCACLKResult] CA Dly = 33
4412 10:07:12.764647 CS Dly: 5 (0~37)
4413 10:07:12.765067
4414 10:07:12.768071 ----->DramcWriteLeveling(PI) begin...
4415 10:07:12.768498 ==
4416 10:07:12.770779 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 10:07:12.774181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 10:07:12.774608 ==
4419 10:07:12.777441 Write leveling (Byte 0): 29 => 29
4420 10:07:12.780828 Write leveling (Byte 1): 30 => 30
4421 10:07:12.784580 DramcWriteLeveling(PI) end<-----
4422 10:07:12.785135
4423 10:07:12.785585 ==
4424 10:07:12.787058 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 10:07:12.790890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 10:07:12.791246 ==
4427 10:07:12.793987 [Gating] SW mode calibration
4428 10:07:12.800561 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4429 10:07:12.806864 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4430 10:07:12.810709 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4431 10:07:12.813310 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4432 10:07:12.820144 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4433 10:07:12.823495 0 9 12 | B1->B0 | 3232 3333 | 0 0 | (0 0) (0 1)
4434 10:07:12.826628 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4435 10:07:12.833464 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 10:07:12.836812 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 10:07:12.839470 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 10:07:12.846326 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 10:07:12.849478 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 10:07:12.856312 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 10:07:12.859451 0 10 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
4442 10:07:12.862951 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4443 10:07:12.869094 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 10:07:12.872578 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 10:07:12.876299 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 10:07:12.882574 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 10:07:12.885652 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 10:07:12.888912 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 10:07:12.895861 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 10:07:12.898786 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 10:07:12.902122 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 10:07:12.908675 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 10:07:12.912361 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 10:07:12.915567 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 10:07:12.918797 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 10:07:12.926084 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 10:07:12.928859 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 10:07:12.935507 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 10:07:12.938617 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 10:07:12.941939 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 10:07:12.948713 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 10:07:12.951861 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 10:07:12.955106 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 10:07:12.961814 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 10:07:12.964882 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4466 10:07:12.968327 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 10:07:12.971760 Total UI for P1: 0, mck2ui 16
4468 10:07:12.974797 best dqsien dly found for B0: ( 0, 13, 12)
4469 10:07:12.978247 Total UI for P1: 0, mck2ui 16
4470 10:07:12.981749 best dqsien dly found for B1: ( 0, 13, 12)
4471 10:07:12.984931 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4472 10:07:12.988629 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4473 10:07:12.989154
4474 10:07:12.994752 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4475 10:07:12.998204 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4476 10:07:12.998668 [Gating] SW calibration Done
4477 10:07:13.001228 ==
4478 10:07:13.004648 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 10:07:13.007789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 10:07:13.008251 ==
4481 10:07:13.008616 RX Vref Scan: 0
4482 10:07:13.008955
4483 10:07:13.011187 RX Vref 0 -> 0, step: 1
4484 10:07:13.011644
4485 10:07:13.014346 RX Delay -230 -> 252, step: 16
4486 10:07:13.017535 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4487 10:07:13.024009 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4488 10:07:13.027746 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4489 10:07:13.030671 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4490 10:07:13.034380 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4491 10:07:13.037674 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4492 10:07:13.044130 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4493 10:07:13.047623 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4494 10:07:13.050916 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4495 10:07:13.053902 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4496 10:07:13.060862 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4497 10:07:13.063884 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4498 10:07:13.067059 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4499 10:07:13.070517 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4500 10:07:13.077343 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4501 10:07:13.080353 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4502 10:07:13.080856 ==
4503 10:07:13.083821 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 10:07:13.086741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 10:07:13.087252 ==
4506 10:07:13.090440 DQS Delay:
4507 10:07:13.091051 DQS0 = 0, DQS1 = 0
4508 10:07:13.091436 DQM Delay:
4509 10:07:13.093675 DQM0 = 38, DQM1 = 29
4510 10:07:13.094133 DQ Delay:
4511 10:07:13.096419 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4512 10:07:13.100508 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4513 10:07:13.103022 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4514 10:07:13.106810 DQ12 =41, DQ13 =33, DQ14 =33, DQ15 =33
4515 10:07:13.107409
4516 10:07:13.107775
4517 10:07:13.109948 ==
4518 10:07:13.110510 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 10:07:13.116340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 10:07:13.116883 ==
4521 10:07:13.117254
4522 10:07:13.117593
4523 10:07:13.119835 TX Vref Scan disable
4524 10:07:13.120298 == TX Byte 0 ==
4525 10:07:13.123157 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4526 10:07:13.129882 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4527 10:07:13.130439 == TX Byte 1 ==
4528 10:07:13.136534 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4529 10:07:13.139223 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4530 10:07:13.139777 ==
4531 10:07:13.143024 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 10:07:13.146104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 10:07:13.146576 ==
4534 10:07:13.146984
4535 10:07:13.147334
4536 10:07:13.149460 TX Vref Scan disable
4537 10:07:13.152453 == TX Byte 0 ==
4538 10:07:13.155460 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4539 10:07:13.159653 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4540 10:07:13.162179 == TX Byte 1 ==
4541 10:07:13.165425 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4542 10:07:13.169398 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4543 10:07:13.172856
4544 10:07:13.173409 [DATLAT]
4545 10:07:13.173777 Freq=600, CH1 RK0
4546 10:07:13.174119
4547 10:07:13.175491 DATLAT Default: 0x9
4548 10:07:13.175953 0, 0xFFFF, sum = 0
4549 10:07:13.178784 1, 0xFFFF, sum = 0
4550 10:07:13.179386 2, 0xFFFF, sum = 0
4551 10:07:13.182363 3, 0xFFFF, sum = 0
4552 10:07:13.182863 4, 0xFFFF, sum = 0
4553 10:07:13.185319 5, 0xFFFF, sum = 0
4554 10:07:13.188882 6, 0xFFFF, sum = 0
4555 10:07:13.189440 7, 0xFFFF, sum = 0
4556 10:07:13.189815 8, 0x0, sum = 1
4557 10:07:13.192209 9, 0x0, sum = 2
4558 10:07:13.192676 10, 0x0, sum = 3
4559 10:07:13.195326 11, 0x0, sum = 4
4560 10:07:13.195788 best_step = 9
4561 10:07:13.196153
4562 10:07:13.196493 ==
4563 10:07:13.198780 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 10:07:13.205121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 10:07:13.205674 ==
4566 10:07:13.206039 RX Vref Scan: 1
4567 10:07:13.206378
4568 10:07:13.208844 RX Vref 0 -> 0, step: 1
4569 10:07:13.209400
4570 10:07:13.211756 RX Delay -195 -> 252, step: 8
4571 10:07:13.212212
4572 10:07:13.215291 Set Vref, RX VrefLevel [Byte0]: 58
4573 10:07:13.218229 [Byte1]: 48
4574 10:07:13.218710
4575 10:07:13.221643 Final RX Vref Byte 0 = 58 to rank0
4576 10:07:13.224849 Final RX Vref Byte 1 = 48 to rank0
4577 10:07:13.228184 Final RX Vref Byte 0 = 58 to rank1
4578 10:07:13.231514 Final RX Vref Byte 1 = 48 to rank1==
4579 10:07:13.235248 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 10:07:13.238323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 10:07:13.238792 ==
4582 10:07:13.241445 DQS Delay:
4583 10:07:13.241902 DQS0 = 0, DQS1 = 0
4584 10:07:13.245557 DQM Delay:
4585 10:07:13.246120 DQM0 = 38, DQM1 = 27
4586 10:07:13.248519 DQ Delay:
4587 10:07:13.249079 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =32
4588 10:07:13.251329 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4589 10:07:13.254485 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4590 10:07:13.257712 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4591 10:07:13.258172
4592 10:07:13.261051
4593 10:07:13.267924 [DQSOSCAuto] RK0, (LSB)MR18= 0x2430, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4594 10:07:13.270782 CH1 RK0: MR19=808, MR18=2430
4595 10:07:13.277893 CH1_RK0: MR19=0x808, MR18=0x2430, DQSOSC=400, MR23=63, INC=163, DEC=109
4596 10:07:13.278455
4597 10:07:13.280824 ----->DramcWriteLeveling(PI) begin...
4598 10:07:13.281296 ==
4599 10:07:13.284508 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 10:07:13.287892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 10:07:13.288360 ==
4602 10:07:13.290557 Write leveling (Byte 0): 30 => 30
4603 10:07:13.294276 Write leveling (Byte 1): 30 => 30
4604 10:07:13.297595 DramcWriteLeveling(PI) end<-----
4605 10:07:13.298157
4606 10:07:13.298527 ==
4607 10:07:13.300692 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 10:07:13.303726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 10:07:13.304195 ==
4610 10:07:13.307090 [Gating] SW mode calibration
4611 10:07:13.313504 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4612 10:07:13.320286 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4613 10:07:13.323859 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4614 10:07:13.330311 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4615 10:07:13.334041 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4616 10:07:13.337192 0 9 12 | B1->B0 | 2f2f 2d2d | 1 0 | (1 0) (0 0)
4617 10:07:13.343340 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4618 10:07:13.347182 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 10:07:13.350024 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 10:07:13.356630 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 10:07:13.359778 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 10:07:13.363469 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 10:07:13.370140 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
4624 10:07:13.373319 0 10 12 | B1->B0 | 3030 3939 | 0 0 | (0 0) (0 0)
4625 10:07:13.376429 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4626 10:07:13.383384 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 10:07:13.386500 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 10:07:13.389723 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 10:07:13.396491 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 10:07:13.399289 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 10:07:13.402786 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 10:07:13.409537 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4633 10:07:13.412606 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4634 10:07:13.415883 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 10:07:13.422806 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 10:07:13.425576 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 10:07:13.428917 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 10:07:13.436056 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 10:07:13.439144 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 10:07:13.442308 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 10:07:13.448604 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 10:07:13.452047 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 10:07:13.454987 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 10:07:13.462143 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 10:07:13.465029 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 10:07:13.468306 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 10:07:13.474961 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 10:07:13.478072 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4649 10:07:13.482069 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4650 10:07:13.485286 Total UI for P1: 0, mck2ui 16
4651 10:07:13.488377 best dqsien dly found for B0: ( 0, 13, 12)
4652 10:07:13.494572 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 10:07:13.495099 Total UI for P1: 0, mck2ui 16
4654 10:07:13.501681 best dqsien dly found for B1: ( 0, 13, 14)
4655 10:07:13.505039 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4656 10:07:13.508539 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4657 10:07:13.509100
4658 10:07:13.511212 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4659 10:07:13.514547 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4660 10:07:13.518163 [Gating] SW calibration Done
4661 10:07:13.518620 ==
4662 10:07:13.521143 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 10:07:13.524755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 10:07:13.525328 ==
4665 10:07:13.527571 RX Vref Scan: 0
4666 10:07:13.528029
4667 10:07:13.528391 RX Vref 0 -> 0, step: 1
4668 10:07:13.531282
4669 10:07:13.531856 RX Delay -230 -> 252, step: 16
4670 10:07:13.537833 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4671 10:07:13.540930 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4672 10:07:13.544475 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4673 10:07:13.547812 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4674 10:07:13.553872 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4675 10:07:13.557668 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4676 10:07:13.560565 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4677 10:07:13.563780 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4678 10:07:13.570930 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4679 10:07:13.574461 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4680 10:07:13.576862 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4681 10:07:13.580270 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4682 10:07:13.587273 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4683 10:07:13.590571 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4684 10:07:13.593382 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4685 10:07:13.597353 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4686 10:07:13.597939 ==
4687 10:07:13.600546 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 10:07:13.606709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 10:07:13.607365 ==
4690 10:07:13.607860 DQS Delay:
4691 10:07:13.610318 DQS0 = 0, DQS1 = 0
4692 10:07:13.610941 DQM Delay:
4693 10:07:13.611433 DQM0 = 35, DQM1 = 29
4694 10:07:13.613664 DQ Delay:
4695 10:07:13.616330 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4696 10:07:13.619850 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4697 10:07:13.623260 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4698 10:07:13.626238 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4699 10:07:13.626819
4700 10:07:13.627347
4701 10:07:13.627802 ==
4702 10:07:13.629792 Dram Type= 6, Freq= 0, CH_1, rank 1
4703 10:07:13.632874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4704 10:07:13.633356 ==
4705 10:07:13.633840
4706 10:07:13.634311
4707 10:07:13.636797 TX Vref Scan disable
4708 10:07:13.639671 == TX Byte 0 ==
4709 10:07:13.642914 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4710 10:07:13.645940 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4711 10:07:13.649456 == TX Byte 1 ==
4712 10:07:13.653218 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4713 10:07:13.656058 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4714 10:07:13.656537 ==
4715 10:07:13.659615 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 10:07:13.666008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 10:07:13.666578 ==
4718 10:07:13.667118
4719 10:07:13.667577
4720 10:07:13.668218 TX Vref Scan disable
4721 10:07:13.669695 == TX Byte 0 ==
4722 10:07:13.673478 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4723 10:07:13.680336 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4724 10:07:13.680905 == TX Byte 1 ==
4725 10:07:13.683201 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4726 10:07:13.689758 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4727 10:07:13.690341
4728 10:07:13.690715 [DATLAT]
4729 10:07:13.691122 Freq=600, CH1 RK1
4730 10:07:13.691464
4731 10:07:13.693199 DATLAT Default: 0x9
4732 10:07:13.693762 0, 0xFFFF, sum = 0
4733 10:07:13.696620 1, 0xFFFF, sum = 0
4734 10:07:13.699555 2, 0xFFFF, sum = 0
4735 10:07:13.700132 3, 0xFFFF, sum = 0
4736 10:07:13.703167 4, 0xFFFF, sum = 0
4737 10:07:13.703740 5, 0xFFFF, sum = 0
4738 10:07:13.706603 6, 0xFFFF, sum = 0
4739 10:07:13.707223 7, 0xFFFF, sum = 0
4740 10:07:13.709711 8, 0x0, sum = 1
4741 10:07:13.710279 9, 0x0, sum = 2
4742 10:07:13.710655 10, 0x0, sum = 3
4743 10:07:13.712922 11, 0x0, sum = 4
4744 10:07:13.713488 best_step = 9
4745 10:07:13.713856
4746 10:07:13.716277 ==
4747 10:07:13.716746 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 10:07:13.722941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 10:07:13.723410 ==
4750 10:07:13.723781 RX Vref Scan: 0
4751 10:07:13.724125
4752 10:07:13.726256 RX Vref 0 -> 0, step: 1
4753 10:07:13.726716
4754 10:07:13.729275 RX Delay -195 -> 252, step: 8
4755 10:07:13.735967 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4756 10:07:13.739406 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4757 10:07:13.742578 iDelay=205, Bit 2, Center 20 (-139 ~ 180) 320
4758 10:07:13.746074 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4759 10:07:13.749528 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4760 10:07:13.755802 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4761 10:07:13.758813 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4762 10:07:13.762994 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4763 10:07:13.765566 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4764 10:07:13.772079 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4765 10:07:13.775661 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4766 10:07:13.778432 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4767 10:07:13.782061 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4768 10:07:13.788655 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4769 10:07:13.792064 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4770 10:07:13.795085 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4771 10:07:13.795555 ==
4772 10:07:13.798534 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 10:07:13.804854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 10:07:13.805412 ==
4775 10:07:13.805780 DQS Delay:
4776 10:07:13.806122 DQS0 = 0, DQS1 = 0
4777 10:07:13.808526 DQM Delay:
4778 10:07:13.809078 DQM0 = 35, DQM1 = 30
4779 10:07:13.811437 DQ Delay:
4780 10:07:13.814991 DQ0 =40, DQ1 =32, DQ2 =20, DQ3 =32
4781 10:07:13.817870 DQ4 =32, DQ5 =44, DQ6 =48, DQ7 =36
4782 10:07:13.821394 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =20
4783 10:07:13.824348 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4784 10:07:13.824811
4785 10:07:13.825204
4786 10:07:13.831414 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c5a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4787 10:07:13.834963 CH1 RK1: MR19=808, MR18=3C5A
4788 10:07:13.841407 CH1_RK1: MR19=0x808, MR18=0x3C5A, DQSOSC=392, MR23=63, INC=170, DEC=113
4789 10:07:13.844505 [RxdqsGatingPostProcess] freq 600
4790 10:07:13.847595 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4791 10:07:13.851233 Pre-setting of DQS Precalculation
4792 10:07:13.857341 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4793 10:07:13.864420 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4794 10:07:13.870471 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4795 10:07:13.871000
4796 10:07:13.871377
4797 10:07:13.873988 [Calibration Summary] 1200 Mbps
4798 10:07:13.877366 CH 0, Rank 0
4799 10:07:13.877928 SW Impedance : PASS
4800 10:07:13.881197 DUTY Scan : NO K
4801 10:07:13.884059 ZQ Calibration : PASS
4802 10:07:13.884616 Jitter Meter : NO K
4803 10:07:13.886945 CBT Training : PASS
4804 10:07:13.887407 Write leveling : PASS
4805 10:07:13.890601 RX DQS gating : PASS
4806 10:07:13.893378 RX DQ/DQS(RDDQC) : PASS
4807 10:07:13.893838 TX DQ/DQS : PASS
4808 10:07:13.896948 RX DATLAT : PASS
4809 10:07:13.900566 RX DQ/DQS(Engine): PASS
4810 10:07:13.901123 TX OE : NO K
4811 10:07:13.903546 All Pass.
4812 10:07:13.904005
4813 10:07:13.904374 CH 0, Rank 1
4814 10:07:13.906782 SW Impedance : PASS
4815 10:07:13.907306 DUTY Scan : NO K
4816 10:07:13.910176 ZQ Calibration : PASS
4817 10:07:13.913881 Jitter Meter : NO K
4818 10:07:13.914439 CBT Training : PASS
4819 10:07:13.917179 Write leveling : PASS
4820 10:07:13.919949 RX DQS gating : PASS
4821 10:07:13.920433 RX DQ/DQS(RDDQC) : PASS
4822 10:07:13.923501 TX DQ/DQS : PASS
4823 10:07:13.926541 RX DATLAT : PASS
4824 10:07:13.927139 RX DQ/DQS(Engine): PASS
4825 10:07:13.930220 TX OE : NO K
4826 10:07:13.930777 All Pass.
4827 10:07:13.931254
4828 10:07:13.933134 CH 1, Rank 0
4829 10:07:13.933693 SW Impedance : PASS
4830 10:07:13.936692 DUTY Scan : NO K
4831 10:07:13.940261 ZQ Calibration : PASS
4832 10:07:13.940834 Jitter Meter : NO K
4833 10:07:13.943204 CBT Training : PASS
4834 10:07:13.946667 Write leveling : PASS
4835 10:07:13.947170 RX DQS gating : PASS
4836 10:07:13.949420 RX DQ/DQS(RDDQC) : PASS
4837 10:07:13.952846 TX DQ/DQS : PASS
4838 10:07:13.953315 RX DATLAT : PASS
4839 10:07:13.956936 RX DQ/DQS(Engine): PASS
4840 10:07:13.957494 TX OE : NO K
4841 10:07:13.959353 All Pass.
4842 10:07:13.959814
4843 10:07:13.960183 CH 1, Rank 1
4844 10:07:13.962986 SW Impedance : PASS
4845 10:07:13.963538 DUTY Scan : NO K
4846 10:07:13.966349 ZQ Calibration : PASS
4847 10:07:13.969928 Jitter Meter : NO K
4848 10:07:13.970490 CBT Training : PASS
4849 10:07:13.972614 Write leveling : PASS
4850 10:07:13.976290 RX DQS gating : PASS
4851 10:07:13.976853 RX DQ/DQS(RDDQC) : PASS
4852 10:07:13.979151 TX DQ/DQS : PASS
4853 10:07:13.983175 RX DATLAT : PASS
4854 10:07:13.983733 RX DQ/DQS(Engine): PASS
4855 10:07:13.986325 TX OE : NO K
4856 10:07:13.986895 All Pass.
4857 10:07:13.987283
4858 10:07:13.989417 DramC Write-DBI off
4859 10:07:13.992474 PER_BANK_REFRESH: Hybrid Mode
4860 10:07:13.992939 TX_TRACKING: ON
4861 10:07:14.002616 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4862 10:07:14.005937 [FAST_K] Save calibration result to emmc
4863 10:07:14.009023 dramc_set_vcore_voltage set vcore to 662500
4864 10:07:14.012214 Read voltage for 933, 3
4865 10:07:14.012767 Vio18 = 0
4866 10:07:14.013139 Vcore = 662500
4867 10:07:14.016038 Vdram = 0
4868 10:07:14.016501 Vddq = 0
4869 10:07:14.016869 Vmddr = 0
4870 10:07:14.022019 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4871 10:07:14.025552 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4872 10:07:14.029553 MEM_TYPE=3, freq_sel=17
4873 10:07:14.032365 sv_algorithm_assistance_LP4_1600
4874 10:07:14.035666 ============ PULL DRAM RESETB DOWN ============
4875 10:07:14.042047 ========== PULL DRAM RESETB DOWN end =========
4876 10:07:14.045559 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4877 10:07:14.048589 ===================================
4878 10:07:14.051641 LPDDR4 DRAM CONFIGURATION
4879 10:07:14.054980 ===================================
4880 10:07:14.055452 EX_ROW_EN[0] = 0x0
4881 10:07:14.058198 EX_ROW_EN[1] = 0x0
4882 10:07:14.058661 LP4Y_EN = 0x0
4883 10:07:14.062025 WORK_FSP = 0x0
4884 10:07:14.062578 WL = 0x3
4885 10:07:14.065004 RL = 0x3
4886 10:07:14.068350 BL = 0x2
4887 10:07:14.068818 RPST = 0x0
4888 10:07:14.071389 RD_PRE = 0x0
4889 10:07:14.071852 WR_PRE = 0x1
4890 10:07:14.075139 WR_PST = 0x0
4891 10:07:14.075605 DBI_WR = 0x0
4892 10:07:14.078393 DBI_RD = 0x0
4893 10:07:14.079006 OTF = 0x1
4894 10:07:14.081709 ===================================
4895 10:07:14.084723 ===================================
4896 10:07:14.087635 ANA top config
4897 10:07:14.091392 ===================================
4898 10:07:14.091855 DLL_ASYNC_EN = 0
4899 10:07:14.094570 ALL_SLAVE_EN = 1
4900 10:07:14.098020 NEW_RANK_MODE = 1
4901 10:07:14.101261 DLL_IDLE_MODE = 1
4902 10:07:14.104386 LP45_APHY_COMB_EN = 1
4903 10:07:14.104945 TX_ODT_DIS = 1
4904 10:07:14.107592 NEW_8X_MODE = 1
4905 10:07:14.110954 ===================================
4906 10:07:14.114344 ===================================
4907 10:07:14.117503 data_rate = 1866
4908 10:07:14.120777 CKR = 1
4909 10:07:14.124252 DQ_P2S_RATIO = 8
4910 10:07:14.127157 ===================================
4911 10:07:14.131039 CA_P2S_RATIO = 8
4912 10:07:14.131591 DQ_CA_OPEN = 0
4913 10:07:14.134198 DQ_SEMI_OPEN = 0
4914 10:07:14.137479 CA_SEMI_OPEN = 0
4915 10:07:14.140537 CA_FULL_RATE = 0
4916 10:07:14.144121 DQ_CKDIV4_EN = 1
4917 10:07:14.147053 CA_CKDIV4_EN = 1
4918 10:07:14.147632 CA_PREDIV_EN = 0
4919 10:07:14.150406 PH8_DLY = 0
4920 10:07:14.153635 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4921 10:07:14.157546 DQ_AAMCK_DIV = 4
4922 10:07:14.160328 CA_AAMCK_DIV = 4
4923 10:07:14.163530 CA_ADMCK_DIV = 4
4924 10:07:14.164083 DQ_TRACK_CA_EN = 0
4925 10:07:14.166954 CA_PICK = 933
4926 10:07:14.170416 CA_MCKIO = 933
4927 10:07:14.173611 MCKIO_SEMI = 0
4928 10:07:14.176789 PLL_FREQ = 3732
4929 10:07:14.179935 DQ_UI_PI_RATIO = 32
4930 10:07:14.183467 CA_UI_PI_RATIO = 0
4931 10:07:14.186348 ===================================
4932 10:07:14.189853 ===================================
4933 10:07:14.190318 memory_type:LPDDR4
4934 10:07:14.192892 GP_NUM : 10
4935 10:07:14.196589 SRAM_EN : 1
4936 10:07:14.197045 MD32_EN : 0
4937 10:07:14.199771 ===================================
4938 10:07:14.203141 [ANA_INIT] >>>>>>>>>>>>>>
4939 10:07:14.206301 <<<<<< [CONFIGURE PHASE]: ANA_TX
4940 10:07:14.209822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4941 10:07:14.212882 ===================================
4942 10:07:14.216067 data_rate = 1866,PCW = 0X8f00
4943 10:07:14.219400 ===================================
4944 10:07:14.222752 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4945 10:07:14.226341 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4946 10:07:14.232900 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4947 10:07:14.235984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4948 10:07:14.242550 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4949 10:07:14.246267 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4950 10:07:14.246899 [ANA_INIT] flow start
4951 10:07:14.249024 [ANA_INIT] PLL >>>>>>>>
4952 10:07:14.252839 [ANA_INIT] PLL <<<<<<<<
4953 10:07:14.253319 [ANA_INIT] MIDPI >>>>>>>>
4954 10:07:14.255575 [ANA_INIT] MIDPI <<<<<<<<
4955 10:07:14.259351 [ANA_INIT] DLL >>>>>>>>
4956 10:07:14.259916 [ANA_INIT] flow end
4957 10:07:14.265809 ============ LP4 DIFF to SE enter ============
4958 10:07:14.269222 ============ LP4 DIFF to SE exit ============
4959 10:07:14.269685 [ANA_INIT] <<<<<<<<<<<<<
4960 10:07:14.272515 [Flow] Enable top DCM control >>>>>
4961 10:07:14.275512 [Flow] Enable top DCM control <<<<<
4962 10:07:14.278819 Enable DLL master slave shuffle
4963 10:07:14.285471 ==============================================================
4964 10:07:14.289099 Gating Mode config
4965 10:07:14.292094 ==============================================================
4966 10:07:14.295394 Config description:
4967 10:07:14.305467 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4968 10:07:14.312345 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4969 10:07:14.315580 SELPH_MODE 0: By rank 1: By Phase
4970 10:07:14.321638 ==============================================================
4971 10:07:14.325946 GAT_TRACK_EN = 1
4972 10:07:14.328473 RX_GATING_MODE = 2
4973 10:07:14.331609 RX_GATING_TRACK_MODE = 2
4974 10:07:14.335107 SELPH_MODE = 1
4975 10:07:14.335663 PICG_EARLY_EN = 1
4976 10:07:14.338662 VALID_LAT_VALUE = 1
4977 10:07:14.344802 ==============================================================
4978 10:07:14.348107 Enter into Gating configuration >>>>
4979 10:07:14.351721 Exit from Gating configuration <<<<
4980 10:07:14.355006 Enter into DVFS_PRE_config >>>>>
4981 10:07:14.364580 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4982 10:07:14.368150 Exit from DVFS_PRE_config <<<<<
4983 10:07:14.371501 Enter into PICG configuration >>>>
4984 10:07:14.374468 Exit from PICG configuration <<<<
4985 10:07:14.377839 [RX_INPUT] configuration >>>>>
4986 10:07:14.381242 [RX_INPUT] configuration <<<<<
4987 10:07:14.387566 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4988 10:07:14.390675 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4989 10:07:14.397209 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4990 10:07:14.403772 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4991 10:07:14.410965 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4992 10:07:14.417102 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4993 10:07:14.420081 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4994 10:07:14.423754 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4995 10:07:14.427111 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4996 10:07:14.434001 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4997 10:07:14.436895 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4998 10:07:14.440198 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4999 10:07:14.443519 ===================================
5000 10:07:14.447206 LPDDR4 DRAM CONFIGURATION
5001 10:07:14.450174 ===================================
5002 10:07:14.453438 EX_ROW_EN[0] = 0x0
5003 10:07:14.453996 EX_ROW_EN[1] = 0x0
5004 10:07:14.456650 LP4Y_EN = 0x0
5005 10:07:14.457208 WORK_FSP = 0x0
5006 10:07:14.459813 WL = 0x3
5007 10:07:14.460368 RL = 0x3
5008 10:07:14.463399 BL = 0x2
5009 10:07:14.463854 RPST = 0x0
5010 10:07:14.466459 RD_PRE = 0x0
5011 10:07:14.467198 WR_PRE = 0x1
5012 10:07:14.469856 WR_PST = 0x0
5013 10:07:14.470408 DBI_WR = 0x0
5014 10:07:14.473168 DBI_RD = 0x0
5015 10:07:14.473637 OTF = 0x1
5016 10:07:14.476267 ===================================
5017 10:07:14.482738 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5018 10:07:14.486262 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5019 10:07:14.489423 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5020 10:07:14.492600 ===================================
5021 10:07:14.495912 LPDDR4 DRAM CONFIGURATION
5022 10:07:14.498992 ===================================
5023 10:07:14.502420 EX_ROW_EN[0] = 0x10
5024 10:07:14.503196 EX_ROW_EN[1] = 0x0
5025 10:07:14.505783 LP4Y_EN = 0x0
5026 10:07:14.506252 WORK_FSP = 0x0
5027 10:07:14.509265 WL = 0x3
5028 10:07:14.509817 RL = 0x3
5029 10:07:14.512769 BL = 0x2
5030 10:07:14.513324 RPST = 0x0
5031 10:07:14.515819 RD_PRE = 0x0
5032 10:07:14.518996 WR_PRE = 0x1
5033 10:07:14.519453 WR_PST = 0x0
5034 10:07:14.522340 DBI_WR = 0x0
5035 10:07:14.522796 DBI_RD = 0x0
5036 10:07:14.525652 OTF = 0x1
5037 10:07:14.529286 ===================================
5038 10:07:14.532294 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5039 10:07:14.537563 nWR fixed to 30
5040 10:07:14.540799 [ModeRegInit_LP4] CH0 RK0
5041 10:07:14.541262 [ModeRegInit_LP4] CH0 RK1
5042 10:07:14.544382 [ModeRegInit_LP4] CH1 RK0
5043 10:07:14.547708 [ModeRegInit_LP4] CH1 RK1
5044 10:07:14.548267 match AC timing 9
5045 10:07:14.554415 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5046 10:07:14.557364 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5047 10:07:14.560932 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5048 10:07:14.567224 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5049 10:07:14.570714 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5050 10:07:14.571308 ==
5051 10:07:14.573796 Dram Type= 6, Freq= 0, CH_0, rank 0
5052 10:07:14.576780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5053 10:07:14.577245 ==
5054 10:07:14.583488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5055 10:07:14.590586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5056 10:07:14.593818 [CA 0] Center 38 (8~69) winsize 62
5057 10:07:14.597045 [CA 1] Center 38 (7~69) winsize 63
5058 10:07:14.600128 [CA 2] Center 35 (5~66) winsize 62
5059 10:07:14.603389 [CA 3] Center 35 (4~66) winsize 63
5060 10:07:14.606509 [CA 4] Center 34 (4~65) winsize 62
5061 10:07:14.609972 [CA 5] Center 33 (3~64) winsize 62
5062 10:07:14.610541
5063 10:07:14.613505 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5064 10:07:14.614070
5065 10:07:14.616240 [CATrainingPosCal] consider 1 rank data
5066 10:07:14.619871 u2DelayCellTimex100 = 270/100 ps
5067 10:07:14.623009 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5068 10:07:14.626285 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5069 10:07:14.630080 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5070 10:07:14.636536 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5071 10:07:14.639722 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5072 10:07:14.642823 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5073 10:07:14.643503
5074 10:07:14.646156 CA PerBit enable=1, Macro0, CA PI delay=33
5075 10:07:14.646719
5076 10:07:14.649194 [CBTSetCACLKResult] CA Dly = 33
5077 10:07:14.649656 CS Dly: 7 (0~38)
5078 10:07:14.652612 ==
5079 10:07:14.655607 Dram Type= 6, Freq= 0, CH_0, rank 1
5080 10:07:14.658865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5081 10:07:14.659334 ==
5082 10:07:14.662873 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5083 10:07:14.668928 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5084 10:07:14.672861 [CA 0] Center 38 (8~69) winsize 62
5085 10:07:14.676009 [CA 1] Center 38 (8~69) winsize 62
5086 10:07:14.678994 [CA 2] Center 35 (5~66) winsize 62
5087 10:07:14.683032 [CA 3] Center 35 (5~65) winsize 61
5088 10:07:14.686202 [CA 4] Center 34 (4~65) winsize 62
5089 10:07:14.689215 [CA 5] Center 33 (3~64) winsize 62
5090 10:07:14.689751
5091 10:07:14.692799 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5092 10:07:14.693366
5093 10:07:14.695646 [CATrainingPosCal] consider 2 rank data
5094 10:07:14.698797 u2DelayCellTimex100 = 270/100 ps
5095 10:07:14.705618 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5096 10:07:14.708761 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5097 10:07:14.712109 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5098 10:07:14.715572 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5099 10:07:14.718325 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5100 10:07:14.721740 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5101 10:07:14.722205
5102 10:07:14.725310 CA PerBit enable=1, Macro0, CA PI delay=33
5103 10:07:14.725775
5104 10:07:14.728532 [CBTSetCACLKResult] CA Dly = 33
5105 10:07:14.732093 CS Dly: 7 (0~39)
5106 10:07:14.732672
5107 10:07:14.734917 ----->DramcWriteLeveling(PI) begin...
5108 10:07:14.735522 ==
5109 10:07:14.738561 Dram Type= 6, Freq= 0, CH_0, rank 0
5110 10:07:14.741445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 10:07:14.741936 ==
5112 10:07:14.744817 Write leveling (Byte 0): 32 => 32
5113 10:07:14.748017 Write leveling (Byte 1): 27 => 27
5114 10:07:14.751576 DramcWriteLeveling(PI) end<-----
5115 10:07:14.752144
5116 10:07:14.752513 ==
5117 10:07:14.754780 Dram Type= 6, Freq= 0, CH_0, rank 0
5118 10:07:14.758078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 10:07:14.758652 ==
5120 10:07:14.761250 [Gating] SW mode calibration
5121 10:07:14.767985 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5122 10:07:14.774521 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5123 10:07:14.777844 0 14 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
5124 10:07:14.784663 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
5125 10:07:14.787835 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 10:07:14.791000 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 10:07:14.797277 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 10:07:14.800976 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 10:07:14.804357 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 10:07:14.810509 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5131 10:07:14.813695 0 15 0 | B1->B0 | 3333 2727 | 1 0 | (1 1) (0 0)
5132 10:07:14.817016 0 15 4 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
5133 10:07:14.823729 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 10:07:14.826806 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 10:07:14.830180 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 10:07:14.837424 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 10:07:14.840057 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 10:07:14.843864 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 10:07:14.850527 1 0 0 | B1->B0 | 2a2a 4040 | 0 0 | (0 0) (0 0)
5140 10:07:14.853549 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5141 10:07:14.856886 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 10:07:14.863670 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 10:07:14.867229 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 10:07:14.870389 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 10:07:14.876832 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 10:07:14.880177 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 10:07:14.883061 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5148 10:07:14.889746 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 10:07:14.893479 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 10:07:14.896444 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 10:07:14.903000 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 10:07:14.906115 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 10:07:14.909856 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 10:07:14.916531 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 10:07:14.919607 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 10:07:14.922924 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 10:07:14.929590 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 10:07:14.932846 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 10:07:14.936328 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 10:07:14.943173 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 10:07:14.945833 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 10:07:14.949595 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5163 10:07:14.956006 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5164 10:07:14.959128 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5165 10:07:14.962714 Total UI for P1: 0, mck2ui 16
5166 10:07:14.966707 best dqsien dly found for B0: ( 1, 2, 30)
5167 10:07:14.969293 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 10:07:14.972630 Total UI for P1: 0, mck2ui 16
5169 10:07:14.975588 best dqsien dly found for B1: ( 1, 3, 4)
5170 10:07:14.979053 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5171 10:07:14.982722 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5172 10:07:14.983349
5173 10:07:14.985521 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5174 10:07:14.992148 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5175 10:07:14.992708 [Gating] SW calibration Done
5176 10:07:14.995493 ==
5177 10:07:14.996112 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 10:07:15.002059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 10:07:15.002635 ==
5180 10:07:15.003103 RX Vref Scan: 0
5181 10:07:15.003465
5182 10:07:15.005763 RX Vref 0 -> 0, step: 1
5183 10:07:15.006316
5184 10:07:15.008802 RX Delay -80 -> 252, step: 8
5185 10:07:15.011947 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5186 10:07:15.015166 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5187 10:07:15.018369 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5188 10:07:15.025207 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5189 10:07:15.028370 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5190 10:07:15.031494 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5191 10:07:15.035049 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5192 10:07:15.038586 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5193 10:07:15.041444 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5194 10:07:15.048255 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5195 10:07:15.051299 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5196 10:07:15.054625 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5197 10:07:15.058227 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5198 10:07:15.065078 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5199 10:07:15.068219 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5200 10:07:15.071359 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5201 10:07:15.071820 ==
5202 10:07:15.074386 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 10:07:15.077984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 10:07:15.078548 ==
5205 10:07:15.081016 DQS Delay:
5206 10:07:15.081574 DQS0 = 0, DQS1 = 0
5207 10:07:15.084249 DQM Delay:
5208 10:07:15.084708 DQM0 = 94, DQM1 = 82
5209 10:07:15.085076 DQ Delay:
5210 10:07:15.087764 DQ0 =95, DQ1 =95, DQ2 =91, DQ3 =91
5211 10:07:15.091190 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5212 10:07:15.094353 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5213 10:07:15.097570 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =91
5214 10:07:15.098132
5215 10:07:15.100910
5216 10:07:15.101488 ==
5217 10:07:15.104054 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 10:07:15.107712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 10:07:15.108282 ==
5220 10:07:15.108656
5221 10:07:15.108998
5222 10:07:15.110866 TX Vref Scan disable
5223 10:07:15.111333 == TX Byte 0 ==
5224 10:07:15.117246 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5225 10:07:15.120241 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5226 10:07:15.120741 == TX Byte 1 ==
5227 10:07:15.127289 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5228 10:07:15.130486 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5229 10:07:15.131081 ==
5230 10:07:15.133322 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 10:07:15.136832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 10:07:15.137299 ==
5233 10:07:15.137668
5234 10:07:15.138011
5235 10:07:15.140483 TX Vref Scan disable
5236 10:07:15.143159 == TX Byte 0 ==
5237 10:07:15.146999 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5238 10:07:15.150307 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5239 10:07:15.153047 == TX Byte 1 ==
5240 10:07:15.156326 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5241 10:07:15.163425 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5242 10:07:15.163987
5243 10:07:15.164354 [DATLAT]
5244 10:07:15.164700 Freq=933, CH0 RK0
5245 10:07:15.165035
5246 10:07:15.166593 DATLAT Default: 0xd
5247 10:07:15.167075 0, 0xFFFF, sum = 0
5248 10:07:15.169743 1, 0xFFFF, sum = 0
5249 10:07:15.170237 2, 0xFFFF, sum = 0
5250 10:07:15.172984 3, 0xFFFF, sum = 0
5251 10:07:15.176107 4, 0xFFFF, sum = 0
5252 10:07:15.176775 5, 0xFFFF, sum = 0
5253 10:07:15.179787 6, 0xFFFF, sum = 0
5254 10:07:15.180315 7, 0xFFFF, sum = 0
5255 10:07:15.183112 8, 0xFFFF, sum = 0
5256 10:07:15.183583 9, 0xFFFF, sum = 0
5257 10:07:15.186355 10, 0x0, sum = 1
5258 10:07:15.186825 11, 0x0, sum = 2
5259 10:07:15.189726 12, 0x0, sum = 3
5260 10:07:15.190304 13, 0x0, sum = 4
5261 10:07:15.190684 best_step = 11
5262 10:07:15.191094
5263 10:07:15.193133 ==
5264 10:07:15.196428 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 10:07:15.199279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 10:07:15.199857 ==
5267 10:07:15.200415 RX Vref Scan: 1
5268 10:07:15.200779
5269 10:07:15.202516 RX Vref 0 -> 0, step: 1
5270 10:07:15.203011
5271 10:07:15.205829 RX Delay -69 -> 252, step: 4
5272 10:07:15.206362
5273 10:07:15.209303 Set Vref, RX VrefLevel [Byte0]: 61
5274 10:07:15.212835 [Byte1]: 57
5275 10:07:15.215847
5276 10:07:15.216300 Final RX Vref Byte 0 = 61 to rank0
5277 10:07:15.219312 Final RX Vref Byte 1 = 57 to rank0
5278 10:07:15.222716 Final RX Vref Byte 0 = 61 to rank1
5279 10:07:15.225818 Final RX Vref Byte 1 = 57 to rank1==
5280 10:07:15.229317 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 10:07:15.235897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 10:07:15.236363 ==
5283 10:07:15.236735 DQS Delay:
5284 10:07:15.237074 DQS0 = 0, DQS1 = 0
5285 10:07:15.238951 DQM Delay:
5286 10:07:15.239407 DQM0 = 95, DQM1 = 83
5287 10:07:15.242512 DQ Delay:
5288 10:07:15.245790 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5289 10:07:15.248801 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106
5290 10:07:15.252170 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =80
5291 10:07:15.255313 DQ12 =86, DQ13 =88, DQ14 =92, DQ15 =90
5292 10:07:15.255827
5293 10:07:15.256306
5294 10:07:15.262250 [DQSOSCAuto] RK0, (LSB)MR18= 0xe0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 417 ps
5295 10:07:15.265464 CH0 RK0: MR19=505, MR18=E0E
5296 10:07:15.272415 CH0_RK0: MR19=0x505, MR18=0xE0E, DQSOSC=417, MR23=63, INC=62, DEC=41
5297 10:07:15.272864
5298 10:07:15.275482 ----->DramcWriteLeveling(PI) begin...
5299 10:07:15.275933 ==
5300 10:07:15.278719 Dram Type= 6, Freq= 0, CH_0, rank 1
5301 10:07:15.281734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 10:07:15.282178 ==
5303 10:07:15.285011 Write leveling (Byte 0): 31 => 31
5304 10:07:15.288287 Write leveling (Byte 1): 31 => 31
5305 10:07:15.291412 DramcWriteLeveling(PI) end<-----
5306 10:07:15.291729
5307 10:07:15.291922 ==
5308 10:07:15.294663 Dram Type= 6, Freq= 0, CH_0, rank 1
5309 10:07:15.298127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 10:07:15.298787 ==
5311 10:07:15.301351 [Gating] SW mode calibration
5312 10:07:15.308375 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5313 10:07:15.314618 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5314 10:07:15.317772 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5315 10:07:15.324955 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 10:07:15.327785 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 10:07:15.331418 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 10:07:15.337589 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 10:07:15.341383 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 10:07:15.344386 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5321 10:07:15.350751 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
5322 10:07:15.354291 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
5323 10:07:15.357589 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 10:07:15.364214 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 10:07:15.368004 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 10:07:15.370629 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 10:07:15.377062 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 10:07:15.380258 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 10:07:15.383980 0 15 28 | B1->B0 | 2929 3636 | 0 1 | (0 0) (0 0)
5330 10:07:15.390505 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5331 10:07:15.393610 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 10:07:15.397282 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 10:07:15.403580 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 10:07:15.406777 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 10:07:15.410071 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 10:07:15.417151 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 10:07:15.420256 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5338 10:07:15.423463 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5339 10:07:15.430273 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 10:07:15.433140 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 10:07:15.436630 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 10:07:15.443424 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 10:07:15.446594 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 10:07:15.449749 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 10:07:15.456662 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 10:07:15.459353 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 10:07:15.462941 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 10:07:15.469293 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 10:07:15.472723 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 10:07:15.476204 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 10:07:15.482640 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 10:07:15.485894 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 10:07:15.489100 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5354 10:07:15.495502 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5355 10:07:15.499207 Total UI for P1: 0, mck2ui 16
5356 10:07:15.502415 best dqsien dly found for B0: ( 1, 2, 28)
5357 10:07:15.505891 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5358 10:07:15.509174 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 10:07:15.512350 Total UI for P1: 0, mck2ui 16
5360 10:07:15.515755 best dqsien dly found for B1: ( 1, 3, 2)
5361 10:07:15.518882 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5362 10:07:15.522157 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5363 10:07:15.522638
5364 10:07:15.528752 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5365 10:07:15.532003 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5366 10:07:15.535397 [Gating] SW calibration Done
5367 10:07:15.535925 ==
5368 10:07:15.538679 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 10:07:15.541697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 10:07:15.542120 ==
5371 10:07:15.542454 RX Vref Scan: 0
5372 10:07:15.545078
5373 10:07:15.545495 RX Vref 0 -> 0, step: 1
5374 10:07:15.545829
5375 10:07:15.548307 RX Delay -80 -> 252, step: 8
5376 10:07:15.551581 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5377 10:07:15.555061 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5378 10:07:15.561912 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5379 10:07:15.565139 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5380 10:07:15.568069 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5381 10:07:15.571295 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5382 10:07:15.574759 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5383 10:07:15.581461 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5384 10:07:15.584264 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5385 10:07:15.588424 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5386 10:07:15.591354 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5387 10:07:15.594381 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5388 10:07:15.601041 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5389 10:07:15.604023 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5390 10:07:15.607502 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5391 10:07:15.610855 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5392 10:07:15.611275 ==
5393 10:07:15.614758 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 10:07:15.620885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 10:07:15.621389 ==
5396 10:07:15.621722 DQS Delay:
5397 10:07:15.622031 DQS0 = 0, DQS1 = 0
5398 10:07:15.624026 DQM Delay:
5399 10:07:15.624434 DQM0 = 91, DQM1 = 83
5400 10:07:15.627254 DQ Delay:
5401 10:07:15.630980 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =87
5402 10:07:15.634023 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5403 10:07:15.637344 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5404 10:07:15.640832 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5405 10:07:15.641289
5406 10:07:15.641645
5407 10:07:15.641977 ==
5408 10:07:15.643772 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 10:07:15.647336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 10:07:15.647816 ==
5411 10:07:15.648180
5412 10:07:15.648512
5413 10:07:15.650755 TX Vref Scan disable
5414 10:07:15.651438 == TX Byte 0 ==
5415 10:07:15.657359 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5416 10:07:15.660544 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5417 10:07:15.664232 == TX Byte 1 ==
5418 10:07:15.666947 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5419 10:07:15.670332 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5420 10:07:15.670786 ==
5421 10:07:15.673634 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 10:07:15.676846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 10:07:15.679990 ==
5424 10:07:15.680444
5425 10:07:15.680804
5426 10:07:15.681134 TX Vref Scan disable
5427 10:07:15.683864 == TX Byte 0 ==
5428 10:07:15.686796 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5429 10:07:15.693679 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5430 10:07:15.694137 == TX Byte 1 ==
5431 10:07:15.696781 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5432 10:07:15.703333 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5433 10:07:15.703792
5434 10:07:15.704152 [DATLAT]
5435 10:07:15.704490 Freq=933, CH0 RK1
5436 10:07:15.704814
5437 10:07:15.706555 DATLAT Default: 0xb
5438 10:07:15.709817 0, 0xFFFF, sum = 0
5439 10:07:15.710297 1, 0xFFFF, sum = 0
5440 10:07:15.713575 2, 0xFFFF, sum = 0
5441 10:07:15.714042 3, 0xFFFF, sum = 0
5442 10:07:15.716893 4, 0xFFFF, sum = 0
5443 10:07:15.717456 5, 0xFFFF, sum = 0
5444 10:07:15.719991 6, 0xFFFF, sum = 0
5445 10:07:15.720453 7, 0xFFFF, sum = 0
5446 10:07:15.722910 8, 0xFFFF, sum = 0
5447 10:07:15.723377 9, 0xFFFF, sum = 0
5448 10:07:15.726374 10, 0x0, sum = 1
5449 10:07:15.726981 11, 0x0, sum = 2
5450 10:07:15.729943 12, 0x0, sum = 3
5451 10:07:15.730405 13, 0x0, sum = 4
5452 10:07:15.733273 best_step = 11
5453 10:07:15.733832
5454 10:07:15.734195 ==
5455 10:07:15.736317 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 10:07:15.740052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 10:07:15.740612 ==
5458 10:07:15.740981 RX Vref Scan: 0
5459 10:07:15.741323
5460 10:07:15.743170 RX Vref 0 -> 0, step: 1
5461 10:07:15.743649
5462 10:07:15.746375 RX Delay -77 -> 252, step: 4
5463 10:07:15.753073 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5464 10:07:15.756330 iDelay=199, Bit 1, Center 96 (7 ~ 186) 180
5465 10:07:15.759737 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5466 10:07:15.762936 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5467 10:07:15.766071 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5468 10:07:15.772951 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5469 10:07:15.775779 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5470 10:07:15.779139 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5471 10:07:15.782566 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5472 10:07:15.785863 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5473 10:07:15.788969 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5474 10:07:15.795691 iDelay=199, Bit 11, Center 80 (-9 ~ 170) 180
5475 10:07:15.798935 iDelay=199, Bit 12, Center 88 (-5 ~ 182) 188
5476 10:07:15.802440 iDelay=199, Bit 13, Center 88 (-5 ~ 182) 188
5477 10:07:15.805977 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5478 10:07:15.809035 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5479 10:07:15.812416 ==
5480 10:07:15.815272 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 10:07:15.818660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 10:07:15.819270 ==
5483 10:07:15.819643 DQS Delay:
5484 10:07:15.821947 DQS0 = 0, DQS1 = 0
5485 10:07:15.822400 DQM Delay:
5486 10:07:15.825416 DQM0 = 92, DQM1 = 85
5487 10:07:15.825871 DQ Delay:
5488 10:07:15.828827 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
5489 10:07:15.831909 DQ4 =90, DQ5 =80, DQ6 =106, DQ7 =104
5490 10:07:15.835382 DQ8 =80, DQ9 =72, DQ10 =86, DQ11 =80
5491 10:07:15.838508 DQ12 =88, DQ13 =88, DQ14 =94, DQ15 =92
5492 10:07:15.839096
5493 10:07:15.839465
5494 10:07:15.845908 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5495 10:07:15.848464 CH0 RK1: MR19=505, MR18=2F10
5496 10:07:15.855152 CH0_RK1: MR19=0x505, MR18=0x2F10, DQSOSC=407, MR23=63, INC=65, DEC=43
5497 10:07:15.858481 [RxdqsGatingPostProcess] freq 933
5498 10:07:15.864997 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5499 10:07:15.868486 best DQS0 dly(2T, 0.5T) = (0, 10)
5500 10:07:15.871410 best DQS1 dly(2T, 0.5T) = (0, 11)
5501 10:07:15.875184 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5502 10:07:15.878435 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5503 10:07:15.879035 best DQS0 dly(2T, 0.5T) = (0, 10)
5504 10:07:15.881535 best DQS1 dly(2T, 0.5T) = (0, 11)
5505 10:07:15.884914 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5506 10:07:15.888176 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5507 10:07:15.891668 Pre-setting of DQS Precalculation
5508 10:07:15.898093 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5509 10:07:15.898622 ==
5510 10:07:15.901373 Dram Type= 6, Freq= 0, CH_1, rank 0
5511 10:07:15.904938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 10:07:15.905396 ==
5513 10:07:15.911423 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5514 10:07:15.917871 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5515 10:07:15.921450 [CA 0] Center 36 (7~66) winsize 60
5516 10:07:15.924695 [CA 1] Center 37 (7~67) winsize 61
5517 10:07:15.927672 [CA 2] Center 34 (5~64) winsize 60
5518 10:07:15.930985 [CA 3] Center 34 (4~64) winsize 61
5519 10:07:15.934055 [CA 4] Center 34 (5~64) winsize 60
5520 10:07:15.937619 [CA 5] Center 33 (4~63) winsize 60
5521 10:07:15.938176
5522 10:07:15.941208 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5523 10:07:15.941766
5524 10:07:15.944299 [CATrainingPosCal] consider 1 rank data
5525 10:07:15.947665 u2DelayCellTimex100 = 270/100 ps
5526 10:07:15.951041 CA0 delay=36 (7~66),Diff = 3 PI (18 cell)
5527 10:07:15.954005 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5528 10:07:15.957510 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5529 10:07:15.960794 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5530 10:07:15.963852 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5531 10:07:15.967453 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5532 10:07:15.968090
5533 10:07:15.974073 CA PerBit enable=1, Macro0, CA PI delay=33
5534 10:07:15.974527
5535 10:07:15.974930 [CBTSetCACLKResult] CA Dly = 33
5536 10:07:15.977247 CS Dly: 6 (0~37)
5537 10:07:15.977812 ==
5538 10:07:15.980403 Dram Type= 6, Freq= 0, CH_1, rank 1
5539 10:07:15.983435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5540 10:07:15.984001 ==
5541 10:07:15.990263 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5542 10:07:15.996831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5543 10:07:16.000185 [CA 0] Center 37 (7~67) winsize 61
5544 10:07:16.003817 [CA 1] Center 37 (7~67) winsize 61
5545 10:07:16.006618 [CA 2] Center 34 (5~64) winsize 60
5546 10:07:16.010235 [CA 3] Center 34 (4~64) winsize 61
5547 10:07:16.013762 [CA 4] Center 34 (5~64) winsize 60
5548 10:07:16.017031 [CA 5] Center 34 (4~64) winsize 61
5549 10:07:16.017590
5550 10:07:16.019947 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5551 10:07:16.020461
5552 10:07:16.023089 [CATrainingPosCal] consider 2 rank data
5553 10:07:16.026967 u2DelayCellTimex100 = 270/100 ps
5554 10:07:16.030154 CA0 delay=36 (7~66),Diff = 3 PI (18 cell)
5555 10:07:16.033606 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5556 10:07:16.036785 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5557 10:07:16.040082 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5558 10:07:16.046724 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5559 10:07:16.049875 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5560 10:07:16.050426
5561 10:07:16.052884 CA PerBit enable=1, Macro0, CA PI delay=33
5562 10:07:16.053341
5563 10:07:16.056268 [CBTSetCACLKResult] CA Dly = 33
5564 10:07:16.056825 CS Dly: 7 (0~39)
5565 10:07:16.057191
5566 10:07:16.059976 ----->DramcWriteLeveling(PI) begin...
5567 10:07:16.060541 ==
5568 10:07:16.062886 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 10:07:16.069631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 10:07:16.070195 ==
5571 10:07:16.072699 Write leveling (Byte 0): 29 => 29
5572 10:07:16.076215 Write leveling (Byte 1): 29 => 29
5573 10:07:16.076781 DramcWriteLeveling(PI) end<-----
5574 10:07:16.077155
5575 10:07:16.079597 ==
5576 10:07:16.082669 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 10:07:16.085751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 10:07:16.086207 ==
5579 10:07:16.089152 [Gating] SW mode calibration
5580 10:07:16.096076 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5581 10:07:16.099332 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5582 10:07:16.105769 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5583 10:07:16.109577 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 10:07:16.112246 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 10:07:16.118928 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 10:07:16.122043 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 10:07:16.125162 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 10:07:16.132111 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 10:07:16.135418 0 14 28 | B1->B0 | 2e2e 3030 | 1 1 | (1 0) (1 0)
5590 10:07:16.138382 0 15 0 | B1->B0 | 2525 2929 | 0 0 | (1 0) (0 0)
5591 10:07:16.145150 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 10:07:16.148559 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 10:07:16.152133 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 10:07:16.158791 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 10:07:16.161916 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 10:07:16.165145 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 10:07:16.171451 0 15 28 | B1->B0 | 3a3a 3636 | 0 0 | (0 0) (0 0)
5598 10:07:16.174980 1 0 0 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
5599 10:07:16.177998 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 10:07:16.184535 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 10:07:16.187958 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 10:07:16.191335 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 10:07:16.197593 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 10:07:16.201329 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 10:07:16.204060 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5606 10:07:16.211201 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5607 10:07:16.214397 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 10:07:16.217691 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 10:07:16.224574 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 10:07:16.227375 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 10:07:16.230892 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 10:07:16.237733 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 10:07:16.240922 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 10:07:16.243941 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 10:07:16.250711 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 10:07:16.254170 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 10:07:16.257162 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 10:07:16.264102 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 10:07:16.267165 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 10:07:16.270494 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 10:07:16.277237 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5622 10:07:16.280235 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5623 10:07:16.283458 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 10:07:16.286895 Total UI for P1: 0, mck2ui 16
5625 10:07:16.289903 best dqsien dly found for B0: ( 1, 2, 30)
5626 10:07:16.293189 Total UI for P1: 0, mck2ui 16
5627 10:07:16.296811 best dqsien dly found for B1: ( 1, 2, 30)
5628 10:07:16.303376 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5629 10:07:16.306255 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5630 10:07:16.306723
5631 10:07:16.309702 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5632 10:07:16.312805 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5633 10:07:16.316300 [Gating] SW calibration Done
5634 10:07:16.316855 ==
5635 10:07:16.319117 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 10:07:16.322547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 10:07:16.323044 ==
5638 10:07:16.325825 RX Vref Scan: 0
5639 10:07:16.326279
5640 10:07:16.326640 RX Vref 0 -> 0, step: 1
5641 10:07:16.327042
5642 10:07:16.329447 RX Delay -80 -> 252, step: 8
5643 10:07:16.332241 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5644 10:07:16.339325 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5645 10:07:16.342282 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5646 10:07:16.345461 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5647 10:07:16.349024 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5648 10:07:16.352176 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5649 10:07:16.359424 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5650 10:07:16.362146 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5651 10:07:16.365350 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5652 10:07:16.368599 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5653 10:07:16.372251 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5654 10:07:16.378512 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5655 10:07:16.381778 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5656 10:07:16.385313 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5657 10:07:16.388385 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5658 10:07:16.391562 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5659 10:07:16.392023 ==
5660 10:07:16.394856 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 10:07:16.401342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 10:07:16.401895 ==
5663 10:07:16.402263 DQS Delay:
5664 10:07:16.404857 DQS0 = 0, DQS1 = 0
5665 10:07:16.405361 DQM Delay:
5666 10:07:16.405951 DQM0 = 94, DQM1 = 90
5667 10:07:16.408187 DQ Delay:
5668 10:07:16.411244 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5669 10:07:16.414625 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5670 10:07:16.418241 DQ8 =83, DQ9 =83, DQ10 =87, DQ11 =87
5671 10:07:16.421284 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5672 10:07:16.421775
5673 10:07:16.422167
5674 10:07:16.422508 ==
5675 10:07:16.424208 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 10:07:16.427570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 10:07:16.428030 ==
5678 10:07:16.428394
5679 10:07:16.428729
5680 10:07:16.431017 TX Vref Scan disable
5681 10:07:16.434452 == TX Byte 0 ==
5682 10:07:16.438042 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5683 10:07:16.441052 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5684 10:07:16.444111 == TX Byte 1 ==
5685 10:07:16.447609 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5686 10:07:16.451033 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5687 10:07:16.451586 ==
5688 10:07:16.454004 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 10:07:16.457442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 10:07:16.460884 ==
5691 10:07:16.461343
5692 10:07:16.461701
5693 10:07:16.462069 TX Vref Scan disable
5694 10:07:16.464363 == TX Byte 0 ==
5695 10:07:16.467557 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5696 10:07:16.474610 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5697 10:07:16.475218 == TX Byte 1 ==
5698 10:07:16.477778 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5699 10:07:16.484100 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5700 10:07:16.484654
5701 10:07:16.485017 [DATLAT]
5702 10:07:16.485354 Freq=933, CH1 RK0
5703 10:07:16.485682
5704 10:07:16.487189 DATLAT Default: 0xd
5705 10:07:16.490667 0, 0xFFFF, sum = 0
5706 10:07:16.491349 1, 0xFFFF, sum = 0
5707 10:07:16.494146 2, 0xFFFF, sum = 0
5708 10:07:16.494706 3, 0xFFFF, sum = 0
5709 10:07:16.497105 4, 0xFFFF, sum = 0
5710 10:07:16.497701 5, 0xFFFF, sum = 0
5711 10:07:16.500314 6, 0xFFFF, sum = 0
5712 10:07:16.500785 7, 0xFFFF, sum = 0
5713 10:07:16.503956 8, 0xFFFF, sum = 0
5714 10:07:16.504675 9, 0xFFFF, sum = 0
5715 10:07:16.506727 10, 0x0, sum = 1
5716 10:07:16.507244 11, 0x0, sum = 2
5717 10:07:16.510643 12, 0x0, sum = 3
5718 10:07:16.511259 13, 0x0, sum = 4
5719 10:07:16.513367 best_step = 11
5720 10:07:16.513827
5721 10:07:16.514200 ==
5722 10:07:16.516956 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 10:07:16.520088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 10:07:16.520552 ==
5725 10:07:16.523229 RX Vref Scan: 1
5726 10:07:16.523680
5727 10:07:16.524042 RX Vref 0 -> 0, step: 1
5728 10:07:16.524383
5729 10:07:16.526760 RX Delay -53 -> 252, step: 4
5730 10:07:16.527265
5731 10:07:16.529873 Set Vref, RX VrefLevel [Byte0]: 58
5732 10:07:16.533195 [Byte1]: 48
5733 10:07:16.537196
5734 10:07:16.537754 Final RX Vref Byte 0 = 58 to rank0
5735 10:07:16.540432 Final RX Vref Byte 1 = 48 to rank0
5736 10:07:16.543918 Final RX Vref Byte 0 = 58 to rank1
5737 10:07:16.547163 Final RX Vref Byte 1 = 48 to rank1==
5738 10:07:16.550263 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 10:07:16.556911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 10:07:16.557464 ==
5741 10:07:16.557833 DQS Delay:
5742 10:07:16.559662 DQS0 = 0, DQS1 = 0
5743 10:07:16.560116 DQM Delay:
5744 10:07:16.560476 DQM0 = 95, DQM1 = 87
5745 10:07:16.563676 DQ Delay:
5746 10:07:16.566728 DQ0 =100, DQ1 =90, DQ2 =86, DQ3 =92
5747 10:07:16.569897 DQ4 =92, DQ5 =106, DQ6 =104, DQ7 =92
5748 10:07:16.573264 DQ8 =74, DQ9 =78, DQ10 =88, DQ11 =80
5749 10:07:16.576805 DQ12 =96, DQ13 =94, DQ14 =96, DQ15 =94
5750 10:07:16.577364
5751 10:07:16.577732
5752 10:07:16.583499 [DQSOSCAuto] RK0, (LSB)MR18= 0xff08, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5753 10:07:16.586557 CH1 RK0: MR19=405, MR18=FF08
5754 10:07:16.592934 CH1_RK0: MR19=0x405, MR18=0xFF08, DQSOSC=419, MR23=63, INC=61, DEC=41
5755 10:07:16.593493
5756 10:07:16.596671 ----->DramcWriteLeveling(PI) begin...
5757 10:07:16.597234 ==
5758 10:07:16.599480 Dram Type= 6, Freq= 0, CH_1, rank 1
5759 10:07:16.603680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 10:07:16.604237 ==
5761 10:07:16.606039 Write leveling (Byte 0): 25 => 25
5762 10:07:16.609547 Write leveling (Byte 1): 26 => 26
5763 10:07:16.612777 DramcWriteLeveling(PI) end<-----
5764 10:07:16.613347
5765 10:07:16.613837 ==
5766 10:07:16.616332 Dram Type= 6, Freq= 0, CH_1, rank 1
5767 10:07:16.619342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 10:07:16.622993 ==
5769 10:07:16.623552 [Gating] SW mode calibration
5770 10:07:16.632509 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5771 10:07:16.635503 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5772 10:07:16.639055 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 10:07:16.645815 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 10:07:16.649331 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 10:07:16.652438 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 10:07:16.658908 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 10:07:16.662550 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 10:07:16.665311 0 14 24 | B1->B0 | 3131 2f2f | 0 1 | (0 0) (1 0)
5779 10:07:16.671942 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
5780 10:07:16.675350 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 10:07:16.678966 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 10:07:16.685590 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 10:07:16.688480 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 10:07:16.691575 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 10:07:16.698295 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 10:07:16.702053 0 15 24 | B1->B0 | 2a2a 3232 | 1 0 | (0 0) (0 0)
5787 10:07:16.705358 0 15 28 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
5788 10:07:16.711865 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 10:07:16.714765 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 10:07:16.718198 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 10:07:16.724851 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 10:07:16.728606 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 10:07:16.730979 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 10:07:16.738210 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5795 10:07:16.740969 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5796 10:07:16.744614 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5797 10:07:16.750909 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 10:07:16.754272 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 10:07:16.757379 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 10:07:16.764525 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 10:07:16.767840 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 10:07:16.770977 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 10:07:16.777342 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 10:07:16.780590 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 10:07:16.784371 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 10:07:16.790493 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 10:07:16.794092 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 10:07:16.797189 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 10:07:16.803939 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 10:07:16.807189 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5811 10:07:16.810202 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5812 10:07:16.817280 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5813 10:07:16.819941 Total UI for P1: 0, mck2ui 16
5814 10:07:16.823280 best dqsien dly found for B0: ( 1, 2, 26)
5815 10:07:16.826549 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 10:07:16.830002 Total UI for P1: 0, mck2ui 16
5817 10:07:16.833745 best dqsien dly found for B1: ( 1, 2, 30)
5818 10:07:16.836622 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5819 10:07:16.840011 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5820 10:07:16.840471
5821 10:07:16.843384 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5822 10:07:16.850009 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5823 10:07:16.850574 [Gating] SW calibration Done
5824 10:07:16.850993 ==
5825 10:07:16.853378 Dram Type= 6, Freq= 0, CH_1, rank 1
5826 10:07:16.859989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5827 10:07:16.860553 ==
5828 10:07:16.860920 RX Vref Scan: 0
5829 10:07:16.861265
5830 10:07:16.863416 RX Vref 0 -> 0, step: 1
5831 10:07:16.863977
5832 10:07:16.866241 RX Delay -80 -> 252, step: 8
5833 10:07:16.870020 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5834 10:07:16.872800 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5835 10:07:16.876261 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5836 10:07:16.883126 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5837 10:07:16.886295 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5838 10:07:16.889813 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5839 10:07:16.892922 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5840 10:07:16.896146 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5841 10:07:16.899172 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5842 10:07:16.905759 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5843 10:07:16.909474 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5844 10:07:16.912631 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5845 10:07:16.916011 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5846 10:07:16.919262 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5847 10:07:16.925535 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5848 10:07:16.929191 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5849 10:07:16.929773 ==
5850 10:07:16.932568 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 10:07:16.935734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 10:07:16.936201 ==
5853 10:07:16.936569 DQS Delay:
5854 10:07:16.939036 DQS0 = 0, DQS1 = 0
5855 10:07:16.939491 DQM Delay:
5856 10:07:16.942492 DQM0 = 95, DQM1 = 88
5857 10:07:16.943100 DQ Delay:
5858 10:07:16.945295 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5859 10:07:16.949307 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5860 10:07:16.951869 DQ8 =75, DQ9 =79, DQ10 =95, DQ11 =79
5861 10:07:16.955414 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5862 10:07:16.956001
5863 10:07:16.956373
5864 10:07:16.956707 ==
5865 10:07:16.958886 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 10:07:16.965219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 10:07:16.965797 ==
5868 10:07:16.966175
5869 10:07:16.966666
5870 10:07:16.967196 TX Vref Scan disable
5871 10:07:16.968930 == TX Byte 0 ==
5872 10:07:16.972079 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5873 10:07:16.978984 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5874 10:07:16.979550 == TX Byte 1 ==
5875 10:07:16.982238 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5876 10:07:16.988551 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5877 10:07:16.989115 ==
5878 10:07:16.991972 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 10:07:16.994987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 10:07:16.995460 ==
5881 10:07:16.995830
5882 10:07:16.996172
5883 10:07:16.998147 TX Vref Scan disable
5884 10:07:17.001969 == TX Byte 0 ==
5885 10:07:17.005120 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5886 10:07:17.007983 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5887 10:07:17.011124 == TX Byte 1 ==
5888 10:07:17.014557 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5889 10:07:17.018621 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5890 10:07:17.019234
5891 10:07:17.019608 [DATLAT]
5892 10:07:17.021628 Freq=933, CH1 RK1
5893 10:07:17.022215
5894 10:07:17.024566 DATLAT Default: 0xb
5895 10:07:17.025030 0, 0xFFFF, sum = 0
5896 10:07:17.028136 1, 0xFFFF, sum = 0
5897 10:07:17.028712 2, 0xFFFF, sum = 0
5898 10:07:17.031116 3, 0xFFFF, sum = 0
5899 10:07:17.031587 4, 0xFFFF, sum = 0
5900 10:07:17.034812 5, 0xFFFF, sum = 0
5901 10:07:17.035332 6, 0xFFFF, sum = 0
5902 10:07:17.037877 7, 0xFFFF, sum = 0
5903 10:07:17.038450 8, 0xFFFF, sum = 0
5904 10:07:17.041161 9, 0xFFFF, sum = 0
5905 10:07:17.041736 10, 0x0, sum = 1
5906 10:07:17.044250 11, 0x0, sum = 2
5907 10:07:17.044721 12, 0x0, sum = 3
5908 10:07:17.047793 13, 0x0, sum = 4
5909 10:07:17.048367 best_step = 11
5910 10:07:17.048735
5911 10:07:17.049078 ==
5912 10:07:17.051185 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 10:07:17.054361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 10:07:17.057569 ==
5915 10:07:17.058131 RX Vref Scan: 0
5916 10:07:17.058500
5917 10:07:17.060794 RX Vref 0 -> 0, step: 1
5918 10:07:17.061306
5919 10:07:17.063819 RX Delay -69 -> 252, step: 4
5920 10:07:17.067353 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5921 10:07:17.070340 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5922 10:07:17.077360 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5923 10:07:17.080488 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5924 10:07:17.084083 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5925 10:07:17.087003 iDelay=203, Bit 5, Center 104 (11 ~ 198) 188
5926 10:07:17.090643 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5927 10:07:17.097224 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5928 10:07:17.100213 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5929 10:07:17.104015 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5930 10:07:17.107438 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5931 10:07:17.110280 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5932 10:07:17.116756 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5933 10:07:17.119996 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5934 10:07:17.123494 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5935 10:07:17.126740 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5936 10:07:17.127232 ==
5937 10:07:17.130204 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 10:07:17.133116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 10:07:17.136676 ==
5940 10:07:17.137140 DQS Delay:
5941 10:07:17.137509 DQS0 = 0, DQS1 = 0
5942 10:07:17.139501 DQM Delay:
5943 10:07:17.139965 DQM0 = 93, DQM1 = 91
5944 10:07:17.142973 DQ Delay:
5945 10:07:17.143434 DQ0 =96, DQ1 =88, DQ2 =82, DQ3 =90
5946 10:07:17.146562 DQ4 =90, DQ5 =104, DQ6 =104, DQ7 =90
5947 10:07:17.149640 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =84
5948 10:07:17.156272 DQ12 =98, DQ13 =98, DQ14 =100, DQ15 =98
5949 10:07:17.156827
5950 10:07:17.157197
5951 10:07:17.162922 [DQSOSCAuto] RK1, (LSB)MR18= 0xa1e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
5952 10:07:17.166453 CH1 RK1: MR19=505, MR18=A1E
5953 10:07:17.173146 CH1_RK1: MR19=0x505, MR18=0xA1E, DQSOSC=412, MR23=63, INC=63, DEC=42
5954 10:07:17.175861 [RxdqsGatingPostProcess] freq 933
5955 10:07:17.179305 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5956 10:07:17.182249 best DQS0 dly(2T, 0.5T) = (0, 10)
5957 10:07:17.186241 best DQS1 dly(2T, 0.5T) = (0, 10)
5958 10:07:17.189113 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5959 10:07:17.192531 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5960 10:07:17.195954 best DQS0 dly(2T, 0.5T) = (0, 10)
5961 10:07:17.199014 best DQS1 dly(2T, 0.5T) = (0, 10)
5962 10:07:17.202587 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5963 10:07:17.205876 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5964 10:07:17.208841 Pre-setting of DQS Precalculation
5965 10:07:17.211994 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5966 10:07:17.222016 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5967 10:07:17.228807 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5968 10:07:17.229271
5969 10:07:17.229638
5970 10:07:17.231955 [Calibration Summary] 1866 Mbps
5971 10:07:17.232417 CH 0, Rank 0
5972 10:07:17.235181 SW Impedance : PASS
5973 10:07:17.235679 DUTY Scan : NO K
5974 10:07:17.238417 ZQ Calibration : PASS
5975 10:07:17.242394 Jitter Meter : NO K
5976 10:07:17.243002 CBT Training : PASS
5977 10:07:17.245194 Write leveling : PASS
5978 10:07:17.248439 RX DQS gating : PASS
5979 10:07:17.248898 RX DQ/DQS(RDDQC) : PASS
5980 10:07:17.251561 TX DQ/DQS : PASS
5981 10:07:17.255021 RX DATLAT : PASS
5982 10:07:17.255478 RX DQ/DQS(Engine): PASS
5983 10:07:17.258519 TX OE : NO K
5984 10:07:17.259021 All Pass.
5985 10:07:17.259395
5986 10:07:17.261901 CH 0, Rank 1
5987 10:07:17.262380 SW Impedance : PASS
5988 10:07:17.264860 DUTY Scan : NO K
5989 10:07:17.268267 ZQ Calibration : PASS
5990 10:07:17.268755 Jitter Meter : NO K
5991 10:07:17.271539 CBT Training : PASS
5992 10:07:17.274920 Write leveling : PASS
5993 10:07:17.275459 RX DQS gating : PASS
5994 10:07:17.277988 RX DQ/DQS(RDDQC) : PASS
5995 10:07:17.278541 TX DQ/DQS : PASS
5996 10:07:17.281293 RX DATLAT : PASS
5997 10:07:17.285172 RX DQ/DQS(Engine): PASS
5998 10:07:17.285724 TX OE : NO K
5999 10:07:17.287815 All Pass.
6000 10:07:17.288274
6001 10:07:17.288635 CH 1, Rank 0
6002 10:07:17.291211 SW Impedance : PASS
6003 10:07:17.291671 DUTY Scan : NO K
6004 10:07:17.295032 ZQ Calibration : PASS
6005 10:07:17.298405 Jitter Meter : NO K
6006 10:07:17.298994 CBT Training : PASS
6007 10:07:17.301265 Write leveling : PASS
6008 10:07:17.304841 RX DQS gating : PASS
6009 10:07:17.305407 RX DQ/DQS(RDDQC) : PASS
6010 10:07:17.308093 TX DQ/DQS : PASS
6011 10:07:17.311076 RX DATLAT : PASS
6012 10:07:17.311539 RX DQ/DQS(Engine): PASS
6013 10:07:17.314254 TX OE : NO K
6014 10:07:17.314715 All Pass.
6015 10:07:17.315133
6016 10:07:17.318186 CH 1, Rank 1
6017 10:07:17.318643 SW Impedance : PASS
6018 10:07:17.321240 DUTY Scan : NO K
6019 10:07:17.324397 ZQ Calibration : PASS
6020 10:07:17.324858 Jitter Meter : NO K
6021 10:07:17.327562 CBT Training : PASS
6022 10:07:17.330952 Write leveling : PASS
6023 10:07:17.331412 RX DQS gating : PASS
6024 10:07:17.334300 RX DQ/DQS(RDDQC) : PASS
6025 10:07:17.337578 TX DQ/DQS : PASS
6026 10:07:17.338147 RX DATLAT : PASS
6027 10:07:17.340534 RX DQ/DQS(Engine): PASS
6028 10:07:17.343797 TX OE : NO K
6029 10:07:17.344267 All Pass.
6030 10:07:17.344638
6031 10:07:17.344981 DramC Write-DBI off
6032 10:07:17.348155 PER_BANK_REFRESH: Hybrid Mode
6033 10:07:17.350774 TX_TRACKING: ON
6034 10:07:17.357298 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6035 10:07:17.360663 [FAST_K] Save calibration result to emmc
6036 10:07:17.366982 dramc_set_vcore_voltage set vcore to 650000
6037 10:07:17.367550 Read voltage for 400, 6
6038 10:07:17.370588 Vio18 = 0
6039 10:07:17.371100 Vcore = 650000
6040 10:07:17.371476 Vdram = 0
6041 10:07:17.373919 Vddq = 0
6042 10:07:17.374376 Vmddr = 0
6043 10:07:17.377121 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6044 10:07:17.383390 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6045 10:07:17.387059 MEM_TYPE=3, freq_sel=20
6046 10:07:17.390254 sv_algorithm_assistance_LP4_800
6047 10:07:17.393361 ============ PULL DRAM RESETB DOWN ============
6048 10:07:17.396607 ========== PULL DRAM RESETB DOWN end =========
6049 10:07:17.403709 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6050 10:07:17.406979 ===================================
6051 10:07:17.407543 LPDDR4 DRAM CONFIGURATION
6052 10:07:17.409852 ===================================
6053 10:07:17.413030 EX_ROW_EN[0] = 0x0
6054 10:07:17.413493 EX_ROW_EN[1] = 0x0
6055 10:07:17.417013 LP4Y_EN = 0x0
6056 10:07:17.417576 WORK_FSP = 0x0
6057 10:07:17.420193 WL = 0x2
6058 10:07:17.423073 RL = 0x2
6059 10:07:17.423540 BL = 0x2
6060 10:07:17.426119 RPST = 0x0
6061 10:07:17.426584 RD_PRE = 0x0
6062 10:07:17.429726 WR_PRE = 0x1
6063 10:07:17.430183 WR_PST = 0x0
6064 10:07:17.433097 DBI_WR = 0x0
6065 10:07:17.433663 DBI_RD = 0x0
6066 10:07:17.436230 OTF = 0x1
6067 10:07:17.439943 ===================================
6068 10:07:17.443255 ===================================
6069 10:07:17.443828 ANA top config
6070 10:07:17.446534 ===================================
6071 10:07:17.449691 DLL_ASYNC_EN = 0
6072 10:07:17.452941 ALL_SLAVE_EN = 1
6073 10:07:17.453505 NEW_RANK_MODE = 1
6074 10:07:17.456021 DLL_IDLE_MODE = 1
6075 10:07:17.459581 LP45_APHY_COMB_EN = 1
6076 10:07:17.462592 TX_ODT_DIS = 1
6077 10:07:17.465668 NEW_8X_MODE = 1
6078 10:07:17.469598 ===================================
6079 10:07:17.472788 ===================================
6080 10:07:17.475405 data_rate = 800
6081 10:07:17.475868 CKR = 1
6082 10:07:17.479116 DQ_P2S_RATIO = 4
6083 10:07:17.482228 ===================================
6084 10:07:17.485577 CA_P2S_RATIO = 4
6085 10:07:17.489006 DQ_CA_OPEN = 0
6086 10:07:17.491988 DQ_SEMI_OPEN = 1
6087 10:07:17.495697 CA_SEMI_OPEN = 1
6088 10:07:17.496283 CA_FULL_RATE = 0
6089 10:07:17.498875 DQ_CKDIV4_EN = 0
6090 10:07:17.502455 CA_CKDIV4_EN = 1
6091 10:07:17.505506 CA_PREDIV_EN = 0
6092 10:07:17.509067 PH8_DLY = 0
6093 10:07:17.512006 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6094 10:07:17.512473 DQ_AAMCK_DIV = 0
6095 10:07:17.515343 CA_AAMCK_DIV = 0
6096 10:07:17.518786 CA_ADMCK_DIV = 4
6097 10:07:17.522072 DQ_TRACK_CA_EN = 0
6098 10:07:17.525047 CA_PICK = 800
6099 10:07:17.528796 CA_MCKIO = 400
6100 10:07:17.531786 MCKIO_SEMI = 400
6101 10:07:17.532251 PLL_FREQ = 3016
6102 10:07:17.535275 DQ_UI_PI_RATIO = 32
6103 10:07:17.538545 CA_UI_PI_RATIO = 32
6104 10:07:17.541749 ===================================
6105 10:07:17.544980 ===================================
6106 10:07:17.548086 memory_type:LPDDR4
6107 10:07:17.551535 GP_NUM : 10
6108 10:07:17.552104 SRAM_EN : 1
6109 10:07:17.555144 MD32_EN : 0
6110 10:07:17.558293 ===================================
6111 10:07:17.558887 [ANA_INIT] >>>>>>>>>>>>>>
6112 10:07:17.561612 <<<<<< [CONFIGURE PHASE]: ANA_TX
6113 10:07:17.564788 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6114 10:07:17.568461 ===================================
6115 10:07:17.571310 data_rate = 800,PCW = 0X7400
6116 10:07:17.574525 ===================================
6117 10:07:17.577891 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6118 10:07:17.584429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6119 10:07:17.594403 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6120 10:07:17.601120 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6121 10:07:17.604433 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6122 10:07:17.607396 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6123 10:07:17.610999 [ANA_INIT] flow start
6124 10:07:17.611460 [ANA_INIT] PLL >>>>>>>>
6125 10:07:17.613995 [ANA_INIT] PLL <<<<<<<<
6126 10:07:17.617081 [ANA_INIT] MIDPI >>>>>>>>
6127 10:07:17.617539 [ANA_INIT] MIDPI <<<<<<<<
6128 10:07:17.620596 [ANA_INIT] DLL >>>>>>>>
6129 10:07:17.624048 [ANA_INIT] flow end
6130 10:07:17.627254 ============ LP4 DIFF to SE enter ============
6131 10:07:17.630732 ============ LP4 DIFF to SE exit ============
6132 10:07:17.634026 [ANA_INIT] <<<<<<<<<<<<<
6133 10:07:17.637228 [Flow] Enable top DCM control >>>>>
6134 10:07:17.640238 [Flow] Enable top DCM control <<<<<
6135 10:07:17.643390 Enable DLL master slave shuffle
6136 10:07:17.646483 ==============================================================
6137 10:07:17.650504 Gating Mode config
6138 10:07:17.656907 ==============================================================
6139 10:07:17.657468 Config description:
6140 10:07:17.667064 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6141 10:07:17.673089 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6142 10:07:17.679705 SELPH_MODE 0: By rank 1: By Phase
6143 10:07:17.682582 ==============================================================
6144 10:07:17.686370 GAT_TRACK_EN = 0
6145 10:07:17.689175 RX_GATING_MODE = 2
6146 10:07:17.692866 RX_GATING_TRACK_MODE = 2
6147 10:07:17.696282 SELPH_MODE = 1
6148 10:07:17.699112 PICG_EARLY_EN = 1
6149 10:07:17.702438 VALID_LAT_VALUE = 1
6150 10:07:17.709060 ==============================================================
6151 10:07:17.712545 Enter into Gating configuration >>>>
6152 10:07:17.715419 Exit from Gating configuration <<<<
6153 10:07:17.718630 Enter into DVFS_PRE_config >>>>>
6154 10:07:17.728666 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6155 10:07:17.732416 Exit from DVFS_PRE_config <<<<<
6156 10:07:17.735435 Enter into PICG configuration >>>>
6157 10:07:17.739035 Exit from PICG configuration <<<<
6158 10:07:17.741990 [RX_INPUT] configuration >>>>>
6159 10:07:17.742450 [RX_INPUT] configuration <<<<<
6160 10:07:17.748769 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6161 10:07:17.755197 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6162 10:07:17.762156 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6163 10:07:17.765355 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6164 10:07:17.771754 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6165 10:07:17.778808 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6166 10:07:17.781886 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6167 10:07:17.788220 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6168 10:07:17.791229 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6169 10:07:17.794695 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6170 10:07:17.797843 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6171 10:07:17.804622 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6172 10:07:17.807571 ===================================
6173 10:07:17.808038 LPDDR4 DRAM CONFIGURATION
6174 10:07:17.810918 ===================================
6175 10:07:17.814470 EX_ROW_EN[0] = 0x0
6176 10:07:17.817433 EX_ROW_EN[1] = 0x0
6177 10:07:17.817895 LP4Y_EN = 0x0
6178 10:07:17.821033 WORK_FSP = 0x0
6179 10:07:17.821496 WL = 0x2
6180 10:07:17.823998 RL = 0x2
6181 10:07:17.824458 BL = 0x2
6182 10:07:17.827393 RPST = 0x0
6183 10:07:17.827859 RD_PRE = 0x0
6184 10:07:17.831304 WR_PRE = 0x1
6185 10:07:17.831764 WR_PST = 0x0
6186 10:07:17.834583 DBI_WR = 0x0
6187 10:07:17.835193 DBI_RD = 0x0
6188 10:07:17.837440 OTF = 0x1
6189 10:07:17.840831 ===================================
6190 10:07:17.844032 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6191 10:07:17.847513 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6192 10:07:17.854526 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6193 10:07:17.857519 ===================================
6194 10:07:17.858088 LPDDR4 DRAM CONFIGURATION
6195 10:07:17.860831 ===================================
6196 10:07:17.864194 EX_ROW_EN[0] = 0x10
6197 10:07:17.867261 EX_ROW_EN[1] = 0x0
6198 10:07:17.867826 LP4Y_EN = 0x0
6199 10:07:17.870556 WORK_FSP = 0x0
6200 10:07:17.871155 WL = 0x2
6201 10:07:17.873969 RL = 0x2
6202 10:07:17.874432 BL = 0x2
6203 10:07:17.877157 RPST = 0x0
6204 10:07:17.877619 RD_PRE = 0x0
6205 10:07:17.880633 WR_PRE = 0x1
6206 10:07:17.881198 WR_PST = 0x0
6207 10:07:17.883704 DBI_WR = 0x0
6208 10:07:17.884267 DBI_RD = 0x0
6209 10:07:17.887406 OTF = 0x1
6210 10:07:17.890170 ===================================
6211 10:07:17.896670 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6212 10:07:17.900727 nWR fixed to 30
6213 10:07:17.903476 [ModeRegInit_LP4] CH0 RK0
6214 10:07:17.903949 [ModeRegInit_LP4] CH0 RK1
6215 10:07:17.907277 [ModeRegInit_LP4] CH1 RK0
6216 10:07:17.909971 [ModeRegInit_LP4] CH1 RK1
6217 10:07:17.910540 match AC timing 19
6218 10:07:17.916711 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6219 10:07:17.919778 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6220 10:07:17.923248 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6221 10:07:17.929737 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6222 10:07:17.933561 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6223 10:07:17.934133 ==
6224 10:07:17.936585 Dram Type= 6, Freq= 0, CH_0, rank 0
6225 10:07:17.939701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6226 10:07:17.940277 ==
6227 10:07:17.946456 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6228 10:07:17.952767 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6229 10:07:17.956492 [CA 0] Center 36 (8~64) winsize 57
6230 10:07:17.959407 [CA 1] Center 36 (8~64) winsize 57
6231 10:07:17.962987 [CA 2] Center 36 (8~64) winsize 57
6232 10:07:17.966227 [CA 3] Center 36 (8~64) winsize 57
6233 10:07:17.969357 [CA 4] Center 36 (8~64) winsize 57
6234 10:07:17.972633 [CA 5] Center 36 (8~64) winsize 57
6235 10:07:17.973202
6236 10:07:17.976031 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6237 10:07:17.976493
6238 10:07:17.979422 [CATrainingPosCal] consider 1 rank data
6239 10:07:17.982631 u2DelayCellTimex100 = 270/100 ps
6240 10:07:17.986041 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 10:07:17.989527 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 10:07:17.992330 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 10:07:17.995972 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 10:07:17.998928 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 10:07:18.002265 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 10:07:18.002747
6247 10:07:18.005498 CA PerBit enable=1, Macro0, CA PI delay=36
6248 10:07:18.009169
6249 10:07:18.009739 [CBTSetCACLKResult] CA Dly = 36
6250 10:07:18.012613 CS Dly: 1 (0~32)
6251 10:07:18.013184 ==
6252 10:07:18.015644 Dram Type= 6, Freq= 0, CH_0, rank 1
6253 10:07:18.018617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 10:07:18.019122 ==
6255 10:07:18.025456 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6256 10:07:18.031781 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6257 10:07:18.035297 [CA 0] Center 36 (8~64) winsize 57
6258 10:07:18.038547 [CA 1] Center 36 (8~64) winsize 57
6259 10:07:18.042168 [CA 2] Center 36 (8~64) winsize 57
6260 10:07:18.042776 [CA 3] Center 36 (8~64) winsize 57
6261 10:07:18.045286 [CA 4] Center 36 (8~64) winsize 57
6262 10:07:18.048299 [CA 5] Center 36 (8~64) winsize 57
6263 10:07:18.048766
6264 10:07:18.055353 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6265 10:07:18.055908
6266 10:07:18.058719 [CATrainingPosCal] consider 2 rank data
6267 10:07:18.061891 u2DelayCellTimex100 = 270/100 ps
6268 10:07:18.065181 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 10:07:18.068145 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 10:07:18.071354 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 10:07:18.074801 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 10:07:18.078492 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 10:07:18.081809 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 10:07:18.082363
6275 10:07:18.085011 CA PerBit enable=1, Macro0, CA PI delay=36
6276 10:07:18.085571
6277 10:07:18.088233 [CBTSetCACLKResult] CA Dly = 36
6278 10:07:18.091166 CS Dly: 1 (0~32)
6279 10:07:18.091651
6280 10:07:18.094895 ----->DramcWriteLeveling(PI) begin...
6281 10:07:18.095459 ==
6282 10:07:18.097862 Dram Type= 6, Freq= 0, CH_0, rank 0
6283 10:07:18.101263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 10:07:18.101730 ==
6285 10:07:18.104427 Write leveling (Byte 0): 40 => 8
6286 10:07:18.107692 Write leveling (Byte 1): 40 => 8
6287 10:07:18.111291 DramcWriteLeveling(PI) end<-----
6288 10:07:18.111838
6289 10:07:18.112208 ==
6290 10:07:18.114326 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 10:07:18.117605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 10:07:18.118073 ==
6293 10:07:18.120972 [Gating] SW mode calibration
6294 10:07:18.127462 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6295 10:07:18.134195 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6296 10:07:18.137194 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6297 10:07:18.144118 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6298 10:07:18.147173 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6299 10:07:18.150806 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6300 10:07:18.157191 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 10:07:18.160491 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 10:07:18.163467 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 10:07:18.170592 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 10:07:18.173644 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6305 10:07:18.176768 Total UI for P1: 0, mck2ui 16
6306 10:07:18.180504 best dqsien dly found for B0: ( 0, 14, 24)
6307 10:07:18.183549 Total UI for P1: 0, mck2ui 16
6308 10:07:18.186786 best dqsien dly found for B1: ( 0, 14, 24)
6309 10:07:18.190071 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6310 10:07:18.193519 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6311 10:07:18.194085
6312 10:07:18.196969 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6313 10:07:18.200007 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6314 10:07:18.203132 [Gating] SW calibration Done
6315 10:07:18.203581 ==
6316 10:07:18.206871 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 10:07:18.213042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 10:07:18.213587 ==
6319 10:07:18.213949 RX Vref Scan: 0
6320 10:07:18.214281
6321 10:07:18.216197 RX Vref 0 -> 0, step: 1
6322 10:07:18.216783
6323 10:07:18.219431 RX Delay -410 -> 252, step: 16
6324 10:07:18.222709 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6325 10:07:18.226011 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6326 10:07:18.232976 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6327 10:07:18.235920 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6328 10:07:18.239343 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6329 10:07:18.242628 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6330 10:07:18.249207 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6331 10:07:18.252866 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6332 10:07:18.255599 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6333 10:07:18.259318 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6334 10:07:18.265579 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6335 10:07:18.269517 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6336 10:07:18.272769 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6337 10:07:18.275784 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6338 10:07:18.282322 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6339 10:07:18.285964 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6340 10:07:18.286537 ==
6341 10:07:18.289126 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 10:07:18.292082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 10:07:18.292557 ==
6344 10:07:18.295258 DQS Delay:
6345 10:07:18.295908 DQS0 = 59, DQS1 = 59
6346 10:07:18.298692 DQM Delay:
6347 10:07:18.299277 DQM0 = 18, DQM1 = 10
6348 10:07:18.302784 DQ Delay:
6349 10:07:18.303370 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6350 10:07:18.305802 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6351 10:07:18.309027 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6352 10:07:18.312067 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6353 10:07:18.312612
6354 10:07:18.312967
6355 10:07:18.315225 ==
6356 10:07:18.315770 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 10:07:18.322209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 10:07:18.322756 ==
6359 10:07:18.323236
6360 10:07:18.323710
6361 10:07:18.324891 TX Vref Scan disable
6362 10:07:18.325354 == TX Byte 0 ==
6363 10:07:18.328176 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 10:07:18.334961 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 10:07:18.335413 == TX Byte 1 ==
6366 10:07:18.338175 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 10:07:18.344911 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 10:07:18.345445 ==
6369 10:07:18.348159 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 10:07:18.351610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 10:07:18.352062 ==
6372 10:07:18.352416
6373 10:07:18.352745
6374 10:07:18.354771 TX Vref Scan disable
6375 10:07:18.355371 == TX Byte 0 ==
6376 10:07:18.358237 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6377 10:07:18.364912 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6378 10:07:18.365457 == TX Byte 1 ==
6379 10:07:18.368126 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6380 10:07:18.374732 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6381 10:07:18.375203
6382 10:07:18.375557 [DATLAT]
6383 10:07:18.375888 Freq=400, CH0 RK0
6384 10:07:18.377947
6385 10:07:18.378393 DATLAT Default: 0xf
6386 10:07:18.381128 0, 0xFFFF, sum = 0
6387 10:07:18.381597 1, 0xFFFF, sum = 0
6388 10:07:18.384416 2, 0xFFFF, sum = 0
6389 10:07:18.384871 3, 0xFFFF, sum = 0
6390 10:07:18.387911 4, 0xFFFF, sum = 0
6391 10:07:18.388383 5, 0xFFFF, sum = 0
6392 10:07:18.391330 6, 0xFFFF, sum = 0
6393 10:07:18.391850 7, 0xFFFF, sum = 0
6394 10:07:18.394378 8, 0xFFFF, sum = 0
6395 10:07:18.394863 9, 0xFFFF, sum = 0
6396 10:07:18.397668 10, 0xFFFF, sum = 0
6397 10:07:18.398231 11, 0xFFFF, sum = 0
6398 10:07:18.400819 12, 0xFFFF, sum = 0
6399 10:07:18.401291 13, 0x0, sum = 1
6400 10:07:18.404138 14, 0x0, sum = 2
6401 10:07:18.404711 15, 0x0, sum = 3
6402 10:07:18.407635 16, 0x0, sum = 4
6403 10:07:18.408104 best_step = 14
6404 10:07:18.408468
6405 10:07:18.408810 ==
6406 10:07:18.411086 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 10:07:18.417670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 10:07:18.418241 ==
6409 10:07:18.418616 RX Vref Scan: 1
6410 10:07:18.419008
6411 10:07:18.421344 RX Vref 0 -> 0, step: 1
6412 10:07:18.421900
6413 10:07:18.423902 RX Delay -359 -> 252, step: 8
6414 10:07:18.424366
6415 10:07:18.427271 Set Vref, RX VrefLevel [Byte0]: 61
6416 10:07:18.430684 [Byte1]: 57
6417 10:07:18.433919
6418 10:07:18.434545 Final RX Vref Byte 0 = 61 to rank0
6419 10:07:18.436885 Final RX Vref Byte 1 = 57 to rank0
6420 10:07:18.440349 Final RX Vref Byte 0 = 61 to rank1
6421 10:07:18.443534 Final RX Vref Byte 1 = 57 to rank1==
6422 10:07:18.447095 Dram Type= 6, Freq= 0, CH_0, rank 0
6423 10:07:18.453688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 10:07:18.454255 ==
6425 10:07:18.454632 DQS Delay:
6426 10:07:18.456694 DQS0 = 60, DQS1 = 68
6427 10:07:18.457152 DQM Delay:
6428 10:07:18.457520 DQM0 = 14, DQM1 = 14
6429 10:07:18.460254 DQ Delay:
6430 10:07:18.463359 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =12
6431 10:07:18.466965 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6432 10:07:18.469991 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6433 10:07:18.473419 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6434 10:07:18.473837
6435 10:07:18.474169
6436 10:07:18.480009 [DQSOSCAuto] RK0, (LSB)MR18= 0x8281, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6437 10:07:18.483102 CH0 RK0: MR19=C0C, MR18=8281
6438 10:07:18.490164 CH0_RK0: MR19=0xC0C, MR18=0x8281, DQSOSC=393, MR23=63, INC=382, DEC=254
6439 10:07:18.490688 ==
6440 10:07:18.493365 Dram Type= 6, Freq= 0, CH_0, rank 1
6441 10:07:18.496637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 10:07:18.497206 ==
6443 10:07:18.499636 [Gating] SW mode calibration
6444 10:07:18.506073 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6445 10:07:18.513259 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6446 10:07:18.516502 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6447 10:07:18.519563 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6448 10:07:18.525851 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6449 10:07:18.529315 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6450 10:07:18.535900 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 10:07:18.539288 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 10:07:18.542651 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 10:07:18.545775 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 10:07:18.552560 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6455 10:07:18.555778 Total UI for P1: 0, mck2ui 16
6456 10:07:18.559037 best dqsien dly found for B0: ( 0, 14, 24)
6457 10:07:18.562179 Total UI for P1: 0, mck2ui 16
6458 10:07:18.565406 best dqsien dly found for B1: ( 0, 14, 24)
6459 10:07:18.568845 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6460 10:07:18.572229 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6461 10:07:18.572691
6462 10:07:18.575263 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6463 10:07:18.578404 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6464 10:07:18.582267 [Gating] SW calibration Done
6465 10:07:18.582867 ==
6466 10:07:18.585360 Dram Type= 6, Freq= 0, CH_0, rank 1
6467 10:07:18.588447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 10:07:18.591722 ==
6469 10:07:18.592281 RX Vref Scan: 0
6470 10:07:18.592654
6471 10:07:18.595366 RX Vref 0 -> 0, step: 1
6472 10:07:18.595923
6473 10:07:18.598515 RX Delay -410 -> 252, step: 16
6474 10:07:18.601405 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6475 10:07:18.604768 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6476 10:07:18.608122 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6477 10:07:18.615151 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6478 10:07:18.618272 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6479 10:07:18.621824 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6480 10:07:18.624832 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6481 10:07:18.631357 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6482 10:07:18.635018 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6483 10:07:18.637792 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6484 10:07:18.641539 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6485 10:07:18.648011 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6486 10:07:18.651048 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6487 10:07:18.654511 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6488 10:07:18.660843 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6489 10:07:18.664455 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6490 10:07:18.664917 ==
6491 10:07:18.667313 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 10:07:18.670876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 10:07:18.671447 ==
6494 10:07:18.673825 DQS Delay:
6495 10:07:18.674282 DQS0 = 59, DQS1 = 59
6496 10:07:18.677262 DQM Delay:
6497 10:07:18.677718 DQM0 = 17, DQM1 = 10
6498 10:07:18.678085 DQ Delay:
6499 10:07:18.680930 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6500 10:07:18.683772 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6501 10:07:18.687258 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6502 10:07:18.690553 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6503 10:07:18.691050
6504 10:07:18.691419
6505 10:07:18.691756 ==
6506 10:07:18.693943 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 10:07:18.700388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 10:07:18.700956 ==
6509 10:07:18.701328
6510 10:07:18.701667
6511 10:07:18.703398 TX Vref Scan disable
6512 10:07:18.703870 == TX Byte 0 ==
6513 10:07:18.707225 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6514 10:07:18.713678 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6515 10:07:18.714243 == TX Byte 1 ==
6516 10:07:18.716819 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6517 10:07:18.723783 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6518 10:07:18.724345 ==
6519 10:07:18.726954 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 10:07:18.729995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 10:07:18.730458 ==
6522 10:07:18.730824
6523 10:07:18.731194
6524 10:07:18.733326 TX Vref Scan disable
6525 10:07:18.733887 == TX Byte 0 ==
6526 10:07:18.736380 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6527 10:07:18.743459 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6528 10:07:18.744030 == TX Byte 1 ==
6529 10:07:18.746297 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6530 10:07:18.753241 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6531 10:07:18.753807
6532 10:07:18.754182 [DATLAT]
6533 10:07:18.754536 Freq=400, CH0 RK1
6534 10:07:18.754970
6535 10:07:18.756163 DATLAT Default: 0xe
6536 10:07:18.759677 0, 0xFFFF, sum = 0
6537 10:07:18.760151 1, 0xFFFF, sum = 0
6538 10:07:18.762634 2, 0xFFFF, sum = 0
6539 10:07:18.763151 3, 0xFFFF, sum = 0
6540 10:07:18.766059 4, 0xFFFF, sum = 0
6541 10:07:18.766645 5, 0xFFFF, sum = 0
6542 10:07:18.769641 6, 0xFFFF, sum = 0
6543 10:07:18.770219 7, 0xFFFF, sum = 0
6544 10:07:18.772578 8, 0xFFFF, sum = 0
6545 10:07:18.773048 9, 0xFFFF, sum = 0
6546 10:07:18.775703 10, 0xFFFF, sum = 0
6547 10:07:18.776178 11, 0xFFFF, sum = 0
6548 10:07:18.778951 12, 0xFFFF, sum = 0
6549 10:07:18.779445 13, 0x0, sum = 1
6550 10:07:18.782436 14, 0x0, sum = 2
6551 10:07:18.783064 15, 0x0, sum = 3
6552 10:07:18.785871 16, 0x0, sum = 4
6553 10:07:18.786443 best_step = 14
6554 10:07:18.786820
6555 10:07:18.787229 ==
6556 10:07:18.789166 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 10:07:18.795751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 10:07:18.796321 ==
6559 10:07:18.796692 RX Vref Scan: 0
6560 10:07:18.797034
6561 10:07:18.798654 RX Vref 0 -> 0, step: 1
6562 10:07:18.799156
6563 10:07:18.802071 RX Delay -359 -> 252, step: 8
6564 10:07:18.808891 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6565 10:07:18.812161 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6566 10:07:18.815878 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6567 10:07:18.822034 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6568 10:07:18.825700 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6569 10:07:18.828462 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6570 10:07:18.831744 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6571 10:07:18.838371 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6572 10:07:18.842392 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6573 10:07:18.845183 iDelay=217, Bit 9, Center -68 (-319 ~ 184) 504
6574 10:07:18.848054 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6575 10:07:18.854800 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6576 10:07:18.858163 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6577 10:07:18.860881 iDelay=217, Bit 13, Center -52 (-303 ~ 200) 504
6578 10:07:18.868206 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6579 10:07:18.871023 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6580 10:07:18.871479 ==
6581 10:07:18.873912 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 10:07:18.877448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 10:07:18.877921 ==
6584 10:07:18.880738 DQS Delay:
6585 10:07:18.881300 DQS0 = 60, DQS1 = 68
6586 10:07:18.883958 DQM Delay:
6587 10:07:18.884416 DQM0 = 11, DQM1 = 14
6588 10:07:18.884781 DQ Delay:
6589 10:07:18.887317 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6590 10:07:18.890917 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6591 10:07:18.893744 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6592 10:07:18.897173 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6593 10:07:18.897632
6594 10:07:18.898070
6595 10:07:18.907399 [DQSOSCAuto] RK1, (LSB)MR18= 0xc378, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6596 10:07:18.907964 CH0 RK1: MR19=C0C, MR18=C378
6597 10:07:18.913756 CH0_RK1: MR19=0xC0C, MR18=0xC378, DQSOSC=385, MR23=63, INC=398, DEC=265
6598 10:07:18.917009 [RxdqsGatingPostProcess] freq 400
6599 10:07:18.924035 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6600 10:07:18.926876 best DQS0 dly(2T, 0.5T) = (0, 10)
6601 10:07:18.930063 best DQS1 dly(2T, 0.5T) = (0, 10)
6602 10:07:18.933592 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6603 10:07:18.936626 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6604 10:07:18.940006 best DQS0 dly(2T, 0.5T) = (0, 10)
6605 10:07:18.943472 best DQS1 dly(2T, 0.5T) = (0, 10)
6606 10:07:18.946755 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6607 10:07:18.949927 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6608 10:07:18.953109 Pre-setting of DQS Precalculation
6609 10:07:18.956444 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6610 10:07:18.957011 ==
6611 10:07:18.959842 Dram Type= 6, Freq= 0, CH_1, rank 0
6612 10:07:18.962968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 10:07:18.966202 ==
6614 10:07:18.969411 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6615 10:07:18.976067 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6616 10:07:18.979522 [CA 0] Center 36 (8~64) winsize 57
6617 10:07:18.982729 [CA 1] Center 36 (8~64) winsize 57
6618 10:07:18.985994 [CA 2] Center 36 (8~64) winsize 57
6619 10:07:18.989374 [CA 3] Center 36 (8~64) winsize 57
6620 10:07:18.992146 [CA 4] Center 36 (8~64) winsize 57
6621 10:07:18.995533 [CA 5] Center 36 (8~64) winsize 57
6622 10:07:18.995991
6623 10:07:18.998895 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6624 10:07:18.999353
6625 10:07:19.002354 [CATrainingPosCal] consider 1 rank data
6626 10:07:19.005652 u2DelayCellTimex100 = 270/100 ps
6627 10:07:19.009213 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 10:07:19.012430 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 10:07:19.015447 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 10:07:19.018966 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 10:07:19.022192 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 10:07:19.025435 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 10:07:19.025993
6634 10:07:19.032171 CA PerBit enable=1, Macro0, CA PI delay=36
6635 10:07:19.032741
6636 10:07:19.035229 [CBTSetCACLKResult] CA Dly = 36
6637 10:07:19.035790 CS Dly: 1 (0~32)
6638 10:07:19.036181 ==
6639 10:07:19.038706 Dram Type= 6, Freq= 0, CH_1, rank 1
6640 10:07:19.042190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 10:07:19.042749 ==
6642 10:07:19.048394 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6643 10:07:19.055515 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6644 10:07:19.058608 [CA 0] Center 36 (8~64) winsize 57
6645 10:07:19.061753 [CA 1] Center 36 (8~64) winsize 57
6646 10:07:19.065096 [CA 2] Center 36 (8~64) winsize 57
6647 10:07:19.068114 [CA 3] Center 36 (8~64) winsize 57
6648 10:07:19.071816 [CA 4] Center 36 (8~64) winsize 57
6649 10:07:19.075052 [CA 5] Center 36 (8~64) winsize 57
6650 10:07:19.075515
6651 10:07:19.078475 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6652 10:07:19.079052
6653 10:07:19.081423 [CATrainingPosCal] consider 2 rank data
6654 10:07:19.084821 u2DelayCellTimex100 = 270/100 ps
6655 10:07:19.088652 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 10:07:19.091679 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 10:07:19.094733 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 10:07:19.097854 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 10:07:19.101116 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 10:07:19.104631 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 10:07:19.105089
6662 10:07:19.110928 CA PerBit enable=1, Macro0, CA PI delay=36
6663 10:07:19.111384
6664 10:07:19.111746 [CBTSetCACLKResult] CA Dly = 36
6665 10:07:19.114729 CS Dly: 1 (0~32)
6666 10:07:19.115326
6667 10:07:19.118056 ----->DramcWriteLeveling(PI) begin...
6668 10:07:19.118621 ==
6669 10:07:19.121110 Dram Type= 6, Freq= 0, CH_1, rank 0
6670 10:07:19.124271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 10:07:19.124833 ==
6672 10:07:19.127334 Write leveling (Byte 0): 40 => 8
6673 10:07:19.131177 Write leveling (Byte 1): 40 => 8
6674 10:07:19.134364 DramcWriteLeveling(PI) end<-----
6675 10:07:19.134960
6676 10:07:19.135329 ==
6677 10:07:19.137333 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 10:07:19.140621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 10:07:19.144032 ==
6680 10:07:19.144591 [Gating] SW mode calibration
6681 10:07:19.154264 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6682 10:07:19.157463 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6683 10:07:19.160663 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6684 10:07:19.167514 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6685 10:07:19.170797 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6686 10:07:19.173905 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6687 10:07:19.179943 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 10:07:19.183533 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 10:07:19.186715 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 10:07:19.193405 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 10:07:19.196780 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6692 10:07:19.200120 Total UI for P1: 0, mck2ui 16
6693 10:07:19.202942 best dqsien dly found for B0: ( 0, 14, 24)
6694 10:07:19.206293 Total UI for P1: 0, mck2ui 16
6695 10:07:19.210006 best dqsien dly found for B1: ( 0, 14, 24)
6696 10:07:19.213139 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6697 10:07:19.216521 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6698 10:07:19.217091
6699 10:07:19.219720 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6700 10:07:19.226994 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6701 10:07:19.227575 [Gating] SW calibration Done
6702 10:07:19.227945 ==
6703 10:07:19.229825 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 10:07:19.236148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 10:07:19.236715 ==
6706 10:07:19.237086 RX Vref Scan: 0
6707 10:07:19.237430
6708 10:07:19.239375 RX Vref 0 -> 0, step: 1
6709 10:07:19.239839
6710 10:07:19.243062 RX Delay -410 -> 252, step: 16
6711 10:07:19.246102 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6712 10:07:19.249649 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6713 10:07:19.255992 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6714 10:07:19.259207 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6715 10:07:19.262954 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6716 10:07:19.266175 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6717 10:07:19.272365 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6718 10:07:19.275877 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6719 10:07:19.278976 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6720 10:07:19.282619 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6721 10:07:19.288598 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6722 10:07:19.292368 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6723 10:07:19.295476 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6724 10:07:19.302328 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6725 10:07:19.305780 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6726 10:07:19.308609 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6727 10:07:19.309168 ==
6728 10:07:19.312122 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 10:07:19.318545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 10:07:19.319138 ==
6731 10:07:19.319553 DQS Delay:
6732 10:07:19.321727 DQS0 = 51, DQS1 = 67
6733 10:07:19.322258 DQM Delay:
6734 10:07:19.322639 DQM0 = 12, DQM1 = 19
6735 10:07:19.325114 DQ Delay:
6736 10:07:19.328471 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6737 10:07:19.328935 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6738 10:07:19.331652 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6739 10:07:19.335205 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6740 10:07:19.335761
6741 10:07:19.338307
6742 10:07:19.338882 ==
6743 10:07:19.341549 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 10:07:19.344522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 10:07:19.345015 ==
6746 10:07:19.345385
6747 10:07:19.345729
6748 10:07:19.348236 TX Vref Scan disable
6749 10:07:19.348794 == TX Byte 0 ==
6750 10:07:19.351787 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 10:07:19.358007 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 10:07:19.358577 == TX Byte 1 ==
6753 10:07:19.361732 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 10:07:19.368035 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 10:07:19.368596 ==
6756 10:07:19.371279 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 10:07:19.374498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 10:07:19.375121 ==
6759 10:07:19.375505
6760 10:07:19.375846
6761 10:07:19.378289 TX Vref Scan disable
6762 10:07:19.378881 == TX Byte 0 ==
6763 10:07:19.384604 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6764 10:07:19.387782 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6765 10:07:19.388249 == TX Byte 1 ==
6766 10:07:19.394246 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6767 10:07:19.397335 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6768 10:07:19.397894
6769 10:07:19.398261 [DATLAT]
6770 10:07:19.400923 Freq=400, CH1 RK0
6771 10:07:19.401634
6772 10:07:19.402020 DATLAT Default: 0xf
6773 10:07:19.404323 0, 0xFFFF, sum = 0
6774 10:07:19.404827 1, 0xFFFF, sum = 0
6775 10:07:19.407704 2, 0xFFFF, sum = 0
6776 10:07:19.408173 3, 0xFFFF, sum = 0
6777 10:07:19.411080 4, 0xFFFF, sum = 0
6778 10:07:19.411551 5, 0xFFFF, sum = 0
6779 10:07:19.413947 6, 0xFFFF, sum = 0
6780 10:07:19.414417 7, 0xFFFF, sum = 0
6781 10:07:19.417455 8, 0xFFFF, sum = 0
6782 10:07:19.418019 9, 0xFFFF, sum = 0
6783 10:07:19.420421 10, 0xFFFF, sum = 0
6784 10:07:19.423723 11, 0xFFFF, sum = 0
6785 10:07:19.424344 12, 0xFFFF, sum = 0
6786 10:07:19.427234 13, 0x0, sum = 1
6787 10:07:19.427747 14, 0x0, sum = 2
6788 10:07:19.428150 15, 0x0, sum = 3
6789 10:07:19.430587 16, 0x0, sum = 4
6790 10:07:19.431164 best_step = 14
6791 10:07:19.431542
6792 10:07:19.431888 ==
6793 10:07:19.434180 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 10:07:19.440512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 10:07:19.440982 ==
6796 10:07:19.441348 RX Vref Scan: 1
6797 10:07:19.441693
6798 10:07:19.444000 RX Vref 0 -> 0, step: 1
6799 10:07:19.444559
6800 10:07:19.446980 RX Delay -375 -> 252, step: 8
6801 10:07:19.447447
6802 10:07:19.450403 Set Vref, RX VrefLevel [Byte0]: 58
6803 10:07:19.453385 [Byte1]: 48
6804 10:07:19.457584
6805 10:07:19.458189 Final RX Vref Byte 0 = 58 to rank0
6806 10:07:19.460639 Final RX Vref Byte 1 = 48 to rank0
6807 10:07:19.464094 Final RX Vref Byte 0 = 58 to rank1
6808 10:07:19.467255 Final RX Vref Byte 1 = 48 to rank1==
6809 10:07:19.470719 Dram Type= 6, Freq= 0, CH_1, rank 0
6810 10:07:19.477534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 10:07:19.478096 ==
6812 10:07:19.478466 DQS Delay:
6813 10:07:19.480363 DQS0 = 52, DQS1 = 68
6814 10:07:19.480921 DQM Delay:
6815 10:07:19.481300 DQM0 = 9, DQM1 = 14
6816 10:07:19.483468 DQ Delay:
6817 10:07:19.487034 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6818 10:07:19.487590 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6819 10:07:19.490633 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6820 10:07:19.493965 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6821 10:07:19.494535
6822 10:07:19.496826
6823 10:07:19.503167 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b6d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6824 10:07:19.506864 CH1 RK0: MR19=C0C, MR18=5B6D
6825 10:07:19.513230 CH1_RK0: MR19=0xC0C, MR18=0x5B6D, DQSOSC=396, MR23=63, INC=376, DEC=251
6826 10:07:19.513776 ==
6827 10:07:19.516707 Dram Type= 6, Freq= 0, CH_1, rank 1
6828 10:07:19.520034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 10:07:19.520522 ==
6830 10:07:19.522910 [Gating] SW mode calibration
6831 10:07:19.529761 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6832 10:07:19.536073 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6833 10:07:19.539920 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6834 10:07:19.542795 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6835 10:07:19.549526 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6836 10:07:19.553183 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6837 10:07:19.556614 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 10:07:19.563220 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 10:07:19.565999 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 10:07:19.569513 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 10:07:19.575741 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6842 10:07:19.576300 Total UI for P1: 0, mck2ui 16
6843 10:07:19.582684 best dqsien dly found for B0: ( 0, 14, 24)
6844 10:07:19.583277 Total UI for P1: 0, mck2ui 16
6845 10:07:19.588978 best dqsien dly found for B1: ( 0, 14, 24)
6846 10:07:19.592389 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6847 10:07:19.595308 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6848 10:07:19.595774
6849 10:07:19.599238 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6850 10:07:19.602401 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6851 10:07:19.605474 [Gating] SW calibration Done
6852 10:07:19.606029 ==
6853 10:07:19.608706 Dram Type= 6, Freq= 0, CH_1, rank 1
6854 10:07:19.611922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 10:07:19.612488 ==
6856 10:07:19.615051 RX Vref Scan: 0
6857 10:07:19.615547
6858 10:07:19.618555 RX Vref 0 -> 0, step: 1
6859 10:07:19.619188
6860 10:07:19.619564 RX Delay -410 -> 252, step: 16
6861 10:07:19.624995 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6862 10:07:19.628208 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6863 10:07:19.631746 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6864 10:07:19.638078 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6865 10:07:19.641721 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6866 10:07:19.645251 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6867 10:07:19.648299 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6868 10:07:19.655152 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6869 10:07:19.658265 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6870 10:07:19.661547 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6871 10:07:19.664675 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6872 10:07:19.671747 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6873 10:07:19.675035 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6874 10:07:19.678391 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6875 10:07:19.681647 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6876 10:07:19.688044 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6877 10:07:19.688629 ==
6878 10:07:19.691648 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 10:07:19.694954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 10:07:19.695529 ==
6881 10:07:19.696018 DQS Delay:
6882 10:07:19.698261 DQS0 = 59, DQS1 = 59
6883 10:07:19.698875 DQM Delay:
6884 10:07:19.701292 DQM0 = 19, DQM1 = 12
6885 10:07:19.701769 DQ Delay:
6886 10:07:19.704391 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6887 10:07:19.707902 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6888 10:07:19.711324 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6889 10:07:19.714390 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6890 10:07:19.715012
6891 10:07:19.715503
6892 10:07:19.715955 ==
6893 10:07:19.717469 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 10:07:19.721141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 10:07:19.724516 ==
6896 10:07:19.725095
6897 10:07:19.725583
6898 10:07:19.726035 TX Vref Scan disable
6899 10:07:19.727821 == TX Byte 0 ==
6900 10:07:19.730795 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6901 10:07:19.734702 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6902 10:07:19.737835 == TX Byte 1 ==
6903 10:07:19.740818 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6904 10:07:19.744463 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6905 10:07:19.745046 ==
6906 10:07:19.747672 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 10:07:19.751165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 10:07:19.754253 ==
6909 10:07:19.754885
6910 10:07:19.755384
6911 10:07:19.755843 TX Vref Scan disable
6912 10:07:19.757778 == TX Byte 0 ==
6913 10:07:19.761124 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6914 10:07:19.764045 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6915 10:07:19.767567 == TX Byte 1 ==
6916 10:07:19.770750 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6917 10:07:19.774025 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6918 10:07:19.774608
6919 10:07:19.777502 [DATLAT]
6920 10:07:19.778083 Freq=400, CH1 RK1
6921 10:07:19.778574
6922 10:07:19.780758 DATLAT Default: 0xe
6923 10:07:19.781235 0, 0xFFFF, sum = 0
6924 10:07:19.783580 1, 0xFFFF, sum = 0
6925 10:07:19.784064 2, 0xFFFF, sum = 0
6926 10:07:19.787047 3, 0xFFFF, sum = 0
6927 10:07:19.787644 4, 0xFFFF, sum = 0
6928 10:07:19.789952 5, 0xFFFF, sum = 0
6929 10:07:19.790439 6, 0xFFFF, sum = 0
6930 10:07:19.793758 7, 0xFFFF, sum = 0
6931 10:07:19.794350 8, 0xFFFF, sum = 0
6932 10:07:19.797069 9, 0xFFFF, sum = 0
6933 10:07:19.797657 10, 0xFFFF, sum = 0
6934 10:07:19.800041 11, 0xFFFF, sum = 0
6935 10:07:19.803244 12, 0xFFFF, sum = 0
6936 10:07:19.803804 13, 0x0, sum = 1
6937 10:07:19.806795 14, 0x0, sum = 2
6938 10:07:19.807344 15, 0x0, sum = 3
6939 10:07:19.807723 16, 0x0, sum = 4
6940 10:07:19.810177 best_step = 14
6941 10:07:19.810755
6942 10:07:19.811193 ==
6943 10:07:19.812948 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 10:07:19.816238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 10:07:19.816705 ==
6946 10:07:19.819652 RX Vref Scan: 0
6947 10:07:19.820170
6948 10:07:19.820576 RX Vref 0 -> 0, step: 1
6949 10:07:19.822963
6950 10:07:19.823420 RX Delay -359 -> 252, step: 8
6951 10:07:19.831944 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6952 10:07:19.834702 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6953 10:07:19.838363 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6954 10:07:19.844720 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6955 10:07:19.848096 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6956 10:07:19.851107 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6957 10:07:19.854598 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6958 10:07:19.861266 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6959 10:07:19.864369 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6960 10:07:19.867615 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6961 10:07:19.871379 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6962 10:07:19.877743 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6963 10:07:19.881096 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6964 10:07:19.884307 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6965 10:07:19.887578 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6966 10:07:19.894390 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6967 10:07:19.894806 ==
6968 10:07:19.897541 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 10:07:19.900713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 10:07:19.901132 ==
6971 10:07:19.901510 DQS Delay:
6972 10:07:19.903955 DQS0 = 60, DQS1 = 64
6973 10:07:19.904391 DQM Delay:
6974 10:07:19.907207 DQM0 = 13, DQM1 = 10
6975 10:07:19.907622 DQ Delay:
6976 10:07:19.910559 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6977 10:07:19.914358 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6978 10:07:19.917464 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6979 10:07:19.920510 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6980 10:07:19.920929
6981 10:07:19.921262
6982 10:07:19.930511 [DQSOSCAuto] RK1, (LSB)MR18= 0x7aab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6983 10:07:19.931101 CH1 RK1: MR19=C0C, MR18=7AAB
6984 10:07:19.937249 CH1_RK1: MR19=0xC0C, MR18=0x7AAB, DQSOSC=388, MR23=63, INC=392, DEC=261
6985 10:07:19.940714 [RxdqsGatingPostProcess] freq 400
6986 10:07:19.947051 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6987 10:07:19.950073 best DQS0 dly(2T, 0.5T) = (0, 10)
6988 10:07:19.953363 best DQS1 dly(2T, 0.5T) = (0, 10)
6989 10:07:19.956526 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6990 10:07:19.959986 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6991 10:07:19.963388 best DQS0 dly(2T, 0.5T) = (0, 10)
6992 10:07:19.966812 best DQS1 dly(2T, 0.5T) = (0, 10)
6993 10:07:19.969875 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6994 10:07:19.973344 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6995 10:07:19.973763 Pre-setting of DQS Precalculation
6996 10:07:19.979849 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6997 10:07:19.986321 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6998 10:07:19.992605 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6999 10:07:19.992903
7000 10:07:19.993136
7001 10:07:19.996265 [Calibration Summary] 800 Mbps
7002 10:07:19.999476 CH 0, Rank 0
7003 10:07:19.999655 SW Impedance : PASS
7004 10:07:20.002654 DUTY Scan : NO K
7005 10:07:20.005768 ZQ Calibration : PASS
7006 10:07:20.005923 Jitter Meter : NO K
7007 10:07:20.008910 CBT Training : PASS
7008 10:07:20.012150 Write leveling : PASS
7009 10:07:20.012279 RX DQS gating : PASS
7010 10:07:20.016080 RX DQ/DQS(RDDQC) : PASS
7011 10:07:20.019183 TX DQ/DQS : PASS
7012 10:07:20.019297 RX DATLAT : PASS
7013 10:07:20.022422 RX DQ/DQS(Engine): PASS
7014 10:07:20.025447 TX OE : NO K
7015 10:07:20.025593 All Pass.
7016 10:07:20.025665
7017 10:07:20.025733 CH 0, Rank 1
7018 10:07:20.028981 SW Impedance : PASS
7019 10:07:20.032010 DUTY Scan : NO K
7020 10:07:20.032102 ZQ Calibration : PASS
7021 10:07:20.035384 Jitter Meter : NO K
7022 10:07:20.038768 CBT Training : PASS
7023 10:07:20.038868 Write leveling : NO K
7024 10:07:20.041976 RX DQS gating : PASS
7025 10:07:20.042067 RX DQ/DQS(RDDQC) : PASS
7026 10:07:20.045243 TX DQ/DQS : PASS
7027 10:07:20.048752 RX DATLAT : PASS
7028 10:07:20.048924 RX DQ/DQS(Engine): PASS
7029 10:07:20.052034 TX OE : NO K
7030 10:07:20.052167 All Pass.
7031 10:07:20.052254
7032 10:07:20.055014 CH 1, Rank 0
7033 10:07:20.055167 SW Impedance : PASS
7034 10:07:20.058495 DUTY Scan : NO K
7035 10:07:20.062092 ZQ Calibration : PASS
7036 10:07:20.062295 Jitter Meter : NO K
7037 10:07:20.065064 CBT Training : PASS
7038 10:07:20.068520 Write leveling : PASS
7039 10:07:20.068694 RX DQS gating : PASS
7040 10:07:20.071588 RX DQ/DQS(RDDQC) : PASS
7041 10:07:20.075165 TX DQ/DQS : PASS
7042 10:07:20.075397 RX DATLAT : PASS
7043 10:07:20.078449 RX DQ/DQS(Engine): PASS
7044 10:07:20.081439 TX OE : NO K
7045 10:07:20.081689 All Pass.
7046 10:07:20.081833
7047 10:07:20.081964 CH 1, Rank 1
7048 10:07:20.085322 SW Impedance : PASS
7049 10:07:20.088455 DUTY Scan : NO K
7050 10:07:20.088730 ZQ Calibration : PASS
7051 10:07:20.091481 Jitter Meter : NO K
7052 10:07:20.095096 CBT Training : PASS
7053 10:07:20.095379 Write leveling : NO K
7054 10:07:20.098139 RX DQS gating : PASS
7055 10:07:20.101845 RX DQ/DQS(RDDQC) : PASS
7056 10:07:20.102200 TX DQ/DQS : PASS
7057 10:07:20.105175 RX DATLAT : PASS
7058 10:07:20.108471 RX DQ/DQS(Engine): PASS
7059 10:07:20.109037 TX OE : NO K
7060 10:07:20.111425 All Pass.
7061 10:07:20.111883
7062 10:07:20.112244 DramC Write-DBI off
7063 10:07:20.114804 PER_BANK_REFRESH: Hybrid Mode
7064 10:07:20.115414 TX_TRACKING: ON
7065 10:07:20.125342 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7066 10:07:20.127883 [FAST_K] Save calibration result to emmc
7067 10:07:20.130979 dramc_set_vcore_voltage set vcore to 725000
7068 10:07:20.134380 Read voltage for 1600, 0
7069 10:07:20.134880 Vio18 = 0
7070 10:07:20.137761 Vcore = 725000
7071 10:07:20.138223 Vdram = 0
7072 10:07:20.138584 Vddq = 0
7073 10:07:20.141426 Vmddr = 0
7074 10:07:20.144554 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7075 10:07:20.151192 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7076 10:07:20.151751 MEM_TYPE=3, freq_sel=13
7077 10:07:20.154331 sv_algorithm_assistance_LP4_3733
7078 10:07:20.160621 ============ PULL DRAM RESETB DOWN ============
7079 10:07:20.164104 ========== PULL DRAM RESETB DOWN end =========
7080 10:07:20.167068 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7081 10:07:20.170315 ===================================
7082 10:07:20.173768 LPDDR4 DRAM CONFIGURATION
7083 10:07:20.177503 ===================================
7084 10:07:20.180662 EX_ROW_EN[0] = 0x0
7085 10:07:20.181333 EX_ROW_EN[1] = 0x0
7086 10:07:20.183993 LP4Y_EN = 0x0
7087 10:07:20.184550 WORK_FSP = 0x1
7088 10:07:20.187517 WL = 0x5
7089 10:07:20.188076 RL = 0x5
7090 10:07:20.190449 BL = 0x2
7091 10:07:20.191059 RPST = 0x0
7092 10:07:20.193408 RD_PRE = 0x0
7093 10:07:20.193862 WR_PRE = 0x1
7094 10:07:20.197277 WR_PST = 0x1
7095 10:07:20.197733 DBI_WR = 0x0
7096 10:07:20.200431 DBI_RD = 0x0
7097 10:07:20.200885 OTF = 0x1
7098 10:07:20.203451 ===================================
7099 10:07:20.206876 ===================================
7100 10:07:20.210116 ANA top config
7101 10:07:20.213558 ===================================
7102 10:07:20.216805 DLL_ASYNC_EN = 0
7103 10:07:20.217374 ALL_SLAVE_EN = 0
7104 10:07:20.219960 NEW_RANK_MODE = 1
7105 10:07:20.223406 DLL_IDLE_MODE = 1
7106 10:07:20.226725 LP45_APHY_COMB_EN = 1
7107 10:07:20.229657 TX_ODT_DIS = 0
7108 10:07:20.230139 NEW_8X_MODE = 1
7109 10:07:20.233002 ===================================
7110 10:07:20.236903 ===================================
7111 10:07:20.240126 data_rate = 3200
7112 10:07:20.243024 CKR = 1
7113 10:07:20.246586 DQ_P2S_RATIO = 8
7114 10:07:20.250114 ===================================
7115 10:07:20.252912 CA_P2S_RATIO = 8
7116 10:07:20.256218 DQ_CA_OPEN = 0
7117 10:07:20.256679 DQ_SEMI_OPEN = 0
7118 10:07:20.259749 CA_SEMI_OPEN = 0
7119 10:07:20.262668 CA_FULL_RATE = 0
7120 10:07:20.266251 DQ_CKDIV4_EN = 0
7121 10:07:20.269634 CA_CKDIV4_EN = 0
7122 10:07:20.272889 CA_PREDIV_EN = 0
7123 10:07:20.273441 PH8_DLY = 12
7124 10:07:20.276472 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7125 10:07:20.279517 DQ_AAMCK_DIV = 4
7126 10:07:20.282869 CA_AAMCK_DIV = 4
7127 10:07:20.286008 CA_ADMCK_DIV = 4
7128 10:07:20.289474 DQ_TRACK_CA_EN = 0
7129 10:07:20.292694 CA_PICK = 1600
7130 10:07:20.293256 CA_MCKIO = 1600
7131 10:07:20.295805 MCKIO_SEMI = 0
7132 10:07:20.299262 PLL_FREQ = 3068
7133 10:07:20.302154 DQ_UI_PI_RATIO = 32
7134 10:07:20.305657 CA_UI_PI_RATIO = 0
7135 10:07:20.309345 ===================================
7136 10:07:20.312276 ===================================
7137 10:07:20.315496 memory_type:LPDDR4
7138 10:07:20.316066 GP_NUM : 10
7139 10:07:20.319455 SRAM_EN : 1
7140 10:07:20.322085 MD32_EN : 0
7141 10:07:20.325462 ===================================
7142 10:07:20.326023 [ANA_INIT] >>>>>>>>>>>>>>
7143 10:07:20.329029 <<<<<< [CONFIGURE PHASE]: ANA_TX
7144 10:07:20.332226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7145 10:07:20.335745 ===================================
7146 10:07:20.338798 data_rate = 3200,PCW = 0X7600
7147 10:07:20.342103 ===================================
7148 10:07:20.345521 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7149 10:07:20.351530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7150 10:07:20.354969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7151 10:07:20.361783 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7152 10:07:20.364915 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7153 10:07:20.368435 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7154 10:07:20.368903 [ANA_INIT] flow start
7155 10:07:20.371370 [ANA_INIT] PLL >>>>>>>>
7156 10:07:20.374910 [ANA_INIT] PLL <<<<<<<<
7157 10:07:20.378274 [ANA_INIT] MIDPI >>>>>>>>
7158 10:07:20.378886 [ANA_INIT] MIDPI <<<<<<<<
7159 10:07:20.381649 [ANA_INIT] DLL >>>>>>>>
7160 10:07:20.384809 [ANA_INIT] DLL <<<<<<<<
7161 10:07:20.385272 [ANA_INIT] flow end
7162 10:07:20.391194 ============ LP4 DIFF to SE enter ============
7163 10:07:20.394916 ============ LP4 DIFF to SE exit ============
7164 10:07:20.395489 [ANA_INIT] <<<<<<<<<<<<<
7165 10:07:20.398132 [Flow] Enable top DCM control >>>>>
7166 10:07:20.400868 [Flow] Enable top DCM control <<<<<
7167 10:07:20.404642 Enable DLL master slave shuffle
7168 10:07:20.411172 ==============================================================
7169 10:07:20.414592 Gating Mode config
7170 10:07:20.417609 ==============================================================
7171 10:07:20.421442 Config description:
7172 10:07:20.430923 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7173 10:07:20.437471 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7174 10:07:20.440721 SELPH_MODE 0: By rank 1: By Phase
7175 10:07:20.447202 ==============================================================
7176 10:07:20.450905 GAT_TRACK_EN = 1
7177 10:07:20.453896 RX_GATING_MODE = 2
7178 10:07:20.457122 RX_GATING_TRACK_MODE = 2
7179 10:07:20.460142 SELPH_MODE = 1
7180 10:07:20.463605 PICG_EARLY_EN = 1
7181 10:07:20.464166 VALID_LAT_VALUE = 1
7182 10:07:20.470265 ==============================================================
7183 10:07:20.473785 Enter into Gating configuration >>>>
7184 10:07:20.477368 Exit from Gating configuration <<<<
7185 10:07:20.479965 Enter into DVFS_PRE_config >>>>>
7186 10:07:20.490103 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7187 10:07:20.493177 Exit from DVFS_PRE_config <<<<<
7188 10:07:20.496403 Enter into PICG configuration >>>>
7189 10:07:20.499740 Exit from PICG configuration <<<<
7190 10:07:20.503285 [RX_INPUT] configuration >>>>>
7191 10:07:20.506637 [RX_INPUT] configuration <<<<<
7192 10:07:20.512785 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7193 10:07:20.516192 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7194 10:07:20.522587 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7195 10:07:20.529309 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7196 10:07:20.535523 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7197 10:07:20.542777 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7198 10:07:20.546046 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7199 10:07:20.549154 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7200 10:07:20.552315 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7201 10:07:20.559263 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7202 10:07:20.561904 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7203 10:07:20.565403 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7204 10:07:20.568784 ===================================
7205 10:07:20.572341 LPDDR4 DRAM CONFIGURATION
7206 10:07:20.575593 ===================================
7207 10:07:20.578645 EX_ROW_EN[0] = 0x0
7208 10:07:20.579247 EX_ROW_EN[1] = 0x0
7209 10:07:20.582056 LP4Y_EN = 0x0
7210 10:07:20.582633 WORK_FSP = 0x1
7211 10:07:20.585844 WL = 0x5
7212 10:07:20.586399 RL = 0x5
7213 10:07:20.589110 BL = 0x2
7214 10:07:20.589671 RPST = 0x0
7215 10:07:20.591790 RD_PRE = 0x0
7216 10:07:20.592253 WR_PRE = 0x1
7217 10:07:20.595212 WR_PST = 0x1
7218 10:07:20.595674 DBI_WR = 0x0
7219 10:07:20.598207 DBI_RD = 0x0
7220 10:07:20.601760 OTF = 0x1
7221 10:07:20.602230 ===================================
7222 10:07:20.608122 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7223 10:07:20.611709 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7224 10:07:20.615143 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7225 10:07:20.618214 ===================================
7226 10:07:20.621470 LPDDR4 DRAM CONFIGURATION
7227 10:07:20.625101 ===================================
7228 10:07:20.628291 EX_ROW_EN[0] = 0x10
7229 10:07:20.628851 EX_ROW_EN[1] = 0x0
7230 10:07:20.631242 LP4Y_EN = 0x0
7231 10:07:20.631708 WORK_FSP = 0x1
7232 10:07:20.634664 WL = 0x5
7233 10:07:20.635219 RL = 0x5
7234 10:07:20.637851 BL = 0x2
7235 10:07:20.638313 RPST = 0x0
7236 10:07:20.641261 RD_PRE = 0x0
7237 10:07:20.641823 WR_PRE = 0x1
7238 10:07:20.644498 WR_PST = 0x1
7239 10:07:20.647454 DBI_WR = 0x0
7240 10:07:20.647965 DBI_RD = 0x0
7241 10:07:20.651414 OTF = 0x1
7242 10:07:20.654965 ===================================
7243 10:07:20.657802 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7244 10:07:20.661112 ==
7245 10:07:20.661675 Dram Type= 6, Freq= 0, CH_0, rank 0
7246 10:07:20.667803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7247 10:07:20.668365 ==
7248 10:07:20.670724 [Duty_Offset_Calibration]
7249 10:07:20.671221 B0:2 B1:0 CA:3
7250 10:07:20.671591
7251 10:07:20.673798 [DutyScan_Calibration_Flow] k_type=0
7252 10:07:20.684580
7253 10:07:20.685136 ==CLK 0==
7254 10:07:20.687212 Final CLK duty delay cell = 0
7255 10:07:20.690598 [0] MAX Duty = 5031%(X100), DQS PI = 12
7256 10:07:20.694116 [0] MIN Duty = 4907%(X100), DQS PI = 2
7257 10:07:20.694582 [0] AVG Duty = 4969%(X100)
7258 10:07:20.697441
7259 10:07:20.700584 CH0 CLK Duty spec in!! Max-Min= 124%
7260 10:07:20.703770 [DutyScan_Calibration_Flow] ====Done====
7261 10:07:20.704239
7262 10:07:20.706757 [DutyScan_Calibration_Flow] k_type=1
7263 10:07:20.723957
7264 10:07:20.724511 ==DQS 0 ==
7265 10:07:20.726997 Final DQS duty delay cell = 0
7266 10:07:20.730557 [0] MAX Duty = 5094%(X100), DQS PI = 14
7267 10:07:20.733644 [0] MIN Duty = 4875%(X100), DQS PI = 50
7268 10:07:20.737647 [0] AVG Duty = 4984%(X100)
7269 10:07:20.738221
7270 10:07:20.738595 ==DQS 1 ==
7271 10:07:20.740237 Final DQS duty delay cell = 0
7272 10:07:20.743515 [0] MAX Duty = 5156%(X100), DQS PI = 32
7273 10:07:20.746926 [0] MIN Duty = 5062%(X100), DQS PI = 0
7274 10:07:20.750050 [0] AVG Duty = 5109%(X100)
7275 10:07:20.750603
7276 10:07:20.753810 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7277 10:07:20.754359
7278 10:07:20.757153 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7279 10:07:20.760269 [DutyScan_Calibration_Flow] ====Done====
7280 10:07:20.760822
7281 10:07:20.763537 [DutyScan_Calibration_Flow] k_type=3
7282 10:07:20.782057
7283 10:07:20.782616 ==DQM 0 ==
7284 10:07:20.784744 Final DQM duty delay cell = 0
7285 10:07:20.788422 [0] MAX Duty = 5156%(X100), DQS PI = 30
7286 10:07:20.791688 [0] MIN Duty = 4844%(X100), DQS PI = 50
7287 10:07:20.794629 [0] AVG Duty = 5000%(X100)
7288 10:07:20.795221
7289 10:07:20.795596 ==DQM 1 ==
7290 10:07:20.797983 Final DQM duty delay cell = 4
7291 10:07:20.801389 [4] MAX Duty = 5187%(X100), DQS PI = 60
7292 10:07:20.804917 [4] MIN Duty = 5031%(X100), DQS PI = 14
7293 10:07:20.807772 [4] AVG Duty = 5109%(X100)
7294 10:07:20.808224
7295 10:07:20.811186 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7296 10:07:20.811636
7297 10:07:20.814728 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7298 10:07:20.817754 [DutyScan_Calibration_Flow] ====Done====
7299 10:07:20.818208
7300 10:07:20.821239 [DutyScan_Calibration_Flow] k_type=2
7301 10:07:20.838133
7302 10:07:20.838672 ==DQ 0 ==
7303 10:07:20.841215 Final DQ duty delay cell = -4
7304 10:07:20.845452 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7305 10:07:20.848166 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7306 10:07:20.851395 [-4] AVG Duty = 4938%(X100)
7307 10:07:20.851848
7308 10:07:20.852209 ==DQ 1 ==
7309 10:07:20.855180 Final DQ duty delay cell = 0
7310 10:07:20.858472 [0] MAX Duty = 5156%(X100), DQS PI = 58
7311 10:07:20.861610 [0] MIN Duty = 5000%(X100), DQS PI = 14
7312 10:07:20.864722 [0] AVG Duty = 5078%(X100)
7313 10:07:20.865268
7314 10:07:20.867872 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7315 10:07:20.868420
7316 10:07:20.870922 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7317 10:07:20.874373 [DutyScan_Calibration_Flow] ====Done====
7318 10:07:20.874990 ==
7319 10:07:20.877926 Dram Type= 6, Freq= 0, CH_1, rank 0
7320 10:07:20.881117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7321 10:07:20.881663 ==
7322 10:07:20.884202 [Duty_Offset_Calibration]
7323 10:07:20.884756 B0:1 B1:-2 CA:0
7324 10:07:20.887846
7325 10:07:20.890632 [DutyScan_Calibration_Flow] k_type=0
7326 10:07:20.899005
7327 10:07:20.899557 ==CLK 0==
7328 10:07:20.901991 Final CLK duty delay cell = 0
7329 10:07:20.905584 [0] MAX Duty = 5031%(X100), DQS PI = 50
7330 10:07:20.908629 [0] MIN Duty = 4876%(X100), DQS PI = 26
7331 10:07:20.912046 [0] AVG Duty = 4953%(X100)
7332 10:07:20.912564
7333 10:07:20.915032 CH1 CLK Duty spec in!! Max-Min= 155%
7334 10:07:20.918740 [DutyScan_Calibration_Flow] ====Done====
7335 10:07:20.919240
7336 10:07:20.922138 [DutyScan_Calibration_Flow] k_type=1
7337 10:07:20.938272
7338 10:07:20.938817 ==DQS 0 ==
7339 10:07:20.941288 Final DQS duty delay cell = -4
7340 10:07:20.944404 [-4] MAX Duty = 4938%(X100), DQS PI = 56
7341 10:07:20.947831 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7342 10:07:20.950815 [-4] AVG Duty = 4891%(X100)
7343 10:07:20.951367
7344 10:07:20.951763 ==DQS 1 ==
7345 10:07:20.954782 Final DQS duty delay cell = 0
7346 10:07:20.957776 [0] MAX Duty = 5125%(X100), DQS PI = 30
7347 10:07:20.960758 [0] MIN Duty = 4844%(X100), DQS PI = 56
7348 10:07:20.964350 [0] AVG Duty = 4984%(X100)
7349 10:07:20.964892
7350 10:07:20.967478 CH1 DQS 0 Duty spec in!! Max-Min= 94%
7351 10:07:20.967926
7352 10:07:20.970764 CH1 DQS 1 Duty spec in!! Max-Min= 281%
7353 10:07:20.974125 [DutyScan_Calibration_Flow] ====Done====
7354 10:07:20.974667
7355 10:07:20.977414 [DutyScan_Calibration_Flow] k_type=3
7356 10:07:20.995208
7357 10:07:20.995754 ==DQM 0 ==
7358 10:07:20.998615 Final DQM duty delay cell = 0
7359 10:07:21.001607 [0] MAX Duty = 5031%(X100), DQS PI = 60
7360 10:07:21.005012 [0] MIN Duty = 4844%(X100), DQS PI = 22
7361 10:07:21.008531 [0] AVG Duty = 4937%(X100)
7362 10:07:21.008983
7363 10:07:21.009343 ==DQM 1 ==
7364 10:07:21.011498 Final DQM duty delay cell = 0
7365 10:07:21.014420 [0] MAX Duty = 5062%(X100), DQS PI = 4
7366 10:07:21.017879 [0] MIN Duty = 4844%(X100), DQS PI = 58
7367 10:07:21.021371 [0] AVG Duty = 4953%(X100)
7368 10:07:21.021913
7369 10:07:21.024880 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7370 10:07:21.025430
7371 10:07:21.028285 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7372 10:07:21.030957 [DutyScan_Calibration_Flow] ====Done====
7373 10:07:21.031511
7374 10:07:21.034222 [DutyScan_Calibration_Flow] k_type=2
7375 10:07:21.052276
7376 10:07:21.052832 ==DQ 0 ==
7377 10:07:21.055484 Final DQ duty delay cell = 0
7378 10:07:21.058912 [0] MAX Duty = 5062%(X100), DQS PI = 0
7379 10:07:21.062492 [0] MIN Duty = 4938%(X100), DQS PI = 14
7380 10:07:21.063106 [0] AVG Duty = 5000%(X100)
7381 10:07:21.065095
7382 10:07:21.065648 ==DQ 1 ==
7383 10:07:21.068610 Final DQ duty delay cell = 0
7384 10:07:21.071939 [0] MAX Duty = 5156%(X100), DQS PI = 24
7385 10:07:21.075242 [0] MIN Duty = 4938%(X100), DQS PI = 56
7386 10:07:21.075801 [0] AVG Duty = 5047%(X100)
7387 10:07:21.078353
7388 10:07:21.081550 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7389 10:07:21.082107
7390 10:07:21.084969 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7391 10:07:21.088287 [DutyScan_Calibration_Flow] ====Done====
7392 10:07:21.091404 nWR fixed to 30
7393 10:07:21.091867 [ModeRegInit_LP4] CH0 RK0
7394 10:07:21.095431 [ModeRegInit_LP4] CH0 RK1
7395 10:07:21.098167 [ModeRegInit_LP4] CH1 RK0
7396 10:07:21.101376 [ModeRegInit_LP4] CH1 RK1
7397 10:07:21.101931 match AC timing 5
7398 10:07:21.107944 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7399 10:07:21.111126 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7400 10:07:21.114770 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7401 10:07:21.121132 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7402 10:07:21.124272 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7403 10:07:21.124737 [MiockJmeterHQA]
7404 10:07:21.125101
7405 10:07:21.127379 [DramcMiockJmeter] u1RxGatingPI = 0
7406 10:07:21.130956 0 : 4258, 4029
7407 10:07:21.131655 4 : 4252, 4027
7408 10:07:21.134127 8 : 4252, 4027
7409 10:07:21.134631 12 : 4252, 4027
7410 10:07:21.137562 16 : 4253, 4027
7411 10:07:21.138030 20 : 4363, 4137
7412 10:07:21.138403 24 : 4253, 4027
7413 10:07:21.140657 28 : 4253, 4026
7414 10:07:21.141224 32 : 4252, 4027
7415 10:07:21.144116 36 : 4255, 4029
7416 10:07:21.144587 40 : 4250, 4026
7417 10:07:21.147327 44 : 4360, 4138
7418 10:07:21.147798 48 : 4360, 4137
7419 10:07:21.150798 52 : 4253, 4029
7420 10:07:21.151299 56 : 4250, 4027
7421 10:07:21.151670 60 : 4250, 4026
7422 10:07:21.153778 64 : 4252, 4027
7423 10:07:21.154243 68 : 4252, 4029
7424 10:07:21.157774 72 : 4361, 4137
7425 10:07:21.158337 76 : 4249, 4027
7426 10:07:21.160948 80 : 4250, 4026
7427 10:07:21.161509 84 : 4250, 4027
7428 10:07:21.163809 88 : 4252, 4029
7429 10:07:21.164279 92 : 4250, 4027
7430 10:07:21.164652 96 : 4360, 4138
7431 10:07:21.167518 100 : 4360, 4137
7432 10:07:21.167986 104 : 4250, 3730
7433 10:07:21.170458 108 : 4250, 4
7434 10:07:21.170957 112 : 4250, 0
7435 10:07:21.173466 116 : 4252, 0
7436 10:07:21.173933 120 : 4250, 0
7437 10:07:21.174303 124 : 4250, 0
7438 10:07:21.177641 128 : 4252, 0
7439 10:07:21.178209 132 : 4360, 0
7440 10:07:21.180237 136 : 4361, 0
7441 10:07:21.180706 140 : 4363, 0
7442 10:07:21.181080 144 : 4250, 0
7443 10:07:21.183378 148 : 4360, 0
7444 10:07:21.183911 152 : 4250, 0
7445 10:07:21.184298 156 : 4249, 0
7446 10:07:21.187390 160 : 4250, 0
7447 10:07:21.187956 164 : 4250, 0
7448 10:07:21.190534 168 : 4252, 0
7449 10:07:21.191148 172 : 4250, 0
7450 10:07:21.191528 176 : 4250, 0
7451 10:07:21.193390 180 : 4252, 0
7452 10:07:21.193860 184 : 4360, 0
7453 10:07:21.197204 188 : 4361, 0
7454 10:07:21.197739 192 : 4363, 0
7455 10:07:21.198120 196 : 4251, 0
7456 10:07:21.200225 200 : 4250, 0
7457 10:07:21.200788 204 : 4250, 0
7458 10:07:21.203404 208 : 4250, 0
7459 10:07:21.203877 212 : 4250, 0
7460 10:07:21.204248 216 : 4250, 0
7461 10:07:21.206898 220 : 4252, 0
7462 10:07:21.207370 224 : 4250, 0
7463 10:07:21.210145 228 : 4250, 0
7464 10:07:21.210613 232 : 4252, 0
7465 10:07:21.211020 236 : 4250, 1098
7466 10:07:21.213350 240 : 4250, 4027
7467 10:07:21.213828 244 : 4360, 4137
7468 10:07:21.216840 248 : 4361, 4137
7469 10:07:21.217402 252 : 4250, 4027
7470 10:07:21.219992 256 : 4250, 4027
7471 10:07:21.220566 260 : 4363, 4140
7472 10:07:21.223220 264 : 4250, 4026
7473 10:07:21.223690 268 : 4250, 4027
7474 10:07:21.226622 272 : 4253, 4027
7475 10:07:21.227222 276 : 4252, 4029
7476 10:07:21.229850 280 : 4250, 4026
7477 10:07:21.230414 284 : 4250, 4027
7478 10:07:21.232965 288 : 4360, 4138
7479 10:07:21.233440 292 : 4250, 4027
7480 10:07:21.233816 296 : 4250, 4026
7481 10:07:21.236552 300 : 4361, 4137
7482 10:07:21.237021 304 : 4250, 4027
7483 10:07:21.239671 308 : 4250, 4027
7484 10:07:21.240139 312 : 4363, 4140
7485 10:07:21.243123 316 : 4250, 4026
7486 10:07:21.243592 320 : 4250, 4027
7487 10:07:21.246142 324 : 4249, 4027
7488 10:07:21.246612 328 : 4252, 4029
7489 10:07:21.249558 332 : 4250, 4026
7490 10:07:21.250023 336 : 4250, 4027
7491 10:07:21.252972 340 : 4360, 4138
7492 10:07:21.253441 344 : 4250, 4027
7493 10:07:21.255939 348 : 4250, 4026
7494 10:07:21.256652 352 : 4361, 4126
7495 10:07:21.259062 356 : 4252, 2827
7496 10:07:21.259391 360 : 4249, 0
7497 10:07:21.259652
7498 10:07:21.262643 MIOCK jitter meter ch=0
7499 10:07:21.262992
7500 10:07:21.266161 1T = (360-108) = 252 dly cells
7501 10:07:21.269316 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7502 10:07:21.269506 ==
7503 10:07:21.272329 Dram Type= 6, Freq= 0, CH_0, rank 0
7504 10:07:21.278678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7505 10:07:21.278886 ==
7506 10:07:21.281822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7507 10:07:21.288674 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7508 10:07:21.291744 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7509 10:07:21.298546 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7510 10:07:21.306256 [CA 0] Center 43 (13~74) winsize 62
7511 10:07:21.309513 [CA 1] Center 43 (13~74) winsize 62
7512 10:07:21.313144 [CA 2] Center 39 (10~68) winsize 59
7513 10:07:21.316251 [CA 3] Center 39 (10~68) winsize 59
7514 10:07:21.319418 [CA 4] Center 36 (7~66) winsize 60
7515 10:07:21.323258 [CA 5] Center 36 (7~66) winsize 60
7516 10:07:21.323343
7517 10:07:21.326023 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7518 10:07:21.326105
7519 10:07:21.332821 [CATrainingPosCal] consider 1 rank data
7520 10:07:21.332908 u2DelayCellTimex100 = 258/100 ps
7521 10:07:21.339248 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7522 10:07:21.342644 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7523 10:07:21.346042 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7524 10:07:21.349363 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7525 10:07:21.352319 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7526 10:07:21.355732 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7527 10:07:21.355816
7528 10:07:21.359216 CA PerBit enable=1, Macro0, CA PI delay=36
7529 10:07:21.362716
7530 10:07:21.362797 [CBTSetCACLKResult] CA Dly = 36
7531 10:07:21.365474 CS Dly: 11 (0~42)
7532 10:07:21.368629 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7533 10:07:21.372313 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7534 10:07:21.375304 ==
7535 10:07:21.378661 Dram Type= 6, Freq= 0, CH_0, rank 1
7536 10:07:21.382086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 10:07:21.382167 ==
7538 10:07:21.385600 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7539 10:07:21.391877 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7540 10:07:21.395494 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7541 10:07:21.401751 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7542 10:07:21.410635 [CA 0] Center 44 (14~75) winsize 62
7543 10:07:21.413981 [CA 1] Center 43 (13~74) winsize 62
7544 10:07:21.417040 [CA 2] Center 39 (10~69) winsize 60
7545 10:07:21.420015 [CA 3] Center 39 (10~68) winsize 59
7546 10:07:21.423422 [CA 4] Center 37 (8~67) winsize 60
7547 10:07:21.427010 [CA 5] Center 36 (7~66) winsize 60
7548 10:07:21.427092
7549 10:07:21.430322 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7550 10:07:21.430403
7551 10:07:21.436427 [CATrainingPosCal] consider 2 rank data
7552 10:07:21.436513 u2DelayCellTimex100 = 258/100 ps
7553 10:07:21.443201 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7554 10:07:21.446541 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7555 10:07:21.450009 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7556 10:07:21.452957 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7557 10:07:21.456362 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7558 10:07:21.459790 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7559 10:07:21.459873
7560 10:07:21.462926 CA PerBit enable=1, Macro0, CA PI delay=36
7561 10:07:21.466449
7562 10:07:21.466534 [CBTSetCACLKResult] CA Dly = 36
7563 10:07:21.469600 CS Dly: 11 (0~43)
7564 10:07:21.472832 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7565 10:07:21.475906 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7566 10:07:21.479576
7567 10:07:21.482723 ----->DramcWriteLeveling(PI) begin...
7568 10:07:21.482842 ==
7569 10:07:21.485846 Dram Type= 6, Freq= 0, CH_0, rank 0
7570 10:07:21.489451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7571 10:07:21.489535 ==
7572 10:07:21.493114 Write leveling (Byte 0): 35 => 35
7573 10:07:21.495653 Write leveling (Byte 1): 30 => 30
7574 10:07:21.499283 DramcWriteLeveling(PI) end<-----
7575 10:07:21.499365
7576 10:07:21.499430 ==
7577 10:07:21.502407 Dram Type= 6, Freq= 0, CH_0, rank 0
7578 10:07:21.505504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 10:07:21.505588 ==
7580 10:07:21.509150 [Gating] SW mode calibration
7581 10:07:21.515411 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7582 10:07:21.522229 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7583 10:07:21.525196 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 10:07:21.528839 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 10:07:21.535063 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 10:07:21.538346 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 10:07:21.541605 1 4 16 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
7588 10:07:21.548350 1 4 20 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
7589 10:07:21.551357 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 10:07:21.554754 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 10:07:21.561599 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 10:07:21.564468 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 10:07:21.567913 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 10:07:21.574544 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7595 10:07:21.577892 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
7596 10:07:21.581532 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7597 10:07:21.587450 1 5 24 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
7598 10:07:21.590836 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 10:07:21.594113 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 10:07:21.601286 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 10:07:21.604293 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 10:07:21.607384 1 6 12 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
7603 10:07:21.614148 1 6 16 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7604 10:07:21.617622 1 6 20 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7605 10:07:21.620613 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7606 10:07:21.627269 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 10:07:21.630689 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 10:07:21.634088 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 10:07:21.640422 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 10:07:21.643823 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 10:07:21.647186 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7612 10:07:21.653952 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7613 10:07:21.656953 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7614 10:07:21.660620 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 10:07:21.666984 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 10:07:21.670205 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 10:07:21.673585 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 10:07:21.679702 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 10:07:21.683199 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 10:07:21.689824 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 10:07:21.692952 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 10:07:21.696465 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 10:07:21.702730 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 10:07:21.706361 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 10:07:21.709595 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 10:07:21.716405 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7627 10:07:21.719527 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7628 10:07:21.722536 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7629 10:07:21.726190 Total UI for P1: 0, mck2ui 16
7630 10:07:21.729249 best dqsien dly found for B0: ( 1, 9, 14)
7631 10:07:21.732411 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7632 10:07:21.739210 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 10:07:21.742646 Total UI for P1: 0, mck2ui 16
7634 10:07:21.745943 best dqsien dly found for B1: ( 1, 9, 24)
7635 10:07:21.749146 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7636 10:07:21.752177 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7637 10:07:21.752258
7638 10:07:21.755437 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7639 10:07:21.758796 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7640 10:07:21.761892 [Gating] SW calibration Done
7641 10:07:21.761973 ==
7642 10:07:21.765379 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 10:07:21.768521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 10:07:21.772537 ==
7645 10:07:21.772619 RX Vref Scan: 0
7646 10:07:21.772685
7647 10:07:21.775390 RX Vref 0 -> 0, step: 1
7648 10:07:21.775504
7649 10:07:21.778635 RX Delay 0 -> 252, step: 8
7650 10:07:21.781955 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7651 10:07:21.785377 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7652 10:07:21.788494 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7653 10:07:21.791697 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7654 10:07:21.798703 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7655 10:07:21.801849 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7656 10:07:21.805457 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7657 10:07:21.808582 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7658 10:07:21.811569 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7659 10:07:21.818407 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7660 10:07:21.822007 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7661 10:07:21.824978 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7662 10:07:21.828208 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7663 10:07:21.831854 iDelay=192, Bit 13, Center 127 (72 ~ 183) 112
7664 10:07:21.838322 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7665 10:07:21.841450 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7666 10:07:21.841608 ==
7667 10:07:21.844743 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 10:07:21.848052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 10:07:21.848211 ==
7670 10:07:21.851650 DQS Delay:
7671 10:07:21.851814 DQS0 = 0, DQS1 = 0
7672 10:07:21.851895 DQM Delay:
7673 10:07:21.855072 DQM0 = 127, DQM1 = 123
7674 10:07:21.855245 DQ Delay:
7675 10:07:21.857928 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7676 10:07:21.861421 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7677 10:07:21.867498 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7678 10:07:21.870810 DQ12 =127, DQ13 =127, DQ14 =135, DQ15 =135
7679 10:07:21.870958
7680 10:07:21.871068
7681 10:07:21.871128 ==
7682 10:07:21.874222 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 10:07:21.877651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 10:07:21.877789 ==
7685 10:07:21.877857
7686 10:07:21.877919
7687 10:07:21.880851 TX Vref Scan disable
7688 10:07:21.884665 == TX Byte 0 ==
7689 10:07:21.887493 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7690 10:07:21.890712 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7691 10:07:21.894305 == TX Byte 1 ==
7692 10:07:21.898059 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7693 10:07:21.901308 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7694 10:07:21.901467 ==
7695 10:07:21.904579 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 10:07:21.910654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 10:07:21.910813 ==
7698 10:07:21.922702
7699 10:07:21.925899 TX Vref early break, caculate TX vref
7700 10:07:21.929253 TX Vref=16, minBit 5, minWin=22, winSum=366
7701 10:07:21.932327 TX Vref=18, minBit 0, minWin=23, winSum=374
7702 10:07:21.935349 TX Vref=20, minBit 0, minWin=23, winSum=382
7703 10:07:21.939136 TX Vref=22, minBit 0, minWin=24, winSum=394
7704 10:07:21.942352 TX Vref=24, minBit 4, minWin=24, winSum=403
7705 10:07:21.949299 TX Vref=26, minBit 2, minWin=25, winSum=414
7706 10:07:21.952617 TX Vref=28, minBit 4, minWin=24, winSum=414
7707 10:07:21.955380 TX Vref=30, minBit 0, minWin=24, winSum=404
7708 10:07:21.958776 TX Vref=32, minBit 9, minWin=24, winSum=399
7709 10:07:21.962232 TX Vref=34, minBit 0, minWin=24, winSum=388
7710 10:07:21.968676 [TxChooseVref] Worse bit 2, Min win 25, Win sum 414, Final Vref 26
7711 10:07:21.969168
7712 10:07:21.972388 Final TX Range 0 Vref 26
7713 10:07:21.972887
7714 10:07:21.973204 ==
7715 10:07:21.975459 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 10:07:21.979186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 10:07:21.979750 ==
7718 10:07:21.980148
7719 10:07:21.980496
7720 10:07:21.982770 TX Vref Scan disable
7721 10:07:21.988555 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7722 10:07:21.989022 == TX Byte 0 ==
7723 10:07:21.991816 u2DelayCellOfst[0]=15 cells (4 PI)
7724 10:07:21.995398 u2DelayCellOfst[1]=18 cells (5 PI)
7725 10:07:21.998857 u2DelayCellOfst[2]=15 cells (4 PI)
7726 10:07:22.002181 u2DelayCellOfst[3]=15 cells (4 PI)
7727 10:07:22.004790 u2DelayCellOfst[4]=11 cells (3 PI)
7728 10:07:22.008782 u2DelayCellOfst[5]=0 cells (0 PI)
7729 10:07:22.011784 u2DelayCellOfst[6]=22 cells (6 PI)
7730 10:07:22.015070 u2DelayCellOfst[7]=22 cells (6 PI)
7731 10:07:22.018520 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7732 10:07:22.022580 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7733 10:07:22.025262 == TX Byte 1 ==
7734 10:07:22.028617 u2DelayCellOfst[8]=0 cells (0 PI)
7735 10:07:22.031173 u2DelayCellOfst[9]=0 cells (0 PI)
7736 10:07:22.034857 u2DelayCellOfst[10]=3 cells (1 PI)
7737 10:07:22.037978 u2DelayCellOfst[11]=3 cells (1 PI)
7738 10:07:22.041170 u2DelayCellOfst[12]=11 cells (3 PI)
7739 10:07:22.041729 u2DelayCellOfst[13]=7 cells (2 PI)
7740 10:07:22.044895 u2DelayCellOfst[14]=15 cells (4 PI)
7741 10:07:22.047772 u2DelayCellOfst[15]=7 cells (2 PI)
7742 10:07:22.054372 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7743 10:07:22.057605 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7744 10:07:22.060873 DramC Write-DBI on
7745 10:07:22.061427 ==
7746 10:07:22.064538 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 10:07:22.068027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 10:07:22.068585 ==
7749 10:07:22.068977
7750 10:07:22.069352
7751 10:07:22.071299 TX Vref Scan disable
7752 10:07:22.071758 == TX Byte 0 ==
7753 10:07:22.077606 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7754 10:07:22.078225 == TX Byte 1 ==
7755 10:07:22.080672 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7756 10:07:22.083741 DramC Write-DBI off
7757 10:07:22.084195
7758 10:07:22.084557 [DATLAT]
7759 10:07:22.087346 Freq=1600, CH0 RK0
7760 10:07:22.087825
7761 10:07:22.088186 DATLAT Default: 0xf
7762 10:07:22.090730 0, 0xFFFF, sum = 0
7763 10:07:22.093302 1, 0xFFFF, sum = 0
7764 10:07:22.093768 2, 0xFFFF, sum = 0
7765 10:07:22.097231 3, 0xFFFF, sum = 0
7766 10:07:22.097714 4, 0xFFFF, sum = 0
7767 10:07:22.100074 5, 0xFFFF, sum = 0
7768 10:07:22.100538 6, 0xFFFF, sum = 0
7769 10:07:22.103354 7, 0xFFFF, sum = 0
7770 10:07:22.104023 8, 0xFFFF, sum = 0
7771 10:07:22.107003 9, 0xFFFF, sum = 0
7772 10:07:22.107610 10, 0xFFFF, sum = 0
7773 10:07:22.110225 11, 0xFFFF, sum = 0
7774 10:07:22.110690 12, 0xFFFF, sum = 0
7775 10:07:22.113696 13, 0xCFFF, sum = 0
7776 10:07:22.114260 14, 0x0, sum = 1
7777 10:07:22.116871 15, 0x0, sum = 2
7778 10:07:22.117338 16, 0x0, sum = 3
7779 10:07:22.120137 17, 0x0, sum = 4
7780 10:07:22.120702 best_step = 15
7781 10:07:22.121067
7782 10:07:22.121402 ==
7783 10:07:22.123441 Dram Type= 6, Freq= 0, CH_0, rank 0
7784 10:07:22.130296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7785 10:07:22.131064 ==
7786 10:07:22.131450 RX Vref Scan: 1
7787 10:07:22.131790
7788 10:07:22.133450 Set Vref Range= 24 -> 127
7789 10:07:22.133907
7790 10:07:22.136946 RX Vref 24 -> 127, step: 1
7791 10:07:22.137402
7792 10:07:22.137760 RX Delay 11 -> 252, step: 4
7793 10:07:22.138099
7794 10:07:22.140135 Set Vref, RX VrefLevel [Byte0]: 24
7795 10:07:22.143131 [Byte1]: 24
7796 10:07:22.147446
7797 10:07:22.147999 Set Vref, RX VrefLevel [Byte0]: 25
7798 10:07:22.150505 [Byte1]: 25
7799 10:07:22.155217
7800 10:07:22.155676 Set Vref, RX VrefLevel [Byte0]: 26
7801 10:07:22.158447 [Byte1]: 26
7802 10:07:22.162588
7803 10:07:22.163181 Set Vref, RX VrefLevel [Byte0]: 27
7804 10:07:22.166167 [Byte1]: 27
7805 10:07:22.170195
7806 10:07:22.170748 Set Vref, RX VrefLevel [Byte0]: 28
7807 10:07:22.173343 [Byte1]: 28
7808 10:07:22.178072
7809 10:07:22.178626 Set Vref, RX VrefLevel [Byte0]: 29
7810 10:07:22.181017 [Byte1]: 29
7811 10:07:22.185862
7812 10:07:22.186433 Set Vref, RX VrefLevel [Byte0]: 30
7813 10:07:22.188793 [Byte1]: 30
7814 10:07:22.192790
7815 10:07:22.193243 Set Vref, RX VrefLevel [Byte0]: 31
7816 10:07:22.196438 [Byte1]: 31
7817 10:07:22.200453
7818 10:07:22.200911 Set Vref, RX VrefLevel [Byte0]: 32
7819 10:07:22.204140 [Byte1]: 32
7820 10:07:22.208450
7821 10:07:22.208904 Set Vref, RX VrefLevel [Byte0]: 33
7822 10:07:22.211656 [Byte1]: 33
7823 10:07:22.215843
7824 10:07:22.216475 Set Vref, RX VrefLevel [Byte0]: 34
7825 10:07:22.218928 [Byte1]: 34
7826 10:07:22.223401
7827 10:07:22.223874 Set Vref, RX VrefLevel [Byte0]: 35
7828 10:07:22.226425 [Byte1]: 35
7829 10:07:22.231090
7830 10:07:22.231637 Set Vref, RX VrefLevel [Byte0]: 36
7831 10:07:22.234115 [Byte1]: 36
7832 10:07:22.238617
7833 10:07:22.239116 Set Vref, RX VrefLevel [Byte0]: 37
7834 10:07:22.241735 [Byte1]: 37
7835 10:07:22.246602
7836 10:07:22.247262 Set Vref, RX VrefLevel [Byte0]: 38
7837 10:07:22.249494 [Byte1]: 38
7838 10:07:22.254382
7839 10:07:22.254981 Set Vref, RX VrefLevel [Byte0]: 39
7840 10:07:22.257359 [Byte1]: 39
7841 10:07:22.261600
7842 10:07:22.262152 Set Vref, RX VrefLevel [Byte0]: 40
7843 10:07:22.264927 [Byte1]: 40
7844 10:07:22.269066
7845 10:07:22.272090 Set Vref, RX VrefLevel [Byte0]: 41
7846 10:07:22.275592 [Byte1]: 41
7847 10:07:22.276146
7848 10:07:22.278742 Set Vref, RX VrefLevel [Byte0]: 42
7849 10:07:22.282453 [Byte1]: 42
7850 10:07:22.283050
7851 10:07:22.285030 Set Vref, RX VrefLevel [Byte0]: 43
7852 10:07:22.288308 [Byte1]: 43
7853 10:07:22.292237
7854 10:07:22.292793 Set Vref, RX VrefLevel [Byte0]: 44
7855 10:07:22.295368 [Byte1]: 44
7856 10:07:22.299847
7857 10:07:22.300417 Set Vref, RX VrefLevel [Byte0]: 45
7858 10:07:22.302819 [Byte1]: 45
7859 10:07:22.307172
7860 10:07:22.307624 Set Vref, RX VrefLevel [Byte0]: 46
7861 10:07:22.310319 [Byte1]: 46
7862 10:07:22.314793
7863 10:07:22.315286 Set Vref, RX VrefLevel [Byte0]: 47
7864 10:07:22.317725 [Byte1]: 47
7865 10:07:22.322861
7866 10:07:22.323501 Set Vref, RX VrefLevel [Byte0]: 48
7867 10:07:22.325930 [Byte1]: 48
7868 10:07:22.329989
7869 10:07:22.330547 Set Vref, RX VrefLevel [Byte0]: 49
7870 10:07:22.333699 [Byte1]: 49
7871 10:07:22.337511
7872 10:07:22.337963 Set Vref, RX VrefLevel [Byte0]: 50
7873 10:07:22.341144 [Byte1]: 50
7874 10:07:22.345229
7875 10:07:22.345687 Set Vref, RX VrefLevel [Byte0]: 51
7876 10:07:22.348523 [Byte1]: 51
7877 10:07:22.353389
7878 10:07:22.353936 Set Vref, RX VrefLevel [Byte0]: 52
7879 10:07:22.356395 [Byte1]: 52
7880 10:07:22.360716
7881 10:07:22.361264 Set Vref, RX VrefLevel [Byte0]: 53
7882 10:07:22.363715 [Byte1]: 53
7883 10:07:22.368233
7884 10:07:22.368783 Set Vref, RX VrefLevel [Byte0]: 54
7885 10:07:22.371224 [Byte1]: 54
7886 10:07:22.375955
7887 10:07:22.376506 Set Vref, RX VrefLevel [Byte0]: 55
7888 10:07:22.379358 [Byte1]: 55
7889 10:07:22.383411
7890 10:07:22.383956 Set Vref, RX VrefLevel [Byte0]: 56
7891 10:07:22.386795 [Byte1]: 56
7892 10:07:22.391107
7893 10:07:22.391656 Set Vref, RX VrefLevel [Byte0]: 57
7894 10:07:22.394668 [Byte1]: 57
7895 10:07:22.398643
7896 10:07:22.399239 Set Vref, RX VrefLevel [Byte0]: 58
7897 10:07:22.402050 [Byte1]: 58
7898 10:07:22.406012
7899 10:07:22.406471 Set Vref, RX VrefLevel [Byte0]: 59
7900 10:07:22.409266 [Byte1]: 59
7901 10:07:22.413481
7902 10:07:22.413989 Set Vref, RX VrefLevel [Byte0]: 60
7903 10:07:22.417113 [Byte1]: 60
7904 10:07:22.421516
7905 10:07:22.422071 Set Vref, RX VrefLevel [Byte0]: 61
7906 10:07:22.424665 [Byte1]: 61
7907 10:07:22.428872
7908 10:07:22.429417 Set Vref, RX VrefLevel [Byte0]: 62
7909 10:07:22.432460 [Byte1]: 62
7910 10:07:22.436562
7911 10:07:22.437018 Set Vref, RX VrefLevel [Byte0]: 63
7912 10:07:22.440294 [Byte1]: 63
7913 10:07:22.445022
7914 10:07:22.445572 Set Vref, RX VrefLevel [Byte0]: 64
7915 10:07:22.447685 [Byte1]: 64
7916 10:07:22.451810
7917 10:07:22.452362 Set Vref, RX VrefLevel [Byte0]: 65
7918 10:07:22.455130 [Byte1]: 65
7919 10:07:22.459710
7920 10:07:22.460263 Set Vref, RX VrefLevel [Byte0]: 66
7921 10:07:22.463352 [Byte1]: 66
7922 10:07:22.467597
7923 10:07:22.468151 Set Vref, RX VrefLevel [Byte0]: 67
7924 10:07:22.470363 [Byte1]: 67
7925 10:07:22.475151
7926 10:07:22.475706 Set Vref, RX VrefLevel [Byte0]: 68
7927 10:07:22.478101 [Byte1]: 68
7928 10:07:22.482418
7929 10:07:22.483019 Set Vref, RX VrefLevel [Byte0]: 69
7930 10:07:22.485573 [Byte1]: 69
7931 10:07:22.490242
7932 10:07:22.490795 Set Vref, RX VrefLevel [Byte0]: 70
7933 10:07:22.493388 [Byte1]: 70
7934 10:07:22.497615
7935 10:07:22.498174 Set Vref, RX VrefLevel [Byte0]: 71
7936 10:07:22.501275 [Byte1]: 71
7937 10:07:22.505107
7938 10:07:22.505561 Set Vref, RX VrefLevel [Byte0]: 72
7939 10:07:22.508301 [Byte1]: 72
7940 10:07:22.512364
7941 10:07:22.512817 Set Vref, RX VrefLevel [Byte0]: 73
7942 10:07:22.516314 [Byte1]: 73
7943 10:07:22.520541
7944 10:07:22.521189 Set Vref, RX VrefLevel [Byte0]: 74
7945 10:07:22.523399 [Byte1]: 74
7946 10:07:22.528089
7947 10:07:22.528645 Set Vref, RX VrefLevel [Byte0]: 75
7948 10:07:22.531514 [Byte1]: 75
7949 10:07:22.535670
7950 10:07:22.536123 Set Vref, RX VrefLevel [Byte0]: 76
7951 10:07:22.538940 [Byte1]: 76
7952 10:07:22.543325
7953 10:07:22.543879 Final RX Vref Byte 0 = 64 to rank0
7954 10:07:22.546406 Final RX Vref Byte 1 = 60 to rank0
7955 10:07:22.550054 Final RX Vref Byte 0 = 64 to rank1
7956 10:07:22.552997 Final RX Vref Byte 1 = 60 to rank1==
7957 10:07:22.556401 Dram Type= 6, Freq= 0, CH_0, rank 0
7958 10:07:22.562790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7959 10:07:22.563384 ==
7960 10:07:22.563753 DQS Delay:
7961 10:07:22.566572 DQS0 = 0, DQS1 = 0
7962 10:07:22.567179 DQM Delay:
7963 10:07:22.567553 DQM0 = 126, DQM1 = 119
7964 10:07:22.569491 DQ Delay:
7965 10:07:22.572678 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
7966 10:07:22.575920 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7967 10:07:22.579432 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7968 10:07:22.582585 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7969 10:07:22.583172
7970 10:07:22.583536
7971 10:07:22.583872
7972 10:07:22.586326 [DramC_TX_OE_Calibration] TA2
7973 10:07:22.589467 Original DQ_B0 (3 6) =30, OEN = 27
7974 10:07:22.592564 Original DQ_B1 (3 6) =30, OEN = 27
7975 10:07:22.595686 24, 0x0, End_B0=24 End_B1=24
7976 10:07:22.599092 25, 0x0, End_B0=25 End_B1=25
7977 10:07:22.599660 26, 0x0, End_B0=26 End_B1=26
7978 10:07:22.602738 27, 0x0, End_B0=27 End_B1=27
7979 10:07:22.605500 28, 0x0, End_B0=28 End_B1=28
7980 10:07:22.609389 29, 0x0, End_B0=29 End_B1=29
7981 10:07:22.609960 30, 0x0, End_B0=30 End_B1=30
7982 10:07:22.612285 31, 0x4141, End_B0=30 End_B1=30
7983 10:07:22.615390 Byte0 end_step=30 best_step=27
7984 10:07:22.618919 Byte1 end_step=30 best_step=27
7985 10:07:22.622173 Byte0 TX OE(2T, 0.5T) = (3, 3)
7986 10:07:22.625961 Byte1 TX OE(2T, 0.5T) = (3, 3)
7987 10:07:22.626517
7988 10:07:22.626927
7989 10:07:22.632388 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
7990 10:07:22.635360 CH0 RK0: MR19=303, MR18=1414
7991 10:07:22.641881 CH0_RK0: MR19=0x303, MR18=0x1414, DQSOSC=399, MR23=63, INC=23, DEC=15
7992 10:07:22.642447
7993 10:07:22.645204 ----->DramcWriteLeveling(PI) begin...
7994 10:07:22.645672 ==
7995 10:07:22.648938 Dram Type= 6, Freq= 0, CH_0, rank 1
7996 10:07:22.652237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7997 10:07:22.652698 ==
7998 10:07:22.655185 Write leveling (Byte 0): 34 => 34
7999 10:07:22.658115 Write leveling (Byte 1): 28 => 28
8000 10:07:22.661843 DramcWriteLeveling(PI) end<-----
8001 10:07:22.662401
8002 10:07:22.662766 ==
8003 10:07:22.665026 Dram Type= 6, Freq= 0, CH_0, rank 1
8004 10:07:22.671399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8005 10:07:22.671957 ==
8006 10:07:22.672342 [Gating] SW mode calibration
8007 10:07:22.681248 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8008 10:07:22.684679 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8009 10:07:22.691542 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 10:07:22.694533 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 10:07:22.697781 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
8012 10:07:22.704285 1 4 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
8013 10:07:22.707596 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8014 10:07:22.711272 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 10:07:22.717928 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 10:07:22.721194 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 10:07:22.724023 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 10:07:22.730805 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 10:07:22.734308 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8020 10:07:22.737228 1 5 12 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
8021 10:07:22.744371 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (0 1) (0 0)
8022 10:07:22.747265 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
8023 10:07:22.750861 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 10:07:22.756928 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 10:07:22.760407 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 10:07:22.763349 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 10:07:22.770059 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8028 10:07:22.773662 1 6 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8029 10:07:22.777010 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
8030 10:07:22.783308 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8031 10:07:22.786893 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 10:07:22.790308 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 10:07:22.796468 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 10:07:22.800225 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 10:07:22.803091 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8036 10:07:22.810110 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8037 10:07:22.813110 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8038 10:07:22.816587 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8039 10:07:22.822994 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 10:07:22.826042 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 10:07:22.829472 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 10:07:22.835858 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 10:07:22.839271 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 10:07:22.842751 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 10:07:22.849273 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 10:07:22.852325 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 10:07:22.855987 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 10:07:22.862124 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 10:07:22.865691 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 10:07:22.868804 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 10:07:22.875933 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8052 10:07:22.878951 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8053 10:07:22.882481 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8054 10:07:22.885818 Total UI for P1: 0, mck2ui 16
8055 10:07:22.888792 best dqsien dly found for B0: ( 1, 9, 10)
8056 10:07:22.895719 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8057 10:07:22.898717 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 10:07:22.901685 Total UI for P1: 0, mck2ui 16
8059 10:07:22.905155 best dqsien dly found for B1: ( 1, 9, 18)
8060 10:07:22.908049 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8061 10:07:22.911779 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8062 10:07:22.912336
8063 10:07:22.914872 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8064 10:07:22.918056 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8065 10:07:22.921464 [Gating] SW calibration Done
8066 10:07:22.921920 ==
8067 10:07:22.924857 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 10:07:22.931739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 10:07:22.932299 ==
8070 10:07:22.932665 RX Vref Scan: 0
8071 10:07:22.933002
8072 10:07:22.934565 RX Vref 0 -> 0, step: 1
8073 10:07:22.935044
8074 10:07:22.937819 RX Delay 0 -> 252, step: 8
8075 10:07:22.941090 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8076 10:07:22.944610 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8077 10:07:22.947721 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8078 10:07:22.951435 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8079 10:07:22.957469 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8080 10:07:22.960806 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8081 10:07:22.963997 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8082 10:07:22.967552 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8083 10:07:22.971299 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8084 10:07:22.977184 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8085 10:07:22.980843 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8086 10:07:22.984185 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8087 10:07:22.987697 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8088 10:07:22.994192 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8089 10:07:22.996804 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8090 10:07:23.000407 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8091 10:07:23.000960 ==
8092 10:07:23.003676 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 10:07:23.007142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 10:07:23.010168 ==
8095 10:07:23.010717 DQS Delay:
8096 10:07:23.011141 DQS0 = 0, DQS1 = 0
8097 10:07:23.013937 DQM Delay:
8098 10:07:23.014484 DQM0 = 128, DQM1 = 121
8099 10:07:23.016974 DQ Delay:
8100 10:07:23.020230 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8101 10:07:23.023374 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8102 10:07:23.026780 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8103 10:07:23.029929 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8104 10:07:23.030478
8105 10:07:23.030883
8106 10:07:23.031234 ==
8107 10:07:23.033119 Dram Type= 6, Freq= 0, CH_0, rank 1
8108 10:07:23.036997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8109 10:07:23.039606 ==
8110 10:07:23.040070
8111 10:07:23.040429
8112 10:07:23.040767 TX Vref Scan disable
8113 10:07:23.043365 == TX Byte 0 ==
8114 10:07:23.046306 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8115 10:07:23.050159 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8116 10:07:23.053016 == TX Byte 1 ==
8117 10:07:23.056676 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8118 10:07:23.059553 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8119 10:07:23.063152 ==
8120 10:07:23.063843 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 10:07:23.069665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 10:07:23.070222 ==
8123 10:07:23.082506
8124 10:07:23.085641 TX Vref early break, caculate TX vref
8125 10:07:23.089064 TX Vref=16, minBit 0, minWin=22, winSum=364
8126 10:07:23.092211 TX Vref=18, minBit 0, minWin=22, winSum=372
8127 10:07:23.095318 TX Vref=20, minBit 4, minWin=23, winSum=380
8128 10:07:23.098738 TX Vref=22, minBit 8, minWin=23, winSum=390
8129 10:07:23.102127 TX Vref=24, minBit 8, minWin=23, winSum=400
8130 10:07:23.109008 TX Vref=26, minBit 0, minWin=24, winSum=403
8131 10:07:23.111602 TX Vref=28, minBit 8, minWin=24, winSum=409
8132 10:07:23.115779 TX Vref=30, minBit 8, minWin=23, winSum=405
8133 10:07:23.118425 TX Vref=32, minBit 8, minWin=23, winSum=399
8134 10:07:23.121873 TX Vref=34, minBit 8, minWin=22, winSum=385
8135 10:07:23.128702 [TxChooseVref] Worse bit 8, Min win 24, Win sum 409, Final Vref 28
8136 10:07:23.129266
8137 10:07:23.132167 Final TX Range 0 Vref 28
8138 10:07:23.132724
8139 10:07:23.133090 ==
8140 10:07:23.134796 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 10:07:23.137954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 10:07:23.138412 ==
8143 10:07:23.138859
8144 10:07:23.139382
8145 10:07:23.141585 TX Vref Scan disable
8146 10:07:23.148324 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8147 10:07:23.148874 == TX Byte 0 ==
8148 10:07:23.151751 u2DelayCellOfst[0]=15 cells (4 PI)
8149 10:07:23.155434 u2DelayCellOfst[1]=15 cells (4 PI)
8150 10:07:23.158286 u2DelayCellOfst[2]=7 cells (2 PI)
8151 10:07:23.161415 u2DelayCellOfst[3]=11 cells (3 PI)
8152 10:07:23.164796 u2DelayCellOfst[4]=7 cells (2 PI)
8153 10:07:23.168006 u2DelayCellOfst[5]=0 cells (0 PI)
8154 10:07:23.171356 u2DelayCellOfst[6]=18 cells (5 PI)
8155 10:07:23.174509 u2DelayCellOfst[7]=18 cells (5 PI)
8156 10:07:23.177641 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8157 10:07:23.180939 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8158 10:07:23.184601 == TX Byte 1 ==
8159 10:07:23.188199 u2DelayCellOfst[8]=0 cells (0 PI)
8160 10:07:23.190912 u2DelayCellOfst[9]=3 cells (1 PI)
8161 10:07:23.191375 u2DelayCellOfst[10]=7 cells (2 PI)
8162 10:07:23.194048 u2DelayCellOfst[11]=7 cells (2 PI)
8163 10:07:23.197277 u2DelayCellOfst[12]=15 cells (4 PI)
8164 10:07:23.201046 u2DelayCellOfst[13]=11 cells (3 PI)
8165 10:07:23.204028 u2DelayCellOfst[14]=15 cells (4 PI)
8166 10:07:23.207316 u2DelayCellOfst[15]=11 cells (3 PI)
8167 10:07:23.214344 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8168 10:07:23.217423 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8169 10:07:23.217983 DramC Write-DBI on
8170 10:07:23.218349 ==
8171 10:07:23.221027 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 10:07:23.227583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 10:07:23.228142 ==
8174 10:07:23.228507
8175 10:07:23.228844
8176 10:07:23.230696 TX Vref Scan disable
8177 10:07:23.231286 == TX Byte 0 ==
8178 10:07:23.237375 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8179 10:07:23.237941 == TX Byte 1 ==
8180 10:07:23.240234 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8181 10:07:23.244048 DramC Write-DBI off
8182 10:07:23.244604
8183 10:07:23.244971 [DATLAT]
8184 10:07:23.247012 Freq=1600, CH0 RK1
8185 10:07:23.247569
8186 10:07:23.247933 DATLAT Default: 0xf
8187 10:07:23.250792 0, 0xFFFF, sum = 0
8188 10:07:23.251394 1, 0xFFFF, sum = 0
8189 10:07:23.253722 2, 0xFFFF, sum = 0
8190 10:07:23.254286 3, 0xFFFF, sum = 0
8191 10:07:23.256717 4, 0xFFFF, sum = 0
8192 10:07:23.257178 5, 0xFFFF, sum = 0
8193 10:07:23.260019 6, 0xFFFF, sum = 0
8194 10:07:23.263475 7, 0xFFFF, sum = 0
8195 10:07:23.264038 8, 0xFFFF, sum = 0
8196 10:07:23.266789 9, 0xFFFF, sum = 0
8197 10:07:23.267283 10, 0xFFFF, sum = 0
8198 10:07:23.269881 11, 0xFFFF, sum = 0
8199 10:07:23.270457 12, 0xFFFF, sum = 0
8200 10:07:23.273292 13, 0xEFFF, sum = 0
8201 10:07:23.273831 14, 0x0, sum = 1
8202 10:07:23.276329 15, 0x0, sum = 2
8203 10:07:23.276793 16, 0x0, sum = 3
8204 10:07:23.279935 17, 0x0, sum = 4
8205 10:07:23.280502 best_step = 15
8206 10:07:23.280867
8207 10:07:23.281396 ==
8208 10:07:23.283124 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 10:07:23.287135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 10:07:23.289861 ==
8211 10:07:23.290330 RX Vref Scan: 0
8212 10:07:23.290694
8213 10:07:23.293343 RX Vref 0 -> 0, step: 1
8214 10:07:23.293913
8215 10:07:23.296023 RX Delay 3 -> 252, step: 4
8216 10:07:23.299663 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8217 10:07:23.302760 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8218 10:07:23.305942 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8219 10:07:23.312706 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8220 10:07:23.315846 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8221 10:07:23.319154 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8222 10:07:23.322713 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8223 10:07:23.326135 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8224 10:07:23.332788 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8225 10:07:23.335788 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8226 10:07:23.338885 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8227 10:07:23.342721 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8228 10:07:23.345983 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8229 10:07:23.352126 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8230 10:07:23.355701 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8231 10:07:23.358902 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8232 10:07:23.359459 ==
8233 10:07:23.361960 Dram Type= 6, Freq= 0, CH_0, rank 1
8234 10:07:23.368748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8235 10:07:23.369304 ==
8236 10:07:23.369668 DQS Delay:
8237 10:07:23.370004 DQS0 = 0, DQS1 = 0
8238 10:07:23.371801 DQM Delay:
8239 10:07:23.372355 DQM0 = 124, DQM1 = 118
8240 10:07:23.375117 DQ Delay:
8241 10:07:23.378880 DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =122
8242 10:07:23.381735 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8243 10:07:23.385210 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8244 10:07:23.388430 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8245 10:07:23.388992
8246 10:07:23.389361
8247 10:07:23.389764
8248 10:07:23.391686 [DramC_TX_OE_Calibration] TA2
8249 10:07:23.395243 Original DQ_B0 (3 6) =30, OEN = 27
8250 10:07:23.398578 Original DQ_B1 (3 6) =30, OEN = 27
8251 10:07:23.401721 24, 0x0, End_B0=24 End_B1=24
8252 10:07:23.402300 25, 0x0, End_B0=25 End_B1=25
8253 10:07:23.404734 26, 0x0, End_B0=26 End_B1=26
8254 10:07:23.408202 27, 0x0, End_B0=27 End_B1=27
8255 10:07:23.411187 28, 0x0, End_B0=28 End_B1=28
8256 10:07:23.414991 29, 0x0, End_B0=29 End_B1=29
8257 10:07:23.415564 30, 0x0, End_B0=30 End_B1=30
8258 10:07:23.417953 31, 0x4141, End_B0=30 End_B1=30
8259 10:07:23.421130 Byte0 end_step=30 best_step=27
8260 10:07:23.424783 Byte1 end_step=30 best_step=27
8261 10:07:23.427635 Byte0 TX OE(2T, 0.5T) = (3, 3)
8262 10:07:23.431329 Byte1 TX OE(2T, 0.5T) = (3, 3)
8263 10:07:23.431783
8264 10:07:23.432142
8265 10:07:23.437414 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8266 10:07:23.441041 CH0 RK1: MR19=303, MR18=210E
8267 10:07:23.447687 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8268 10:07:23.450935 [RxdqsGatingPostProcess] freq 1600
8269 10:07:23.457861 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8270 10:07:23.458418 best DQS0 dly(2T, 0.5T) = (1, 1)
8271 10:07:23.460897 best DQS1 dly(2T, 0.5T) = (1, 1)
8272 10:07:23.463845 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8273 10:07:23.467719 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8274 10:07:23.470902 best DQS0 dly(2T, 0.5T) = (1, 1)
8275 10:07:23.473924 best DQS1 dly(2T, 0.5T) = (1, 1)
8276 10:07:23.477357 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8277 10:07:23.480422 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8278 10:07:23.483892 Pre-setting of DQS Precalculation
8279 10:07:23.486804 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8280 10:07:23.487301 ==
8281 10:07:23.490307 Dram Type= 6, Freq= 0, CH_1, rank 0
8282 10:07:23.497028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 10:07:23.497594 ==
8284 10:07:23.500397 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8285 10:07:23.506689 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8286 10:07:23.510158 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8287 10:07:23.516857 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8288 10:07:23.524567 [CA 0] Center 41 (12~71) winsize 60
8289 10:07:23.528386 [CA 1] Center 42 (13~72) winsize 60
8290 10:07:23.531323 [CA 2] Center 37 (8~66) winsize 59
8291 10:07:23.534545 [CA 3] Center 37 (8~66) winsize 59
8292 10:07:23.537597 [CA 4] Center 37 (8~67) winsize 60
8293 10:07:23.540825 [CA 5] Center 36 (7~66) winsize 60
8294 10:07:23.541267
8295 10:07:23.544628 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8296 10:07:23.545073
8297 10:07:23.547781 [CATrainingPosCal] consider 1 rank data
8298 10:07:23.550931 u2DelayCellTimex100 = 258/100 ps
8299 10:07:23.557490 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8300 10:07:23.561320 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8301 10:07:23.564827 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8302 10:07:23.567697 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8303 10:07:23.571195 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8304 10:07:23.574175 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8305 10:07:23.574670
8306 10:07:23.577198 CA PerBit enable=1, Macro0, CA PI delay=36
8307 10:07:23.577639
8308 10:07:23.580399 [CBTSetCACLKResult] CA Dly = 36
8309 10:07:23.583432 CS Dly: 9 (0~40)
8310 10:07:23.587383 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8311 10:07:23.590701 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8312 10:07:23.591297 ==
8313 10:07:23.593537 Dram Type= 6, Freq= 0, CH_1, rank 1
8314 10:07:23.600387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8315 10:07:23.600935 ==
8316 10:07:23.603471 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8317 10:07:23.610141 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8318 10:07:23.613125 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8319 10:07:23.619681 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8320 10:07:23.627668 [CA 0] Center 42 (13~71) winsize 59
8321 10:07:23.630887 [CA 1] Center 42 (12~72) winsize 61
8322 10:07:23.634516 [CA 2] Center 38 (9~67) winsize 59
8323 10:07:23.637572 [CA 3] Center 36 (7~66) winsize 60
8324 10:07:23.640904 [CA 4] Center 38 (8~68) winsize 61
8325 10:07:23.644233 [CA 5] Center 36 (6~66) winsize 61
8326 10:07:23.644676
8327 10:07:23.647621 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8328 10:07:23.648067
8329 10:07:23.650756 [CATrainingPosCal] consider 2 rank data
8330 10:07:23.654196 u2DelayCellTimex100 = 258/100 ps
8331 10:07:23.660962 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8332 10:07:23.664187 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8333 10:07:23.667472 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8334 10:07:23.671162 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8335 10:07:23.674209 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8336 10:07:23.677298 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8337 10:07:23.677769
8338 10:07:23.680650 CA PerBit enable=1, Macro0, CA PI delay=36
8339 10:07:23.681201
8340 10:07:23.684226 [CBTSetCACLKResult] CA Dly = 36
8341 10:07:23.687355 CS Dly: 10 (0~43)
8342 10:07:23.690390 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8343 10:07:23.694173 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8344 10:07:23.694717
8345 10:07:23.697505 ----->DramcWriteLeveling(PI) begin...
8346 10:07:23.698054 ==
8347 10:07:23.700498 Dram Type= 6, Freq= 0, CH_1, rank 0
8348 10:07:23.706630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8349 10:07:23.707199 ==
8350 10:07:23.710075 Write leveling (Byte 0): 24 => 24
8351 10:07:23.713140 Write leveling (Byte 1): 29 => 29
8352 10:07:23.717069 DramcWriteLeveling(PI) end<-----
8353 10:07:23.717611
8354 10:07:23.717964 ==
8355 10:07:23.720057 Dram Type= 6, Freq= 0, CH_1, rank 0
8356 10:07:23.723498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8357 10:07:23.724047 ==
8358 10:07:23.726512 [Gating] SW mode calibration
8359 10:07:23.733230 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8360 10:07:23.740066 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8361 10:07:23.742991 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 10:07:23.746188 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 10:07:23.753187 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 10:07:23.755876 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 10:07:23.759789 1 4 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8366 10:07:23.766053 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 10:07:23.769552 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 10:07:23.772928 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 10:07:23.779159 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 10:07:23.782344 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 10:07:23.786029 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 10:07:23.792731 1 5 12 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8373 10:07:23.796094 1 5 16 | B1->B0 | 2323 2525 | 0 0 | (1 0) (1 0)
8374 10:07:23.799118 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 10:07:23.805580 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 10:07:23.809054 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 10:07:23.812062 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 10:07:23.818693 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 10:07:23.821590 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 10:07:23.825118 1 6 12 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
8381 10:07:23.831723 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 10:07:23.835620 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 10:07:23.838253 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 10:07:23.845069 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 10:07:23.848380 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 10:07:23.851358 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 10:07:23.858540 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 10:07:23.861570 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 10:07:23.864743 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8390 10:07:23.870948 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8391 10:07:23.874738 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 10:07:23.878000 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 10:07:23.884721 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 10:07:23.887685 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 10:07:23.890933 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 10:07:23.897214 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 10:07:23.901179 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 10:07:23.904031 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 10:07:23.910567 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 10:07:23.914200 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 10:07:23.917151 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 10:07:23.924194 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 10:07:23.927154 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 10:07:23.930245 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 10:07:23.936672 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8406 10:07:23.940090 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 10:07:23.943161 Total UI for P1: 0, mck2ui 16
8408 10:07:23.946998 best dqsien dly found for B0: ( 1, 9, 16)
8409 10:07:23.950186 Total UI for P1: 0, mck2ui 16
8410 10:07:23.953371 best dqsien dly found for B1: ( 1, 9, 16)
8411 10:07:23.956833 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8412 10:07:23.959688 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8413 10:07:23.960147
8414 10:07:23.963053 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8415 10:07:23.970528 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8416 10:07:23.971131 [Gating] SW calibration Done
8417 10:07:23.971502 ==
8418 10:07:23.972955 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 10:07:23.979495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 10:07:23.980044 ==
8421 10:07:23.980416 RX Vref Scan: 0
8422 10:07:23.980757
8423 10:07:23.983232 RX Vref 0 -> 0, step: 1
8424 10:07:23.983782
8425 10:07:23.986271 RX Delay 0 -> 252, step: 8
8426 10:07:23.989411 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8427 10:07:23.992407 iDelay=208, Bit 1, Center 127 (64 ~ 191) 128
8428 10:07:23.996505 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8429 10:07:24.002664 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8430 10:07:24.006165 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8431 10:07:24.008968 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8432 10:07:24.012813 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8433 10:07:24.016033 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8434 10:07:24.022315 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8435 10:07:24.025781 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8436 10:07:24.028915 iDelay=208, Bit 10, Center 127 (80 ~ 175) 96
8437 10:07:24.032191 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8438 10:07:24.035519 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8439 10:07:24.042073 iDelay=208, Bit 13, Center 131 (72 ~ 191) 120
8440 10:07:24.045603 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8441 10:07:24.048727 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8442 10:07:24.049187 ==
8443 10:07:24.051862 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 10:07:24.055528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 10:07:24.058460 ==
8446 10:07:24.059057 DQS Delay:
8447 10:07:24.059441 DQS0 = 0, DQS1 = 0
8448 10:07:24.062318 DQM Delay:
8449 10:07:24.062772 DQM0 = 133, DQM1 = 126
8450 10:07:24.065810 DQ Delay:
8451 10:07:24.068438 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =131
8452 10:07:24.072177 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8453 10:07:24.075058 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8454 10:07:24.078412 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8455 10:07:24.078989
8456 10:07:24.079356
8457 10:07:24.079692 ==
8458 10:07:24.081815 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 10:07:24.085212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 10:07:24.088319 ==
8461 10:07:24.088867
8462 10:07:24.089236
8463 10:07:24.089576 TX Vref Scan disable
8464 10:07:24.091338 == TX Byte 0 ==
8465 10:07:24.094695 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8466 10:07:24.098205 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8467 10:07:24.101445 == TX Byte 1 ==
8468 10:07:24.104931 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8469 10:07:24.108015 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8470 10:07:24.111095 ==
8471 10:07:24.114584 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 10:07:24.117932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 10:07:24.118491 ==
8474 10:07:24.131392
8475 10:07:24.134799 TX Vref early break, caculate TX vref
8476 10:07:24.137806 TX Vref=16, minBit 8, minWin=21, winSum=359
8477 10:07:24.140910 TX Vref=18, minBit 8, minWin=21, winSum=364
8478 10:07:24.144496 TX Vref=20, minBit 10, minWin=22, winSum=377
8479 10:07:24.147412 TX Vref=22, minBit 5, minWin=23, winSum=386
8480 10:07:24.154234 TX Vref=24, minBit 11, minWin=23, winSum=396
8481 10:07:24.157362 TX Vref=26, minBit 10, minWin=24, winSum=405
8482 10:07:24.160601 TX Vref=28, minBit 13, minWin=24, winSum=409
8483 10:07:24.164247 TX Vref=30, minBit 6, minWin=24, winSum=409
8484 10:07:24.167754 TX Vref=32, minBit 1, minWin=24, winSum=403
8485 10:07:24.170631 TX Vref=34, minBit 6, minWin=23, winSum=393
8486 10:07:24.177406 TX Vref=36, minBit 0, minWin=22, winSum=377
8487 10:07:24.180416 [TxChooseVref] Worse bit 13, Min win 24, Win sum 409, Final Vref 28
8488 10:07:24.180870
8489 10:07:24.183888 Final TX Range 0 Vref 28
8490 10:07:24.184456
8491 10:07:24.184827 ==
8492 10:07:24.186970 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 10:07:24.193747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 10:07:24.194283 ==
8495 10:07:24.194646
8496 10:07:24.195015
8497 10:07:24.195343 TX Vref Scan disable
8498 10:07:24.201120 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8499 10:07:24.201673 == TX Byte 0 ==
8500 10:07:24.204398 u2DelayCellOfst[0]=22 cells (6 PI)
8501 10:07:24.207516 u2DelayCellOfst[1]=18 cells (5 PI)
8502 10:07:24.211014 u2DelayCellOfst[2]=0 cells (0 PI)
8503 10:07:24.214295 u2DelayCellOfst[3]=7 cells (2 PI)
8504 10:07:24.217550 u2DelayCellOfst[4]=11 cells (3 PI)
8505 10:07:24.220618 u2DelayCellOfst[5]=22 cells (6 PI)
8506 10:07:24.224041 u2DelayCellOfst[6]=22 cells (6 PI)
8507 10:07:24.227367 u2DelayCellOfst[7]=7 cells (2 PI)
8508 10:07:24.231002 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8509 10:07:24.234191 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8510 10:07:24.237018 == TX Byte 1 ==
8511 10:07:24.240345 u2DelayCellOfst[8]=0 cells (0 PI)
8512 10:07:24.244558 u2DelayCellOfst[9]=11 cells (3 PI)
8513 10:07:24.247286 u2DelayCellOfst[10]=15 cells (4 PI)
8514 10:07:24.250888 u2DelayCellOfst[11]=15 cells (4 PI)
8515 10:07:24.253801 u2DelayCellOfst[12]=18 cells (5 PI)
8516 10:07:24.257212 u2DelayCellOfst[13]=22 cells (6 PI)
8517 10:07:24.260509 u2DelayCellOfst[14]=22 cells (6 PI)
8518 10:07:24.261125 u2DelayCellOfst[15]=22 cells (6 PI)
8519 10:07:24.266753 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8520 10:07:24.270357 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8521 10:07:24.273359 DramC Write-DBI on
8522 10:07:24.273917 ==
8523 10:07:24.276903 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 10:07:24.279956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 10:07:24.280419 ==
8526 10:07:24.280817
8527 10:07:24.281159
8528 10:07:24.283567 TX Vref Scan disable
8529 10:07:24.284128 == TX Byte 0 ==
8530 10:07:24.290138 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8531 10:07:24.290704 == TX Byte 1 ==
8532 10:07:24.296811 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8533 10:07:24.297389 DramC Write-DBI off
8534 10:07:24.297759
8535 10:07:24.298100 [DATLAT]
8536 10:07:24.300215 Freq=1600, CH1 RK0
8537 10:07:24.300677
8538 10:07:24.303193 DATLAT Default: 0xf
8539 10:07:24.303753 0, 0xFFFF, sum = 0
8540 10:07:24.306290 1, 0xFFFF, sum = 0
8541 10:07:24.306890 2, 0xFFFF, sum = 0
8542 10:07:24.309836 3, 0xFFFF, sum = 0
8543 10:07:24.310420 4, 0xFFFF, sum = 0
8544 10:07:24.313002 5, 0xFFFF, sum = 0
8545 10:07:24.313575 6, 0xFFFF, sum = 0
8546 10:07:24.316598 7, 0xFFFF, sum = 0
8547 10:07:24.317172 8, 0xFFFF, sum = 0
8548 10:07:24.319721 9, 0xFFFF, sum = 0
8549 10:07:24.320292 10, 0xFFFF, sum = 0
8550 10:07:24.322972 11, 0xFFFF, sum = 0
8551 10:07:24.323565 12, 0xFFFF, sum = 0
8552 10:07:24.326118 13, 0x8FFF, sum = 0
8553 10:07:24.326690 14, 0x0, sum = 1
8554 10:07:24.329629 15, 0x0, sum = 2
8555 10:07:24.330197 16, 0x0, sum = 3
8556 10:07:24.332723 17, 0x0, sum = 4
8557 10:07:24.333191 best_step = 15
8558 10:07:24.333555
8559 10:07:24.333899 ==
8560 10:07:24.335814 Dram Type= 6, Freq= 0, CH_1, rank 0
8561 10:07:24.342938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8562 10:07:24.343403 ==
8563 10:07:24.343772 RX Vref Scan: 1
8564 10:07:24.344113
8565 10:07:24.346107 Set Vref Range= 24 -> 127
8566 10:07:24.346669
8567 10:07:24.349031 RX Vref 24 -> 127, step: 1
8568 10:07:24.349487
8569 10:07:24.349853 RX Delay 11 -> 252, step: 4
8570 10:07:24.352468
8571 10:07:24.352923 Set Vref, RX VrefLevel [Byte0]: 24
8572 10:07:24.355954 [Byte1]: 24
8573 10:07:24.360520
8574 10:07:24.361107 Set Vref, RX VrefLevel [Byte0]: 25
8575 10:07:24.363351 [Byte1]: 25
8576 10:07:24.367951
8577 10:07:24.368509 Set Vref, RX VrefLevel [Byte0]: 26
8578 10:07:24.371496 [Byte1]: 26
8579 10:07:24.375247
8580 10:07:24.375709 Set Vref, RX VrefLevel [Byte0]: 27
8581 10:07:24.378867 [Byte1]: 27
8582 10:07:24.383440
8583 10:07:24.384147 Set Vref, RX VrefLevel [Byte0]: 28
8584 10:07:24.386388 [Byte1]: 28
8585 10:07:24.390719
8586 10:07:24.391225 Set Vref, RX VrefLevel [Byte0]: 29
8587 10:07:24.394057 [Byte1]: 29
8588 10:07:24.398365
8589 10:07:24.398968 Set Vref, RX VrefLevel [Byte0]: 30
8590 10:07:24.401450 [Byte1]: 30
8591 10:07:24.406188
8592 10:07:24.406746 Set Vref, RX VrefLevel [Byte0]: 31
8593 10:07:24.412938 [Byte1]: 31
8594 10:07:24.413500
8595 10:07:24.415608 Set Vref, RX VrefLevel [Byte0]: 32
8596 10:07:24.418919 [Byte1]: 32
8597 10:07:24.419487
8598 10:07:24.422538 Set Vref, RX VrefLevel [Byte0]: 33
8599 10:07:24.425549 [Byte1]: 33
8600 10:07:24.428760
8601 10:07:24.429327 Set Vref, RX VrefLevel [Byte0]: 34
8602 10:07:24.432202 [Byte1]: 34
8603 10:07:24.436340
8604 10:07:24.436903 Set Vref, RX VrefLevel [Byte0]: 35
8605 10:07:24.439804 [Byte1]: 35
8606 10:07:24.443868
8607 10:07:24.444326 Set Vref, RX VrefLevel [Byte0]: 36
8608 10:07:24.447379 [Byte1]: 36
8609 10:07:24.451822
8610 10:07:24.452351 Set Vref, RX VrefLevel [Byte0]: 37
8611 10:07:24.454545 [Byte1]: 37
8612 10:07:24.459225
8613 10:07:24.459798 Set Vref, RX VrefLevel [Byte0]: 38
8614 10:07:24.462819 [Byte1]: 38
8615 10:07:24.466673
8616 10:07:24.467160 Set Vref, RX VrefLevel [Byte0]: 39
8617 10:07:24.469762 [Byte1]: 39
8618 10:07:24.474608
8619 10:07:24.475211 Set Vref, RX VrefLevel [Byte0]: 40
8620 10:07:24.478019 [Byte1]: 40
8621 10:07:24.482098
8622 10:07:24.482556 Set Vref, RX VrefLevel [Byte0]: 41
8623 10:07:24.484995 [Byte1]: 41
8624 10:07:24.489983
8625 10:07:24.490570 Set Vref, RX VrefLevel [Byte0]: 42
8626 10:07:24.492861 [Byte1]: 42
8627 10:07:24.497148
8628 10:07:24.497707 Set Vref, RX VrefLevel [Byte0]: 43
8629 10:07:24.500657 [Byte1]: 43
8630 10:07:24.505160
8631 10:07:24.505791 Set Vref, RX VrefLevel [Byte0]: 44
8632 10:07:24.511318 [Byte1]: 44
8633 10:07:24.511886
8634 10:07:24.514322 Set Vref, RX VrefLevel [Byte0]: 45
8635 10:07:24.518104 [Byte1]: 45
8636 10:07:24.518563
8637 10:07:24.521247 Set Vref, RX VrefLevel [Byte0]: 46
8638 10:07:24.524702 [Byte1]: 46
8639 10:07:24.527953
8640 10:07:24.528513 Set Vref, RX VrefLevel [Byte0]: 47
8641 10:07:24.530750 [Byte1]: 47
8642 10:07:24.535925
8643 10:07:24.536487 Set Vref, RX VrefLevel [Byte0]: 48
8644 10:07:24.538521 [Byte1]: 48
8645 10:07:24.542899
8646 10:07:24.543460 Set Vref, RX VrefLevel [Byte0]: 49
8647 10:07:24.546326 [Byte1]: 49
8648 10:07:24.550821
8649 10:07:24.551402 Set Vref, RX VrefLevel [Byte0]: 50
8650 10:07:24.553879 [Byte1]: 50
8651 10:07:24.558212
8652 10:07:24.558771 Set Vref, RX VrefLevel [Byte0]: 51
8653 10:07:24.561819 [Byte1]: 51
8654 10:07:24.565978
8655 10:07:24.566540 Set Vref, RX VrefLevel [Byte0]: 52
8656 10:07:24.569050 [Byte1]: 52
8657 10:07:24.573423
8658 10:07:24.573984 Set Vref, RX VrefLevel [Byte0]: 53
8659 10:07:24.576616 [Byte1]: 53
8660 10:07:24.580971
8661 10:07:24.581580 Set Vref, RX VrefLevel [Byte0]: 54
8662 10:07:24.585139 [Byte1]: 54
8663 10:07:24.588847
8664 10:07:24.589410 Set Vref, RX VrefLevel [Byte0]: 55
8665 10:07:24.591719 [Byte1]: 55
8666 10:07:24.596041
8667 10:07:24.596592 Set Vref, RX VrefLevel [Byte0]: 56
8668 10:07:24.599373 [Byte1]: 56
8669 10:07:24.603673
8670 10:07:24.604223 Set Vref, RX VrefLevel [Byte0]: 57
8671 10:07:24.607731 [Byte1]: 57
8672 10:07:24.611532
8673 10:07:24.612082 Set Vref, RX VrefLevel [Byte0]: 58
8674 10:07:24.614984 [Byte1]: 58
8675 10:07:24.618735
8676 10:07:24.619236 Set Vref, RX VrefLevel [Byte0]: 59
8677 10:07:24.622419 [Byte1]: 59
8678 10:07:24.627052
8679 10:07:24.627606 Set Vref, RX VrefLevel [Byte0]: 60
8680 10:07:24.630075 [Byte1]: 60
8681 10:07:24.634962
8682 10:07:24.635512 Set Vref, RX VrefLevel [Byte0]: 61
8683 10:07:24.637683 [Byte1]: 61
8684 10:07:24.642097
8685 10:07:24.642654 Set Vref, RX VrefLevel [Byte0]: 62
8686 10:07:24.645054 [Byte1]: 62
8687 10:07:24.649827
8688 10:07:24.650689 Set Vref, RX VrefLevel [Byte0]: 63
8689 10:07:24.652670 [Byte1]: 63
8690 10:07:24.657531
8691 10:07:24.658082 Set Vref, RX VrefLevel [Byte0]: 64
8692 10:07:24.661043 [Byte1]: 64
8693 10:07:24.664735
8694 10:07:24.665287 Set Vref, RX VrefLevel [Byte0]: 65
8695 10:07:24.668283 [Byte1]: 65
8696 10:07:24.672456
8697 10:07:24.673009 Set Vref, RX VrefLevel [Byte0]: 66
8698 10:07:24.675733 [Byte1]: 66
8699 10:07:24.680121
8700 10:07:24.680676 Set Vref, RX VrefLevel [Byte0]: 67
8701 10:07:24.683460 [Byte1]: 67
8702 10:07:24.687475
8703 10:07:24.688039 Set Vref, RX VrefLevel [Byte0]: 68
8704 10:07:24.690815 [Byte1]: 68
8705 10:07:24.695261
8706 10:07:24.695822 Set Vref, RX VrefLevel [Byte0]: 69
8707 10:07:24.698198 [Byte1]: 69
8708 10:07:24.703249
8709 10:07:24.703854 Set Vref, RX VrefLevel [Byte0]: 70
8710 10:07:24.705883 [Byte1]: 70
8711 10:07:24.710464
8712 10:07:24.711076 Set Vref, RX VrefLevel [Byte0]: 71
8713 10:07:24.713951 [Byte1]: 71
8714 10:07:24.718093
8715 10:07:24.718560 Final RX Vref Byte 0 = 56 to rank0
8716 10:07:24.721257 Final RX Vref Byte 1 = 54 to rank0
8717 10:07:24.724735 Final RX Vref Byte 0 = 56 to rank1
8718 10:07:24.727925 Final RX Vref Byte 1 = 54 to rank1==
8719 10:07:24.731003 Dram Type= 6, Freq= 0, CH_1, rank 0
8720 10:07:24.737473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8721 10:07:24.738003 ==
8722 10:07:24.738398 DQS Delay:
8723 10:07:24.741179 DQS0 = 0, DQS1 = 0
8724 10:07:24.741638 DQM Delay:
8725 10:07:24.744293 DQM0 = 131, DQM1 = 123
8726 10:07:24.744750 DQ Delay:
8727 10:07:24.747253 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =130
8728 10:07:24.751140 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8729 10:07:24.754593 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8730 10:07:24.757360 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8731 10:07:24.757917
8732 10:07:24.758285
8733 10:07:24.758625
8734 10:07:24.761034 [DramC_TX_OE_Calibration] TA2
8735 10:07:24.764118 Original DQ_B0 (3 6) =30, OEN = 27
8736 10:07:24.767327 Original DQ_B1 (3 6) =30, OEN = 27
8737 10:07:24.770231 24, 0x0, End_B0=24 End_B1=24
8738 10:07:24.774002 25, 0x0, End_B0=25 End_B1=25
8739 10:07:24.774569 26, 0x0, End_B0=26 End_B1=26
8740 10:07:24.776873 27, 0x0, End_B0=27 End_B1=27
8741 10:07:24.780261 28, 0x0, End_B0=28 End_B1=28
8742 10:07:24.783698 29, 0x0, End_B0=29 End_B1=29
8743 10:07:24.786925 30, 0x0, End_B0=30 End_B1=30
8744 10:07:24.787487 31, 0x5151, End_B0=30 End_B1=30
8745 10:07:24.790259 Byte0 end_step=30 best_step=27
8746 10:07:24.793469 Byte1 end_step=30 best_step=27
8747 10:07:24.797029 Byte0 TX OE(2T, 0.5T) = (3, 3)
8748 10:07:24.800092 Byte1 TX OE(2T, 0.5T) = (3, 3)
8749 10:07:24.800657
8750 10:07:24.801025
8751 10:07:24.806277 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8752 10:07:24.809573 CH1 RK0: MR19=303, MR18=A0E
8753 10:07:24.816389 CH1_RK0: MR19=0x303, MR18=0xA0E, DQSOSC=402, MR23=63, INC=22, DEC=15
8754 10:07:24.816946
8755 10:07:24.819588 ----->DramcWriteLeveling(PI) begin...
8756 10:07:24.820059 ==
8757 10:07:24.823036 Dram Type= 6, Freq= 0, CH_1, rank 1
8758 10:07:24.826625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8759 10:07:24.827278 ==
8760 10:07:24.829843 Write leveling (Byte 0): 24 => 24
8761 10:07:24.832628 Write leveling (Byte 1): 28 => 28
8762 10:07:24.836230 DramcWriteLeveling(PI) end<-----
8763 10:07:24.836692
8764 10:07:24.837193 ==
8765 10:07:24.839373 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 10:07:24.846554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 10:07:24.847169 ==
8768 10:07:24.847547 [Gating] SW mode calibration
8769 10:07:24.856082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8770 10:07:24.859233 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8771 10:07:24.862397 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 10:07:24.869479 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 10:07:24.872595 1 4 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8774 10:07:24.876233 1 4 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
8775 10:07:24.882515 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 10:07:24.885730 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 10:07:24.889242 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 10:07:24.895371 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 10:07:24.898555 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 10:07:24.905692 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 10:07:24.908739 1 5 8 | B1->B0 | 3333 2424 | 0 0 | (0 1) (0 0)
8782 10:07:24.911904 1 5 12 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
8783 10:07:24.918470 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 10:07:24.922069 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 10:07:24.925213 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 10:07:24.931570 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 10:07:24.934769 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 10:07:24.938698 1 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8789 10:07:24.944887 1 6 8 | B1->B0 | 2b2b 4545 | 0 1 | (0 0) (0 0)
8790 10:07:24.948354 1 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8791 10:07:24.951664 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 10:07:24.958252 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 10:07:24.961324 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 10:07:24.964660 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 10:07:24.971402 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 10:07:24.974775 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8797 10:07:24.977662 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8798 10:07:24.984888 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8799 10:07:24.988660 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 10:07:24.991162 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 10:07:24.997347 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 10:07:25.000561 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 10:07:25.004113 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 10:07:25.010879 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 10:07:25.014345 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 10:07:25.017092 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 10:07:25.023828 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 10:07:25.027393 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 10:07:25.030390 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 10:07:25.037034 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 10:07:25.040018 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 10:07:25.043618 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 10:07:25.050156 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8814 10:07:25.053473 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8815 10:07:25.056579 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 10:07:25.060043 Total UI for P1: 0, mck2ui 16
8817 10:07:25.063368 best dqsien dly found for B0: ( 1, 9, 10)
8818 10:07:25.066878 Total UI for P1: 0, mck2ui 16
8819 10:07:25.069987 best dqsien dly found for B1: ( 1, 9, 12)
8820 10:07:25.073547 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8821 10:07:25.076713 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8822 10:07:25.077329
8823 10:07:25.082806 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8824 10:07:25.086563 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8825 10:07:25.089817 [Gating] SW calibration Done
8826 10:07:25.090381 ==
8827 10:07:25.092657 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 10:07:25.095953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 10:07:25.096518 ==
8830 10:07:25.096888 RX Vref Scan: 0
8831 10:07:25.099701
8832 10:07:25.100259 RX Vref 0 -> 0, step: 1
8833 10:07:25.100629
8834 10:07:25.102770 RX Delay 0 -> 252, step: 8
8835 10:07:25.105819 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8836 10:07:25.109586 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8837 10:07:25.116010 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8838 10:07:25.118944 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8839 10:07:25.122223 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8840 10:07:25.125748 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8841 10:07:25.129318 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8842 10:07:25.135304 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8843 10:07:25.138654 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8844 10:07:25.141653 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8845 10:07:25.144928 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8846 10:07:25.152150 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8847 10:07:25.155421 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8848 10:07:25.158476 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8849 10:07:25.161833 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8850 10:07:25.165063 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8851 10:07:25.168116 ==
8852 10:07:25.171659 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 10:07:25.174909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 10:07:25.175465 ==
8855 10:07:25.175836 DQS Delay:
8856 10:07:25.178416 DQS0 = 0, DQS1 = 0
8857 10:07:25.178916 DQM Delay:
8858 10:07:25.181650 DQM0 = 132, DQM1 = 128
8859 10:07:25.182211 DQ Delay:
8860 10:07:25.184787 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8861 10:07:25.188417 DQ4 =131, DQ5 =139, DQ6 =139, DQ7 =131
8862 10:07:25.191726 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8863 10:07:25.194585 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8864 10:07:25.195221
8865 10:07:25.195596
8866 10:07:25.198018 ==
8867 10:07:25.198572 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 10:07:25.204464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 10:07:25.205030 ==
8870 10:07:25.205401
8871 10:07:25.205743
8872 10:07:25.207410 TX Vref Scan disable
8873 10:07:25.207873 == TX Byte 0 ==
8874 10:07:25.211216 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8875 10:07:25.217440 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8876 10:07:25.217999 == TX Byte 1 ==
8877 10:07:25.224219 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8878 10:07:25.227454 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8879 10:07:25.227923 ==
8880 10:07:25.230632 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 10:07:25.234331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 10:07:25.234798 ==
8883 10:07:25.247460
8884 10:07:25.250937 TX Vref early break, caculate TX vref
8885 10:07:25.254021 TX Vref=16, minBit 0, minWin=23, winSum=384
8886 10:07:25.257530 TX Vref=18, minBit 0, minWin=23, winSum=391
8887 10:07:25.260381 TX Vref=20, minBit 0, minWin=24, winSum=399
8888 10:07:25.263725 TX Vref=22, minBit 0, minWin=24, winSum=408
8889 10:07:25.270629 TX Vref=24, minBit 0, minWin=23, winSum=413
8890 10:07:25.273585 TX Vref=26, minBit 0, minWin=25, winSum=425
8891 10:07:25.277169 TX Vref=28, minBit 5, minWin=25, winSum=427
8892 10:07:25.280356 TX Vref=30, minBit 1, minWin=24, winSum=422
8893 10:07:25.283306 TX Vref=32, minBit 5, minWin=24, winSum=408
8894 10:07:25.287170 TX Vref=34, minBit 5, minWin=23, winSum=402
8895 10:07:25.293557 [TxChooseVref] Worse bit 5, Min win 25, Win sum 427, Final Vref 28
8896 10:07:25.294160
8897 10:07:25.296673 Final TX Range 0 Vref 28
8898 10:07:25.297230
8899 10:07:25.297602 ==
8900 10:07:25.300269 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 10:07:25.303520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 10:07:25.304079 ==
8903 10:07:25.304452
8904 10:07:25.306525
8905 10:07:25.307124 TX Vref Scan disable
8906 10:07:25.313346 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8907 10:07:25.313905 == TX Byte 0 ==
8908 10:07:25.316557 u2DelayCellOfst[0]=15 cells (4 PI)
8909 10:07:25.320058 u2DelayCellOfst[1]=11 cells (3 PI)
8910 10:07:25.323016 u2DelayCellOfst[2]=0 cells (0 PI)
8911 10:07:25.326358 u2DelayCellOfst[3]=3 cells (1 PI)
8912 10:07:25.329467 u2DelayCellOfst[4]=7 cells (2 PI)
8913 10:07:25.333263 u2DelayCellOfst[5]=18 cells (5 PI)
8914 10:07:25.335991 u2DelayCellOfst[6]=18 cells (5 PI)
8915 10:07:25.339348 u2DelayCellOfst[7]=3 cells (1 PI)
8916 10:07:25.342925 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8917 10:07:25.346178 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8918 10:07:25.349119 == TX Byte 1 ==
8919 10:07:25.352690 u2DelayCellOfst[8]=0 cells (0 PI)
8920 10:07:25.355543 u2DelayCellOfst[9]=7 cells (2 PI)
8921 10:07:25.359155 u2DelayCellOfst[10]=15 cells (4 PI)
8922 10:07:25.362546 u2DelayCellOfst[11]=7 cells (2 PI)
8923 10:07:25.365587 u2DelayCellOfst[12]=18 cells (5 PI)
8924 10:07:25.366049 u2DelayCellOfst[13]=18 cells (5 PI)
8925 10:07:25.368985 u2DelayCellOfst[14]=22 cells (6 PI)
8926 10:07:25.372301 u2DelayCellOfst[15]=22 cells (6 PI)
8927 10:07:25.378922 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8928 10:07:25.382144 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8929 10:07:25.385524 DramC Write-DBI on
8930 10:07:25.386076 ==
8931 10:07:25.389018 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 10:07:25.392135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 10:07:25.392695 ==
8934 10:07:25.393063
8935 10:07:25.393406
8936 10:07:25.395128 TX Vref Scan disable
8937 10:07:25.395596 == TX Byte 0 ==
8938 10:07:25.402069 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8939 10:07:25.402628 == TX Byte 1 ==
8940 10:07:25.405085 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8941 10:07:25.408660 DramC Write-DBI off
8942 10:07:25.409211
8943 10:07:25.409579 [DATLAT]
8944 10:07:25.411462 Freq=1600, CH1 RK1
8945 10:07:25.411921
8946 10:07:25.412289 DATLAT Default: 0xf
8947 10:07:25.415240 0, 0xFFFF, sum = 0
8948 10:07:25.418184 1, 0xFFFF, sum = 0
8949 10:07:25.418653 2, 0xFFFF, sum = 0
8950 10:07:25.421298 3, 0xFFFF, sum = 0
8951 10:07:25.421765 4, 0xFFFF, sum = 0
8952 10:07:25.425270 5, 0xFFFF, sum = 0
8953 10:07:25.425861 6, 0xFFFF, sum = 0
8954 10:07:25.428167 7, 0xFFFF, sum = 0
8955 10:07:25.428636 8, 0xFFFF, sum = 0
8956 10:07:25.431449 9, 0xFFFF, sum = 0
8957 10:07:25.431916 10, 0xFFFF, sum = 0
8958 10:07:25.434888 11, 0xFFFF, sum = 0
8959 10:07:25.435462 12, 0xFFFF, sum = 0
8960 10:07:25.438109 13, 0x8FFF, sum = 0
8961 10:07:25.438680 14, 0x0, sum = 1
8962 10:07:25.441762 15, 0x0, sum = 2
8963 10:07:25.442329 16, 0x0, sum = 3
8964 10:07:25.444842 17, 0x0, sum = 4
8965 10:07:25.445470 best_step = 15
8966 10:07:25.445847
8967 10:07:25.446188 ==
8968 10:07:25.448233 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 10:07:25.454588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 10:07:25.455205 ==
8971 10:07:25.455582 RX Vref Scan: 0
8972 10:07:25.455925
8973 10:07:25.457789 RX Vref 0 -> 0, step: 1
8974 10:07:25.458245
8975 10:07:25.461312 RX Delay 11 -> 252, step: 4
8976 10:07:25.464310 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8977 10:07:25.467770 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8978 10:07:25.471394 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8979 10:07:25.477664 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8980 10:07:25.481129 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8981 10:07:25.484265 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8982 10:07:25.487401 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8983 10:07:25.491095 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8984 10:07:25.498015 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8985 10:07:25.500993 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8986 10:07:25.504300 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8987 10:07:25.507562 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8988 10:07:25.513909 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8989 10:07:25.516776 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8990 10:07:25.520383 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8991 10:07:25.523511 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8992 10:07:25.523969 ==
8993 10:07:25.527196 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 10:07:25.533973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 10:07:25.534540 ==
8996 10:07:25.534958 DQS Delay:
8997 10:07:25.537099 DQS0 = 0, DQS1 = 0
8998 10:07:25.537659 DQM Delay:
8999 10:07:25.538027 DQM0 = 129, DQM1 = 125
9000 10:07:25.539952 DQ Delay:
9001 10:07:25.544123 DQ0 =134, DQ1 =128, DQ2 =116, DQ3 =124
9002 10:07:25.546743 DQ4 =126, DQ5 =140, DQ6 =140, DQ7 =126
9003 10:07:25.550318 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9004 10:07:25.553676 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9005 10:07:25.554266
9006 10:07:25.554642
9007 10:07:25.555090
9008 10:07:25.556468 [DramC_TX_OE_Calibration] TA2
9009 10:07:25.559778 Original DQ_B0 (3 6) =30, OEN = 27
9010 10:07:25.563090 Original DQ_B1 (3 6) =30, OEN = 27
9011 10:07:25.566281 24, 0x0, End_B0=24 End_B1=24
9012 10:07:25.569840 25, 0x0, End_B0=25 End_B1=25
9013 10:07:25.570408 26, 0x0, End_B0=26 End_B1=26
9014 10:07:25.572822 27, 0x0, End_B0=27 End_B1=27
9015 10:07:25.576301 28, 0x0, End_B0=28 End_B1=28
9016 10:07:25.580033 29, 0x0, End_B0=29 End_B1=29
9017 10:07:25.580604 30, 0x0, End_B0=30 End_B1=30
9018 10:07:25.582940 31, 0x4141, End_B0=30 End_B1=30
9019 10:07:25.586879 Byte0 end_step=30 best_step=27
9020 10:07:25.590266 Byte1 end_step=30 best_step=27
9021 10:07:25.593092 Byte0 TX OE(2T, 0.5T) = (3, 3)
9022 10:07:25.596131 Byte1 TX OE(2T, 0.5T) = (3, 3)
9023 10:07:25.596619
9024 10:07:25.596987
9025 10:07:25.603020 [DQSOSCAuto] RK1, (LSB)MR18= 0x111d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9026 10:07:25.606625 CH1 RK1: MR19=303, MR18=111D
9027 10:07:25.612653 CH1_RK1: MR19=0x303, MR18=0x111D, DQSOSC=395, MR23=63, INC=23, DEC=15
9028 10:07:25.616438 [RxdqsGatingPostProcess] freq 1600
9029 10:07:25.619453 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9030 10:07:25.622695 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 10:07:25.626040 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 10:07:25.629688 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 10:07:25.632795 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 10:07:25.636020 best DQS0 dly(2T, 0.5T) = (1, 1)
9035 10:07:25.639523 best DQS1 dly(2T, 0.5T) = (1, 1)
9036 10:07:25.642923 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9037 10:07:25.645866 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9038 10:07:25.649242 Pre-setting of DQS Precalculation
9039 10:07:25.652232 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9040 10:07:25.662244 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9041 10:07:25.669074 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9042 10:07:25.669645
9043 10:07:25.670019
9044 10:07:25.671921 [Calibration Summary] 3200 Mbps
9045 10:07:25.672384 CH 0, Rank 0
9046 10:07:25.675476 SW Impedance : PASS
9047 10:07:25.675937 DUTY Scan : NO K
9048 10:07:25.678914 ZQ Calibration : PASS
9049 10:07:25.682092 Jitter Meter : NO K
9050 10:07:25.682667 CBT Training : PASS
9051 10:07:25.685468 Write leveling : PASS
9052 10:07:25.688799 RX DQS gating : PASS
9053 10:07:25.689372 RX DQ/DQS(RDDQC) : PASS
9054 10:07:25.691855 TX DQ/DQS : PASS
9055 10:07:25.695397 RX DATLAT : PASS
9056 10:07:25.695990 RX DQ/DQS(Engine): PASS
9057 10:07:25.698876 TX OE : PASS
9058 10:07:25.699458 All Pass.
9059 10:07:25.699949
9060 10:07:25.702041 CH 0, Rank 1
9061 10:07:25.702615 SW Impedance : PASS
9062 10:07:25.704890 DUTY Scan : NO K
9063 10:07:25.708349 ZQ Calibration : PASS
9064 10:07:25.708917 Jitter Meter : NO K
9065 10:07:25.711710 CBT Training : PASS
9066 10:07:25.714783 Write leveling : PASS
9067 10:07:25.715379 RX DQS gating : PASS
9068 10:07:25.718244 RX DQ/DQS(RDDQC) : PASS
9069 10:07:25.721830 TX DQ/DQS : PASS
9070 10:07:25.722395 RX DATLAT : PASS
9071 10:07:25.724912 RX DQ/DQS(Engine): PASS
9072 10:07:25.725467 TX OE : PASS
9073 10:07:25.728542 All Pass.
9074 10:07:25.729096
9075 10:07:25.729464 CH 1, Rank 0
9076 10:07:25.731561 SW Impedance : PASS
9077 10:07:25.732023 DUTY Scan : NO K
9078 10:07:25.734729 ZQ Calibration : PASS
9079 10:07:25.739020 Jitter Meter : NO K
9080 10:07:25.739575 CBT Training : PASS
9081 10:07:25.741589 Write leveling : PASS
9082 10:07:25.744998 RX DQS gating : PASS
9083 10:07:25.745551 RX DQ/DQS(RDDQC) : PASS
9084 10:07:25.748092 TX DQ/DQS : PASS
9085 10:07:25.751391 RX DATLAT : PASS
9086 10:07:25.751852 RX DQ/DQS(Engine): PASS
9087 10:07:25.754420 TX OE : PASS
9088 10:07:25.754925 All Pass.
9089 10:07:25.755298
9090 10:07:25.757819 CH 1, Rank 1
9091 10:07:25.758376 SW Impedance : PASS
9092 10:07:25.761450 DUTY Scan : NO K
9093 10:07:25.764482 ZQ Calibration : PASS
9094 10:07:25.764943 Jitter Meter : NO K
9095 10:07:25.767499 CBT Training : PASS
9096 10:07:25.771048 Write leveling : PASS
9097 10:07:25.771625 RX DQS gating : PASS
9098 10:07:25.774791 RX DQ/DQS(RDDQC) : PASS
9099 10:07:25.777779 TX DQ/DQS : PASS
9100 10:07:25.778242 RX DATLAT : PASS
9101 10:07:25.781091 RX DQ/DQS(Engine): PASS
9102 10:07:25.784073 TX OE : PASS
9103 10:07:25.784536 All Pass.
9104 10:07:25.784902
9105 10:07:25.785249 DramC Write-DBI on
9106 10:07:25.787331 PER_BANK_REFRESH: Hybrid Mode
9107 10:07:25.790784 TX_TRACKING: ON
9108 10:07:25.797613 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9109 10:07:25.808042 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9110 10:07:25.813775 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9111 10:07:25.817479 [FAST_K] Save calibration result to emmc
9112 10:07:25.820822 sync common calibartion params.
9113 10:07:25.823585 sync cbt_mode0:1, 1:1
9114 10:07:25.824044 dram_init: ddr_geometry: 2
9115 10:07:25.827608 dram_init: ddr_geometry: 2
9116 10:07:25.830339 dram_init: ddr_geometry: 2
9117 10:07:25.833773 0:dram_rank_size:100000000
9118 10:07:25.834336 1:dram_rank_size:100000000
9119 10:07:25.840260 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9120 10:07:25.843386 DFS_SHUFFLE_HW_MODE: ON
9121 10:07:25.846751 dramc_set_vcore_voltage set vcore to 725000
9122 10:07:25.847233 Read voltage for 1600, 0
9123 10:07:25.850263 Vio18 = 0
9124 10:07:25.850812 Vcore = 725000
9125 10:07:25.851225 Vdram = 0
9126 10:07:25.853597 Vddq = 0
9127 10:07:25.854078 Vmddr = 0
9128 10:07:25.856778 switch to 3200 Mbps bootup
9129 10:07:25.857240 [DramcRunTimeConfig]
9130 10:07:25.860196 PHYPLL
9131 10:07:25.860747 DPM_CONTROL_AFTERK: ON
9132 10:07:25.863192 PER_BANK_REFRESH: ON
9133 10:07:25.866601 REFRESH_OVERHEAD_REDUCTION: ON
9134 10:07:25.867195 CMD_PICG_NEW_MODE: OFF
9135 10:07:25.870226 XRTWTW_NEW_MODE: ON
9136 10:07:25.870779 XRTRTR_NEW_MODE: ON
9137 10:07:25.872997 TX_TRACKING: ON
9138 10:07:25.873456 RDSEL_TRACKING: OFF
9139 10:07:25.876762 DQS Precalculation for DVFS: ON
9140 10:07:25.879471 RX_TRACKING: OFF
9141 10:07:25.880080 HW_GATING DBG: ON
9142 10:07:25.883053 ZQCS_ENABLE_LP4: ON
9143 10:07:25.883510 RX_PICG_NEW_MODE: ON
9144 10:07:25.886164 TX_PICG_NEW_MODE: ON
9145 10:07:25.886625 ENABLE_RX_DCM_DPHY: ON
9146 10:07:25.889777 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9147 10:07:25.892741 DUMMY_READ_FOR_TRACKING: OFF
9148 10:07:25.895960 !!! SPM_CONTROL_AFTERK: OFF
9149 10:07:25.899434 !!! SPM could not control APHY
9150 10:07:25.899904 IMPEDANCE_TRACKING: ON
9151 10:07:25.902714 TEMP_SENSOR: ON
9152 10:07:25.903295 HW_SAVE_FOR_SR: OFF
9153 10:07:25.905795 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9154 10:07:25.908864 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9155 10:07:25.912736 Read ODT Tracking: ON
9156 10:07:25.915711 Refresh Rate DeBounce: ON
9157 10:07:25.916168 DFS_NO_QUEUE_FLUSH: ON
9158 10:07:25.918963 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9159 10:07:25.922324 ENABLE_DFS_RUNTIME_MRW: OFF
9160 10:07:25.925854 DDR_RESERVE_NEW_MODE: ON
9161 10:07:25.926408 MR_CBT_SWITCH_FREQ: ON
9162 10:07:25.928786 =========================
9163 10:07:25.948189 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9164 10:07:25.951705 dram_init: ddr_geometry: 2
9165 10:07:25.969874 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9166 10:07:25.973526 dram_init: dram init end (result: 0)
9167 10:07:25.979568 DRAM-K: Full calibration passed in 24590 msecs
9168 10:07:25.983081 MRC: failed to locate region type 0.
9169 10:07:25.983632 DRAM rank0 size:0x100000000,
9170 10:07:25.986679 DRAM rank1 size=0x100000000
9171 10:07:25.996160 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9172 10:07:26.002571 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9173 10:07:26.009073 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9174 10:07:26.019264 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9175 10:07:26.019758 DRAM rank0 size:0x100000000,
9176 10:07:26.022951 DRAM rank1 size=0x100000000
9177 10:07:26.023440 CBMEM:
9178 10:07:26.025761 IMD: root @ 0xfffff000 254 entries.
9179 10:07:26.028782 IMD: root @ 0xffffec00 62 entries.
9180 10:07:26.032246 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9181 10:07:26.039236 WARNING: RO_VPD is uninitialized or empty.
9182 10:07:26.042175 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9183 10:07:26.050062 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9184 10:07:26.062938 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9185 10:07:26.074178 BS: romstage times (exec / console): total (unknown) / 24056 ms
9186 10:07:26.074743
9187 10:07:26.075155
9188 10:07:26.084017 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9189 10:07:26.087488 ARM64: Exception handlers installed.
9190 10:07:26.090614 ARM64: Testing exception
9191 10:07:26.093889 ARM64: Done test exception
9192 10:07:26.094452 Enumerating buses...
9193 10:07:26.096985 Show all devs... Before device enumeration.
9194 10:07:26.100273 Root Device: enabled 1
9195 10:07:26.103790 CPU_CLUSTER: 0: enabled 1
9196 10:07:26.104300 CPU: 00: enabled 1
9197 10:07:26.107446 Compare with tree...
9198 10:07:26.108006 Root Device: enabled 1
9199 10:07:26.110219 CPU_CLUSTER: 0: enabled 1
9200 10:07:26.113421 CPU: 00: enabled 1
9201 10:07:26.113884 Root Device scanning...
9202 10:07:26.116742 scan_static_bus for Root Device
9203 10:07:26.120241 CPU_CLUSTER: 0 enabled
9204 10:07:26.123383 scan_static_bus for Root Device done
9205 10:07:26.126868 scan_bus: bus Root Device finished in 8 msecs
9206 10:07:26.127433 done
9207 10:07:26.133315 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9208 10:07:26.136966 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9209 10:07:26.143220 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9210 10:07:26.149760 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9211 10:07:26.150322 Allocating resources...
9212 10:07:26.153402 Reading resources...
9213 10:07:26.156344 Root Device read_resources bus 0 link: 0
9214 10:07:26.159497 DRAM rank0 size:0x100000000,
9215 10:07:26.159960 DRAM rank1 size=0x100000000
9216 10:07:26.166431 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9217 10:07:26.167036 CPU: 00 missing read_resources
9218 10:07:26.172731 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9219 10:07:26.176528 Root Device read_resources bus 0 link: 0 done
9220 10:07:26.179375 Done reading resources.
9221 10:07:26.182674 Show resources in subtree (Root Device)...After reading.
9222 10:07:26.186444 Root Device child on link 0 CPU_CLUSTER: 0
9223 10:07:26.189315 CPU_CLUSTER: 0 child on link 0 CPU: 00
9224 10:07:26.199441 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9225 10:07:26.200007 CPU: 00
9226 10:07:26.205882 Root Device assign_resources, bus 0 link: 0
9227 10:07:26.209334 CPU_CLUSTER: 0 missing set_resources
9228 10:07:26.212402 Root Device assign_resources, bus 0 link: 0 done
9229 10:07:26.212873 Done setting resources.
9230 10:07:26.218792 Show resources in subtree (Root Device)...After assigning values.
9231 10:07:26.222204 Root Device child on link 0 CPU_CLUSTER: 0
9232 10:07:26.228841 CPU_CLUSTER: 0 child on link 0 CPU: 00
9233 10:07:26.235294 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9234 10:07:26.238455 CPU: 00
9235 10:07:26.238962 Done allocating resources.
9236 10:07:26.245029 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9237 10:07:26.245690 Enabling resources...
9238 10:07:26.248636 done.
9239 10:07:26.251687 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9240 10:07:26.255195 Initializing devices...
9241 10:07:26.255659 Root Device init
9242 10:07:26.258608 init hardware done!
9243 10:07:26.259137 0x00000018: ctrlr->caps
9244 10:07:26.262100 52.000 MHz: ctrlr->f_max
9245 10:07:26.265224 0.400 MHz: ctrlr->f_min
9246 10:07:26.268437 0x40ff8080: ctrlr->voltages
9247 10:07:26.269004 sclk: 390625
9248 10:07:26.269379 Bus Width = 1
9249 10:07:26.271746 sclk: 390625
9250 10:07:26.272300 Bus Width = 1
9251 10:07:26.274805 Early init status = 3
9252 10:07:26.278256 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9253 10:07:26.281552 in-header: 03 fc 00 00 01 00 00 00
9254 10:07:26.284475 in-data: 00
9255 10:07:26.288291 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9256 10:07:26.293072 in-header: 03 fd 00 00 00 00 00 00
9257 10:07:26.296088 in-data:
9258 10:07:26.299318 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9259 10:07:26.303485 in-header: 03 fc 00 00 01 00 00 00
9260 10:07:26.306520 in-data: 00
9261 10:07:26.309592 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9262 10:07:26.314777 in-header: 03 fd 00 00 00 00 00 00
9263 10:07:26.318135 in-data:
9264 10:07:26.321229 [SSUSB] Setting up USB HOST controller...
9265 10:07:26.324747 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9266 10:07:26.327770 [SSUSB] phy power-on done.
9267 10:07:26.331288 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9268 10:07:26.338034 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9269 10:07:26.341342 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9270 10:07:26.347999 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9271 10:07:26.354519 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9272 10:07:26.361010 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9273 10:07:26.367409 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9274 10:07:26.374268 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9275 10:07:26.377485 SPM: binary array size = 0x9dc
9276 10:07:26.380389 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9277 10:07:26.387315 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9278 10:07:26.394171 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9279 10:07:26.400534 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9280 10:07:26.403886 configure_display: Starting display init
9281 10:07:26.438030 anx7625_power_on_init: Init interface.
9282 10:07:26.441593 anx7625_disable_pd_protocol: Disabled PD feature.
9283 10:07:26.444540 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9284 10:07:26.472495 anx7625_start_dp_work: Secure OCM version=00
9285 10:07:26.475741 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9286 10:07:26.490935 sp_tx_get_edid_block: EDID Block = 1
9287 10:07:26.593099 Extracted contents:
9288 10:07:26.596671 header: 00 ff ff ff ff ff ff 00
9289 10:07:26.599652 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9290 10:07:26.603126 version: 01 04
9291 10:07:26.606225 basic params: 95 1f 11 78 0a
9292 10:07:26.609667 chroma info: 76 90 94 55 54 90 27 21 50 54
9293 10:07:26.612841 established: 00 00 00
9294 10:07:26.619151 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9295 10:07:26.625835 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9296 10:07:26.629870 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9297 10:07:26.635793 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9298 10:07:26.642959 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9299 10:07:26.645804 extensions: 00
9300 10:07:26.646255 checksum: fb
9301 10:07:26.646615
9302 10:07:26.652013 Manufacturer: IVO Model 57d Serial Number 0
9303 10:07:26.652467 Made week 0 of 2020
9304 10:07:26.655359 EDID version: 1.4
9305 10:07:26.655812 Digital display
9306 10:07:26.658711 6 bits per primary color channel
9307 10:07:26.662057 DisplayPort interface
9308 10:07:26.662510 Maximum image size: 31 cm x 17 cm
9309 10:07:26.665455 Gamma: 220%
9310 10:07:26.666033 Check DPMS levels
9311 10:07:26.672059 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9312 10:07:26.675593 First detailed timing is preferred timing
9313 10:07:26.678794 Established timings supported:
9314 10:07:26.679286 Standard timings supported:
9315 10:07:26.681986 Detailed timings
9316 10:07:26.685054 Hex of detail: 383680a07038204018303c0035ae10000019
9317 10:07:26.691594 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9318 10:07:26.695257 0780 0798 07c8 0820 hborder 0
9319 10:07:26.698287 0438 043b 0447 0458 vborder 0
9320 10:07:26.702147 -hsync -vsync
9321 10:07:26.702693 Did detailed timing
9322 10:07:26.708526 Hex of detail: 000000000000000000000000000000000000
9323 10:07:26.711420 Manufacturer-specified data, tag 0
9324 10:07:26.715124 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9325 10:07:26.718257 ASCII string: InfoVision
9326 10:07:26.721682 Hex of detail: 000000fe00523134304e574635205248200a
9327 10:07:26.724910 ASCII string: R140NWF5 RH
9328 10:07:26.725362 Checksum
9329 10:07:26.727824 Checksum: 0xfb (valid)
9330 10:07:26.731581 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9331 10:07:26.734657 DSI data_rate: 832800000 bps
9332 10:07:26.741480 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9333 10:07:26.744484 anx7625_parse_edid: pixelclock(138800).
9334 10:07:26.747843 hactive(1920), hsync(48), hfp(24), hbp(88)
9335 10:07:26.751244 vactive(1080), vsync(12), vfp(3), vbp(17)
9336 10:07:26.754042 anx7625_dsi_config: config dsi.
9337 10:07:26.760941 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9338 10:07:26.775494 anx7625_dsi_config: success to config DSI
9339 10:07:26.778777 anx7625_dp_start: MIPI phy setup OK.
9340 10:07:26.782240 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9341 10:07:26.785091 mtk_ddp_mode_set invalid vrefresh 60
9342 10:07:26.788622 main_disp_path_setup
9343 10:07:26.789179 ovl_layer_smi_id_en
9344 10:07:26.791782 ovl_layer_smi_id_en
9345 10:07:26.792237 ccorr_config
9346 10:07:26.792595 aal_config
9347 10:07:26.795022 gamma_config
9348 10:07:26.795590 postmask_config
9349 10:07:26.798086 dither_config
9350 10:07:26.801509 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9351 10:07:26.807978 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9352 10:07:26.811492 Root Device init finished in 552 msecs
9353 10:07:26.815074 CPU_CLUSTER: 0 init
9354 10:07:26.821310 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9355 10:07:26.827726 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9356 10:07:26.828288 APU_MBOX 0x190000b0 = 0x10001
9357 10:07:26.831144 APU_MBOX 0x190001b0 = 0x10001
9358 10:07:26.834313 APU_MBOX 0x190005b0 = 0x10001
9359 10:07:26.837637 APU_MBOX 0x190006b0 = 0x10001
9360 10:07:26.844390 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9361 10:07:26.854486 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9362 10:07:26.866477 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9363 10:07:26.873056 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9364 10:07:26.885067 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9365 10:07:26.894354 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9366 10:07:26.897384 CPU_CLUSTER: 0 init finished in 81 msecs
9367 10:07:26.901033 Devices initialized
9368 10:07:26.904223 Show all devs... After init.
9369 10:07:26.904807 Root Device: enabled 1
9370 10:07:26.907127 CPU_CLUSTER: 0: enabled 1
9371 10:07:26.910925 CPU: 00: enabled 1
9372 10:07:26.913580 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9373 10:07:26.916924 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9374 10:07:26.920486 ELOG: NV offset 0x57f000 size 0x1000
9375 10:07:26.927252 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9376 10:07:26.933996 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9377 10:07:26.936864 ELOG: Event(17) added with size 13 at 2023-06-10 10:07:29 UTC
9378 10:07:26.943362 out: cmd=0x121: 03 db 21 01 00 00 00 00
9379 10:07:26.946688 in-header: 03 46 00 00 2c 00 00 00
9380 10:07:26.957166 in-data: 18 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9381 10:07:26.963337 ELOG: Event(A1) added with size 10 at 2023-06-10 10:07:29 UTC
9382 10:07:26.969994 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9383 10:07:26.976917 ELOG: Event(A0) added with size 9 at 2023-06-10 10:07:29 UTC
9384 10:07:26.979658 elog_add_boot_reason: Logged dev mode boot
9385 10:07:26.986428 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9386 10:07:26.987221 Finalize devices...
9387 10:07:26.989612 Devices finalized
9388 10:07:26.992948 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9389 10:07:26.996361 Writing coreboot table at 0xffe64000
9390 10:07:26.999294 0. 000000000010a000-0000000000113fff: RAMSTAGE
9391 10:07:27.006609 1. 0000000040000000-00000000400fffff: RAM
9392 10:07:27.009434 2. 0000000040100000-000000004032afff: RAMSTAGE
9393 10:07:27.013175 3. 000000004032b000-00000000545fffff: RAM
9394 10:07:27.016442 4. 0000000054600000-000000005465ffff: BL31
9395 10:07:27.019503 5. 0000000054660000-00000000ffe63fff: RAM
9396 10:07:27.025982 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9397 10:07:27.029414 7. 0000000100000000-000000023fffffff: RAM
9398 10:07:27.032506 Passing 5 GPIOs to payload:
9399 10:07:27.036186 NAME | PORT | POLARITY | VALUE
9400 10:07:27.042457 EC in RW | 0x000000aa | low | undefined
9401 10:07:27.046025 EC interrupt | 0x00000005 | low | undefined
9402 10:07:27.052051 TPM interrupt | 0x000000ab | high | undefined
9403 10:07:27.055772 SD card detect | 0x00000011 | high | undefined
9404 10:07:27.058980 speaker enable | 0x00000093 | high | undefined
9405 10:07:27.062064 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9406 10:07:27.065710 in-header: 03 f9 00 00 02 00 00 00
9407 10:07:27.068769 in-data: 02 00
9408 10:07:27.072275 ADC[4]: Raw value=894821 ID=7
9409 10:07:27.075931 ADC[3]: Raw value=213440 ID=1
9410 10:07:27.076486 RAM Code: 0x71
9411 10:07:27.078588 ADC[6]: Raw value=75092 ID=0
9412 10:07:27.082182 ADC[5]: Raw value=212700 ID=1
9413 10:07:27.082647 SKU Code: 0x1
9414 10:07:27.088668 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9415 10:07:27.089228 coreboot table: 964 bytes.
9416 10:07:27.091908 IMD ROOT 0. 0xfffff000 0x00001000
9417 10:07:27.095352 IMD SMALL 1. 0xffffe000 0x00001000
9418 10:07:27.098436 RO MCACHE 2. 0xffffc000 0x00001104
9419 10:07:27.101441 CONSOLE 3. 0xfff7c000 0x00080000
9420 10:07:27.105035 FMAP 4. 0xfff7b000 0x00000452
9421 10:07:27.108806 TIME STAMP 5. 0xfff7a000 0x00000910
9422 10:07:27.111654 VBOOT WORK 6. 0xfff66000 0x00014000
9423 10:07:27.115281 RAMOOPS 7. 0xffe66000 0x00100000
9424 10:07:27.118238 COREBOOT 8. 0xffe64000 0x00002000
9425 10:07:27.121947 IMD small region:
9426 10:07:27.124979 IMD ROOT 0. 0xffffec00 0x00000400
9427 10:07:27.128580 VPD 1. 0xffffeba0 0x0000004c
9428 10:07:27.131410 MMC STATUS 2. 0xffffeb80 0x00000004
9429 10:07:27.138204 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9430 10:07:27.139003 Probing TPM: done!
9431 10:07:27.145104 Connected to device vid:did:rid of 1ae0:0028:00
9432 10:07:27.152006 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9433 10:07:27.155366 Initialized TPM device CR50 revision 0
9434 10:07:27.158302 Checking cr50 for pending updates
9435 10:07:27.163600 Reading cr50 TPM mode
9436 10:07:27.172165 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9437 10:07:27.178991 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9438 10:07:27.218997 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9439 10:07:27.222565 Checking segment from ROM address 0x40100000
9440 10:07:27.225521 Checking segment from ROM address 0x4010001c
9441 10:07:27.231637 Loading segment from ROM address 0x40100000
9442 10:07:27.232096 code (compression=0)
9443 10:07:27.242170 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9444 10:07:27.248998 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9445 10:07:27.249565 it's not compressed!
9446 10:07:27.255160 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9447 10:07:27.261742 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9448 10:07:27.279330 Loading segment from ROM address 0x4010001c
9449 10:07:27.279890 Entry Point 0x80000000
9450 10:07:27.282483 Loaded segments
9451 10:07:27.286054 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9452 10:07:27.292700 Jumping to boot code at 0x80000000(0xffe64000)
9453 10:07:27.299526 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9454 10:07:27.305711 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9455 10:07:27.313861 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9456 10:07:27.316822 Checking segment from ROM address 0x40100000
9457 10:07:27.320195 Checking segment from ROM address 0x4010001c
9458 10:07:27.326787 Loading segment from ROM address 0x40100000
9459 10:07:27.327365 code (compression=1)
9460 10:07:27.333631 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9461 10:07:27.343623 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9462 10:07:27.344188 using LZMA
9463 10:07:27.352571 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9464 10:07:27.358880 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9465 10:07:27.361783 Loading segment from ROM address 0x4010001c
9466 10:07:27.362245 Entry Point 0x54601000
9467 10:07:27.365540 Loaded segments
9468 10:07:27.368584 NOTICE: MT8192 bl31_setup
9469 10:07:27.375501 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9470 10:07:27.379545 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9471 10:07:27.382352 WARNING: region 0:
9472 10:07:27.386198 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 10:07:27.386763 WARNING: region 1:
9474 10:07:27.392439 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9475 10:07:27.395705 WARNING: region 2:
9476 10:07:27.398982 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9477 10:07:27.402128 WARNING: region 3:
9478 10:07:27.405855 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9479 10:07:27.408502 WARNING: region 4:
9480 10:07:27.415320 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9481 10:07:27.415888 WARNING: region 5:
9482 10:07:27.418503 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 10:07:27.421865 WARNING: region 6:
9484 10:07:27.425139 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 10:07:27.428943 WARNING: region 7:
9486 10:07:27.431892 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 10:07:27.439023 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9488 10:07:27.442778 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9489 10:07:27.445145 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9490 10:07:27.452043 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9491 10:07:27.455397 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9492 10:07:27.461946 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9493 10:07:27.465555 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9494 10:07:27.468281 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9495 10:07:27.475091 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9496 10:07:27.478631 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9497 10:07:27.482081 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9498 10:07:27.488349 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9499 10:07:27.491518 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9500 10:07:27.498724 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9501 10:07:27.501516 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9502 10:07:27.505028 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9503 10:07:27.511486 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9504 10:07:27.514981 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9505 10:07:27.521699 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9506 10:07:27.524686 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9507 10:07:27.527843 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9508 10:07:27.534274 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9509 10:07:27.537795 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9510 10:07:27.544175 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9511 10:07:27.547952 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9512 10:07:27.551114 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9513 10:07:27.557866 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9514 10:07:27.560987 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9515 10:07:27.567771 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9516 10:07:27.570980 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9517 10:07:27.574496 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9518 10:07:27.581034 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9519 10:07:27.584338 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9520 10:07:27.587387 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9521 10:07:27.590453 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9522 10:07:27.597617 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9523 10:07:27.600496 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9524 10:07:27.604391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9525 10:07:27.607581 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9526 10:07:27.614278 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9527 10:07:27.617316 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9528 10:07:27.620901 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9529 10:07:27.627272 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9530 10:07:27.630770 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9531 10:07:27.633992 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9532 10:07:27.637146 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9533 10:07:27.643653 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9534 10:07:27.646797 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9535 10:07:27.651026 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9536 10:07:27.656863 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9537 10:07:27.660267 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9538 10:07:27.666997 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9539 10:07:27.670423 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9540 10:07:27.673856 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9541 10:07:27.680330 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9542 10:07:27.683459 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9543 10:07:27.690330 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9544 10:07:27.693443 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9545 10:07:27.700062 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9546 10:07:27.703481 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9547 10:07:27.710397 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9548 10:07:27.713659 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9549 10:07:27.716548 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9550 10:07:27.723610 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9551 10:07:27.726960 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9552 10:07:27.733208 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9553 10:07:27.736264 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9554 10:07:27.743042 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9555 10:07:27.746432 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9556 10:07:27.753036 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9557 10:07:27.756342 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9558 10:07:27.759642 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9559 10:07:27.766370 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9560 10:07:27.769453 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9561 10:07:27.776575 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9562 10:07:27.779612 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9563 10:07:27.785782 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9564 10:07:27.789727 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9565 10:07:27.796286 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9566 10:07:27.799390 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9567 10:07:27.802937 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9568 10:07:27.809255 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9569 10:07:27.812749 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9570 10:07:27.819590 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9571 10:07:27.822309 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9572 10:07:27.829465 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9573 10:07:27.832414 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9574 10:07:27.835758 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9575 10:07:27.842333 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9576 10:07:27.845609 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9577 10:07:27.852465 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9578 10:07:27.855941 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9579 10:07:27.862250 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9580 10:07:27.865628 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9581 10:07:27.872120 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9582 10:07:27.875009 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9583 10:07:27.878481 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9584 10:07:27.885137 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9585 10:07:27.889044 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9586 10:07:27.892208 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9587 10:07:27.895367 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9588 10:07:27.901994 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9589 10:07:27.905692 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9590 10:07:27.911825 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9591 10:07:27.915688 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9592 10:07:27.918681 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9593 10:07:27.925004 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9594 10:07:27.928531 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9595 10:07:27.935009 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9596 10:07:27.938744 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9597 10:07:27.941798 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9598 10:07:27.948302 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9599 10:07:27.951291 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9600 10:07:27.958344 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9601 10:07:27.961643 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9602 10:07:27.965341 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9603 10:07:27.971376 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9604 10:07:27.974928 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9605 10:07:27.977931 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9606 10:07:27.984685 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9607 10:07:27.988268 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9608 10:07:27.991475 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9609 10:07:27.995036 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9610 10:07:28.001471 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9611 10:07:28.004793 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9612 10:07:28.007787 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9613 10:07:28.014663 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9614 10:07:28.018258 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9615 10:07:28.024976 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9616 10:07:28.028052 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9617 10:07:28.031182 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9618 10:07:28.038240 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9619 10:07:28.041170 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9620 10:07:28.044157 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9621 10:07:28.051062 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9622 10:07:28.054475 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9623 10:07:28.060908 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9624 10:07:28.064234 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9625 10:07:28.068071 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9626 10:07:28.074283 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9627 10:07:28.077544 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9628 10:07:28.083980 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9629 10:07:28.087242 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9630 10:07:28.091060 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9631 10:07:28.097217 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9632 10:07:28.100525 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9633 10:07:28.107634 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9634 10:07:28.110911 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9635 10:07:28.114126 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9636 10:07:28.120613 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9637 10:07:28.124168 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9638 10:07:28.130964 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9639 10:07:28.134485 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9640 10:07:28.137199 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9641 10:07:28.143737 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9642 10:07:28.147351 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9643 10:07:28.153624 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9644 10:07:28.157279 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9645 10:07:28.160577 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9646 10:07:28.166908 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9647 10:07:28.169936 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9648 10:07:28.176590 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9649 10:07:28.179964 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9650 10:07:28.183319 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9651 10:07:28.189531 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9652 10:07:28.192948 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9653 10:07:28.199474 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9654 10:07:28.202821 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9655 10:07:28.206319 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9656 10:07:28.213351 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9657 10:07:28.216132 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9658 10:07:28.223109 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9659 10:07:28.226369 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9660 10:07:28.229471 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9661 10:07:28.235975 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9662 10:07:28.239756 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9663 10:07:28.246067 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9664 10:07:28.249196 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9665 10:07:28.252264 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9666 10:07:28.259164 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9667 10:07:28.262193 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9668 10:07:28.268927 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9669 10:07:28.272237 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9670 10:07:28.275717 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9671 10:07:28.281944 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9672 10:07:28.285233 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9673 10:07:28.291548 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9674 10:07:28.294971 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9675 10:07:28.301580 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9676 10:07:28.305032 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9677 10:07:28.308163 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9678 10:07:28.315004 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9679 10:07:28.318145 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9680 10:07:28.324693 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9681 10:07:28.328024 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9682 10:07:28.334976 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9683 10:07:28.338152 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9684 10:07:28.341275 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9685 10:07:28.348148 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9686 10:07:28.350968 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9687 10:07:28.358200 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9688 10:07:28.361092 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9689 10:07:28.364739 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9690 10:07:28.370652 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9691 10:07:28.374553 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9692 10:07:28.381027 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9693 10:07:28.383921 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9694 10:07:28.390665 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9695 10:07:28.394059 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9696 10:07:28.397055 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9697 10:07:28.403512 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9698 10:07:28.407240 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9699 10:07:28.413618 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9700 10:07:28.417296 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9701 10:07:28.423885 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9702 10:07:28.427330 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9703 10:07:28.430179 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9704 10:07:28.436820 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9705 10:07:28.440109 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9706 10:07:28.446690 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9707 10:07:28.449932 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9708 10:07:28.456979 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9709 10:07:28.459993 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9710 10:07:28.463108 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9711 10:07:28.469422 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9712 10:07:28.472872 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9713 10:07:28.479557 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9714 10:07:28.482764 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9715 10:07:28.489602 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9716 10:07:28.492833 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9717 10:07:28.495801 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9718 10:07:28.499488 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9719 10:07:28.505668 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9720 10:07:28.509056 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9721 10:07:28.512092 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9722 10:07:28.518919 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9723 10:07:28.522459 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9724 10:07:28.525804 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9725 10:07:28.532196 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9726 10:07:28.535504 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9727 10:07:28.539023 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9728 10:07:28.545569 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9729 10:07:28.548591 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9730 10:07:28.555176 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9731 10:07:28.558875 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9732 10:07:28.562092 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9733 10:07:28.568440 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9734 10:07:28.571835 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9735 10:07:28.575168 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9736 10:07:28.581782 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9737 10:07:28.584936 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9738 10:07:28.591762 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9739 10:07:28.594541 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9740 10:07:28.598262 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9741 10:07:28.604398 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9742 10:07:28.607695 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9743 10:07:28.614477 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9744 10:07:28.617873 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9745 10:07:28.621139 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9746 10:07:28.627692 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9747 10:07:28.630570 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9748 10:07:28.634185 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9749 10:07:28.640838 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9750 10:07:28.643771 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9751 10:07:28.650649 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9752 10:07:28.653944 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9753 10:07:28.657457 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9754 10:07:28.664188 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9755 10:07:28.667413 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9756 10:07:28.670372 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9757 10:07:28.673565 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9758 10:07:28.680406 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9759 10:07:28.683390 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9760 10:07:28.686922 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9761 10:07:28.690262 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9762 10:07:28.696552 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9763 10:07:28.700210 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9764 10:07:28.703219 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9765 10:07:28.706772 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9766 10:07:28.712956 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9767 10:07:28.716662 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9768 10:07:28.719866 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9769 10:07:28.726477 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9770 10:07:28.729286 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9771 10:07:28.735860 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9772 10:07:28.739110 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9773 10:07:28.745830 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9774 10:07:28.749188 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9775 10:07:28.752375 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9776 10:07:28.759278 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9777 10:07:28.762590 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9778 10:07:28.768835 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9779 10:07:28.772274 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9780 10:07:28.778812 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9781 10:07:28.782136 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9782 10:07:28.785581 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9783 10:07:28.791899 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9784 10:07:28.795035 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9785 10:07:28.801879 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9786 10:07:28.804760 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9787 10:07:28.808504 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9788 10:07:28.815236 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9789 10:07:28.818121 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9790 10:07:28.825266 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9791 10:07:28.828201 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9792 10:07:28.831576 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9793 10:07:28.838183 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9794 10:07:28.841026 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9795 10:07:28.847855 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9796 10:07:28.851524 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9797 10:07:28.857804 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9798 10:07:28.861454 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9799 10:07:28.867611 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9800 10:07:28.870808 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9801 10:07:28.873799 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9802 10:07:28.881012 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9803 10:07:28.883960 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9804 10:07:28.890782 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9805 10:07:28.893954 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9806 10:07:28.900532 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9807 10:07:28.903741 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9808 10:07:28.906964 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9809 10:07:28.913563 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9810 10:07:28.917181 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9811 10:07:28.923379 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9812 10:07:28.926733 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9813 10:07:28.929804 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9814 10:07:28.936369 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9815 10:07:28.940034 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9816 10:07:28.946134 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9817 10:07:28.949856 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9818 10:07:28.956378 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9819 10:07:28.959813 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9820 10:07:28.962984 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9821 10:07:28.969626 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9822 10:07:28.972830 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9823 10:07:28.979434 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9824 10:07:28.982453 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9825 10:07:28.986077 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9826 10:07:28.992219 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9827 10:07:28.996006 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9828 10:07:29.002342 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9829 10:07:29.005251 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9830 10:07:29.012083 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9831 10:07:29.015700 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9832 10:07:29.019002 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9833 10:07:29.025187 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9834 10:07:29.028791 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9835 10:07:29.035236 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9836 10:07:29.038963 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9837 10:07:29.045189 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9838 10:07:29.048106 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9839 10:07:29.051337 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9840 10:07:29.058227 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9841 10:07:29.061193 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9842 10:07:29.068017 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9843 10:07:29.071781 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9844 10:07:29.078120 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9845 10:07:29.081367 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9846 10:07:29.084860 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9847 10:07:29.091255 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9848 10:07:29.094875 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9849 10:07:29.101467 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9850 10:07:29.104361 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9851 10:07:29.111556 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9852 10:07:29.114617 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9853 10:07:29.120975 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9854 10:07:29.124188 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9855 10:07:29.131087 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9856 10:07:29.134454 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9857 10:07:29.137533 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9858 10:07:29.143683 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9859 10:07:29.147215 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9860 10:07:29.154151 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9861 10:07:29.157189 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9862 10:07:29.164328 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9863 10:07:29.167287 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9864 10:07:29.170397 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9865 10:07:29.176941 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9866 10:07:29.180035 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9867 10:07:29.186891 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9868 10:07:29.190375 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9869 10:07:29.197286 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9870 10:07:29.200184 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9871 10:07:29.207259 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9872 10:07:29.210025 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9873 10:07:29.213400 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9874 10:07:29.220242 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9875 10:07:29.223598 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9876 10:07:29.230338 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9877 10:07:29.232861 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9878 10:07:29.239900 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9879 10:07:29.243239 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9880 10:07:29.246184 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9881 10:07:29.253028 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9882 10:07:29.255818 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9883 10:07:29.263168 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9884 10:07:29.266014 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9885 10:07:29.272478 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9886 10:07:29.275788 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9887 10:07:29.282370 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9888 10:07:29.285877 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9889 10:07:29.288868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9890 10:07:29.295545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9891 10:07:29.298878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9892 10:07:29.305395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9893 10:07:29.309042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9894 10:07:29.315527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9895 10:07:29.318671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9896 10:07:29.324891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9897 10:07:29.328624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9898 10:07:29.335087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9899 10:07:29.338595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9900 10:07:29.345180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9901 10:07:29.348322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9902 10:07:29.354870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9903 10:07:29.358438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9904 10:07:29.364901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9905 10:07:29.367937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9906 10:07:29.374686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9907 10:07:29.377905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9908 10:07:29.385037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9909 10:07:29.387844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9910 10:07:29.394433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9911 10:07:29.397829 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9912 10:07:29.404360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9913 10:07:29.407716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9914 10:07:29.413941 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9915 10:07:29.417474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9916 10:07:29.424045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9917 10:07:29.427445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9918 10:07:29.434002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9919 10:07:29.437161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9920 10:07:29.443905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9921 10:07:29.447042 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9922 10:07:29.449925 INFO: [APUAPC] vio 0
9923 10:07:29.453850 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9924 10:07:29.459987 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9925 10:07:29.463738 INFO: [APUAPC] D0_APC_0: 0x400510
9926 10:07:29.466967 INFO: [APUAPC] D0_APC_1: 0x0
9927 10:07:29.470185 INFO: [APUAPC] D0_APC_2: 0x1540
9928 10:07:29.470743 INFO: [APUAPC] D0_APC_3: 0x0
9929 10:07:29.473598 INFO: [APUAPC] D1_APC_0: 0xffffffff
9930 10:07:29.476365 INFO: [APUAPC] D1_APC_1: 0xffffffff
9931 10:07:29.479876 INFO: [APUAPC] D1_APC_2: 0x3fffff
9932 10:07:29.483389 INFO: [APUAPC] D1_APC_3: 0x0
9933 10:07:29.486474 INFO: [APUAPC] D2_APC_0: 0xffffffff
9934 10:07:29.489556 INFO: [APUAPC] D2_APC_1: 0xffffffff
9935 10:07:29.492800 INFO: [APUAPC] D2_APC_2: 0x3fffff
9936 10:07:29.496159 INFO: [APUAPC] D2_APC_3: 0x0
9937 10:07:29.499568 INFO: [APUAPC] D3_APC_0: 0xffffffff
9938 10:07:29.502709 INFO: [APUAPC] D3_APC_1: 0xffffffff
9939 10:07:29.506366 INFO: [APUAPC] D3_APC_2: 0x3fffff
9940 10:07:29.509198 INFO: [APUAPC] D3_APC_3: 0x0
9941 10:07:29.512909 INFO: [APUAPC] D4_APC_0: 0xffffffff
9942 10:07:29.516022 INFO: [APUAPC] D4_APC_1: 0xffffffff
9943 10:07:29.519263 INFO: [APUAPC] D4_APC_2: 0x3fffff
9944 10:07:29.522771 INFO: [APUAPC] D4_APC_3: 0x0
9945 10:07:29.526108 INFO: [APUAPC] D5_APC_0: 0xffffffff
9946 10:07:29.529357 INFO: [APUAPC] D5_APC_1: 0xffffffff
9947 10:07:29.532492 INFO: [APUAPC] D5_APC_2: 0x3fffff
9948 10:07:29.535784 INFO: [APUAPC] D5_APC_3: 0x0
9949 10:07:29.539154 INFO: [APUAPC] D6_APC_0: 0xffffffff
9950 10:07:29.542617 INFO: [APUAPC] D6_APC_1: 0xffffffff
9951 10:07:29.545898 INFO: [APUAPC] D6_APC_2: 0x3fffff
9952 10:07:29.549346 INFO: [APUAPC] D6_APC_3: 0x0
9953 10:07:29.551875 INFO: [APUAPC] D7_APC_0: 0xffffffff
9954 10:07:29.555904 INFO: [APUAPC] D7_APC_1: 0xffffffff
9955 10:07:29.559163 INFO: [APUAPC] D7_APC_2: 0x3fffff
9956 10:07:29.562066 INFO: [APUAPC] D7_APC_3: 0x0
9957 10:07:29.565653 INFO: [APUAPC] D8_APC_0: 0xffffffff
9958 10:07:29.569030 INFO: [APUAPC] D8_APC_1: 0xffffffff
9959 10:07:29.571978 INFO: [APUAPC] D8_APC_2: 0x3fffff
9960 10:07:29.575736 INFO: [APUAPC] D8_APC_3: 0x0
9961 10:07:29.578996 INFO: [APUAPC] D9_APC_0: 0xffffffff
9962 10:07:29.582125 INFO: [APUAPC] D9_APC_1: 0xffffffff
9963 10:07:29.585549 INFO: [APUAPC] D9_APC_2: 0x3fffff
9964 10:07:29.588261 INFO: [APUAPC] D9_APC_3: 0x0
9965 10:07:29.591557 INFO: [APUAPC] D10_APC_0: 0xffffffff
9966 10:07:29.595403 INFO: [APUAPC] D10_APC_1: 0xffffffff
9967 10:07:29.598574 INFO: [APUAPC] D10_APC_2: 0x3fffff
9968 10:07:29.602199 INFO: [APUAPC] D10_APC_3: 0x0
9969 10:07:29.604804 INFO: [APUAPC] D11_APC_0: 0xffffffff
9970 10:07:29.608164 INFO: [APUAPC] D11_APC_1: 0xffffffff
9971 10:07:29.611428 INFO: [APUAPC] D11_APC_2: 0x3fffff
9972 10:07:29.615206 INFO: [APUAPC] D11_APC_3: 0x0
9973 10:07:29.618015 INFO: [APUAPC] D12_APC_0: 0xffffffff
9974 10:07:29.621420 INFO: [APUAPC] D12_APC_1: 0xffffffff
9975 10:07:29.624684 INFO: [APUAPC] D12_APC_2: 0x3fffff
9976 10:07:29.628188 INFO: [APUAPC] D12_APC_3: 0x0
9977 10:07:29.631451 INFO: [APUAPC] D13_APC_0: 0xffffffff
9978 10:07:29.634934 INFO: [APUAPC] D13_APC_1: 0xffffffff
9979 10:07:29.638025 INFO: [APUAPC] D13_APC_2: 0x3fffff
9980 10:07:29.641614 INFO: [APUAPC] D13_APC_3: 0x0
9981 10:07:29.644464 INFO: [APUAPC] D14_APC_0: 0xffffffff
9982 10:07:29.647791 INFO: [APUAPC] D14_APC_1: 0xffffffff
9983 10:07:29.651077 INFO: [APUAPC] D14_APC_2: 0x3fffff
9984 10:07:29.654927 INFO: [APUAPC] D14_APC_3: 0x0
9985 10:07:29.658054 INFO: [APUAPC] D15_APC_0: 0xffffffff
9986 10:07:29.661163 INFO: [APUAPC] D15_APC_1: 0xffffffff
9987 10:07:29.664035 INFO: [APUAPC] D15_APC_2: 0x3fffff
9988 10:07:29.667477 INFO: [APUAPC] D15_APC_3: 0x0
9989 10:07:29.671210 INFO: [APUAPC] APC_CON: 0x4
9990 10:07:29.674326 INFO: [NOCDAPC] D0_APC_0: 0x0
9991 10:07:29.677207 INFO: [NOCDAPC] D0_APC_1: 0x0
9992 10:07:29.680701 INFO: [NOCDAPC] D1_APC_0: 0x0
9993 10:07:29.683907 INFO: [NOCDAPC] D1_APC_1: 0xfff
9994 10:07:29.687325 INFO: [NOCDAPC] D2_APC_0: 0x0
9995 10:07:29.690643 INFO: [NOCDAPC] D2_APC_1: 0xfff
9996 10:07:29.691185 INFO: [NOCDAPC] D3_APC_0: 0x0
9997 10:07:29.693837 INFO: [NOCDAPC] D3_APC_1: 0xfff
9998 10:07:29.696935 INFO: [NOCDAPC] D4_APC_0: 0x0
9999 10:07:29.700481 INFO: [NOCDAPC] D4_APC_1: 0xfff
10000 10:07:29.703994 INFO: [NOCDAPC] D5_APC_0: 0x0
10001 10:07:29.707315 INFO: [NOCDAPC] D5_APC_1: 0xfff
10002 10:07:29.710396 INFO: [NOCDAPC] D6_APC_0: 0x0
10003 10:07:29.713877 INFO: [NOCDAPC] D6_APC_1: 0xfff
10004 10:07:29.716786 INFO: [NOCDAPC] D7_APC_0: 0x0
10005 10:07:29.720161 INFO: [NOCDAPC] D7_APC_1: 0xfff
10006 10:07:29.723631 INFO: [NOCDAPC] D8_APC_0: 0x0
10007 10:07:29.726534 INFO: [NOCDAPC] D8_APC_1: 0xfff
10008 10:07:29.730345 INFO: [NOCDAPC] D9_APC_0: 0x0
10009 10:07:29.730960 INFO: [NOCDAPC] D9_APC_1: 0xfff
10010 10:07:29.733385 INFO: [NOCDAPC] D10_APC_0: 0x0
10011 10:07:29.737009 INFO: [NOCDAPC] D10_APC_1: 0xfff
10012 10:07:29.740087 INFO: [NOCDAPC] D11_APC_0: 0x0
10013 10:07:29.743355 INFO: [NOCDAPC] D11_APC_1: 0xfff
10014 10:07:29.746496 INFO: [NOCDAPC] D12_APC_0: 0x0
10015 10:07:29.749932 INFO: [NOCDAPC] D12_APC_1: 0xfff
10016 10:07:29.752920 INFO: [NOCDAPC] D13_APC_0: 0x0
10017 10:07:29.756101 INFO: [NOCDAPC] D13_APC_1: 0xfff
10018 10:07:29.759313 INFO: [NOCDAPC] D14_APC_0: 0x0
10019 10:07:29.763195 INFO: [NOCDAPC] D14_APC_1: 0xfff
10020 10:07:29.766027 INFO: [NOCDAPC] D15_APC_0: 0x0
10021 10:07:29.769487 INFO: [NOCDAPC] D15_APC_1: 0xfff
10022 10:07:29.773061 INFO: [NOCDAPC] APC_CON: 0x4
10023 10:07:29.775946 INFO: [APUAPC] set_apusys_apc done
10024 10:07:29.779679 INFO: [DEVAPC] devapc_init done
10025 10:07:29.782481 INFO: GICv3 without legacy support detected.
10026 10:07:29.786196 INFO: ARM GICv3 driver initialized in EL3
10027 10:07:29.789172 INFO: Maximum SPI INTID supported: 639
10028 10:07:29.792859 INFO: BL31: Initializing runtime services
10029 10:07:29.799351 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10030 10:07:29.802576 INFO: SPM: enable CPC mode
10031 10:07:29.809346 INFO: mcdi ready for mcusys-off-idle and system suspend
10032 10:07:29.812129 INFO: BL31: Preparing for EL3 exit to normal world
10033 10:07:29.815553 INFO: Entry point address = 0x80000000
10034 10:07:29.818780 INFO: SPSR = 0x8
10035 10:07:29.823651
10036 10:07:29.824206
10037 10:07:29.824573
10038 10:07:29.826875 Starting depthcharge on Spherion...
10039 10:07:29.827341
10040 10:07:29.827704 Wipe memory regions:
10041 10:07:29.828045
10042 10:07:29.830552 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10043 10:07:29.831127 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10044 10:07:29.831564 Setting prompt string to ['asurada:']
10045 10:07:29.831982 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10046 10:07:29.832713 [0x00000040000000, 0x00000054600000)
10047 10:07:29.952907
10048 10:07:29.953460 [0x00000054660000, 0x00000080000000)
10049 10:07:30.213291
10050 10:07:30.213851 [0x000000821a7280, 0x000000ffe64000)
10051 10:07:30.958272
10052 10:07:30.958856 [0x00000100000000, 0x00000240000000)
10053 10:07:32.848729
10054 10:07:32.851780 Initializing XHCI USB controller at 0x11200000.
10055 10:07:33.889812
10056 10:07:33.892730 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10057 10:07:33.893284
10058 10:07:33.893651
10059 10:07:33.893987
10060 10:07:33.894767 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10062 10:07:33.996079 asurada: tftpboot 192.168.201.1 10670703/tftp-deploy-huopdwre/kernel/image.itb 10670703/tftp-deploy-huopdwre/kernel/cmdline
10063 10:07:33.996738 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10064 10:07:33.997205 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10065 10:07:34.002130 tftpboot 192.168.201.1 10670703/tftp-deploy-huopdwre/kernel/image.itp-deploy-huopdwre/kernel/cmdline
10066 10:07:34.002703
10067 10:07:34.003132 Waiting for link
10068 10:07:34.162647
10069 10:07:34.163256 R8152: Initializing
10070 10:07:34.163632
10071 10:07:34.165943 Version 6 (ocp_data = 5c30)
10072 10:07:34.166497
10073 10:07:34.169448 R8152: Done initializing
10074 10:07:34.170015
10075 10:07:34.170381 Adding net device
10076 10:07:36.194998
10077 10:07:36.195712 done.
10078 10:07:36.196187
10079 10:07:36.196542 MAC: 00:24:32:30:78:ff
10080 10:07:36.196876
10081 10:07:36.197908 Sending DHCP discover... done.
10082 10:07:36.198369
10083 10:07:36.201494 Waiting for reply... done.
10084 10:07:36.202046
10085 10:07:36.204804 Sending DHCP request... done.
10086 10:07:36.205359
10087 10:07:36.208340 Waiting for reply... done.
10088 10:07:36.208899
10089 10:07:36.209430 My ip is 192.168.201.21
10090 10:07:36.209954
10091 10:07:36.211146 The DHCP server ip is 192.168.201.1
10092 10:07:36.211611
10093 10:07:36.214347 TFTP server IP predefined by user: 192.168.201.1
10094 10:07:36.218077
10095 10:07:36.221294 Bootfile predefined by user: 10670703/tftp-deploy-huopdwre/kernel/image.itb
10096 10:07:36.224235
10097 10:07:36.224695 Sending tftp read request... done.
10098 10:07:36.225062
10099 10:07:36.233589 Waiting for the transfer...
10100 10:07:36.234146
10101 10:07:36.940975 00000000 ################################################################
10102 10:07:36.941564
10103 10:07:37.630924 00080000 ################################################################
10104 10:07:37.631516
10105 10:07:38.352337 00100000 ################################################################
10106 10:07:38.352898
10107 10:07:39.064841 00180000 ################################################################
10108 10:07:39.065425
10109 10:07:39.794757 00200000 ################################################################
10110 10:07:39.795470
10111 10:07:40.518786 00280000 ################################################################
10112 10:07:40.519355
10113 10:07:41.237515 00300000 ################################################################
10114 10:07:41.238041
10115 10:07:41.965683 00380000 ################################################################
10116 10:07:41.966260
10117 10:07:42.677006 00400000 ################################################################
10118 10:07:42.677634
10119 10:07:43.401467 00480000 ################################################################
10120 10:07:43.402031
10121 10:07:44.128608 00500000 ################################################################
10122 10:07:44.129261
10123 10:07:44.858734 00580000 ################################################################
10124 10:07:44.859319
10125 10:07:45.586504 00600000 ################################################################
10126 10:07:45.587116
10127 10:07:46.314380 00680000 ################################################################
10128 10:07:46.314946
10129 10:07:47.041483 00700000 ################################################################
10130 10:07:47.042047
10131 10:07:47.762890 00780000 ################################################################
10132 10:07:47.763455
10133 10:07:48.491152 00800000 ################################################################
10134 10:07:48.491713
10135 10:07:49.224318 00880000 ################################################################
10136 10:07:49.224929
10137 10:07:49.943558 00900000 ################################################################
10138 10:07:49.944336
10139 10:07:50.675115 00980000 ################################################################
10140 10:07:50.675664
10141 10:07:51.380934 00a00000 ################################################################
10142 10:07:51.381499
10143 10:07:52.100705 00a80000 ################################################################
10144 10:07:52.101270
10145 10:07:52.830288 00b00000 ################################################################
10146 10:07:52.830873
10147 10:07:53.546939 00b80000 ################################################################
10148 10:07:53.547502
10149 10:07:54.272123 00c00000 ################################################################
10150 10:07:54.272690
10151 10:07:54.998174 00c80000 ################################################################
10152 10:07:54.998721
10153 10:07:55.725784 00d00000 ################################################################
10154 10:07:55.726399
10155 10:07:56.464905 00d80000 ################################################################
10156 10:07:56.465472
10157 10:07:57.189333 00e00000 ################################################################
10158 10:07:57.189913
10159 10:07:57.917089 00e80000 ################################################################
10160 10:07:57.917653
10161 10:07:58.647307 00f00000 ################################################################
10162 10:07:58.647829
10163 10:07:59.373630 00f80000 ################################################################
10164 10:07:59.374213
10165 10:08:00.109900 01000000 ################################################################
10166 10:08:00.110480
10167 10:08:00.842463 01080000 ################################################################
10168 10:08:00.843066
10169 10:08:01.548513 01100000 ################################################################
10170 10:08:01.549056
10171 10:08:02.278220 01180000 ################################################################
10172 10:08:02.278795
10173 10:08:03.016462 01200000 ################################################################
10174 10:08:03.017033
10175 10:08:03.748029 01280000 ################################################################
10176 10:08:03.748610
10177 10:08:04.475117 01300000 ################################################################
10178 10:08:04.475674
10179 10:08:05.207011 01380000 ################################################################
10180 10:08:05.207572
10181 10:08:05.932185 01400000 ################################################################
10182 10:08:05.932770
10183 10:08:06.651973 01480000 ################################################################
10184 10:08:06.652488
10185 10:08:07.377274 01500000 ################################################################
10186 10:08:07.377820
10187 10:08:08.094227 01580000 ################################################################
10188 10:08:08.094813
10189 10:08:08.822516 01600000 ################################################################
10190 10:08:08.823253
10191 10:08:09.558021 01680000 ################################################################
10192 10:08:09.558606
10193 10:08:10.279686 01700000 ################################################################
10194 10:08:10.280235
10195 10:08:11.003764 01780000 ################################################################
10196 10:08:11.004365
10197 10:08:11.725240 01800000 ################################################################
10198 10:08:11.725843
10199 10:08:12.441763 01880000 ################################################################
10200 10:08:12.442335
10201 10:08:13.167331 01900000 ################################################################
10202 10:08:13.167925
10203 10:08:13.889683 01980000 ################################################################
10204 10:08:13.890251
10205 10:08:14.612938 01a00000 ################################################################
10206 10:08:14.613522
10207 10:08:15.336034 01a80000 ################################################################
10208 10:08:15.336588
10209 10:08:16.062477 01b00000 ################################################################
10210 10:08:16.063082
10211 10:08:16.778317 01b80000 ################################################################
10212 10:08:16.778864
10213 10:08:17.491210 01c00000 ################################################################
10214 10:08:17.491790
10215 10:08:18.210877 01c80000 ################################################################
10216 10:08:18.211429
10217 10:08:18.919005 01d00000 ################################################################
10218 10:08:18.919574
10219 10:08:19.651528 01d80000 ################################################################
10220 10:08:19.652090
10221 10:08:20.371182 01e00000 ################################################################
10222 10:08:20.371772
10223 10:08:21.073474 01e80000 ################################################################
10224 10:08:21.074032
10225 10:08:21.785170 01f00000 ################################################################
10226 10:08:21.785769
10227 10:08:22.508492 01f80000 ################################################################
10228 10:08:22.509100
10229 10:08:23.229438 02000000 ################################################################
10230 10:08:23.230021
10231 10:08:23.943917 02080000 ################################################################
10232 10:08:23.944485
10233 10:08:24.658681 02100000 ################################################################
10234 10:08:24.659376
10235 10:08:25.383533 02180000 ################################################################
10236 10:08:25.384116
10237 10:08:26.105543 02200000 ################################################################
10238 10:08:26.106097
10239 10:08:26.822775 02280000 ################################################################
10240 10:08:26.823384
10241 10:08:27.548568 02300000 ################################################################
10242 10:08:27.549142
10243 10:08:28.257632 02380000 ################################################################
10244 10:08:28.258195
10245 10:08:28.974161 02400000 ################################################################
10246 10:08:28.974821
10247 10:08:29.691403 02480000 ################################################################
10248 10:08:29.691977
10249 10:08:30.417669 02500000 ################################################################
10250 10:08:30.418270
10251 10:08:31.128589 02580000 ################################################################
10252 10:08:31.129161
10253 10:08:31.856234 02600000 ################################################################
10254 10:08:31.856834
10255 10:08:32.590425 02680000 ################################################################
10256 10:08:32.591031
10257 10:08:33.318618 02700000 ################################################################
10258 10:08:33.319297
10259 10:08:34.037903 02780000 ################################################################
10260 10:08:34.038461
10261 10:08:34.765508 02800000 ################################################################
10262 10:08:34.766087
10263 10:08:35.431849 02880000 ################################################################
10264 10:08:35.432000
10265 10:08:36.080208 02900000 ################################################################
10266 10:08:36.080746
10267 10:08:36.761050 02980000 ################################################################
10268 10:08:36.761577
10269 10:08:37.459482 02a00000 ################################################################
10270 10:08:37.460227
10271 10:08:38.176397 02a80000 ################################################################
10272 10:08:38.176973
10273 10:08:38.852432 02b00000 ################################################################
10274 10:08:38.852710
10275 10:08:39.566183 02b80000 ################################################################
10276 10:08:39.566879
10277 10:08:40.286139 02c00000 ################################################################
10278 10:08:40.286282
10279 10:08:40.855350 02c80000 ################################################################
10280 10:08:40.855539
10281 10:08:41.415436 02d00000 ################################################################
10282 10:08:41.415636
10283 10:08:42.015241 02d80000 ################################################################
10284 10:08:42.015394
10285 10:08:42.623094 02e00000 ################################################################
10286 10:08:42.623283
10287 10:08:43.205871 02e80000 ################################################################
10288 10:08:43.206026
10289 10:08:43.765769 02f00000 ################################################################
10290 10:08:43.765961
10291 10:08:44.256271 02f80000 ######################################################## done.
10292 10:08:44.256467
10293 10:08:44.259809 The bootfile was 50265910 bytes long.
10294 10:08:44.259967
10295 10:08:44.263089 Sending tftp read request... done.
10296 10:08:44.263200
10297 10:08:44.263293 Waiting for the transfer...
10298 10:08:44.263380
10299 10:08:44.266710 00000000 # done.
10300 10:08:44.266823
10301 10:08:44.272613 Command line loaded dynamically from TFTP file: 10670703/tftp-deploy-huopdwre/kernel/cmdline
10302 10:08:44.272727
10303 10:08:44.285911 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10304 10:08:44.286057
10305 10:08:44.286156 Loading FIT.
10306 10:08:44.286246
10307 10:08:44.289070 Image ramdisk-1 has 40129633 bytes.
10308 10:08:44.289177
10309 10:08:44.292676 Image fdt-1 has 46924 bytes.
10310 10:08:44.292788
10311 10:08:44.295708 Image kernel-1 has 10087317 bytes.
10312 10:08:44.295825
10313 10:08:44.306081 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10314 10:08:44.306210
10315 10:08:44.322090 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10316 10:08:44.322275
10317 10:08:44.328624 Choosing best match conf-1 for compat google,spherion-rev2.
10318 10:08:44.328740
10319 10:08:44.331984 Connected to device vid:did:rid of 1ae0:0028:00
10320 10:08:44.343023
10321 10:08:44.346232 tpm_get_response: command 0x17b, return code 0x0
10322 10:08:44.346351
10323 10:08:44.349491 ec_init: CrosEC protocol v3 supported (256, 248)
10324 10:08:44.353769
10325 10:08:44.357079 tpm_cleanup: add release locality here.
10326 10:08:44.357194
10327 10:08:44.357294 Shutting down all USB controllers.
10328 10:08:44.360250
10329 10:08:44.360369 Removing current net device
10330 10:08:44.360474
10331 10:08:44.367076 Exiting depthcharge with code 4 at timestamp: 103868733
10332 10:08:44.367194
10333 10:08:44.370203 LZMA decompressing kernel-1 to 0x821a6718
10334 10:08:44.370323
10335 10:08:44.373779 LZMA decompressing kernel-1 to 0x40000000
10336 10:08:45.641305
10337 10:08:45.641494 jumping to kernel
10338 10:08:45.642090 end: 2.2.4 bootloader-commands (duration 00:01:16) [common]
10339 10:08:45.642232 start: 2.2.5 auto-login-action (timeout 00:03:09) [common]
10340 10:08:45.642341 Setting prompt string to ['Linux version [0-9]']
10341 10:08:45.642442 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10342 10:08:45.642542 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10343 10:08:45.723849
10344 10:08:45.727039 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10345 10:08:45.730772 start: 2.2.5.1 login-action (timeout 00:03:09) [common]
10346 10:08:45.730957 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10347 10:08:45.731087 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10348 10:08:45.731201 Using line separator: #'\n'#
10349 10:08:45.731297 No login prompt set.
10350 10:08:45.731395 Parsing kernel messages
10351 10:08:45.731486 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10352 10:08:45.731653 [login-action] Waiting for messages, (timeout 00:03:09)
10353 10:08:45.749697 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j19381-arm64-gcc-10-defconfig-arm64-chromebook-d6qsg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023
10354 10:08:45.753807 [ 0.000000] random: crng init done
10355 10:08:45.756763 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10356 10:08:45.760124 [ 0.000000] efi: UEFI not found.
10357 10:08:45.769894 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10358 10:08:45.776524 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10359 10:08:45.786402 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10360 10:08:45.796084 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10361 10:08:45.802641 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10362 10:08:45.809255 [ 0.000000] printk: bootconsole [mtk8250] enabled
10363 10:08:45.816266 [ 0.000000] NUMA: No NUMA configuration found
10364 10:08:45.822417 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10365 10:08:45.825690 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10366 10:08:45.828944 [ 0.000000] Zone ranges:
10367 10:08:45.835623 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10368 10:08:45.838753 [ 0.000000] DMA32 empty
10369 10:08:45.845655 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10370 10:08:45.848808 [ 0.000000] Movable zone start for each node
10371 10:08:45.852081 [ 0.000000] Early memory node ranges
10372 10:08:45.858523 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10373 10:08:45.865019 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10374 10:08:45.871697 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10375 10:08:45.878471 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10376 10:08:45.885035 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10377 10:08:45.891528 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10378 10:08:45.947826 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10379 10:08:45.954357 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10380 10:08:45.960727 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10381 10:08:45.964056 [ 0.000000] psci: probing for conduit method from DT.
10382 10:08:45.970539 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10383 10:08:45.974060 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10384 10:08:45.980362 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10385 10:08:45.983869 [ 0.000000] psci: SMC Calling Convention v1.2
10386 10:08:45.990500 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10387 10:08:45.993520 [ 0.000000] Detected VIPT I-cache on CPU0
10388 10:08:46.000317 [ 0.000000] CPU features: detected: GIC system register CPU interface
10389 10:08:46.006752 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10390 10:08:46.013428 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10391 10:08:46.019969 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10392 10:08:46.030103 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10393 10:08:46.036592 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10394 10:08:46.039586 [ 0.000000] alternatives: applying boot alternatives
10395 10:08:46.046717 [ 0.000000] Fallback order for Node 0: 0
10396 10:08:46.053311 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10397 10:08:46.056957 [ 0.000000] Policy zone: Normal
10398 10:08:46.069614 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10399 10:08:46.079843 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10400 10:08:46.089407 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10401 10:08:46.099526 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10402 10:08:46.106020 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10403 10:08:46.109258 <6>[ 0.000000] software IO TLB: area num 8.
10404 10:08:46.165057 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10405 10:08:46.313982 <6>[ 0.000000] Memory: 7933752K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419016K reserved, 32768K cma-reserved)
10406 10:08:46.320730 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10407 10:08:46.327501 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10408 10:08:46.330713 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10409 10:08:46.337206 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10410 10:08:46.343867 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10411 10:08:46.347093 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10412 10:08:46.356661 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10413 10:08:46.363388 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10414 10:08:46.369974 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10415 10:08:46.376876 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10416 10:08:46.380101 <6>[ 0.000000] GICv3: 608 SPIs implemented
10417 10:08:46.383382 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10418 10:08:46.389835 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10419 10:08:46.393179 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10420 10:08:46.399878 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10421 10:08:46.412746 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10422 10:08:46.426171 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10423 10:08:46.432679 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10424 10:08:46.440929 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10425 10:08:46.454087 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10426 10:08:46.460541 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10427 10:08:46.467379 <6>[ 0.009177] Console: colour dummy device 80x25
10428 10:08:46.477072 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10429 10:08:46.484017 <6>[ 0.024413] pid_max: default: 32768 minimum: 301
10430 10:08:46.487178 <6>[ 0.029287] LSM: Security Framework initializing
10431 10:08:46.493628 <6>[ 0.034226] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10432 10:08:46.503435 <6>[ 0.042039] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10433 10:08:46.513514 <6>[ 0.051524] cblist_init_generic: Setting adjustable number of callback queues.
10434 10:08:46.520018 <6>[ 0.059023] cblist_init_generic: Setting shift to 3 and lim to 1.
10435 10:08:46.523087 <6>[ 0.065401] cblist_init_generic: Setting shift to 3 and lim to 1.
10436 10:08:46.530048 <6>[ 0.071811] rcu: Hierarchical SRCU implementation.
10437 10:08:46.536703 <6>[ 0.076825] rcu: Max phase no-delay instances is 1000.
10438 10:08:46.543233 <6>[ 0.083881] EFI services will not be available.
10439 10:08:46.546602 <6>[ 0.088851] smp: Bringing up secondary CPUs ...
10440 10:08:46.554702 <6>[ 0.093935] Detected VIPT I-cache on CPU1
10441 10:08:46.560998 <6>[ 0.094007] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10442 10:08:46.567904 <6>[ 0.094040] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10443 10:08:46.571005 <6>[ 0.094373] Detected VIPT I-cache on CPU2
10444 10:08:46.577544 <6>[ 0.094422] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10445 10:08:46.587329 <6>[ 0.094438] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10446 10:08:46.590547 <6>[ 0.094695] Detected VIPT I-cache on CPU3
10447 10:08:46.597487 <6>[ 0.094736] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10448 10:08:46.604122 <6>[ 0.094750] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10449 10:08:46.607357 <6>[ 0.095037] CPU features: detected: Spectre-v4
10450 10:08:46.613767 <6>[ 0.095042] CPU features: detected: Spectre-BHB
10451 10:08:46.617044 <6>[ 0.095046] Detected PIPT I-cache on CPU4
10452 10:08:46.623862 <6>[ 0.095098] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10453 10:08:46.630498 <6>[ 0.095113] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10454 10:08:46.636643 <6>[ 0.095409] Detected PIPT I-cache on CPU5
10455 10:08:46.643305 <6>[ 0.095472] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10456 10:08:46.650060 <6>[ 0.095488] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10457 10:08:46.653251 <6>[ 0.095770] Detected PIPT I-cache on CPU6
10458 10:08:46.660070 <6>[ 0.095834] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10459 10:08:46.669522 <6>[ 0.095850] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10460 10:08:46.673346 <6>[ 0.096151] Detected PIPT I-cache on CPU7
10461 10:08:46.679520 <6>[ 0.096216] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10462 10:08:46.686319 <6>[ 0.096232] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10463 10:08:46.689489 <6>[ 0.096279] smp: Brought up 1 node, 8 CPUs
10464 10:08:46.695913 <6>[ 0.237640] SMP: Total of 8 processors activated.
10465 10:08:46.702786 <6>[ 0.242592] CPU features: detected: 32-bit EL0 Support
10466 10:08:46.709679 <6>[ 0.247955] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10467 10:08:46.715824 <6>[ 0.256810] CPU features: detected: Common not Private translations
10468 10:08:46.722681 <6>[ 0.263286] CPU features: detected: CRC32 instructions
10469 10:08:46.729054 <6>[ 0.268637] CPU features: detected: RCpc load-acquire (LDAPR)
10470 10:08:46.732162 <6>[ 0.274596] CPU features: detected: LSE atomic instructions
10471 10:08:46.738725 <6>[ 0.280378] CPU features: detected: Privileged Access Never
10472 10:08:46.745953 <6>[ 0.286158] CPU features: detected: RAS Extension Support
10473 10:08:46.752071 <6>[ 0.291767] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10474 10:08:46.755684 <6>[ 0.298988] CPU: All CPU(s) started at EL2
10475 10:08:46.761839 <6>[ 0.303305] alternatives: applying system-wide alternatives
10476 10:08:46.772275 <6>[ 0.314020] devtmpfs: initialized
10477 10:08:46.787654 <6>[ 0.322951] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10478 10:08:46.794150 <6>[ 0.332919] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10479 10:08:46.800652 <6>[ 0.340970] pinctrl core: initialized pinctrl subsystem
10480 10:08:46.804050 <6>[ 0.347631] DMI not present or invalid.
10481 10:08:46.810470 <6>[ 0.352041] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10482 10:08:46.820896 <6>[ 0.358889] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10483 10:08:46.826771 <6>[ 0.366472] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10484 10:08:46.836817 <6>[ 0.374682] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10485 10:08:46.840029 <6>[ 0.382926] audit: initializing netlink subsys (disabled)
10486 10:08:46.849939 <5>[ 0.388623] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10487 10:08:46.857003 <6>[ 0.389337] thermal_sys: Registered thermal governor 'step_wise'
10488 10:08:46.863006 <6>[ 0.396590] thermal_sys: Registered thermal governor 'power_allocator'
10489 10:08:46.866343 <6>[ 0.402843] cpuidle: using governor menu
10490 10:08:46.873221 <6>[ 0.413801] NET: Registered PF_QIPCRTR protocol family
10491 10:08:46.879586 <6>[ 0.419281] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10492 10:08:46.886091 <6>[ 0.426383] ASID allocator initialised with 32768 entries
10493 10:08:46.889276 <6>[ 0.432961] Serial: AMBA PL011 UART driver
10494 10:08:46.899818 <4>[ 0.441670] Trying to register duplicate clock ID: 134
10495 10:08:46.955837 <6>[ 0.501129] KASLR enabled
10496 10:08:46.970280 <6>[ 0.508920] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10497 10:08:46.976805 <6>[ 0.515932] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10498 10:08:46.983778 <6>[ 0.522420] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10499 10:08:46.990081 <6>[ 0.529424] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10500 10:08:46.996509 <6>[ 0.535913] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10501 10:08:47.003165 <6>[ 0.542920] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10502 10:08:47.009935 <6>[ 0.549404] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10503 10:08:47.016363 <6>[ 0.556406] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10504 10:08:47.019367 <6>[ 0.563927] ACPI: Interpreter disabled.
10505 10:08:47.028362 <6>[ 0.570351] iommu: Default domain type: Translated
10506 10:08:47.035178 <6>[ 0.575462] iommu: DMA domain TLB invalidation policy: strict mode
10507 10:08:47.038338 <5>[ 0.582118] SCSI subsystem initialized
10508 10:08:47.044775 <6>[ 0.586287] usbcore: registered new interface driver usbfs
10509 10:08:47.051397 <6>[ 0.592020] usbcore: registered new interface driver hub
10510 10:08:47.054573 <6>[ 0.597571] usbcore: registered new device driver usb
10511 10:08:47.061666 <6>[ 0.603668] pps_core: LinuxPPS API ver. 1 registered
10512 10:08:47.071660 <6>[ 0.608860] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10513 10:08:47.075179 <6>[ 0.618205] PTP clock support registered
10514 10:08:47.077969 <6>[ 0.622446] EDAC MC: Ver: 3.0.0
10515 10:08:47.086117 <6>[ 0.627611] FPGA manager framework
10516 10:08:47.092128 <6>[ 0.631291] Advanced Linux Sound Architecture Driver Initialized.
10517 10:08:47.095362 <6>[ 0.638069] vgaarb: loaded
10518 10:08:47.102456 <6>[ 0.641242] clocksource: Switched to clocksource arch_sys_counter
10519 10:08:47.105712 <5>[ 0.647681] VFS: Disk quotas dquot_6.6.0
10520 10:08:47.112055 <6>[ 0.651866] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10521 10:08:47.115578 <6>[ 0.659054] pnp: PnP ACPI: disabled
10522 10:08:47.123896 <6>[ 0.665819] NET: Registered PF_INET protocol family
10523 10:08:47.134100 <6>[ 0.671411] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10524 10:08:47.145010 <6>[ 0.683713] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10525 10:08:47.155148 <6>[ 0.692528] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10526 10:08:47.161841 <6>[ 0.700497] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10527 10:08:47.171151 <6>[ 0.709198] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10528 10:08:47.178015 <6>[ 0.718938] TCP: Hash tables configured (established 65536 bind 65536)
10529 10:08:47.184502 <6>[ 0.725791] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10530 10:08:47.194274 <6>[ 0.732989] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10531 10:08:47.200812 <6>[ 0.740686] NET: Registered PF_UNIX/PF_LOCAL protocol family
10532 10:08:47.207568 <6>[ 0.746834] RPC: Registered named UNIX socket transport module.
10533 10:08:47.210991 <6>[ 0.752987] RPC: Registered udp transport module.
10534 10:08:47.217439 <6>[ 0.757920] RPC: Registered tcp transport module.
10535 10:08:47.224098 <6>[ 0.762849] RPC: Registered tcp NFSv4.1 backchannel transport module.
10536 10:08:47.228024 <6>[ 0.769516] PCI: CLS 0 bytes, default 64
10537 10:08:47.231054 <6>[ 0.773880] Unpacking initramfs...
10538 10:08:47.240928 <6>[ 0.777989] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10539 10:08:47.247300 <6>[ 0.786637] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10540 10:08:47.253639 <6>[ 0.795485] kvm [1]: IPA Size Limit: 40 bits
10541 10:08:47.257321 <6>[ 0.800011] kvm [1]: GICv3: no GICV resource entry
10542 10:08:47.264003 <6>[ 0.805030] kvm [1]: disabling GICv2 emulation
10543 10:08:47.270303 <6>[ 0.809719] kvm [1]: GIC system register CPU interface enabled
10544 10:08:47.273550 <6>[ 0.815895] kvm [1]: vgic interrupt IRQ18
10545 10:08:47.280342 <6>[ 0.820254] kvm [1]: VHE mode initialized successfully
10546 10:08:47.283446 <5>[ 0.826702] Initialise system trusted keyrings
10547 10:08:47.289935 <6>[ 0.831491] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10548 10:08:47.299782 <6>[ 0.841645] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10549 10:08:47.306210 <5>[ 0.848037] NFS: Registering the id_resolver key type
10550 10:08:47.309756 <5>[ 0.853338] Key type id_resolver registered
10551 10:08:47.316155 <5>[ 0.857754] Key type id_legacy registered
10552 10:08:47.322765 <6>[ 0.862034] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10553 10:08:47.329252 <6>[ 0.868954] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10554 10:08:47.336097 <6>[ 0.876661] 9p: Installing v9fs 9p2000 file system support
10555 10:08:47.372129 <5>[ 0.913899] Key type asymmetric registered
10556 10:08:47.375054 <5>[ 0.918233] Asymmetric key parser 'x509' registered
10557 10:08:47.385324 <6>[ 0.923381] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10558 10:08:47.388461 <6>[ 0.930997] io scheduler mq-deadline registered
10559 10:08:47.391526 <6>[ 0.935756] io scheduler kyber registered
10560 10:08:47.410803 <6>[ 0.952849] EINJ: ACPI disabled.
10561 10:08:47.442824 <4>[ 0.978435] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10562 10:08:47.452777 <4>[ 0.989076] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10563 10:08:47.467755 <6>[ 1.009878] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10564 10:08:47.475775 <6>[ 1.017789] printk: console [ttyS0] disabled
10565 10:08:47.503549 <6>[ 1.042440] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10566 10:08:47.510170 <6>[ 1.051917] printk: console [ttyS0] enabled
10567 10:08:47.513789 <6>[ 1.051917] printk: console [ttyS0] enabled
10568 10:08:47.520152 <6>[ 1.060809] printk: bootconsole [mtk8250] disabled
10569 10:08:47.523476 <6>[ 1.060809] printk: bootconsole [mtk8250] disabled
10570 10:08:47.530160 <6>[ 1.072165] SuperH (H)SCI(F) driver initialized
10571 10:08:47.533392 <6>[ 1.077456] msm_serial: driver initialized
10572 10:08:47.547824 <6>[ 1.086330] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10573 10:08:47.557834 <6>[ 1.094876] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10574 10:08:47.564110 <6>[ 1.103418] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10575 10:08:47.574406 <6>[ 1.112046] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10576 10:08:47.584032 <6>[ 1.120754] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10577 10:08:47.590286 <6>[ 1.129474] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10578 10:08:47.600186 <6>[ 1.138017] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10579 10:08:47.607237 <6>[ 1.146827] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10580 10:08:47.616534 <6>[ 1.155370] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10581 10:08:47.628895 <6>[ 1.171131] loop: module loaded
10582 10:08:47.635680 <6>[ 1.177168] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10583 10:08:47.658435 <4>[ 1.200689] mtk-pmic-keys: Failed to locate of_node [id: -1]
10584 10:08:47.665525 <6>[ 1.207700] megasas: 07.719.03.00-rc1
10585 10:08:47.675728 <6>[ 1.217498] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10586 10:08:47.682584 <6>[ 1.224627] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10587 10:08:47.699303 <6>[ 1.240920] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10588 10:08:47.758504 <6>[ 1.294075] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10589 10:08:48.854082 <6>[ 2.396351] Freeing initrd memory: 39184K
10590 10:08:48.864243 <6>[ 2.406599] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10591 10:08:48.875432 <6>[ 2.417491] tun: Universal TUN/TAP device driver, 1.6
10592 10:08:48.878472 <6>[ 2.423533] thunder_xcv, ver 1.0
10593 10:08:48.882051 <6>[ 2.427038] thunder_bgx, ver 1.0
10594 10:08:48.885282 <6>[ 2.430537] nicpf, ver 1.0
10595 10:08:48.895925 <6>[ 2.434547] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10596 10:08:48.899086 <6>[ 2.442024] hns3: Copyright (c) 2017 Huawei Corporation.
10597 10:08:48.905596 <6>[ 2.447610] hclge is initializing
10598 10:08:48.909204 <6>[ 2.451191] e1000: Intel(R) PRO/1000 Network Driver
10599 10:08:48.915558 <6>[ 2.456320] e1000: Copyright (c) 1999-2006 Intel Corporation.
10600 10:08:48.919005 <6>[ 2.462336] e1000e: Intel(R) PRO/1000 Network Driver
10601 10:08:48.925538 <6>[ 2.467552] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10602 10:08:48.932144 <6>[ 2.473739] igb: Intel(R) Gigabit Ethernet Network Driver
10603 10:08:48.938437 <6>[ 2.479389] igb: Copyright (c) 2007-2014 Intel Corporation.
10604 10:08:48.945609 <6>[ 2.485225] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10605 10:08:48.951656 <6>[ 2.491743] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10606 10:08:48.955397 <6>[ 2.498203] sky2: driver version 1.30
10607 10:08:48.961568 <6>[ 2.503183] VFIO - User Level meta-driver version: 0.3
10608 10:08:48.969066 <6>[ 2.511403] usbcore: registered new interface driver usb-storage
10609 10:08:48.975600 <6>[ 2.517849] usbcore: registered new device driver onboard-usb-hub
10610 10:08:48.984779 <6>[ 2.526942] mt6397-rtc mt6359-rtc: registered as rtc0
10611 10:08:48.994485 <6>[ 2.532436] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-10T10:08:51 UTC (1686391731)
10612 10:08:48.997730 <6>[ 2.542038] i2c_dev: i2c /dev entries driver
10613 10:08:49.014652 <6>[ 2.553692] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10614 10:08:49.021724 <6>[ 2.563863] sdhci: Secure Digital Host Controller Interface driver
10615 10:08:49.028954 <6>[ 2.570300] sdhci: Copyright(c) Pierre Ossman
10616 10:08:49.035190 <6>[ 2.575685] Synopsys Designware Multimedia Card Interface Driver
10617 10:08:49.038056 <6>[ 2.582310] mmc0: CQHCI version 5.10
10618 10:08:49.044728 <6>[ 2.582843] sdhci-pltfm: SDHCI platform and OF driver helper
10619 10:08:49.052391 <6>[ 2.594566] ledtrig-cpu: registered to indicate activity on CPUs
10620 10:08:49.063265 <6>[ 2.601989] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10621 10:08:49.069641 <6>[ 2.609424] usbcore: registered new interface driver usbhid
10622 10:08:49.072778 <6>[ 2.615252] usbhid: USB HID core driver
10623 10:08:49.079322 <6>[ 2.619510] spi_master spi0: will run message pump with realtime priority
10624 10:08:49.122929 <6>[ 2.658673] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10625 10:08:49.142053 <6>[ 2.673557] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10626 10:08:49.145026 <6>[ 2.687121] mmc0: Command Queue Engine enabled
10627 10:08:49.152182 <6>[ 2.688903] cros-ec-spi spi0.0: Chrome EC device registered
10628 10:08:49.158487 <6>[ 2.691863] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10629 10:08:49.161643 <6>[ 2.704977] mmcblk0: mmc0:0001 DA4128 116 GiB
10630 10:08:49.175745 <6>[ 2.714344] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10631 10:08:49.182175 <6>[ 2.718349] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10632 10:08:49.188696 <6>[ 2.725747] NET: Registered PF_PACKET protocol family
10633 10:08:49.191952 <6>[ 2.731019] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10634 10:08:49.198764 <6>[ 2.734996] 9pnet: Installing 9P2000 support
10635 10:08:49.202017 <6>[ 2.740713] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10636 10:08:49.208650 <5>[ 2.744674] Key type dns_resolver registered
10637 10:08:49.215217 <6>[ 2.750468] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10638 10:08:49.218291 <6>[ 2.754916] registered taskstats version 1
10639 10:08:49.221630 <5>[ 2.765276] Loading compiled-in X.509 certificates
10640 10:08:49.257423 <4>[ 2.792775] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10641 10:08:49.267172 <4>[ 2.803471] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10642 10:08:49.276869 <3>[ 2.816071] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10643 10:08:49.289363 <6>[ 2.831745] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10644 10:08:49.296286 <6>[ 2.838560] xhci-mtk 11200000.usb: xHCI Host Controller
10645 10:08:49.302763 <6>[ 2.844077] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10646 10:08:49.313427 <6>[ 2.852022] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10647 10:08:49.319604 <6>[ 2.861467] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10648 10:08:49.326279 <6>[ 2.867562] xhci-mtk 11200000.usb: xHCI Host Controller
10649 10:08:49.333106 <6>[ 2.873048] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10650 10:08:49.339319 <6>[ 2.880703] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10651 10:08:49.346554 <6>[ 2.888621] hub 1-0:1.0: USB hub found
10652 10:08:49.349597 <6>[ 2.892672] hub 1-0:1.0: 1 port detected
10653 10:08:49.359757 <6>[ 2.897036] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10654 10:08:49.362797 <6>[ 2.905912] hub 2-0:1.0: USB hub found
10655 10:08:49.365922 <6>[ 2.909959] hub 2-0:1.0: 1 port detected
10656 10:08:49.374739 <6>[ 2.917100] mtk-msdc 11f70000.mmc: Got CD GPIO
10657 10:08:49.396300 <6>[ 2.935073] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10658 10:08:49.402700 <6>[ 2.943198] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10659 10:08:49.412369 <4>[ 2.951201] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10660 10:08:49.422643 <6>[ 2.960896] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10661 10:08:49.429317 <6>[ 2.968983] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10662 10:08:49.439045 <6>[ 2.977036] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10663 10:08:49.445416 <6>[ 2.984953] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10664 10:08:49.452491 <6>[ 2.992814] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10665 10:08:49.461890 <6>[ 3.000640] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10666 10:08:49.472223 <6>[ 3.011186] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10667 10:08:49.482150 <6>[ 3.019554] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10668 10:08:49.488890 <6>[ 3.027941] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10669 10:08:49.498514 <6>[ 3.036289] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10670 10:08:49.505448 <6>[ 3.044661] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10671 10:08:49.515176 <6>[ 3.053005] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10672 10:08:49.522219 <6>[ 3.061376] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10673 10:08:49.532098 <6>[ 3.069721] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10674 10:08:49.538600 <6>[ 3.078084] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10675 10:08:49.548213 <6>[ 3.086428] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10676 10:08:49.554997 <6>[ 3.094771] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10677 10:08:49.564731 <6>[ 3.103116] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10678 10:08:49.571447 <6>[ 3.111459] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10679 10:08:49.581228 <6>[ 3.119809] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10680 10:08:49.588331 <6>[ 3.128153] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10681 10:08:49.595076 <6>[ 3.137029] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10682 10:08:49.602077 <6>[ 3.144444] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10683 10:08:49.609472 <6>[ 3.151493] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10684 10:08:49.619670 <6>[ 3.158608] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10685 10:08:49.626174 <6>[ 3.165894] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10686 10:08:49.636290 <6>[ 3.172819] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10687 10:08:49.642541 <6>[ 3.181960] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10688 10:08:49.652376 <6>[ 3.191131] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10689 10:08:49.662216 <6>[ 3.200544] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10690 10:08:49.672313 <6>[ 3.210022] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10691 10:08:49.682096 <6>[ 3.219497] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10692 10:08:49.692185 <6>[ 3.228624] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10693 10:08:49.698869 <6>[ 3.238099] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10694 10:08:49.708549 <6>[ 3.247230] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10695 10:08:49.718748 <6>[ 3.256534] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10696 10:08:49.728841 <6>[ 3.266721] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10697 10:08:49.739323 <6>[ 3.278520] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10698 10:08:49.786558 <6>[ 3.325516] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10699 10:08:49.940508 <6>[ 3.482891] hub 1-1:1.0: USB hub found
10700 10:08:49.943816 <6>[ 3.487361] hub 1-1:1.0: 4 ports detected
10701 10:08:50.066509 <6>[ 3.605516] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10702 10:08:50.091180 <6>[ 3.633060] hub 2-1:1.0: USB hub found
10703 10:08:50.094197 <6>[ 3.637439] hub 2-1:1.0: 3 ports detected
10704 10:08:50.266388 <6>[ 3.805515] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10705 10:08:50.399372 <6>[ 3.941521] hub 1-1.4:1.0: USB hub found
10706 10:08:50.402675 <6>[ 3.946154] hub 1-1.4:1.0: 2 ports detected
10707 10:08:50.478368 <6>[ 4.017547] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10708 10:08:50.698165 <6>[ 4.237488] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10709 10:08:50.882457 <6>[ 4.421487] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10710 10:09:02.023305 <6>[ 15.570071] ALSA device list:
10711 10:09:02.029515 <6>[ 15.573328] No soundcards found.
10712 10:09:02.042492 <6>[ 15.585752] Freeing unused kernel memory: 8384K
10713 10:09:02.045314 <6>[ 15.590683] Run /init as init process
10714 10:09:02.076246 <6>[ 15.619838] NET: Registered PF_INET6 protocol family
10715 10:09:02.082751 <6>[ 15.626448] Segment Routing with IPv6
10716 10:09:02.086153 <6>[ 15.630437] In-situ OAM (IOAM) with IPv6
10717 10:09:02.120762 <30>[ 15.644574] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10718 10:09:02.124265 <30>[ 15.668527] systemd[1]: Detected architecture arm64.
10719 10:09:02.127630
10720 10:09:02.130406 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10721 10:09:02.130508
10722 10:09:02.145820 <30>[ 15.689673] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10723 10:09:02.301801 <30>[ 15.842240] systemd[1]: Queued start job for default target Graphical Interface.
10724 10:09:02.351273 <30>[ 15.894664] systemd[1]: Created slice system-getty.slice.
10725 10:09:02.357645 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10726 10:09:02.374339 <30>[ 15.918181] systemd[1]: Created slice system-modprobe.slice.
10727 10:09:02.381061 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10728 10:09:02.398814 <30>[ 15.942669] systemd[1]: Created slice system-serial\x2dgetty.slice.
10729 10:09:02.408746 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10730 10:09:02.422577 <30>[ 15.966029] systemd[1]: Created slice User and Session Slice.
10731 10:09:02.429176 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10732 10:09:02.449426 <30>[ 15.990087] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10733 10:09:02.459634 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10734 10:09:02.477889 <30>[ 16.018039] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10735 10:09:02.484026 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10736 10:09:02.504551 <30>[ 16.041630] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10737 10:09:02.511185 <30>[ 16.053672] systemd[1]: Reached target Local Encrypted Volumes.
10738 10:09:02.517840 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10739 10:09:02.533953 <30>[ 16.077875] systemd[1]: Reached target Paths.
10740 10:09:02.537322 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10741 10:09:02.554114 <30>[ 16.097576] systemd[1]: Reached target Remote File Systems.
10742 10:09:02.560135 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10743 10:09:02.577918 <30>[ 16.121792] systemd[1]: Reached target Slices.
10744 10:09:02.584761 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10745 10:09:02.598101 <30>[ 16.141589] systemd[1]: Reached target Swap.
10746 10:09:02.601382 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10747 10:09:02.621363 <30>[ 16.161919] systemd[1]: Listening on initctl Compatibility Named Pipe.
10748 10:09:02.627939 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10749 10:09:02.634954 <30>[ 16.176664] systemd[1]: Listening on Journal Audit Socket.
10750 10:09:02.641380 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10751 10:09:02.654447 <30>[ 16.197830] systemd[1]: Listening on Journal Socket (/dev/log).
10752 10:09:02.660576 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10753 10:09:02.678735 <30>[ 16.222308] systemd[1]: Listening on Journal Socket.
10754 10:09:02.685551 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10755 10:09:02.701675 <30>[ 16.241946] systemd[1]: Listening on Network Service Netlink Socket.
10756 10:09:02.707996 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10757 10:09:02.722801 <30>[ 16.266292] systemd[1]: Listening on udev Control Socket.
10758 10:09:02.729360 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10759 10:09:02.746446 <30>[ 16.290230] systemd[1]: Listening on udev Kernel Socket.
10760 10:09:02.753155 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10761 10:09:02.790568 <30>[ 16.333921] systemd[1]: Mounting Huge Pages File System...
10762 10:09:02.796730 Mounting [0;1;39mHuge Pages File System[0m...
10763 10:09:02.812315 <30>[ 16.355800] systemd[1]: Mounting POSIX Message Queue File System...
10764 10:09:02.818674 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10765 10:09:02.835961 <30>[ 16.379713] systemd[1]: Mounting Kernel Debug File System...
10766 10:09:02.842426 Mounting [0;1;39mKernel Debug File System[0m...
10767 10:09:02.861117 <30>[ 16.401837] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10768 10:09:02.872439 <30>[ 16.412875] systemd[1]: Starting Create list of static device nodes for the current kernel...
10769 10:09:02.879285 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10770 10:09:02.896755 <30>[ 16.440151] systemd[1]: Starting Load Kernel Module configfs...
10771 10:09:02.903079 Starting [0;1;39mLoad Kernel Module configfs[0m...
10772 10:09:02.920219 <30>[ 16.464034] systemd[1]: Starting Load Kernel Module drm...
10773 10:09:02.926794 Starting [0;1;39mLoad Kernel Module drm[0m...
10774 10:09:02.945529 <30>[ 16.485695] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10775 10:09:02.955998 <30>[ 16.499606] systemd[1]: Starting Journal Service...
10776 10:09:02.959033 Starting [0;1;39mJournal Service[0m...
10777 10:09:02.976540 <30>[ 16.520098] systemd[1]: Starting Load Kernel Modules...
10778 10:09:02.983076 Starting [0;1;39mLoad Kernel Modules[0m...
10779 10:09:03.004142 <30>[ 16.544522] systemd[1]: Starting Remount Root and Kernel File Systems...
10780 10:09:03.010822 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10781 10:09:03.028300 <30>[ 16.572251] systemd[1]: Starting Coldplug All udev Devices...
10782 10:09:03.034895 Starting [0;1;39mColdplug All udev Devices[0m...
10783 10:09:03.052796 <30>[ 16.596374] systemd[1]: Mounted Huge Pages File System.
10784 10:09:03.059443 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10785 10:09:03.074408 <30>[ 16.618248] systemd[1]: Started Journal Service.
10786 10:09:03.080837 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10787 10:09:03.095915 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10788 10:09:03.114693 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10789 10:09:03.133958 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10790 10:09:03.151694 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10791 10:09:03.171401 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10792 10:09:03.186890 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10793 10:09:03.206961 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10794 10:09:03.221518 See 'systemctl status systemd-remount-fs.service' for details.
10795 10:09:03.271589 Mounting [0;1;39mKernel Configuration File System[0m...
10796 10:09:03.288758 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10797 10:09:03.305721 <46>[ 16.846453] systemd-journald[180]: Received client request to flush runtime journal.
10798 10:09:03.314589 Starting [0;1;39mLoad/Save Random Seed[0m...
10799 10:09:03.336497 Starting [0;1;39mApply Kernel Variables[0m...
10800 10:09:03.356347 Starting [0;1;39mCreate System Users[0m...
10801 10:09:03.378423 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10802 10:09:03.402331 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10803 10:09:03.415098 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10804 10:09:03.431168 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10805 10:09:03.450361 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10806 10:09:03.470410 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10807 10:09:03.525941 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10808 10:09:03.548216 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10809 10:09:03.562041 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10810 10:09:03.581933 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10811 10:09:03.622402 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10812 10:09:03.645994 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10813 10:09:03.663067 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10814 10:09:03.687078 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10815 10:09:03.727352 Starting [0;1;39mNetwork Service[0m...
10816 10:09:03.747971 Starting [0;1;39mNetwork Time Synchronization[0m...
10817 10:09:03.766943 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10818 10:09:03.806341 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10819 10:09:03.822798 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10820 10:09:03.898471 Starting [0;1;39mNetwork Name Resolution[0m...
10821 10:09:03.919174 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10822 10:09:03.948498 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10823 10:09:03.958387 <3>[ 17.498396] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10824 10:09:03.964707 <4>[ 17.499110] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10825 10:09:03.971430 <6>[ 17.504522] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10826 10:09:03.981314 <3>[ 17.506800] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10827 10:09:03.988061 <6>[ 17.507011] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10828 10:09:03.997986 <6>[ 17.507046] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10829 10:09:04.004405 <6>[ 17.507057] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10830 10:09:04.014174 <4>[ 17.521510] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10831 10:09:04.021109 <3>[ 17.529497] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10832 10:09:04.027821 <6>[ 17.537187] remoteproc remoteproc0: scp is available
10833 10:09:04.034176 <3>[ 17.552831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10834 10:09:04.041123 <6>[ 17.555347] remoteproc remoteproc0: powering up scp
10835 10:09:04.044298 <6>[ 17.557287] mc: Linux media interface: v0.10
10836 10:09:04.050412 <3>[ 17.561667] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10837 10:09:04.060327 <3>[ 17.561677] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10838 10:09:04.067107 <6>[ 17.569771] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10839 10:09:04.077296 <3>[ 17.574988] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10840 10:09:04.083739 <6>[ 17.583079] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10841 10:09:04.090017 <3>[ 17.588195] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10842 10:09:04.096695 <6>[ 17.606192] videodev: Linux video capture interface: v2.00
10843 10:09:04.103325 <3>[ 17.620087] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10844 10:09:04.109941 <6>[ 17.646772] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10845 10:09:04.120331 <6>[ 17.647376] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10846 10:09:04.126527 <6>[ 17.656268] usbcore: registered new interface driver r8152
10847 10:09:04.133583 <3>[ 17.657468] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10848 10:09:04.143133 <3>[ 17.657494] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10849 10:09:04.149513 <3>[ 17.657503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10850 10:09:04.159479 <3>[ 17.657594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10851 10:09:04.166486 <3>[ 17.657602] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10852 10:09:04.175973 <3>[ 17.657610] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10853 10:09:04.182679 <3>[ 17.657619] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10854 10:09:04.192645 <3>[ 17.657626] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10855 10:09:04.198929 <3>[ 17.657675] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10856 10:09:04.206188 <6>[ 17.659965] pci_bus 0000:00: root bus resource [bus 00-ff]
10857 10:09:04.212604 <6>[ 17.672029] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10858 10:09:04.219212 <6>[ 17.675014] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10859 10:09:04.229014 <6>[ 17.675022] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10860 10:09:04.239375 <4>[ 17.698344] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10861 10:09:04.242805 <4>[ 17.698344] Fallback method does not support PEC.
10862 10:09:04.249808 <6>[ 17.699832] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10863 10:09:04.259897 <6>[ 17.718119] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10864 10:09:04.266984 <6>[ 17.718124] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10865 10:09:04.273190 <6>[ 17.723905] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10866 10:09:04.283358 <6>[ 17.724793] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10867 10:09:04.293287 <6>[ 17.725294] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10868 10:09:04.300013 <6>[ 17.732034] remoteproc remoteproc0: remote processor scp is now up
10869 10:09:04.303482 <6>[ 17.741024] pci 0000:00:00.0: supports D1 D2
10870 10:09:04.313097 <3>[ 17.756405] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10871 10:09:04.319669 <6>[ 17.759643] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10872 10:09:04.326377 <6>[ 17.762127] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10873 10:09:04.333963 <6>[ 17.764140] usbcore: registered new interface driver cdc_ether
10874 10:09:04.337026 <6>[ 17.788552] Bluetooth: Core ver 2.22
10875 10:09:04.343868 <3>[ 17.796874] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 10:09:04.350479 <6>[ 17.799228] usbcore: registered new interface driver r8153_ecm
10877 10:09:04.357286 <6>[ 17.799810] NET: Registered PF_BLUETOOTH protocol family
10878 10:09:04.364134 <6>[ 17.799816] Bluetooth: HCI device and connection manager initialized
10879 10:09:04.367540 <6>[ 17.799833] Bluetooth: HCI socket layer initialized
10880 10:09:04.374536 <6>[ 17.799839] Bluetooth: L2CAP socket layer initialized
10881 10:09:04.377905 <6>[ 17.799854] Bluetooth: SCO socket layer initialized
10882 10:09:04.387835 <4>[ 17.800954] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10883 10:09:04.394758 <4>[ 17.800968] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10884 10:09:04.404513 <6>[ 17.807168] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10885 10:09:04.411155 <6>[ 17.808474] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10886 10:09:04.418001 <6>[ 17.817528] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10887 10:09:04.425218 <6>[ 17.822027] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10888 10:09:04.431783 <6>[ 17.822330] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10889 10:09:04.444580 <6>[ 17.833768] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10890 10:09:04.456044 <6>[ 17.837512] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10891 10:09:04.462186 <6>[ 17.841135] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10892 10:09:04.468585 <6>[ 17.841153] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10893 10:09:04.475765 <6>[ 17.848428] usbcore: registered new interface driver uvcvideo
10894 10:09:04.482145 <6>[ 17.848846] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10895 10:09:04.485604 <6>[ 17.849061] usbcore: registered new interface driver btusb
10896 10:09:04.499115 <4>[ 17.849805] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10897 10:09:04.502291 <3>[ 17.849821] Bluetooth: hci0: Failed to load firmware file (-2)
10898 10:09:04.509083 <3>[ 17.849826] Bluetooth: hci0: Failed to set up firmware (-2)
10899 10:09:04.519300 <4>[ 17.849833] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10900 10:09:04.522609 <6>[ 17.852285] pci 0000:01:00.0: supports D1 D2
10901 10:09:04.529262 <6>[ 17.853833] r8152 2-1.3:1.0 eth0: v1.12.13
10902 10:09:04.536062 <3>[ 17.864403] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 10:09:04.546578 <3>[ 17.865075] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
10904 10:09:04.553080 <6>[ 17.867569] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10905 10:09:04.559770 <6>[ 17.868060] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10906 10:09:04.566349 <6>[ 17.881419] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10907 10:09:04.573197 <3>[ 17.888127] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 10:09:04.583098 <3>[ 17.888935] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10909 10:09:04.589542 <6>[ 17.893768] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10910 10:09:04.599238 <3>[ 17.914014] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 10:09:04.609213 <6>[ 17.917128] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10912 10:09:04.615946 <3>[ 17.942724] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 10:09:04.625752 <6>[ 17.944681] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10914 10:09:04.632362 <3>[ 17.973416] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 10:09:04.642110 <6>[ 17.974919] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10916 10:09:04.649015 <3>[ 18.002233] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 10:09:04.658754 <6>[ 18.002622] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10918 10:09:04.661981 <6>[ 18.207017] pci 0000:00:00.0: PCI bridge to [bus 01]
10919 10:09:04.671934 <6>[ 18.207025] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10920 10:09:04.678812 <6>[ 18.207205] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10921 10:09:04.685068 [[0;32m OK [<6>[ 18.227503] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10922 10:09:04.691594 0m] Created slic<6>[ 18.234872] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10923 10:09:04.698201 e [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10924 10:09:04.712923 <5>[ 18.253603] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10925 10:09:04.719618 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10926 10:09:04.732527 <5>[ 18.273384] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10927 10:09:04.739204 <4>[ 18.280319] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10928 10:09:04.745520 <6>[ 18.289223] cfg80211: failed to load regulatory.db
10929 10:09:04.752026 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10930 10:09:04.792865 <6>[ 18.333450] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10931 10:09:04.799402 <6>[ 18.341001] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10932 10:09:04.805696 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10933 10:09:04.825348 [[0;32m OK [0m] Started [0;<6>[ 18.367920] mt7921e 0000:01:00.0: ASIC revision: 79610010
10934 10:09:04.828557 1;39mNetwork Name Resolution[0m.
10935 10:09:04.849804 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10936 10:09:04.931878 <4>[ 18.469346] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10937 10:09:05.036527 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10938 10:09:05.050751 <4>[ 18.587895] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10939 10:09:05.056945 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10940 10:09:05.074090 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10941 10:09:05.089684 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10942 10:09:05.109104 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10943 10:09:05.124830 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10944 10:09:05.137588 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10945 10:09:05.159168 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10946 10:09:05.172211 <4>[ 18.708544] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10947 10:09:05.178399 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10948 10:09:05.193635 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10949 10:09:05.213425 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10950 10:09:05.242208 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10951 10:09:05.268069 Starting [0;1;39mUser Login Management[0m...
10952 10:09:05.291406 <4>[ 18.828788] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10953 10:09:05.297911 Starting [0;1;39mPermit User Sessions[0m...
10954 10:09:05.314639 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10955 10:09:05.324017 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10956 10:09:05.340408 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10957 10:09:05.346861 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10958 10:09:05.366934 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10959 10:09:05.384174 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10960 10:09:05.414556 [[0;32m OK [<4>[ 18.952174] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10961 10:09:05.421121 0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10962 10:09:05.439030 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10963 10:09:05.457999 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10964 10:09:05.505935 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10965 10:09:05.536940 <4>[ 19.074144] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10966 10:09:05.543283 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10967 10:09:05.594057
10968 10:09:05.594236
10969 10:09:05.597500 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10970 10:09:05.597600
10971 10:09:05.600840 debian-bullseye-arm64 login: root (automatic login)
10972 10:09:05.600953
10973 10:09:05.601045
10974 10:09:05.617966 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023 aarch64
10975 10:09:05.618084
10976 10:09:05.624549 The programs included with the Debian GNU/Linux system are free software;
10977 10:09:05.630803 the exact distribution terms for each program are described in the
10978 10:09:05.634420 individual files in /usr/share/doc/*/copyright.
10979 10:09:05.634518
10980 10:09:05.641072 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10981 10:09:05.644224 permitted by applicable law.
10982 10:09:05.644574 Matched prompt #10: / #
10984 10:09:05.644777 Setting prompt string to ['/ #']
10985 10:09:05.644868 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10987 10:09:05.645059 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10988 10:09:05.645148 start: 2.2.6 expect-shell-connection (timeout 00:02:49) [common]
10989 10:09:05.645219 Setting prompt string to ['/ #']
10990 10:09:05.645278 Forcing a shell prompt, looking for ['/ #']
10992 10:09:05.695503 / # <4>[ 19.192108] mt7921e 0000:
10993 10:09:05.695699 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10994 10:09:05.695826 Waiting using forced prompt support (timeout 00:02:30)
10995 10:09:05.695957 01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10996 10:09:05.700212
10997 10:09:05.700489 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10998 10:09:05.700584 start: 2.2.7 export-device-env (timeout 00:02:49) [common]
10999 10:09:05.700679 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11000 10:09:05.700767 end: 2.2 depthcharge-retry (duration 00:02:11) [common]
11001 10:09:05.700850 end: 2 depthcharge-action (duration 00:02:11) [common]
11002 10:09:05.700935 start: 3 lava-test-retry (timeout 00:07:31) [common]
11003 10:09:05.701019 start: 3.1 lava-test-shell (timeout 00:07:31) [common]
11004 10:09:05.701089 Using namespace: common
11006 10:09:05.801414 / # #
11007 10:09:05.801604 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11008 10:09:05.801735 #<4>[ 19.311504] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11009 10:09:05.806973
11010 10:09:05.807239 Using /lava-10670703
11012 10:09:05.907581 / # export SHELL=/bin/sh
11013 10:09:05.907807 export SHELL=/bin/sh<4>[ 19.431995] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11014 10:09:05.913062
11016 10:09:06.013615 / # . /lava-10670703/environment
11017 10:09:06.013837 . /lava-10670703/environment<6>[ 19.548731] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11018 10:09:06.014876 <6>[ 19.556759] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11019 10:09:06.054957 <4>[ 19.556786] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11020 10:09:06.055089
11022 10:09:06.155631 / # /lava-10670703/bin/lava-test-runner /lava-10670703/0
11023 10:09:06.155790 Test shell timeout: 10s (minimum of the action and connection timeout)
11024 10:09:06.156126 /lava-10670703/bin/lava-test-runner /lava-10670703/0<3>[ 19.681601] mt7921e 0000:01:00.0: hardware init failed
11025 10:09:06.160398
11026 10:09:06.202988 + export TESTRUN_ID=0_v4l2-compliance-uvc
11027 10:09:06.203087 + cd /lava-10670703/0/tests/0_v4l2-compliance-uvc
11028 10:09:06.203156 + cat uuid
11029 10:09:06.203218 + UUID=10670703_1.5.2.3.1
11030 10:09:06.203279 + set +x
11031 10:09:06.203338 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 10670703_1.5.2.3.1>
11032 10:09:06.203396 + /usr/bin/v4l2-parser.sh -d uvcvideo
11033 10:09:06.203634 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 10670703_1.5.2.3.1
11034 10:09:06.203702 Starting test lava.0_v4l2-compliance-uvc (10670703_1.5.2.3.1)
11035 10:09:06.203782 Skipping test definition patterns.
11036 10:09:06.205812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11037 10:09:06.205898 device: /dev/video0
11038 10:09:06.206138 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11040 10:09:10.264911 <4>[ 23.809593] ------------[ cut here ]------------
11041 10:09:10.271549 <4>[ 23.814532] get_vaddr_frames() cannot follow VM_IO mapping
11042 10:09:10.281335 <4>[ 23.814672] WARNING: CPU: 1 PID: 310 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11043 10:09:10.331479 <4>[ 23.832774] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 btusb mtk_vcodec_enc mtk_vcodec_common btintel mtk_vpu btmtk btrtl v4l2_mem2mem cros_ec_rpmsg uvcvideo btbcm videobuf2_dma_contig videobuf2_vmalloc videobuf2_memops r8153_ecm bluetooth videobuf2_v4l2 cdc_ether usbnet videobuf2_common ecdh_generic crct10dif_ce ecc r8152 videodev sbs_battery elan_i2c mc rfkill hid_google_hammer pcie_mediatek_gen3 elants_i2c cros_ec_chardev hid_vivaldi_common mtk_scp cros_ec_typec mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11044 10:09:10.337546 <4>[ 23.882159] CPU: 1 PID: 310 Comm: v4l2-compliance Not tainted 6.1.31 #1
11045 10:09:10.344339 <4>[ 23.889024] Hardware name: Google Spherion (rev0 - 3) (DT)
11046 10:09:10.351032 <4>[ 23.894758] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11047 10:09:10.358040 <4>[ 23.901970] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11048 10:09:10.364500 <4>[ 23.908061] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11049 10:09:10.367397 <4>[ 23.914152] sp : ffff80000919b810
11050 10:09:10.374215 <4>[ 23.917716] x29: ffff80000919b810 x28: ffffabdc1dc67000 x27: ffffabdc1dc63238
11051 10:09:10.384018 <4>[ 23.925103] x26: 0000000000000000 x25: ffffabdc1dc674c0 x24: ffff6820cd140538
11052 10:09:10.390400 <4>[ 23.932490] x23: 00000000001c2000 x22: 0000000000000000 x21: 0000000000000000
11053 10:09:10.397106 <4>[ 23.939876] x20: 00000000fffffff2 x19: ffff6820c9c66000 x18: fffffffffffe9530
11054 10:09:10.404074 <4>[ 23.947263] x17: 0000000000000000 x16: ffffabdc7548bb60 x15: 0000000000000038
11055 10:09:10.413659 <4>[ 23.954650] x14: ffffabdc77bc34a8 x13: 0000000000000636 x12: 0000000000000212
11056 10:09:10.420419 <4>[ 23.962036] x11: fffffffffffe9530 x10: fffffffffffe94f8 x9 : 00000000fffff212
11057 10:09:10.427317 <4>[ 23.969423] x8 : ffffabdc77bc34a8 x7 : ffffabdc77c1b4a8 x6 : 00000000000018d8
11058 10:09:10.433633 <4>[ 23.976809] x5 : ffff6821fef27a18 x4 : 00000000fffff212 x3 : ffffbc4587a24000
11059 10:09:10.443503 <4>[ 23.984196] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff6820caa9ac40
11060 10:09:10.443587 <4>[ 23.991583] Call trace:
11061 10:09:10.450158 <4>[ 23.994280] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11062 10:09:10.456570 <4>[ 24.000025] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11063 10:09:10.463125 <4>[ 24.006026] vb2_vmalloc_get_userptr+0x60/0x1a0 [videobuf2_vmalloc]
11064 10:09:10.470039 <4>[ 24.012549] __prepare_userptr+0x280/0x410 [videobuf2_common]
11065 10:09:10.473549 <4>[ 24.018552] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11066 10:09:10.479772 <4>[ 24.024208] vb2_core_qbuf+0x3c8/0x5e0 [videobuf2_common]
11067 10:09:10.486497 <4>[ 24.029864] vb2_qbuf+0x90/0xf0 [videobuf2_v4l2]
11068 10:09:10.489862 <4>[ 24.034757] uvc_queue_buffer+0x3c/0x60 [uvcvideo]
11069 10:09:10.496245 <4>[ 24.039822] uvc_ioctl_qbuf+0x2c/0x40 [uvcvideo]
11070 10:09:10.499638 <4>[ 24.044699] v4l_qbuf+0x48/0x60 [videodev]
11071 10:09:10.506142 <4>[ 24.049118] __video_do_ioctl+0x184/0x3d0 [videodev]
11072 10:09:10.509435 <4>[ 24.054362] video_usercopy+0x358/0x680 [videodev]
11073 10:09:10.516162 <4>[ 24.059433] video_ioctl2+0x18/0x30 [videodev]
11074 10:09:10.519473 <4>[ 24.064157] v4l2_ioctl+0x40/0x60 [videodev]
11075 10:09:10.522656 <4>[ 24.068706] __arm64_sys_ioctl+0xa8/0xf0
11076 10:09:10.525971 <4>[ 24.072887] invoke_syscall+0x48/0x114
11077 10:09:10.532390 <4>[ 24.076893] el0_svc_common.constprop.0+0x44/0xec
11078 10:09:10.535877 <4>[ 24.081848] do_el0_svc+0x2c/0xd0
11079 10:09:10.539005 <4>[ 24.085414] el0_svc+0x2c/0x84
11080 10:09:10.542529 <4>[ 24.088725] el0t_64_sync_handler+0xb8/0xc0
11081 10:09:10.548814 <4>[ 24.093158] el0t_64_sync+0x18c/0x190
11082 10:09:10.552145 <4>[ 24.097072] ---[ end trace 0000000000000000 ]---
11083 10:09:12.972573 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11084 10:09:12.983402 v4l2-compliance SHA: 52926c1f2f03 2023-05-25 13:56:39
11085 10:09:12.990990
11086 10:09:13.003990 Compliance test for uvcvideo device /dev/video0:
11087 10:09:13.011112
11088 10:09:13.021825 Driver Info:
11089 10:09:13.032403 Driver name : uvcvideo
11090 10:09:13.046999 Card type : HD User Facing: HD User Facing
11091 10:09:13.057400 Bus info : usb-11200000.usb-1.4.1
11092 10:09:13.064844 Driver version : 6.1.31
11093 10:09:13.076087 Capabilities : 0x84a00001
11094 10:09:13.088884 Metadata Capture
11095 10:09:13.098725 Streaming
11096 10:09:13.109161 Extended Pix Format
11097 10:09:13.119715 Device Capabilities
11098 10:09:13.129781 Device Caps : 0x04200001
11099 10:09:13.142319 Streaming
11100 10:09:13.152818 Extended Pix Format
11101 10:09:13.163110 Media Driver Info:
11102 10:09:13.173360 Driver name : uvcvideo
11103 10:09:13.187120 Model : HD User Facing: HD User Facing
11104 10:09:13.195063 Serial : 200901010001
11105 10:09:13.208582 Bus info : usb-11200000.usb-1.4.1
11106 10:09:13.216193 Media version : 6.1.31
11107 10:09:13.229145 Hardware revision: 0x00009758 (38744)
11108 10:09:13.236496 Driver version : 6.1.31
11109 10:09:13.247239 Interface Info:
11110 10:09:13.263114 <LAVA_SIGNAL_TESTSET START Interface-Info>
11111 10:09:13.263200 ID : 0x03000002
11112 10:09:13.263449 Received signal: <TESTSET> START Interface-Info
11113 10:09:13.263523 Starting test_set Interface-Info
11114 10:09:13.272787 Type : V4L Video
11115 10:09:13.283573 Entity Info:
11116 10:09:13.290369 <LAVA_SIGNAL_TESTSET STOP>
11117 10:09:13.290626 Received signal: <TESTSET> STOP
11118 10:09:13.290701 Closing test_set Interface-Info
11119 10:09:13.299505 <LAVA_SIGNAL_TESTSET START Entity-Info>
11120 10:09:13.299796 Received signal: <TESTSET> START Entity-Info
11121 10:09:13.299875 Starting test_set Entity-Info
11122 10:09:13.302376 ID : 0x00000001 (1)
11123 10:09:13.312767 Name : HD User Facing: HD User Facing
11124 10:09:13.320436 Function : V4L2 I/O
11125 10:09:13.330788 Flags : default
11126 10:09:13.341467 Pad 0x01000007 : 0: Sink
11127 10:09:13.362660 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11128 10:09:13.362753
11129 10:09:13.374056 Required ioctls:
11130 10:09:13.380803 <LAVA_SIGNAL_TESTSET STOP>
11131 10:09:13.381065 Received signal: <TESTSET> STOP
11132 10:09:13.381139 Closing test_set Entity-Info
11133 10:09:13.391017 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11134 10:09:13.391353 Received signal: <TESTSET> START Required-ioctls
11135 10:09:13.391430 Starting test_set Required-ioctls
11136 10:09:13.394475 test MC information (see 'Media Driver Info' above): OK
11137 10:09:13.418655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11138 10:09:13.418962 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11140 10:09:13.421989 test VIDIOC_QUERYCAP: OK
11141 10:09:13.441101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11142 10:09:13.441395 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11144 10:09:13.443933 test invalid ioctls: OK
11145 10:09:13.463745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11146 10:09:13.463860
11147 10:09:13.464130 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11149 10:09:13.474037 Allow for multiple opens:
11150 10:09:13.480275 <LAVA_SIGNAL_TESTSET STOP>
11151 10:09:13.480589 Received signal: <TESTSET> STOP
11152 10:09:13.480749 Closing test_set Required-ioctls
11153 10:09:13.489071 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11154 10:09:13.489437 Received signal: <TESTSET> START Allow-for-multiple-opens
11155 10:09:13.489584 Starting test_set Allow-for-multiple-opens
11156 10:09:13.492573 test second /dev/video0 open: OK
11157 10:09:13.513391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11158 10:09:13.513693 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11160 10:09:13.516782 test VIDIOC_QUERYCAP: OK
11161 10:09:13.537165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11162 10:09:13.537428 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11164 10:09:13.540455 test VIDIOC_G/S_PRIORITY: OK
11165 10:09:13.559240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11166 10:09:13.559514 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11168 10:09:13.562753 test for unlimited opens: OK
11169 10:09:13.583443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11170 10:09:13.583576
11171 10:09:13.583814 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11173 10:09:13.593372 Debug ioctls:
11174 10:09:13.600445 <LAVA_SIGNAL_TESTSET STOP>
11175 10:09:13.600697 Received signal: <TESTSET> STOP
11176 10:09:13.600766 Closing test_set Allow-for-multiple-opens
11177 10:09:13.610219 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11178 10:09:13.610469 Received signal: <TESTSET> START Debug-ioctls
11179 10:09:13.610538 Starting test_set Debug-ioctls
11180 10:09:13.613635 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11181 10:09:13.635716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11182 10:09:13.635971 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11184 10:09:13.641967 test VIDIOC_LOG_STATUS: OK (Not Supported)
11185 10:09:13.659741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11186 10:09:13.659826
11187 10:09:13.660060 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11189 10:09:13.669747 Input ioctls:
11190 10:09:13.676550 <LAVA_SIGNAL_TESTSET STOP>
11191 10:09:13.676801 Received signal: <TESTSET> STOP
11192 10:09:13.676872 Closing test_set Debug-ioctls
11193 10:09:13.686940 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11194 10:09:13.687230 Received signal: <TESTSET> START Input-ioctls
11195 10:09:13.687300 Starting test_set Input-ioctls
11196 10:09:13.689823 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11197 10:09:13.714623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11198 10:09:13.714867 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11200 10:09:13.717400 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11201 10:09:13.735571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11202 10:09:13.735830 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11204 10:09:13.742169 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11205 10:09:13.760843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11206 10:09:13.761097 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11208 10:09:13.767063 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11209 10:09:13.786193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11210 10:09:13.786448 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11212 10:09:13.789719 test VIDIOC_G/S/ENUMINPUT: OK
11213 10:09:13.810543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11214 10:09:13.810796 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11216 10:09:13.814041 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11217 10:09:13.835012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11218 10:09:13.835263 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11220 10:09:13.838320 Inputs: 1 Audio Inputs: 0 Tuners: 0
11221 10:09:13.845239
11222 10:09:13.862216 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11223 10:09:13.883467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11224 10:09:13.883761 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11226 10:09:13.890315 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11227 10:09:13.909969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11228 10:09:13.910253 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11230 10:09:13.916373 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11231 10:09:13.934491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11232 10:09:13.934856 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11234 10:09:13.941395 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11235 10:09:13.958963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11236 10:09:13.959836 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11238 10:09:13.965539 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11239 10:09:13.984076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11240 10:09:13.984637
11241 10:09:13.985280 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11243 10:09:14.003318 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11244 10:09:14.024446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11245 10:09:14.025234 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11247 10:09:14.030598 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11248 10:09:14.051877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11249 10:09:14.052666 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11251 10:09:14.055124 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11252 10:09:14.074024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11253 10:09:14.074824 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11255 10:09:14.077492 test VIDIOC_G/S_EDID: OK (Not Supported)
11256 10:09:14.099181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11257 10:09:14.099729
11258 10:09:14.100551 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11260 10:09:14.109187 Control ioctls (Input 0):
11261 10:09:14.115765 <LAVA_SIGNAL_TESTSET STOP>
11262 10:09:14.116556 Received signal: <TESTSET> STOP
11263 10:09:14.116941 Closing test_set Input-ioctls
11264 10:09:14.125382 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11265 10:09:14.126404 Received signal: <TESTSET> START Control-ioctls-Input-0
11266 10:09:14.126937 Starting test_set Control-ioctls-Input-0
11267 10:09:14.128772 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11268 10:09:14.153746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11269 10:09:14.154274 test VIDIOC_QUERYCTRL: OK
11270 10:09:14.154925 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11272 10:09:14.174224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11273 10:09:14.175055 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11275 10:09:14.177466 test VIDIOC_G/S_CTRL: OK
11276 10:09:14.199518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11277 10:09:14.200425 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11279 10:09:14.202823 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11280 10:09:14.223560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11281 10:09:14.224381 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11283 10:09:14.230004 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11284 10:09:14.250983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11285 10:09:14.251815 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11287 10:09:14.254286 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11288 10:09:14.271811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11289 10:09:14.272595 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11291 10:09:14.274713 Standard Controls: 16 Private Controls: 0
11292 10:09:14.282011
11293 10:09:14.293517 Format ioctls (Input 0):
11294 10:09:14.300077 <LAVA_SIGNAL_TESTSET STOP>
11295 10:09:14.300894 Received signal: <TESTSET> STOP
11296 10:09:14.301295 Closing test_set Control-ioctls-Input-0
11297 10:09:14.308934 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11298 10:09:14.309737 Received signal: <TESTSET> START Format-ioctls-Input-0
11299 10:09:14.310202 Starting test_set Format-ioctls-Input-0
11300 10:09:14.312340 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11301 10:09:14.334919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11302 10:09:14.335698 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11304 10:09:14.337754 test VIDIOC_G/S_PARM: OK
11305 10:09:14.356441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11306 10:09:14.357238 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11308 10:09:14.359275 test VIDIOC_G_FBUF: OK (Not Supported)
11309 10:09:14.381409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11310 10:09:14.382217 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11312 10:09:14.385071 test VIDIOC_G_FMT: OK
11313 10:09:14.406739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11314 10:09:14.407565 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11316 10:09:14.409958 test VIDIOC_TRY_FMT: OK
11317 10:09:14.431709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11318 10:09:14.432439 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11320 10:09:14.438203 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11321 10:09:14.442809 test VIDIOC_S_FMT: OK
11322 10:09:14.467160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11323 10:09:14.467946 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11325 10:09:14.470478 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11326 10:09:14.492278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11327 10:09:14.493135 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11329 10:09:14.495179 test Cropping: OK (Not Supported)
11330 10:09:14.517935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11331 10:09:14.518754 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11333 10:09:14.521318 test Composing: OK (Not Supported)
11334 10:09:14.543327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11335 10:09:14.544162 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11337 10:09:14.546502 test Scaling: OK (Not Supported)
11338 10:09:14.566986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11339 10:09:14.567506
11340 10:09:14.568162 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11342 10:09:14.576696 Codec ioctls (Input 0):
11343 10:09:14.584280 <LAVA_SIGNAL_TESTSET STOP>
11344 10:09:14.585190 Received signal: <TESTSET> STOP
11345 10:09:14.585600 Closing test_set Format-ioctls-Input-0
11346 10:09:14.593344 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11347 10:09:14.594065 Received signal: <TESTSET> START Codec-ioctls-Input-0
11348 10:09:14.594587 Starting test_set Codec-ioctls-Input-0
11349 10:09:14.596962 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11350 10:09:14.618573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11351 10:09:14.619395 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11353 10:09:14.625022 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11354 10:09:14.643852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11355 10:09:14.644703 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11357 10:09:14.649787 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11358 10:09:14.667221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11359 10:09:14.667760
11360 10:09:14.668390 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11362 10:09:14.677654 Buffer ioctls (Input 0):
11363 10:09:14.684976 <LAVA_SIGNAL_TESTSET STOP>
11364 10:09:14.685767 Received signal: <TESTSET> STOP
11365 10:09:14.686152 Closing test_set Codec-ioctls-Input-0
11366 10:09:14.694822 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11367 10:09:14.695617 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11368 10:09:14.696012 Starting test_set Buffer-ioctls-Input-0
11369 10:09:14.697687 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11370 10:09:14.722858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11371 10:09:14.723411 test VIDIOC_EXPBUF: OK
11372 10:09:14.724036 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11374 10:09:14.743353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11375 10:09:14.744173 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11377 10:09:14.746751 test Requests: OK (Not Supported)
11378 10:09:14.767534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11379 10:09:14.768095
11380 10:09:14.768718 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11382 10:09:14.778334 Test input 0:
11383 10:09:14.788325
11384 10:09:14.798953 Streaming ioctls:
11385 10:09:14.805966 <LAVA_SIGNAL_TESTSET STOP>
11386 10:09:14.806761 Received signal: <TESTSET> STOP
11387 10:09:14.807250 Closing test_set Buffer-ioctls-Input-0
11388 10:09:14.815820 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11389 10:09:14.816619 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11390 10:09:14.817014 Starting test_set Streaming-ioctls_Test-input-0
11391 10:09:14.819215 test read/write: OK (Not Supported)
11392 10:09:14.839817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11393 10:09:14.840619 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11395 10:09:14.843161 test blocking wait: OK
11396 10:09:14.863709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11397 10:09:14.864545 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11399 10:09:14.873369 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11400 10:09:14.876501 test MMAP (no poll): FAIL
11401 10:09:14.897303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11402 10:09:14.898116 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11404 10:09:14.906775 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11405 10:09:14.910230 test MMAP (select): FAIL
11406 10:09:14.933046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11407 10:09:14.933840 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11409 10:09:14.942710 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11410 10:09:14.947859 test MMAP (epoll): FAIL
11411 10:09:14.971731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11412 10:09:14.972335
11413 10:09:14.972986 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11415 10:09:14.984968
11416 10:09:15.151684
11417 10:09:15.158514 test USERPTR (no poll): OK
11418 10:09:15.182797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11419 10:09:15.183280
11420 10:09:15.183964 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11422 10:09:15.196621
11423 10:09:15.362588
11424 10:09:15.369950 test USERPTR (select): OK
11425 10:09:15.394212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11426 10:09:15.394948 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11428 10:09:15.400861 test DMABUF: Cannot test, specify --expbuf-device
11429 10:09:15.404476
11430 10:09:15.421450 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11431 10:09:15.424932 <LAVA_TEST_RUNNER EXIT>
11432 10:09:15.425617 ok: lava_test_shell seems to have completed
11433 10:09:15.426111 Marking unfinished test run as failed
11435 10:09:15.431879 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11436 10:09:15.432581 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11437 10:09:15.433058 end: 3 lava-test-retry (duration 00:00:10) [common]
11438 10:09:15.433719 start: 4 finalize (timeout 00:07:21) [common]
11439 10:09:15.434417 start: 4.1 power-off (timeout 00:00:30) [common]
11440 10:09:15.435226 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11441 10:09:15.543732 >> Command sent successfully.
11442 10:09:15.546847 Returned 0 in 0 seconds
11443 10:09:15.647598 end: 4.1 power-off (duration 00:00:00) [common]
11445 10:09:15.649261 start: 4.2 read-feedback (timeout 00:07:21) [common]
11446 10:09:15.650819 Listened to connection for namespace 'common' for up to 1s
11447 10:09:16.651074 Finalising connection for namespace 'common'
11448 10:09:16.651692 Disconnecting from shell: Finalise
11449 10:09:16.652357 / #
11450 10:09:16.753358 end: 4.2 read-feedback (duration 00:00:01) [common]
11451 10:09:16.753732 end: 4 finalize (duration 00:00:01) [common]
11452 10:09:16.754045 Cleaning after the job
11453 10:09:16.754307 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670703/tftp-deploy-huopdwre/ramdisk
11454 10:09:16.764922 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670703/tftp-deploy-huopdwre/kernel
11455 10:09:16.786642 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670703/tftp-deploy-huopdwre/dtb
11456 10:09:16.786960 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670703/tftp-deploy-huopdwre/modules
11457 10:09:16.794273 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10670703
11458 10:09:16.850893 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10670703
11459 10:09:16.851068 Job finished correctly